Display device

Abstract

To provide a metal oxide film including a crystal part and also to provide the metal oxide film having high stability of physical properties.SOLUTION: Provided is a metal oxide film having a new structure in which a plurality of spots circumferentially arranged together with a halo pattern showing an amorphous state are observed in an electron diffraction pattern using nanobeam electron diffraction. Each of the plurality of spots is unlike a spot having regularity indicating a crystalline state oriented in a particular plane and does not have directionality. Moreover, in the metal oxide film, the plurality of spots is not observed in a selected visual field electron diffraction pattern.SELECTED DRAWING: Figure 1

Description

Technical Field

[0001] One aspect of the present invention relates to, for example, semiconductor devices, display devices, light-emitting devices, their driving methods, and also to their manufacturing methods. In particular, one aspect of the present invention relates to a metal oxide film and a metal oxide film forming method. It also relates to a semiconductor device using the metal oxide film.

[0002] Note that in this specification and the like, a semiconductor device refers to all devices that can function by utilizing semiconductor characteristics, and electro-optical devices, semiconductor circuits, and electronic devices are all semiconductor devices.

Background Art

[0003] Techniques for constructing transistors using semiconductor films formed on substrates having insulating surfaces have attracted attention. Such transistors are widely applied to electronic devices such as integrated circuits (ICs) and image display devices (simply referred to as display devices). Silicon-based semiconductor materials are widely known as semiconductor films applicable to transistors, but metal oxides (oxide semiconductors) exhibiting semiconductor characteristics are attracting attention as other materials. For example, as an oxide semiconductor, a technique for fabricating a transistor using an amorphous oxide containing In, Zn, Ga, Sn, etc. is disclosed in Patent Document 1.

[0004] For example, as an oxide semiconductor, a technique for fabricating a transistor using an amorphous oxide containing In, Zn, Ga, Sn, etc. is disclosed in Patent Document 1.

Prior Art Documents

Patent Documents

[0005]

Patent Document 1

Summary of the Invention

Problems to be Solved by the Invention

[0006] One aspect of the present invention aims to provide a metal oxide film including a crystalline portion.

[0007] Or, one aspect of the present invention aims to provide a metal oxide film having high physical property stability. as one of the problems.

[0008] Also, one aspect of the present invention aims to provide a highly reliable semiconductor device to which the above-described metal oxide film or the like is applied. as a problem.

[0009] Or, one aspect of the present invention aims to provide a novel semiconductor device. Note that the description of these problems does not prevent the existence of other problems. Note that one aspect of the present invention does not necessarily need to solve all of these problems. Note that other problems will be apparent from the description in the specification, drawings, claims, etc., and it is possible to extract these other problems from the description in the specification, drawings, claims, etc. from the description in the specification, drawings, claims, etc. from the description in the specification, drawings, claims, etc. from the description in the specification, drawings, claims, etc. from the description in the specification, drawings, claims, etc.

Means for Solving the Problems

[0010] One aspect of the disclosed invention is a metal oxide film including extremely fine crystal portions to such an extent that periodicity is not observed in the atomic arrangement macroscopically or long-range order is not observed macroscopically. The metal oxide film of one aspect of the present invention shows a halo pattern indicating an amorphous state in the restricted field electron beam diffraction pattern of the film plane, and in the nano-beam electron beam diffraction pattern of the cross section, the halo pattern is not observed, and a region including spots having no directionality, different from spots having regularity indicating crystals oriented on a specific plane, is observed. More specifically, for example, it is a metal oxide film having the following configuration. to such an extent that periodicity is not observed in the atomic arrangement macroscopically or long-range order is not observed macroscopically. In the restricted field electron beam diffraction pattern of the film plane, a halo pattern indicating an amorphous state is observed, and in the nano-beam electron beam diffraction pattern of the cross section, the halo pattern is not observed, and a region including spots having no directionality, different from spots having regularity indicating crystals oriented on a specific plane, is observed. In the restricted field electron beam diffraction pattern of the film plane, a halo pattern indicating an amorphous state is observed, and in the nano-beam electron beam diffraction pattern of the cross section, the halo pattern is not observed, and a region including spots having no directionality, different from spots having regularity indicating crystals oriented on a specific plane, is observed. In the restricted field electron beam diffraction pattern of the film plane, a halo pattern indicating an amorphous state is observed, and in the nano-beam electron beam diffraction pattern of the cross section, the halo pattern is not observed, and a region including spots having no directionality, different from spots having regularity indicating crystals oriented on a specific plane, is observed. In the restricted field electron beam diffraction pattern of the film plane, a halo pattern indicating an amorphous state is observed, and in the nano-beam electron beam diffraction pattern of the cross section, the halo pattern is not observed, and a region including spots having no directionality, different from spots having regularity indicating crystals oriented on a specific plane, is observed. More specifically, for example, it is a metal oxide film having the following configuration.

[0011] One aspect of the present invention is a metal oxide film characterized by including a region where a plurality of spots distributed circumferentially are observed in a cross-sectional nano-beam electron diffraction pattern. The metal oxide film includes a region where a plurality of spots distributed circumferentially are observed in a cross-sectional nano-beam electron diffraction pattern.

[0012] Another aspect of the present invention is a metal oxide film characterized by including a region where a plurality of spots distributed circumferentially are observed in a cross-sectional nano-beam electron diffraction pattern and a halo pattern is observed in a planar selected area electron diffraction pattern. In the above, it is preferable that the measurement range in the selected area electron diffraction pattern is 300 nmφ or more. The metal oxide film includes a region where a plurality of spots distributed circumferentially are observed in a cross-sectional nano-beam electron diffraction pattern and a halo pattern is observed in a planar selected area electron diffraction pattern.

[0013] In the above, it is preferable that the measurement range of the nano-beam electron diffraction is 5 nmφ or more and 10 nmφ or less. By irradiating an electron beam focused to a beam diameter of 1 nmφ, a nano-beam electron diffraction pattern with a measurement range of 5 nmφ or more and 10 nmφ or less can be obtained. The above nano-beam electron diffraction pattern is preferably a nano-beam electron diffraction pattern of a cross-section of a sample thinned to a thickness greater than 10 nm and 50 nm or less.

[0014] In the above, the metal oxide film preferably includes a crystalline portion, and the size of the crystalline portion is preferably 10 nm or less. Alternatively, it is preferably 1 nm or more and 10 nm or less. Another aspect of the present invention is a metal oxide film including a crystalline portion, wherein the crystalline portion is obtained by subjecting the metal oxide film to nano-beam electron diffraction with a measurement range of 5 nmφ or more and 10 nmφ or less. The metal oxide film includes a crystalline portion, and the size of the crystalline portion is preferably 10 nm or less. Alternatively, it is preferably 1 nm or more and 10 nm or less. The above nano-beam electron diffraction pattern is preferably a nano-beam electron diffraction pattern of a cross-section of a sample thinned to a thickness greater than 10 nm and 50 nm or less.

[0015] In the above, the metal oxide film preferably includes a crystalline portion, and the size of the crystalline portion is preferably 10 nm or less. Alternatively, it is preferably 1 nm or more and 10 nm or less. Another aspect of the present invention is a metal oxide film including a crystalline portion, wherein the crystalline portion is obtained by subjecting the metal oxide film to nano-beam electron diffraction with a measurement range of 5 nmφ or more and 10 nmφ or less.

[0016] In the above, the metal oxide film preferably includes a crystalline portion, and the size of the crystalline portion is preferably 10 nm or less. Alternatively, it is preferably 1 nm or more and 10 nm or less. Another aspect of the present invention is a metal oxide film including a crystalline portion, wherein the crystalline portion is obtained by subjecting the metal oxide film to nano-beam electron diffraction with a measurement range of 5 nmφ or more and 10 nmφ or less.

[0017] Another aspect of the present invention is a metal oxide film including a crystalline portion, wherein the crystalline portion is obtained by subjecting the metal oxide film to nano-beam electron diffraction with a measurement range of 5 nmφ or more and 10 nmφ or less. nmφ or more and 10 nmφ or less, and in the nano-beam electron diffraction, the metal oxide film is thinned to 10 n In the diffraction pattern of a cross-section thinned to a thickness greater than m and not exceeding 50 nm, a plurality of spots are distributed circumferentially and are observed. In the diffraction pattern of a cross-section thinned to a thickness of 10 nm or less of the metal oxide film, a region is observed where spots having regularity indicating crystals oriented on a specific plane are observed. The metal oxide film is characterized by including such a region.

[0018] Further, in any one of the above metal oxide films, the metal oxide film is preferably composed of at least indium, gallium, or zinc.

[0019] Another aspect of the present invention is to perform a sputtering method using an oxide target at room temperature and in an atmosphere containing oxygen, so that in the cross-sectional direction nano-beam electron diffraction pattern, a metal oxide film is formed that includes a region where a plurality of spots distributed circumferentially are observed. This is a method for forming a metal oxide film.

[0020] Further, in the method for forming the above metal oxide film, it is preferable to form the film in an atmosphere with an oxygen partial pressure of 33% or more.

Advantages of the Invention

[0021] According to one aspect of the present invention, a metal oxide film including a crystal part can be provided.

[0022] Also, according to one aspect of the present invention, a metal oxide film with high physical property stability can be provided. Further, by applying the metal oxide film to a semiconductor device, a highly reliable semiconductor device can be provided.

Brief Description of the Drawings

[0023]

Figure 1

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Mode for Carrying Out the Invention

[0024] Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings. However, the present invention is not limited to the following description, and it will be easily understood by those skilled in the art that its form and aspect can be variously changed. Therefore, the present invention is not interpreted as being limited to the description of the embodiments shown below.

[0025] (Embodiment 1) In the present embodiment, a metal oxide film of one aspect of the present invention will be described with reference to FIGS. 1 to 7 and FIGS. 15 to 21.

[0026] <Crystal part of the metal oxide film> The metal oxide film of the present embodiment is a metal oxide film containing extremely fine crystal parts to such an extent that periodicity is not seen in the atomic arrangement macroscopically, or long-range order is not seen macroscopically. Therefore, depending on the electron diffraction in a measurement range larger (wider) than the crystal parts contained in the metal oxide film of the present embodiment, spots having regularity indicating a crystalline state may not be obtained.

[0027] ≪Cross-sectional TEM image and ultramicro electron diffraction pattern≫ ​​​​Figure 1(A) shows a cross-sectional TEM (Transmission Electron Microscopy) image of the metal oxide film of the present embodiment. Also, as shown in Figure 1(B), the electron diffraction pattern measured using nano-beam electron diffraction at point 1 in Figure 1(A) is shown in Figure 1(B), the electron diffraction pattern measured using nano-beam electron diffraction at point 2 in Figure 1(A) is shown in Figure 1(C), and the electron diffraction pattern measured using nano-beam electron diffraction at point 3 in Figure 1(A) is shown in Figure 1(D). lectron Microscopy) image is shown. Also, as shown in Figure 1( B), the electron diffraction pattern measured using nano-beam electron diffraction at point 1 in Figure 1(A) is shown, the electron diffraction pattern measured using nano-beam electron diffraction at point 2 in Figure 1(A) is shown in Figure 1(C), and the electron diffraction pattern measured using nano-beam electron diffraction at point 3 in Figure 1(A) is shown in Figure 1(D). As an example of the metal oxide film, a sample in which an In-Ga-Zn-based oxide film was formed on a quartz glass substrate with a film thickness of 50 nm was used. The film formation conditions of the metal oxide film were as follows: using an oxide target with In:Ga:Zn = 1:1: 1 (atomic ratio), in an oxygen atmosphere (flow rate 45 sccm),

[0028] pressure 0.4 Pa, DC power supply 0.5 kW, and the substrate temperature was room temperature. Then, the formed metal oxide film was thinned to a thickness of about 50 nm (for example, 40 nm ± 10 nm), and a cross-sectional TEM image and a nano-beam electron diffraction pattern were obtained. nm was used. The film formation conditions of the metal oxide film were as follows: using an oxide target with In:Ga:Zn = 1:1: 1 (atomic ratio), in an oxygen atmosphere (flow rate 45 sccm), pressure 0.4 Pa, DC power supply 0.5 kW, and the substrate temperature was room temperature. Then, the formed metal oxide film was thinned to a thickness of about 50 nm (for example, 40 nm ± 10 nm), and a cross-sectional TEM image and a nano-beam electron diffraction pattern were obtained. pressure 0.4 Pa, DC power supply 0.5 kW, and the substrate temperature was room temperature. Then, the formed metal oxide film was thinned to a thickness of about 50 nm (for example, 40 nm ± 10 nm), and a cross-sectional TEM image and a nano-beam electron diffraction pattern were obtained. pressure 0.4 Pa, DC power supply 0.5 kW, and the substrate temperature was room temperature. Then, the formed metal oxide film was thinned to a thickness of about 50 nm (for example, 40 nm ± 10 nm), and a cross-sectional TEM image and a nano-beam electron diffraction pattern were obtained.

[0029] The cross-sectional observation of the metal oxide film was performed using a transmission electron microscope (Hitachi High-Technologies Corporation's "H-900 0NAR") with an acceleration voltage of 300 kV and a magnification of 2 million times. The nano-beam electron diffraction was performed using a transmission electron microscope (Hitachi High-Technologies Corporation's "HF-2000") [[ID=and the acceleration voltage was 200 kV and the beam diameter was about 1 nmφ. The measurement range in nano-beam electron diffraction is 5 nmφ or more and 10 nmφ or less. electron diffraction was performed using a transmission electron microscope (Hitachi High-Technologies Corporation's "HF-2000") with an acceleration voltage of 200 kV and a beam diameter of about 1 nmφ. The measurement range in nano-beam electron diffraction is 5 nmφ or more and 10 nmφ or less.

[0030] [[ID=As shown in Figure 1(B), the metal oxide film of the present embodiment has a nano-beam electron diffraction pattern In this image, multiple spots (bright points) arranged in a circular pattern are observed. In the metal oxide film of the embodiment, a plurality of spots distributed circumferentially are observed. It can also be said that the multiple spots distributed circumferentially form multiple concentric circles.

[0031] In addition, the vicinity of the interface with the quartz glass substrate (Fig. 1(D)) and the center of the metal oxide film in the thickness direction are In Fig. 1(C) of the part, multiple spots distributed circumferentially were observed, similar to Fig. 1(B). In FIG. 1(C), the radius of the first circle (the distance from the main spot) is 3.8 The interplanar spacing was 0.203 nm to 0.2 It is 57nm.

[0032] The nanobeam electron diffraction pattern in Figure 1 shows a halo pattern that indicates an amorphous state. Therefore, the metal oxide film of this embodiment has a crystalline portion. However, the nanobeam electron diffraction pattern in Figure 1 shows that a specific The spots are not regular, which indicates crystals oriented in the plane, but random spots. From the observation, it can be seen that the metal oxide film of this embodiment has irregular plane orientation and large It is presumed that the film is a mixture of multiple crystal parts with different sizes.

[0033] FIG. 5 shows a partially enlarged view of the cross-sectional TEM image shown in FIG. 1(A). Cross-sectional TEM image of the area around point 1 in (A) (metal oxide film surface) observed at 8 million magnifications In addition, Fig. 5(B) shows the vicinity of point 2 in Fig. 1(A) (in the thickness direction of the metal oxide film). This is a cross-sectional TEM image of the sample (center) observed at 8 million times magnification.

[0034] In addition, from the cross-sectional TEM image shown in Fig. 5, the crystal structure of the metal oxide film of this embodiment is not clearly identifiable.

[0035] ≪Planar TEM Image and Selected Area Electron Diffraction Pattern≫ Next, Fig. 2(A) shows a planar TEM image of the metal oxide film of this embodiment. Also, Fig. 2( B) shows the electron beam diffraction pattern measured using selected area electron diffraction for the area circled in Fig. 2(A).

[0036] As an example of the metal oxide film, a sample of an In-Ga-Zn-based oxide film formed on a quartz glass substrate with a film thickness of 30 nm was used. The film formation conditions of the metal oxide film were as follows: an oxide target with In:Ga:Zn = 1:1: 1 (atomic ratio) was used, in an oxygen atmosphere (flow rate 45 sccm), at a pressure of 0.4 Pa, a DC power supply of 0.5 kW, and the substrate temperature was room temperature. Then, the formed sample was thinned so as to leave the metal oxide film, and a planar TEM image and a selected area electron diffraction pa ttern were obtained.

[0037] The images in Fig. 2 were obtained using a transmission electron microscope ("H-9000NAR " manufactured by Hitachi High-Technologies) at an acceleration voltage of 300 kV. Fig. 2(A) was obtained by planar observation of the metal oxide film at a magnification of 500,000 times. Also, Fig. 2(B) shows the result of measurement by selected area electron diffraction within the circle shown in Fig. 2(A). The pattern in Fig. 2(B) was obtained by performing electron beam diffraction with the selected area region being 300 nmφ. Considering the spread of the electron beam (about several nm), the measurement range is 300 nmφ or more. As shown in Fig. 2(B), in the metal oxide film of this embodiment, the measurement by selected area electron diffraction is more than that by micro electron diffraction.

[0038] As shown in Fig. 2(B), in the metal oxide film of this embodiment, the measurement by selected area electron diffraction is more In the electron diffraction pattern using a wide-range restricted-view electron beam diffraction, multiple spots observed by nano-beam electron diffraction are not seen, and a halo pattern is observed. Therefore, the metal oxide film in this embodiment has a nano-scale crystalline structure that does not have periodicity in atomic arrangement macroscopically (for example, when the measurement range is 300 nmφ or more), or does not have long-range order macroscopically. It can be said that it is a metal oxide film containing extremely fine crystal parts. That is, it can be said that it is a metal oxide film containing extremely fine crystal parts. In the form of the metal oxide film of this embodiment, macroscopically (for example, when the measurement range is 300 nmφ or more), the atomic arrangement does not have periodicity, or macroscopically, there is no long-range order, and it can be said that it is a metal oxide film containing extremely fine crystal parts.

[0039] <<Conceptual diagram of electron diffraction intensity distribution>> Fig. 3 conceptually shows the distribution of diffraction intensities in the electron diffraction patterns of Figs. 1 and 2. Fig. 3(A) is a conceptual diagram of the distribution of diffraction intensities in the nano-beam electron diffraction pattern shown in Figs. 1(B) to 1(D). Also, Fig. 3(B) is a conceptual diagram of the distribution of diffraction intensities in the restricted-view electron diffraction pattern shown in Fig. 2(B). Fig. 3(C) is a conceptual diagram of the distribution of diffraction intensities in the electron diffraction pattern of an ideal polycrystalline structure. In Fig. 3, the vertical axis represents the electron diffraction intensity (in arbitrary units), and the horizontal axis represents the distance from the main spot. In the ideal polycrystalline structure shown in Fig. 3(C), peaks are observed at specific distances from the main spot according to the interplanar spacing (d-value) of the planes to which the crystal parts are oriented. In this case, in the electron diffraction pattern, a ring with a small line width is clearly observed at a specific distance from the main spot. In the ideal polycrystalline structure shown in Fig. 3(C), peaks are observed at specific distances from the main spot according to the interplanar spacing (d-value) of the planes to which the crystal parts are oriented. In this case, in the electron diffraction pattern, a ring with a small line width is clearly observed at a specific distance from the main spot.

[0040] In Fig. 3, the vertical axis represents the electron diffraction intensity (in arbitrary units), and the horizontal axis represents the distance from the main spot. shows.

[0041] In the ideal polycrystalline structure shown in Fig. 3(C), peaks are observed at specific distances from the main spot according to the interplanar spacing (d-value) of the planes to which the crystal parts are oriented. In this case, in the electron diffraction pattern, a ring with a small line width is clearly observed at a specific distance from the main spot. In this case, in the electron diffraction pattern, a ring with a small line width is clearly observed at a specific distance from the main spot. is observed.

[0042] On the other hand, as shown in Fig. 1, the circumferential region formed by the multiple spots observed in the nano-beam electron diffraction pattern of the metal oxide film of this embodiment has a relatively large width. The circumferential region formed by the multiple spots observed in the nano-beam electron diffraction pattern of the metal oxide film of this embodiment has a relatively large width. Therefore, as shown in Fig. 3(A), the electron diffraction intensity shows a discrete intensity distribution with a plurality of peak bands (peak bands) distributed in a band shape. Also, in the nano-beam electron diffraction pattern, since there are a small number of spots between concentric regions, as shown in Fig. 3(A), it can be seen that there is a diffraction peak between the two peak bands.

[0043] On the other hand, as shown in Fig. 3(B), the electron diffraction intensity distribution in the selected area electron diffraction pattern of the metal oxide film of the present embodiment shows a continuous intensity distribution. Since Fig. 3(B) can be approximated to the result of observing the electron diffraction intensity distribution shown in Fig. 3(A) over a wide range, it can be considered that the peak bands shown in Fig. 3(A) are integrated to obtain a continuous intensity distribution. As shown in Figs. 3(A) to 3(C), the metal oxide film of the present embodiment is a film in which the plane orientation is irregular and a plurality of crystal parts of different sizes are mixed, and the crystal parts are extremely fine to the extent that spots are not observed in the selected area electron diffraction pattern. This is suggested. In the nano-beam electron diffraction pattern, a metal oxide film in which a plurality of spots are observed as shown in Fig. 1 is thinned to a thickness of about 50 nm. Also, since the beam diameter of the electron beam is converged to 1 nmφ, the measurement range is 5 nm or more and 10 nm or less. Therefore, the size of the crystal parts included in the metal oxide film of the present embodiment is presumed to be at least 50 nm or less, for example, 10 nm or less, or 5 nm or less.

[0044] As shown in Figs. 3(A) to 3(C), the metal oxide film of the present embodiment is a film in which the plane orientation is irregular and a plurality of crystal parts of different sizes are mixed, and the crystal parts are extremely fine to the extent that spots are not observed in the selected area electron diffraction pattern. This is suggested. In the nano-beam electron diffraction pattern, a metal oxide film in which a plurality of spots are observed as shown in Fig. 1 is thinned to a thickness of about 50 nm. Also, since the beam diameter of the electron beam is converged to 1 nmφ, the measurement range is 5 nm or more and 10 nm or less. Therefore, the size of the crystal parts included in the metal oxide film of the present embodiment is presumed to be at least 50 nm or less, for example, 10 nm or less, or 5 nm or less. This is suggested.

[0045] In the nano-beam electron diffraction pattern, a metal oxide film in which a plurality of spots are observed as shown in Fig. 1 is thinned to a thickness of about 50 nm. Also, since the beam diameter of the electron beam is converged to 1 nmφ, the measurement range is 5 nm or more and 10 nm or less. Therefore, the size of the crystal parts included in the metal oxide film of the present embodiment is presumed to be at least 50 nm or less, for example, 10 nm or less, or 5 nm or less. In the nano-beam electron diffraction pattern, a metal oxide film in which a plurality of spots are observed as shown in Fig. 1 is thinned to a thickness of about 50 nm. Also, since the beam diameter of the electron beam is converged to 1 nmφ, the measurement range is 5 nm or more and 10 nm or less. Therefore, the size of the crystal parts included in the metal oxide film of the present embodiment is presumed to be at least 50 nm or less, for example, 10 nm or less, or 5 nm or less. Since the beam diameter of the electron beam is converged to 1 nmφ, the measurement range is 5 nm or more and 10 nm or less. Therefore, the size of the crystal parts included in the metal oxide film of the present embodiment is presumed to be at least 50 nm or less, for example, 10 nm or less, or 5 nm or less. Therefore, the size of the crystal parts included in the metal oxide film of the present embodiment is presumed to be at least 50 nm or less, for example, 10 nm or less, or 5 nm or less. For example, it is presumed to be 10 nm or less, or 5 nm or less.

[0046] << Nano-beam electron diffraction pattern of an extremely thin sample >> The size of the crystal portion contained in the metal oxide film of this embodiment is 10 nm or less, or 5 nm or less. In this case, the metal oxide film is sliced to a thickness of about 50 nm, and the depth direction is measured. Since the measurement range is larger than the size of the crystal part, multiple crystal parts are included within the measurement range. Therefore, the metal oxide film is sliced to a thickness of 10 nm or less, and its cross section is nano-sized. The crystals were observed by electron diffraction.

[0047] The sample preparation method is as follows: An In-Ga-Zn oxide film was formed on a quartz glass substrate to a thickness of 5 mm. The film was formed at a thickness of 0 nm. The film formation conditions were In:Ga:Zn=1:1:1 (atomic ratio). Using an oxide target, under an oxygen atmosphere (flow rate 45sccm), pressure 0.4Pa, DC The DC power supply was 0.5 kW, and the substrate temperature was room temperature. After the metal oxide film was formed, A first heat treatment at 0°C under nitrogen atmosphere for 1 hour, and a second heat treatment at 450°C under nitrogen and oxygen atmosphere for 1 hour. A second heat treatment was carried out for 1 hour under reduced pressure.

[0048] After the second heat treatment, the metal oxide film was thinned by ion milling using Ar ions. First, a quartz glass substrate with a metal oxide film formed on it was thinned. After bonding the substrate, it was cut and polished to a thickness of approximately 50 μm. Thereafter, as shown in FIG. 16, the quartz glass substrate 200 on which the metal oxide film 204 is provided and The dummy substrate 202 is irradiated with argon ions from a low angle (approximately 3°) to form ions. The region 21 is thinned to a thickness of about 50 nm (40 nm ± 10 nm). 0a and a thinned region 210b having a thickness of 10 nm or less, for example, 5 to 10 nm. The cross sections of each were observed.

[0049] FIG. 15(A) shows a cross section of a sample sliced to a thickness of about 50 nm, which corresponds to the region 210a. The cross section shown in Figure 15(A) was measured by nanobeam electron diffraction. The electron beam diffraction patterns are shown in Figures 15(B) to 15(E). FIG. 15(C) shows an electron beam diffraction pattern using an electron beam focused to a diameter of 1 nm. This is an electron beam diffraction pattern using an electron beam focused to a beam diameter of 10 nm. D) is an electron beam diffraction pattern using an electron beam focused to a beam diameter of 20 nmφ. FIG. 15(E) shows electron beam diffraction using an electron beam converged to a beam diameter of 30 nm. It's a pattern.

[0050] As shown in FIG. 15(B), the metal oxide film after the heat treatment also has a circumferential distribution similar to that shown in FIG. In addition, from Fig. 15(C) to Fig. 15(E), it is clear that the When the beam diameter of the sagittal beam is increased to widen the measurement range, the multiple spots gradually broaden. It is confirmed that this will occur.

[0051] 17(A) to 17(D) show a thin film having a thickness of 10 nm or less, which corresponds to the region 210b. Four arbitrary points on the fragmented sample were measured using an electron beam focused to a beam diameter of 1 nmφ. Nanobeam electron diffraction patterns are shown.

[0052] In Fig. 17(A) and Fig. 17(B), regular spots showing crystals oriented in a specific plane are shown. From this, it can be seen that the metal oxide film according to this embodiment certainly has crystalline parts. On the other hand, in Fig. 17(C) and Fig. 17(D), the complex distribution of Several spots (bright points) are observed.

[0053] As described above, the size of the crystal part included in the metal oxide film of the present embodiment is at least 50 nm or less, for example, extremely fine at 10 nm or less, or 5 nm or less. Therefore , for example, when the sample is thinned to a thickness of 10 nm or less and the electron beam is converged to 1 nmφ, and the measurement range is reduced to a region smaller than, for example, the size of one crystal part, depending on the measurement region spots having regularity indicating crystals oriented on a specific plane can be observed. Further, when a plurality of crystal parts are included in the measurement region, the electron beam transmitted through the crystal part may be irradiated to another crystal part existing in the depth direction. In this case, it can be considered that a plurality of nano-beam electron beam diffraction patterns are observed.

[0054] ≪Electron diffraction pattern of quartz substrate at extremely fine electron beam≫ Fig. 4 shows the nano-beam electron beam diffraction pattern of a quartz glass substrate. The measurement conditions were the same as those for the metal oxide film shown in Fig. 1.

[0055] From Fig. 4, in the quartz glass substrate having an amorphous structure, a halo pattern in which the luminance continuously changes from the main spot without being diffracted to a specific spot is observed. Thus, even when electron beam diffraction of an extremely minute region is performed in a film having an amorphous structure, a plurality of spots arranged in a circular shape as observed in the metal oxide film of the present embodiment are not observed. Therefore, it is confirmed that the plurality of spots arranged in a circular shape observed in Figs. 1(B) to 1(D) are unique to the metal oxide film of the present embodiment.

[0056] ≪Electron diffraction pattern after continuous irradiation with extremely fine electron beam≫ ​​​​Fig. 8 shows the electron diffraction pattern measured after irradiating the electron beam converged to a beam diameter of about 1 nmφ at the point 2 shown in Fig. 1(A) for 1 minute.

[0057] Similar to the electron diffraction pattern shown in Fig. 1(C), the electron diffraction pattern shown in Fig. 8 shows a plurality of spots distributed in a circular shape, and no particular difference is confirmed between the measurement results of the two. This means that the crystal part confirmed in Fig. 1(C) existed during the film formation of the metal oxide film of the present embodiment, and it means that the crystal part was not formed by irradiating the converged electron beam.

[0058] ≪Analysis by X-ray Diffraction≫ The sample in which the metal oxide film of the present embodiment was formed on a quartz glass substrate, used in Figs. 1 and 2, was analyzed using X-ray diffraction (XRD: X-Ray Diffraction). Fig. 6 shows the result of measuring the XRD spectrum using the out-of-plane method.

[0059] In Fig. 6, the vertical axis represents the X-ray diffraction intensity (arbitrary unit), and the horizontal axis represents the diffraction angle 2θ (deg.). The measurement of the XRD spectrum was performed using an X-ray diffractometer D- 8 ADVANCE manufactured by Bruker AXS.

[0060] As shown in Fig. 6, although a peak due to quartz is observed in the vicinity of 2θ = 20 to 23°, no peak due to the crystal part contained in the metal oxide film can be confirmed.

[0061] Also from the result of Fig. 6, it is suggested that the crystal part contained in the metal oxide film of the present embodiment is an extremely fine crystal part.

[0062] ​​​​​​​As described above, the metal oxide film of the present embodiment is presumed to be a film formed by aggregation of irregular crystal parts in the plane orientation. It can be presumed that the film is formed.

[0063] In addition, the size of the crystal parts included in the metal oxide film of the present embodiment is presumed to be, for example, 10 nm or less or 5 nm or less. The metal oxide film of the present embodiment contains, for example, crystal parts (nanocrystals (nc)) of 1 nm or more and 10 nm or less and is a metal oxide film.

[0064] <Method for forming metal oxide film> The method for forming the metal oxide film of the present embodiment will be described below. As described above, the metal oxide film of the present embodiment is formed by a sputtering method in an atmosphere containing oxygen at room temperature. By setting the film-forming atmosphere to an atmosphere containing oxygen, oxygen deficiency in the metal oxide film can be reduced, and a film containing crystal parts can be obtained.

[0065] ≪Reduction of oxygen deficiency≫ In the metal oxide film of the present embodiment, by reducing oxygen deficiency, a film with stable physical properties can be obtained. In particular, when an oxide semiconductor film is applied as the metal oxide film of the present embodiment to fabricate a semiconductor device, oxygen deficiency in the oxide semiconductor film becomes a factor for generating carriers and, as a result, a factor for changing the electrical characteristics of the semiconductor device. Therefore, by fabricating a semiconductor device using an oxide semiconductor film with reduced oxygen deficiency, a highly reliable semiconductor device can be obtained. can be obtained.

[0066] Note that for the metal oxide film of the present embodiment, increasing the oxygen partial pressure in the film-forming atmosphere is preferable because oxygen deficiency can be further reduced. For example, the oxygen partial pressure in the film-forming atmosphere is set to 33% or more. ​ is preferable.

[0067] Fig. 7 shows the nano-beam electron diffraction pattern of the metal oxide film of the present embodiment formed at an oxygen partial pressure of 33%. The metal oxide film of the present embodiment shown in Fig. 7 was produced under the same conditions as the metal oxide film shown in Fig. 1, except that the film formation atmosphere was a mixed atmosphere of argon and oxygen (Ar:O2 = 30 sccm:15 sccm). Also, the nano-beam electron diffraction measurement was performed in the same manner as the measurement described in Figs. 1(B) to 1(D).

[0068] From Fig. 7, it is also confirmed that in the metal oxide film of the present embodiment formed with an oxygen partial pressure of 33%, a plurality of spots arranged in a circular shape are observed in the nano-beam electron diffraction pattern, and a metal oxide film including a crystal part is formed.

[0069] ≪Film formation by sputtering method≫ The oxide target that can be used for forming the metal oxide film of the present embodiment is not limited to the In-Ga-Zn-based oxide. For example, an In-M-Zn-based oxide (M is Al, T i, Ga, Y, Zr, La, Ce, Nd or Hf) can be applied.

[0070] Also, it is preferable to form a metal oxide film including a crystal part, which is the metal oxide film of the present embodiment, using a sputtering target including a polycrystalline oxide having a plurality of crystal grains. When the sputtering target has a plurality of crystal grains and there is an interface where the bonding between the plurality of crystal grains is weak and is easily cleaved, by colliding ions with the sputtering target, the crystal grains may be cleaved to obtain plate-like sputtering particles. The obtained The deposited flat sputtering particles may form a metal oxide film containing nanocrystals by depositing on a substrate. However, it should be noted that the film formation mechanism of the metal oxide film according to the above-described embodiment is merely a consideration. This is because the deposited flat sputtering particles may form a metal oxide film containing nanocrystals by depositing on a substrate. However, it should be noted that the film formation mechanism of the metal oxide film according to the above-described embodiment is merely a consideration. This is because the deposited flat sputtering particles may form a metal oxide film containing nanocrystals by depositing on a substrate. However, it should be noted that the film formation mechanism of the metal oxide film according to the above-described embodiment is merely a consideration.

[0071] The metal oxide film of the above-described embodiment is a film in which crystal parts having irregular plane orientations and different sizes are mixed, and the crystal parts are suggested to be extremely fine to the extent that spots are not observed in the selected area electron diffraction pattern. The metal oxide film of the above-described embodiment is a film in which crystal parts having irregular plane orientations and different sizes are mixed, and the crystal parts are suggested to be extremely fine to the extent that spots are not observed in the selected area electron diffraction pattern. The metal oxide film of the above-described embodiment is a film in which crystal parts having irregular plane orientations and different sizes are mixed, and the crystal parts are suggested to be extremely fine to the extent that spots are not observed in the selected area electron diffraction pattern.

[0072] Further, the metal oxide film of the present embodiment has a region containing crystal parts and is a film with stable physical properties. Therefore, by applying the metal oxide film of the present embodiment to a semiconductor device, it is possible to provide a highly reliable semiconductor device. Further, the metal oxide film of the present embodiment has a region containing crystal parts and is a film with stable physical properties. Therefore, by applying the metal oxide film of the present embodiment to a semiconductor device, it is possible to provide a highly reliable semiconductor device. Further, the metal oxide film of the present embodiment has a region containing crystal parts and is a film with stable physical properties. Therefore, by applying the metal oxide film of the present embodiment to a semiconductor device, it is possible to provide a highly reliable semiconductor device.

[0073] (Comparative Example) In this comparative example, the crystallinity of the metal oxide film produced by the liquid phase method will be described with reference to the drawings. In this comparative example, the crystallinity of the metal oxide film produced by the liquid phase method will be described with reference to the drawings.

[0074] The film formation method of the metal oxide film formed in this comparative example is shown below.

[0075] First, In2O3 (5 wt%), Ga2O3 (3 wt%), ZnO (5 wt%) and a coating agent were mixed so that In:Ga:Zn = 1:1:1, and spin coated on a glass substrate. The conditions for spin coating were changed stepwise from 900 rpm to 2 000 rpm using a spinner.

[0076] After coating, a first heat treatment was performed at 150 ° C for 2 minutes in an air atmosphere using a hot plate. After coating, a first heat treatment was performed at 150 ° C for 2 minutes in an air atmosphere using a hot plate.

[0077] Next, a second heat treatment was carried out in an air atmosphere at 450° C. for 1 hour. The metal oxide film of this comparative example (liquid phase film formation) and the metal oxide film shown in FIG. For each of the metal oxide films (deposited by sputtering) of the present embodiment, X X-ray Photoelectron Spectros (XPS) The bonding state was evaluated using a 100% JIS copy. The evaluation results are shown in Figure 24.

[0078] In the XPS analysis, a QuanteraSXM manufactured by PHI was used as the measuring device. For each metal oxide film, the In 3d(5 / 2) orbital (see Figure 24(A)), G 3d orbital of a (see FIG. 24(B)), 3p orbital of Zn (see FIG. 24(C)), and 1p orbital of O The spectrum in the region corresponding to the s orbital (see Figure 24(D)) is shown. 24 shows the evaluation results of an In—Ga—Zn oxide film formed by a liquid phase method according to a comparative example. The dashed line indicates the In-Ga-Zn film formed by the sputtering method according to the present embodiment. 1 shows the evaluation results of the oxide film.

[0079] From Figure 24(A) to (D), although a slight shift in the binding energy is observed, this comparison The metal oxide film formed by the liquid phase method shown in the example and the sputtering method according to the present embodiment The metal oxide film formed in this comparative example had a spectrum similar to that of the film formed in the previous example. The metal oxide film prepared by the liquid phase method shown here is indeed an In-Ga-Zn oxide film. It was identified that:

[0080] Next, the prepared sample of this comparative example was analyzed by XRD. The results of analysis using the plane method are shown below.

[0081] For the analysis by XRD, after the first heat treatment, In-Ga-Zn oxide film samples that were subjected to a second heat treatment at 350 °C, 450 °C, or 550 °C for 1 hour in an air atmosphere were used.

[0082] In Fig. 19, the vertical axis is the X-ray diffraction intensity (arbitrary unit), and the horizontal axis is the diffraction angle 2θ (deg. ). The XRD measurement was performed using an X-ray diffractometer D-8 ADVANCE E manufactured by Bruker AXS.

[0083] Fig. 19(A) shows the measurement results of the sample prepared by the liquid phase method in this comparative example. Also, the XRD pattern of the sample without the first heat treatment is the pattern indicated as as-depo. Note that in Figs. 19(B), (C), and (D), the measurement results of indium oxide films, gallium oxide films, or zinc oxide films formed by the liquid phase method and then subjected to a heat treatment at 350 °C, 450 °C, or 550 °C for 1 hour in an air atmosphere are shown.

[0084] From Fig. 19, in the XRD pattern of the indium oxide film after the heat treatment, peaks corresponding to the crystal peaks of In2O3 were confirmed. Also, in the XRD pattern of the zinc oxide film after the heat treatment, peaks corresponding to the crystal peaks of ZnO were confirmed. On the other hand, in the sample of this comparative example, unlike the indium oxide film and the zinc oxide film, no crystalline peaks were confirmed in the samples after the heat treatment under any temperature conditions.

[0085] Also, for the sample subjected to a second heat treatment at 450 °C for 1 hour in an air atmosphere, the film density was measured by the X-ray reflectivity measurement method (XRR: X-Ray Reflection).

[0086] In XRR measurement, X-rays are incident on a measurement sample, and the critical angle and amplitude wave of the incident X-rays are measured. By measuring the change in shape, etc., and performing theoretical analysis using the measured critical angle, amplitude waveform, etc., This is a measurement method for measuring the density of the formed thin film.

[0087] The measured film densities are shown in Table 1.

[0088] [Table 1]

[0089] From Table 1, the film obtained by the liquid phase method has a non-uniformity compared with the theoretical value calculated from the single crystal structure. However, the film formed by the liquid phase method has a low roughness. It should be noted that it is difficult to measure the film density with high accuracy due to its large size.

[0090] Next, the metal oxide film of the comparative example and the metal oxide film of the present embodiment were examined to determine the amount of ions contained in the film. The impurity concentration was measured by SIMS (Secondary Ion Mass Spectroscopy) It was measured by try analysis.

[0091] FIG. 18(A) shows the hydrogen ( 1 18(B) shows the profile of the H) concentration in the metal oxide film of the comparative example and the present example. The carbon ( 12 C) Concentration profile. The axis represents the depth (nm), and the vertical axis represents the hydrogen or carbon concentration (atoms / cm 3 ) is doing.

[0092] In FIG. 18, the metal oxide film of the comparative example was produced by the liquid phase method under the same conditions as above. The prepared sample was applied. However, before spin coating, filtration was performed with a membrane filter (0.2 μm ). Also, the conditions for the second heat treatment were 450 °C, 500 °C or 550 °C for 1 hour under an air atmosphere. Other conditions were the same as those for the metal oxide film in the above-described liquid phase method . Also, the metal oxide film of the present embodiment was fabricated by a sputtering method under the same conditions as the metal oxide film shown in FIG. 7

[0093] From FIGS. 18(A) and 18(B), it was confirmed that a larger amount of hydrogen and carbon uniformly existed in the metal oxide film of the comparative example than in the metal oxide film of the present embodiment in the film

[0094] Since the carbon concentration of the metal oxide film of the present embodiment shown in FIG. 18(B) gradually decreases from the surface into the film, it is suggested that the carbon contained in the metal oxide film of the present embodiment has a strong side derived from surface contamination

[0095] On the other hand, in the metal oxide film of the comparative example, hydrogen was 1×10 22 (atoms / cm 3 ) or more and carbon was 4×10 21 (atoms / cm 3 ) or more, and it was found that they uniformly existed in the film at high values . It is presumed that the carbon contained in the metal oxide film of the comparative example is derived from the organic acid salt that is the raw material of the spin coating material

[0096] Next, a cross-sectional TEM image of the sample of the comparative example that was subjected to the second heat treatment at 450 °C for 1 hour under an air atmosphere is shown in FIG. 20. The cross-sectional observation was performed with a transmission electron microscope (Hitachi High-Technologies Corporation "H-9000NAR") at an acceleration voltage of 300 kV. FIG. 20(A) shows a magnification of 5 ​​​20(B) is a cross-sectional observation image at a magnification of 2,000,000 times, and FIG. 20(C) is a cross-sectional observation image at a magnification of 2,000,000 times. (C) is a cross-sectional image observed at 8 million times magnification.

[0097] As can be seen from Figures 20(A) and 20(B), the sample prepared by the liquid phase method in this comparative example has an amorphous region. It can be seen that the majority of the area is covered by the film. ) is found to exist.

[0098] In the region a in FIG. 20(C), the brightness of the cross-sectional TEM image is high, and the film density is low. In region b in Figure 20(C), the brightness of the cross-sectional TEM image is low, and it can be said that the film It can be said that this is an area with high density.

[0099] Regions a and b in Figure 20(C) were observed using nanobeam electron diffraction. 21(A) to (C) show the nanobeam electron diffraction patterns.

[0100] Electron diffraction was performed using a transmission electron microscope (Hitachi High-Technologies Corporation "HF-2000"). The acceleration voltage was 200 kV and the beam diameter was approximately 1 nm. 21(B) and 21(C) are nanobeam electron diffraction patterns of region a in FIG. 21(B) and FIG. 21(C). are both nanobeam electron diffraction patterns of region b in Figure 20(C), and are obtained from two different locations. (denoted as b1 and b2) are the observation results.

[0101] FIG. 21(D) shows a nanobeam electron diffraction pattern of a metal oxide film according to one embodiment of the present invention. The electron diffraction pattern was prepared and observed under the same conditions as those shown in Figure 7. be.

[0102] As shown in Fig. 21, in the metal oxide film prepared by the liquid phase method in this comparative example, in any region it was confirmed that the pattern was different from the plurality of spots (bright spots) arranged circumferentially observed in the metal oxide film of one aspect of the present invention shown in Fig. 21(D).

[0103] As shown in Fig. 21(A), the nano-beam electron diffraction pattern of region a showed a pattern close to a halo indicating amorphous. The existence of such a region with low crystallinity can be presumed to be due to the low density of the film or a high impurity concentration.

[0104] Also, as shown in Figs. 21(B) and (C), in the nano-beam electron diffraction pattern of region b, spots (indicated by 1 to 3 in Figs. 21(B) and (C)) having regularity indicating crystals oriented on a specific plane were observed. The results of analyzing the diffraction pattern for these spots are shown in Table 2 below.

[0105]

Table 2

[0106] From Table 2, the measured values of the d-values derived from the spots observed in Fig. 21(B) or Fig. 21(C) are almost the same as the theoretical values in a plurality of plane orientations of InGaZnO4, and in the In-Ga-Zn oxide film of this comparative example formed by the liquid phase method, there are crystalline regions partially due to InZnGaO4. It was confirmed that

[0107] From the above, the In-Ga-Zn oxide film prepared by the liquid phase method contains impurities, but it can be said that regions having a periodic atomic arrangement due to the crystals of InZnGaO4 and regions with very low crystallinity close to amorphous coexist. ​​​

[0108] Next, the effects of impurities such as hydrogen and carbon present in the metal oxide film of the comparative example on the crystallinity of the metal oxide film were evaluated by calculation.

[0109] In the following calculations, the effect of hydrogen on the crystallization of the metal oxide film was investigated by first-principles calculations from. Specifically, the energy differences between the amorphous state and the crystalline state were examined for the cases where InGaZnO4 contains no hydrogen and where it contains 6.67 a tom% of hydrogen, respectively. The atomic number density of the In -Ga-Zn-O crystal is 8.54×10 22 atoms / cm 3 and, from the SIMS analysis results shown in Fig. 18, this hydrogen concentration is equivalent to the hydrogen concentration contained in the metal oxide film of this comparative example. In the calculations, an In-Ga-Zn oxide film with an atomic ratio of In:Ga: Zn = 1:1:1 was applied as an example of the metal oxide film.

[0110] Fig. 22 shows the lattice structure of the In-Ga-Zn-O crystal having 112 atoms used in the calculation.

[0111] In the calculation, for the structure shown in Fig. 22, structures without adding H and with 8 H atoms added were created, each was optimized, and the energy was calculated. Furthermore, based on the obtained optimized structures, an amorphous structure was created in the following process. [[ID=4H1]]

[0112] (1) Molecular dynamics calculation in the NVT ensemble at a temperature of 3000 K. (2) Molecular dynamics calculation in the NVT ensemble at a temperature of 1000 K and a time of 2 psec. (3) Structure optimization.

[0113] ​​​However, the structures at 5 psec, 5.5 psec, and 6 psec after the calculation in (1) above were extracted, and the calculations after (2) were performed to create three amorphous structures each, and the average value of the energy was taken. For the calculation, the first-principles calculation software "VASP (Vienna Ab-initio Simulation Package)" was used. The calculation conditions are shown in Table 3. were extracted, and the calculations after (2) were performed to create three amorphous structures each, and the average value of the energy was taken. For the calculation, the first-principles calculation software "VASP (Vienna Ab-initio Simulation Package)" was used. The calculation conditions are shown in Table 3. shown in Table 3.

[0114]

Table 3

[0115] A part of the structure obtained by calculation is shown in Fig. 23, and the calculation results of the energy difference are shown in Table 4. Fig. 23(A) shows the structure of a single-crystalline In-Ga-Zn oxide film without H addition (0 atom%). Fig. 23(B) shows the structure of a single-crystalline In-Ga-Z n oxide film with 8 H atoms added (6.67 atom%). Fig. 23(C) shows the structure of an amorphous In-Ga-Zn oxide film without H addition (0 atom%). Fig. 23(D) shows the structure of an amorphous In-Ga-Zn oxide film with 8 H atoms added (6.67 atom%). atom%).

[0116]

Table 4

[0117] From Table 4, it can be seen that the energy of the In-Ga-Zn oxide film decreases significantly upon crystallization. On the other hand, when H is added, the stabilization energy due to crystallization decreases. From the above, in the metal oxide film prepared by the liquid-phase method of this comparative example, together with the pattern including spots showing a periodic atomic arrangement, the nanobeam electron diffraction pattern close to the halo pattern and the pattern including spots showing a periodic atomic arrangement, the nanobeam electron diffraction pattern close to the halo pattern is obtained. is obtained. As a factor for obtaining the - on, destabilization of the crystal structure by hydrogen is presumed.

[0118] As described above, by including hydrogen, which is an impurity, in the metal oxide film, the stability of the crystal decreases. This calculation result is also consistent with the fact that in the metal oxide film of the comparative example where a nano-beam electron diffraction pattern close to the halo pattern was confirmed, the contents of hydrogen and carbon, which are impurities, are higher than those of the metal oxide film of the present embodiment.

[0119] As described above, the present embodiment can be implemented in appropriate combination with other embodiments described in this specification.

[0120] (Embodiment 2) In the present embodiment, a configuration example of a transistor to which a metal oxide film (oxide semiconductor film) that exhibits semiconductor characteristics and is the metal oxide film exemplified in Embodiment 1 is applied will be described with reference to the drawings.

[0121] <Configuration Example of Transistor> Fig. 9(A) shows a schematic cross-sectional view of a transistor 100 exemplified below. The transistor 1 00 is a bottom gate type transistor.

[0122] The transistor 100 includes a gate electrode 102 provided on a substrate 101, an insulating layer 103 provided on the substrate 101 and on the gate electrode 102, an oxide semiconductor layer 104 provided so as to overlap the gate electrode 102 on the insulating layer 103, and a pair of electrodes 105a and 105b in contact with the upper surface of the oxide semiconductor layer 104. Further, an insulating layer 106 covering the insulating layer 103, the oxide semiconductor layer 104, and the pair of electrodes 105a and 105b, and an insulating layer 107 is provided on the insulating layer 106.

[0123] The oxide semiconductor film of one embodiment of the present invention is applied to the oxide semiconductor layer 104 of the transistor 100. It is possible.

[0124] Circuit Board 101 There is no particular restriction on the material of the substrate 101, but it should be strong enough to withstand the subsequent heat treatment. Use heat-resistant materials, such as glass substrates, ceramic substrates, quartz substrates, and sapphire substrates. A ceramic substrate, a YSZ (yttria stabilized zirconia) substrate, or the like may be used as the substrate 101. In addition, a single crystal semiconductor substrate such as silicon or silicon carbide, a polycrystalline semiconductor substrate, a silicon It is also possible to use a compound semiconductor substrate such as a congermanium substrate, an SOI substrate, or the like. Moreover, a substrate having a semiconductor element provided thereon may be used as the substrate 101. .

[0125] In addition, a flexible substrate such as plastic is used as the substrate 101, and the substrate is directly formed on the flexible substrate. Alternatively, the transistor 100 may be formed between the substrate 101 and the transistor 100. The peeling layer may be provided on the upper layer of the transistor. After that, it can be separated from the substrate 101 and used for transferring to another substrate. Therefore, the transistor 100 can be mounted on a substrate with poor heat resistance or a flexible substrate.

[0126] Gate electrode 102 The gate electrode 102 may be made of aluminum, chromium, copper, tantalum, titanium, molybdenum, or titanium. or an alloy containing the above metals or a combination of the above metals. It can be formed by using an alloy in which manganese or zirconium is combined. One or more metals selected therefrom may be used. Further, the gate electrode 102 may have a single-layer structure or a laminated structure of two or more layers. For example, a single-layer structure of an aluminum film containing silicon, a two-layer structure in which a titanium film is laminated on the aluminum film, a two-layer structure in which a titanium film is laminated on a titanium nitride film a two-layer structure in which a tungsten film is laminated on a titanium nitride film, a two-layer structure in which a tungsten film is laminated on a tantalum nitride film or a tungsten nitride film, a three-layer structure in which a titanium film is formed on a titanium film and an aluminum film is laminated on the titanium film, and further a titanium film is formed thereon, etc. There is. Also, an alloy film in which aluminum is combined with one or more metals selected from titanium, tantalum, tungsten, molybdenum, chromium , neodymium, scandium, or a nitride film thereof may be used.

[0127] <00,00854> Further, the gate electrode 102 may be applied with a conductive material having translucency such as indium tin oxide, indium oxide containing tungsten oxide , indium zinc oxide containing tungsten oxide, indium oxide containing titanium oxide , indium tin oxide containing titanium oxide, indium zinc oxide, indium tin oxide added with silicon oxide , etc. Further, a laminated structure of the above-mentioned conductive material having translucency and the above-mentioned metal may also be used.

[0128] Further, an In-Ga-Zn-based oxynitride semiconductor film , an In-Sn-based oxynitride semiconductor film, an In-Ga-based oxynitride semiconductor film, an In-Zn-based oxynitride It has a function and a value greater than the electron affinity of the oxide semiconductor. Therefore, when using the oxide semiconductor the threshold voltage of the transistor can be shifted to a positive value, and a switching element with so-called normally-off characteristics can be realized. For example, an In-Ga-Zn-based oxynitride semiconductor film having a nitrogen concentration higher than that of at least the oxide semiconductor layer 104, specifically, a nitrogen concentration of 7 atomic% or more, is used.

[0129] 《Insulating layer 103》 The insulating layer 103 functions as a gate insulating film. The insulating layer 103 in contact with the lower surface of the oxide semiconductor layer 104 is preferably an amorphous film.

[0130] The insulating layer 103 may be made of, for example, silicon oxide, silicon oxynitride, silicon nitride oxide, silicon nitride, aluminum oxide, hafnium oxide, gallium oxide, or a Ga-Zn-based metal oxide , silicon nitride, etc., and may be provided in a laminated or single-layer form.

[0131] Also, as the insulating layer 103, hafnium silicate (HfSiO x ), hafnium silicate with nitrogen added (HfSi O x O y N z ), hafnium aluminate with nitrogen added (HfAl O x O y N z ), high-k materials such as hafnium oxide and yttrium oxide are used to reduce the gate leakage of the transistor.

[0132] 《Pair of electrodes 105a, 105b》 The pair of electrodes 105a and 105b function as the source electrode or drain electrode of the transistor.

[0133] The pair of electrodes 105a and 105b can use, as the conductive material, a metal composed of aluminum, titanium, chromium, nickel, copper, yttrium, zirconium, molybdenum, silver, tantalum, or tungsten, or an alloy containing the same, in a single-layer structure or a laminated structure. For example, a single-layer structure of an aluminum film containing silicon, a two-layer structure in which a titanium film is laminated on an aluminum film, a two-layer structure in which a titanium film is laminated on a tungsten film, a two-layer structure in which a copper film is laminated on a copper-magnesium-aluminum alloy film, a titanium film or a titanium nitride film and, an aluminum film or a copper film is laminated on the titanium film or the titanium nitride film, and further a titanium film or a titanium nitride film is formed thereon, a three-layer structure; a molybdenum film or a molybdenum nitride film and, an aluminum film or a copper film is laminated on the molybdenum film or the molybdenum nitride film, and further a molybdenum film or a molybdenum nitride film is formed thereon, a three-layer structure, etc. are available. Note that a transparent conductive material containing indium oxide, tin oxide, or zinc oxide may be used.

[0134] 《Insulating Layers 106 and 107》 The insulating layer 106 preferably uses an oxide insulating film containing more oxygen than oxygen satisfying the stoichiometric composition. Some oxygen desorbs from such an oxide insulating film by heating. For example, when such an oxide insulating film is heated at a temperature equal to or higher than the heat treatment temperature in the manufacturing process of the transistor, by temperature-programmed desorption spectroscopy (TDS: Thermal Desorption S pectroscopy) analysis, the desorption amount of oxygen in terms of oxygen atoms is 1.0×10 atoms / cm 18 or more, preferably 3.0×10 3 atoms / cm 20 or more, preferably 3.0×10 3The above is the case .

[0135] As the insulating layer 106, silicon oxide, silicon oxynitride, or the like can be used.

[0136] Note that the insulating layer 106 also functions as a damage relaxation film for the oxide semiconductor layer 10 4 when forming the insulating layer 107 formed later.

[0137] Further, an oxide film that permeates oxygen may be provided between the insulating layer 106 and the oxide semiconductor layer 104. .

[0138] As the oxide film that permeates oxygen, silicon oxide, silicon oxynitride, or the like can be used. Note that in this specification, the silicon oxynitride film refers to a film having a higher oxygen content than nitrogen in its composition, and the silicon nitride oxide film refers to a film having a higher nitrogen content than oxygen in its composition. <

[0139] As the insulating layer 107, an insulating film having a blocking effect on oxygen, hydrogen, water, etc. can be used. By providing the insulating layer 107 on the insulating layer 106, it is possible to prevent the diffusion of oxygen from the oxide semiconductor layer 104 to the outside and the intrusion of hydrogen, water, etc. from the outside into the oxide semiconductor layer 104. Examples of such insulating films include silicon nitride, silicon nitride oxide, aluminum oxide, aluminum nitride oxide, gallium oxide, gallium nitride oxide, yttrium oxide, yttrium nitride oxide, hafnium oxide, hafnium nitride oxide, and the like.

[0140] <Example of manufacturing method of transistor> Subsequently, an example of a method for manufacturing the transistor 100 illustrated in FIG. 9 will be described.

[0141] ​​​​​First, as shown in FIG. 10(A), a gate electrode 102 is formed on a substrate 101. An insulating layer 103 is formed on the electrode 102 .

[0142] Here, a glass substrate is used as the substrate 101.

[0143] <<Formation of gate electrode>> The gate electrode 102 is formed by the following methods. First, the gate electrode 102 is formed by sputtering, CVD, or evaporation. A conductive film is formed by deposition or the like, and a first photomask is used to perform photolithography on the conductive film. A resist mask is formed by a deposition process. Next, a part of the conductive film is The resist mask is then etched to form the gate electrode 102. After that, the resist mask is removed.

[0144] The gate electrode 102 may be formed by electrolytic plating, printing, inkjet printing, or the like instead of the above-mentioned method. It may also be formed by a jet method or the like.

[0145] <<Formation of gate insulating layer>> The insulating layer 103 is formed by a sputtering method, a CVD method, a vapor deposition method, or the like.

[0146] The insulating layer 103 is a silicon oxide film, a silicon oxynitride film, or a silicon nitride oxide film. When forming the silicon-containing film, a deposition gas containing silicon and an oxidizing gas are used as the source gas. Representative examples of silicon-containing deposition gases include silane, disilane, trisilane, and the like. Examples of oxidizing gases include oxygen, ozone, nitrous oxide, and dioxygen. Examples include nitrogen dioxide.

[0147] In addition, when forming a silicon nitride film as the insulating layer 103, a two-stage formation method is used. First, a mixed gas of silane, nitrogen, and ammonia is used as a raw material gas. A first silicon nitride film with few defects is formed by the plasma CVD method. Next, the raw material gas is switched to a mixed gas of silane and nitrogen, and a second silicon nitride film with a low hydrogen concentration and capable of blocking hydrogen is formed. By such a formation method, a silicon nitride film with few defects and having hydrogen blocking properties can be formed as the insulating layer 103. Moreover, when forming a gallium oxide film as the insulating layer 103, it can be formed using the MOCVD (Metal Organic Chemical Vapor Deposition) method.

[0148] Also, when forming a gallium oxide film as the insulating layer 103, it can be formed using the MOCVD (Metal Organic Chemical Vapor Deposition) method.

[0149] 《Formation of Oxide Semiconductor Layer》 Next, as shown in FIG. 10(B), an oxide semiconductor layer 104 is formed on the insulating layer 103.

[0150] The method for forming the oxide semiconductor layer 104 is shown below. First, an oxide semiconductor film is formed by the method exemplified in Embodiment 1. Subsequently, a resist mask is formed on the oxide semiconductor film by a photolithography process using a second photomask. Next, a part of the oxide semiconductor film is etched using the resist mask to form the oxide semiconductor layer 104. Thereafter, the resist mask is removed.

[0151] After that, a heat treatment may be performed. When performing the heat treatment, it is preferably performed in an atmosphere containing oxygen.

[0152] 《Formation of a Pair of Electrodes》 Next, as shown in FIG. 10(C), a pair of electrodes 105a and 105b are formed.

[0153] The method for forming the pair of electrodes 105a and 105b will be described below. First, a sputtering method is used. A conductive film is formed by a CVD method, a vapor deposition method, etc. Next, a third photomask is used on the conductive film. A resist mask is formed by a photolithography process. The conductive film is partially etched using the etching solution to form a pair of electrodes 105a and 105b. Thereafter, the resist mask is removed.

[0154] Note that as shown in FIG. 10B, when the conductive film is etched, the upper surface of the oxide semiconductor layer 104 is Therefore, the oxide semiconductor layer 104 may be partially etched and thinned. It is preferable that the thickness of the oxide semiconductor film be set to be thick in advance during the formation.

[0155] <<Formation of insulating layer>> Next, as shown in FIG. 10(D), the oxide semiconductor layer 104 and the pair of electrodes 105a and 105b are An insulating layer 106 is formed on 5b, and then an insulating layer 107 is formed on the insulating layer 106.

[0156] When a silicon oxide film or a silicon oxynitride film is formed as the insulating layer 106, the source gas As the gas, it is preferable to use a deposition gas containing silicon and an oxidizing gas. Representative examples of deposition gases containing silane include silane, disilane, trisilane, and fluorinated silane. Oxidizing gases include oxygen, ozone, nitrous oxide, and nitrogen dioxide.

[0157] For example, a substrate placed in a vacuum-evacuated processing chamber of a plasma CVD device is heated to 180°C or higher. The temperature is kept at 260°C or less, more preferably 200°C to 240°C, and the raw material gas is introduced into the processing chamber. By introducing the gas, the pressure in the processing chamber is set to 100 Pa or more and 250 Pa or less, more preferably 1 Set it to 200 Pa or less and 00 Pa or more, and supply high-frequency power to the electrode provided in the processing chamber at 0.17 W / cm 2 or more 0.5 W / cm 2 or less, more preferably 0.25 W / cm 2 or more and 0.35 W / cm 2 or less to form a silicon oxide film or a silicon oxynitride film under the condition of supplying high-frequency power .

[0158] By supplying high-frequency power, the decomposition efficiency of the source gas in the plasma increases, the oxygen radicals increase, and the oxidation of the source gas proceeds, so that the oxygen content in the oxide insulating film becomes more than the stoichiometric ratio . However, in the film formed at the above temperature of the substrate temperature, a part of the oxygen in the film desorbs by heating in a later process . As a result, it is possible to form an oxide insulating film that contains more oxygen than the stoichiometric composition and in which a part of the oxygen desorbs by heating .

[0159] When an oxide insulating film is provided between the oxide semiconductor layer 104 and the insulating layer 106, in the formation process of the insulating layer 106, the oxide insulating film serves as a protective film for the oxide semiconductor layer 104 . As a result, it is possible to form the insulating layer 106 using high-frequency power with a high power density while reducing damage to the oxide semiconductor layer 104 .

[0160] For example, a substrate placed in a vacuum-exhausted processing chamber of a plasma CVD apparatus is maintained at 180°C or more and 400°C or less, more preferably 200°C or more and 370°C or less, and a source gas is introduced into the processing chamber to set the pressure in the processing chamber to 20 Pa or more and 250 Pa or less, more preferably 10 0 Pa or more and 250 Pa or less, and supply high-frequency power to the electrode provided in the processing chamber ​Thus, a silicon oxide film or a silicon oxynitride film can be formed as the oxide insulating film. Further, by setting the pressure in the processing chamber to 100 Pa or more and 250 Pa or less, it is possible to reduce the damage to the oxide semiconductor layer 104 when forming the oxide insulating layer.

[0161] As the raw material gas for the oxide insulating film, it is preferable to use a depositable gas containing silicon and an oxidizing gas. Typical examples of the depositable gas containing silicon include silane, disilane, trisilane, silane fluoride, and the like. Examples of the oxidizing gas include oxygen, ozone, nitrous oxide, nitrogen dioxide, and the like.

[0162] The insulating layer 107 can be formed by a sputtering method, a CVD method, or the like.

[0163] When forming a silicon nitride film or a silicon oxynitride film as the insulating layer 107, as the raw material gas, it is preferable to use a depositable gas containing silicon, an oxidizing gas, and a gas containing nitrogen. Typical examples of the depositable gas containing silicon include silane, disilane, trisilane, silane fluoride, and the like. Examples of the oxidizing gas include oxygen, ozone, nitrous oxide, nitrogen dioxide, and the like. Examples of the gas containing nitrogen include nitrogen, ammonia, and the like.

[0164] The transistor 100 can be formed by the above steps.

[0165] <Modification Example of Transistor 100> Hereinafter, a configuration example of a transistor that is partially different from the transistor 100 will be described.

[0166] <<Modification Example 1>> Fig. 9(B) shows a schematic cross-sectional view of a transistor 110 exemplified below. Transistor 1 10 differs from transistor 100 in that the structure of the oxide semiconductor layer is different. Note that in the following, for components having the same structure or the same functions as those in other configuration examples, the same reference numerals are given and duplicate explanations are omitted.

[0167] The oxide semiconductor layer 114 included in transistor 110 is formed by laminating an oxide semiconductor layer 114a and an oxide semiconductor layer 114b.

[0168] Note that the boundary between the oxide semiconductor layer 114a and the oxide semiconductor layer 114b may be unclear, and therefore, in the drawings such as FIG. 9(B), these boundaries are indicated by broken lines.

[0169] Of the oxide semiconductor layer 114a and the oxide semiconductor layer 114b, one or both of them may be applied with the oxide semiconductor film of one aspect of the present invention.

[0170] For example, the oxide semiconductor layer 114a typically uses In-Ga oxide, In-Zn oxide, In-M-Zn oxide (M is Al, Ti, Ga, Y, Zr, La, Ce, Nd, or H f). Further, when the oxide semiconductor layer 114a is In-M-Zn oxide, the atomic ratio of In and M excluding Zn and oxygen is preferably such that In is 25 atomic% or more and M is less than 75 atomic% when the total of In and M is 100 atomic%, more preferably, In is 34 atomic% or more and M is less than 66 atomic%. Further for example, the oxide semiconductor layer 114a uses a material having an energy gap of 2 eV or more, preferably 2 .5 eV or more, more preferably 3 eV or more.

[0171] For example, the oxide semiconductor layer 114b contains In or Ga, and typically, an In-Ga acid oxide, an In-Zn oxide, or an In-M-Zn oxide (M is Al, Ti, Ga, Y, Zr, La, Ce, Nd, or Hf), and the energy level of the lower end of the conduction band is closer to the vacuum level than that of the oxide semiconductor layer 114a. Typically, the difference between the energy level of the lower end of the conduction band of the oxide semiconductor layer 114b and the energy level of the lower end of the conduction band of the oxide semiconductor layer 114a is preferably 0.05 eV or more, 0.07 eV or more, 0.1 eV or more, or 0.15 eV or more, and 2 eV or less, 1 eV or less, 0.5 eV or less, or 0.4 eV or less.

[0172] For another example, when the oxide semiconductor layer 114b is an In-M-Zn oxide, the atomic ratio of In to M excluding Zn and oxygen is preferably such that, assuming the total of In and M is 100 atomic%, In is less than 50 atomic% and M is 50 atomic% or more, and more preferably, In is less than 25 atomic% and M is 75 atomic% or more.

[0173] For example, a target with an atomic ratio of In:Ga:Zn = 1:1:1 or 3:1:2 can be used for the oxide semiconductor layer 114a. Also, a target with an atomic ratio of In:Ga:Zn = 1:3:2, 1:6:4, or 1:9:6 can be used for the oxide semiconductor layer 114b. Note that the atomic ratio of the oxide semiconductor layer 114a and the oxide semiconductor layer 114b may be different from the atomic ratio of the target used, and there may be a difference of plus or minus 20%.

[0174] ​​​​​​​​​The content of Ga that functions as a stabilizer in the oxide semiconductor layer 114b provided in the upper layer By using an oxide with a high content of it is possible to suppress the release of oxygen from the oxide semiconductor layer 114a and the oxide semiconductor layer 114

[0175] Note that it is not limited to these, and those with an appropriate composition may be used according to the semiconductor characteristics and electrical characteristics (field effect mobility, threshold voltage, etc.) of the required transistor. Also, in order to obtain the semiconductor characteristics of the required transistor, it is preferable to make the carrier density, impurity concentration, defect density, atomic number ratio of metal elements to oxygen, interatomic distance, density, etc. of the oxide semiconductor layer 114a and the oxide semiconductor layer 11 4b appropriate.

[0176] Note that in the above, as the oxide semiconductor layer 114, a structure in which two oxide semiconductor layers are stacked is exemplified, but a structure in which three or more oxide semiconductor layers are stacked may also be used.

[0177] <<Modification 2>> FIG. 9(C) shows a schematic cross-sectional view of a transistor 120 exemplified below. The transistor 1 20 is different from the transistor 100 and the transistor 11 0 in that the structure of the oxide semiconductor layer is different.

[0178] The oxide semiconductor layer 124 included in the transistor 120 is composed of an oxide semiconductor layer 124a, an oxide semiconductor layer 124b, and an oxide semiconductor layer 124c stacked in this order.

[0179] The oxide semiconductor layer 124a and the oxide semiconductor layer 124b are stacked and provided on the insulating layer 103 Further, the oxide semiconductor layer 124c is provided in contact with the upper surface of the oxide semiconductor layer 124b, and the upper surfaces and side surfaces of the pair of electrodes 105a and 105b.

[0180] Of the oxide semiconductor layer 124a, the oxide semiconductor layer 124b, and the oxide semiconductor layer 124c, the oxide semiconductor film of one aspect of the present invention can be applied to any one, or any two, or all of them. It can be done.

[0181] For example, as the oxide semiconductor layer 124b, the same configuration as the oxide semiconductor layer 114a exemplified in the above Modification 1 can be used. Also, for example, as the oxide semiconductor layers 124a and 124c, the same configuration as the oxide semiconductor layer 114b exemplified in the above Modification 1 can be used. It can be done. It can be done.

[0182] For example, by using an oxide having a high content of Ga that functions as a stabilizer in the oxide semiconductor layers 124a and 124c, the release of oxygen from the oxide semiconductor layer 124a, the oxide semiconductor layer 124b, and the oxide semiconductor layer 124c can be suppressed. It can be done. It can be done. It can be done.

[0183] Also, for example, when a channel is mainly formed in the oxide semiconductor layer 124b, by using an oxide having a high content of In in the oxide semiconductor layer 124b and providing a pair of electrodes 105a and 105b in contact with the oxide semiconductor layer 124b, the on-current of the transistor 120 can be increased. It can be done. It can be done. It can be done.

[0184] <Another configuration example of the transistor> Hereinafter, a configuration example of a top-gate type transistor to which the oxide semiconductor film of one aspect of the present invention can be applied will be described. It can be done.

[0185] <Configuration example> FIG. 11(A) shows a schematic cross-sectional view of a top-gate type transistor 150 exemplified below. Yes.

[0186] Transistor 150 includes an oxide semiconductor layer 104 provided on a substrate 101 provided with an insulating layer 151, a pair of electrodes 105a and 105b in contact with the upper surface of the oxide semiconductor layer 104, an insulating layer 103 provided on the oxide semiconductor layer 104 and the pair of electrodes 105a and 105b, and a gate electrode 102 provided on the insulating layer 103 so as to overlap the oxide semiconductor layer 104. Further, an insulating layer 152 is provided to cover the insulating layer 103 and the gate electrode 102. The oxide semiconductor film of one aspect of the present invention can be applied to the oxide semiconductor layer 104 of the transistor 150. The insulating layer 151 has a function of suppressing the diffusion of impurities from the substrate 101 to the oxide semiconductor layer 104. For example, the same configuration as the insulating layer 107 can be used. Note that the insulating layer 151 may not be provided if it is not necessary. The insulating layer 152 can be applied with an insulating film having a blocking effect on oxygen, hydrogen, water, etc., similar to the insulating layer 107. Note that the insulating layer 107 may not be provided if it is not necessary.

[0187]

[0188]

[0189]

[0190]

[0191]

[0192] <<Modification Example>> Hereinafter, a configuration example of a transistor that is partially different from the transistor 150 will be described.

[0191] FIG. 11(B) shows a schematic cross-sectional view of a transistor 160 exemplified below. The transistor 160 is different from the transistor 150 in that the configuration of the oxide semiconductor layer is different.

[0192] ​The oxide semiconductor layer 164 included in the transistor 160 is composed of an oxide semiconductor layer 164a, an oxide semiconductor layer 164b, and an oxide semiconductor layer 164c laminated in this order.

[0193] Among the oxide semiconductor layer 164a, the oxide semiconductor layer 164b, and the oxide semiconductor layer 164c, the oxide semiconductor film of one aspect of the present invention can be applied to any one, or any two, or all of them.

[0194] For example, as the oxide semiconductor layer 164b, the same configuration as the oxide semiconductor layer 114 a exemplified in the above Modification 1 can be used. Also, for example, as the oxide semiconductor layers 164a and 164c, the same configuration as the oxide semiconductor layer 114b exemplified in the above Modification 1 can be used.

[0195] For example, by using an oxide with a high Ga content that functions as a stabilizer in the oxide semiconductor layers 164a and 164c, the release of oxygen from the oxide semiconductor layer 164a, the oxide semiconductor layer 164b, and the oxide semiconductor layer 164c can be suppressed.

[0196] When forming the oxide semiconductor layer 164, an oxide semiconductor film that is processed by etching the oxide semiconductor layer 164c and the oxide semiconductor layer 164b to become the oxide semiconductor layer 164a is exposed, and then the oxide semiconductor film is processed by a dry etching method to form the oxide semiconductor layer 164a. In this case, the reaction product of the oxide semiconductor film may reattach to the side surfaces of the oxide semiconductor layer 16 4b and the oxide semiconductor layer 164c, and a sidewall protection layer (also called a rabbit ear) may be formed. Note that the reaction product is caused by a sputtering phenomenon. ​​​​​In addition to reattachment, reattachment may also occur during dry etching.

[0197] FIG. 11(C) shows a schematic cross-sectional view of the transistor 161 when the sidewall protection layer 164d is formed on the side surface of the oxide semiconductor layer 164 as described above. In the transistor 161, the other configurations are the same as those of the transistor 160.

[0198] The sidewall protection layer 164d mainly contains the same material as the oxide semiconductor layer 164a. Further, the sidewall protection layer 164d may contain components (for example, silicon) of the layer (here, the insulating layer 151) provided under the oxide semiconductor layer 164a.

[0199] Also, as shown in FIG. 11(C), by covering the side surface of the oxide semiconductor layer 164b with the sidewall protection layer 164d and making it not in contact with the pair of electrodes 105a and 105b, particularly when a channel is mainly formed in the oxide semiconductor layer 164b, an unintended leakage current when the transistor is off can be suppressed, and a transistor having excellent off characteristics can be realized. Further, by using a material having a high content of Ga that functions as a stabilizer as the sidewall protection layer 164d, the desorption of oxygen from the side surface of the oxide semiconductor layer 164b can be effectively suppressed, and a transistor having excellent electrical characteristic stability can be realized.

[0200] This embodiment can be implemented in appropriate combination with other embodiments described in this specification.

[0201] (Embodiment 3) In this embodiment, the configuration of the display panel according to one aspect of the present invention will be described with reference to FIG. 12.

[0202] ​​​​​​​​​​​ Figure 12(A) is a top view of a display panel according to an aspect of the present invention, and Figure 12(B) is a circuit diagram for explaining a pixel circuit that can be used when applying a liquid crystal element to a pixel of a display panel according to an aspect of the present invention. Further, Figure 12(C) is a circuit diagram for explaining a pixel circuit that can be used when applying an organic EL element to a pixel of a display panel according to an aspect of the present invention.

[0203] The transistor disposed in the pixel portion can be formed according to Embodiment 2. Further, since it is easy to make the transistor an n-channel type, a part of the drive circuit composed of n-channel type transistors is formed on the same substrate as the transistor in the pixel portion. In this way, by using the transistors shown in Embodiment 2 in the pixel portion and the drive circuit, a highly reliable display device can be provided.

[0204] An example of a block diagram of an active matrix type display device is shown in Figure 12(A). On the substrate 500 of the display device, there are a pixel portion 501, a first scan line drive circuit 502, a second scan line drive circuit 503, and a signal line drive circuit 504. A plurality of signal lines extend from the signal line drive circuit 504 and are arranged in the pixel portion 501, and a plurality of scan lines extend from the first scan line drive circuit 502 and the scan line drive circuit 503 and are arranged. In the intersection region of the scan line and the signal line, pixels each having a display element are provided in a matrix. Further, the substrate 500 of the display device is connected to a timing control circuit (also referred to as a controller or a control IC) via a connection portion such as an FPC (Flexible Printed Circuit).

[0205] ​​​​In FIG. 12(A), the first scanning line driving circuit 502, the second scanning line driving circuit 503, and the signal line driving circuit 504 are formed on the same substrate 500 as the pixel portion 501. Therefore, the number of components such as driving circuits provided externally can be reduced, and the cost can be reduced. Also, when a driving circuit is provided outside the substrate 500, it is necessary to extend the wiring, so the number of connections between the wirings increases. However, by providing the driving circuit on the same substrate 500, the number of connections between the wirings can be reduced. Thus, the reliability or the yield of the semiconductor device can be improved.

[0206] <Liquid crystal panel> Also, an example of the circuit configuration of the pixel is shown in FIG. 12(B). Here, a pixel circuit applicable to the pixels of the VA type liquid crystal display panel is shown.

[0207] This pixel circuit can be applied to a configuration having a plurality of pixel electrode layers in one pixel. Each pixel electrode layer is connected to a different transistor, and each transistor is configured to be driven by a different gate signal. Thus, the signals applied to the individual pixel electrode layers of the pixels designed in a multi-domain can be controlled independently.

[0208] The gate wiring 512 of the transistor 516 and the gate wiring 513 of the transistor 517 are separated so that different gate signals can be applied thereto. On the other hand, the source electrode layer or the drain electrode layer 514 functioning as a data line is commonly used by the transistor 516 and the transistor 517. The transistor 516 and the transistor 517 can appropriately use the transistors described in the second embodiment. Thus, a highly reliable liquid crystal display panel can be provided. ​

[0209] The shape of the first pixel electrode layer electrically connected to the transistor 516 and the second pixel electrode layer electrically connected to the transistor 517 will be described. The shapes of the first pixel electrode layer and the second pixel electrode layer are separated by a slit. The first pixel electrode layer has a shape that spreads in a V shape and the second pixel electrode layer is formed so as to surround the outside of the first pixel electrode layer.

[0210] The gate electrode of the transistor 516 is connected to the gate wiring 512, and the gate electrode of the transistor 517 is connected to the gate wiring 513. Different gate signals are applied to the gate wiring 512 and the gate wiring 513 to make the operation timings of the transistor 516 and the transistor 517 different, and the liquid crystal alignment can be controlled.

[0211] Also, a holding capacitor may be formed by the capacitance wiring 510, the gate insulating film functioning as a dielectric, and the capacitance electrode electrically connected to the first pixel electrode layer or also the second pixel electrode layer.

[0212] The multi-domain structure includes a first liquid crystal element 518 and a second liquid crystal element 519 in one pixel. The first liquid crystal element 518 is composed of the first pixel electrode layer, the counter electrode layer, and the liquid crystal layer therebetween. The second liquid crystal element 519 is composed of the second pixel electrode layer, the counter electrode layer, and the liquid crystal layer therebetween.

[0213] Note that the pixel circuit shown in FIG. 12(B) is not limited to this. For example, a new switch, resistor element, capacitor element, transistor, sensor, or logic circuit may be added to the pixel shown in FIG. 12(B).

[0214] <Organic EL panel> Another example of the circuit configuration of a pixel is shown in FIG. 12(C). Here, an organic EL element is used to show the pixel structure of the display panel.

[0215] When a voltage is applied to the light-emitting element, electrons are injected from one of the pair of electrodes into the layer containing the light-emitting organic compound, and holes are injected from the other, and a current flows. Then when the electrons and holes recombine, the light-emitting organic compound forms an excited state, and light is emitted when the excited state returns to the ground state. Due to such a mechanism, such a light-emitting element is called a current-excited light-emitting element. element is called a current-excited light-emitting element. element is called a current-excited light-emitting element.

[0216] FIG. 12(C) is a diagram showing an example of an applicable pixel circuit. Here, an example of using two n-channel transistors in one pixel is shown. Note that the metal oxide film of one aspect of the present invention can be used for the channel formation region of an n-channel transistor. Also, the pixel circuit can apply digital time-division driving. circuit can apply digital time-division driving.

[0217] The configuration of the applicable pixel circuit and the operation of the pixel when digital time-division driving is applied will be described. will be described.

[0218] Pixel 520 has a switching transistor 521, a driving transistor 522, a light-emitting element 524, and a capacitive element 523. The switching transistor 521 has a gate electrode layer connected to the scanning line 526, a first electrode (one of the source electrode layer and the drain electrode layer ) connected to the signal line 525, and a second electrode (the other of the source electrode layer and the drain electrode layer) connected to the gate electrode layer of the driving transistor 522. The driving transistor 522 , the gate electrode layer is connected to the power line 527 via the capacitor element 523, the first electrode is connected to the power line 5 27, and the second electrode is connected to the first electrode (pixel electrode) of the light emitting element 524. The second electrode of the light emitting element 524 corresponds to the common electrode 528. The common electrode 528 is electrically connected to the common potential line formed on the same substrate .

[0219] As the switching transistor 521 and the driving transistor 522, the transistors described in Embodiment 2 can be appropriately used. Thereby, a highly reliable organic EL display panel can be provided.

[0220] The potential of the second electrode (common electrode 528) of the light emitting element 524 is set to a low power supply potential. Note that the low power supply potential is a potential lower than the high power supply potential set for the power line 527, and for example, GND [[ID=2I]] , 0V, etc. can be set as the low power supply potential. The high power supply potential and the low power supply potential are set so that the forward threshold voltage of the light emitting element 524 is reached or exceeded, and the potential difference is applied to the light emitting element 524 to cause a current to flow through the light emitting element 524 and emit light. Note that the forward voltage of the light emitting element 52 4 refers to the voltage when a desired luminance is obtained, and is at least greater than the forward threshold voltage.

[0221] Note that the capacitor element 523 can be omitted by substituting the gate capacitance of the driving transistor 522. Regarding the gate capacitance of the driving transistor 522, a capacitance may be formed between the channel formation region and the gate electrode layer.

[0222] Next, the signal input to the driving transistor 522 will be described. Voltage input voltage drive method In the case of the formula, the driving transistor 522 has two states: being surely turned on or turned off, and a video signal is input to the driving transistor 522. Note that, in order to operate the driving transistor 522 in the linear region, a voltage higher than the voltage of the power supply line 527 is applied to the gate electrode layer of the driving transistor 522. Also, a voltage equal to or higher than the value obtained by adding the threshold voltage Vth of the driving transistor 522 to the power supply line voltage is applied to the signal line 525. A video signal that causes such a state is input to the driving transistor 522. Note that, in order to operate the driving transistor 522 in the linear region, a voltage higher than the voltage of the power supply line 527 is applied to the gate electrode layer of the driving transistor 522. Also, a voltage equal to or higher than the value obtained by adding the threshold voltage Vth of the driving transistor 522 to the power supply line voltage is applied to the signal line 525. When performing analog gradation driving, a voltage equal to or higher than the value obtained by adding the threshold voltage Vth of the driving transistor 522 to the forward voltage of the light emitting element 524 is applied to the gate electrode layer of the driving transistor 522. Note that a video signal is input so that the driving transistor 522 operates in the saturation region, and a current is caused to flow through the light emitting element 524. Also, in order to operate the driving transistor 522 in the saturation region, the potential of the power supply line 527 is made higher than the gate potential of the driving transistor 522. By using an analog video signal, a current corresponding to the video signal can be caused to flow through the light emitting element 524, and analog gradation driving can be performed. When performing analog gradation driving, a voltage equal to or higher than the value obtained by adding the threshold voltage Vth of the driving transistor 522 to the forward voltage of the light emitting element 524 is applied to the gate electrode layer of the driving transistor 522. Note that a video signal is input so that the driving transistor 522 operates in the saturation region, and a current is caused to flow through the light emitting element 524. Also, in order to operate the driving transistor 522 in the saturation region, the potential of the power supply line 527 is made higher than the gate potential of the driving transistor 522. By using an analog video signal, a current corresponding to the video signal can be caused to flow through the light emitting element 524, and analog gradation driving can be performed. When performing analog gradation driving, a voltage equal to or higher than the value obtained by adding the threshold voltage Vth of the driving transistor 522 to the forward voltage of the light emitting element 524 is applied to the gate electrode layer of the driving transistor 522. Note that a video signal is input so that the driving transistor 522 operates in the saturation region, and a current is caused to flow through the light emitting element 524. Also, in order to operate the driving transistor 522 in the saturation region, the potential of the power supply line 527 is made higher than the gate potential of the driving transistor 522. By using an analog video signal, a current corresponding to the video signal can be caused to flow through the light emitting element 524, and analog gradation driving can be performed.

[0223] When performing analog gradation driving, a voltage equal to or higher than the value obtained by adding the threshold voltage Vth of the driving transistor 522 to the forward voltage of the light emitting element 524 is applied to the gate electrode layer of the driving transistor 522. Note that a video signal is input so that the driving transistor 522 operates in the saturation region, and a current is caused to flow through the light emitting element 524. Also, in order to operate the driving transistor 522 in the saturation region, the potential of the power supply line 527 is made higher than the gate potential of the driving transistor 522. By using an analog video signal, a current corresponding to the video signal can be caused to flow through the light emitting element 524, and analog gradation driving can be performed. When performing analog gradation driving, a voltage equal to or higher than the value obtained by adding the threshold voltage Vth of the driving transistor 522 to the forward voltage of the light emitting element 524 is applied to the gate electrode layer of the driving transistor 522. Note that a video signal is input so that the driving transistor 522 operates in the saturation region, and a current is caused to flow through the light emitting element 524. Also, in order to operate the driving transistor 522 in the saturation region, the potential of the power supply line 527 is made higher than the gate potential of the driving transistor 522. By using an analog video signal, a current corresponding to the video signal can be caused to flow through the light emitting element 524, and analog gradation driving can be performed. When performing analog gradation driving, a voltage equal to or higher than the value obtained by adding the threshold voltage Vth of the driving transistor 522 to the forward voltage of the light emitting element 524 is applied to the gate electrode layer of the driving transistor 522. Note that a video signal is input so that the driving transistor 522 operates in the saturation region, and a current is caused to flow through the light emitting element 524. Also, in order to operate the driving transistor 522 in the saturation region, the potential of the power supply line 527 is made higher than the gate potential of the driving transistor 522. By using an analog video signal, a current corresponding to the video signal can be caused to flow through the light emitting element 524, and analog gradation driving can be performed. When performing analog gradation driving, a voltage equal to or higher than the value obtained by adding the threshold voltage Vth of the driving transistor 522 to the forward voltage of the light emitting element 524 is applied to the gate electrode layer of the driving transistor 522. Note that a video signal is input so that the driving transistor 522 operates in the saturation region, and a current is caused to flow through the light emitting element 524. Also, in order to operate the driving transistor 522 in the saturation region, the potential of the power supply line 527 is made higher than the gate potential of the driving transistor 522. By using an analog video signal, a current corresponding to the video signal can be caused to flow through the light emitting element 524, and analog gradation driving can be performed. When performing analog gradation driving, a voltage equal to or higher than the value obtained by adding the threshold voltage Vth of the driving transistor 522 to the forward voltage of the light emitting element 524 is applied to the gate electrode layer of the driving transistor 522. Note that a video signal is input so that the driving transistor 522 operates in the saturation region, and a current is caused to flow through the light emitting element 524. Also, in order to operate the driving transistor 522 in the saturation region, the potential of the power supply line 527 is made higher than the gate potential of the driving transistor 522. By using an analog video signal, a current corresponding to the video signal can be caused to flow through the light emitting element 524, and analog gradation driving can be performed. When performing analog gradation driving, a voltage equal to or higher than the value obtained by adding the threshold voltage Vth of the driving transistor 522 to the forward voltage of the light emitting element 524 is applied to the gate electrode layer of the driving transistor 522. Note that a video signal is input so that the driving transistor 522 operates in the saturation region, and a current is caused to flow through the light emitting element 524. Also, in order to operate the driving transistor 522 in the saturation region, the potential of the power supply line 527 is made higher than the gate potential of the driving transistor 522. By using an analog video signal, a current corresponding to the video signal can be caused to flow through the light emitting element 524, and analog gradation driving can be performed. When performing analog gradation driving, a voltage equal to or higher than the value obtained by adding the threshold voltage Vth of the driving transistor 522 to the forward voltage of the light emitting element 524 is applied to the gate electrode layer of the driving transistor 522. Note that a video signal is input so that the driving transistor 522 operates in the saturation region, and a current is caused to flow through the light emitting element 524. Also, in order to operate the driving transistor 522 in the saturation region, the potential of the power supply line 527 is made higher than the gate potential of the driving transistor 522. By using an analog video signal, a current corresponding to the video signal can be caused to flow through the light emitting element 524, and analog gradation driving can be performed.

[0224] Note that the configuration of the pixel circuit is not limited to the pixel configuration shown in Fig. 12(C). For example, a switch, a resistance element, a capacitance element, a sensor, a transistor, or a logic circuit, etc. may be added to the pixel circuit shown in Fig. 12(C). (Embodiment 4) In this embodiment, the configuration of a semiconductor device and an electronic device using a metal oxide film of an aspect of the present invention will be described with reference to Figs. 13 and 14.

[0225] (Embodiment 4) In this embodiment, the configuration of a semiconductor device and an electronic device using a metal oxide film of an aspect of the present invention will be described with reference to Figs. 13 and 14. In this embodiment, the configuration of a semiconductor device and an electronic device using a metal oxide film of an aspect of the present invention will be described with reference to Figs. 13 and 14.

[0226] Fig. 13 is a block diagram of an electronic device including a semiconductor device to which a metal oxide film of an aspect of the present invention is applied. It is a block diagram.

[0227] FIG. 14 is an external view of an electronic device including a semiconductor device to which a metal oxide film according to an aspect of the present invention is applied. It is.

[0228] The electronic device shown in FIG. 13 includes an RF circuit 901, an analog baseband circuit 902, a digital base band circuit 903, a battery 904, a power supply circuit 905, an application processor 906, a flash memory 910, a display controller 911, a memory circuit 91 2, a display 913, a touch sensor 919, an audio circuit 917, a keyboard 918, etc. It is composed of.

[0229] The application processor 906 has a CPU 907, a DSP 908, and an interface ( IF) 909. The memory circuit 912 can be composed of SRAM or DRAM. It can be.

[0230] By applying the transistor described in Embodiment 2 to the memory circuit 912, it is possible to provide a highly reliable electronic device capable of writing and reading information. It can be.

[0231] Also, by applying the transistor described in Embodiment 2 to a register or the like included in the CPU 907 or the DSP 908, it is possible to provide a highly reliable electronic device capable of writing and reading information. It can be. It can be.

[0232] When the off-leakage current of the transistor described in Embodiment 2 is extremely small, it is possible to provide a memory circuit 912 capable of long-term storage retention and with sufficiently reduced power consumption. It can be. During the power gating period, the state before power gating is registered. A CPU 907 or DSP 908 may be provided, which may store the data in a memory or the like.

[0233] The display 913 includes a display unit 914, a source driver 915, a gate driver 91 It consists of 6.

[0234] The display unit 914 has a plurality of pixels arranged in a matrix. Each pixel includes a pixel circuit. The pixel circuit is electrically connected to a gate driver 916 .

[0235] The transistor described in Embodiment 2 is used as appropriate in the pixel circuit or the gate driver 916. This makes it possible to provide a highly reliable display.

[0236] Examples of electronic devices include television sets (also known as televisions or television receivers). (hereinafter referred to as "computer monitors"), cameras such as digital cameras and digital video cameras digital photo frames, mobile phones (also called mobile phones or mobile phone devices), portable Examples include game machines, mobile information terminals, sound reproduction devices, and large game machines such as pachinko machines. do.

[0237] FIG. 14A shows a portable information terminal, which includes a main body 1001, a housing 1002, a display unit 100 The display unit 1003b is a touch panel. The screen can be operated by touching keyboard buttons 1004 displayed on the display unit 1003b. Of course, the display unit 1003a can be configured as a touch panel. The transistor described in Embodiment 2 may be used as a switching element in a liquid crystal panel or By manufacturing an organic light-emitting panel and applying it to the display units 1003a and 1003b, a highly reliable portable information terminal can be obtained.

[0238] The portable information terminal shown in Fig. 14(A) can have functions such as displaying various information (still images, moving images, text images, etc. ), displaying a calendar, date, or time on the display unit, operating or editing the information shown on the display unit, controlling processing by various software (programs), etc. Further, on the back or side of the housing, external connection terminals ( earphone terminals, USB terminals, etc.), a recording medium insertion part, etc. may be provided.

[0239] Also, the portable information terminal shown in Fig. 14(A) may be configured to be able to wirelessly transmit and receive information. By wirelessly purchasing and downloading desired book data, etc. from an e-book server, it is also possible to configure it in this way.

[0240] Fig. 14(B) shows a portable music player. The main body 1021 is provided with a display unit 1023, a fixing part 1022 for wearing on the ear, a speaker, operation buttons 1024, an external memory slot 1025, etc. By manufacturing a liquid crystal panel or an organic light-emitting panel using the transistor shown in Embodiment 2 as a switching element and applying it to the display unit 1023, a more reliable portable music player can be obtained.

[0241] Furthermore, if the portable music player shown in Fig. 14(B) is equipped with an antenna, a microphone function, and a wireless function and is linked with a mobile phone, it is possible to have a hands-free conversation wirelessly while driving a vehicle, etc.

[0242] FIG. 14C shows a mobile phone, which is composed of two housings, a housing 1030 and a housing 1031. The housing 1031 is provided with a display panel 1032, a speaker 1033, a microphone, and the like. 1034, pointing device 1036, camera lens 1037, external connection terminal The housing 1030 also includes a solar cell for charging the mobile phone. The housing 10 is provided with an antenna. The transistor described in Embodiment 2 is built in the display panel 1032. By applying this technology, a highly reliable mobile phone can be achieved.

[0243] The display panel 1032 is also equipped with a touch panel, and the image displayed on the display panel 1032 is shown in FIG. The operation keys 1035 are indicated by dotted lines. It also has a boost circuit to boost the voltage required for each circuit.

[0244] For example, the power transistor used in a power supply circuit such as a booster circuit is also described in the second embodiment. The metal oxide film of the transistor is formed to have a thickness of 2 μm or more and 50 μm or less. It is possible.

[0245] The display direction of the display panel 1032 changes appropriately depending on the usage mode. The camera lens 1037 is located on the same surface as the camera 1032, so video calls are possible. The speaker 1033 and microphone 1034 are not limited to voice calls, but also to video calls, Recording and playback are possible. Furthermore, the housing 1030 and the housing 1031 can be slid apart. As shown in 14(C), it can be folded from the unfolded state to the overlapped state, making it suitable for carrying. miniaturization can be achieved.

[0246] The external connection terminal 1038 can be connected to various cables such as an AC adapter and a USB cable and is capable of charging and data communication with a personal computer or the like. Also, an external recording medium can be inserted into the external memory slot 1041 to support storage and transfer of a larger amount of data .

[0247] In addition to the above functions, it may also be equipped with an infrared communication function, a television receiving function, etc. That's fine.

[0248] FIG. 14(D) shows an example of a television apparatus. The television apparatus 1050 has a display unit 1053 incorporated in a housing 1051. The display unit 1053 can display images . Also, a CPU is built into a stand 1055 that supports the housing 1051 . By applying the transistor described in Embodiment 2 to the display unit 1053 and the CPU , a highly reliable television apparatus 1050 can be obtained.

[0249] The operation of the television apparatus 1050 can be performed by an operation switch provided on the housing 1051 or a separate remote control unit. Also, the remote control unit may be configured to be provided with a display unit for displaying information output from the remote control unit .

[0250] Note that the television apparatus 1050 is configured to include a receiver, a modem, etc. The receiver can receive more common television broadcasts, and further, by connecting to a communication network by wire or wirelessly via the modem , one-way (from sender to receiver) or two-way communication can be achieved. It is also possible to communicate information (between a sender and a receiver, or between receivers).

[0251] The television device 1050 also includes an external connection terminal 1054 and a storage medium playback / recording unit 10 52, an external memory slot. An external connection terminal 1054 is provided for connecting a USB cable or the like. It can be connected to various cables, enabling data communication with a personal computer, etc. The storage medium playback / recording unit 1052 receives a disc-shaped recording medium and records the data on the recording medium. It is possible to read data stored in the external memory and write data to the recording medium. Displays images and videos stored in the external memory 1056 inserted into the slot. It is also possible to display it on the display unit 1053.

[0252] In addition, when the off-leak current of the transistor described in Embodiment 2 is extremely small, By applying this transistor to the external memory 1056 or CPU, power consumption is sufficiently reduced. This results in a television device 1050 with reduced reliability. [Explanation of symbols]

[0253] 100 transistors 101 Substrate 102 gate electrode 103 Insulating layer 104 Oxide semiconductor layer 105a electrode 105b electrode 106 Insulating layer 107 Insulating layer 110 Transistor 114 Oxide semiconductor layer 114a Oxide semiconductor layer 114b Oxide semiconductor layer 120 transistors 124 Oxide semiconductor layer 124a Oxide semiconductor layer 124b Oxide semiconductor layer 124c Oxide semiconductor layer 150 Transistor 151 Insulating layer 152 Insulating layer 160 Transistor 161 Transistor 164 Oxide semiconductor layer 164a Oxide semiconductor layer 164b Oxide semiconductor layer 164c Oxide semiconductor layer 164d Sidewall protection layer 200 Quartz glass substrate 202Dummy substrate 204 Metal oxide film 210a Region 210b Region 500 Substrate 501 Pixel portion 502 Scanning line drive circuit 503 Scanning line drive circuit 504 Signal line drive circuit 510 Capacitance wiring 512 Gate wiring 513 Gate wiring 514 Drain electrode layer 516 Transistor 517 Transistor 518 Liquid crystal element 519 Liquid crystal element 520 Pixel 521 Switching transistor 522 Driving transistor 523 Capacitance element 524 Light emitting element 525 Signal line 526 Scanning line 527 Power supply line 528 Common electrode 901 RF circuit 902 Analog baseband circuit 903 Digital baseband circuit 904 Battery 905 Power circuit 906 Application processor 907 CPU 908 DSP 910 Flash memory 911 Display controller 912 Memory circuit 913 Display 914 Display section 915 Source driver 916 Gate driver 917 Audio circuit 918 Keyboard 919 Touch sensor 1001 Main body 1002 Housing 1003a Display section 1003b Display section 1004 Keyboard button 1021 Main body 1022 Fixing part 1023 Display section 1024 Operation button 1025 External memory slot 1030 Housing 1031 Housing 1032 Display panel 1033 Speaker 1034 Microphone 1035 Operation key 1036 Pointing device 1037 Camera lens 1038 External connection terminal 1040 Solar cell 1041 External memory slot 1050 Television apparatus 1051 Housing 1052 Recording and playback unit for storage medium 1053 Display section 1054 External connection terminal 1055 Stand 1056 External memory

Claims

1. A display device having a plurality of pixels arranged in a matrix, wherein at least one of the pixels has a transistor and a liquid crystal element electrically connected to the transistor, and has a region in contact with an insulating surface and has a first conductive layer functioning as a gate electrode of the transistor, a first insulating film having a region located above the first conductive layer, an oxide semiconductor layer having a region located above the first insulating film and having a channel formation region of the transistor, a second conductive layer having a region in contact with the oxide semiconductor layer and functioning as a source electrode or a drain electrode of the transistor, and a second insulating film having a region located above the oxide semiconductor layer, wherein the oxide semiconductor layer shows a plurality of circumferentially arranged spots different from a plurality of circumferentially arranged spots having regularity of crystals oriented on a specific plane in a nano-beam electron diffraction pattern, the first insulating film contains silicon oxide, and the second insulating film contains silicon oxide.

2. A display device having a plurality of pixels arranged in a matrix, wherein at least one of the pixels has a transistor and a liquid crystal element electrically connected to the transistor, and has a region in contact with an insulating surface and has a first conductive layer functioning as a gate electrode of the transistor, a first insulating film having a region located above the first conductive layer, an oxide semiconductor layer having a region located above the first insulating film and having a channel formation region of the transistor, a second conductive layer having a region in contact with the oxide semiconductor layer and functioning as a source electrode or a drain electrode of the transistor, and a second insulating film having a region located above the oxide semiconductor layer, wherein the oxide semiconductor layer shows a plurality of circumferentially arranged spots different from a plurality of circumferentially arranged spots having regularity of crystals oriented on a specific plane in a nano-beam electron diffraction pattern, the first insulating film contains silicon oxide, the second insulating film contains silicon oxide, and a nano-beam electron diffraction pattern before irradiating the oxide semiconductor layer with an electron beam converging to 1 nmφ is the same as a nano-beam electron diffraction pattern after irradiating the oxide semiconductor layer with the electron beam for 1 minute.

3. In claim 1 or 2, The carbon concentration of the oxide semiconductor layer is less than 4 × 10 ２１ atoms / cm ３ , a display device.

4. In any one of claims 1 to 3, The hydrogen concentration of the oxide semiconductor layer is 1×10 ２２ atoms / cm ３ or less. A display device.

5. In any one of claims 1 to 4, The display device, wherein the nano-beam electron diffraction pattern is observed by irradiating an electron beam with a beam diameter of 1 nmφ.

6. In any one of claims 1 to 5, The oxide semiconductor layer has a plurality of crystals, The plane orientations of the plurality of crystals are irregular, The display device having a region where peaks due to the plurality of crystals are not observed in XRD measurement.

7. In claim 6, The display device, wherein each size of the plurality of crystals is 1 nm or more and 10 nm or less.

Images