Display device and display panel

Abstract

To provide a display device with a repair structure, and a display panel.SOLUTION: A display device according to embodiments of the present disclosure may include a first lower metal directly connected to a first pixel electrode or a first source electrode in a first sub-pixel to overlap with a first active layer, a second lower metal directly connected to a second pixel electrode or a second source electrode in a second sub-pixel to overlap with a second active layer, and an overlapping pattern having one side overlapping with at least a portion of the first lower metal and another side overlapping with at least a portion of the second lower metal.SELECTED DRAWING: Figure 8

Description

Technical Field

[0001] Embodiments of the present disclosure relate to a display device and a display panel.

Background Art

[0002] When manufacturing a display panel, due to various reasons such as the occurrence of foreign matters at various positions within a sub-pixel, a defect may occur in which the sub-pixel becomes a bright spot or a dark spot. For example, the driving transistors within each sub-pixel are manufactured through many processes, and at this time, fine process-induced foreign matters may occur in the driving transistors. Thus, if a foreign matter occurs in the driving transistor, a short-circuit or open phenomenon may occur due to the foreign matter. Due to such a phenomenon, the sub-pixel becomes a defective sub-pixel that cannot emit light normally, and the yield of the display panel may decrease.

Summary of the Invention

Problems to be Solved by the Invention

[0003] Embodiments of the present disclosure can provide a display device and a display panel having a repair structure capable of normalizing a sub-pixel when a defect occurs in the sub-pixel.

[0004] Embodiments of the present disclosure can provide a display device and a display panel having a repair structure with high repair performance or a high probability of repair success.

[0005] Embodiments of the present disclosure can provide a display device and a display panel having a repair structure that does not induce a decrease in aperture ratio.

[0006] Embodiments of the present disclosure can provide a display device and a display panel having a repair structure that does not occupy much space.

[0007] Embodiments of the present disclosure can provide a display device having a repair structure suitable for a high-resolution configuration.

Means for Solving the Problems

[0008] The display device according to an embodiment of the present disclosure includes a first driving transistor including a first active layer, a first drain electrode, and a first gate electrode; a first pixel electrode directly connected to a part of the first active layer or electrically connected to a part of the first active layer through an additional first source electrode; a second driving transistor including a second active layer, a second drain electrode, and a second gate electrode; a second pixel electrode directly connected to a part of the second active layer or electrically connected to a part of the second active layer through an additional second source electrode; a first lower metal directly connected to the first pixel electrode or directly connected to the first source electrode and overlapping the first active layer; a second lower metal directly connected to the second pixel electrode or directly connected to the second source electrode and overlapping the second active layer; a first buffer layer disposed on the first lower metal and the second lower metal; an overlapping pattern including a first part overlapping at least a part of the first lower metal, a second part overlapping at least a part of the second lower metal, and a third part between the first part and the second part; and a second buffer layer disposed on the overlapping pattern and under the first active layer and the second active layer.

[0009] The display panel according to an embodiment of the present disclosure may include a first sub-pixel including a first sub-pixel circuit and a first light-emitting element; a second sub-pixel including a second sub-pixel circuit and a second light-emitting element; a first lower metal connected to the first sub-pixel circuit; a second lower metal connected to the second sub-pixel circuit; an overlapping pattern including a first part overlapping a part of the first lower metal, a second part overlapping a part of the second lower metal, and a third part between the first part and the second part; and a first buffer layer disposed between the first lower metal and the second lower metal and the overlapping pattern.

Advantages of the Invention

[0010] According to an embodiment of the present disclosure, when a defect occurs in a subpixel, a display device and a display panel having a repair structure capable of normalizing the corresponding subpixel can be provided.

[0011] According to an embodiment of the present disclosure, a display device and a display panel having a repair structure that does not induce a decrease in aperture ratio can be provided.

[0012] According to an embodiment of the present disclosure, a display device and a display panel having a repair structure that does not occupy much space can be provided.

[0013] According to an embodiment of the present disclosure, a display device having a repair structure suitable for a high-resolution configuration can be provided.

[0014] According to an embodiment of the present disclosure, a display device and a display panel having a repair structure with high repair performance or a high probability of repair success can be provided. Also, the manufacturing cost can be reduced and the process can be optimized.

Brief Description of the Drawings

[0015] [Figure 1] It is a system configuration diagram of a display device according to an embodiment of the present disclosure. [Figure 2] It is an equivalent circuit of a subpixel of a display device according to an embodiment of the present disclosure. [Figure 3] It is a schematic plan view of a subpixel of a display device according to an embodiment of the present disclosure. [Figure 4] It is an equivalent circuit of first and second subpixels adjacent in the column direction in a display device according to an embodiment of the present disclosure. [Figure 5] It shows the symmetric structure of first and second subpixels adjacent in the column direction in a display device according to an embodiment of the present disclosure. [Figure 6] It shows the symmetric structure of first and second subpixels adjacent in the column direction in a display device according to an embodiment of the present disclosure. [Figure 7]This shows a situation where a defect has occurred in the second sub-pixel among the first and second sub-pixels adjacent to each other in the column direction in a display device according to an embodiment of the present disclosure. [Figure 8] This shows a repair structure of a display device according to an embodiment of the present disclosure. [Figure 9] This shows a repair structure of a display device according to an embodiment of the present disclosure. [Figure 10] This is a drawing showing a welding repair process in the case where a defect has occurred in a second sub-pixel circuit within the second sub-pixel among the first and second sub-pixels adjacent to each other in the column direction in a display device according to an embodiment of the present disclosure. [Figure 11] This is a drawing showing a welding repair process in the case where a defect has occurred in a second sub-pixel circuit within the second sub-pixel among the first and second sub-pixels adjacent to each other in the column direction in a display device according to an embodiment of the present disclosure. [Figure 12] This is an equivalent circuit in which a cutting point for disabling the second sub-pixel circuit within the second sub-pixel is shown in the case where a defect has occurred in the second sub-pixel circuit within the second sub-pixel among the first and second sub-pixels adjacent to each other in the column direction in a display device according to an embodiment of the present disclosure. [Figure 13] This shows the first to eighth sub-pixels in a display panel according to an embodiment of the present disclosure. [Figure 14] This is a plan view of the circuit group area in FIG. 13. [Figure 15] This is a plan view of a display panel according to an embodiment of the present disclosure. [Figure 16] This is an enlarged plan view of a partial area in FIG. 15. [Figure 17] This is a cross-sectional view taken along the line A-A' in FIG. 16. [Figure 18] This is a cross-sectional view of the first and second sub-pixels adjacent to each other in the column direction in a display device according to an embodiment of the present disclosure. [Figure 19] This is a plan view of a repaired display panel. [Figure 20] This is an enlarged plan view of a partial area in FIG. 15. [Figure 21]3 is a cross-sectional view of first and second sub-pixels adjacent to each other in a column direction in a display device according to an embodiment of the present disclosure. [Figure 22] FIG. 1 is a plan view of a display panel according to an embodiment of the present disclosure. [Figure 23] FIG. 23 is an enlarged plan view of a part of FIG. 22. [Figure 24] FIG. 24 is a cross-sectional view taken along the line BB' in FIG. 23. [Figure 25] 3 is a cross-sectional view of first and second sub-pixels adjacent to each other in a column direction in a display device according to an embodiment of the present disclosure. [Figure 26] FIG. 10 is a plan view of a display panel that has been repaired. [Figure 27] 10 is a diagram illustrating a current supply state after a repair process when a defect occurs in a second sub-pixel among first to fourth sub-pixels arranged in a column direction in a display panel according to an embodiment of the present disclosure. [Figure 28] 10 is a diagram illustrating a current supply state after a repair process when a defect occurs in a first subpixel among first to fourth subpixels arranged in a column direction in a display panel according to an embodiment of the present disclosure. DETAILED DESCRIPTION OF THE INVENTION

[0016] Some embodiments of the present invention will be described in detail below with reference to the accompanying drawings. When adding reference numerals to components in each drawing, the same components may be assigned the same numerals whenever possible, even if they are displayed in different drawings. Furthermore, when describing the present invention, if it is determined that a detailed description of related known structures or functions may obscure the gist of the present invention, such a detailed description may be omitted. When terms such as "include," "have," and "be made" are used in this specification, other terms may be added unless "only" is used. When a component is expressed in the singular, it may also include a plural unless otherwise expressly stated.

[0017] In addition, when describing the components of this embodiment, terms such as first, second, A, B, (a), (b), etc. can be used. Such terms are only for distinguishing the components from other components, and the essence, order, sequence, or number of the corresponding components are not limited by such terms.

[0018] In the description of the positional relationship of components, when two or more components are described as "connected", "coupled", or "connected", etc., two or more components can be directly "connected", "coupled", or "connected", but it should be understood that two or more components and different components can also be "interposed" and then "connected", "coupled", or "connected". Here, other components can be included in one or more of the two or more components that are "connected", "coupled", or "connected" to each other.

[0019] In the description of the time flow relationship related to components, operation methods, manufacturing methods, etc., for example, when the time sequence relationship or flow sequence relationship is described by "after ~", "subsequent to ~", "next to ~", "before ~", etc., it may include cases where it is not continuous unless "immediately" or "directly" is used.

[0020] On the other hand, when a numerical value or its corresponding information (e.g., level, etc.) for a component is mentioned, even without separate explicit description, the numerical value or its corresponding information can be interpreted as including the error range that can occur due to various factors (e.g., process factors, internal or external impacts, noise, etc.).

[0021] Hereinafter, various embodiments of the present disclosure will be described in detail with reference to the accompanying drawings.

[0022] FIG. 1 is a system configuration diagram of a display device 100 according to an embodiment of the present disclosure.

[0023] Referring to FIG. 1, a display device 100 according to an embodiment of the present disclosure may include a display panel 110 including a plurality of sub-pixels (SP), and a driving circuit for driving the plurality of sub-pixels (SP) included in the display panel 110.

[0024] The driving circuit includes a data driving circuit 120 and a gate driving circuit 130 , and may further include a controller 140 that controls the data driving circuit 120 and the gate driving circuit 130 .

[0025] The display panel 110 may include a substrate (SUB) and signal lines such as a plurality of data lines (DL) and a plurality of gate lines (GL) disposed on the substrate (SUB). The plurality of data lines (DL) and the plurality of gate lines (GL) may be connected to a plurality of sub-pixels (SP).

[0026] The display panel 110 may include a display area (DA) where an image is displayed and a non-display area (NDA) where an image is not displayed. In the display area (DA) of the display panel 110, a plurality of sub-pixels (SP) for displaying an image are arranged, and in the non-display area (NDA), the driver circuits 120, 130, and the controller 140 are electrically connected or the driver circuits 120, 130, and the controller 140 are mounted, and a pad unit to which an integrated circuit or a printed circuit is connected may be arranged.

[0027] The data driving circuit 120 is a circuit for driving a plurality of data lines (DL), and can supply data signals to the plurality of data lines (DL).

[0028] The gate driving circuit 130 is a circuit for driving a plurality of gate lines (GL) and can supply gate signals to the plurality of gate lines (GL).

[0029] The controller 140 can supply a data control signal (DCS) to the data driving circuit 120 to control the operation timing of the data driving circuit 120, and can supply a gate control signal (GCS) to the gate driving circuit 130 to control the operation timing of the gate driving circuit 130.

[0030] The controller 140 starts scanning according to the timing configured for each frame, converts the input image data input from the outside to match the data signal format used by the data driving circuit 120, supplies the converted image data (Data) to the data driving circuit 120, and controls data driving at an appropriate time in accordance with the scan.

[0031] The controller 140 receives various timing signals, including a vertical synchronization signal (VSYNC), a horizontal synchronization signal (HSYNC), an input data enable signal (DE), a clock signal (CLK), and the like, along with input video data from an external device (e.g., a host system 150).

[0032] In order to control the data driving circuit 120 and the gate driving circuit 130, the controller 140 receives timing signals such as a vertical synchronization signal (VSYNC), a horizontal synchronization signal (HSYNC), an input data enable signal (DE), and a clock signal (CLK), generates various control signals (DCS, GCS), and outputs them to the data driving circuit 120 and the gate driving circuit 130.

[0033] For example, the controller 140 outputs various gate control signals (GCS) including a gate start pulse (GSP), a gate shift clock (GSC), a gate output enable signal (GOE), etc. to control the gate driving circuit 130.

[0034] In addition, in order to control the data driving circuit 120, the controller 140 outputs various data control signals (DCS) including a source start pulse (SSP), a source sampling clock (SSC), a source output enable signal (SOE), etc.

[0035] The controller 140 can be composed of components separate from the data driving circuit 120, or can be integrated with the data driving circuit 120 to form an integrated circuit.

[0036] The data driving circuit 120 drives a plurality of data lines (DL) by receiving an input of video data (Data) from the controller 140 and supplying data voltages to the plurality of data lines (DL). Here, the data driving circuit 120 is also referred to as a source driving circuit.

[0037] The data driving circuit 120 may include one or more source driver integrated circuits (SDIC).

[0038] Each source driver integrated circuit (SDIC) can include a shift register, a latch circuit, a digital to analog converter (DAC), an output buffer, etc. Each source driver integrated circuit (SDIC) may further include an analog to digital converter (ADC) in some cases.

[0039] For example, each source driver integrated circuit (SDIC) can be connected to the display panel 110 by a tape automated bonding (TAB) method, or connected to a bonding pad of the display panel 110 by a chip on glass (COG) or chip on panel (COP) method, or configured by a chip on film (COF) method and connected to the display panel 110.

[0040] The gate driving circuit 130 can output a gate signal with a turn-on level voltage or a gate signal with a turn-off level voltage under the control of the controller 140. The gate driving circuit 130 can sequentially drive a plurality of gate lines (GL) by sequentially supplying gate signals with a turn-on level voltage to the plurality of gate lines (GL).

[0041] The gate driving circuit 130 can be connected to the display panel 110 by a tape automated bonding (TAB) method, or connected to a bonding pad of the display panel 110 by a chip on glass (COG) or chip on panel (COP) method, or connected to the display panel 110 according to a chip on film (COF) method. Alternatively, the gate driving circuit 130 can be formed in a non-display area (NDA) of the display panel 110 in a gate in panel (GIP, hereinafter may also be referred to as "GIP") type. The gate driving circuit 130 can be disposed on the substrate (SUB) or connected to the substrate (SUB). That is, the gate driving circuit 130 can be disposed in a non-display area (NDA) of the substrate (SUB) in the case of the GIP type. The gate driving circuit 130 can be connected to the substrate (SUB) in the case of a chip on glass (COG) type, a chip on film (COF) type, etc.

[0042] On the other hand, at least one of the data driving circuit 120 and the gate driving circuit 130 can also be arranged in the display area (DA). For example, at least one of the data driving circuit 120 and the gate driving circuit 130 can be arranged so as not to overlap with the sub-pixel (SP), and can be arranged so as to partially or entirely overlap with the sub-pixel (SP).

[0043] When the gate line (GL) selected by the gate driving circuit 130 is driven, the data driving circuit 120 can convert the video data (Data) received from the controller 140 into an analog data voltage and supply it to a plurality of data lines (DL).

[0044] The data driving circuit 120 may be connected to one side (e.g., the upper side or the lower side) of the display panel 110. Depending on the driving method, the panel design method, etc., the data driving circuit 120 may be connected to both sides (e.g., the upper side and the lower side) of the display panel 110, or may be connected to two or more sides among the four sides of the display panel 110.

[0045] The gate driving circuit 130 can be connected to one side (e.g., the left side or the right side) of the display panel 110. Depending on the gate driving method and the panel design method, etc., the gate driving circuit 130 may be connected to both sides (e.g., the left side and the right side) of the display panel 110, or may be connected to two or more sides among the four sides of the display panel 110.

[0046] The controller 140 can be a timing controller used in ordinary display technology, or a control device that includes a timing controller and can further perform other control functions, or it can be a control device different from the timing controller, or it can be a circuit within the control device. The controller 140 can be composed of various circuits and electronic components such as an IC (Integrated Circuit), FPGA (Field Programmable Gate Array), ASIC (Application Specific Integrated Circuit), or a processor (Processor).

[0047] The controller 140 is mounted on a printed circuit board, a flexible printed circuit, etc., and can be electrically connected to the data driving circuit 120 and the gate driving circuit 130 through the printed circuit board, the flexible printed circuit, etc.

[0048] The controller 140 can transmit and receive signals with the data driving circuit 120 through one or more predetermined interfaces. Here, for example, the interface can include an LVDS (Low Voltage Differential Signaling) interface, an EPI (Embedded Clock Point to Point Interface), an SPI (Serial Peripheral Interface), etc.

[0049] The controller 140 can include a storage medium such as one or more registers.

[0050] The display device 100 according to this embodiment can be a display including a backlight unit such as a liquid crystal display device, or it can be a self-emitting display such as an organic light-emitting display device, a quantum dot (Quantum Dot) display device, or an inorganic light-emitting display device.

[0051] When the display device 100 according to this embodiment is an organic light-emitting display device, each sub-pixel (SP) may include an organic light-emitting diode (OLED: Organic Light Emitting Diode) that emits light by itself as a light-emitting element.

[0052] When the display device 100 according to this embodiment is a quantum dot display device, each sub-pixel (SP) may include a light-emitting element made of quantum dots, which are semiconductor determiners that emit light by themselves.

[0053] When the display device 100 according to this embodiment is an inorganic light-emitting display device, each sub-pixel (SP) may include an inorganic light-emitting element that emits light by itself and is made of an inorganic substance on a substrate as a light-emitting element. For example, the inorganic light-emitting element is also referred to as a micro or nano unit light-emitting diode (LED: Light Emitting Diode), and the inorganic light-emitting display device is also referred to as a micro LED display device or a nano LED display device.

[0054] FIG. 2 is an equivalent circuit of a sub-pixel (SP) in the display panel 110 according to an embodiment of the present disclosure.

[0055] Referring to FIG. 2, each of the plurality of sub-pixels (SP) arranged in the display panel 110 according to an embodiment of the present disclosure may include a light-emitting element (ED) and a sub-pixel circuit (SPC) for driving the light-emitting element (ED).

[0056] The sub-pixel circuit (SPC) of each sub-pixel (SP) may include a driving transistor (DRT), a scan transistor (SCT), a sensing transistor (SENT), and a storage capacitor (Cst). In such a case, since the sub-pixel circuit (SPC) of each sub-pixel (SP) includes three transistors (DRT, SCT, SENT) and one capacitor (Cst), it can be said to have a 3T (Transistor) 1C (Capacitor) structure.

[0057] Referring to FIG. 2, the light-emitting element (ED) includes a pixel electrode (PE) and a common electrode (CE), and may include a light-emitting layer (EL) positioned between the pixel electrode (PE) and the common electrode (CE).

[0058] The pixel electrode (PE) is an electrode connected to a transistor such as a driving transistor (DRT), and may be an electrode arranged for each sub-pixel (SP). The common electrode (CE) may be an electrode to which a common voltage is applied, or may be an electrode commonly arranged for all sub-pixels (SP). For example, the common voltage may be a driving voltage (EVDD) which is a high-level common voltage or a base voltage (EVSS) which is a low-level common voltage.

[0059] When a base voltage (EVSS) is applied to the common electrode (CE), the common electrode (CE) may receive the supply of the base voltage (EVSS) through a base voltage line (BVL).

[0060] According to the illustration of FIG. 2, the pixel electrode (PE) may be an anode electrode, and the common electrode (CE) may be a cathode electrode. Alternatively, the pixel electrode (PE) may be a cathode electrode, and the common electrode (CE) may be an anode electrode.

[0061] For example, the light-emitting element (ED) may be an organic light-emitting diode (OLED), an inorganic-based light-emitting diode (LED), or a quantum dot light-emitting element, etc.

[0062] Referring to FIG. 2, the driving transistor (DRT) is a transistor for driving the light-emitting element (ED), and may include a first node (N1), a second node (N2), and a third node (N3), etc.

[0063] The first node (N1) of the driving transistor (DRT) is a source node or a drain node of the driving transistor (DRT), is electrically connected to the source node or the drain node of the sensing transistor (SENT), and may also be electrically connected to the pixel electrode (PE) of the light-emitting element (ED).

[0064] The second node (N2) of the drive transistor (DRT) is the gate node of the drive transistor (DRT) and can be electrically connected to the source node or the drain node of the scan transistor (SCT).

[0065] The third node (N3) of the drive transistor (DRT) can be electrically connected to a drive voltage line (DVL) that supplies a drive voltage (EVDD).

[0066] Referring to FIG. 2, the scan transistor (SCT) can be controlled by a scan signal (SC), which is a type of gate signal, and connected between the second node (N2) of the drive transistor (DRT) and the data line (DL). In other words, the scan transistor (SCT) can be turned on or off by the scan signal (SC) supplied from a scan signal line (SCL), which is a type of gate line, and control the connection between the data line (DL) and the second node (N2) of the drive transistor (DRT).

[0067] The scan transistor (SCT) can be turned on by a scan signal (SC) having a turn-on level voltage and transmit a data voltage (Vdata) supplied from the data line (DL) to the second node (N2) of the drive transistor (DRT).

[0068] Here, when the scan transistor (SCT) is an n-type transistor, the turn-on level voltage of the scan signal (SC) may be a high level voltage. When the scan transistor (SCT) is a p-type transistor, the turn-on level voltage of the scan signal (SC) may be a low level voltage. Hereinafter, an example in which the scan transistor (SCT) is an n-type transistor is given. Also, an example in which the turn-on level voltage is a high level voltage is given.

[0069] Referring to FIG. 2, the sensing transistor (SENT) can be controlled by a sensing signal (SE), which is a type of gate signal, and connected between the first node (N1) of the driving transistor (DRT) and the reference voltage line (RVL). In other words, the sensing transistor (SENT) is turned on or off by the sensing signal (SE) supplied from the sensing signal line (SENL), which is another type of gate line, and can control the connection between the reference voltage line (RVL) and the first node (N1) of the driving transistor (DRT).

[0070] The sensing transistor (SENT) can be turned on by the sensing signal (SE) having a turn-on level voltage and transmit the reference voltage (Vref) supplied from the reference voltage line (RVL) to the first node (N1) of the driving transistor (DRT). Here, the sensing signal (SE) can be a second scan signal different from the scan signal (SC).

[0071] Also, the sensing transistor (SENT) can be turned on by the sensing signal (SE) having a turn-on level voltage and transmit the voltage of the first node (N1) of the driving transistor (DRT) to the reference voltage line (RVL).

[0072] Here, when the sensing transistor (SENT) is an n-type transistor, the turn-on level voltage of the sensing signal (SE) can be a high level voltage. When the sensing transistor (SENT) is a p-type transistor, the turn-on level voltage of the sensing signal (SE) can be a low level voltage. Hereinafter, an example where the sensing transistor (SENT) is an n-type transistor will be given. Also, an example where the turn-on level voltage is a high level voltage will be given.

[0073] The function of the sensing transistor (SENT) to transfer the voltage of the first node (N1) of the driving transistor (DRT) to the reference voltage line (RVL) can be utilized during driving to sense the characteristic value of the sub-pixel (SP). In this case, the voltage transferred to the reference voltage line (RVL) can be a voltage for calculating the characteristic value of the sub-pixel (SP), or a voltage reflecting the characteristic value of the sub-pixel (SP).

[0074] In the present disclosure, the characteristic value of the sub-pixel (SP) can be the characteristic value of the driving transistor (DRT) or the light-emitting element (ED). For example, the characteristic value of the driving transistor (DRT) can include the threshold voltage and mobility of the driving transistor (DRT), etc. The characteristic value of the light-emitting element (ED) can include the threshold voltage of the light-emitting element (ED).

[0075] Referring to FIG. 2, the storage capacitor (Cst) can be connected between the second node (N2) and the first node (N1) of the driving transistor (DRT). The storage capacitor (Cst) is charged with the amount of charge corresponding to the voltage difference between both ends and can play a role in maintaining the voltage difference between both ends during a predetermined frame time. Thereby, during a determined frame time, the corresponding sub-pixel (SP) can emit light.

[0076] In this specification, the source node, drain node, and gate node of various transistors (DRT, SCT, SENT) are also described as the source electrode, drain electrode, and gate electrode.

[0077] Referring to FIG. 2, each of the driving transistor (DRT), the scan transistor (SCT), and the sensing transistor (SENT) can be an n-type transistor or a p-type transistor. In the present disclosure, for the convenience of explanation, an example is given where each of the driving transistor (DRT), the scan transistor (SCT), and the sensing transistor (SENT) is of the n-type.

[0078] The storage capacitor (Cst) is an external capacitor intentionally designed outside the driving transistor (DRT), rather than a parasitic capacitor such as the internal capacitor (e.g., Cgs, Cgd) existing between the gate node and the source node (or drain node) of the driving transistor (DRT).

[0079] The sub-pixel (SP) illustrated in FIG. 2 is merely an example and can be variously modified to further include one or more transistors or one or more capacitors.

[0080] Referring to FIG. 2, in one example, the gate node of the scan transistor (SCT) and the gate node of the sensing transistor (SENT) may not be connected. That is, the gate node of the scan transistor (SCT) and the gate node of the sensing transistor (SENT) can be connected to different gate lines (GLs) from each other.

[0081] In this case, the on-off of the scan transistor (SCT) and the on-off of the sensing transistor (SENT) can be independently controlled.

[0082] Referring to FIG. 2, in another example, the gate node of the scan transistor (SCT) and the gate node of the sensing transistor (SENT) can be electrically connected to each other. That is, the gate node of the scan transistor (SCT) and the gate node of the sensing transistor (SENT) can be commonly connected to one gate line (GL).

[0083] In this case, the on-off of the scan transistor (SCT) and the on-off of the sensing transistor (SENT) can be controlled together.

[0084] The display panel 110 according to the embodiment of the present disclosure may have a top emission structure in which light emitted from the light emitting element (ED) is emitted in a direction away from the substrate (SUB), or a bottom emission structure in which light emitted from the light emitting element (ED) is emitted in the direction of the substrate (SUB). For convenience of explanation, the following description will be given assuming that the display panel 110 according to the embodiment of the present disclosure has a bottom emission structure.

[0085] FIG. 3 is a schematic plan view of a sub-pixel (SP) of a display device 100 according to an embodiment of the present disclosure.

[0086] Referring to FIG. 3, each sub-pixel (SP) may include an emissive area (EA) and a sub-pixel circuit (SPC).

[0087] Referring to FIG. 3, a pixel electrode (PE) may be disposed in the light emitting area (EA).

[0088] Referring to FIG. 3, a portion of the pixel electrode (PE) may be extended to an area where the sub-pixel circuit (SPC) is disposed, and may be electrically connected to an electrode (e.g., source electrode or drain electrode) corresponding to the first node (N1) of the driving transistor (DRT) in the sub-pixel circuit (SPC) through a contact hole (CNT).

[0089] FIG. 4 is an equivalent circuit diagram of first and second sub-pixels (SP1, SP2) adjacent to each other in the column direction in a display device 100 according to an embodiment of the present disclosure.

[0090] Each of the first sub-pixel (SP1) and the second sub-pixel (SP2) has the same structure (equivalent circuit) as the sub-pixel (SP) in FIG.

[0091] The first sub-pixel SP1 and the second sub-pixel SP2 may be arranged adjacent to each other in a column direction, where the column direction may refer to the direction in which the data line DL extends.

[0092] The first sub-pixel (SP1) may include a first light-emitting element (ED1) and a first sub-pixel circuit (SPC1) for driving the same.

[0093] The first sub-pixel circuit (SPC1) may include a first driving transistor (DRT1), a first scan transistor (SCT1), a first sensing transistor (SENT1), and a first storage capacitor (Cst1).

[0094] The first driving transistor (DRT1) may include a first node (N1), a second node (N2), and a third node (N3). Hereinafter, for convenience of explanation, the first node (N1), the second node (N2), and the third node (N3) of the first driving transistor (DRT1) are referred to as a first source electrode (S1), a first gate electrode (G1), and a first drain electrode (D1).

[0095] The first scan transistor (SCT1) can control the connection between the data line (DL) and the first gate electrode (G1) of the first driving transistor (DRT1) by a first scan signal (SC1).

[0096] The first sensing transistor (SENT1) can control the connection between the reference voltage line (RLV) and the first source electrode (S1) of the first driving transistor (DRT1) by a first sensing signal (SE1).

[0097] The first storage capacitor (Cst1) may be formed between the first gate electrode (G1) and the first source electrode (S1) of the first driving transistor (DRT1).

[0098] The first light-emitting element (ED1) may include a first pixel electrode (PE1), a light-emitting layer (EL), and a common electrode (CE).

[0099] The second sub-pixel (SP2) may include a second light-emitting element (ED2) and a second sub-pixel circuit (SPC2) for driving the same.

[0100] The second sub-pixel circuit (SPC2) may include a second driving transistor (DRT2), a second scan transistor (SCT2), a second sensing transistor (SENT2), and a second storage capacitor (Cst2).

[0101] It may include a first node (N1), a second node (N2), and a third node (N3) of the second driving transistor (DRT2). Hereinafter, for convenience of explanation, the first node (N1), the second node (N2), and the third node (N3) of the second driving transistor (DRT2) are referred to as a second source electrode (S2), a second gate electrode (G2), and a second drain electrode (D2).

[0102] The second scan transistor (SCT2) can control the connection between the data line (DL) and the second gate electrode (G2) of the second driving transistor (DRT2) by a second scan signal (SC2).

[0103] The second sensing transistor (SENT2) can control the connection between the reference voltage line (RLV) and the second source electrode (S2) of the second driving transistor (DRT2) by a second sensing signal (SE2).

[0104] The second storage capacitor (Cst2) may be formed between the second gate electrode (G2) and the second source electrode (S2) of the second driving transistor (DRT2).

[0105] The second light-emitting element (ED2) may include a second pixel electrode (PE2), a light-emitting layer (EL), and a common electrode (CE).

[0106] On the other hand, when a defect occurs in the sub-pixel circuit (SPC) within the sub-pixel (SP) during the panel manufacturing process, the display device 100 according to an embodiment of the present disclosure can have a repair structure that can improve the aperture ratio while facilitating the repair for normalizing the defective sub-pixel (SP).

[0107] FIG. 5 and FIG. 6 show a symmetric structure of first and second sub-pixels (SP1, SP2) adjacent to each other in the column direction in the display device 100 according to an embodiment of the present disclosure. However, in the following description, FIG. 4 is also referred to together.

[0108] Referring to FIGS. 5 and 6, the first sub-pixel (SP1) and the second sub-pixel (SP2) can be arranged to be in contact with each other in the column direction.

[0109] The first sub-pixel (SP1) may include a first light-emitting region (EA1) and a first sub-pixel circuit (SPC1).

[0110] A first pixel electrode (PE1) is disposed in the first light-emitting region (EA1), and a part of the first pixel electrode (PE1) extends to a region where the first sub-pixel circuit (SPC1) is disposed and is electrically connected to a part (point) (for example, the first source electrode (S1) of the first driving transistor (DRT1)) in the first sub-pixel circuit (SPC1) through the first contact hole (CNT1).

[0111] The second sub-pixel (SP2) may include a second light-emitting region (EA2) and a second sub-pixel circuit (SPC2).

[0112] A second pixel electrode (PE2) is disposed in the second light-emitting region (EA2), and a part of the second pixel electrode (PE2) extends to a region where the second sub-pixel circuit (SPC2) is disposed and is electrically connected to a part (point) (for example, the second source electrode (S2) of the second driving transistor (DRT2)) in the second sub-pixel circuit (SPC2) through the second contact hole (CNT2).

[0113] Referring to FIGS. 5 and 6, the first sub-pixel (SP1) and the second sub-pixel (SP2) can have a symmetric structure with respect to each other based on the boundary between the first sub-pixel (SP1) and the second sub-pixel (SP2).

[0114] Referring to FIGS. 5 and 6, according to the symmetric structure of the first sub-pixel (SP1) and the second sub-pixel (SP2), the first sub-pixel circuit (SPC1) can be arranged closer to the second sub-pixel circuit (SPC3) among the second light-emitting region (EA2) and the second sub-pixel circuit (SPC2).

[0115] Referring to FIG. 6, according to the symmetric structure of the first sub-pixel (SP1) and the second sub-pixel (SP2), the first source electrode (S1) can be arranged closer to the second source electrode (S2) among the second source electrode (S2) and the second pixel electrode (PE2).

[0116] Referring to FIGS. 5 and 6, when the first sub-pixel (SP1) and the second sub-pixel (SP2) are both normal sub-pixels (SP), the first sub-pixel circuit (SPC1) can supply a first current (I1) to the first light-emitting element (ED1), and the second sub-pixel circuit (SPC2) can supply a second current (I2) to the second light-emitting element (ED2).

[0117] Accordingly, the first current (I1) can flow from the first source electrode (S1) of the first driving transistor (DRT1) to the first pixel electrode (PE1), and the second current (I2) can flow from the second source electrode (S2) of the second driving transistor (DRT2) to the second pixel electrode (PE2).

[0118] FIG. 7 shows a situation where a defect occurs in the second sub-pixel (SP2) among the first and second sub-pixels (SP1, SP2) adjacent in the column direction in the display device 100 according to an embodiment of the present disclosure. However, in the following description, FIGS. 4 to 6 are also referred to together.

[0119] Referring to FIG. 7, during the panel manufacturing process, a defect may occur in the second sub-pixel circuit (SPC2) within the second sub-pixel (SP2) among the first sub-pixel (SP1) and the second sub-pixel (SP2). In this case, the second sub-pixel (SP2) may not emit light normally, and a decrease in image quality may occur.

[0120] For example, a defect (e.g., a disconnection in the circuit) occurs in the second sub-pixel circuit (SPC2), and current is not supplied to the second light-emitting element (ED2) by the second sub-pixel circuit (SPC2), so the second light-emitting element (ED2) cannot emit light. In this case, the second sub-pixel (SP2) may appear as a dark spot, and an image abnormality phenomenon may occur.

[0121] For example, the defect occurring in the second sub-pixel circuit (SPC2) may be a defect in the second driving transistor (DRT2) within the second sub-pixel circuit (SPC2). For example, when at least one of the second source electrode (S2), the second drain electrode (D2), and the second gate electrode (G2) of the second driving transistor (DRT2) is cut by a foreign object or the like generated during the process, a defect in the second driving transistor (DRT2) may occur.

[0122] In this specification, a sub-pixel (SP) in which a defect has occurred is referred to as a defective sub-pixel, and a sub-pixel (SP) in which no defect has occurred is also referred to as a normal sub-pixel.

[0123] FIG. 8 shows the repair structure of the display device 100 according to an embodiment of the present disclosure, and FIG. 9 is a cross-sectional view taken along the line X-X' of FIG. 8. However, it is assumed that the first sub-pixel (SP1) and the second sub-pixel (SP2) shown in FIGS. 8 and 9 are normal sub-pixels, respectively.

[0124] Referring to FIG. 8, the first sub-pixel (SP1) includes a first pixel electrode (PE1) and a first source electrode (S1), and the second sub-pixel (SP2) includes a second pixel electrode (PE2) and a second source electrode (S2).

[0125] Each of the first source electrode (S1) and the second source electrode (S2) may be formed of a single metal layer. Alternatively, each of the first source electrode (S1) and the second source electrode (S2) may be formed of a plurality of metal layers. Alternatively, each of the first source electrode (S1) and the second source electrode (S2) may include a plurality of electrodes that are electrically connected to each other.

[0126] When the first sub-pixel (SP1) is a normal sub-pixel, a first current (I1) may flow from the first source electrode (S1) to the first pixel electrode (PE1). When the second sub-pixel (SP2) is a normal sub-pixel, a second current (I2) may flow from the second source electrode (S2) to the second pixel electrode (PE2).

[0127] Referring to FIGS. 8 and 9, the display device 100 according to an embodiment of the present disclosure may include a repair structure for repairing a defect when a defect occurs in either one of the first sub-pixel (SP1) and the second sub-pixel (SP2).

[0128] Referring to FIGS. 8 and 9, the repair structure of the display device 100 according to an embodiment of the present disclosure may include an overlapping pattern (OP) that overlaps at least one of the first source electrode (S1) and the second source electrode (S2) in a vertical direction.

[0129] Referring to FIGS. 8 and 9, the repair structure of the display device 100 according to an embodiment of the present disclosure may include a first lower metal (LM1) connected to the first source electrode (S1) and a second lower metal (LM2) connected to the second source electrode (S2).

[0130] Referring to FIGS. 8 and 9, the first lower metal (LM1) may be disposed within the region of the first sub-pixel (SP1), and the second lower metal (LM2) may be disposed within the region of the second sub-pixel (SP2).

[0131] In this case, as shown in FIG. 9, in one example, the overlapping pattern (OP) may include a first portion (PART1) that overlaps a part of the first lower metal (LM1), a second portion (PART2) that overlaps a part of the second lower metal (LM2), and a third portion (PART3) between the first portion (PART1) and the second portion (PART2).

[0132] Referring to FIG. 9, the first lower metal (LM1) and the second lower metal (LM2) are disposed on the substrate (SUB), and a first buffer layer (BUF1) is disposed on the first lower metal (LM1) and the second lower metal (LM2), and a superimposed pattern (OP) may be disposed on the first buffer layer (BUF1).

[0133] Therefore, the first lower metal (LM1) and the second lower metal (LM2) can be separated from the superimposed pattern (OP) by the first buffer layer (BUF1).

[0134] The first lower metal (LM1) and the second lower metal (LM2) may be formed of the lowest metal layer closest to the substrate (SUB) from the display panel 110. The superimposed pattern (OP) may be formed of the second lowest metal layer that is second closest to the substrate (SUB) in the display panel 110.

[0135] The first lower metal (LM1) may be superimposed on the first driving transistor (DRT1), and the second lower metal (LM2) may be superimposed on the second driving transistor (DRT2). For example, the first lower metal (LM1) may be superimposed on the first active layer (ACT1) of the first driving transistor (DRT1), and the second lower metal (LM2) may be superimposed on the second active layer (ACT2) of the second driving transistor (DRT2).

[0136] FIG. 10 shows a welding repair process in the second sub-pixel circuit (SPC2) in the second sub-pixel (SP2) among the first and second sub-pixels (SP1, SP2) adjacent in the column direction in the display device 100 according to an embodiment of the present disclosure when a defect occurs. FIG. 11 is a cross-sectional view taken along the line X-X' of FIG. 10.

[0137] Referring to FIGS. 10 and 11, the first lower metal (LM1) may be connected to the first source electrode (S1) of the first driving transistor (DRT1), and the second lower metal (LM2) may be connected to the first source electrode (S2) of the second driving transistor (DRT2).

[0138] Referring to FIGS. 10 and 11, before the welding repair process, not only are the first part (PART1) of the overlapping pattern (OP) and the first lower metal (LM1) separated from each other, but they can also be electrically separated from each other. The second part (PART2) of the overlapping pattern (OP) and the second lower metal (LM2) are not only separated from each other, but can also be electrically separated from each other.

[0139] Referring to FIGS. 10 and 11, when a fault occurs in the second sub-pixel circuit (SPC2) within the second sub-pixel (SP2) among the first and second adjacent sub-pixels (SP1, SP2) in the column direction, through laser welding, the first part (PART1) of the overlapping pattern (OP) and the first lower metal (LM1) can be electrically connected, and the second part (PART2) of the overlapping pattern (OP) and the second lower metal (LM2) can be electrically connected.

[0140] By laser welding, a first welding pattern (WPTN1) can be formed between the first part (PART1) of the overlapping pattern (OP) and the first lower metal (LM1), and a second welding pattern (WPTN2) can be formed between the second part (PART2) of the overlapping pattern (OP) and the second lower metal (LM2).

[0141] The first welding pattern (WPTN1) is formed by being welded to at least one of the first part (PART1) of the overlapping pattern (OP) and the first lower metal (LM1), or can be a pattern made of a material different from the first part (PART1) of the overlapping pattern (OP) and the first lower metal (LM1).

[0142] The second welding pattern (WPTN2) is formed by being welded to at least one of the second part (PART2) of the overlapping pattern (OP) and the second lower metal (LM2), or can be a pattern made of a material different from the second part (PART2) of the overlapping pattern (OP) and the second lower metal (LM2).

[0143] Accordingly, the first driving transistor (DRT1) can supply not only the first current (I1) to the first pixel electrode (PE1), but also the first current (I1) to the second pixel electrode (PE2). As a result, the first light-emitting element (ED1) of the first sub-pixel (SP1) can emit light, and the second light-emitting element (ED2) of the second sub-pixel (SP2) can emit light.

[0144] Even if a defect occurs in the second sub-pixel circuit (SPC2) of the second sub-pixel (SP2), the second light-emitting element (ED2) can emit light normally through the first driving transistor (DRT1) of the first sub-pixel (SP1), and the second sub-pixel (SP2) can operate normally.

[0145] FIG. 12 is an equivalent circuit showing cutting points (CP1, CP2, CP3) for disabling the second sub-pixel circuit (SPC2) in the second sub-pixel (SP2) when a defect occurs in the second sub-pixel circuit (SPC2) in the second sub-pixel (SP2) adjacent in the column direction among the first and second sub-pixels (SP1, SP2) according to an embodiment of the present disclosure in a display device 100.

[0146] Referring to FIG. 12, the display panel 110 according to an embodiment of the present disclosure may include a driving voltage line (DVL) that transmits a driving voltage (EVDD) to the first drain electrode (D1) of the first driving transistor (DRT1) and the second drain electrode (D2) of the second driving transistor (DRT2).

[0147] Referring to FIG. 12, a display panel 110 according to an embodiment of the present disclosure may include a data line (DL) for transmitting a data voltage (Vdata), a first scan transistor (SCT1) for controlling a connection between the data line (DL) and a first gate electrode (G1) of a first driving transistor (DRT1), and a second scan transistor (SCT2) for controlling a connection between the data line (DL) and a second gate electrode (G2) of a second driving transistor (DRT2).

[0148] Referring to FIG. 12, a display panel 110 according to an embodiment of the present disclosure may include a reference voltage line (RVL) for transmitting a reference voltage, a first sensing transistor (SENT1) for controlling a connection between the reference voltage line (RVL) and a first source electrode (S1) of a first driving transistor (DRT1), and a second sensing transistor (SENT2) for controlling a connection between the reference voltage line (RVL) and a second source electrode (S2) of a second driving transistor (DRT2).

[0149] Referring to FIG. 12, when a defect occurs in a second sub-pixel circuit (SPC2) within a second sub-pixel (SP2) among first and second sub-pixels (SP1, SP2) adjacent in the column direction, at least one of a driving voltage (EVDD), a data voltage (Vdata), and a reference voltage (Vref) needs not to be supplied to the second sub-pixel circuit (SPC2) in order to disable the second sub-pixel circuit (SPC2) within the second sub-pixel (SP2).

[0150] Referring to FIG. 12, cutting points for disabling the second sub-pixel circuit (SPC2) within the second sub-pixel (SP2) may include a first cutting point (CP1) for cutting off the supply of the driving voltage (EVDD), a second cutting point (CP2) for cutting off the supply of the data voltage (Vdata), and a third cutting point (CP3) for cutting off the supply of the reference voltage (Vref).

[0151] Referring to FIG. 12, the first cutting point (CP1) can be the connection point between the drive voltage line (DVL) and the second sub-pixel circuit (SPC2), the second cutting point (CP2) can be the connection point between the data line (DL) and the second sub-pixel circuit (SPC2), and the third cutting point (CP3) can be the connection point between the reference voltage line (RVL) and the second sub-pixel circuit (SPC2).

[0152] Referring to FIG. 12, when both the first sub-pixel circuit (SPC1) and the second sub-pixel circuit (SPC2) are normal, a first current (I1) can be supplied from the first drive transistor (DRT1) to the first pixel electrode (PE1), and a second current (I2) can be supplied from the second drive transistor (DRT2) to the second pixel electrode (PE2). At this time, the drive voltage line (DVL) and the first drain electrode (D1) can be electrically connected, and the drive voltage line (DVL) and the second drain electrode (D2) can be electrically connected.

[0153] Referring to FIG. 12, when the second sub-pixel circuit (SPC2) is defective among the first sub-pixel circuit (SPC1) and the second sub-pixel circuit (SPC2), a first current (I1) can be supplied from the first drive transistor (DRT1) to the first pixel electrode (PE1) and the second pixel electrode (PE2). At this time, the drive voltage line (DVL) and the first drain electrode (D1) can be electrically connected, and the drive voltage line (DVL) and the second drain electrode (D2) can be electrically disconnected.

[0154] Referring to FIG. 12, when both the first sub-pixel circuit (SPC1) and the second sub-pixel circuit (SPC2) are normal, a first current (I1) can be supplied from the first drive transistor (DRT1) to the first pixel electrode (PE1), and a second current (I2) can be supplied from the second drive transistor (DRT2) to the second pixel electrode (PE2). At this time, the data line (DL) and the first scan transistor (SCT1) can be connected, and the data line (DL) and the second scan transistor (SCT2) can be connected.

[0155] Referring to FIG. 12, when the second sub-pixel circuit (SPC2) is defective among the first sub-pixel circuit (SPC1) and the second sub-pixel circuit (SPC2), a first current (I1) can be supplied from the first driving transistor (DRT1) to the first pixel electrode (PE1) and the second pixel electrode (PE2). At this time, the data line (DL) and the first scan transistor (SCT1) can be connected, and the data line (DL) and the second scan transistor (SCT2) can be disconnected.

[0156] Referring to FIG. 12, when both the first sub-pixel circuit (SPC1) and the second sub-pixel circuit (SPC2) are normal, a first current (I1) can be supplied from the first driving transistor (DRT1) to the first pixel electrode (PE1), and a second current (I2) can be supplied from the second driving transistor (DRT2) to the second pixel electrode (PE2). At this time, the reference voltage line (RVL) and the first sensing transistor (SENT1) can be connected, and the reference voltage line (RVL) and the second sensing transistor (SENT2) can be connected.

[0157] Referring to FIG. 12, when the second sub-pixel circuit (SPC2) is defective among the first sub-pixel circuit (SPC1) and the second sub-pixel circuit (SPC2), a first current (I1) can be supplied from the first driving transistor (DRT1) to the first pixel electrode (PE1) and the second pixel electrode (PE2). At this time, the reference voltage line (RVL) and the first sensing transistor (SENT1) are connected, and the reference voltage line (RVL) and the second sensing transistor (SENT2) can be disconnected.

[0158] FIG. 13 shows the first to eighth sub-pixels (SP1 to SP8) in the display panel 110 according to an embodiment of the present disclosure. FIG. 14 is a plan view of the circuit group area 1500 in FIG. 13.

[0159] Referring to FIG. 13, the first sub-pixel (SP1), the third sub-pixel (SP3), the fifth sub-pixel (SP5), and the seventh sub-pixel (SP7) can be arranged in the first sub-pixel row (ROW1) and arrayed in the row direction. The second sub-pixel (SP2), the fourth sub-pixel (SP4), the sixth sub-pixel (SP6), and the eighth sub-pixel (SP8) can be arranged in the second sub-pixel row (ROW2) and arrayed in the row direction.

[0160] Referring to FIG. 13, the first sub-pixel (SP1) and the second sub-pixel (SP2) can be arranged in the first sub-pixel column (COL1) and arranged to be adjacent in the column direction. The third sub-pixel (SP3) and the fourth sub-pixel (SP4) can be arranged in the second sub-pixel column (COL2) and arranged to be adjacent in the column direction. The fifth sub-pixel (SP5) and the sixth sub-pixel (SP6) can be arranged in the third sub-pixel column (COL3) and arranged to be adjacent in the column direction. The seventh sub-pixel (SP7) and the eighth sub-pixel (SP8) can be arranged in the fourth sub-pixel column (COL4) and arranged to be adjacent in the column direction.

[0161] Referring to FIG. 13, the first sub-pixel (SP1) may include the first light-emitting region (EA1) and the first sub-pixel circuit (SPC1). The second sub-pixel (SP2) may include the second light-emitting region (EA2) and the second sub-pixel circuit (SPC2). The third sub-pixel (SP3) may include the third light-emitting region (EA3) and the third sub-pixel circuit (SPC3). The fourth sub-pixel (SP4) may include the fourth light-emitting region (EA4) and the fourth sub-pixel circuit (SPC4). The fifth sub-pixel (SP5) may include the fifth light-emitting region (EA5) and the fifth sub-pixel circuit (SPC5). The sixth sub-pixel (SP6) may include the sixth light-emitting region (EA6) and the sixth sub-pixel circuit (SPC6). The seventh sub-pixel (SP7) may include the seventh light-emitting region (EA7) and the seventh sub-pixel circuit (SPC7). The eighth sub-pixel (SP8) may include the eighth light-emitting region (EA8) and the eighth sub-pixel circuit (SPC8).

[0162] Referring to FIG. 13, the first sub-pixel (SP1) and the second sub-pixel (SP2) adjacent to each other in the column direction can have a structure that is symmetric with respect to the boundary. Accordingly, a first sub-pixel circuit (SPC1) and a second sub-pixel circuit (SPC2) are arranged between the first light-emitting region (EA1) and the second light-emitting region (EA2), and the first sub-pixel circuit (SPC1) and the second sub-pixel circuit (SPC2) can be arranged to be in contact with each other.

[0163] Referring to FIG. 13, the third sub-pixel (SP3) and the fourth sub-pixel (SP4) adjacent to each other in the column direction can have a structure that is symmetric with respect to the boundary. Accordingly, a third sub-pixel circuit (SPC3) and a fourth sub-pixel circuit (SPC4) are arranged between the third light-emitting region (EA3) and the fourth light-emitting region (EA4), and the third sub-pixel circuit (SPC3) and the fourth sub-pixel circuit (SPC4) can be arranged to be in contact with each other.

[0164] Referring to FIG. 13, the fifth sub-pixel (SP5) and the sixth sub-pixel (SP6) adjacent to each other in the column direction can have a structure that is symmetric with respect to the boundary. Accordingly, a fifth sub-pixel circuit (SPC5) and a sixth sub-pixel circuit (SPC6) are arranged between the fifth light-emitting region (EA5) and the sixth light-emitting region (EA6), and the fifth sub-pixel circuit (SPC5) and the sixth sub-pixel circuit (SPC6) can be arranged to be in contact with each other.

[0165] Referring to FIG. 13, the seventh sub-pixel (SP7) and the eighth sub-pixel (SP8) adjacent to each other in the column direction can have a structure that is symmetric with respect to the boundary. Accordingly, a seventh sub-pixel circuit (SPC7) and an eighth sub-pixel circuit (SPC8) are arranged between the seventh light-emitting region (EA7) and the eighth light-emitting region (EA8), and the seventh sub-pixel circuit (SPC7) and the eighth sub-pixel circuit (SPC8) can be arranged to be in contact with each other.

[0166] Hereinafter, the symmetric structure possessed by two adjacent sub-pixels (SP) in the column direction is referred to as an "up-down symmetric structure".

[0167] Referring to FIG. 13, FIG. 14 shows a schematic planar structure of a circuit group region 1500 where first to eighth sub-pixel circuits (SPC1 to SPC8) are gathered.

[0168] Referring to FIG. 14, the first sub-pixel circuit (SPC1) may include a first driving transistor (DRT1), a first scan transistor (SCT1), a first sensing transistor (SENT1), and a first storage capacitor (Cst1). The second sub-pixel circuit (SPC2) may include a second driving transistor (DRT2), a second scan transistor (SCT2), a second sensing transistor (SENT2), and a second storage capacitor (Cst2). The third sub-pixel circuit (SPC3) may include a third driving transistor (DRT3), a third scan transistor (SCT3), a third sensing transistor (SENT3), and a third storage capacitor (Cst3). The fourth sub-pixel circuit (SPC4) may include a fourth driving transistor (DRT4), a fourth scan transistor (SCT4), a fourth sensing transistor (SENT4), and a fourth storage capacitor (Cst4). The fifth sub-pixel circuit (SPC5) may include a fifth driving transistor (DRT5), a fifth scan transistor (SCT5), a fifth sensing transistor (SENT5), and a fifth storage capacitor (Cst5). The sixth sub-pixel circuit (SPC6) may include a sixth driving transistor (DRT6), a sixth scan transistor (SCT6), a sixth sensing transistor (SENT6), and a sixth storage capacitor (Cst6). The seventh sub-pixel circuit (SPC7) may include a seventh driving transistor (DRT7), a seventh scan transistor (SCT7), a seventh sensing transistor (SENT7), and a seventh storage capacitor (Cst7). The eighth sub-pixel circuit (SPC8) may include an eighth driving transistor (DRT8), an eighth scan transistor (SCT8), an eighth sensing transistor (SENT8), and an eighth storage capacitor (Cst8).

[0169] Referring to FIG. 14, the array structure of the column wirings (DL1 to DL4, DVL, RVL) will be described.

[0170] Referring to FIG. 14, the first data line (DL1) and the second data line (DL2) can be arranged between the first sub-pixel column (COL1) and the second sub-pixel column (COL2). The third data line (DL3) and the fourth data line (DL4) can be arranged between the third sub-pixel column (COL3) and the fourth sub-pixel column (COL4).

[0171] The first data line (DL1) can supply the first data voltage (Vdata1) to the first sub-pixel circuit (SPC1) and the second sub-pixel circuit (SPC2) arranged in the first sub-pixel column (COL1). The first data line (DL1) is connected to the first scan transistor (SCT1) in the first sub-pixel circuit (SPC1) and can be connected to the second scan transistor (SCT2) in the second sub-pixel circuit (SPC2).

[0172] The second data line (DL2) can supply the second data voltage (Vdata2) to the third sub-pixel circuit (SPC3) and the fourth sub-pixel circuit (SPC4) arranged in the second sub-pixel column (COL2). The second data line (DL2) is connected to the third scan transistor (SCT3) in the third sub-pixel circuit (SPC3) and can be connected to the fourth scan transistor (SCT4) in the fourth sub-pixel circuit (SPC4).

[0173] The third data line (DL3) can supply the third data voltage (Vdata3) to the fifth sub-pixel circuit (SPC5) and the sixth sub-pixel circuit (SPC6) arranged in the third sub-pixel column (COL3). The third data line (DL3) is connected to the fifth scan transistor (SCT5) in the fifth sub-pixel circuit (SPC5) and can be connected to the sixth scan transistor (SCT6) in the sixth sub-pixel circuit (SPC6).

[0174] The fourth data line (DL4) can supply the fourth data voltage (Vdata4) to the seventh sub-pixel circuit (SPC7) and the eighth sub-pixel circuit (SPC8) arranged in the fourth sub-pixel column (COL4). The fourth data line (DL4) can be connected to the seventh scan transistor (SCT7) in the seventh sub-pixel circuit (SPC7) and can be connected to the eighth scan transistor (SCT8) in the eighth sub-pixel circuit (SPC8).

[0175] Referring to FIG. 14, the reference voltage line (RVL) can be arranged between the second sub-pixel column (COL2) and the third sub-pixel column (COL3).

[0176] The reference voltage line (RVL) can be connected to the first to eighth sub-pixel circuits (SPC1 to SPC8) arranged in the first to fourth sub-pixel columns (COL1 to COL4). The reference voltage line (RVL) can be connected to the first to eighth sub-pixel circuits (SPC1 to SPC8) arranged in the first to fourth sub-pixel columns (COL1 to COL4) through the reference connection pattern (CPTN_RVL).

[0177] The reference voltage line (RVL) can supply the reference voltage (Vref) at the drain node or the source node of the first to eighth sensing transistors (SENT1 to SENT8) in the first to eighth sub-pixel circuits (SPC1 to SPC8) arranged in the first to fourth sub-pixel columns (COL1 to COL4).

[0178] Referring to FIG. 14, the drive voltage line (DVL) can be arranged on one side of the first sub-pixel column (COL1) and on the other side of the fourth sub-pixel column (COL4).

[0179] The driving voltage line (DVL) disposed on one side of the first sub-pixel column (COL1) can be connected to the first to fourth sub-pixel circuits (SPC1 to SPC4) disposed in the first and second sub-pixel columns (COL1, COL2). The driving voltage line (DVL) disposed on one side of the first sub-pixel column (COL1) can be connected to the first to fourth sub-pixel circuits (SPC1 to SPC4) disposed in the first and second sub-pixel columns (COL1, COL2) through the driving connection pattern (CPTN_DVL).

[0180] The driving voltage line (DVL) disposed on one side of the first sub-pixel column (COL1) can supply a driving voltage (EVDD) to the drain nodes or source nodes of the first to fourth scan transistors (SCT1 to SCT4) in the first to fourth sub-pixel circuits (SPC1 to SPC4) disposed in the first and second sub-pixel columns (COL1, COL2).

[0181] The driving voltage line (DVL) disposed on the other side of the fourth sub-pixel column (COL4) can be connected to the fifth to eighth sub-pixel circuits (SPC5 to SPC8) disposed in the third and fourth sub-pixel columns (COL3, COL4). The driving voltage line (DVL) disposed on the other side of the fourth sub-pixel column (COL4) can be connected to the fifth to eighth sub-pixel circuits (SPC5 to SPC8) disposed in the third and fourth sub-pixel columns (COL3, COL4) through the driving connection pattern (CPTN_DVL).

[0182] The driving voltage line (DVL) disposed on the other side of the fourth sub-pixel column (COL4) can supply a driving voltage (EVDD) to the drain nodes or source nodes of the fifth to eighth scan transistors (SCT5 to SCT8) in the fifth to eighth sub-pixel circuits (SPC5 to SPC8) disposed in the third and fourth sub-pixel columns (COL3, COL4).

[0183] Referring to FIG. 14, since the first sub-pixel (SP1) and the second sub-pixel (SP2) have a vertically symmetric structure, the first sub-pixel circuit (SPC1) and the second sub-pixel circuit (SPC2) can also have a vertically symmetric structure.

[0184] Referring to FIG. 14, since the third sub-pixel (SP3) and the fourth sub-pixel (SP4) have a vertically symmetric structure, the third sub-pixel circuit (SPC3) and the fourth sub-pixel circuit (SPC4) can also have a vertically symmetric structure.

[0185] Referring to FIG. 14, since the fifth sub-pixel (SP5) and the sixth sub-pixel (SP6) have a vertically symmetric structure, the fifth sub-pixel circuit (SPC5) and the sixth sub-pixel circuit (SPC6) can also have a vertically symmetric structure.

[0186] Referring to FIG. 14, since the seventh sub-pixel (SP7) and the eighth sub-pixel (SP8) have a vertically symmetric structure, the seventh sub-pixel circuit (SPC7) and the eighth sub-pixel circuit (SPC8) can also have a vertically symmetric structure.

[0187] Hereinafter, in the display panel 110 according to the embodiment of the present disclosure, a repair structure that can improve the aperture ratio while facilitating repair will be described.

[0188] FIG. 15 is a plan view of a partial region 1600 of FIG. 14, FIG. 16 is an enlarged plan view of a partial region 1700 of FIG. 15, FIG. 17 is a cross-sectional view taken along line A-A' of FIG. 16, and FIG. 18 is a cross-sectional view of the display device 100 according to the embodiment of the present disclosure for the first and second sub-pixels (SP1, SP2) adjacent in the column direction. FIG. 19 is a plan view of the display panel 110 for which repair processing has been performed as a plan view of a partial region 1600 of FIG. 14.

[0189] Referring to FIG. 15, the first sub-pixel circuit (SPC1) and the second sub-pixel circuit (SPC2) can be in contact in the column direction and have a vertically symmetric structure. The third sub-pixel circuit (SPC3) and the fourth sub-pixel circuit (SPC4) can be in contact in the column direction and have a vertically symmetric structure. The fifth sub-pixel circuit (SPC5) and the sixth sub-pixel circuit (SPC6) can be in contact in the column direction and have a vertically symmetric structure. The seventh sub-pixel circuit (SPC7) and the eighth sub-pixel circuit (SPC8) can be in contact in the column direction and have a vertically symmetric structure.

[0190] Referring to FIG. 15, the repair structure of the display panel 110 according to an embodiment of the present disclosure may include lower metals (LM1 and LM2, LM3 and LM4, LM5 and LM6, LM7 and LM8) respectively disposed in sub-pixel circuits (SPC1 and SPC2, SPC3 and SPC4, SPC5 and SPC6, SPC7 and SPC8) having a vertically symmetric structure, and a superimposed pattern (OP) superimposed on the lower metals (LM1 and LM2, LM3 and LM4, LM5 and LM6, LM7 and LM8) respectively disposed in sub-pixel circuits (SPC1 and SPC2, SPC3 and SPC4, SPC5 and SPC6, SPC7 and SPC8) having a vertically symmetric structure.

[0191] Before the repair process, the lower metals (LM1 and LM2, LM3 and LM4, LM5 and LM6, LM7 and LM8) can be connected to adjacent positive power supply wirings (e.g., drive voltage line (DVL), reference voltage line (RVL), etc.).

[0192] During the repair process, the connection points between the lower metals (LM1 and LM2, LM3 and LM4, LM5 and LM6, LM7 and LM8) and the positive power supply wirings (e.g., drive voltage line (DVL), reference voltage line (RVL), etc.) can be cut. That is, the connection points between the lower metals (LM1 and LM2, LM3 and LM4, LM5 and LM6, LM7 and LM8) and the positive power supply wirings (e.g., drive voltage line (DVL), reference voltage line (RVL), etc.) become cutting points (CP) to be cut during the repair process.

[0193] Also, during the repair process, as shown in FIG. 12, the cutting process for disabling the sub-pixel circuit can also proceed together. The cutting points (CP1, CP2, CP3) for disabling the sub-pixel circuit can be the connection points between the sub-pixel circuit to be disabled and the signal wiring (e.g., DL, DVL, RVL).

[0194] Hereinafter, the repair structure will be exemplified and described in more detail through the first sub-pixel (SP1) and the second sub-pixel (SP2).

[0195] Referring to FIGS. 15 to 17, in the first sub-pixel circuit (SPC1) and the second sub-pixel circuit (SPC2) having a vertically symmetric structure, the first lower metal (LM1) is disposed in the first sub-pixel circuit (SPC1), the second lower metal (LM2) is disposed in the second sub-pixel circuit (SPC2), and the overlapping pattern (OP) can overlap at least a part of the first lower metal (LM1) and at least a part of the second lower metal (LM2).

[0196] As shown in FIG. 17, in the first state, the overlapping pattern (OP) can be electrically disconnected from the first lower metal (LM1) and the second lower metal (LM2).

[0197] Alternatively, in the first state, the overlapping pattern (OP) can be electrically connected to one of the first lower metal (LM1) and the second lower metal (LM2) and electrically disconnected from the other one.

[0198] In the second state different from the first state, the overlapping pattern (OP) can be electrically connected to all of the first lower metal (LM1) and the second lower metal (LM2).

[0199] The first state can mean that the first sub-pixel (SP1) and the second sub-pixel (SP2) are all in the state of normal sub-pixels. In the first state, the first sub-pixel circuit (SPC1) can supply a first current to the first light-emitting element (ED1), and the second sub-pixel circuit (SPC2) can supply a second current to the second light-emitting element (ED2).

[0200] The second state may mean a state in which a repair process has been performed on a defective sub-pixel when one of the first sub-pixel (SP1) and the second sub-pixel (SP2) is a normal sub-pixel and the other is a defective sub-pixel (abnormal sub-pixel).

[0201] For example, when the first sub-pixel (SP1) is a normal sub-pixel and the second sub-pixel (SP2) is a defective sub-pixel (abnormal sub-pixel) among the first sub-pixel (SP1) and the second sub-pixel (SP2), the second state may be a state in which the second sub-pixel (SP2) has been repaired and normalized.

[0202] In such a second state, not only does the first sub-pixel circuit (SPC1) supply a first current to the first light-emitting element (ED1), but it can also supply the first current to the second light-emitting element (ED2) together. The second sub-pixel circuit (SPC2) is disabled and does not supply current to the second light-emitting element (ED2).

[0203] The repair process may include a welding process (welding repair process) and a cutting process (cutting repair process).

[0204] The welding point (WP), which is a location for the welding process, may include a location corresponding to the first part (PART1) of the overlapping pattern (OP) and a location corresponding to the second part (PART2) of the overlapping pattern (OP).

[0205] Referring to FIGS. 17 and 18, the vertical structure of the display panel 110 including the repair structure will be described in detail.

[0206] Referring to FIGS. 17 and 18, the first lower metal (LM1) and the second lower metal (LM2) may be disposed on the substrate (SUB). The first lower metal (LM1) may be disposed in the region of the first sub-pixel circuit (SPC1), and the second lower metal (LM2) may be disposed in the region of the second sub-pixel circuit (SPC2).

[0207] Referring to FIGS. 17 and 18, a first buffer layer (BUF1) can be disposed on a first lower metal (LM1) and a second lower metal (LM2), and a superimposed pattern (OP) can be disposed on the first buffer layer (BUF1).

[0208] Referring to FIGS. 17 and 18, plates (PLT) of first and second subpixel circuits (SPC1, SPC2) can be disposed on the first buffer layer (BUF1) together with the superimposed pattern (OP). The superimposed pattern (OP) and the plates (PLT) of the first and second subpixel circuits (SPC1, SPC2) can be located in the same layer and contain the same material.

[0209] Referring to FIGS. 17 and 18, a second buffer layer (BUF2) can be disposed on the plate (PLT) and the superimposed pattern (OP).

[0210] Referring to FIGS. 17 and 18, an active layer pattern can be disposed on the second buffer layer (BUF2).

[0211] For example, the active layer pattern can include a first active layer (ACT1) of a first driving transistor (DRT1), an active layer pattern (AP_SCT1) for forming an active layer of a first scan transistor (SCT1), an active layer pattern (AP_SENT1) for forming an active layer of a first sensing transistor (SENT1), a second active layer (ACT2) of a second driving transistor (DRT2), an active layer pattern (AP_SCT2) for forming an active layer of a second scan transistor (SCT2), and an active layer pattern (AP_SENT2) for forming an active layer of a second sensing transistor (SENT2).

[0212] For example, the active layer pattern may further include a drive connection pattern (CPTN_DVL) for connecting the drive voltage line (DVL) to the first drain electrode (D1) of the first drive transistor (DRT1) and the second drain electrode (D2) of the second drive transistor (DRT2).

[0213] For example, the active layer pattern may include an oxide semiconductor material.

[0214] Referring to FIGS. 17 and 18, a gate insulating layer (GI) may be disposed on the active layer patterns (ACT1, AP_SCT1, AP_SENT1, ACT2, AP_SCT2, AP_SENT2, CPTN_DVL).

[0215] Referring to FIGS. 16, 17, and 18, the first gate electrode (G1) and the first source electrode (S1) of the first drive transistor (DRT1) may be disposed on the gate insulating layer (GI). The second gate electrode (G2) and the second source electrode (S2) of the second drive transistor (DRT2) may be disposed on the gate insulating layer (GI).

[0216] The first source electrode (S1) may be connected to the first lower metal (LM1) through holes (GI Hole) in the gate insulating layer (GI), the second buffer layer (BUF2), and the first buffer layer (BUF1).

[0217] The second source electrode (S2) may be connected to the second lower metal (LM2) through holes (GI Hole) in the gate insulating layer (GI), the second buffer layer (BUF2), and the first buffer layer (BUF1).

[0218] Referring to FIGS. 17 and 18, a passivation layer (PAS) may be disposed on the first gate electrode (G1), the first source electrode (S1), the second gate electrode (G2), and the second source electrode (S2).

[0219] Referring to FIGS. 17 and 18, an overcoat layer (OC) may be disposed on the passivation layer (PAS).

[0220] Referring to FIGS. 16, 17 and 18, the first pixel electrode (PE1) and the second pixel electrode (PE2) can be disposed on the overcoat layer (OC). The first pixel electrode (PE1) can be connected to the first source electrode (S1) through the hole (OC Hole) of the overcoat layer (OC) and the hole (PAS Hole) of the passivation layer (PAS). The second pixel electrode (PE2) can be connected to the second source electrode (S2) through the hole (OC Hole) of the overcoat layer (OC) and the hole (PAS Hole) of the passivation layer (PAS).

[0221] Referring to FIGS. 16, 17 and 18, the hole (OC Hole) of the overcoat layer (OC) and the hole (PAS Hole) of the passivation layer (PAS) can overlap each other. The hole (OC Hole) of the overcoat layer (OC) can be larger than the hole (PAS Hole) of the passivation layer (PAS).

[0222] Referring to FIGS. 16, 17 and 18, the positions of the hole (OC Hole) of the overcoat layer (OC) and the hole (PAS Hole) of the passivation layer (PAS) can be different from the position of the hole (GI Hole) of the gate insulating layer (GI).

[0223] Referring to FIGS. 17 and 18, the bank (BK) can be disposed on the first pixel electrode (PE1) and the second pixel electrode (PE2). The bank (BK) can include a first opening (not shown) corresponding to (overlapping) the first light-emitting region (EA1) and a second opening (not shown) corresponding to (overlapping) the second light-emitting region (EA2). A part of the first pixel electrode (PE1) can be exposed through the first opening of the bank (BK), and a part of the second pixel electrode (PE2) can be exposed through the second opening of the bank (BK).

[0224] The repair structure of the display device 100 according to the embodiment of the present disclosure described above will be described again from the perspective of the first sub-pixel (SP1) and the second sub-pixel (SP2) adjacent in the column direction.

[0225] In the display device 100 according to the embodiment of the present disclosure, when the first sub-pixel (SP1) and the second sub-pixel (SP2) have a vertically symmetric structure and are a set for repair processing, the distance between the first source electrode (S1) of the first driving transistor (DRT1) and the second source electrode (S2) of the second driving transistor (DRT2) may be even closer than the distance between the first light-emitting region (EA1) of the first light-emitting element (ED1) and the second light-emitting region (EA2) of the second light-emitting element (ED2).

[0226] The display device 100 according to the embodiment of the present disclosure includes a first sub-pixel (SP1) including a first driving transistor (DRT1) and a first light-emitting element (ED1), a second sub-pixel (SP2) including a second driving transistor (DRT2) and a second light-emitting element (ED2), a first lower metal (LM1) connected to the first source electrode (S1) of the first driving transistor (DRT1), a second lower metal (LM2) connected to the second source electrode (S2) of the second driving transistor (DRT2), a first portion (PART1) overlapping a part of the first lower metal (LM1), a second portion (PART2) overlapping a part of the second lower metal (LM2), and a third portion (PART3) between the first portion (PART1) and the second portion (PART2), and may include an overlapping pattern (OP), and a first buffer layer (BUF1) disposed between the first lower metal (LM1) and the second lower metal (LM2) and the overlapping pattern (OP).

[0227] In the display device 100 according to the embodiment of the present disclosure, the first lower metal (LM1) is disposed below the first active layer (ACT1) of the first driving transistor (DRT1), the second lower metal (LM2) is disposed below the first active layer (ACT1) of the second driving transistor (DRT2), and the overlapping pattern (OP) may be disposed below the first lower metal (LM1) and the second lower metal (LM2).

[0228] If it is confirmed during the process that the first sub-pixel (SP1) and the second sub-pixel (SP2) are normal sub-pixels, no repair process is performed during the process. In the first state of the display panel 110 in such a case, a first current (I1) can be supplied from the first driving transistor (DRT1) to the first pixel electrode (PE1), and a second current (I2) can be supplied from the second driving transistor (DRT2) to the second pixel electrode (PE2).

[0229] In such a first state, the first part (PART1) of the overlapping pattern (OP) and the first lower metal (LM1) are separated, and the second part (PART2) of the overlapping pattern (OP) and the second lower metal (LM2) can be separated.

[0230] Also, in the first state, the overlapping pattern (OP) can be electrically connected to a common power line. For example, the common power line may include one or more of a driving voltage line (DVL), a reference voltage line (RVL), and a base voltage line (BVL).

[0231] In the first state, if the overlapping pattern (OP) is in a floating state not electrically connected to the common power line, foreign matter can be induced around the overlapping pattern (OP), which may cause defects due to the repair structure. Therefore, by electrically connecting the overlapping pattern (OP) to an adjacent common power line in the first state, defects due to the repair structure can be prevented, and the repair performance and the probability of repair success can be improved.

[0232] If it is confirmed during the process that the first sub-pixel (SP1) is a normal sub-pixel and the second sub-pixel (SP) is a defective sub-pixel, a repair process for normalizing the second sub-pixel (SP2) (i.e., a repair process for causing the second light-emitting element (ED2) to emit light) can be performed during the process. In the second state of the display panel 110 in such a case, a first current (I1) can be supplied from the first driving transistor (DRT1) to the first pixel electrode (PE1) and the second pixel electrode (PE2).

[0233] In such a second state, the first part (PART1) of the overlay pattern (OP) and the first lower metal (LM1) may be connected, and the second part (PART2) of the overlay pattern (OP) and the second lower metal (LM2) may be connected.

[0234] Also, in the second state, the overlay pattern (OP) may be electrically disconnected from the common power supply line. For example, the common power supply line may include one or more of a drive voltage line (DVL), a reference voltage line (RVL), and a base voltage line (BVL).

[0235] The display device 100 according to an embodiment of the present disclosure may include a first driving transistor (DRT1) including a first active layer (ACT1), a first source electrode (S1), a first drain electrode (D1), and a first gate electrode (G1), a first pixel electrode (PE1) electrically connected to the first source electrode (S1), a second driving transistor (DRT2) including a second active layer (ACT2), a second source electrode (S2), a second drain electrode (D2), and a second gate electrode (G2), and a second pixel electrode (PE2) electrically connected to the second source electrode (S2).

[0236] The display device 100 according to an embodiment of the present disclosure may include a first lower metal (LM1) electrically connected to the first source electrode (S1) and overlapping the first active layer (ACT1), a second lower metal (LM2) electrically connected to the second source electrode (S2) and overlapping the second active layer (ACT2), a first buffer layer (BUF1) disposed on the first lower metal (LM1) and the second lower metal (LM2), a first part (PART1) disposed on the first buffer layer (BUF1) and overlapping a part of the first lower metal (LM1), a second part (PART2) overlapping a part of the second lower metal (LM2), a third part (PART3) between the first part (PART1) and the second part (PART2), an overlay pattern (OP), and a second buffer layer (BUF2) disposed on the overlay pattern (OP) and under the first active layer (ACT1) and the second active layer (ACT2).

[0237] The distance between the first source electrode (S1) and the second source electrode (S2) is closer than the distance between the first light-emitting region (EA1) formed by the first pixel electrode (PE1) and the second light-emitting region (EA2) formed by the second pixel electrode (PE2).

[0238] The display device 100 according to an embodiment of the present disclosure may further include a gate insulating layer (GI) disposed on the first active layer (ACT1) and the second active layer (ACT2).

[0239] The first source electrode (S1) is disposed on the gate insulating layer (GI) and may be connected to the first lower metal (LM1) through a hole (GI Hole) in the gate insulating layer (GI), the second buffer layer (BUF2), and the first buffer layer (BUF1).

[0240] The second source electrode (S2) is disposed on the gate insulating layer (GI) and may be connected to the second lower metal (LM2) through a hole (GI Hole) in the gate insulating layer (GI), the second buffer layer (BUF2), and the first buffer layer (BUF1).

[0241] The display device 100 according to an embodiment of the present disclosure may further include a passivation layer (PAS) disposed on the first source electrode (S1), the first gate electrode (G1), the second source electrode (S2), and the second gate electrode (G2), and an overcoat layer (OC) disposed on the passivation layer (PAS).

[0242] The first pixel electrode (PE1) is disposed on the overcoat layer (OC) and may be connected to the first source electrode (S1) through a hole (OC Hole) in the overcoat layer (OC) and a hole (PAS Hole) in the passivation layer (PAS). The second pixel electrode (PE2) is disposed on the overcoat layer (OC) and may be connected to the second source electrode (S2) through a hole (OC Hole) in the overcoat layer (OC) and a hole (PAS Hole) in the passivation layer (PAS).

[0243] The first source electrode (S1) and the second source electrode (S2) may equally contain the gate electrode material included in the first gate electrode (G1) and the second gate electrode (G2), and may be arranged in the same layer as the first gate electrode (G1) and the second gate electrode (G2).

[0244] The first gate electrode (G1) is arranged on the first active layer (ACT1), and the second gate electrode (G2) may be arranged on the first active layer (ACT1).

[0245] Referring to FIGS. 15 to 18, a display device 100 according to an embodiment of the present disclosure may further include a first storage capacitor (Cst1) formed between the first source electrode (S1) and the first gate electrode (G1), and a second storage capacitor (Cst2) formed between the second source electrode (S2) and the second gate electrode (G2).

[0246] The first storage capacitor (Cst1) may include a first upper capacitor (Cu1) and a first lower capacitor (Cd1).

[0247] The first upper capacitor (Cu1) may include a first capacitor electrode corresponding to the first source electrode (S1) and a second capacitor electrode (AP_SCT1) including the same material (active layer pattern) as the first active layer (ACT1).

[0248] The first lower capacitor (Cd1) may include a third capacitor electrode (PLT) including the same material as the overlapping pattern (OP) and a fourth capacitor electrode corresponding to the first lower metal (LM1).

[0249] The first capacitor electrode and the fourth capacitor electrode may be at the same potential as the first source electrode (S1), and the second capacitor electrode and the third capacitor electrode may be at the same potential as the first gate electrode (G1).

[0250] Therefore, the first upper capacitor (Cu1) and the first lower capacitor (Cd1) may be connected in parallel. As a result, the capacitance of the first storage capacitor (Cst1) may increase.

[0251] The second storage capacitor (Cst2) may include a second upper capacitor (Cu2) and a second lower capacitor (Cd2).

[0252] The second upper capacitor (Cu2) may include a fifth capacitor electrode corresponding to the second source electrode (S2) and a sixth capacitor electrode (AP_SCT2) including the same material (active layer pattern) as the second active layer (ACT2).

[0253] The second lower capacitor (Cd2) may include a seventh capacitor electrode (PLT) including the same material as the overlapping pattern (OP) and an eighth capacitor electrode corresponding to the second lower metal (LM2).

[0254] The fifth capacitor electrode and the eighth capacitor electrode may have the same potential as the second source electrode (S2), and the sixth capacitor electrode and the seventh capacitor electrode may have the same potential as the second gate electrode (G2).

[0255] Therefore, the second upper capacitor (Cu2) and the second lower capacitor (Cd2) may be connected in parallel. As a result, the capacitance of the second storage capacitor (Cst2) may increase.

[0256] If it is confirmed during the process that the first sub-pixel (SP1) and the second sub-pixel (SP2) are normal sub-pixels, no repair process is performed during the process. In the first state of the display panel 110 in such a case, a first current (I1) may be supplied from the first driving transistor (DRT1) to the first pixel electrode (PE1), and a second current (I2) may be supplied from the second driving transistor (DRT2) to the second pixel electrode (PE2).

[0257] In such a first state, as shown in FIGS. 17 and 18, the first part (PART1) of the overlapping pattern (OP) and the first lower metal (LM1) may be separated, and the second part (PART2) of the overlapping pattern (OP) and the second lower metal (LM2) may be separated.

[0258] Also, in the first state, as shown in FIG. 15, the overlapping pattern (OP) can be electrically connected to a common power line. For example, the common power line may include one or more of a drive voltage line (DVL), a reference voltage line (RVL), and a base voltage line (BVL).

[0259] As shown in FIG. 15, for example, in the first state, the drive voltage line (DVL) can be connected to at least one of both ends of the overlapping pattern (OP) as a common power line for transmitting a drive voltage (EVDD) to the first drain electrode (D1) and the second drain electrode (D2).

[0260] The repair structure for the third sub-pixel circuit (SPC3) and the fourth sub-pixel circuit (SPC4) may include a third lower metal (LM3) connected to the source electrode of the third drive transistor (DRT3) in the third sub-pixel circuit (SPC3), a fourth lower metal (LM4) connected to the source electrode of the fourth drive transistor (DRT4) in the fourth sub-pixel circuit (SPC4), and an overlapping pattern (OP) that overlaps at least a part of the third lower metal (LM3) and at least a part of the fourth lower metal (LM4). Here, the overlapping pattern (OP) may include a first part (PART1) that overlaps at least a part of the third lower metal (LM3), a second part (PART2) that overlaps at least a part of the fourth lower metal (LM4), and a third part (PART3) between the first part (PART1) and the second part (PART2).

[0261] Also, when it is confirmed that the third sub-pixel (SP3) and the fourth sub-pixel (SP4) are normal sub-pixels and in the first state where the third sub-pixel (SP3) and the fourth sub-pixel (SP4) are not in a repaired state, as shown in FIG. 15, at least one of both ends of the overlapping pattern (OP) can be connected to the reference voltage line (RVL), which is the common power line in closest contact.

[0262] If it is confirmed during the process that the first sub-pixel (SP1) is a normal sub-pixel and the second sub-pixel (SP2) is a defective sub-pixel, a repair process for normalizing the second sub-pixel (SP2) (i.e., a repair process for causing the second light-emitting element (ED2) to emit light) can be performed during the process. In the second state of the display panel 110 in such a case, a first current (I1) can be supplied from the first driving transistor (DRT1) to the first pixel electrode (PE1) and the second pixel electrode (PE2).

[0263] As shown in FIGS. 11 and 18, in such a second state, the first portion (PART1) of the overlapping pattern (OP) and the first lower metal (LM1) can be connected, and the second portion (PART2) of the overlapping pattern (OP) and the second lower metal (LM2) can be connected. Thereby, a first welding pattern (WPTN1) is formed between the first portion (PART1) of the overlapping pattern (OP) and the first lower metal (LM1), and a second welding pattern (WPTN2) can be formed between the second portion (PART2) of the overlapping pattern (OP) and the second lower metal (LM2).

[0264] Also, as shown in FIG. 19, in the second state, the overlapping pattern (OP) can be electrically disconnected from the common power line. For example, the common power line can include one or more of a driving voltage line (DVL), a reference voltage line (RVL), and a base voltage line (BVL).

[0265] For example, the overlapping pattern (OP) can be cut during the repair process while being connected to the driving voltage line (DVL) (1st cutting).

[0266] As shown in FIG. 19, in the second state, it further includes a driving voltage line (DVL) for transmitting a driving voltage (EVDD) to the first drain electrode (D1) and the second drain electrode (D2), and both ends of the overlapping pattern (OP) are electrically disconnected from the driving voltage line (DVL).

[0267] On the other hand, in the second state where it is confirmed that the fourth sub-pixel (SP4) among the third sub-pixel (SP3) and the fourth sub-pixel (SP4) is a defective sub-pixel and a repair process for normalizing the fourth sub-pixel (SP4) has been performed, the connection state between at least one of both ends of the overlapping pattern (OP) and the reference voltage line (RVL) can be cut by a cutting process.

[0268] Also, as shown in FIG. 19, in the second state, for the inactivation of the second driving transistor (DRT2), in one example, the connection point between the first driving transistor (DRT2) and the driving voltage line (DLV) is cut (2nd Cutting).

[0269] As described above, the repair structure described with reference to FIGS. 15 to 19 requires two welding processes (i.e., welding processes at two welding points (WP1, WP2)) and two cutting processes (1st cutting, 2nd cutting).

[0270] FIG. 20 is a plan view of an enlarged partial region 1700 of FIG. 15, and FIG. 21 is a cross-sectional view of a display device according to an embodiment of the present disclosure for first and second sub-pixels adjacent in the column direction. The cross-sectional view of FIG. 21 includes a portion cut along the C-C' line of FIG. 20.

[0271] The plan view of FIG. 20 and the plan view of FIG. 16 are plan views showing an enlarged and more detailed same partial region 1700 of FIG. 15. Accordingly, the plan view of FIG. 20 is almost the same as the plan view of FIG. 16. Also, the cross-sectional view of FIG. 21 and the cross-sectional view of FIG. 18 are cross-sectional views of equal regions. Therefore, the cross-sectional view of FIG. 21 and the cross-sectional view of FIG. 18 are also almost the same. However, FIGS. 20 and 21 have some differences compared to FIGS. 16 and 18. Therefore, hereinafter, the description of the same content will be omitted, and the differences will be mainly described.

[0272] The positions of the passivation layer (PAS) in FIGS. 20 and 21 are different from the positions of the holes (PAS Hole) in the passivation layer (PAS) in FIGS. 16 and 18, and the positions of the holes (GI Hole) in the gate insulating layer (GI) in FIGS. 20 and 21 are different from the positions of the holes (GI Hole) in the gate insulating layer (GI) in FIGS. 16 and 18.

[0273] Such differences are due to the absence of the first source electrode (S1) and the second source electrode (S2) in FIGS. 16 and 18 in FIGS. 20 and 21.

[0274] In FIGS. 16 and 18, the first pixel electrode (PE1) and the first lower metal (LM1) are not directly connected but are electrically connected through the first source electrode (S1), and the second pixel electrode (PE2) and the second lower metal (LM2) can be electrically connected through the second source electrode (S2) without being directly connected.

[0275] In contrast, in FIGS. 20 and 21, the first pixel electrode (PE1) can be directly connected to the first lower metal (LM1), and the second pixel electrode (PE2) can be directly connected to the second lower metal (LM2).

[0276] The first pixel electrode (PE1) can be directly connected to the first lower metal (LM1) through a hole that penetrates through the overcoat layer (OC), the passivation layer (PAS), the second buffer layer (BUF2), and the first buffer layer (BUF1).

[0277] The second pixel electrode (PE2) can be directly connected to the second lower metal (LM2) through a hole that penetrates through the overcoat layer (OC), the passivation layer (PAS), the second buffer layer (BUF2), and the first buffer layer (BUF1).

[0278] Referring to FIGS. 20 and 21, the hole that penetrates through the overcoat layer (OC), the passivation layer (PAS), the second buffer layer (BUF2), and the first buffer layer (BUF1) includes the hole (PAS Hole) of the passivation layer (PAS).

[0279] In FIGS. 20 and 21, the active layer pattern (AP_SENT1) for forming the active layer of the first sensing transistor (SENT1) serves as the first source electrode (S1), and the first pixel electrode (PE1) can also serve as the first source electrode (S1).

[0280] In FIGS. 20 and 21, the active layer pattern (AP_SENT2) for forming the active layer of the second sensing transistor (SENT2) serves as the second source electrode (S2), and the second pixel electrode (PE2) can also serve as the second source electrode (S2).

[0281] Due to the points where the first source electrode (S1) and the second source electrode (S2) in FIGS. 16 and 18 do not exist in FIGS. 20 and 21, the storage capacitor structure in FIGS. 20 and 21 may change.

[0282] Referring to FIG. 21, the first storage capacitor (Cst1) may include a first upper capacitor (Cu1) and a first lower capacitor (Cd1).

[0283] The first upper capacitor (Cu1) may include a first capacitor electrode (AP_SCT1) including the same material (active layer pattern) as the first active layer (ACT1), and a second capacitor electrode (PLT) including the same material as the overlapping pattern (OP). Here, the first capacitor electrode (AP_SCT1) including the same material (active layer pattern) as the first active layer (ACT1) is electrically connected to the first pixel electrode (PE1). Therefore, the first capacitor electrode (AP_SCT1) can also be seen as the first pixel electrode (PE1).

[0284] The first lower capacitor (Cd1) may include a second capacitor electrode (PLT) containing the same material as the overlapping pattern (OP) and a third capacitor electrode corresponding to the first lower metal (LM1).

[0285] The first capacitor electrode and the third capacitor electrode may be at the same potential as the first source electrode (S1), and the second capacitor electrode may be at the same potential as the first gate electrode (G1). Therefore, the first upper capacitor (Cu1) and the first lower capacitor (Cd1) may be connected in parallel. As a result, the capacitance of the first storage capacitor (Cst1) may increase.

[0286] Referring to FIG. 21, the second storage capacitor (Cst2) may include a second upper capacitor (Cu2) and a second lower capacitor (Cd2).

[0287] The second upper capacitor (Cu2) may include a fourth capacitor electrode (AP_SCT2) containing the same material (active layer pattern) as the second active layer (ACT2) and a fifth capacitor electrode (PLT) containing the same material as the overlapping pattern (OP). Here, the fourth capacitor electrode (AP_SCT2) containing the same material (active layer pattern) as the second active layer (ACT2) is electrically connected to the second pixel electrode (PE2). Therefore, the fourth capacitor electrode (AP_SCT2) may be regarded as the second pixel electrode (PE2).

[0288] The second lower capacitor (Cd2) may include a fifth capacitor electrode (PLT) containing the same material as the overlapping pattern (OP) and a sixth capacitor electrode corresponding to the second lower metal (LM2).

[0289] The fourth capacitor electrode and the sixth capacitor electrode may be at the same potential as the second source electrode (S2), and the fifth capacitor electrode may be at the same potential as the second gate electrode (G2). Therefore, the second upper capacitor (Cu2) and the second lower capacitor (Cd2) may be connected in parallel. As a result, the capacitance of the first storage capacitor (Cst1) may increase.

[0290] Hereinafter, a repair structure that can reduce two welding processes to one welding process and reduce two cutting processes to one cutting process will be described with reference to FIGS. 22 to 26.

[0291] FIG. 22 is a plan view of a partial region 1600 of FIG. 14, FIG. 23 is an enlarged plan view of a partial region 2200 in FIG. 22, FIG. 24 is a cross-sectional view taken along line B-B' of FIG. 23, FIG. 25 is a display device 100 according to an embodiment of the present disclosure, and is a cross-sectional view of first and second sub-pixels (SP1, SP2) adjacent in the column direction. FIG. 26 is a plan view of a display panel 110 for which repair processing has been performed as a plan view of a partial region 1600 of FIG. 14.

[0292] FIGS. 22 to 26 are only slightly different in the repair structure and can respectively correspond to FIGS. 15 to 19. Therefore, in the description with reference to FIGS. 22 to 26, the description of the same content as that in FIGS. 15 to 19 will be omitted, and the description will be centered on other content.

[0293] Referring to FIGS. 22 to 26, before the repair process, the second part (PART2) of the overlay pattern (OP) is not electrically connected to the second lower metal (LM2), but the first part (PART1) of the overlay pattern (OP) can be electrically connected to the first lower metal (LM1) through the connection pattern (CPTN_OP).

[0294] Conversely, before the repair process, the first part (PART1) of the overlay pattern (OP) is not electrically connected to the first lower metal (LM1), but the second part (PART2) of the overlay pattern (OP) can be electrically connected to the second lower metal (LM2) through the connection pattern (CPTN_OP).

[0295] That is, the repair structure according to the embodiments of the present disclosure may further include a connection pattern (CPTN_OP) that connects the first part (PART1) of the overlay pattern (OP) to the first lower metal (LM1) or connects the second part (PART2) of the overlay pattern (OP) to the second lower metal (LM2).

[0296] The connection pattern (CPTN_OP) may include the same material as the first source electrode (S1) and the second source electrode (S2), and may be disposed within the layer in which the first source electrode (S1) and the second source electrode (S2) are disposed.

[0297] Referring to FIGS. 22 to 26, before the repair process, the overlay pattern (OP) may not be connected to adjacent common power lines (e.g., drive voltage line (DVL), reference voltage line (RVL)).

[0298] Referring to FIGS. 22 to 26, it is confirmed that a defect has occurred in the second sub-pixel circuit (SPC2) among the first sub-pixel circuit (SPC1) and the second sub-pixel circuit (SPC2). To perform a repair process for normalizing the second sub-pixel (SP2), only one welding process and one cutting process need to be performed.

[0299] One welding process may be a welding process for electrically connecting one end to which the connection pattern (CPTN_OP) is not connected among both ends of the overlay pattern (OP) to the corresponding lower metal. That is, through one welding process, a welding pattern (WPTN) may be formed between one end to which the connection pattern (CPTN_OP) is not connected among both ends of the overlay pattern (OP) and the corresponding lower metal.

[0300] For example, through one welding process, the second part (PART2) of the overlapping pattern (OP) and the second lower metal (LM2) can be electrically connected. That is, through one welding process, a welding pattern (WPTN) can be formed between the second part (PART2) of the overlapping pattern (OP) and the second lower metal (LM2).

[0301] One cutting process can be a cutting process (2nd cutting) for disabling the second sub-pixel circuit (SPC2). For example, as shown in FIG. 26, through one cutting process, the connection between the second driving transistor (DRT2) and the driving voltage line (DVL) in the second sub-pixel circuit (SPC2) can be cut.

[0302] FIG. 27 shows the current supply situation after the repair process when a defect occurs in the second sub-pixel (SP2) among the first to fourth sub-pixels (SP) arranged in the column direction in the display panel 110 according to an embodiment of the present disclosure, and FIG. 28 shows the current supply situation after the repair process when a defect occurs in the first sub-pixel (SP1) among the first to fourth sub-pixels (SP) arranged in the column direction in the display panel 110 according to an embodiment of the present disclosure.

[0303] Referring to FIGS. 27 and 28, an example is given where the first to fourth sub-pixels (SP1 to SP4) are arranged in the column direction.

[0304] Referring to FIGS. 27 and 28, the first sub-pixel (SP1) may include the first pixel electrode (PE1) of the first light-emitting element (ED1) and the first source electrode (S1) of the first driving transistor (DRT1) in the first sub-pixel circuit (SPC1). The second sub-pixel (SP2) may include the second pixel electrode (PE2) of the second light-emitting element (ED2) and the second source electrode (S2) of the second driving transistor (DRT2) in the second sub-pixel circuit (SPC2). The third sub-pixel (SP3) may include the third pixel electrode (PE3) of the third light-emitting element (ED3) and the third source electrode (S3) of the third driving transistor (DRT3) in the third sub-pixel circuit (SPC3). The fourth sub-pixel (SP4) may include the fourth pixel electrode (PE4) of the fourth light-emitting element (ED4) and the fourth source electrode (S4) of the fourth driving transistor (DRT4) in the fourth sub-pixel circuit (SPC4).

[0305] The first to fourth pixel electrodes (PE1 to PE4) and the first to fourth source electrodes (S1 to S4) may be electrically connected through contact holes (CNT) of an insulating layer (e.g., an overcoat layer (OC), a passivation layer (PAS)).

[0306] Referring to FIGS. 27 and 28, the first sub-pixel (SP1) and the second sub-pixel (SP2) may have a vertically symmetric structure and be a set for repair processing, and the third sub-pixel (SP3) and the fourth sub-pixel (SP4) may have a vertically symmetric structure and be a set for repair processing.

[0307] Referring to FIGS. 27 and 28, according to the vertically symmetric structure of the first sub-pixel (SP1) and the second sub-pixel (SP2), the first sub-pixel circuit (SPC1) and the second sub-pixel circuit (SPC2) may be arranged to be in contact with each other. According to the vertically symmetric structure of the third sub-pixel (SP3) and the fourth sub-pixel (SP4), the third sub-pixel circuit (SPC3) and the fourth sub-pixel circuit (SPC4) may be arranged to be in contact with each other. According to such a vertically symmetric structure, the second light-emitting element (ED2) and the third light-emitting element (ED3) may be arranged to be in contact with each other.

[0308] Referring to FIGS. 27 and 28, the repair structure for the first and second sub-pixels (SP1, SP2) may include a first lower metal connected to the first source electrode (S1), a second lower metal connected to the second source electrode (S2), and an overlapping pattern (OP) that overlaps at least a part of the first lower metal and at least a part of the second lower metal.

[0309] Referring to FIGS. 27 and 28, the repair structure for the third and fourth sub-pixels (SP3, SP4) may include a third lower metal connected to the third source electrode (S3), a fourth lower metal connected to the fourth source electrode (S4), and an overlapping pattern (OP) that overlaps at least a part of the third lower metal and at least a part of the fourth lower metal.

[0310] Referring to FIG. 27, when a defect occurs in the second sub-pixel circuit (SPC2), through a repair process for normalizing the second sub-pixel (SP2), the first lower metal connected to the first source electrode (S1) and the second lower metal connected to the second source electrode (S2) may be connected to the overlapping pattern (OP). As a result, a first welding pattern (WPTN1) may be formed between the overlapping pattern (OP) and the first lower metal, and a second welding pattern (WPTN2) may be formed between the overlapping pattern (OP) and the second lower metal.

[0311] And through a repair process for normalizing the second sub-pixel (SP2), the second sub-pixel circuit (SPC2) may be disabled.

[0312] Referring to FIG. 27, through a repair process for normalizing the second sub-pixel (SP2), the first current (I1) output from the first source electrode (S1) of the first driving transistor (DRT1) in the normal first sub-pixel circuit (SPC1) can be supplied not only to the first pixel electrode (PE1) but also to the second pixel electrode (PE2). As a result, the second light-emitting element (ED2) can emit light normally.

[0313] Referring to FIG. 28, when a defect occurs in the first sub-pixel circuit (SPC1), through a repair process for normalizing the first sub-pixel (SP1), the first lower metal connected to the first source electrode (S1) and the second lower metal connected to the second source electrode (S2) can be connected to the overlapping pattern (OP). As a result, a first welding pattern (WPTN1) can be formed between the overlapping pattern (OP) and the first lower metal, and a second welding pattern (WPTN2) can be formed between the overlapping pattern (OP) and the second lower metal.

[0314] And through a repair process for normalizing the first sub-pixel (SP1), the first sub-pixel circuit (SPC1) can be disabled.

[0315] Referring to FIG. 28, through a repair process for normalizing the second sub-pixel (SP2), the second current (I2) output from the second source electrode (S2) of the second driving transistor (DRT2) in the normal second sub-pixel circuit (SPC2) can be supplied not only to the second pixel electrode (PE2) but also to the first pixel electrode (PE1). As a result, the first light-emitting element (ED1) can emit light normally.

[0316] Summarizing the embodiments of the present disclosure described above, it is as follows.

[0317] The display device according to the embodiments of the present disclosure may include a first lower metal directly connected to the first pixel electrode or the first source electrode in the first sub-pixel and overlapping the first active layer, a second lower metal directly connected to the second pixel electrode or the second source electrode in the second sub-pixel and overlapping the second active layer, and an overlapping pattern having one side overlapping at least a part of the first lower metal and the other side overlapping at least a part of the second lower metal.

[0318] The display device according to an embodiment of the present disclosure includes a first driving transistor including a first active layer, a first drain electrode, and a first gate electrode, a first pixel electrode directly connected to a part of the first active layer or electrically connected to a part of the first active layer through an additional first source electrode, a second driving transistor including a second active layer, a second drain electrode, and a second gate electrode, a second pixel electrode directly connected to a part of the second active layer or electrically connected to a part of the second active layer through an additional second source electrode, a first lower metal directly connected to the first pixel electrode or directly connected to the first source electrode and overlapping the first active layer, a second lower metal directly connected to the second pixel electrode or directly connected to the second source electrode and overlapping the second active layer, a first buffer layer disposed on the first lower metal and the second lower metal, an overlapping pattern including a first portion disposed on the first buffer layer and overlapping at least a part of the first lower metal, a second portion overlapping at least a part of the second lower metal, and a third portion between the first portion and the second portion, and a second buffer layer disposed on the overlapping pattern and under the first active layer and the second active layer may be included.

[0319] The distance between the first source electrode and the second source electrode is closer than the distance between a first light-emitting region formed by the first pixel electrode and a second light-emitting region formed by the second pixel electrode.

[0320] The display device according to an embodiment of the present disclosure may further include a gate insulating layer disposed on the first active layer and the second active layer.

[0321] The first source electrode is disposed on the gate insulating layer and may be connected to the first lower metal through holes in the gate insulating layer, the second buffer layer, and the first buffer layer.

[0322] The second source electrode is disposed on the gate insulating layer and may be connected to the second lower metal through holes in the gate insulating layer, the second buffer layer, and the first buffer layer.

[0323] The display device according to an embodiment of the present disclosure may further include a passivation layer disposed on a first source electrode, a first gate electrode, a second source electrode, and a second gate electrode, and an overcoat layer disposed on the passivation layer.

[0324] The first pixel electrode may be disposed on the overcoat layer and connected to the first source electrode through holes in the overcoat layer and the passivation layer. The second pixel electrode may be disposed on the overcoat layer and connected to the second source electrode through holes in the overcoat layer and the passivation layer.

[0325] The first gate electrode may be disposed on the first active layer, and the second gate electrode may be disposed on the second active layer.

[0326] The first source electrode and the second source electrode may equally include a gate electrode material included in the first gate electrode and the second gate electrode.

[0327] As an example of a storage capacitor structure, the display device according to an embodiment of the present disclosure may further include a first storage capacitor formed between the first source electrode and the first gate electrode, and a second storage capacitor formed between the second source electrode and the second gate electrode.

[0328] The first storage capacitor may include a first upper capacitor and a first lower capacitor. The first upper capacitor and the first lower capacitor may be connected in parallel to form the first storage capacitor.

[0329] The second storage capacitor may include a second upper capacitor and a second lower capacitor. The second upper capacitor and the second lower capacitor may be connected in parallel to form the second storage capacitor.

[0330] The first upper capacitor may include a first capacitor electrode corresponding to the first source electrode and a second capacitor electrode including the same material as the first active layer.

[0331] The first lower capacitor may include a third capacitor electrode containing the same material as the overlapping pattern and a fourth capacitor electrode corresponding to the first lower metal.

[0332] The second upper capacitor may include a fifth capacitor electrode corresponding to the second source electrode and a sixth capacitor electrode containing the same material as the second active layer.

[0333] The second lower capacitor may include a seventh capacitor electrode containing the same material as the overlapping pattern and an eighth capacitor electrode corresponding to the second lower metal.

[0334] As another example of the storage capacitor structure, a display device according to an embodiment of the present disclosure may include a first storage capacitor formed between a first pixel electrode and a first gate electrode, and a second storage capacitor formed between a second pixel electrode and a second gate electrode.

[0335] The first storage capacitor may include a first upper capacitor and a first lower capacitor, and the second storage capacitor may include a second upper capacitor and a second lower capacitor.

[0336] The first upper capacitor and the first lower capacitor may be connected in parallel to form a first storage capacitor.

[0337] The first upper capacitor may include a first capacitor electrode containing the same material as the first active layer and a second capacitor electrode containing the same material as the overlapping pattern.

[0338] The first lower capacitor may include the second capacitor electrode and the third capacitor electrode corresponding to the first lower metal.

[0339] The second upper capacitor and the second lower capacitor may be connected in parallel to form a second storage capacitor.

[0340] The second upper capacitor may include a fourth capacitor electrode containing the same material as the second active layer and a fifth capacitor electrode containing the same material as the overlapping pattern.

[0341] The second lower capacitor may include the fifth capacitor electrode and the sixth capacitor electrode corresponding to the first lower metal.

[0342] When a first current is supplied from the first driving transistor to the first pixel electrode and a second current is supplied from the second driving transistor to the second pixel electrode (when it is confirmed that the first sub-pixel and the second sub-pixel are both normal sub-pixels and no repair process is performed), the first portion and the first lower metal may be separated, or the second portion and the second lower metal may be separated.

[0343] When a first current is supplied from the first driving transistor to the first pixel electrode and a second current is supplied from the second driving transistor to the second pixel electrode, at least one of the first lower metal and the second lower metal may be electrically separated from the overlapping pattern.

[0344] The display device according to an embodiment of the present disclosure may further include a connection pattern that connects the first portion and the first lower metal or connects the second portion and the second lower metal. Here, the connection pattern may include the same material as the first source electrode and the second source electrode.

[0345] When a first current is supplied from the first driving transistor to the first pixel electrode and the second pixel electrode, the first portion and the first lower metal may be connected, and the second portion and the second lower metal may be connected.

[0346] The display device according to an embodiment of the present disclosure may further include a driving voltage line for transmitting a driving voltage to the first drain electrode and the second drain electrode.

[0347] When a first current is supplied from a first driving transistor to a first pixel electrode and a second current is supplied from a second driving transistor to a second pixel electrode, at least one of both ends of the overlapping pattern can be connected to a driving voltage line.

[0348] When a first current is supplied from a first driving transistor to a first pixel electrode and a second pixel electrode (when it is confirmed that among a first sub-pixel and a second sub-pixel, the first sub-pixel is a normal sub-pixel and the second sub-pixel is a defective sub-pixel and repair processing is performed), both ends of the overlapping pattern can be electrically disconnected from the driving voltage line.

[0349] When a first current is supplied from a first driving transistor to a first pixel electrode and a second current is supplied from a second driving transistor to a second pixel electrode, the driving voltage line and the first drain electrode are electrically connected, and the driving voltage line and the second drain electrode can be electrically connected.

[0350] When a first current is supplied from a first driving transistor to a first pixel electrode and a second pixel electrode, the driving voltage line and the first drain electrode are electrically connected, and the driving voltage line and the second drain electrode can be electrically disconnected.

[0351] The display device according to an embodiment of the present disclosure may include a data line for transmitting a data voltage, a first scan transistor for controlling a connection between the data line and a first gate electrode, and a second scan transistor for controlling a connection between the data line and a second gate electrode.

[0352] When a first current is supplied from a first driving transistor to a first pixel electrode and a second current is supplied from a second driving transistor to a second pixel electrode, the data line and the first scan transistor are connected, and the data line and the second scan transistor can be connected.

[0353] When a first current is supplied from the first driving transistor to the first pixel electrode and the second pixel electrode, the data line and the first scanning transistor are connected, and the data line and the second scanning transistor may be disconnected.

[0354] The display device according to an embodiment of the present disclosure may include a reference voltage line for transmitting a reference voltage, a first sensing transistor for controlling a connection between the reference voltage line and the first source electrode, and a second sensing transistor for controlling a connection between the reference voltage line and the second source electrode.

[0355] When a first current is supplied from the first driving transistor to the first pixel electrode and a second current is supplied from the second driving transistor to the second pixel electrode, the reference voltage line and the first sensing transistor are connected, and the reference voltage line and the second sensing transistor may be connected.

[0356] When a first current is supplied from the first driving transistor to the first pixel electrode and the second pixel electrode, the reference voltage line and the first sensing transistor are connected, and the reference voltage line and the second sensing transistor may be disconnected.

[0357] The display device according to an embodiment of the present disclosure may include a first sub-pixel including a first driving transistor and a first light-emitting element, a second sub-pixel including a second driving transistor and a second light-emitting element, a first lower metal connected to the first source electrode of the first driving transistor, a second lower metal connected to the second source electrode of the second driving transistor, a first portion overlapping with a part of the first lower metal, a second portion overlapping with a part of the second lower metal, an overlapping pattern including a third portion between the first portion and the second portion, and a first buffer layer disposed between the first lower metal and the second lower metal and the overlapping pattern.

[0358] The first lower metal is disposed below the first active layer of the first driving transistor, the second lower metal is disposed below the first active layer of the second driving transistor, and the overlapping pattern may be disposed below the first lower metal and the second lower metal.

[0359] When a first current is supplied from the first driving transistor to the first pixel electrode and a second current is supplied from the second driving transistor to the second pixel electrode, the first portion and the first lower metal may be separated, or the second portion and the second lower metal may be separated.

[0360] When a first current is supplied from the first driving transistor to the first pixel electrode and the second pixel electrode, the first portion and the first lower metal may be connected, and the second portion and the second lower metal may be connected.

[0361] The distance between the first source electrode and the second source electrode is closer than the distance between the first light-emitting region of the first light-emitting element and the second light-emitting region of the second light-emitting element.

[0362] When a first current is supplied from the first driving transistor to the first pixel electrode and a second current is supplied from the second driving transistor to the second pixel electrode, the overlapping pattern may be electrically connected to the common power line.

[0363] When a first current is supplied from the first driving transistor to the first pixel electrode and the second pixel electrode, the overlapping pattern may be electrically disconnected from the common power line.

[0364] The display panel according to an embodiment of the present disclosure may include a first sub-pixel including a first sub-pixel circuit and a first light-emitting element, a second sub-pixel including a second sub-pixel circuit and a second light-emitting element, a first lower metal connected to the first sub-pixel circuit, a second lower metal connected to the second sub-pixel circuit, a first portion overlapping a part of the first lower metal, a second portion overlapping a part of the second lower metal, an overlapping pattern including a third portion between the first portion and the second portion, and a first buffer layer disposed between the first lower metal and the second lower metal and the overlapping pattern.

[0365] When a first current is supplied from the first sub-pixel circuit to the first light-emitting element and a second current is supplied from the second sub-pixel circuit to the second light-emitting element, the first portion and the first lower metal may be separated, or the second portion and the second lower metal may be separated.

[0366] When a first current is supplied from the first sub-pixel circuit to the first light-emitting element and the second light-emitting element, the first portion and the first lower metal may be connected, and the second portion and the second lower metal may be connected.

[0367] The distance between the first sub-pixel circuit and the second sub-pixel circuit is closer than the distance between the first light-emitting region of the first light-emitting element and the second light-emitting region of the second light-emitting element.

[0368] The display panel according to an embodiment of the present disclosure may further include a common power line adjacent to the overlapping pattern. For example, the common power line may include at least one of a driving voltage line, a reference voltage line, and a base voltage line. For example, the common power line may be a positive voltage line whose voltage level does not change according to time variation.

[0369] When a first current is supplied from the first sub-pixel circuit to the first light-emitting element and a second current is supplied from the second sub-pixel circuit to the second light-emitting element, the overlapping pattern may be electrically connected to the common power line.

[0370] When a first current is supplied from the first sub-pixel circuit to the first light-emitting element and the second light-emitting element, the overlapping pattern may be electrically disconnected from the common power line.

[0371] The display panel according to an embodiment of the present disclosure may further include a substrate, a first active layer disposed in the first sub-pixel circuit, and a second active layer disposed in the second sub-pixel circuit.

[0372] The first lower metal may be disposed under the first active layer and overlap the first active layer. The second lower metal may be disposed under the second active layer and overlap the second active layer.

[0373] The stacked pattern can be disposed within a metal layer between the first lower metal, the second lower metal, and the substrate.

[0374] According to the embodiments of the present disclosure described above, when a defect occurs in a sub-pixel, a display device and a display panel having a repair structure capable of normalizing the sub-pixel can be provided.

[0375] According to the embodiments of the present disclosure, a display device and a display panel having a repair structure that does not induce a decrease in aperture ratio can be provided.

[0376] According to the embodiments of the present disclosure, a display device and a display panel having a repair structure that does not occupy much space can be provided.

[0377] According to the embodiments of the present disclosure, a display device having a repair structure suitable for a high-resolution configuration can be provided.

[0378] According to the embodiments of the present disclosure, a display device and a display panel having a repair structure having high repair performance or a high probability of repair success can be provided. Through this, the manufacturing cost can be reduced and the manufacturing process can be optimized.

[0379] The above description merely exemplarily explains the technical idea of the present disclosure, and those with ordinary knowledge in the technical field to which the present disclosure belongs can make various modifications and variations without departing from the essential characteristics of the present disclosure. In addition, the embodiments disclosed in the present disclosure are not for limiting the technical idea of the present disclosure, but for explanation purposes, so the scope of the technical idea of the present disclosure is not limited by such embodiments.

Description of Reference Numerals

[0380] SP1 First sub-pixel PE1 First pixel electrode S1 First source electrode SP2 Second sub-pixel PE2 Second pixel electrode S2 Second source electrode

Claims

1. A first driving transistor including a first active layer, a first drain electrode, and a first gate electrode; A first pixel electrode directly connected to a part of the first active layer or electrically connected to a part of the first active layer through an additional first source electrode; A second driving transistor including a second active layer, a second drain electrode, and a second gate electrode; A second pixel electrode directly connected to a part of the second active layer or electrically connected to a part of the second active layer through an additional second source electrode; A first lower metal directly connected to the first pixel electrode or directly connected to the first source electrode and overlapping the first active layer; A second lower metal directly connected to the second pixel electrode or directly connected to the second source electrode and overlapping the second active layer; A first buffer layer disposed on the first lower metal and the second lower metal; A superimposed pattern disposed on the first buffer layer, including a first part overlapping at least a part of the first lower metal, a second part overlapping at least a part of the second lower metal, and a third part between the first part and the second part; A display device including a second buffer layer disposed on the superimposed pattern and disposed under the first active layer and the second active layer.

2. The display device according to claim 1, wherein the distance between the first source electrode and the second source electrode is shorter than the distance between a first light-emitting region formed by the first pixel electrode and a second light-emitting region formed by the second pixel electrode.

3. Further including a gate insulating layer disposed on the first active layer and the second active layer, The first source electrode is disposed on the gate insulating layer and is connected to the first lower metal through holes in the gate insulating layer, the second buffer layer, and the first buffer layer, The second source electrode is disposed on the gate insulating layer and is connected to the second lower metal through holes in the gate insulating layer, the second buffer layer, and the first buffer layer. The display device according to claim 1.

4. A passivation layer disposed on the first source electrode, the first gate electrode, the second source electrode, and the second gate electrode; Further including an overcoat layer disposed on the passivation layer. The first pixel electrode is disposed on the overcoat layer and is connected to the first source electrode through holes in the overcoat layer and the passivation layer. The display device according to claim 1, wherein the second pixel electrode is disposed on the overcoat layer and is connected to the second source electrode through holes in the overcoat layer and the passivation layer.

5. The first gate electrode is disposed on the first active layer. The second gate electrode is disposed on the second active layer. The display device according to claim 1, wherein the first source electrode and the second source electrode contain the same gate electrode material as that contained in the first gate electrode and the second gate electrode.

6. A first upper capacitor including a first capacitor electrode corresponding to the first source electrode and a second capacitor electrode containing the same material as the first active layer. A first lower capacitor including a third capacitor electrode containing the same material as the overlapping pattern and a fourth capacitor electrode corresponding to the first lower metal. A second upper capacitor including a fifth capacitor electrode corresponding to the second source electrode and a sixth capacitor electrode containing the same material as the second active layer. Including a second lower capacitor including a seventh capacitor electrode containing the same material as the overlapping pattern and an eighth capacitor electrode corresponding to the second lower metal. The first upper capacitor and the first lower capacitor are connected in parallel to form a first storage capacitor. The display device according to claim 1, wherein the second upper capacitor and the second lower capacitor are connected in parallel to form a second storage capacitor.

7. A first upper capacitor including a first capacitor electrode containing the same material as the first active layer and a second capacitor electrode containing the same material as the overlapping pattern. A first lower capacitor including the second capacitor electrode and a third capacitor electrode corresponding to the first lower metal. A second upper capacitor including a fourth capacitor electrode containing the same material as the second active layer and a fifth capacitor electrode containing the same material as the overlapping pattern. Further including a second lower capacitor including the fifth capacitor electrode and a sixth capacitor electrode corresponding to the first lower metal. The first upper capacitor and the first lower capacitor are connected in parallel to form a first storage capacitor. The display device according to claim 1, wherein the second upper capacitor and the second lower capacitor are connected in parallel to form a second storage capacitor.

8. When a first current is supplied from the first driving transistor to the first pixel electrode and a second current is supplied from the second driving transistor to the second pixel electrode, the first portion and the first lower metal are separated, or the second portion and the second lower metal are separated, the display device according to claim 1, wherein at least one of the first lower metal and the second lower metal is electrically separated from the overlapping pattern.

9. The display device according to claim 8, further comprising a connection pattern connecting the first portion and the first lower metal or connecting the second portion and the second lower metal, the connection pattern including the same material as the first source electrode and the second source electrode.

10. When a first current is supplied from the first driving transistor to the first pixel electrode and the second pixel electrode, the first portion and the first lower metal are connected, and the second portion and the second lower metal are connected. The display device according to claim 1.

11. The display device further includes a driving voltage line for transmitting a driving voltage to the first drain electrode and the second drain electrode. When a first current is supplied from the first driving transistor to the first pixel electrode and a second current is supplied from the second driving transistor to the second pixel electrode, at least one of both ends of the overlapping pattern is connected to the driving voltage line. The display device according to claim 1.

12. The display device further includes a driving voltage line for transmitting a driving voltage to the first drain electrode and the second drain electrode. When a first current is supplied from the first driving transistor to the first pixel electrode and the second pixel electrode, both ends of the overlapping pattern are electrically disconnected from the driving voltage line. The display device according to claim 1.

13. The display device further includes a driving voltage line for transmitting a driving voltage to the first drain electrode and the second drain electrode. When a first current is supplied from the first driving transistor to the first pixel electrode and a second current is supplied from the second driving transistor to the second pixel electrode, the driving voltage line and the first drain electrode are electrically connected, and the driving voltage line and the second drain electrode are electrically connected. The display device according to claim 1, wherein when a first current is supplied from the first driving transistor to the first pixel electrode and the second pixel electrode, the driving voltage line and the first drain electrode are electrically connected, and the driving voltage line and the second drain electrode are electrically disconnected.

14. A data line for transmitting a data voltage; A first scan transistor for controlling the connection between the data line and the first gate electrode; A second scan transistor for controlling the connection between the data line and the second gate electrode, When a first current is supplied from the first driving transistor to the first pixel electrode and a second current is supplied from the second driving transistor to the second pixel electrode, the data line and the first scan transistor are connected, and the data line and the second scan transistor are connected. The display device according to claim 1, wherein when a first current is supplied from the first driving transistor to the first pixel electrode and the second pixel electrode, the data line and the first scan transistor are connected, and the data line and the second scan transistor are disconnected.

15. A reference voltage line for transmitting a reference voltage; A first sensing transistor for controlling the connection between the reference voltage line and the first source electrode; A second sensing transistor for controlling the connection between the reference voltage line and the second source electrode, When a first current is supplied from the first driving transistor to the first pixel electrode and a second current is supplied from the second driving transistor to the second pixel electrode, the reference voltage line and the first sensing transistor are connected, and the reference voltage line and the second sensing transistor are connected. In the display device according to claim 1, when a first current is supplied from the first driving transistor to the first pixel electrode and the second pixel electrode, the reference voltage line and the first sensing transistor are connected, and the reference voltage line and the second sensing transistor are not connected.

16. A first sub-pixel including a first sub-pixel circuit and a first light-emitting element, A second sub-pixel including a second sub-pixel circuit and a second light-emitting element, A first lower metal connected to the first sub-pixel circuit, A second lower metal connected to the second sub-pixel circuit, An overlapping pattern including a first portion overlapping a part of the first lower metal, a second portion overlapping a part of the second lower metal, and a third portion between the first portion and the second portion, A display panel including a first buffer layer disposed between the first lower metal and the second lower metal and the overlapping pattern.

17. A substrate, A first active layer disposed within the first sub-pixel circuit, Further including a second active layer disposed within the second sub-pixel circuit, The first lower metal is disposed under the first active layer and overlaps the first active layer, The second lower metal is disposed under the second active layer and overlaps the second active layer, The display panel according to claim 16, wherein the overlapping pattern is disposed within a metal layer between the first lower metal and the second lower metal and the substrate.

18. In the display panel according to claim 16, a distance between the first sub-pixel circuit and the second sub-pixel circuit is shorter than a distance between a first light-emitting region of the first light-emitting element and a second light-emitting region of the second light-emitting element.

19. When a first current is supplied from the first sub-pixel circuit to the first light-emitting element and a second current is supplied from the second sub-pixel circuit to the second light-emitting element, the first portion and the first lower metal are separated, or the second portion and the second lower metal are separated. When a first current is supplied from the first sub-pixel circuit to the first light-emitting element and the second light-emitting element, the first portion and the first lower metal are connected, and the second portion and the second lower metal are connected. The display panel according to claim 16.

20. Further including a common power supply line adjacent to the overlapping pattern, When a first current is supplied from the first sub-pixel circuit to the first light-emitting element and a second current is supplied from the second sub-pixel circuit to the second light-emitting element, the overlapping pattern is electrically connected to the common power supply line. The display panel according to claim 16, wherein when a first current is supplied from the first sub-pixel circuit to the first light-emitting element and the second light-emitting element, the overlapping pattern is not electrically connected to the common power supply line.

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