Information processing device and information processing method

Abstract

To obtain an information processing device which can detect attack, even when the attack which inserts failure of the same value is performed at the same timing with respect to two arithmetic circuits having the same configuration which are protection objects.SOLUTION: An information processing device comprises: a first arithmetic circuit which performs first calculation on the basis of first data having two or more bits being secret information, and outputs second data; a reversal circuit which reverses the logic of each bit of the first data, and outputs third data; a second arithmetic circuit which has the same circuit arrangement as the first arithmetic circuit, performs second calculation same as the first calculation, on the basis of the third data, and outputs fourth data; a third arithmetic circuit which performs third calculation on the basis of the second data and the fourth data, and outputs fifth data; and a comparison circuit which compares the fifth data with an expectation value based on a value according to the bit number of the first data.SELECTED DRAWING: Figure 1

Description

Technical Field

[0001] The present invention relates to an information processing apparatus and an information processing method.

Background Art

[0002] With the development of IoT technology in recent years, various information processing apparatuses are connected to a network, and as a result, the threat level of secret information being stolen from the information processing apparatus by a physical attack on the information processing apparatus is increasing. Physical attacks include a side-channel attack (Side-Channel Attack, hereinafter referred to as "SCA") and a fault attack (Fault Attack, hereinafter referred to as "FA"). SCA is an attack that steals secret information by analyzing side-channel information such as power consumption or electromagnetic waves generated when the information processing apparatus processes secret information. FA is an attack that steals secret information by physically stimulating the information processing apparatus while it is executing the processing of secret information, intentionally inducing a calculation error, and analyzing its behavior.

[0003] One of the encryption methods is public key encryption. Among the various operations used in public key encryption, scalar multiplication or modular exponentiation is the operation with the dominant and critical computational cost. As a method for accelerating scalar multiplication or modular exponentiation, the binary method is widely implemented. However, in the binary method, since the side-channel information becomes a characteristic waveform according to the value of the input secret information, it is vulnerable to attacks such as simple power analysis (Simple Power Analysis, hereinafter referred to as "SPA"), which is a type of SCA. As countermeasures against SPA, there are a method of inserting dummy operations or the Montgomery ladder method. These make the waveform of the side-channel information have a certain form regardless of the value of the secret information.

[0004] On the one hand, in the FA, there is an attack that identifies secret information by analyzing incorrect calculation results obtained by rewriting a part of the value during the calculation. As a countermeasure against such an attack, there is a method of duplicating the arithmetic circuit to be protected and comparing the calculation results of the two arithmetic circuits. Since the two arithmetic circuits have the same circuit configuration, the same result can be obtained if the same value is input. When one of the arithmetic circuits is attacked by the FA, a calculation error occurs in the attacked arithmetic circuit. Therefore, by comparing the calculation results of the two arithmetic circuits and detecting that the two calculation results are different, it can be detected that an attack by the FA has occurred. The information processing apparatus outputs the correct calculation result if the two calculation results match, while if the two calculation results do not match, it does not output the calculation result or outputs an irrelevant value.

[0005] Note that Patent Document 1 discloses a semiconductor device related to the background art. The semiconductor device is a semiconductor device in which a plurality of IC chips are stacked and capable of executing data processing including cryptographic calculations. The plurality of IC chips execute the same cryptographic calculation in parallel to calculate their respective calculation results. One of the plurality of IC chips has its element surface covered by another IC chip, and compares the plurality of calculation results corresponding to the plurality of IC chips with each other, and controls the content of subsequent data processing based on the comparison result.

Prior Art Document

Patent Document

[0006]

Patent Document 1

Summary of the Invention

Problems to be Solved by the Invention

[0007] According to the method of duplicating the arithmetic circuit to be protected as a countermeasure against FA, two arithmetic circuits having the same circuit configuration perform arithmetic operations with the same value at the same timing. Therefore, if a failure with the same value is inserted at the same timing into both of the two arithmetic circuits during the arithmetic operation, the two arithmetic circuits will generate the same calculation error. Such an attack of inserting a failure with the same value at the same timing into two arithmetic circuits is hereinafter referred to as "double FA". As a result, the arithmetic operation results of the two arithmetic circuits will match, and FA cannot be detected.

[0008] The present invention has been made in view of such circumstances, and an object thereof is to obtain an information processing apparatus and an information processing method capable of detecting an attack in which a failure with the same value is inserted at the same timing into two arithmetic circuits having the same configuration to be protected.

Means for Solving the Problem

[0009] An information processing apparatus according to a first aspect of the present invention includes: a first arithmetic circuit that performs a first arithmetic operation based on a plurality of bits of first data that is secret information and outputs second data; an inversion circuit that inverts the logic of each bit of the first data and outputs third data; a second arithmetic circuit having the same circuit configuration as the first arithmetic circuit, performing a second arithmetic operation identical to the first arithmetic operation based on the third data, and outputting fourth data; a third arithmetic circuit that performs a third arithmetic operation based on the second data and the fourth data and outputs fifth data; and a comparison circuit that compares the fifth data with an expected value based on a value corresponding to the number of bits of the first data.

[0010] According to the first aspect, the first arithmetic circuit performs the first arithmetic operation based on the first data, and the second arithmetic circuit performs the second arithmetic operation based on the third data obtained by inverting the logic of each bit of the first data. Therefore, even when an attack of inserting a failure with the same value at the same timing is performed on the first arithmetic circuit and the second arithmetic circuit having the same circuit configuration, the attack can be detected.

[0011] In the information processing apparatus according to the second aspect of the present invention, in the first aspect, as the first operation, the first arithmetic circuit performs scalar multiplication defined on an elliptic curve based on the first data and coordinate data indicating an arbitrary rational point, and as the second operation, the second arithmetic circuit performs scalar multiplication defined on an elliptic curve based on the third data and the coordinate data, and as the third operation, the third arithmetic circuit performs point addition defined on an elliptic curve based on the second data and the fourth data.

[0012] According to the second aspect, even when an attack is performed in which a failure of the same value is inserted at the same timing with respect to the first arithmetic circuit and the second arithmetic circuit that perform scalar multiplication based on coordinate data indicating an arbitrary rational point, the attack can be detected.

[0013] In the information processing apparatus according to the third aspect of the present invention, in the first aspect, as the first operation, the first arithmetic circuit performs a modular exponentiation operation based on the first data and value data indicating an arbitrary value, and as the second operation, the second arithmetic circuit performs a modular exponentiation operation based on the third data and the value data, and as the third operation, the third arithmetic circuit performs multiplication based on the second data and the fourth data.

[0014] According to the third aspect, even when an attack is performed in which a failure of the same value is inserted at the same timing with respect to the first arithmetic circuit and the second arithmetic circuit that perform modular exponentiation based on value data indicating an arbitrary value, the attack can be detected.

[0015] In the information processing apparatus according to the fourth aspect of the present invention, in the first aspect, as the first operation, the first arithmetic circuit performs scalar multiplication defined on an elliptic curve based on the first data and coordinate data indicating a predetermined base point, and as the second operation, the second arithmetic circuit performs scalar multiplication defined on an elliptic curve based on the third data and the coordinate data, and as the third operation, the third arithmetic circuit performs point addition defined on an elliptic curve based on the second data and the fourth data.

[0016] According to the fourth aspect, even when an attack is performed in which the same value of a fault is inserted at the same timing on the first arithmetic circuit and the second arithmetic circuit that perform scalar multiplication based on the coordinate data indicating a predetermined base point, the attack can be detected.

[0017] In the information processing apparatus according to the fifth aspect of the present invention, in the first aspect, the first arithmetic circuit performs a power residue operation as the first operation based on the first data and value data indicating a predetermined primitive root, and the second arithmetic circuit performs a power residue operation as the second operation based on the third data and the value data, and the third arithmetic circuit performs multiplication as the third operation based on the second data and the fourth data.

[0018] According to the fifth aspect, even when an attack is performed in which the same value of a fault is inserted at the same timing on the first arithmetic circuit and the second arithmetic circuit that perform a power residue operation based on the value data indicating a predetermined primitive root, the attack can be detected.

[0019] The information processing apparatus according to the sixth aspect of the present invention further includes, in any one of the second to fifth aspects, a fourth arithmetic circuit that performs a fourth operation based on a value corresponding to the number of bits of the first data and outputs the expected value.

[0020] According to the sixth aspect, the comparison circuit can obtain the expected value from the fourth arithmetic circuit.

[0021] The information processing apparatus according to the seventh aspect of the present invention further includes, in the fourth or fifth aspect, a storage circuit that stores the expected value calculated by pre-calculation based on a value corresponding to the number of bits of the first data.

[0022] According to the seventh aspect, the comparison circuit can obtain the expected value from the storage circuit. Further, since it is not necessary to sequentially calculate the expected value, the arithmetic load can be reduced.

[0023] In the eighth aspect of the present invention, in the first aspect, the value corresponding to the number of bits of the first data is 2 n represented by -1, where the number of bits is n.

[0024] According to the eighth aspect, regardless of the scalar value or exponent of the first data, an expected value can be calculated based on a value that depends only on the number of bits of the first data.

[0025] In the ninth aspect of the present invention, in the first aspect, the third arithmetic circuit is shared with the first arithmetic circuit or the second arithmetic circuit, so that the third arithmetic is performed by the first arithmetic circuit or the second arithmetic circuit.

[0026] According to the ninth aspect, by sharing the third arithmetic circuit with the first arithmetic circuit or the second arithmetic circuit, the circuit scale and circuit cost can be reduced.

[0027] In the tenth aspect of the present invention, in the second or fourth aspect, the first arithmetic circuit performs a point doubling operation when the logic of the bit of the first data is "0" in the scalar multiplication, and performs a point doubling operation and a point addition operation when the logic of the bit of the first data is "1", and further performs a point addition operation when the logic of the bit of the first data is "0". The second arithmetic circuit performs a point doubling operation when the logic of the bit of the third data is "0" in the scalar multiplication, and performs a point doubling operation and a point addition operation when the logic of the bit of the third data is "1", and further performs a point addition operation when the logic of the bit of the third data is "0".

[0028] According to the tenth aspect, it is possible to provide resistance against attacks such as simple power analysis.

[0029] In the information processing apparatus according to the eleventh aspect of the present invention, in the third or fifth aspect, in the power residue operation, the first arithmetic circuit performs a square multiplication when the logic of the bit of the first data is "0", and performs a square multiplication and a multiplication when the logic of the bit of the first data is "1", and further performs a multiplication when the logic of the bit of the first data is "0". The second arithmetic circuit performs a square multiplication when the logic of the bit of the third data is "0" in the power residue operation, and performs a square multiplication and a multiplication when the logic of the bit of the third data is "1", and further performs a multiplication when the logic of the bit of the third data is "0".

[0030] According to the eleventh aspect, it is possible to provide resistance against attacks such as simple power analysis.

[0031] In the information processing apparatus according to the twelfth aspect of the present invention, in the second or fourth aspect, in the scalar multiplication, the first arithmetic circuit performs a point doubling when the logic of the bit of the first data is "0", and performs a point doubling and a point addition when the logic of the bit of the first data is "1", and further performs a standby process corresponding to the processing time of the point addition when the logic of the bit of the first data is "0". The second arithmetic circuit performs a point doubling when the logic of the bit of the third data is "0" in the scalar multiplication, and performs a point doubling and a point addition when the logic of the bit of the third data is "1", and further performs a standby process corresponding to the processing time of the point addition when the logic of the bit of the third data is "0".

[0032] According to the twelfth aspect, it is possible to provide resistance against attacks such as simple power analysis. Further, instead of the additional point addition when the logic of the bit is "0", a standby process corresponding to the processing time of the point addition is performed, so that the power consumption can be reduced.

[0033] The information processing apparatus according to the 13th aspect of the present invention, in the 3rd or 5th aspect, in the power residue operation, the first arithmetic circuit performs a square multiplication when the logic of the bit of the first data is "0", and performs a square multiplication and a multiplication when the logic of the bit of the first data is "1", and further performs a standby process corresponding to the processing time of the multiplication when the logic of the bit of the first data is "0". The second arithmetic circuit performs a square multiplication when the logic of the bit of the third data is "0" in the power residue operation, and performs a square multiplication and a multiplication when the logic of the bit of the third data is "1", and further performs a standby process corresponding to the processing time of the multiplication when the logic of the bit of the third data is "0".

[0034] According to the 13th aspect, it is possible to provide resistance against attacks such as simple power analysis. Also, instead of the additional multiplication when the logic of the bit is "0", a standby process corresponding to the processing time of the multiplication is performed, so that power consumption can be reduced.

[0035] The information processing apparatus according to the 14th aspect of the present invention, in the 2nd or 4th aspect, in the scalar multiplication, the first arithmetic circuit performs a point doubling when the logic of the bit of the first data is "0", and performs a point doubling and a point addition in parallel when the logic of the bit of the first data is "1", and further performs a standby process corresponding to the processing time difference between the point addition and the point doubling when the logic of the bit of the first data is "0". The second arithmetic circuit performs a point doubling when the logic of the bit of the third data is "0" in the scalar multiplication, and performs a point doubling and a point addition in parallel when the logic of the bit of the third data is "1", and further performs a standby process corresponding to the processing time difference between the point addition and the point doubling when the logic of the bit of the third data is "0".

[0036] According to the 14th aspect, it is possible to provide resistance against attacks such as simple power analysis. Also, instead of the additional point addition when the logic of the bit is "0", a standby process corresponding to the processing time difference between the point addition and the point doubling is performed, so that power consumption can be reduced.

[0037] In the 15th aspect of the present invention, in the 3rd or 5th aspect, in the power residue operation, when the logic of the bit of the first data is "0", the first arithmetic circuit performs a square multiplication, and when the logic of the bit of the first data is "1", the first arithmetic circuit performs a square multiplication and a multiplication in parallel. When the logic of the bit of the first data is "0", the first arithmetic circuit further performs a standby process corresponding to the processing time difference between the multiplication and the square multiplication. In the power residue operation, when the logic of the bit of the third data is "0", the second arithmetic circuit performs a square multiplication, and when the logic of the bit of the third data is "1", the second arithmetic circuit performs a square multiplication and a multiplication in parallel. When the logic of the bit of the first data is "0", the second arithmetic circuit further performs a standby process corresponding to the processing time difference between the multiplication and the square multiplication.

[0038] According to the 15th aspect, it is possible to provide resistance against attacks such as simple power analysis. Further, instead of an additional multiplication when the logic of the bit is "0", a standby process corresponding to the processing time difference between the multiplication and the square multiplication is performed, so that power consumption can be reduced.

[0039] In the information processing method according to the 16th aspect of the present invention, an information processing apparatus performs a first operation based on first data of a plurality of bits that is secret information, outputs second data, inverts the logic of each bit of the first data, outputs third data, performs a second operation that is the same as the first operation based on the third data, outputs fourth data, performs a third operation based on the second data and the fourth data, outputs fifth data, and compares the fifth data with an expected value based on a value corresponding to the number of bits of the first data.

[0040] According to the 16th aspect, the information processing apparatus performs a first operation based on the first data and performs a second operation based on the third data obtained by inverting the logic of each bit of the first data. Therefore, even when an attack that inserts a failure of the same value at the same timing is performed on the arithmetic circuit that performs the first operation and the arithmetic circuit that performs the second operation, the attack can be detected.

Advantages of the Invention

[0041] According to the present invention, even when an attack is performed in which the same value of a fault is inserted at the same timing into two arithmetic circuits having the same configuration to be protected, it is possible to detect the attack.

Brief Description of the Drawings

[0042]

Figure 1

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Figure 15

Best Mode for Carrying Out the Invention

[0043] Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings. Note that elements denoted by the same reference numerals in different drawings represent the same or corresponding elements. Also, the following multiple embodiments can be arbitrarily combined and applied.

[0044] FIG. 1 is a diagram schematically showing the configuration of an information processing apparatus 1 according to the present invention. The information processing apparatus 1 includes a first arithmetic circuit 11, a second arithmetic circuit 12, a third arithmetic circuit 13, a fourth arithmetic circuit 14, an inversion circuit 15, a memory circuit 16, and a comparison circuit 17. The first arithmetic circuit 11 performs a first operation based on a plurality of bits of first data D1, which is secret information, and data D6, and outputs second data D2. The inversion circuit 15 inverts the logic of each bit of the first data D1 and outputs third data D3. The second arithmetic circuit 12 has the same circuit configuration as the first arithmetic circuit 11, performs a second operation identical to the first operation based on the third data D3 and the data D6, and outputs fourth data D4. The third arithmetic circuit 13 performs a third operation based on the second data D2 and the fourth data D4, and outputs fifth data D5. The fourth arithmetic circuit 14 performs a fourth operation based on a value D7 corresponding to the number of bits of the first data D1 and data D8 identical to the data D6, and outputs an expected value D9. The memory circuit 16 stores the expected value D9. The comparison circuit 17 compares the fifth data D5 with the expected value D9 and outputs data D10 indicating the comparison result.

[0045] (First Embodiment) FIG. 2 is a diagram schematically showing the configuration of an information processing apparatus 1A according to the first embodiment of the present invention. The information processing apparatus 1A is obtained by applying the information processing apparatus 1 to the elliptic curve cryptography included in public key cryptography. The information processing apparatus 1A includes a scalar multiplication circuit 11A corresponding to the first arithmetic circuit 11, a scalar multiplication circuit 12A corresponding to the second arithmetic circuit 12, a point addition circuit 13A corresponding to the third arithmetic circuit 13, a scalar multiplication circuit 14A corresponding to the fourth arithmetic circuit 14, an inversion circuit 15A corresponding to the inversion circuit 15, a storage circuit 16A corresponding to the storage circuit 16, and a comparison circuit 17A corresponding to the comparison circuit 17.

[0046] In elliptic curve cryptography, the arithmetic cost of scalar multiplication is dominant and critical. The scalar multiplication circuits 11A, 12A, and 14A perform scalar multiplication at high speed using the binary method.

[0047] The scalar multiplication circuit 11A performs scalar multiplication defined on an elliptic curve based on the first data D1A and the coordinate data D6A1 as the first operation. The first data D1A indicates an n-bit scalar value k. n is, for example, 256, but is not limited thereto. The first data D1A may be secret information such as a secret key. The coordinate data D6A1 indicates the coordinates (X coordinate and Y coordinate) of an arbitrary rational point P on the elliptic curve. The coordinate data D6A1 may be public information such as a public key or public parameters. The scalar multiplication circuit 11A outputs second data D2A indicating a value kP obtained by scalar multiplying the scalar value k and the rational point P.

[0048] The inversion circuit 15A inverts the logic of each bit of the first data D1A and outputs third data D3A. The third data D3A indicates an n-bit inverted scalar value k' obtained by inverting the logic of all bits of the n-bit scalar value k. The inversion circuit 15A may invert the logic of each bit of the n-bit first data D1A one by one in order, or may invert all bits simultaneously.

[0049] The scalar multiplication circuit 12A performs scalar multiplication defined on the elliptic curve as the second operation based on the third data D3A and the coordinate data D6A1. The scalar multiplication circuit 12A outputs fourth data D4A indicating a value k'P obtained by scalar multiplying the inverted scalar value k' and the rational point P.

[0050] The point addition circuit 13A performs point addition defined on the elliptic curve as the third operation based on the second data D2A input from the scalar multiplication circuit 11A and the fourth data D4A input from the scalar multiplication circuit 12A. The point addition circuit 13A outputs fifth data D5A indicating a value (k + k')P obtained by point adding the value kP and the value k'P.

[0051] The scalar multiplication circuit 14A performs scalar multiplication defined on the elliptic curve as the fourth operation based on a value D7A corresponding to the number of bits n of the first data D1A and the same coordinate data D8A1 as the coordinate data D6A1. The value D7A corresponding to the number of bits n of the first data D1A is represented by 2 n - 1. The scalar multiplication circuit 14A outputs an expected value D9A indicating a value (2 n - 1)P obtained by scalar multiplying the value 2 n - 1 and the rational point P.

[0052] The scalar multiplication circuit 14A calculates the expected value D9A in advance by pre - calculation before the processing by the scalar multiplication circuits 11A and 12A, and stores the calculated expected value D9A in the storage circuit 16A. Note that the storage circuit 16A may be omitted, and the expected value D9A may be input from the scalar multiplication circuit 14A to the comparison circuit 17A.

[0053] FIG. 3 is a diagram showing a simplified configuration of the scalar multiplication circuits 11A and 12A. The scalar multiplication circuits 11A and 12A include a point doubling circuit 21 that performs point doubling and a point addition circuit 22 that performs point addition. Point doubling means doubling a point on an elliptic curve. Point addition means adding points on an elliptic curve. The point doubling circuit 21 and the point addition circuit 22 may be physically configured as separate circuits. For example, only the point doubling circuit 21 may be arranged inside the scalar multiplication circuits 11A and 12A, and the point addition circuit 22 may be arranged outside the scalar multiplication circuits 11A and 12A.

[0054] The point addition circuit 13A may omit its individual implementation by being shared with the point addition circuit 22 included in the scalar multiplication circuit 11A or the scalar multiplication circuit 12A. In this case, the third operation is performed by the point addition circuit 22 included in the scalar multiplication circuit 11A or the scalar multiplication circuit 12A. Similarly, the scalar multiplication circuit 14A may omit its individual implementation by being shared with the scalar multiplication circuit 11A or the scalar multiplication circuit 12A. In this case, the fourth operation is performed by the scalar multiplication circuit 11A or the scalar multiplication circuit 12A. Thereby, the circuit scale and the circuit cost can be reduced.

[0055] Referring to FIG. 2, the comparison circuit 17A receives the fifth data D5A from the point addition circuit 13A and the expected value D9A from the storage circuit 16A. The comparison circuit 17A compares the value (k + k')P indicated by the fifth data D5A with the value (2 n - 1)P and outputs data D10 indicating the comparison result.

[0056] When the scalar multiplication circuits 11A and 12A do not receive FA, since k + k' = 2 n - 1, the value (k + k')P and the value (2 n - 1)P match. When only one of the scalar multiplication circuits 11A and 12A receives FA, a calculation error occurs only in the attacked scalar multiplication circuit 11A or 12A. Therefore, the value (k + k')P and the value (2 n-1) It does not match P. Also, when the scalar multiplication circuits 11A and 12A receive a double FA, since the scalar multiplication circuits 11A and 12A perform operations based on the first data D1A and the third data D3A with inverted logic, the value (k + k')P and the value (2 n -1) It does not match P. That is, when the scalar multiplication circuits 11A and 12A do not receive an FA, the value (k + k')P and the value (2 n -1) match P, and when the scalar multiplication circuits 11A and 12A receive an FA or a double FA, the value (k + k')P and the value (2 n -1) do not match P.

[0057] Based on the data D10, when the information processing apparatus 1A determines that the value (k + k')P and the value (2 n -1) match P, it outputs the correct operation result (for example, the second data D2A). On the other hand, based on the data D10, when the information processing apparatus 1A determines that the value (k + k')P and the value (2 n -1) do not match P, it does not output the correct operation result or outputs an irrelevant value.

[0058] According to the information processing apparatus 1 according to the present invention, the first arithmetic circuit 11 performs a first operation based on the first data D1, and the second arithmetic circuit 12 performs a second operation based on the third data D3 in which the logic of each bit of the first data D1 is inverted. Therefore, even when an attack (double FA) in which a failure of the same value is inserted at the same timing is performed on the first arithmetic circuit 11 and the second arithmetic circuit 12 having the same circuit configuration, the attack can be detected.

[0059] Also, according to the information processing apparatus 1A according to the first embodiment, even when an attack in which a failure of the same value is inserted at the same timing is performed on the scalar multiplication circuits 11A and 12A that perform scalar multiplication based on the coordinate data D6A1 indicating an arbitrary rational point P, the attack can be detected.

[0060] Also, according to the information processing apparatus 1A according to the first embodiment, the value D7A corresponding to the number of bits n of the first data D1A is 2 nIt is represented by -1. Therefore, regardless of the scalar value k of the first data D1A, the expected value D9A can be calculated based on the value D7A corresponding only to the number of bits n of the first data D1A.

[0061] (Second Embodiment) FIG. 4 is a diagram schematically showing the configuration of the information processing apparatus 1B according to the second embodiment of the present invention. The information processing apparatus 1B is obtained by applying the information processing apparatus 1 to the RSA cipher included in the public key cipher. However, it is not limited to the RSA cipher, and any public key cipher using the power residue operation may be used. The information processing apparatus 1B includes a power residue operation circuit 11B corresponding to the first operation circuit 11, a power residue operation circuit 12B corresponding to the second operation circuit 12, a multiplication circuit 13B corresponding to the third operation circuit 13, a power residue operation circuit 14B corresponding to the fourth operation circuit 14, an inversion circuit 15B corresponding to the inversion circuit 15, a storage circuit 16B corresponding to the storage circuit 16, and a comparison circuit 17B corresponding to the comparison circuit 17.

[0062] In the RSA cipher, the operation cost of the power residue operation is dominant and critical. The power residue operation circuits 11B, 12B, and 14B perform the power residue operation at high speed using the binary method.

[0063] The power residue operation circuit 11B performs a power residue operation based on the first data D1B and the value data D6B1 as the above-described first operation. The first data D1B indicates the value of the n-bit exponent k. n is, for example, 2048, but is not limited thereto. The first data D1B may be secret information such as a secret key. The value data D6B1 indicates an arbitrary value of the base c. The value data D6B1 may be public information such as a public parameter. The power residue operation circuit 11B outputs the second data D2B indicating the value c k using the exponent k and the base c.

[0064] The inversion circuit 15B inverts the logic of each bit of the first data D1B and outputs the third data D3B. The third data D3B indicates an n-bit inverted power exponent k' in which the logic of all bits of the n-bit power exponent k is inverted. The inversion circuit 15B may invert the logic of each bit of the n-bit first data D1B one by one in order, or may invert all bits simultaneously.

[0065] Based on the third data D3B and the value data D6B1 as the above second operation, the power residue operation circuit 12B performs a power residue operation. The power residue operation circuit 12B outputs the fourth data D4B indicating the value c k’ using the inverted power exponent k' and the base c.

[0066] Based on the second data D2B input from the power residue operation circuit 11B and the fourth data D4B input from the power residue operation circuit 12B as the above third operation, the multiplication circuit 13B performs a multiplication. The multiplication circuit 13B outputs the fifth data D5B indicating the value c k and the value c k’ multiplied by each other, which is the value c (k+k’) .

[0067] In this embodiment, the power residue operation and the multiplication are defined over a finite field. When the modulus is p, the calculation formulas are represented as follows respectively.

[0068] Power residue operation: c k mod p or c k’ mod p Multiplication: c k ×c k’ mod p

[0069] Based on the value D7B corresponding to the number of bits n of the first data D1B and the same value data D8B1 as the value data D6B1 as the above fourth operation, the power residue operation circuit 14B performs a power residue operation. The value D7B corresponding to the number of bits n of the first data D1B is represented by 2 n -1. The power residue operation circuit 14B uses the value 2 nOutput the expected value D9B that indicates the value Z1 using -1 and the base c. The value Z1 is represented as follows.

[0070] [Number]

[0071] The power residue operation circuit 14B pre - calculates the expected value D9B by pre - calculation before the processing by the power residue operation circuits 11B and 12B is started, and stores the calculated expected value D9B in the storage circuit 16B. Note that the storage circuit 16B may be omitted, and the expected value D9B may be input from the power residue operation circuit 14B to the comparison circuit 17B.

[0072] FIG. 5 is a diagram showing a simplified configuration of the power residue operation circuits 11B and 12B. The power residue operation circuits 11B and 12B include a squaring circuit 31 that performs squaring and a multiplication circuit 32 that performs multiplication. The squaring and multiplication mean squaring and multiplication defined over a finite field. The squaring circuit 31 and the multiplication circuit 32 may be physically configured as separate circuits. For example, only the squaring circuit 31 may be arranged inside the power residue operation circuits 11B and 12B, and the multiplication circuit 32 may be arranged outside the power residue operation circuits 11B and 12B. The multiplication circuit 13B may share the multiplication circuit 32 included in the power residue operation circuit 11B or the power residue operation circuit 12B, and thus the individual implementation of the multiplication circuit 13B may be omitted. In this case, the third operation is performed by the multiplication circuit 32 included in the power residue operation circuit 11B or the power residue operation circuit 12B. Similarly, the power residue operation circuit 14B may share the power residue operation circuit 11B or the power residue operation circuit 12B, and thus the individual implementation of the power residue operation circuit 14B may be omitted. In this case, the fourth operation is performed by the power residue operation circuit 11B or the power residue operation circuit 12B. Thereby, the circuit scale and the circuit cost can be reduced.

[0073] Referring to FIG. 4, the fifth data D5B is input to the comparison circuit 17B from the multiplication circuit 13B, and the expected value D9B is input from the storage circuit 16B. The comparison circuit 17B uses the value c indicated by the fifth data D5B(k+k’) Compare it with the value Z1 indicated by the expected value D9B, and output data D10 indicating the comparison result.

[0074] When the exponentiation remainder arithmetic circuits 11B and 12B do not receive FA, k + k' = 2 n is -1, so the value c (k+k’) matches the value Z1. When only one of the exponentiation remainder arithmetic circuits 11B and 12B receives FA, a calculation error occurs only in the exponentiation remainder arithmetic circuit 11B or 12B that has been attacked, so the value c (k+k’) does not match the value Z1. Also, when the exponentiation remainder arithmetic circuits 11B and 12B receive double FA, the exponentiation remainder arithmetic circuits 11B and 12B perform operations based on the first data D1B and the third data D3B whose logic has been inverted, so the value c (k+k’) does not match the value Z1. That is, when the exponentiation remainder arithmetic circuits 11B and 12B do not receive FA, the value c (k+k’) matches the value Z1, and when the exponentiation remainder arithmetic circuits 11B and 12B receive FA or double FA, the value c (k+k’) does not match the value Z1.

[0075] Based on the data D10, the information processing apparatus 1B outputs the correct calculation result (for example, the second data D2B) when the value c (k+k’) matches the value Z1. On the other hand, based on the data D10, the information processing apparatus 1B does not output the correct calculation result or outputs an irrelevant value when the value c (k+k’) does not match the value Z1.

[0076] According to the information processing apparatus 1B according to the second embodiment, even when an attack is performed to insert a failure of the same value at the same timing on the exponentiation remainder arithmetic circuits 11B and 12B that should perform an exponentiation remainder operation based on the value data D6B1 indicating an arbitrary value of the base c, the attack can be detected.

[0077] (Third Embodiment) FIG. 6 is a diagram schematically showing the configuration of the information processing apparatus 1C according to the third embodiment of the present invention. The arithmetic circuit to be protected in the third embodiment is, for example, a scalar multiplication circuit of ECDSA or EdDSA of a digital signature protocol. Hereinafter, the description will focus on the differences from the first embodiment.

[0078] The scalar multiplication circuit 11A performs, as the first operation, a scalar multiplication defined on an elliptic curve based on the first data D1A and the coordinate data D6A2. The coordinate data D6A2 indicates the coordinates (X coordinate and Y coordinate) of a predetermined base point G on the elliptic curve. The scalar multiplication circuit 11A outputs second data D2A indicating a value kG obtained by scalar multiplying the scalar value k and the base point G.

[0079] The scalar multiplication circuit 12A performs, as the second operation, a scalar multiplication defined on an elliptic curve based on the third data D3A and the coordinate data D6A2. The scalar multiplication circuit 12A outputs fourth data D4A indicating a value k'G obtained by scalar multiplying the inverted scalar value k' and the base point G.

[0080] The point addition circuit 13A performs, as the third operation, a point addition defined on an elliptic curve based on the second data D2A input from the scalar multiplication circuit 11A and the fourth data D4A input from the scalar multiplication circuit 12A. The point addition circuit 13A outputs fifth data D5A indicating a value (k + k')G obtained by point adding the value kG and the value k'G.

[0081] The scalar multiplication circuit 14A performs, as the fourth operation, a scalar multiplication defined on an elliptic curve based on a value D7A corresponding to the number of bits n of the first data D1A and the same coordinate data D8A2 as the coordinate data D6A2. The value D7A corresponding to the number of bits n of the first data D1A is represented by 2 n -1. The scalar multiplication circuit 14A outputs an expected value D9A indicating a value (2 n -1)G obtained by scalar multiplying 2 n -1 and the base point G.

[0082] The scalar multiplication circuit 14A pre-calculates the expected value D9A by pre-calculation before the processing by the scalar multiplication circuits 11A and 12A starts, and stores the calculated expected value D9A in the storage circuit 16A. Note that the storage circuit 16A may be omitted, and the expected value D9A may be input from the scalar multiplication circuit 14A to the comparison circuit 17A. Also, when the base point G is a fixed value, the base point G does not change even if the scalar value k is changed. Therefore, instead of the scalar multiplication circuit 14A, software or the like may be used to pre-calculate the expected value D9A, and the calculated expected value D9A may be stored in the storage circuit 16A.

[0083] The comparison circuit 17A receives the fifth data D5A from the point addition circuit 13A and the expected value D9A from the storage circuit 16A. The comparison circuit 17A compares the value (k + k')G indicated by the fifth data D5A with the value (2 n - 1)G indicated by the expected value D9A, and outputs data D10 indicating the comparison result.

[0084] When the scalar multiplication circuits 11A and 12A do not receive FA, k + k' = 2 n - 1, so the value (k + k')G and the value (2 n - 1)G match. When only one of the scalar multiplication circuits 11A and 12A receives FA, a calculation error occurs only in the attacked scalar multiplication circuit 11A or 12A, so the value (k + k')G and the value (2 n - 1)G do not match. Also, when the scalar multiplication circuits 11A and 12A receive double FA, the scalar multiplication circuits 11A and 12A perform operations based on the first data D1A and the third data D3A whose logic is inverted, so the value (k + k')G and the value (2 n - 1)G do not match. That is, when the scalar multiplication circuits 11A and 12A do not receive FA, the value (k + k')G and the value (2 n - 1)G match, and when the scalar multiplication circuits 11A and 12A receive FA or double FA, the value (k + k')G and the value (2 n - 1)G do not match.

[0085] Based on the data D10, the information processing apparatus 1C outputs the correct calculation result (for example, the second data D2A) when the value (k + k')G matches the value (2 n - 1)G. On the other hand, when the value (k + k')G does not match the value (2 n - 1)G based on the data D10, the information processing apparatus 1C does not output the correct calculation result or outputs an irrelevant value.

[0086] According to the third embodiment, even when an attack is performed in which a failure of the same value is inserted at the same timing on the scalar multiplication circuits 11A and 12A that perform scalar multiplication based on the coordinate data D6A2 indicating a predetermined base point G, the attack can be detected.

[0087] (Fourth Embodiment) FIG. 7 is a diagram schematically showing the configuration of the information processing apparatus 1D according to the fourth embodiment of the present invention. The arithmetic circuit to be protected in the fourth embodiment is, for example, the exponentiation remainder arithmetic circuit of DSA of the digital signature protocol. Hereinafter, the description will focus on the differences from the second embodiment.

[0088] The exponentiation remainder arithmetic circuit 11B performs an exponentiation remainder operation based on the first data D1B and the value data D6B2 as the above-described first operation. The value data D6B2 indicates the value of a predetermined primitive root g. The primitive root g may be any fixed value. The exponentiation remainder arithmetic circuit 11B outputs the second data D2B indicating the value g k using the exponent k and the primitive root g.

[0089] The exponentiation remainder arithmetic circuit 12B performs an exponentiation remainder operation based on the third data D3B and the value data D6B2 as the above-described second operation. The exponentiation remainder arithmetic circuit 12B outputs the fourth data D4B indicating the value g k’ using the inverse exponent k' and the primitive root g.

[0090] The multiplication circuit 13B performs multiplication based on the second data D2B input from the power residue operation circuit 11B and the fourth data D4B input from the power residue operation circuit 12B as the above third operation. The multiplication circuit 13B outputs fifth data D5B indicating a value g k multiplied by a value g k’ resulting in a value g (k+k’) .

[0091] In this embodiment, the power residue operation and multiplication are defined over a finite field. When the modulus is p, the calculation formulas are as follows respectively.

[0092] Power residue operation: g k mod p or g k’ mod p Multiplication: g k ×g k’ mod p

[0093] The power residue operation circuit 14B performs a power residue operation based on a value D7B corresponding to the number of bits n of the first data D1B and the same value data D8B2 as the value data D6B2 as the above fourth operation. The value D7B corresponding to the number of bits n of the first data D1B is represented by 2 n -1. The power residue operation circuit 14B outputs an expected value D9B indicating a value Z2 using 2 n -1 and the primitive root g. The value Z2 is represented as follows.

[0094]

Equation

[0095] The power residue operation circuit 14B calculates the expected value D9B in advance by pre-calculation before the processing by the power residue operation circuits 11B and 12B is started, and stores the calculated expected value D9B in the storage circuit 16B. Note that the storage circuit 16B may be omitted, and the expected value D9B may be input from the power residue operation circuit 14B to the comparison circuit 17B. Further, when the primitive root g is a fixed value, the primitive root g does not change even if the scalar value k is changed. Therefore, instead of the power residue operation circuit 14B, software or the like may be used to calculate the expected value D9B in advance, and the calculated expected value D9B may be stored in the storage circuit 16B.

[0096] The comparison circuit 17B receives the fifth data D5B from the multiplication circuit 13B and the expected value D9B from the storage circuit 16B. The comparison circuit 17B compares the value g (k+k’) indicated by the fifth data D5B with the value Z2 indicated by the expected value D9B, and outputs data D10 indicating the comparison result.

[0097] When the power residue operation circuits 11B and 12B have not received FA, k + k' = 2 n -1, so the value g (k+k’) matches the value Z2. When only one of the power residue operation circuits 11B and 12B receives FA, a calculation error occurs only in the attacked power residue operation circuit 11B or 12B, so the value g (k+k’) does not match the value Z2. Further, when the power residue operation circuits 11B and 12B receive double FA, the power residue operation circuits 11B and 12B perform operations based on the first data D1B and the third data D3B whose logic is inverted, so the value g (k+k’) does not match the value Z2. That is, when the power residue operation circuits 11B and 12B have not received FA, the value g (k+k’) matches the value Z2, and when the power residue operation circuits 11B and 12B receive FA or double FA, the value g (k+k’) does not match the value Z2.

[0098] The information processing apparatus 1D, based on the data D10, the value g (k+k’)When it matches the value Z2, it outputs the correct calculation result (e.g., the second data D2B). On the other hand, based on the data D10, the information processing apparatus 1D (k+k’) When it does not match the value Z2, it does not output the correct calculation result or outputs an irrelevant value.

[0099] According to the information processing apparatus 1D according to the fourth embodiment, even when an attack is performed in which a failure of the same value is inserted at the same timing on the exponentiation remainder operation circuits 11B and 12B that should perform the exponentiation remainder operation based on the value data D6B2 indicating the predetermined primitive root g, the attack can be detected.

[0100] (First modification example) Hereinafter, based on the first embodiment, the first modification example will be described. By changing the rational point P to the base point G, the first modification example is also applicable to the third embodiment.

[0101] FIG. 8 is a diagram showing the processing in the scalar multiplication circuits 11A and 12A according to the first modification example. In the example shown in FIG. 8, the scalar value k is 01011 ···. Therefore, the inverted scalar value k' is 10100 ···.

[0102] As shown in (A), the scalar multiplication circuit 11A in which the simple binary method is implemented performs point doubling by the point doubling circuit 21 when the logic of the bit of the scalar value k is "0", and performs point doubling by the point doubling circuit 21 and point addition by the point addition circuit 22 when the logic of the bit of the scalar value k is "1". "D" in the figure means point doubling, and "A" means point addition. In the example shown in FIG. 8, the processing time of point addition is longer than the processing time of point doubling, but this is not limited to this example. Hereinafter, the case where the processing time of point addition is longer than the processing time of point doubling will be assumed for explanation.

[0103] As shown in (B), in the scalar multiplication circuit 12A where a simple binary method is implemented, when the logic of the bit of the inverted scalar value k' is "0", point doubling by the point doubling circuit 21 is performed, and when the logic of the bit of the inverted scalar value k' is "1", point doubling by the point doubling circuit 21 and point addition by the point addition circuit 22 are performed.

[0104] Since the power consumption of the information processing apparatus 1A differs between point doubling and point addition, the logic of the scalar value k or the inverted scalar value k' is determined by SPA.

[0105] Therefore, as shown in (C), in the scalar multiplication circuit 11A according to the first modification example, when the logic of the bit of the scalar value k is "0", point doubling by the point doubling circuit 21 is performed, and following the point doubling, point addition 41 by the point addition circuit 22 is further performed. The scalar multiplication circuit 11A may discard the operation result of the additionally inserted point addition 41 or propagate it to the operation of the next bit. Examples of discarding the operation result of point addition 41 include Add and Double Always. Examples of propagating the operation result of point addition 41 to the operation of the next bit include the Montgomery ladder method or BRIP (Binary Expansion with Random Initial Point). Also, when the logic of the bit of the scalar value k is "1", the scalar multiplication circuit 11A performs point doubling by the point doubling circuit 21 and point addition by the point addition circuit 22.

[0106] Also, as shown in (D), in the scalar multiplication circuit 12A according to the first modification example, when the logic of the bit of the inverted scalar value k' is "0", point doubling by the point doubling circuit 21 is performed, and following the point doubling, point addition 42 by the point addition circuit 22 is further performed. The scalar multiplication circuit 12A may discard the operation result of the additionally inserted point addition 42 or propagate it to the operation of the next bit. Also, when the logic of the bit of the inverted scalar value k' is "1", the scalar multiplication circuit 12A performs point doubling by the point doubling circuit 21 and point addition by the point addition circuit 22.

[0107] As shown in (E), the power consumption of the information processing apparatus 1A within one-bit processing period is the total power consumption of two dot multiplications and two dot additions (2D + 2A), which is common to all bits.

[0108] According to the first modification example, by inserting the dot additions 41 and 42, the waveform of the side-channel information such as power consumption can be made into a constant form regardless of the values of the secret information (scalar value k and inverted scalar value k'). As a result, not only resistance to FA and double FA but also resistance to SPA can be provided.

[0109] (Second Modification Example) Hereinafter, based on the second embodiment, the second modification example will be described. By changing the base c to the primitive root g, the second modification example is also applicable to the fourth embodiment.

[0110] FIG. 9 is a diagram showing the processing in the power residue operation circuits 11B and 12B according to the second modification example. In the example shown in FIG. 9, the power exponent k is 01011 ···. Therefore, the inverted power exponent k' is 10100 ···.

[0111] As shown in (A), the power residue operation circuit 11B in which a simple binary method is implemented performs a squaring operation by the squaring circuit 31 when the logic of the bit of the power exponent k is "0", and performs a squaring operation by the squaring circuit 31 and a multiplication operation by the multiplication circuit 32 when the logic of the bit of the power exponent k is "1". "S" in the figure means squaring, and "M" means multiplication. In the example shown in FIG. 9, the processing time of multiplication is longer than the processing time of squaring, but this is not limited to this example. Hereinafter, the description will be made assuming that the processing time of multiplication is longer than the processing time of squaring.

[0112] As shown in (B), the power residue operation circuit 12B in which a simple binary method is implemented performs a squaring operation by the squaring circuit 31 when the logic of the bit of the inverted power exponent k' is "0", and performs a squaring operation by the squaring circuit 31 and a multiplication operation by the multiplication circuit 32 when the logic of the bit of the inverted power exponent k' is "1".

[0113] Since the power consumption of the information processing apparatus 1B differs between squaring and multiplication, the SPA discriminates the logic of the exponent k or the inverse exponent k'.

[0114] Therefore, as shown in (C), when the logic of the bit of the exponent k in the second modification example is “0”, the modular exponentiation circuit 11B according to the second modification example performs squaring by the squaring circuit 31, and subsequent to the squaring, further performs multiplication 43 by the multiplication circuit 32. The modular exponentiation circuit 11B may discard the calculation result of the additionally inserted multiplication 43, or may propagate it to the calculation of the next bit. Examples of discarding the calculation result of multiplication 43 include Square and Multiply Always. Examples of propagating the calculation result of multiplication 43 to the calculation of the next bit include the Montgomery ladder method. Further, when the logic of the bit of the exponent k is “1”, the modular exponentiation circuit 11B performs squaring by the squaring circuit 31 and multiplication by the multiplication circuit 32.

[0115] Also, as shown in (D), when the logic of the bit of the inverse exponent k' in the second modification example is “0”, the modular exponentiation circuit 12B according to the second modification example performs squaring by the squaring circuit 31, and subsequent to the squaring, further performs multiplication 44 by the multiplication circuit 32. The modular exponentiation circuit 12B may discard the calculation result of the additionally inserted multiplication 44, or may propagate it to the calculation of the next bit. Also, when the logic of the bit of the inverse exponent k' is “1”, the modular exponentiation circuit 12B performs squaring by the squaring circuit 31 and multiplication by the multiplication circuit 32.

[0116] As shown in (E), the power consumption of the information processing apparatus 1B within the processing period of one bit becomes the total power consumption of two squarings and two multiplications (2S + 2M), which is common to all bits.

[0117] According to the second modification example, by inserting the multiplications 43 and 44, the waveform of the side channel information such as power consumption can be made into a fixed form regardless of the values of the secret information (the exponent k and the inverse exponent k'). As a result, not only resistance to FA and double FA but also resistance to SPA can be provided.

[0118] (Third Modification Example) FIG. 10 is a diagram showing the processing in the scalar multiplication circuits 11A and 12A according to the third modification example.

[0119] When the logic of the bits of the scalar value k in the scalar multiplication circuit 11A according to the first modification example is “0”, the point doubling circuit 21 performs point doubling, and following the point doubling, the point addition circuit 22 further performs point addition 41. As shown in (C), the scalar multiplication circuit 11A according to the third modification example performs a standby process 45 corresponding to the processing time of the point addition 41 instead of the point addition 41.

[0120] Also, when the logic of the bits of the inverse scalar value k' in the scalar multiplication circuit 12A according to the first modification example is “0”, the point doubling circuit 21 performs point doubling, and following the point doubling, the point addition circuit 22 further performs point addition 42. As shown in (D), the scalar multiplication circuit 12A according to the third modification example performs a standby process 46 corresponding to the processing time of the point addition 42 instead of the point addition 42.

[0121] As shown in (E), the power consumption of the information processing apparatus 1A within the processing period of one bit is the power consumption of the total of two point doublings and one point addition (2D + A), which is common to all bits.

[0122] According to the third modification example, while providing resistance to FA, double FA, and SPA, the power consumption of the information processing apparatus 1A can be reduced compared to the first modification example.

[0123] (Fourth Modification Example) FIG. 11 is a diagram showing the processing in the modular multiplication circuits 11B and 12B according to the fourth modification example.

[0124] The power residue operation circuit 11B according to the second modification example performs a squaring operation by the squaring circuit 31 when the logic of the bits of the power exponent k is "0", and following the squaring operation, further performs a multiplication 43 by the multiplication circuit 32. As shown in (C), the power residue operation circuit 11B according to the fourth modification example performs a standby process 47 corresponding to the processing time of the multiplication 43 instead of the multiplication 43.

[0125] Also, the power residue operation circuit 12B according to the second modification example performs a squaring operation by the squaring circuit 31 when the logic of the bits of the inverted power exponent k' is "0", and following the squaring operation, further performs a multiplication 44 by the multiplication circuit 32. As shown in (D), the power residue operation circuit 12B according to the fourth modification example performs a standby process 48 corresponding to the processing time of the multiplication 44 instead of the multiplication 44.

[0126] As shown in (E), the power consumption of the information processing device 1B within the processing period of one bit is the total power consumption of two squaring operations and one multiplication (2S + M), which is common to all bits.

[0127] According to the fourth modification example, while having resistance to FA, double FA, and SPA, the power consumption of the information processing device 1B can be reduced compared to the second modification example.

[0128] (Fifth Modification Example) Hereinafter, a fifth modification example will be described based on the first embodiment. By changing the rational point P to the base point G, the fifth modification example is also applicable to the third embodiment.

[0129] FIG. 12 is a diagram showing the processing in the scalar multiplication circuits 11A and 12A according to the fifth modification. In the fifth modification, the left-to-right binary method is implemented in the scalar multiplication circuits 11A and 12A. In the left-to-right binary method, the processing of each bit proceeds from the least significant bit to the most significant bit in the left direction. In the left-to-right binary method, different from the right-to-left binary method, point doubling and point addition can be performed in parallel (that is, simultaneously). In the example shown in FIG. 12, the scalar value k is...11010. Therefore, the inverted scalar value k' is...00101.

[0130] As shown in (A), in the scalar multiplication circuit 11A in which a simple left-to-right binary method is implemented, when the logic of the bit of the scalar value k is "0", point doubling by the point doubling circuit 21 is performed, and when the logic of the bit of the scalar value k is "1", point doubling by the point doubling circuit 21 and point addition by the point addition circuit 22 are performed.

[0131] As shown in (B), in the scalar multiplication circuit 12A in which a simple left-to-right binary method is implemented, when the logic of the bit of the inverted scalar value k' is "0", point doubling by the point doubling circuit 21 is performed, and when the logic of the bit of the inverted scalar value k' is "1", point doubling by the point doubling circuit 21 and point addition by the point addition circuit 22 are performed.

[0132] Since the power consumption of the information processing apparatus 1A differs between point doubling and point addition, the logic of the scalar value k or the inverted scalar value k' is discriminated by the SPA.

[0133] Therefore, as shown in (C), in the scalar multiplication circuit 11A according to the fifth modification, when the logic of the bit of the scalar value k is "0", point doubling by the point doubling circuit 21 is performed, and in parallel with the point doubling, point addition 49 by the point addition circuit 22 is further performed. The scalar multiplication circuit 11A may discard the calculation result of the additionally inserted point addition 49, or may propagate it to the calculation of the next bit. Also, in the scalar multiplication circuit 11A, when the logic of the bit of the scalar value k is "1", point doubling by the point doubling circuit 21 and point addition by the point addition circuit 22 are performed in parallel.

[0134] Also, as shown in (D), when the logic of the bits of the inverted scalar value k' is "0", the scalar multiplication circuit 12A according to the fifth modification example performs point doubling by the point doubling circuit 21, and in parallel with the point doubling, further performs point addition 50 by the point addition circuit 22. The scalar multiplication circuit 12A may discard the operation result of the additionally inserted point addition 50, or may propagate it to the operation of the next bit. Also, when the logic of the bits of the inverted scalar value k' is "1", the scalar multiplication circuit 12A performs point doubling by the point doubling circuit 21 and point addition by the point addition circuit 22 in parallel.

[0135] (E) As shown, the power consumption of the information processing apparatus 1A within one-bit processing period is the total power consumption of two point doublings and two point additions (2D + 2A), which is common to all bits.

[0136] According to the fifth modification example, by inserting the point additions 49 and 50, the waveform of the side-channel information such as power consumption can be made into a fixed form regardless of the values of the secret information (scalar value k and inverted scalar value k'). As a result, not only resistance to FA and double FA but also resistance to SPA can be provided.

[0137] Also, according to the fifth modification example, since the scalar multiplication circuits 11A and 12A perform point doubling and point addition in parallel, the processing time can be shortened compared to the first modification example.

[0138] (Sixth Modification Example) Hereinafter, based on the second embodiment, the sixth modification example will be described. By changing the base c to the primitive root g, the sixth modification example is also applicable to the fourth embodiment.

[0139] FIG. 13 is a diagram showing the processing in the power residue calculation circuits 11B and 12B according to the sixth modification example. In the sixth modification example, the left-to-right binary method is implemented in the power residue calculation circuits 11B and 12B. In the example shown in FIG. 13, the exponent k is ···11010. Therefore, the inverted exponent k' is ···00101.

[0140] As shown in (A), in the power residue operation circuit 11B implementing the simple leftward binary method, when the logic of the bit of the power exponent k is "0", a square operation is performed by the square operation circuit 31, and when the logic of the bit of the power exponent k is "1", a square operation by the square operation circuit 31 and a multiplication by the multiplication circuit 32 are performed.

[0141] As shown in (B), in the power residue operation circuit 12B implementing the simple leftward binary method, when the logic of the bit of the inverted power exponent k' is "0", a square operation is performed by the square operation circuit 31, and when the logic of the bit of the inverted power exponent k' is "1", a square operation by the square operation circuit 31 and a multiplication by the multiplication circuit 32 are performed.

[0142] Since the power consumption of the information processing apparatus 1B differs between the point doubling operation and the point addition operation, the logic of the power exponent k or the inverted power exponent k' is determined by SPA.

[0143] Therefore, as shown in (C), in the power residue operation circuit 11B according to the sixth modification example, when the logic of the bit of the power exponent k is "0", a square operation is performed by the square operation circuit 31, and in parallel with the square operation, a multiplication 51 by the multiplication circuit 32 is further performed. The power residue operation circuit 11B may discard the operation result of the additionally inserted multiplication 51 or propagate it to the operation of the next bit. Also, when the logic of the bit of the power exponent k is "1", the power residue operation circuit 11B performs the square operation by the square operation circuit 31 and the multiplication by the multiplication circuit 32 in parallel.

[0144] Also, as shown in (D), in the power residue operation circuit 12B according to the sixth modification example, when the logic of the bit of the inverted power exponent k' is "0", a square operation is performed by the square operation circuit 31, and in parallel with the square operation, a multiplication 52 by the multiplication circuit 32 is further performed. The power residue operation circuit 12B may discard the operation result of the additionally inserted multiplication 52 or propagate it to the operation of the next bit. Also, when the logic of the bit of the inverted power exponent k' is "1", the power residue operation circuit 12B performs the square operation by the square operation circuit 31 and the multiplication by the multiplication circuit 32 in parallel.

[0145] As shown in (E), the power consumption of the information processing apparatus 1B within one-bit processing period is the total power consumption of two squarings and two multiplications (2S + 2M), which is common to all bits.

[0146] According to the sixth modification example, by inserting the multiplications 51 and 52, the waveform of the side-channel information such as the power consumption can be made into a fixed form regardless of the values of the secret information (the base exponent k and the inverse base exponent k'). As a result, not only the resistance to FA and double FA but also the resistance to SPA can be provided.

[0147] Also, according to the sixth modification example, since the square multiplier circuits 11B and 12B perform squaring and multiplication in parallel, the processing time can be shortened compared to the second modification example.

[0148] (Seventh Modification Example) FIG. 14 is a diagram showing the processing in the scalar multiplication circuits 11A and 12A according to the seventh modification example.

[0149] When the logic of the bit of the scalar value k in the scalar multiplication circuit 11A according to the fifth modification example is “0”, the scalar multiplication circuit 11A performs the scalar multiplication by the scalar multiplication circuit 21, and in parallel with the scalar multiplication, further performs the point addition 49 by the point addition circuit 22. The scalar multiplication circuit 11A according to the seventh modification example, as shown in (C), instead of adding the point addition 49, performs a standby process 53 corresponding to the processing time difference between the point addition and the scalar multiplication after the scalar multiplication is completed.

[0150] Also, when the logic of the bit of the inverted scalar value k' in the scalar multiplication circuit 12A according to the fifth modification example is “0”, the scalar multiplication circuit 12A performs the scalar multiplication by the scalar multiplication circuit 21, and in parallel with the scalar multiplication, further performs the point addition 50 by the point addition circuit 22. The scalar multiplication circuit 12A according to the seventh modification example, as shown in (D), instead of adding the point addition 50, performs a standby process 54 corresponding to the processing time difference between the point addition and the scalar multiplication after the scalar multiplication is completed.

[0151] As shown in (E), the power consumption of the information processing apparatus 1A within the processing period of 1 bit is the total power consumption of two point doublings and one point addition (2D + A), which is common to all bits.

[0152] According to the seventh modification example, while having resistance to FA, double FA, and SPA, the power consumption of the information processing apparatus 1A can be reduced as compared with the fifth modification example.

[0153] (Eighth Modification Example) FIG. 15 is a diagram showing the processing in the power residue operation circuits 11B and 12B according to the eighth modification example.

[0154] In the power residue operation circuit 11B according to the sixth modification example, when the logic of the bit of the power exponent k is “0”, a squaring operation is performed by the squaring circuit 31, and in parallel with the squaring operation, a multiplication 51 is further performed by the multiplication circuit 32. In the power residue operation circuit 11B according to the eighth modification example, as shown in (C), instead of adding the multiplication 51, a standby process 55 corresponding to the processing time difference between the multiplication and the squaring is performed after the completion of the squaring operation.

[0155] Also, in the power residue operation circuit 12B according to the sixth modification example, when the logic of the bit of the inverted power exponent k' is “0”, a squaring operation is performed by the squaring circuit 31, and in parallel with the squaring operation, a multiplication 52 is further performed by the multiplication circuit 32. In the power residue operation circuit 12B according to the eighth modification example, as shown in (D), instead of adding the multiplication 52, a standby process 56 corresponding to the processing time difference between the multiplication and the squaring is performed after the completion of the squaring operation.

[0156] As shown in (E), the power consumption of the information processing apparatus 1B within the processing period of 1 bit is the total power consumption of two squaring operations and one multiplication (2S + M), which is common to all bits.

[0157] According to the eighth modification example, while having resistance to FA, double FA, and SPA, the power consumption of the information processing apparatus 1B can be reduced as compared with the sixth modification example.

[0158] The functions of the elements disclosed herein may be implemented using a general-purpose processor, a dedicated processor, an integrated circuit, an ASIC ("application-specific integrated circuit"), a conventional circuit configuration, and / or a combination thereof configured to execute the disclosed elements or programmed to execute the disclosed functions. A processor is considered a processing circuit configuration or a circuit configuration when it includes transistors and other circuit configurations therein. In the present disclosure, a circuit configuration, unit, or means is hardware that executes the recited functions or hardware programmed to execute the functions. The hardware may be any hardware disclosed herein or other known hardware programmed or configured to execute the recited functions. When the hardware is a processor that may be considered a type of circuit configuration, the circuit configuration, means, or unit is a combination of hardware and software, software used to configure the hardware, and / or a processor.

Explanation of Signs

[0159] 1 Information processing apparatus 11 First arithmetic circuit 12 Second arithmetic circuit 13 Third arithmetic circuit 14 Fourth arithmetic circuit 15 Inversion circuit 16 Memory circuit 17 Comparison circuit

Claims

1. A first arithmetic circuit that performs a first operation based on a plurality of bits of first data that is secret information and outputs second data; An inversion circuit that inverts the logic of each bit of the first data and outputs third data; A second arithmetic circuit having the same circuit configuration as the first arithmetic circuit, performing a second operation identical to the first operation based on the third data, and outputting fourth data; A third arithmetic circuit that performs a third operation based on the second data and the fourth data and outputs fifth data; A comparison circuit that compares the fifth data with an expected value based on a value corresponding to the number of bits of the first data; An information processing apparatus comprising the same.

2. The first arithmetic circuit performs, as the first operation, scalar multiplication defined on an elliptic curve based on the first data and coordinate data indicating an arbitrary rational point; The second arithmetic circuit performs, as the second operation, scalar multiplication defined on an elliptic curve based on the third data and the coordinate data; The third arithmetic circuit performs, as the third operation, point addition defined on an elliptic curve based on the second data and the fourth data. The information processing apparatus according to claim 1.

3. The first arithmetic circuit performs, as the first operation, a modular exponentiation operation based on the first data and value data indicating an arbitrary value; The second arithmetic circuit performs, as the second operation, a modular exponentiation operation based on the third data and the value data; The third arithmetic circuit performs multiplication as the third operation based on the second data and the fourth data. The information processing apparatus according to claim 1.

4. The first arithmetic circuit performs, as the first operation, scalar multiplication defined on an elliptic curve based on the first data and coordinate data indicating a predetermined base point; The second arithmetic circuit performs, as the second operation, scalar multiplication defined on an elliptic curve based on the third data and the coordinate data; The third arithmetic circuit performs, as the third operation, point addition defined on an elliptic curve based on the second data and the fourth data. The information processing apparatus according to claim 1.

5. The first arithmetic circuit performs, as the first operation, a modular exponentiation operation based on the first data and value data indicating a predetermined primitive root; The second arithmetic circuit performs, as the second operation, a modular exponentiation operation based on the third data and the value data; ​ ​ ​ As the third operation, the third arithmetic circuit performs multiplication based on the second data and the fourth data. The information processing apparatus according to claim 1.

6. The information processing apparatus further includes a fourth arithmetic circuit that performs a fourth operation based on a value corresponding to the number of bits of the first data and outputs the expected value. The information processing apparatus according to any one of claims 2 to 5.

7. The information processing apparatus further includes a storage circuit that stores the expected value calculated by pre-calculation based on a value corresponding to the number of bits of the first data. The information processing apparatus according to claim 4 or 5.

8. The value corresponding to the number of bits of the first data is expressed as 2 ｎ −1, where n is the number of bits The information processing apparatus according to claim 1.

9. The third arithmetic circuit is shared with the first arithmetic circuit or the second arithmetic circuit, and the third operation is performed by the first arithmetic circuit or the second arithmetic circuit. The information processing apparatus according to claim 1.

10. In the scalar multiplication, when the logic of the bit of the first data is "0", the first arithmetic circuit performs a point doubling operation. When the logic of the bit of the first data is "1", the first arithmetic circuit performs a point doubling operation and a point addition operation. When the logic of the bit of the first data is "0", the first arithmetic circuit further performs a point addition operation. In the scalar multiplication, when the logic of the bit of the third data is "0", the second arithmetic circuit performs a point doubling operation. When the logic of the bit of the third data is "1", the second arithmetic circuit performs a point doubling operation and a point addition operation. When the logic of the bit of the third data is "0", the second arithmetic circuit further performs a point addition operation. The information processing apparatus according to claim 2 or 4.

11. In the power residue operation, when the logic of the bit of the first data is "0", the first arithmetic circuit performs a squaring operation. When the logic of the bit of the first data is "1", the first arithmetic circuit performs a squaring operation and a multiplication operation. When the logic of the bit of the first data is "0", the first arithmetic circuit further performs a multiplication operation. In the power residue operation, when the logic of the bit of the third data is "0", the second arithmetic circuit performs a squaring operation. When the logic of the bit of the third data is "1", the second arithmetic circuit performs a squaring operation and a multiplication operation. When the logic of the bit of the third data is "0", the second arithmetic circuit further performs a multiplication operation. The information processing apparatus according to claim 3 or 5.

12. In the scalar multiplication, when the logic of the bit of the first data is "0", the first arithmetic circuit performs a point doubling operation; when the logic of the bit of the first data is "1", the first arithmetic circuit performs a point doubling operation and a point addition operation. When the logic of the bit of the first data is "0", the first arithmetic circuit further performs a standby process corresponding to the processing time of the point addition operation. In the scalar multiplication, when the logic of the bit of the third data is "0", the second arithmetic circuit performs a point doubling operation; when the logic of the bit of the third data is "1", the second arithmetic circuit performs a point doubling operation and a point addition operation. When the logic of the bit of the third data is "0", the second arithmetic circuit further performs a standby process corresponding to the processing time of the point addition operation. The information processing apparatus according to claim 2 or 4.

13. In the power residue operation, when the logic of the bit of the first data is "0", the first arithmetic circuit performs a squaring operation; when the logic of the bit of the first data is "1", the first arithmetic circuit performs a squaring operation and a multiplication operation. When the logic of the bit of the first data is "0", the first arithmetic circuit further performs a standby process corresponding to the processing time of the multiplication operation. In the power residue operation, when the logic of the bit of the third data is "0", the second arithmetic circuit performs a squaring operation; when the logic of the bit of the third data is "1", the second arithmetic circuit performs a squaring operation and a multiplication operation. When the logic of the bit of the third data is "0", the second arithmetic circuit further performs a standby process corresponding to the processing time of the multiplication operation. The information processing apparatus according to claim 3 or 5.

14. In the scalar multiplication, when the logic of the bit of the first data is "0", the first arithmetic circuit performs a point doubling operation; when the logic of the bit of the first data is "1", the first arithmetic circuit performs a point doubling operation and a point addition operation in parallel. When the logic of the bit of the first data is "0", the first arithmetic circuit further performs a standby process corresponding to the processing time difference between the point addition operation and the point doubling operation. In the scalar multiplication, when the logic of the bit of the third data is "0", the second arithmetic circuit performs a point doubling operation; when the logic of the bit of the third data is "1", the second arithmetic circuit performs a point doubling operation and a point addition operation in parallel. When the logic of the bit of the third data is "0", the second arithmetic circuit further performs a standby process corresponding to the processing time difference between the point addition operation and the point doubling operation. The information processing apparatus according to claim 2 or 4. [[ID=!]]

15. In the power residue operation, when the logic of the bit of the first data is "0", the first arithmetic circuit performs a square operation. When the logic of the bit of the first data is "1", the first arithmetic circuit performs a square operation and a multiplication operation in parallel. When the logic of the bit of the first data is "0", the first arithmetic circuit further performs a standby process corresponding to the processing time difference between the multiplication operation and the square operation. In the power residue operation, when the logic of the bit of the third data is "0", the second arithmetic circuit performs a square operation. When the logic of the bit of the third data is "1", the second arithmetic circuit performs a square operation and a multiplication operation in parallel. When the logic of the bit of the first data is "0", the second arithmetic circuit further performs a standby process corresponding to the processing time difference between the multiplication operation and the square operation. The information processing apparatus according to claim 3 or 5.

16. An information processing apparatus performs a first operation based on a plurality of bits of first data that is secret information and outputs second data. inverts the logic of each bit of the first data and outputs third data. performs a second operation identical to the first operation based on the third data and outputs fourth data. performs a third operation based on the second data and the fourth data and outputs fifth data. compares the fifth data with an expected value based on a value corresponding to the number of bits of the first data. An information processing method.

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