Relaxation oscillator

Abstract

To stably output a signal of a predetermined frequency.SOLUTION: A relaxation oscillator includes: a first transistor M1 that flows a constant current; a first capacitor C1 that is charged by a current from the first transistor M1; a second transistor M2 that pulls out the charge of the first capacitor C1; a third transistor M3 that flows a constant current; a second capacitor C2 that is charged by the current from the third transistor M3; a fourth transistor M4 that pulls out the charge accumulated in the second capacitor C2; and a flip-flop FF that changes from a first state to a second state when a charging voltage of the first capacitor C1 reaches a predetermined value, changes from the second state to the first state when the charging voltage of the second capacitor C2 reaches the predetermined value, turns off the second transistor M2 and turns on the fourth transistor M4 in the first state, and turns on the second transistor M2 and turns off the fourth transistor M4 in the second state. A signal of a predetermined frequency is output from the flip-flop FF.SELECTED DRAWING: Figure 1

Description

Technical Field

[0001] The present disclosure relates to a relaxation oscillator that oscillates by using the on / off of a switch.

Background Art

[0002] Conventionally, as one of the oscillation circuits, a relaxation oscillator that generates an intermittent electrical signal by controlling the on / off timing of a switch is known. For example, a capacitor is charged, a comparator detects that the charging voltage has reached a predetermined value, and the on / off timing of the switch is determined.

Prior Art Documents

Non-Patent Documents

[0003]

Non-Patent Document 1

Summary of the Invention

Problems to be Solved by the Invention

[0004] Here, for accurate and stable oscillation, it is required that the comparator be fast and highly accurate, consume a large current, and require a large-scale circuit.

[0005] In addition, when a comparator detects that the charging voltage of the capacitor has reached a predetermined value, there is a problem that the charging current becomes small near the trigger point, so the operation at the trigger point tends to be unstable.

Means for Solving the Problems

[0006] The relaxation oscillator according to the present disclosure includes a first transistor that conducts a constant current, a first capacitor that is charged by the current from the first transistor, a second transistor that extracts the charge of the first capacitor, a third transistor that conducts a constant current, a second capacitor that is charged by the current from the third transistor, a fourth transistor that extracts the stored charge of the second capacitor, and a flip-flop that changes its state from a first state to a second state when the charging voltage of the first capacitor reaches a predetermined value, changes from the second state to the first state when the charging voltage of the second capacitor reaches a predetermined value, turns off the second transistor and turns on the fourth transistor in the first state, and turns on the second transistor and turns off the fourth transistor in the second state, and outputs a signal having a predetermined frequency from the flip-flop.

Advantages of the Invention

[0007] In the relaxation oscillator according to the present disclosure, a constant current is used for charging, and the voltage slope is constant even near the trigger point, so that stable operation can be obtained.

Brief Description of the Drawings

[0008]

Figure 1

Figure 2

Figure 3

Figure 4

Modes for Carrying Out the Invention

[0009] Hereinafter, embodiments of the present disclosure will be described below with reference to the drawings. Note that the following embodiments do not limit the present disclosure, and configurations formed by selectively combining a plurality of examples are also included in the present disclosure.

[0010] "Circuit Configuration" Figure 1 is a circuit diagram showing the configuration of a relaxation oscillator according to an embodiment. In this circuit, as the transistor, a MOSFET (Metal Oxide Semiconductor Field Effect Transistor) whose control terminal is the gate is used.

[0011] The source of the p-channel transistor M0 is connected to the power supply Vdd, and the drain is connected to the ground GND via the resistor R0. The gate-drain terminals of the transistor M0 are short-circuited, that is, diode-connected. Therefore, a constant current Iref determined by the voltage of the power supply Vdd (Vdd) and the resistance value of the resistor R0 flows through the transistor M0 and the resistor R0.

[0012] The gate of the transistor M0 is connected to the gate of the p-channel transistor M1. The source of the transistor M1 is connected to the power supply Vdd, and the drain is connected to the ground GND via the capacitor C1. Since the transistors M0 and M1 form a current mirror, by making both transistors equivalent, the same current Iref as that of the transistor M0 flows through the transistor M1, and the capacitor C1 is charged with this current Iref. Note that the ratio of the currents flowing through the two transistors can be changed by changing the ratio of the sizes of the input-side transistor and the output-side transistor of the current mirror.

[0013] Also, the drain of the n-channel transistor M2 is connected to the connection point between the drain of the transistor M1 and the capacitor C1, and the source of the transistor M2 is connected to the ground. Therefore, when the transistor M2 is turned on, the capacitor C1 is discharged.

[0014] The gate of transistor M0 is also connected to the gate of p-channel transistor M3. The source of transistor M3 is connected to power supply Vdd, and the drain is connected to ground GND via capacitor C2. Since transistors M0 and M3 form a current mirror, the same current Iref as that in transistor M1 also flows through transistor M3, and capacitor C2 is charged with this current Iref.

[0015] Also, the drain of n-channel transistor M4 is connected to the connection point between the drain of transistor M3 and capacitor C2, and the source of transistor M4 is connected to ground. Therefore, when transistor M4 is turned on, capacitor C2 is discharged.

[0016] The gate of transistor M5 is connected to the drain of transistor M1. Transistor M5 is a p-channel transistor, with its source connected to power supply Vdd and its drain connected to ground GND via resistor R1. Transistor M5 turns on when the difference between its gate voltage (= the charging voltage Vc1 of capacitor C1) and the power supply voltage Vdd is a predetermined value, i.e., the threshold voltage Vgson or more, and turns off when it is less. In other words, transistor M5 turns off when its gate voltage Vc1 becomes Vdd - Vgson or more.

[0017] The gate of transistor M6 is connected to the drain of transistor M3. Transistor M6 is a p-channel transistor, with its source connected to power supply Vdd and its drain connected to ground GND via resistor R2. Transistor M6 turns off when the difference between its gate voltage (= the charging voltage Vc2 of capacitor C2) and the power supply voltage Vdd is less than or equal to the threshold voltage Vgson. That is, transistor M6 turns off when its gate voltage Vc2 becomes Vdd - Vgson or more.

[0018] The drain of transistor M5 is connected to the inverted set terminal Sb of the RS-type flip-flop FF. Also, the drain of transistor M6 is connected to the inverted reset terminal Rb of the flip-flop FF. The output terminal Q of the flip-flop FF is connected to the gate of transistor M2, and the inverted output terminal Qb is connected to the gate of transistor M4.

[0019] <Description of the operation> Figure 2 is a timing chart for explaining the operation of the circuit in Figure 1.

[0020] First, assume that the state of the flip-flop FF is "0". In this case, the output terminal Q is at the L level, transistor M2 is off, the inverted output terminal Qb is at the H level, and transistor M4 is on. Therefore, the capacitor C1 is charged with a constant current, and the voltage Vc1 gradually increases. On the other hand, since transistor M4 is on, the voltage Vc2 remains at 0V.

[0021] When the voltage Vc1 of the capacitor C1 rises and the gate voltage of transistor M5 becomes equal to or higher than Vdd - Vgson, transistor M5 turns off. As a result, the current flowing through the resistor R1 disappears, and the voltage at the connection between the resistor R1 and transistor M5 becomes 0V. For this reason, the inverted set terminal Sb of the flip-flop FF changes from the H level to the L level. Thereby, the state of the flip-flop FF becomes "1", the output terminal Q becomes the H level, and the inverted output terminal Qb becomes the L level.

[0022] As a result, transistor M2 turns on and transistor M4 turns off. Therefore, the capacitor C1 is discharged and the voltage Vc1 becomes 0V. On the other hand, when transistor M4 turns off, the capacitor C2 is charged and the voltage Vc2 gradually increases. Also, since transistor M2 is on, the voltage Vc1 remains at 0V.

[0023] When the voltage Vc2 of the capacitor C2 rises and the gate voltage of the transistor M6 becomes equal to or higher than the threshold voltage, the transistor M6 turns off. As a result, the inverted reset terminal Rb of the flip-flop FF changes from the H level to the L level, the state of the flip-flop FF becomes "0", the output terminal Q becomes the L level, and the inverted output terminal Qb becomes the H level.

[0024] As a result, the transistor M2 turns off and the transistor M4 turns on. Therefore, the capacitor C2 is discharged and the voltage Vc2 becomes 0V. On the other hand, the capacitor C1 starts to be charged and the voltage Vc1 gradually rises. Since the transistor M4 is on, the voltage Vc2 remains at 0V.

[0025] In this way, by charging the capacitors C1 and C2 with the constant current flowing through the transistors M1 and M3, the state of the flip-flop FF changes between "0" and "1" every predetermined period. Therefore, a signal with a predetermined frequency can be obtained at the output of the flip-flop FF.

[0026] If the transistors M1 and M3 have the same configuration and the capacitances of the capacitors C1 and C2 are the same, the charging of the capacitors C1 and C2 becomes equivalent, and the time t1 in the "0" state and the time t2 in the "1" state of the flip-flop FF can be made the same.

[0027] Note that the two states of the flip-flop FF are referred to as the first state and the second state, respectively. The first state and the second state may be either "0" or "1", as long as they are different states.

[0028] Next, the above operation will be described using equations. Here, assume that M0:M1:M3 = 1:1:1, C1 = C2 = C, and td (operation delay time) << t1 (half of the output period). Also, assume that the charging current is Iref and the threshold voltage of the transistor is Vgson.

[0029] First, the charging charge q of the capacitor is the value obtained by multiplying the capacitance C of the capacitor by its voltage V. q = C * V

[0030] The charging charge q of the capacitor is the value obtained by multiplying the current I by the charging time t. I * t = q = C * V

[0031] The transistors M5 and M6 are when the voltages of the capacitors C1 and C2 become (Vdd - Vgson) or more.

[0032] Therefore, Iref * t1 = C1 * (Vdd - Vgson) is.

[0033] For this reason, t1 = C1 * (vdd - vgson) / Iref is.

[0034] Also, the charging current Iref is the current flowing through the resistor R0 on the downstream side of the transistor M0. Since the voltage drop in the diode-connected transistor M0 is Vgson, Iref = (Vdd - Vgson) / R0 is.

[0035] Therefore, t1 = C1 * R0 = C * R0 results in.

[0036] t2 is the same, t2 = C2 * R0 = C * R0 = t1 is.

[0037] According to this, the clock timing does not depend on the power supply, and the duty ratio is 50%.

[0038] In the relaxation oscillator according to this embodiment, since a constant current is used for charging, the voltage slope is constant at the trigger point for turning off transistors M5 and M6, and stable operation can be obtained. For example, in a CR type relaxation oscillator, since the charging current becomes small near the trigger point, there is a problem in the operation at the trigger point, but such a problem does not exist in the relaxation oscillator according to the present disclosure.

[0039] Further, in this embodiment, the on / off of transistors M5 and M6 may be controlled by the charging voltage of the capacitor, the consumption current may be relatively small, and high-speed operation is possible with a simple configuration.

[0040] Also, since switching can be performed using the charging voltage of the capacitor close to the power supply voltage, it is resistant to noise and suitable for miniaturization of the capacitor.

[0041] The charging current of the capacitor is the current flowing through transistors M1 and M3, is proportional to the comparison voltage (Vdd - Vgson), and the voltage for stopping charging is also (Vdd - Vgson), so the time constant of the circuit operation does not depend on the power supply voltage.

[0042] "Modification 1" FIG. 3 is a circuit diagram showing the configuration of Modification 1. Compared with the configuration of FIG. 1, the resistors R1 and R2 that are the loads of transistors M5 and M6 are replaced with constant current sources.

[0043] That is, a p-channel transistor M8 having a gate connected to transistor M0 and a source connected to power supply Vdd is provided, and a current corresponding to the current Iref flowing through transistor M0 is made to flow here. The drain of transistor M8 is connected to the drain of n-channel transistor M9. Transistor M9 has a short circuit between the gate and the drain, that is, is diode-connected, and the source is connected to the ground.

[0044] The gate of transistor M9 is connected to the gate of n-channel transistor M10, and the drain of this transistor M10 is connected to the source of transistor M5. Transistors M9 and M10 form a current mirror. Transistor M5 allows sufficient current to flow when it is on. When transistor M5 is on, the current flowing through transistor M5 is the same as the current through transistor M10, and the drain of transistor M5, that is, the inverted set terminal Sb of flip-flop FF, becomes the H level. On the other hand, when transistor M5 is off, since transistor M10 tries to conduct current, the drain of transistor M5, that is, the inverted set terminal Sb of flip-flop FF, becomes the L level.

[0045] Also, transistor M11 operates in the same manner as transistor M10, although with opposite timing. The inverted reset terminal of flip-flop FF becomes the H level when transistor M6 is on and the L level when it is off. Note that FIG. 3 shows the signal levels in the state where flip-flop FF is "0".

[0046] Thus, in this Modification 1 as well, the same operation as in the embodiment of FIG. 1 is possible. Also, since transistors are used instead of resistors R1 and R2, a more accurate oscillator can be obtained.

[0047] "Modification 2" FIG. 4 is a circuit diagram showing the configuration of Modification 2. In Modification 2, compared with the configuration of FIG. 1, by adding a selector composed of transistors M12 and M13, the charging current to capacitors C1 and C2 can charge capacitors C1 and C2 alternately with the current from transistor M1, which is a single current source, by omitting transistor M3. Thereby, the power consumption can be reduced.

[0048] That is, the sources of p-channel transistors M12 and M13 are connected to the drain of transistor M1. The drain of transistor M12 is connected to capacitor C1, and the drain of transistor M13 is connected to capacitor C2. Then, the gate of transistor M12 is connected to the output terminal Q of flip-flop FF, and the gate of transistor M13 is connected to the inverted output terminal Qb of flip-flop FF.

[0049] Therefore, when transistor M2 is off, transistor M12 turns on and capacitor C1 is charged. When transistor M4 is off, transistor M13 turns on and capacitor C2 is charged.

[0050] "Effects of the Embodiment" According to this embodiment, an oscillator that is a relatively simple circuit, easy to implement, and has a small number of components can be realized. As the charging voltages of capacitors C1 and C2 approach the voltage of power supply Vdd, transistors M5 and M6 are turned off, so that oscillation can be performed using the full power supply voltage, and phase noise can be reduced.

[0051] The gates and sources of transistors M5 and M6 operate as the negative input and positive input of a comparator having a predetermined offset voltage. Therefore, transistors M5 and M6 operate as a comparator instead of using a conventional two-input comparator having a voltage reference.

[0052] Also, the above offset is the same as Vgs of transistor M0, and they cancel each other out. Therefore, high-precision oscillation is possible.

[0053] Such a simple and sufficiently accurate high-speed comparator is suitable for high-frequency oscillation.

[0054] Also, by tuning resistor R0, the oscillation frequency can be easily adjusted.

[0055] "Others" The capacitor C1 is referred to as the first capacitor, the capacitor C2 as the second capacitor, and the transistors M1 to M11 as the first to eleventh transistors, respectively.

Explanation of Signs

[0056] M0 - M11 transistors, C1 - C2 capacitors, FF flip - flop.

Claims

1. A first transistor that conducts a constant current, A first capacitor charged by the current from the first transistor, A second transistor that extracts the charging charge of the first capacitor, A third transistor that conducts a constant current, A second capacitor charged by the current from the third transistor, A fourth transistor that extracts the stored charge of the second capacitor, A flip-flop that changes its state from a first state to a second state when the charging voltage of the first capacitor reaches a predetermined value, and changes from the second state to the first state when the charging voltage of the second capacitor reaches a predetermined value. In the first state, the second transistor is turned off and the fourth transistor is turned on. In the second state, the second transistor is turned on and the fourth transistor is turned off., Including, A relaxation oscillator that outputs a signal of a predetermined frequency from the flip-flop.

2. The relaxation oscillator according to claim 1, A fifth transistor that receives the charging voltage of the first capacitor at its control terminal and turns on and off, A sixth transistor that receives the charging voltage of the second capacitor at its control terminal and turns on and off, Further including, The state of the flip-flop changes depending on the on / off states of the fifth transistor and the sixth transistor., Relaxation oscillator.

3. The relaxation oscillator according to claim 2, Including a first resistor connected in series with the fifth transistor, and the voltage at the connection point with the fifth transistor changes depending on the on / off state of the fifth transistor, The state of the flip-flop changes due to the voltage change at the connection point between the first resistor and the fifth transistor, Including a second resistor connected in series with the sixth transistor, and the voltage at the connection point with the sixth transistor changes depending on the on / off state of the sixth transistor, The state of the flip-flop changes due to the voltage change at the connection point between the second resistor and the sixth transistor., Relaxation oscillator.

4. The relaxation oscillator according to claim 2, A tenth transistor that conducts a constant current, which is connected in series with the fifth transistor, and the voltage at the connection point with the fifth transistor changes depending on the on / off state of the fifth transistor., The state of the flip-flop changes due to the voltage change at the connection point between the tenth transistor and the fifth transistor. An eleventh transistor that conducts a constant current, which is connected in series with the sixth transistor, and the voltage at the connection point with the sixth transistor changes depending on the on / off state of the sixth transistor. The state of the flip-flop changes due to the voltage change at the connection point between the eleventh transistor and the sixth transistor. A relaxation oscillator. **Claim 5** The relaxation oscillator according to claim 2, wherein the first transistor and the second transistor switch and alternately conduct the constant current from one constant current source. A relaxation oscillator. **Claim 6** The relaxation oscillator according to claim 1, a zeroeth transistor having a diode-connected control terminal connected to the control terminals of the first transistor and the third transistor, a zeroeth resistor connected in series with the zeroeth transistor, wherein the resistance value of the zeroeth resistor adjusts the magnitudes of the constant current flowing through the first transistor and the constant current flowing through the second transistor. A relaxation oscillator.

Images