Semiconductor device

Abstract

To provide a programmable logic device capable of achieving reduction in power consumption while suppressing reduction in working speed.SOLUTION: A programmable logic device comprises: a first circuit; a second circuit; a first transistor that controls electrical connection between the first circuit and the second circuit according to a potential at its gate; a first switch that controls supply of a signal to a first node; a second switch that controls supply of the signal to a second node; a second transistor in which one of a source and a drain, and a gate are electrically connected with the first node, and the other of the source and the drain is electrically connected with the second node; and a capacitive element that holds a potential of the signal supplied to the first node.SELECTED DRAWING: Figure 1

Description

Technical Field

[0001] One aspect of the present invention relates to a semiconductor device. For example, the present invention relates to a programmable logic device whose hardware configuration can be changed and a semiconductor device using the programmable logic device. and a semiconductor device using the programmable logic device.

Background Art

[0002] A programmable logic device (PLD) has a configuration in which logic circuits (logic blocks, programmable logic elements) of an appropriate scale are electrically connected by wiring resources, and the functions of each logic block and the connection structure between the logic blocks can be changed after manufacturing. The functions of each logic block and the connection structure between the logic blocks constituted by the wiring resources are defined by configuration data, and the configuration data is stored in a register included in each logic block or a register included in the wiring resources. Hereinafter, a register for storing configuration data is referred to as a configuration memory. and the connection structure between the logic blocks constituted by the wiring resources are defined by configuration data, and the configuration data is stored in a register included in each logic block or a register included in the wiring resources. and the connection structure between the logic blocks can be changed after manufacturing. The functions of each logic block and the connection structure between the logic blocks constituted by the wiring resources are defined by configuration data, and the configuration data is stored in a register included in each logic block or a register included in the wiring resources. characterized in that The functions of each logic block and the connection structure between the logic blocks constituted by the wiring resources are defined by configuration data, and the configuration data is stored in a register included in each logic block or a register included in the wiring resources. is defined by configuration data, and the configuration data is stored in a register included in each logic block or a register included in the wiring resources. is stored in a register included in each logic block or a register included in the wiring resources. Hereinafter, a register for storing configuration data is referred to as a configuration memory.

[0003] Non-Patent Document 1 below describes an FPGA (Field Programmable Gate Array) in which wiring resources are configured by a circuit in which an SRAM cell is connected to the gate of a pass transistor via an isolator transistor. is connected to the gate of a pass transistor via an isolator transistor.

Prior Art Documents

Non-Patent Documents

[0004]

Non-Patent Document 1

[0005] By the way, low power consumption and high - speed operation are both important points in evaluating the performance of semiconductor devices such as programmable logic devices. However, when the power supply voltage is reduced to reduce the power consumption of the semiconductor device, the on - current of the transistor becomes small, so the operating speed of the semiconductor device also decreases. That is, there is a trade - off relationship between power consumption reduction and operating speed improvement. Considering the operating speed, simply reducing the power supply voltage cannot be done only for the purpose of reducing power consumption. Moreover, the high - level potential applied to a node in a semiconductor device through an n - channel type transistor drops by the threshold voltage of the transistor. Therefore, when the power supply voltage of the semiconductor device is reduced to reduce power consumption, the potential at the node inside the semiconductor device becomes too low, and the logic level of the signal output from the semiconductor device changes, so the reliability of the data tends to decrease. Under the technical background as described above, one aspect of the present invention is a programmable logic device, a programmable switch that can achieve low power consumption while suppressing a reduction in operating speed,

[0006] Also, the high - level potential applied to a node in a semiconductor device through an n - channel type transistor drops by the threshold voltage of the transistor. Therefore, when the power supply voltage of the semiconductor device is reduced to reduce power consumption, the potential at the node inside the semiconductor device becomes too low, and the logic level of the signal output from the semiconductor device changes, so the reliability of the data tends to decrease. Moreover, the high - level potential applied to a node in a semiconductor device through an n - channel type transistor drops by the threshold voltage of the transistor. Therefore, when the power supply voltage of the semiconductor device is reduced to reduce power consumption, the potential at the node inside the semiconductor device becomes too low, and the logic level of the signal output from the semiconductor device changes, so the reliability of the data tends to decrease. Moreover, the high - level potential applied to a node in a semiconductor device through an n - channel type transistor drops by the threshold voltage of the transistor. Therefore, when the power supply voltage of the semiconductor device is reduced to reduce power consumption, the potential at the node inside the semiconductor device becomes too low, and the logic level of the signal output from the semiconductor device changes, so the reliability of the data

[0007] Under the technical background as described above, one aspect of the present invention is a programmable logic device, a programmable switch that can achieve low power consumption while suppressing a reduction in operating speed, a programmable logic device, a programmable switch, Another object of the present invention is to provide a semiconductor device. Alternatively, one aspect of the present invention is to provide a programmable logic device, a programmable switch, or a semiconductor device that can achieve low power consumption while ensuring normal operation. Another object of the present invention is to provide a programmable logic device, a programmable switch, or a semiconductor device that can achieve low power consumption while ensuring normal operation.

Means for Solving the Problem

[0008] In one aspect of the present invention, data is written to a semiconductor device by accumulating charge on a first node via a first switch. Also, the above data is written to the semiconductor device by accumulating charge on a second node via a second switch. The gate of a first transistor is connected to the second node. And the electrical connection between the first node and the second node is controlled by a second transistor whose gate is electrically connected to the first node. Also, a capacitive element is electrically connected to the first node.

[0009]

[0010] ​​​​​​​​​​​​​​When the potential of the above signal is at a high level, when the first switch and the second switch and the second transistor are in a non-conducting state, as time passes, when the potential of the second node drops, the charge stored in the holding capacitor is supplied to the second node through the second transistor, so that the potential drop of the second node can be prevented.

[0011] Furthermore, in the semiconductor device according to one aspect of the present invention, the second node has a first transistor whose gate is electrically connected. When the potential of one of the source and drain of the first transistor rises from a low level to a high level, when the second node is in a floating state, due to the capacitive coupling of the capacitance C formed between the source and gate of the first transistor, the potential of the gate of the first transistor, that is, the potential of the second node also rises. Therefore, when the potential of the above signal is at a high level, even if the potential of the second node has dropped by the threshold voltage of the transistor included in the second switch with respect to the potential,

[0012] the potential of the second node can be raised by the above operation. Therefore, the gate voltage of the first transistor whose gate is electrically connected to the second node can be made sufficiently larger than the threshold voltage, and the conducting state of the first transistor can be ensured. Therefore, in the semiconductor device according to one aspect of the present invention, even if the power supply voltage supplied to the semiconductor device becomes small, the operation speed of the semiconductor device can be prevented from decreasing. Specifically, the semiconductor device according to one aspect of the present invention includes a first transistor whose conduction or non-conduction is controlled according to the potential of the gate, and a first that controls the supply of a signal to the first node.

[0013] switch that controls the supply of a signal to the first node. A switch, a second switch for controlling the supply of the signal to the second node, a source and a drain One of the source and the drain is electrically connected to the first node, and the source And the other of the drain is electrically connected to the second node, and a second transistor And a capacitive element for holding the potential of the signal supplied to the first node.

[0014] Specifically, a programmable logic device according to an aspect of the present invention includes a first circuit, A second circuit, a first transistor for controlling the electrical connection between the first circuit and the second circuit according to the potential of the gate, A first switch for controlling the supply of a signal to the first node, a second switch for controlling the supply of the signal to the second node, A second transistor in which one of the source and the drain and the gate are electrically connected to the first node, and the source and the drain The other of which is electrically connected to the second node, and a capacitive element for holding the potential of the signal supplied to the first node. And a capacitive element for holding the potential of the signal supplied to the first node. And a capacitive element for holding the potential of the signal supplied to the first node.

Advantages of the Invention

[0015] According to one aspect of the present invention, it is possible to provide a programmable logic device or a semiconductor device that can achieve low power consumption while suppressing a reduction in operating speed. Alternatively, according to one aspect of the present invention, it is possible to provide a programmable logic device or a semiconductor device that can achieve low power consumption while ensuring normal operation. According to one aspect of the present invention, it is possible to provide a programmable logic device or a semiconductor device that can achieve low power consumption while suppressing a reduction in operating speed. Alternatively, according to one aspect of the present invention, it is possible to provide a programmable logic device or a semiconductor device that can achieve low power consumption while ensuring normal operation. According to one aspect of the present invention, it is possible to provide a programmable logic device or a semiconductor device that can achieve low power consumption while ensuring normal operation. And a semiconductor device.

Brief Description of the Drawings

[0016]

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Embodiments for Carrying Out the Invention

[0017] Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings. However, the present invention is not limited to the following description, and those skilled in the art can easily understand that the form and details can be variously changed without departing from the spirit and scope of the present invention. Therefore, the present invention is not to be construed as being limited to the description of the embodiments shown below.

[0018] Note that a semiconductor device according to an aspect of the present invention includes various semiconductor integrated circuits using semiconductor elements, such as a microprocessor, an image processing circuit, a controller for a semiconductor display device, a DSP (Digital Signal Processor ), a microcontroller, a control circuit or a protection circuit for a battery such as a secondary battery. Further, a semiconductor device according to an aspect of the present invention includes various devices using the above semiconductor integrated circuits, such as an RF tag and a semiconductor display device, within its scope. The semiconductor display device includes a liquid crystal display device and a light-emitting element typified by an organic light-emitting element ). and so on. in its scope. Also, a semiconductor device according to an aspect of the present invention includes various devices such as an RF tag and a semiconductor display device using the above semiconductor integrated circuit within its scope. The semiconductor display device includes a liquid crystal display device and a light-emitting element represented by an organic light-emitting element A light-emitting device having a sub for each pixel, an electronic paper, a DMD (Digital Micromi rror Device), a PDP (Plasma Display Panel), F ED (Field Emission Display), etc., and other semiconductor display devices having semiconductor elements in the drive circuit are included in that category. In the present specification, connection means electrical connection, which corresponds to a state where current, voltage, or potential

[0019] can be supplied or transmitted. Therefore, the connected state does not necessarily refer to the directly connected state, but also includes the state where current, voltage, or potential is electrically connected through circuit elements such as wiring, resistors, diodes, and transistors so that they can be supplied or transmitted. Further, the source of a transistor means a source region that is a part of the semiconductor film functioning as the active layer, or a source electrode electrically connected to the semiconductor film. Similarly, the drain of a transistor means a drain region that is a part of the semiconductor film functioning as the active layer, or

[0020] a drain electrode electrically connected to the semiconductor film. Also, the gate means the gate electrode. The source and drain of a transistor are interchanged in their naming depending on the conductivity type of the transistor and the levels of the potentials applied to each terminal. Generally, in an n-channel type transistor, the terminal to which a low potential is applied is called the source, and the terminal to which a high potential is applied is called the drain. Also, in a p-channel type transistor, the terminal to which a low potential is applied is called the drain.

[0021] ​​​​​​​The terminal to which a high potential is applied is called the source and is called rain. In this specification, for convenience , assuming that the source and the drain are fixed, the connection relationship of the transistor may be described . However, in reality, the names of the source and the drain are interchanged according to the above potential relationship .

[0022] <Example Configuration 1 of Semiconductor Device> First, a configuration example of a semiconductor device according to an aspect of the present invention will be described. FIG. 1(A) illustrates the configuration of a semiconductor device 10 according to an aspect of the present invention .

[0023] A semiconductor device 10 according to an aspect of the present invention includes a first switch 11, a second switch 12, a transistor 13, a transistor 14, and a capacitive element 15. The first switch 11 has a function of controlling the supply of a signal including data supplied from the wiring BL to the node ND1 . In FIG. 1(A), the case where the conduction or non-conduction of the first switch 11 and the second switch 12 is selected according to the potential of the signal supplied to the wiring WL is illustrated. However, the first switch 11 and the second switch 12 may be selected to conduct or not conduct according to signals supplied via separate wirings . When the potential of the signal is supplied to the node ND1 via the first switch 11, the charge corresponding to the potential is accumulated in the node ND1, and data is written to the node ND1

[0024] . The second switch 12 has a function of controlling the supply of a signal including data supplied from the wiring BL to the node ND 2. When the potential of the signal is supplied to the node ND2 via the second switch 12, the charge corresponding to the potential is accumulated in the node ND2, and the node ND2 . When the potential of the signal is supplied to the node ND2 via the second switch 12, the charge corresponding to the potential is accumulated in the node ND2, and the node ND2 Data is written to ND2.

[0025] One of the source and drain of transistor 13 and the gate are electrically connected to node ND1. The other of the source and drain of transistor 13 is electrically connected to node ND2. The capacitor element 15 has a function of holding the potential of the signal supplied to node ND1 via the first switch 11. Specifically, the capacitor element 15 has a pair of electrodes, and one of the electrodes is electrically connected to node ND1. And one of the electrodes is electrically connected to node ND1. And one of the electrodes is electrically connected to node ND1.

[0026] Also, node ND2 is connected to wiring DL. Transistor 14 is selected to be conductive or non-conductive according to the potential of node ND2. Specifically, the wiring DL is connected to the gate of transistor 14. And when transistor 14 is in the conductive state, terminal 16a connected to one of the source or drain of transistor 14 and terminal 16b connected to the other of the source or drain of transistor 14 are electrically connected. Also, when transistor 14 is in the non-conductive state, terminal 16a connected to one of the source or drain of transistor 14 and terminal 16b connected to the other of the source or drain of transistor 14 are electrically separated. Also, node ND2 is connected to wiring DL. Transistor 14 is selected to be conductive or non-conductive according to the potential of node ND2. Specifically, the wiring DL is connected to the gate of transistor 14. And when transistor 14 is in the conductive state, terminal 16a connected to one of the source or drain of transistor 14 and terminal 16b connected to the other of the source or drain of transistor 14 are electrically connected. Also, when transistor 14 is in the non-conductive state, terminal 16a connected to one of the source or drain of transistor 14 and terminal 16b connected to the other of the source or drain of transistor 14 are electrically separated. And when transistor 14 is in the conductive state, terminal 16a connected to one of the source or drain of transistor 14 and terminal 16b connected to the other of the source or drain of transistor 14 are electrically connected. Also, when transistor 14 is in the non-conductive state, terminal 16a connected to one of the source or drain of transistor 14 and terminal 16b connected to the other of the source or drain of transistor 14 are electrically separated. And when transistor 14 is in the conductive state, terminal 16a connected to one of the source or drain of transistor 14 and terminal 16b connected to the other of the source or drain of transistor 14 are electrically connected. Also, when transistor 14 is in the non-conductive state, terminal 16a connected to one of the source or drain of transistor 14 and terminal 16b connected to the other of the source or drain of transistor 14 are electrically separated. And when transistor 14 is in the conductive state, terminal 16a connected to one of the source or drain of transistor 14 and terminal 16b connected to the other of the source or drain of transistor 14 are electrically connected. Also, when transistor 14 is in the non-conductive state, terminal 16a connected to one of the source or drain of transistor 14 and terminal 16b connected to the other of the source or drain of transistor 14 are electrically separated. And when transistor 14 is in the non-conductive state, terminal 16a connected to one of the source or drain of transistor 14 and terminal 16b connected to the other of the source or drain of transistor 14 are electrically separated. And when transistor 14 is in the non-conductive state, terminal 16a connected to one of the source or drain of transistor 14 and terminal 16b connected to the other of the source or drain of transistor 14 are electrically separated. And when transistor 14 is in the non-conductive state, terminal 16a connected to one of the source or drain of transistor 14 and terminal 16b connected to the other of the source or drain of transistor 14 are electrically separated.

[0027] And in one aspect of the present invention, the off-currents of the first switch 11 and the second switch 12 are made extremely small. Specifically, the off-currents of the transistors included in the first switch 11 and the transistors included in the second switch 12 are made extremely small. Further, in one aspect of the present invention, the off-current of transistor 13 is made extremely small. And in one aspect of the present invention, the off-currents of the first switch 11 and the second switch 12 are made extremely small. Specifically, the off-currents of the transistors included in the first switch 11 and the transistors included in the second switch 12 are made extremely small. And in one aspect of the present invention, the off-currents of the first switch 11 and the second switch 12 are made extremely small. Specifically, the off-currents of the transistors included in the first switch 11 and the transistors included in the second switch 12 are made extremely small. Further, in one aspect of the present invention, the off-current of transistor 13 is made extremely small. Further, in one aspect of the present invention, the off-current of transistor 13 is made extremely small.

[0028] A semiconductor with a wider bandgap and lower intrinsic carrier density than silicon The transistor in which the channel formation region is formed is made of ordinary silicon or germanium. The off-state current can be significantly reduced compared to transistors made of any semiconductor. Therefore, the transistor is connected to the first switch 11 and the second switch 12. Such a semiconductor is suitable for use as the transistor 13. Examples include oxide semiconductors and gallium nitride, which have a band gap more than twice that of silicon. can be done.

[0029] With the above configuration, when the first switch 11 and the transistor 13 are in a non-conductive state, ND1 can be placed in a floating state with extremely high insulation between it and other electrodes and wiring. Furthermore, with the above configuration, when the second switch 12 and the transistor 13 are in a non-conductive state, The node ND2 can be placed in a floating state with extremely high insulation between it and other electrodes and wiring. Therefore, the first switch 11, the second switch 12, and the transistor 13 are non-conductive. When in a conducting state, the voltage of a signal containing data is applied to the nodes ND1 and ND2. The position is maintained.

[0030] Unless otherwise specified, the off-state current in this specification refers to the amount of current that flows through a transistor in a cutoff region. This refers to the current that flows between the source and drain of a transistor.

[0031] Next, a configuration example of a PLD according to one embodiment of the present invention will be described. The configuration of a PLD 10a according to one embodiment of the present invention is shown as an example.

[0032] In the PLD 10a shown in FIG. 1B, the terminal 16a of the semiconductor device 10 shown in FIG. The output terminal of the logic block 18a is connected to the terminal 16b, and the input terminal of the logic block 18b is connected to the terminal 16c. In FIG. 1B, in PLD 10a, the node ND2 The potential of the logic block 18a and the logic block 18b is determined according to the potential of the wiring DL. This illustrates a case where an electrical connection is defined.

[0033] Therefore, the data supplied to PLD10a from the wiring BL is the configuration data. If it is a node, it will be configured according to the configuration data stored in node ND2. This makes it possible to control the electrical connection between the logic block 18a and the logic block 18b.

[0034] <Specific Configuration Example of Semiconductor Device> Next, a more specific example of the configuration of the semiconductor device 10 shown in FIG. 1(A) will be described. 2 illustrates an example of the structure of a semiconductor device 10 according to one embodiment of the present invention.

[0035] The semiconductor device 10 shown in FIG. 2 includes a transistor 11t functioning as the first switch 11 and a , a transistor 12t functioning as the second switch 12, a transistor 13, and a transistor The circuit includes a resistor 14 and a capacitance element 15.

[0036] The gate of the transistor 11t is connected to the wiring WL. t has one of its source and drain connected to the wiring BL, and the other of its source and drain connected to the wiring BL. The gate of the transistor 12t is connected to the wiring WL. In addition, one of the source and the drain of the transistor 12t is connected to the wiring BL. The other of the source and drain is connected to node ND2. One of the source and the drain and the gate are connected to node ND1. Also , for transistor 13, the other of the source and the drain is connected to node ND2. The node ND2 is connected to wiring DL, and the wiring DL is connected to the gate of transistor 14. For transistor 14, one of the source and the drain is connected to terminal 16a, and the other of the source and the drain is connected to terminal 16b.

[0037] <Example of operation of semiconductor device> Next, an example of the operation of the semiconductor device 10 shown in FIG. 2 will be described using the timing chart shown in FIG. 3. However, taking the case where all of transistor 11t, transistor 12t, transistor 13, and transistor 14 are all n-channel type as an example, the operation of the semiconductor device 10 will be described.

[0038] First, by applying a high-level potential VDD to the wiring WL, transistor 11t and transistor 12t are turned on. Then, the high-level potential VDD corresponding to the logical level of "1" supplied to the wiring BL is applied to node ND1 via transistor 11t and to node ND2 via transistor 12t, respectively. Specifically, node ND1 becomes a potential obtained by subtracting the threshold voltage of transistor 11t from the potential VDD. Also , node ND2 becomes a potential obtained by subtracting the threshold voltage of transistor 12t from the potential VDD (let the potential be VDD - Vth).

[0039] Note that when transistor 11t and transistor 12t are in the conductive state, a low-level potential (for example, the ground potential GND) corresponding to the logical level of "0" is supplied to the wiring BL. When this occurs, the ground potential GND is applied to the nodes ND1 and ND2. In the following description the operation of the semiconductor device 10 will be described by taking as an example the case where the potential VDD corresponding to the logical level of "1" is applied from the wiring BL to the nodes ND1 and the node ND2.

[0040] Next, by applying a low-level potential to the wiring WL, the transistors 11t and the transistor 12t are turned off. Therefore, data corresponding to the logical level of " 1" is held at the nodes ND1 and ND2. Also, since the transistor 13 is in the non-conducting state the nodes ND1 and ND2 are in a floating state. Therefore, the wiring DL also has a potential V which is the potential VDD minus the threshold voltage of the transistor 12t, the same as that of the node ND2, held. VDD-Vth.

[0041] Next, at time T1, the potential of the terminal 16a rises from the ground potential GND to the potential VDD. Then, due to the capacitive coupling of the capacitance C formed between the source and the gate of the transistor 14, as the potential of the terminal 16a rises, the potential of the gate of the transistor 14, that is, the wiring DL and the potential of the node ND2 also start to rise. In an ideal state where the parasitic capacitance added to the node ND2 is significantly smaller than the capacitance C formed between the source and the gate of the transistor 14 the potential of the wiring DL and the node ND2 rises to a potential 2VDD-Vth which is the potential VDD minus the threshold voltage of the transistor 12t plus a voltage corresponding to the difference between the ground potential GND and the potential VDD. Therefore, the gate voltage of the transistor 14 can be made sufficiently larger than the threshold voltage, and the above transistor 14 can be turned on. In the case of, the potential of the wiring DL and the node ND2 rises to a potential 2VDD-Vth which is the potential VDD minus the threshold voltage of the transistor 12t plus a voltage corresponding to the difference between the ground potential GND and the potential VDD. As a result, the transistor 14 can be turned on by making the gate voltage of the transistor 14 sufficiently larger than the threshold voltage. ​The state can be ensured. Therefore, the potential of terminal 16a is supplied to terminal 16b. .

[0042] In the semiconductor device 10 according to one aspect of the present invention, even if the power supply voltage supplied to the semiconductor device 10 becomes small and the potential difference between the potential VDD and the ground potential GND becomes small, the on-current of the transistor 14 can be prevented from decreasing, and thereby the operation speed of the semiconductor device 10 can be prevented from decreasing.

[0043] The rising width of the potential of node ND2 changes according to the capacitance ratio between the parasitic capacitance added to node ND2 and the capacitance C formed between the source and gate of transistor 1 4. That is, the smaller the parasitic capacitance added to node ND2 is compared to capacitance C, the larger the rising width of the potential of node ND2 is, and the larger the parasitic capacitance added to node ND2 is compared to capacitance C, the smaller the rising width of the potential of node ND2 is. Therefore, the smaller the parasitic capacitance of node ND2 is, the higher the on-current of transistor 14 can be increased, and it can be said that the operation speed of the semiconductor device 10 can be increased.

[0044] In addition, the longer the potential corresponding to the data can be held at node ND2, the longer the data holding time in the semiconductor device 10 can be. Therefore, in order to ensure a long data holding time, it is desirable that a capacitive element with a larger capacitance value is connected to node ND2. However, as described above, in order to increase the rising width of the gate potential due to the capacitive coupling of capacitance C of transistor 14, it is not preferable that a capacitive element with a large capacitance value including parasitic capacitance is connected to node ND2. That is, for transistor 14 The increase in the potential of the gate due to the capacitive coupling of the capacitance C and the data retention time in the semiconductor device 10 can be said to be in a trade-off relationship. It can be said that they are in a trade-off relationship.

[0045] In the semiconductor device 10 according to one aspect of the present invention, a capacitive element 15 is connected to the node ND1, and the connection between the node ND1 and the node ND2 is controlled by a transistor 13 whose gate is connected to the node ND1. Therefore, when the transistor 13 is in the non-conductive state, the node ND2 and the capacitive element 15 are electrically separated, and the capacitance value of the capacitive element 15 does not affect the increase in the potential of the gate of the transistor 14 due to the capacitive coupling of the capacitance C of the transistor 14. As time passes, when the potential of the node ND2 tends to decrease below the potential of the node ND1 due to the off-current of the transistor 12t, the leakage current flowing between the gate and the source or drain of the transistor 14, etc., a potential is supplied from the node ND1 to the node ND2 via the transistor 13. Therefore, the capacitive element 15 contributes to the retention of the potential at the node ND2. That is, in one aspect of the present invention, it can be said that the increase in the potential of the gate of the transistor 14 due to the capacitive coupling of the capacitance C can be increased while ensuring a long data retention time in the semiconductor device 10. and the connection between the node ND1 and the node ND2 is controlled by the transistor 13 whose gate is connected to the node ND1. Thus, when the transistor 13 is in the non-conductive state, the node ND2 and the capacitive element 15 are electrically separated, and the capacitance value of the capacitive element 15 does not participate in the increase in the potential of the gate of the transistor 14 due to the capacitive coupling of the capacitance C of the transistor 14. And as time elapses, when the potential of the node ND2 tends to decrease below the potential of the node ND1 due to the off-current of the transistor 12t, the leakage current flowing between the gate of the transistor 14 and the source or drain, etc., a potential is supplied from the node ND1 to the node ND2 via the transistor 13. Therefore, the capacitive element 15 contributes to the retention of the potential at the node ND2. That is, in one aspect of the present invention, it can be said that the increase in the potential of the gate of the transistor 14 due to the capacitive coupling of the capacitance C can be increased while ensuring a long data retention time in the semiconductor device 10. The connection between the node ND1 and the node ND2 is controlled by the transistor 13 whose gate is connected to the node ND1. Therefore, when the transistor 13 is in the non-conductive state, the node ND2 and the capacitive element 15 are electrically separated, and the capacitance value of the capacitive element 15 does not affect the increase in the potential of the gate of the transistor 14 due to the capacitive coupling of the capacitance C of the transistor 14. As time passes, when the potential of the node ND2 tends to decrease below the potential of the node ND1 due to the off-current of the transistor 12t, the leakage current flowing between the gate and the source or drain of the transistor 14, etc., a potential is supplied from the node ND1 to the node ND2 via the transistor 13. Therefore, the capacitive element 15 contributes to the retention of the potential at the node ND2. That is, in one aspect of the present invention, it can be said that the increase in the potential of the gate of the transistor 14 due to the capacitive coupling of the capacitance C can be increased while ensuring a long data retention time in the semiconductor device 10. When the transistor 13 is in the non-conductive state, the node ND2 and the capacitive element 15 are electrically separated, and the capacitance value of the capacitive element 15 does not affect the increase in the potential of the gate of the transistor 14 due to the capacitive coupling of the capacitance C of the transistor 14. As time passes, when the potential of the node ND2 tends to decrease below the potential of the node ND1 due to the off-current of the transistor 12t, the leakage current flowing between the gate and the source or drain of the transistor 14, etc., a potential is supplied from the node ND1 to the node ND2 via the transistor 13. Therefore, the capacitive element 15 contributes to the retention of the potential at the node ND2. That is, in one aspect of the present invention, it can be said that the increase in the potential of the gate of the transistor 14 due to the capacitive coupling of the capacitance C can be increased while ensuring a long data retention time in the semiconductor device 10. the capacitance value of the capacitive element 15 does not participate in the increase in the potential of the gate of the transistor 14 due to the capacitive coupling of the capacitance C of the transistor 14. And as time elapses, when the potential of the node ND2 tends to decrease below the potential of the node ND1 due to the off-current of the transistor 12t, the leakage current flowing between the gate of the transistor 14 and the source or drain, etc., a potential is supplied from the node ND1 to the node ND2 via the transistor 13. Therefore, the capacitive element 15 contributes to the retention of the potential at the node ND2. That is, in one aspect of the present invention, it can be said that the increase in the potential of the gate of the transistor 14 due to the capacitive coupling of the capacitance C can be increased while ensuring a long data retention time in the semiconductor device 10. the capacitance value of the capacitive element 15 does not participate in the increase in the potential of the gate of the transistor 14 due to the capacitive coupling of the capacitance C of the transistor 14. And as time elapses, when the potential of the node ND2 tends to decrease below the potential of the node ND1 due to the off-current of the transistor 12t, the leakage current flowing between the gate of the transistor 14 and the source or drain, etc., a potential is supplied from the node ND1 to the node ND2 via the transistor 13. Therefore, the capacitive element 15 contributes to the retention of the potential at the node ND2. That is, in one aspect of the present invention, it can be said that the increase in the potential of the gate of the transistor 14 due to the capacitive coupling of the capacitance C can be increased while ensuring a long data retention time in the semiconductor device 10. As time passes, when the potential of the node ND2 tends to decrease below the potential of the node ND1 due to the off-current of the transistor 12t, the leakage current flowing between the gate of the transistor 14 and the source or drain, etc., a potential is supplied from the node ND1 to the node ND2 via the transistor 13. Therefore, the capacitive element 15 contributes to the retention of the potential at the node ND2. That is, in one aspect of the present invention, it can be said that the increase in the potential of the gate of the transistor 14 due to the capacitive coupling of the capacitance C can be increased while ensuring a long data retention time in the semiconductor device 10. As time passes, when the potential of the node ND2 tends to decrease below the potential of the node ND1 due to the off-current of the transistor 12t, the leakage current flowing between the gate of the transistor 14 and the source or drain, etc., a potential is supplied from the node ND1 to the node ND2 via the transistor 13. Therefore, the capacitive element 15 contributes to the retention of the potential at the node ND2. That is, in one aspect of the present invention, it can be said that the increase in the potential of the gate of the transistor 14 due to the capacitive coupling of the capacitance C can be increased while ensuring a long data retention time in the semiconductor device 10. a potential is supplied from the node ND1 to the node ND2 via the transistor 13. Therefore, the capacitive element 15 contributes to the retention of the potential at the node ND2. That is, in one aspect of the present invention, it can be said that the increase in the potential of the gate of the transistor 14 due to the capacitive coupling of the capacitance C can be increased while ensuring a long data retention time in the semiconductor device 10. Therefore, the capacitive element 15 contributes to the retention of the potential at the node ND2. That is, in one aspect of the present invention, it can be said that the increase in the potential of the gate of the transistor 14 due to the capacitive coupling of the capacitance C can be increased while ensuring a long data retention time in the semiconductor device 10. That is, in one aspect of the present invention, it can be said that the increase in the potential of the gate of the transistor 14 due to the capacitive coupling of the capacitance C can be increased while ensuring a long data retention time in the semiconductor device 10. while increasing the increase in the potential of the gate of the transistor 14 due to the capacitive coupling of the capacitance C, it can be said that a long data retention time in the semiconductor device 10 can be ensured. it can be said that a long data retention time in the semiconductor device 10 can be ensured.

[0046] Since the capacitance value of the capacitive element 15 connected to the node ND1 is larger than the capacitance value of the parasitic capacitance added to the node ND2, the channel width of the transistor 11t that controls the supply of potential to the node ND1 is preferably larger than the channel widths of the transistor 12t and the transistor 13 that control the supply of potential to the node ND2. Since the capacitance value of the capacitive element 15 connected to the node ND1 is larger than the capacitance value of the parasitic capacitance added to the node ND2, the channel width of the transistor 11t that controls the supply of potential to the node ND1 is preferably larger than the channel widths of the transistor 12t and the transistor 13 that control the supply of potential to the node ND2. Since the capacitance value of the capacitive element 15 connected to the node ND1 is larger than the capacitance value of the parasitic capacitance added to the node ND2, the channel width of the transistor 11t that controls the supply of potential to the node ND1 is preferably larger than the channel widths of the transistor 12t and the transistor 13 that control the supply of potential to the node ND2.

[0047] At time T2, when the potential of terminal 16a changes from VDD to the ground potential GND, due to the capacitive coupling of the capacitance C of transistor 14, the potential of node ND2 drops from the potential VDD to the potential VDD - Vth obtained by subtracting the threshold voltage of transistor 12t. At time T2, when the potential of terminal 16a changes from VDD to the ground potential GND, due to the capacitive coupling of the capacitance C of transistor 14, the potential of node ND2 drops from the potential VDD to the potential VDD - Vth obtained by subtracting the threshold voltage of transistor 12t. At time T2, when the potential of terminal 16a changes from VDD to the ground potential GND, due to the capacitive coupling of the capacitance C of transistor 14, the potential of node ND2 drops from the potential VDD to the potential VDD - Vth obtained by subtracting the threshold voltage of transistor 12t.

[0048] <Example Configuration 2 of the Semiconductor Device> Next, another configuration example of the semiconductor device 10 shown in Fig. 1(A) will be described. Fig. 4(A) shows an example of the semiconductor device 10. The semiconductor device 10 shown in Fig. 4(A) has a switch 11, a switch 12, a transistor 13, and a transistor 14, similar to the semiconductor device 10 shown in Fig. 1(A). However, the semiconductor device 10 shown in Fig. 4(A) is different in configuration from the semiconductor device 10 shown in Fig. 1(A) in that an inverter 30 and an inverter 31 for holding the potential of node ND1 are provided instead of the capacitor element 15. Next, another configuration example of the semiconductor device 10 shown in Fig. 1(A) will be described. Fig. 4(A) shows an example of the semiconductor device 10. The semiconductor device 10 shown in Fig. 4(A) has a switch 11, a switch 12, a transistor 13, and a transistor 14, similar to the semiconductor device 10 shown in Fig. 1(A). However, the semiconductor device 10 shown in Fig. 4(A) is different in configuration from the semiconductor device 10 shown in Fig. 1(A) in that an inverter 30 and an inverter 31 for holding the potential of node ND1 are provided instead of the capacitor element 15. Next, another configuration example of the semiconductor device 10 shown in Fig. 1(A) will be described. Fig. 4(A) shows an example of the semiconductor device 10. The semiconductor device 10 shown in Fig. 4(A) has a switch 11, a switch 12, a transistor 13, and a transistor 14, similar to the semiconductor device 10 shown in Fig. 1(A). However, the semiconductor device 10 shown in Fig. 4(A) is different in configuration from the semiconductor device 10 shown in Fig. 1(A) in that an inverter 30 and an inverter 31 for holding the potential of node ND1 are provided instead of the capacitor element 15. Next, another configuration example of the semiconductor device 10 shown in Fig. 1(A) will be described. Fig. 4(A) shows an example of the semiconductor device 10. The semiconductor device 10 shown in Fig. 4(A) has a switch 11, a switch 12, a transistor 13, and a transistor 14, similar to the semiconductor device 10 shown in Fig. 1(A). However, the semiconductor device 10 shown in Fig. 4(A) is different in configuration from the semiconductor device 10 shown in Fig. 1(A) in that an inverter 30 and an inverter 31 for holding the potential of node ND1 are provided instead of the capacitor element 15. Specifically, in Fig. 4(A), the input terminal of inverter 30 and the output terminal of inverter 31 are electrically connected to node ND1, and the output terminal of inverter 30 and the input terminal of inverter 31 are electrically connected. In the semiconductor device 10 shown in Fig. 4(A), with the above configuration, the potential of node ND1 can be held by inverter 30 and inverter 31. Specifically, in Fig. 4(A), the input terminal of inverter 30 and the output terminal of inverter 31 are electrically connected to node ND1, and the output terminal of inverter 30 and the input terminal of inverter 31 are electrically connected. In the semiconductor device 10 shown in Fig. 4(A), with the above configuration, the potential of node ND1 can be held by inverter 30 and inverter 31.

[0049] Specifically, in Fig. 4(A), the input terminal of inverter 30 and the output terminal of inverter 31 are electrically connected to node ND1, and the output terminal of inverter 30 and the input terminal of inverter 31 are electrically connected. In the semiconductor device 10 shown in Fig. 4(A), with the above configuration, the potential of node ND1 can be held by inverter 30 and inverter 31. Specifically, in Fig. 4(A), the input terminal of inverter 30 and the output terminal of inverter 31 are electrically connected to node ND1, and the output terminal of inverter 30 and the input terminal of inverter 31 are electrically connected. In the semiconductor device 10 shown in Fig. 4(A), with the above configuration, the potential of node ND1 can be held by inverter 30 and inverter 31. Specifically, in Fig. 4(A), the input terminal of inverter 30 and the output terminal of inverter 31 are electrically connected to node ND1, and the output terminal of inverter 30 and the input terminal of inverter 31 are electrically connected. In the semiconductor device 10 shown in Fig. 4(A), with the above configuration, the potential of node ND1 can be held by inverter 30 and inverter 31. Specifically, in Fig. 4(A), the input terminal of inverter 30 and the output terminal of inverter 31 are electrically connected to node ND1, and the output terminal of inverter 30 and the input terminal of inverter 31 are electrically connected. In the semiconductor device 10 shown in Fig. 4(A), with the above configuration, the potential of node ND1 can be held by inverter 30 and inverter 31. Specifically, in Fig. 4(A), the input terminal of inverter 30 and the output terminal of inverter 31 are electrically connected to node ND1, and the output terminal of inverter 30 and the input terminal of inverter 31 are electrically connected. In the semiconductor device 10 shown in Fig. 4(A), with the above configuration, the potential of node ND1 can be held by inverter 30 and inverter 31.

[0050] Next, another configuration example of the semiconductor device 10 shown in Fig. 1(A) will be described. Fig. 4(B) shows an example of the semiconductor device 10. The semiconductor device 10 shown in Fig. 4(B) has a switch 11, a transistor 13, a transistor 14, similar to the semiconductor device 10 shown in Fig. 1(A). Next, another configuration example of the semiconductor device 10 shown in Fig. 1(A) will be described. Fig. 4(B) shows an example of the semiconductor device 10. The semiconductor device 10 shown in Fig. 4(B) has a switch 11, a transistor 13, a transistor 14, similar to the semiconductor device 10 shown in Fig. 1(A). Next, another configuration example of the semiconductor device 10 shown in Fig. 1(A) will be described. Fig. 4(B) shows an example of the semiconductor device 10. The semiconductor device 10 shown in Fig. 4(B) has a switch 11, a transistor 13, a transistor 14, similar to the semiconductor device 10 shown in Fig. 1(A). , and has a capacitive element 15. However, the semiconductor device 10 shown in Fig. 4(B) does not have a switch 1 2, and the transistor 13 has a pair of gates overlapping with a semiconductor film interposed therebetween, which is different in configuration from the semiconductor device 10 shown in Fig. 1(A). Specifically, in Fig. 4(B), one gate (front gate

[0051] ) of the transistor 13 is connected to the node ND1, and the other gate of the transistor 13 is connected to the wiring BG . When supplying the potential of a signal including data to the nodes ND1 and ND2, by supplying a potential higher than the source and drain of the transistor 13 to the wiring BG , the threshold voltage of the transistor 13 is shifted in the negative direction. With the above configuration , when a high-level potential is held at the node ND2, even if the switch 12 is not provided , a low-level potential can be supplied to the node ND2 through the transistor 13 .

[0052] The semiconductor devices 10 shown in Figs. 4(A) and 4(B) may further have other circuit elements such as transistors, diodes, resistive elements, capacitive elements, inductors, etc., if necessary .

[0053] <Example Configuration 3 of Semiconductor Device> Next, a configuration example of a semiconductor device 10b that controls the electrical connection between the terminal 16a and the terminal 16b by combining a plurality of the semiconductor devices 10 shown in Fig. 2 will be described .

[0054] Fig. 5 shows an example of the semiconductor device 10b. The semiconductor device 10b has a plurality of the semiconductor devices 10 shown in Fig. 2 . In Fig. 5, the semiconductor device 10b has the semiconductor devices 10-1 and the semiconductor device ​​An example is given of the case where there are two semiconductor devices shown by 10-2.

[0055] Further, the semiconductor device 10b has a transistor 17-1 for controlling the electrical connection between the terminal 16a and the terminal 16b connected in series with the transistor 14 that the semiconductor device 10-1 has. Furthermore, the semiconductor device 10b has a transistor 17-2 for controlling the electrical connection between the terminal 16a and the terminal 16b connected in series with the transistor 14 that the semiconductor device 10-2 has. The wiring CL1 is connected to the gate of the transistor 17-1, and the wiring CL2 is connected to the gate of the transistor 17-2.

[0056] In the semiconductor device 10-1 and the semiconductor device 10-2, conduction or non-conduction of the transistor 14 is selected according to the potential of the signal including data held at the node ND2 and the wiring DL. Therefore, by selecting either one of the wiring CL1 and the wiring CL2 to be at a high level potential, the connection between the terminal 16a and the terminal 16b is controlled according to the potential of the signal including data held in either the semiconductor device 10-1 or the semiconductor device 10-2. Specifically, when a high level potential is supplied to the wiring CL1 and a low level potential is supplied to the wiring CL2, the transistor 17-1 becomes conductive and the transistor 17-2 becomes non-conductive. Therefore, according to the potential of the signal including data held in the semiconductor device 10-1, the connection between the terminal 16a and the terminal 1 6b is controlled by the transistor 14 that the semiconductor device 10-1 has. When a low level potential is supplied to the wiring CL1 and a high level potential is supplied to the wiring CL2,

[0057] Specifically, when a high level potential is supplied to the wiring CL1 and a low level potential is supplied to the wiring CL2, the transistor 17-1 becomes conductive and the transistor 17-2 becomes non-conductive. Therefore, according to the potential of the signal including data held in the semiconductor device 10-1, the connection between the terminal 16a and the terminal 1 6b is controlled by the transistor 14 that the semiconductor device 10-1 has. When a low level potential is supplied to the wiring CL1 and a high level potential is supplied to the wiring CL2, the connection between the terminal 16a and the terminal 16b is controlled by the transistor 14 that the semiconductor device 10-1 has according to the potential of the signal including data held in the semiconductor device 10-1. When a low level potential is supplied to the wiring CL1 and a high level potential is supplied to the wiring CL2, the connection between the terminal 16a and the terminal 16b is controlled according to the potential of the signal including data held in the semiconductor device 10-1 by the transistor 14 that the semiconductor device 10-1 has. When a low level potential is supplied to the wiring CL1 and a high level potential is supplied to the wiring CL2, When a potential of a certain level is supplied, transistor 17-2 becomes conductive and transistor 17-1 becomes non-conductive. Therefore, according to the potential of the signal including the data held in semiconductor device 10-2, the connection between terminal 1 6a and terminal 16b is controlled by transistor 14 included in semiconductor device 10-2.

[0058] <More detailed configuration example of PLD> In the PLD according to one aspect of the present invention, a switch for initializing the potential of terminal 16b or a latch for holding the potential of terminal 16b may be electrically connected to terminal 16b. The state where switch 20 for initializing the potential of terminal 16b and latch 22 for holding the potential of terminal 16b are electrically connected to terminal 16b is shown in FIG. 6. .

[0059] Switch 20 has a function of controlling the electrical connection between terminal 16b and wiring 21 to which an initialization potential is applied. In one aspect of the present invention, by electrically connecting switch 20 to terminal 16b, after the PLD is powered on, the potential of terminal 16b can be kept at a low level, so that an intermediate potential can be prevented from being applied to terminal 16b. As a result, a through current can be prevented from occurring in logic block 18b whose input terminal is connected to terminal 16b. .

[0060] Also, latch 22 shown in FIG. 6 has a function of keeping the potential of terminal 16b at either a high level or a low level. Specifically, latch 22 includes inverter 23 and a p-channel type transistor 24. The input terminal of inverter 23 is electrically connected to terminal 16b. Continuing, the output terminal of the inverter 23 is electrically connected to the gate of the transistor 24. One of the source and drain of the transistor 24 is electrically connected to a wiring 25 to which a potential higher than that of the wiring 21 is applied, and the other is electrically connected to the terminal 16b.

[0061] In one aspect of the present invention, by electrically connecting the latch 22 having the above configuration to the terminal 16b, after the PLD is powered on, the potential of the terminal 16b can be maintained at either a high level or a low level. Therefore, it is possible to prevent an intermediate potential from being applied to the terminal 16b. As a result, it is possible to prevent a through current from occurring in the logic block 18b whose input terminal is connected to the terminal 16b.

[0062] FIG. 7(A) illustrates one form of a logic block (LB) 40. The logic block 40 shown in FIG. 7(A) includes a look-up table (LUT) 41, a flip-flop 42, and a storage device 43. The LUT 41 defines a logical operation to be performed according to the configuration data of the storage device 43. Specifically, the LUT 41 determines one output value for the input values of a plurality of input signals given to the input terminal 44. Then, a signal including the above output value is output from the LUT 41. The flip-flop 42 holds the signal output from the LUT 41 and outputs an output signal corresponding to the signal in synchronization with the signal CLK from the first output terminal 45 and the second output terminal 46. Note that the logic block 40 further has a multiplexer circuit, and the multiplexer circuit selects whether the output signal from the LUT 41 passes through the flip-flop 42.

[0063] ​ It may be configured to cut.

[0064] Also, the type of flip-flop 42 may be defined by configuration data. It may be configured to be able to do so. Specifically, according to the configuration data, the flip flop 42 may have the function of any one of a D-type flip-flop, a T-type flip-flop, a JK-type flip-flop , or an RS-type flip-flop.

[0065] Also, another form of the logic block 40 is illustrated in FIG. 7(B). The logic block 40 shown in FIG. 7(B) has a configuration in which an AND circuit 47 is added to the logic block 40 shown in FIG. 7(A). A signal from the flip-flop 42 is given as a positive logic input to the AND circuit 47, and a signal INIT2 for initializing the potential of the wiring DL is given as a negative logic input. With the above configuration, the potential of the wiring to which the output signal from the logic block 40 is supplied can be initialized. Therefore, it is possible to prevent a large amount of current from flowing between the logic blocks 40 and prevent damage to the PLD.

[0066] Also, another form of the logic block 40 is illustrated in FIG. 7(C). The logic block 40 shown in FIG. 7(C) has a configuration in which a multiplexer 48 is added to the logic block 40 shown in FIG. 7(A). Also, the logic block 40 shown in FIG. 7(C) has two storage devices 43 represented by a storage device 43a and a storage device 43b. The logic operation performed by the LUT41 is defined according to the configuration data of the storage device 4 3a. Also, the multiplexer 48 selects between the output signal from the LUT41 and the signal from the flip-flop 42. ​ The output signals are being input. Then, the multiplexer 48 stores in accordance with the configuration data stored in the storage device 43b, selects one of the two output signals, and has a function of outputting. The output signal from the multiplexer 48 is output from the first output terminal 45 and the second output terminal 46.

[0067] FIG. 8(A) schematically shows a part of the structure of the PLD 50 as an example. As shown in FIG. 8(A), the PLD 50 has a plurality of logic blocks (LB) 40, a wiring group 51 connected to any one of the plurality of logic blocks 40, and a switch circuit 52 that controls the connection between the wirings constituting the wiring group 51. The wiring group 51 and the switch circuit 52 correspond to the wiring resource 53. .

[0068] FIG. 8(B) shows a configuration example of the switch circuit 52. The switch circuit 52 shown in FIG. 8(B) has a function of controlling the connection structure between the wiring 55 and the wiring 56 included in the wiring group 51. Specifically, the switch circuit 52 has transistors 57 to 62. The transistors 57 to 62 correspond to the transistor 14 of the semiconductor device 10. . Although not shown, the gates of the transistors 57 to 62 are connected to the wiring DL and the node ND2 of the plurality of semiconductor devices 10, respectively. Then, the selection (switching) of the conduction state or non-conduction state of the transistors 57 to 62 is determined by the data held in the node ND2 and the wiring DL of the semiconductor device 10.

[0069] The transistor 57 is at Point A in the wiring 55 and Point The transistor 58 has a function of controlling the electrical connection of the wiring 55. It has the function of controlling the electrical connection between intB and Point C in the wiring 56. The transistor 59 is connected to Point A in the wiring 55 and Point D in the wiring 56. The transistor 60 has a function of controlling the electrical connection. It has the function of controlling the electrical connection between Point B and Point D in the wiring 56. The resistor 61 controls the electrical connection between Point A and Point B in the wiring 55. The transistor 62 functions to connect the voltages at Points C and D on the wiring 56. It has the function of controlling electrical connections.

[0070] The switch circuit 52 electrically connects the wiring group 51 to the terminal 54 of the PLD 50. It has the function of controlling.

[0071] FIG. 9 shows an example of the overall configuration of the PLD 50. In FIG. 9, the PLD 50 includes an I / O element. Element 70, PLL (phase lock loop) 71, RAM 72, multiplier 7 The I / O element 70 receives signals from external circuits of the PLD 50. or has a function as an interface that controls the output of signals to an external circuit. The PLL 71 has a function of generating a signal CLK. The RAM 72 is used for logical operations. The multiplier 73 corresponds to a logic circuit dedicated to multiplication. If D50 includes a multiplication function, the multiplier 73 does not necessarily have to be provided.

[0072] <Example of cross-sectional structure of semiconductor device> Next, the transistor 13 and the transistor 14 included in the semiconductor device 10 shown in FIG. The cross-sectional structure of 14 is shown as an example in FIG. 10.

[0073] In FIG. 10, a transistor 13 having a channel formation region in an oxide semiconductor film is formed on a transistor 14 having a channel formation region in a single crystal silicon substrate is exemplified.

[0074] Transistor 14 may have a channel formation region in a semiconductor film or semiconductor substrate such as amorphous, microcrystalline, polycrystalline, or single crystal silicon or germanium magnesium. Alternatively, transistor 14 may have a channel formation region in an oxide semiconductor film or oxide semiconductor substrate. If all transistors have a channel formation region in an oxide semiconductor film or oxide semiconductor substrate, transistor 13 does not necessarily have to be stacked on transistor 14, and transistor 13 and transistor 14 may be formed in the same layer.

[0075] When forming transistor 14 using a thin film of silicon, the thin film may use amorphous silicon produced by a vapor phase growth method such as plasma CVD method or sputtering method, polycrystalline silicon obtained by crystallizing amorphous silicon by treatment such as laser annealing, single crystal silicon obtained by implanting hydrogen ions or the like into a single crystal silicon wafer and peeling off the surface layer portion, etc.

[0075]

[0076]

[0077] Semiconductor substrate 400 can use, for example, a silicon substrate, a germanium substrate, a silicon germanium substrate, etc. In FIG. 10, the case of using a single crystal silicon substrate as semiconductor substrate 400 is exemplified.

[0077] ​​The transistor 14 is electrically isolated by an element isolation method. Then, the selective oxidation method (LOCOS method: Local Oxidation of Silic on method), trench isolation method (STI method: Shallow Trench Isolati method) In FIG. 10, a transistor 14 is formed using trench isolation. Specifically, in FIG. 10, an electrode is formed on a semiconductor substrate 400. After forming a trench by etching or the like, an insulating material containing silicon oxide or the like is filled into the trench. The transistor 14 is isolated by the element isolation region 401 formed by embedding. The case is illustrated.

[0078] In addition, an n-channel transistor 14 is formed between the element isolation regions 401. In the region to be formed, a p-well 402 in which an impurity element that imparts p-type conductivity is selectively introduced is formed. is provided.

[0079] The transistor 14 then has a source region or drain region formed in the p-well 402. impurity regions 404 and 405 functioning as gate regions, and a gate electrode 406; The semiconductor device has a gate insulating film 407 provided between a semiconductor substrate 400 and a gate electrode 406 . The gate electrode 406 is connected to the impurity region 404 and the impurity region 405 with a gate insulating film 407 sandwiched therebetween. It overlaps with the channel forming region formed between 405.

[0080] An insulating film 411 is provided over the transistor 14. The insulating film 411 has an opening. In the opening, impurity regions 404 and 405 are formed. A conductive film 412 and a conductive film 413 are formed, which are electrically connected to each other.

[0081] The conductive film 412 is electrically connected to a conductive film 418 formed on the insulating film 411, and the conductive film 413 is electrically connected to a conductive film 419 formed on the insulating film 411.

[0082] An insulating film 420 is formed on the conductive films 418 and 419. An opening is formed in the insulating film 420, and a conductive film 421 electrically connected to the conductive film 419 is formed in the opening.

[0083] In FIG. 10, a transistor 13 is formed on the insulating film 420.

[0084] The transistor 13 includes a semiconductor film 430 containing an oxide semiconductor, conductive films 432 and 433 that function as a source electrode or a drain electrode on the semiconductor film 430, a gate insulating film 431 on the semiconductor film 430, the conductive films 432 and 433, and a conductive film 434 that is located on the gate insulating film 431 and overlaps the semiconductor film 430 between the conductive films 432 and 433 and functions as a gate electrode. Note that the conductive film 433 is electrically connected to the conductive film 421.

[0085] An insulating film 441 and an insulating film 442 are sequentially stacked on the transistor 13. Openings are provided in the insulating films 441 and 442, and a conductive film 443 in contact with the conductive films 432 and 434 is provided on the insulating film 442 in the opening.

[0086] In FIG. 10, the transistor 13 has the conductive film 434 on one side of the semiconductor film 430, ​​​​​​It is sufficient to have at least, but a pair of gate electrodes sandwiching the semiconductor film 430 may be provided. The transistor 13 may have a pair of gate electrodes sandwiching the semiconductor film 430.

[0087] When the transistor 13 has a pair of gate electrodes sandwiching the semiconductor film 430, a signal for controlling the conductive state or non-conductive state is applied to one of the gate electrodes, and the other gate electrode may be in a state where a potential is applied from another source. In this case, the same height potential may be applied to the pair of gate electrodes, or only a fixed potential such as a ground potential may be applied to the other gate electrode. By controlling the height of the potential applied to the other gate electrode, the threshold voltage of the transistor can be controlled.

[0088] Also, in FIG. 10, an example is shown where the transistor 13 has a single gate structure having a channel formation region corresponding to one conductive film 434. However, the transistor 13 may have a multi-gate structure having a plurality of channel formation regions in one active layer by having a plurality of electrically connected gate electrodes.

[0089] 〈Regarding the semiconductor film〉 Note that an oxide semiconductor (purified Oxide Semiconductor) that has been purified by reducing impurities such as moisture or hydrogen that act as electron donors and also reducing oxygen deficiency is of the i-type (intrinsic semiconductor) or extremely close to the i-type. Therefore, a transistor having a channel formation region in a purified oxide semiconductor film has an extremely small off-current and high reliability.

[0090] Specifically, for a transistor having a channel formation region in a purified oxide semiconductor film The small off-current can be proven by various experiments. For example, even in an element with a channel width of 1× 10 6 μm and a channel length of 10 μm, when the voltage between the source electrode and the drain electrode (drain voltage) is in the range of 1 V to 10 V, the off-current can be made below the measurement limit of the semiconductor parameter analyzer, that is, 1×10 A or less. In this case, it can be seen that the off-current normalized by the channel width of the transistor is 100 zA / μm or less. -13 In addition, a circuit is used in which a capacitor element and a transistor are connected and the charge flowing into or flowing out of the capacitor element is controlled by the transistor to measure the off-current. In this measurement, a highly purified oxide semiconductor film is used for the channel formation region of the transistor, and the off-current of the transistor is measured from the change in the charge amount per unit time of the capacitor element. As a result, when the voltage between the source electrode and the drain electrode of the transistor is 3 V, it was found that an even smaller off-current of several tens of yA / μm can be obtained. Therefore, a transistor using a highly purified oxide semiconductor film for the channel formation region has a significantly smaller off-current than a transistor using crystalline silicon. When an oxide semiconductor film is used as the semiconductor film, the oxide semiconductor preferably contains at least indium (In) or zinc (Zn). In addition, in order to reduce the variation in the electrical characteristics of the transistor using the oxide semiconductor, it is preferable to have gallium (Ga) in addition to them. Also, it is preferable to have tin (Sn) as a stabilizer. Further, it is preferable to have hafnium (Hf) as a stabilizer. When the voltage between the source electrode and the drain electrode of the transistor is 3 V, it was found that an even smaller off-current of several tens of yA / μm can be obtained. Therefore, a transistor using a highly purified oxide semiconductor film for the channel formation region has a significantly smaller off-current than a transistor using crystalline silicon.

[0091] Note that when an oxide semiconductor film is used as the semiconductor film, the oxide semiconductor preferably contains at least indium (In) or zinc (Zn). In addition, in order to reduce the variation in the electrical characteristics of the transistor using the oxide semiconductor, it is preferable to have gallium (Ga) in addition to them. Also, it is preferable to have tin (Sn) as a stabilizer. Further, it is preferable to have hafnium (Hf) as a stabilizer. In addition, it is preferable to have gallium (Ga) in addition to them. Also, it is preferable to have tin (Sn) as a stabilizer. Further, it is preferable to have hafnium (Hf) as a stabilizer. Preferably, it has. Also, it preferably has aluminum (Al) as a stabilizer. Preferably, it contains zirconium (Zr) as a stabilizer. .

[0092] Among oxide semiconductors, In-Ga-Zn-based oxides, In-Sn-Zn-based oxides, etc. Unlike silicon carbide, gallium nitride, or gallium oxide, it is possible to fabricate transistors with excellent electrical characteristics by sputtering or wet methods, and it has advantages such as excellent mass productivity. Also, unlike silicon carbide, gallium nitride, or gallium oxide, the above In-Ga-Zn-based oxide can fabricate transistors with excellent electrical characteristics on a glass substrate. Moreover, it can also accommodate the enlargement of the substrate size.

[0093] Also, as other stabilizers, it may contain any one or more of lanthanum (La), cerium (Ce), praseodymium (Pr), neodymium (Nd), samarium (Sm), europium (Eu), gadolinium (Gd), terbium (Tb), dysprosium (Dy), holmium (Ho), erbium (Er), thulium (Tm), ytterbium (Yb), lutetium (Lu), which are lanthanoids.

[0094] For example, as the oxide semiconductor, indium oxide, gallium oxide, tin oxide, zinc oxide, In-Zn-based oxides, Sn-Zn-based oxides, Al-Zn-based oxides, Zn-Mg-based oxides, Sn-Mg-based oxides, In-Mg-based oxides, In-Ga-based oxides, In-Ga-Zn-based acid oxides (also denoted as IGZO), In-Al-Zn-based oxides, In-Sn-Zn-based oxides , Sn-Ga-Zn-based oxides, Al-Ga-Zn-based oxides, Sn-Al-Zn-based oxides, In-Hf-Zn-based oxides, In-La-Zn-based oxides, In-Pr-Zn-based oxides, I n-Nd-Zn-based oxides, In-Ce-Zn-based oxides, In-Sm-Zn-based oxides, In -Eu-Zn-based oxides, In-Gd-Zn-based oxides, In-Tb-Zn-based oxides, In- Dy-Zn-based oxides, In-Ho-Zn-based oxides, In-Er-Zn-based oxides, In-T m-Zn-based oxides, In-Yb-Zn-based oxides, In-Lu-Zn-based oxides, In-Sn -Ga-Zn-based oxides, In-Hf-Ga-Zn-based oxides, In-Al-Ga-Zn-based acid oxides, In-Sn-Al-Zn-based oxides, In-Sn-Hf-Zn-based oxides, In-Hf -Al-Zn-based oxides can be used.

[0095] Note that, for example, the In-Ga-Zn-based oxide means an oxide containing In, Ga, and Zn, and the ratio of In, Ga, and Zn is not limited. Also, it may contain metal elements other than In, Ga, and Zn. The In-Ga-Zn-based oxide has a sufficiently high resistance in the absence of an electric field and can make the off-current sufficiently small, and also has a high mobility.

[0096] For example, a relatively high mobility can be obtained easily with an In-Sn-Zn-based oxide. However, even with an In-Ga-Zn-based oxide, the mobility can be increased by reducing the bulk defect density.

[0097] Hereinafter, the structure of the oxide semiconductor film will be described.

[0098] The oxide semiconductor film is roughly classified into a single-crystalline oxide semiconductor film and a non-single-crystalline oxide semiconductor film. The non-single-crystal oxide semiconductor film includes an amorphous oxide semiconductor film, a microcrystalline oxide semiconductor film, a polycrystalline oxide semiconductor film, and a polycrystalline oxide semiconductor film. Compound semiconductor film, CAAC-OS (C Axis Aligned Crystallin e Oxide Semiconductor) film, etc.

[0099] An amorphous oxide semiconductor film has an irregular atomic arrangement in the film and does not contain crystalline components. The oxide semiconductor film does not have any crystalline parts even in the microscopic regions, and the entire film has a completely amorphous structure. A typical example is an oxide semiconductor film.

[0100] The microcrystalline oxide semiconductor film is made up of, for example, microcrystals (nanocrystals) with a size of 1 nm or more and less than 10 nm. Therefore, a microcrystalline oxide semiconductor film has a higher crystallinity than an amorphous oxide semiconductor film. The atomic arrangement is highly regular. Therefore, the microcrystalline oxide semiconductor film has a higher atomic regularity than the amorphous oxide semiconductor film. It has the advantage of having a lower defect level density than silicon.

[0101] The CAAC-OS film is one of the oxide semiconductor films with multiple crystal parts. The crystal part is small enough to fit inside a cube with a side length of less than 100 nm. The crystals contained in the OS film are cubes with sides of less than 10 nm, 5 nm, or 3 nm. The CAAC-OS film has a smaller size than the microcrystalline oxide semiconductor film. The CAAC-OS film has the advantage of having a low density of defect states. cormorant.

[0102] The CAAC-OS film was observed under a transmission electron microscope (TEM). When observed under a tron microscope, clear boundaries between the crystalline parts are observed. It is not possible to confirm the grain boundary. It can be said that the AAC-OS film is less likely to cause a decrease in electron mobility due to crystal grain boundaries.

[0103] When the CAAC-OS film is observed by TEM from a direction substantially parallel to the sample surface (cross-sectional TEM observation), it can be confirmed that metal atoms are arranged in layers in the crystal part. Each layer of metal atoms has a shape that reflects the concavity and convexity of the surface (also referred to as the formed surface) or the upper surface of the CAAC-OS film, and is arranged parallel to the formed surface or the upper surface of the CAAC-OS film. In this specification, "parallel" refers to a state in which two straight lines are arranged at an angle of -10° or more and 10° or less. Therefore, the case of -5° or more and 5° or less is also included. Also, "perpendicular" refers to a state in which two straight lines are arranged at an angle of 80° or more and 100° or less. Therefore, the case of 85° or more and 95° or less is also included.

[0104] In this specification, "parallel" means a state where two straight lines are arranged at an angle of -10° or more and 10° or less. Thus, the case of -5° or more and 5° or less is also included. Also, "perpendicular" means a state where two straight lines are arranged at an angle of 80° or more and 100° or less. Thus, the case of 85° or more and 95° or less is also included. On the other hand, when the CAAC-OS film is observed by TEM from a direction substantially perpendicular to the sample surface (planar TEM observation), it can be confirmed that metal atoms are arranged in a triangular or hexagonal shape in the crystal part. However, no regularity is seen in the arrangement of metal atoms between different crystal parts.

[0105] From cross-sectional TEM observation and planar TEM observation, it can be seen that the crystal part of the CAAC-OS film has orientation. When structural analysis is performed on the CAAC-OS film using an X-ray diffraction (XRD) apparatus, for example, in the analysis of the out-of-plane method of the CAAC-OS film having crystals of InGaZnO4, the diffraction angle (2θ) has a peak near 31°.

[0106] It can be understood from cross-sectional TEM observation and planar TEM observation that the crystal part of the CAAC-OS film has orientation.

[0107] When structural analysis is performed on the CAAC-OS film using an X-ray diffraction (XRD) apparatus, for example, in the analysis of the out-of-plane method of the CAAC-OS film having crystals of InGaZnO4, the diffraction angle (2θ) has a peak near 31°. may appear. This peak is attributed to the (009) plane of the InGaZnO4 crystal From this, it can be confirmed that the crystal of the CAAC-OS film has c-axis orientation, and the c-axis is oriented in a direction approximately perpendicular to the surface to be formed or the upper surface

[0108] On the other hand, in the analysis by the in-plane method in which X-rays are incident on the CAAC-OS film from a direction approximately perpendicular to the c-axis, a peak may appear around 2θ = 56°. This peak is attributed to the (110) plane of the InGaZnO4 crystal. In the case of a single crystal oxide semiconductor film of InGaZnO4, when the analysis (φ scan) is performed while rotating the sample with the normal vector of the sample surface as the axis (φ axis) with 2θ fixed around 56°, six peaks attributed to crystal planes equivalent to the (110) plane are observed. In contrast, in the case of the CAAC-OS film, no distinct peak appears even when φ scan is performed with 2θ fixed around 56°

[0109] From the above, in the CAAC-OS film, the orientations of the a-axis and b-axis are irregular between different crystal parts, but it has c-axis orientation, and the c-axis is oriented in a direction parallel to the normal vector of the surface to be formed or the upper surface Therefore, each layer of the metal atoms arranged in a layered manner confirmed by the cross-sectional TEM observation described above is a plane parallel to the ab plane of the crystal

[0110] Note that the crystal parts are formed when the CAAC-OS film is formed or when crystallization treatment such as heat treatment is performed. As described above, the c-axis of the crystal is oriented in a direction parallel to the normal vector of the surface to be formed or the upper surface of the CAAC-OS film. Therefore, for example, when the shape of the CAAC-OS film is changed by etching or the like, the c-axis of the crystal is the surface to be formed of the CAAC-OS film ​​​​​​​​​​It may not be parallel to the normal vector of the surface or the upper surface.

[0111] Also, the crystallinity in the CAAC-OS film may not be uniform. For example, when the crystal part of the CAAC-OS film is formed by crystal growth from near the upper surface of the CAAC-OS film, the region near the upper surface may have a higher crystallinity than the region near the surface to be formed. Also, when impurities are added to the CAAC-OS film, the crystallinity of the region where the impurities are added changes, and regions with different crystallinities may be formed partially.

[0112] In addition, in the out-of-plane analysis of the CAAC-OS film having InGaZnO4 crystals, in addition to the peak with 2θ near 31°, a peak may also appear at 2θ near 36°. The peak with 2θ near 36° indicates that a part of the CAAC-OS film contains crystals without c-axis orientation. The CAAC-OS film preferably shows a peak at 2θ near 31° and does not show a peak at 2θ near 36°.

[0113] A transistor using a CAAC-OS film has small fluctuations in electrical characteristics due to irradiation with visible light or ultraviolet light. Therefore, the transistor has high reliability.

[0114] In addition, the oxide semiconductor film may be, for example, a laminated film having two or more of an amorphous oxide semiconductor film, a microcrystalline oxide semiconductor film, and a C AAC-OS film.

[0115] Also, in order to form a CAAC-OS film, it is preferable to apply the following conditions.

[0116] By reducing the incorporation of impurities during film formation, it is possible to suppress the breakdown of the crystal state due to impurities. It is possible. For example, the impurity concentration (such as hydrogen, water, carbon dioxide, and nitrogen) present in the processing chamber may be reduced. Also, the impurity concentration in the film-forming gas may be reduced. Specifically, a film-forming gas with a dew point of -80°C or lower, preferably -100°C or lower, is used.

[0117] Also, by increasing the substrate heating temperature during film formation, migration of sputtering particles occurs after reaching the substrate. Specifically, film formation is performed with the substrate heating temperature set at 100°C or higher and 740°C or lower, preferably 200°C or higher and 500°C or lower. By increasing the substrate heating temperature during film formation, when flat or pellet-shaped sputtering particles reach the substrate, migration occurs on the substrate, and the flat surface of the sputtering particles adheres to the substrate.

[0118] Also, it is preferable to reduce plasma damage during film formation by increasing the oxygen ratio in the film-forming gas and optimizing the power. The oxygen ratio in the film-forming gas is 30% by volume or higher, preferably 100 % by volume.

[0119] As an example of the target, an In-Ga-Zn-based oxide target is shown below.

[0120] InO X powder, GaO Y powder, and ZnO Z powder are mixed at a predetermined molar ratio, and after pressure treatment and then heat-treated at a temperature of 1000°C or higher and 1500°C or lower to obtain a polycrystalline In-G a-Zn-based oxide target. Here, X, Y, and Z are arbitrary positive numbers. Here, the predetermined molar ratio is, for example, InO X powder, GaO Y powder, and ZnO Z powder being 2:2 ​: 1, 8:4:3, 3:1:1, 1:1:1, 4:2:3 or 3:1:2. Note that , the type of powder and the molar ratio of its mixture can be appropriately changed according to the target to be produced. That's all.

[0121] Since the alkali metal is not an element constituting the oxide semiconductor, it is an impurity. Similarly, alkaline earth metals also become impurities when they are not elements constituting the oxide semiconductor. In particular, among the alkali metals, when the insulating film in contact with the oxide semiconductor film is an oxide, Na diffuses into the insulating film to form Na + . Also, in the oxide semiconductor film, Na breaks or interrupts the bond between the metal and oxygen that constitutes the oxide semiconductor. As a result, for example, abnormal ionization occurs due to the shift of the threshold voltage in the negative direction, and the mobility decreases, etc., resulting in deterioration of the electrical characteristics of the transistor, and in addition, variations in characteristics also occur. . Specifically, the measured value of the Na concentration by secondary ion mass spectrometry is 5×10 16 / cm 3 or less, preferably 1×10 / cm 16 or less, more preferably 1×10 3 / cm 15 or less. Similarly, the measured value of the Li concentration is 5×10 3 / cm or less, preferably 1× 15 / cm 3 or less. Similarly, the measured value of the K concentration is 5×10 10 15 / cm 3 or less. Similarly, the measured value of the K concentration is 5×10 15 / cm 3 or less, preferably 1×10 15 / cm 3 or less.

[0122] In addition, when a metal oxide containing indium is used, silicon or carbon having a bond energy with oxygen greater than that of indium may break the bond between indium and oxygen to form oxygen vacancies. Therefore, if silicon or carbon is mixed in the oxide semiconductor film, similar to the case of alkali metals or alkaline earth metals, the electrical characteristics of the transistor are likely to deteriorate. Thus, it is desirable that the concentrations of silicon and carbon in the oxide semiconductor film are low. Specifically, the measured value of the C concentration or the measured value of the Si concentration by secondary ion mass spectrometry is preferably 1×10 18 / cm 3 or less. With the above configuration, deterioration of the electrical characteristics of the transistor can be prevented, and the reliability of the semiconductor device can be improved.

[0123] In addition, depending on the conductive material used for the source electrode and the drain electrode, the metal in the source electrode and the drain electrode may extract oxygen from the oxide semiconductor film. In this case, in the oxide semiconductor film, the regions in contact with the source electrode and the drain electrode are more n-type due to the formation of oxygen vacancies.

[0124] The n-type regions function as source regions or drain regions, so the contact resistance between the oxide semiconductor film and the source electrode and the drain electrode can be reduced. Therefore, by forming the n-type regions, the mobility and on-current of the transistor can be increased, and thereby, high-speed operation of a switch circuit using the transistor can be realized.

[0125] Note that the extraction of oxygen by the metal in the source electrode and the drain electrode is related to the source electrode and ​​​This can occur when forming the drain electrode by a sputtering method or the like, and can also occur by the heat treatment performed after forming the source electrode and the drain electrode.

[0126] Further, the region to be n-type is more easily formed by using a conductive material that easily binds to oxygen for the source electrode and the drain electrode. Examples of the conductive material include Al, Cr, Cu, Ta, Ti, Mo, W, and the like.

[0127] Further, the oxide semiconductor film is not necessarily composed of a single metal oxide film, and may be composed of a plurality of stacked metal oxide films. For example, in the case of a semiconductor film in which the first to third metal oxide films are stacked in order, the first metal oxide film and the third metal oxide film contain at least one of the metal elements constituting the second metal oxide film in their components, and the energy at the lower end of the conduction band is 0.05 eV or more, 0.07 eV or more, 0 .1 eV or more or 0.15 eV or more, and 2 eV or less, 1 eV or less, 0.5 eV or less or 0.4 eV or less, and is an oxide film close to the vacuum level. Further, it is preferable that the second metal oxide film contains at least indium because the carrier mobility increases. When the transistor has the semiconductor film having the above configuration, when a voltage is applied to the gate electrode,

[0128] and an electric field is applied to the semiconductor film, a channel region is formed in the second metal oxide film having a small energy at the lower end of the conduction band among the semiconductor films. That is, due to the provision of the third metal oxide film between the second metal oxide film and the gate insulating film, a channel region can be formed in the second metal oxide film separated from the gate insulating film.

[0129] In addition, since the third metal oxide film contains at least one of the metal elements constituting the second metal oxide film, interface scattering is less likely to occur at the interface between the second metal oxide film and the third metal oxide film. Therefore, carrier movement is less likely to be inhibited at the interface, and the field-effect mobility of the transistor is increased. When interface levels are formed at the interface between the second metal oxide film and the first metal oxide film, channel regions are also formed in the region near the interface, causing fluctuations in the threshold voltage of the transistor. However, since the first metal oxide film contains at least one of the metal elements constituting the second metal oxide film, interface levels are less likely to be formed at the interface between the second metal oxide film and the first metal oxide film. Thus, with the above configuration, variations in electrical characteristics such as the threshold voltage of the transistor can be reduced. Moreover, it is desirable to stack a plurality of oxide semiconductor films so that impurities do not form interface levels that inhibit the flow of carriers at the interfaces of the respective films. If impurities are present between the stacked metal oxide films, the continuity of the energy at the lower end of the conduction band between the metal oxide films is lost, and carriers are trapped or disappear due to recombination in the vicinity of the interface. By reducing the impurities between the films, a continuous junction (specifically, a U-shaped well structure in which the energy at the lower end of the conduction band changes continuously between the films) is more likely to be formed than simply stacking a plurality of metal oxide films having at least one common metal as the main component.

[0130] When interface levels are formed at the interface between the second metal oxide film and the first metal oxide film, channel regions are also formed in the region near the interface, causing fluctuations in the threshold voltage of the transistor. However, since the first metal oxide film contains at least one of the metal elements constituting the second metal oxide film, interface levels are less likely to be formed at the interface between the second metal oxide film and the first metal oxide film. Thus, with the above configuration, variations in electrical characteristics such as the threshold voltage of the transistor can be reduced. Moreover, it is desirable to stack a plurality of oxide semiconductor films so that impurities do not form interface levels that inhibit the flow of carriers at the interfaces of the respective films. If impurities are present between the stacked metal oxide films, the continuity of the energy at the lower end of the conduction band between the metal oxide films is lost, and carriers are trapped or disappear due to recombination in the vicinity of the interface. By reducing the impurities between the films, a continuous junction (specifically, a U-shaped well structure in which the energy at the lower end of the conduction band changes continuously between the films) is more likely to be formed than simply stacking a plurality of metal oxide films having at least one common metal as the main component.

[0131] In addition, when impurities are present between the metal oxide films, interface levels that inhibit the flow of carriers are not formed at the interfaces of the respective films. If impurities are present between the stacked metal oxide films, the continuity of the energy at the lower end of the conduction band between the metal oxide films is lost, and carriers are trapped or disappear due to recombination in the vicinity of the interface. By reducing the impurities between the films, a continuous junction (specifically, a U-shaped well structure in which the energy at the lower end of the conduction band changes continuously between the films) is more likely to be formed than simply stacking a plurality of metal oxide films having at least one common metal as the main component. When interface levels are formed at the interface between the second metal oxide film and the first metal oxide film, channel regions are also formed in the region near the interface, causing fluctuations in the threshold voltage of the transistor. However, since the first metal oxide film contains at least one of the metal elements constituting the second metal oxide film, interface levels are less likely to be formed at the interface between the second metal oxide film and the first metal oxide film. Thus, with the above configuration, variations in electrical characteristics such as the threshold voltage of the transistor can be reduced. Moreover, it is desirable to stack a plurality of oxide semiconductor films so that impurities do not form interface levels that inhibit the flow of carriers at the interfaces of the respective films. If impurities are present between the stacked metal oxide films, the continuity of the energy at the lower end of the conduction band between the metal oxide films is lost, and carriers are trapped or disappear due to recombination in the vicinity of the interface.

[0132] ​ To form a continuous junction, each film needs to be continuously laminated using a multi-chamber film forming apparatus (sputtering apparatus) equipped with a load lock chamber without exposing it to the atmosphere. Each chamber in the sputtering apparatus is evacuated to a high vacuum (to about 5×10 Pa to 1×10 Pa) using an adsorption type vacuum exhaust pump such as a cryopump to remove impurities such as water that would become impurities for the oxide semiconductor as much as possible. Alternatively, it is preferable to combine a turbo molecular pump and a cold trap to prevent gas from flowing back into the chamber from the exhaust system. -7 Pa to 1×10 -4 Pa). In addition to evacuating each chamber to a high vacuum, it is also important to purify the gas used for sputtering to obtain a high-purity genuine oxide semiconductor. The dew point of the oxygen gas or argon gas used as the above gas is set to -40°C or lower, preferably -80°C or lower, more preferably -100°C or lower. By purifying the gas used, it is possible to prevent moisture and the like from being incorporated into the oxide semiconductor film as much as possible. Specifically, when the second metal oxide film is an In

[0133] -M-Zn oxide (M is Ga, Y, Zr, La, Ce, or Nd), in the target used to form the second metal oxide film, if the atomic ratio of the metal elements is In:M :Zn = x1:y1:z1, then x1 / y1 is 1 / 3 or more and 6 or less, further 1 or more and 6 or less, and z1 / y1 is 1 / 3 or more and 6 or less, further 1 or more and 6 or less, which is preferred. Note that by setting z1 / y1 to 1 or more and 6 or less, a C AAC-OS film is likely to be formed as the second metal oxide film. As a representative example of the atomic ratio of the metal elements in the target 、 x1 / y1 is 1 / 3 or more and 6 or less, further 1 or more and 6 or less, and z1 / y1 is 1 / 3 or more and 6 or less, further 1 or more and 6 or less. Preferably. In addition, by setting z1 / y1 to 1 or more and 6 or less, a C AAC-OS film is likely to be formed as the second metal oxide film. As a representative example of the atomic ratio of the metal elements in the target There are cases such as In:M:Zn = 1:1:1 and In:M:Zn = 3:1:2.

[0134] Specifically, when the first metal oxide film and the third metal oxide film are In-M-Zn oxides (M is Ga, Y, Zr, La, Ce, or Nd), in the target used to form the first metal oxide film and the third metal oxide film, if the atomic ratio of the metal elements is In:M:Z n = x2:y2:z2, then 、 x2 / y2 < x1 / y1, and z2 / y2 is preferably 1 / 3 or more and 6 or less, more preferably 1 or more and 6 or less. By setting z2 / y2 to 1 or more and 6 or less, it becomes easier to form a CAAC-OS film as the first metal oxide film and the third metal oxide film. Representative examples of the atomic ratio of the metal elements in the target include In:M: Zn = 1:3:2, In:M:Zn = 1:3:4, In:M:Zn = 1:3:6, In: M:Zn = 1:3:8, etc. M:Zn = 1:3:8, etc.

[0135] Note that the thickness of the first metal oxide film and the third metal oxide film is 3 nm or more and 100 nm or less, preferably 3 nm or more and 50 nm or less. Also, the thickness of the second metal oxide film is 3 nm or more and 200 nm or less, preferably 3 nm or more and 100 nm or less, and more preferably 3 nm or more and 50 nm or less.

[0136] In the three-layer semiconductor film, the first metal oxide film to the third metal oxide film can take both amorphous and crystalline forms. However, since the second metal oxide film in which the channel region is formed being crystalline can impart stable electrical characteristics to the transistor, it is preferable that the second metal oxide film be crystalline. it is possible to, so the second metal oxide film is preferably crystalline.

[0137] Note that the channel formation region refers to the region in the semiconductor film of the transistor that overlaps with the gate electrode and is sandwiched between the source electrode and the drain electrode. Also, the channel region refers to the region in the channel formation region where current mainly flows.

[0138] For example, when using an In-Ga-Zn oxide film formed by sputtering as the first metal oxide film and the third metal oxide film, for forming the first metal oxide film and the third metal oxide film, a target of In-Ga-Zn oxide (In:Ga:Zn = 1:3:2 [atomic ratio]) can be used. The film formation conditions are, for example, using argon gas at 30 sccm and oxygen gas at 15 sccm as the film formation gas, setting the pressure to 0.4 Pa, the substrate temperature to 200 °C, and the DC power to 0.5 kW.

[0139] Also, when the second metal oxide film is a CAAC-OS film, for forming the second metal oxide film, it is preferable to use a target of In-Ga-Zn oxide (In:Ga:Zn = 1:1:1 [atomic ratio]) and containing polycrystalline In-Ga-Zn oxide. The film formation conditions are, for example, using argon gas at 30 sccm and oxygen gas at 15 sccm as the film formation gas, using them, setting the pressure to 0.4 Pa, the temperature of the substrate to 300 °C, and the DC power to 0.5 kW.

[0140] Note that the transistor may have a structure in which the end of the semiconductor film is inclined, or may have a structure in which the end of the semi conductor film is rounded.

[0141] Also, when using a semiconductor film having a plurality of stacked metal oxide films for the transistor, ​​However, the regions in contact with the source electrode and the drain electrode may be n-type. The above configuration can increase the mobility and on-current of the transistor, and achieve high-speed operation of a semiconductor device using the transistor. Furthermore, when a semiconductor film having a plurality of stacked metal oxide films is used for the transistor, the region to be n-type reaches the second metal oxide film that becomes the channel region, which is more preferable for increasing the mobility and on-current of the transistor and realizing further high-speed operation of the semiconductor device.

[0142] <Examples of Electronic Devices> The PLD or semiconductor device according to one aspect of the present invention can be used in a display device, a personal computer , an image playback device equipped with a recording medium (typically a device having a display capable of playing a recording medium such as a DVD: Digital Versatile Disc and displaying its image ). In addition, as electronic devices in which the PLD or semiconductor device according to one aspect of the present invention can be used, mobile phones, game machines including portable types, portable information terminals, electronic books, video cameras, cameras such as digital still cameras, goggle-type displays (head mounted displays), navigation systems, audio playback devices (car audio , digital audio players, etc.), copiers, facsimiles, printers, printer multifunction machines, automated teller machines (ATMs), vending machines, etc. can be mentioned. Specific examples of these electronic devices are shown in FIG. 11.

[0143] FIG. 11(A) shows a portable game machine, including a housing 5001, a housing 5002, a display unit 5003 , a display unit 5004, a microphone 5005, a speaker 5006, operation keys 5007, and an s It has a tilas 5008 or the like. The portable game machine shown in Fig. 11(A) has two display parts 5003 and a display part 5004, but the number of display parts of the portable game machine is , not limited to this.

[0144] Fig. 11(B) is a portable information terminal and has a first housing 5601, a second housing 5602, a first display part 5603, a second display part 5604, a connection part 5605, operation keys 5606, etc. The first display part 5603 is provided on the first housing 5601, and the second display part 5604 is provided on the second housing 5 602. The first housing 5601 and the second housing 5602 are connected by a connection part 5 605, and the angle between the first housing 5601 and the second housing 5602 can be changed by the connection part 5605. The video on the first display part 5603 may be switched according to the angle between the first housing 5601 and the second housing 5602 at the connection part 560 5. Further, a display device with a function as a position input device may be used for at least one of the first display part 5603 and the second display part 5604. Note that the function as a position input device can be added by providing a touch panel on the display device. Alternatively, the function as a position input device can also be added by providing a photoelectric conversion element, also called a photosensor, in the pixel part of the display device.

[0145] Fig. 11(C) is a notebook personal computer and has a housing 5401, a display part 540 2, a keyboard 5403, a pointing device 5404, etc.

[0146] Fig. 11(D) is an electric refrigerator-freezer and has a housing 5301, a refrigerator door 5302, a freezer door 5303, etc.

[0147] FIG. 11(E) is a video camera, which includes a first housing 5801, a second housing 5802, a display unit 5 803, operation keys 5804, a lens 5805, a connection part 5806, etc. The operation keys 58 04 and the lens 5805 are provided on the first housing 5801, and the display unit 5803 is provided on the second housing 5802. The first housing 5801 and the second housing 5802 are connected by a connection part 5806, and the angle between the first housing 5801 and the second housing 5802 can be changed by the connection part 5806. The video on the display unit 5803 can be switched according to the angle between the first housing 580 1 and the second housing 5802 at the connection part 5806.

[0148] FIG. 11(F) is an ordinary automobile, which includes a vehicle body 5101, wheels 5102, a dashboard 51 03, lights 5104, etc.

Explanation of Reference Numerals

[0149] 10 Semiconductor device 10-1 Semiconductor device 10-2 Semiconductor device 10a PLD 10b Semiconductor device 11 Switch 11t Transistor 12 Switch 12t Transistor 13 Transistor 14 Transistor 15 Capacitive element 16a Terminal 16b Terminal 17-1 Transistor 17-2 Transistor 18a Logic block 18b Logic block 20 Switch 21 Wiring​ 22 Latch 23 Inverter 24 Transistor 25 Wiring 30 Inverter 31 Inverter 40 Logic Block 41 LUT 42 Flip-Flop 43 Memory Device 43a Memory Device 43b Memory Device 44 Input Terminal 45 Output Terminal 46 Output Terminal 47 AND Circuit 48 Multiplexer 50 PLD 51 Wiring Group 52 Switch Circuit 53 Wiring Resource 54 Terminal 55 Wiring 56 Wiring 57 Transistor 58 Transistor 59 Transistor 60 Transistor 61 Transistor 62 Transistor 70 I / O Element 71 PLL 72 RAM 73 Multiplier 400 Semiconductor Substrate 401 Element Isolation Region 402 p-Well 404 Impurity Region 405 Impurity Region 406 Gate Electrode 407 Gate Insulating Film 411 Insulating Film 412 Conductive Film 413 Conductive Film 418 Conductive Film 419 Conductive Film 420 Insulating Film 421 Conductive Film 430 Semiconductor film 431 Gate insulating film 432 Conductive film 433 Conductive film 434 Conductive film 441 Insulating film 442 Insulating film 443 Conductive film 5001 Housing 5002 Housing 5003 Display unit 5004 Display unit 5005 Microphone 5006 Speaker 5007 Operation key 5008 Stylus 5101 Vehicle body 5102 Wheel 5103 Dashboard 5104 Light 5301 Housing 5302 Door for refrigerator compartment 5303 Door for freezer compartment 5401 Housing 5402 Display unit 5403 Keyboard 5404 Pointing device 5601 Housing 5602 Housing 5603 Display unit 5604 Display unit 5605 Connection part 5606 Operation key 5801 Housing 5802 Housing 5803 Display unit 5804 Operation key 5805 Lens 5806 Connection part

Claims

1. A semiconductor device having a plurality of circuits, each of the plurality of circuits includes a first transistor to a fourth transistor and a capacitor; one of the source and the drain of the first transistor is always electrically connected to one of the source and the drain of the second transistor; a gate of the first transistor is always electrically connected to a gate of the second transistor; one of the source and the drain of the third transistor is always electrically connected to the gate of the third transistor; the other of the source and the drain of the third transistor is always electrically connected to the gate of the fourth transistor; one electrode of the capacitance element is always electrically connected to the gate of the third transistor; a high-level potential or a low-level potential is input to one of a source or a drain of the first transistor and one of a source or a drain of the second transistor; a signal is input to the gate of the first transistor and the gate of the second transistor; when one of the source or drain of the first transistor and the gate of the third transistor are electrically connected via at least a channel formation region of the first transistor, and one of the source or drain of the second transistor and the gate of the fourth transistor are electrically connected via at least a channel formation region of the second transistor, either the high-level potential or the low-level potential is input to the gate of the third transistor via at least a channel formation region of the first transistor, and the one potential is input to the gate of the fourth transistor via at least a channel formation region of the second transistor; Semiconductor device.

2. A semiconductor device having a plurality of circuits, each of the plurality of circuits includes a first transistor to a fourth transistor and a capacitor; one of the source and the drain of the first transistor is always electrically connected to one of the source and the drain of the second transistor; a gate of the first transistor is always electrically connected to a gate of the second transistor; one of the source and the drain of the third transistor is always electrically connected to the gate of the third transistor; the other of the source and the drain of the third transistor is always electrically connected to the gate of the fourth transistor; one electrode of the capacitance element is always electrically connected to the gate of the third transistor; a high-level potential or a low-level potential is input to one of a source or a drain of the first transistor and one of a source or a drain of the second transistor; a signal is input to the gate of the first transistor and the gate of the second transistor; when one of the source or drain of the first transistor and the gate of the third transistor are electrically connected via at least a channel formation region of the first transistor, and one of the source or drain of the second transistor and the gate of the fourth transistor are electrically connected via at least a channel formation region of the second transistor, either the high-level potential or the low-level potential is input to the gate of the third transistor via at least a channel formation region of the first transistor, and the one potential is input to the gate of the fourth transistor via at least a channel formation region of the second transistor; a period in which the first transistor is in a non-conductive state, the second transistor is in a non-conductive state, the gate of the third transistor is in a floating state, and the gate of the fourth transistor is in a floating state; Semiconductor device.

3. A semiconductor device having a plurality of circuits, each of the plurality of circuits includes a first transistor to a fourth transistor and a capacitor; one of the source and the drain of the first transistor is always electrically connected to one of the source and the drain of the second transistor; a gate of the first transistor is always electrically connected to a gate of the second transistor; one of the source and the drain of the third transistor is always electrically connected to the gate of the third transistor; the other of the source and the drain of the third transistor is always electrically connected to the gate of the fourth transistor; one electrode of the capacitance element is always electrically connected to the gate of the third transistor; a high-level potential or a low-level potential is input to one of a source or a drain of the first transistor and one of a source or a drain of the second transistor; a signal is input to the gate of the first transistor and the gate of the second transistor; when one of the source or drain of the first transistor and the gate of the third transistor are electrically connected via at least a channel formation region of the first transistor, and one of the source or drain of the second transistor and the gate of the fourth transistor are electrically connected via at least a channel formation region of the second transistor, either the high-level potential or the low-level potential is input to the gate of the third transistor via at least a channel formation region of the first transistor, and the one potential is input to the gate of the fourth transistor via at least a channel formation region of the second transistor; one of a source or a drain of the fourth transistor included in a first circuit of the plurality of circuits is always electrically connected to one of a source or a drain of the fourth transistor included in a second circuit of the plurality of circuits; Semiconductor device.

4. A semiconductor device having a plurality of circuits, each of the plurality of circuits includes a first transistor to a fourth transistor and a capacitor; one of the source and the drain of the first transistor is always electrically connected to one of the source and the drain of the second transistor; a gate of the first transistor is always electrically connected to a gate of the second transistor; one of the source and the drain of the third transistor is always electrically connected to the gate of the third transistor; the other of the source and the drain of the third transistor is always electrically connected to the gate of the fourth transistor; one electrode of the capacitance element is always electrically connected to the gate of the third transistor; a high-level potential or a low-level potential is input to one of a source or a drain of the first transistor and one of a source or a drain of the second transistor; a signal is input to the gate of the first transistor and the gate of the second transistor; when one of the source or drain of the first transistor and the gate of the third transistor are electrically connected via at least a channel formation region of the first transistor, and one of the source or drain of the second transistor and the gate of the fourth transistor are electrically connected via at least a channel formation region of the second transistor, either the high-level potential or the low-level potential is input to the gate of the third transistor via at least a channel formation region of the first transistor, and the one potential is input to the gate of the fourth transistor via at least a channel formation region of the second transistor; a period in which the first transistor is in a non-conductive state, the second transistor is in a non-conductive state, a gate of the third transistor is in a floating state, and a gate of the fourth transistor is in a floating state; one of a source or a drain of the fourth transistor included in a first circuit of the plurality of circuits is always electrically connected to one of a source or a drain of the fourth transistor included in a second circuit of the plurality of circuits; Semiconductor device.

5. In any one of claims 1 to 4, In each of the plurality of circuits, all transistors have the same polarity. Semiconductor device.

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