Circuit adjustment method and device, electronic equipment, storage medium and circuit

Abstract

The present disclosure provides a circuit adjustment method and device, electronic equipment, storage medium and circuit. The method comprises: determining a first data path circuit in an integrated circuit; wherein there is a target path between different registers in the first data path circuit; based on the device delay of electronic components included in the target path in the first data path circuit, inserting a selected buffer in the first data path circuit to obtain a second data path circuit, wherein the delays of each target path in the second data path circuit are consistent; performing a component adjustment operation on the second data path circuit to obtain an adjusted third data path circuit; wherein the first clock period corresponding to the third data path circuit is less than the second clock period corresponding to the second data path circuit, and the delay of different input signals reaching the same logic device in the third data path circuit differs by an integer multiple of the first clock period.

Description

TECHNICAL FIELD

[0001] The present disclosure relates to the technical field of integrated circuits, and in particular, to a circuit adjustment method and device, electronic equipment, storage medium and circuit. BACKGROUND

[0002] With the progress of science and technology, integrated circuits are rapidly developing. An integrated circuit refers to a circuit with a specific function that integrates a certain number of commonly used electronic components, such as resistors, capacitors, transistors, and the connections between these components, through semiconductor processes. A chip is a general term for semiconductor component products and is the carrier of an integrated circuit (IC) that is divided from a wafer.

[0003] As the integration of chips is becoming higher and higher, the computing power is also becoming stronger, making the low-power design of chips more and more important. Therefore, it is particularly important to propose a circuit adjustment method for reducing the power consumption of a chip. SUMMARY

[0004] Therefore, the present disclosure at least provides a circuit adjustment method, device, electronic equipment, storage medium and circuit.

[0005] In a first aspect, the present disclosure provides a circuit adjustment method, comprising:

[0006] determining a first data path circuit in an integrated circuit; wherein there is a target path between different registers in the first data path circuit;

[0007] based on the device delay of the electronic components included in the target path in the first data path circuit, inserting a selected buffer in the first data path circuit to obtain a second data path circuit, wherein the delays of each target path in the second data path circuit are consistent;

[0008] performing a component adjustment operation on the second data path circuit to obtain an adjusted third data path circuit; wherein the first clock period corresponding to the third data path circuit is less than the second clock period corresponding to the second data path circuit, and the delay of different input signals reaching the same logic device in the third data path circuit differs by an integer multiple of the first clock period.

[0009] In the above method, by inserting a selected buffer in the first data path circuit based on the device delay of the electronic components included in the target path in the first data path circuit, a second data path circuit is obtained, so that the delays of each target path in the second data path circuit are consistent, avoiding the generation of glitches in the second data path circuit, i.e. avoiding the generation of glitch power consumption, and reducing the power consumption of the data path circuit.

[0010] Further, the second data path circuit is subjected to component adjustment operation to obtain an adjusted third data path circuit, wherein the delay of different input signals reaching the same logic device in the third data path circuit differs by an integer multiple of the first clock period, which can avoid glitch power consumption in the third data path circuit and reduce the static power consumption of the data path circuit, on the basis of guaranteeing the low power consumption requirement of the data path circuit, the clock period of the third data path circuit is reduced, the clock frequency of the third data path circuit is improved, and thus the operation speed and operation capacity of the integrated circuit are guaranteed.

[0011] In a possible implementation, the second data path circuit is obtained by inserting selected buffers in the first data path circuit based on the device delay of the electronic components included in the target path in the first data path circuit, and the second data path circuit comprises:

[0012] The path delay corresponding to the target path in the first data path circuit is determined based on the device delay of the electronic components included in the target path in the first data path circuit.

[0013] The maximum delay in the path delays corresponding to each target path in the first data path circuit is taken as a target delay.

[0014] The second data path circuit is obtained by inserting selected buffers in the first data path circuit based on the target delay and the intermediate delay between the registers and the logic devices included in the target path in the first data path circuit.

[0015] Here, the second data path circuit can be obtained by inserting selected buffers in the first data path circuit based on the target delay and the intermediate delay between the registers and the logic devices included in the target path in the first data path circuit, so that the delays of each target path in the second data path circuit are consistent, and glitch power consumption of the data path circuit is avoided.

[0016] In a possible implementation, in the case that there is a first buffer between the input port of the first data path circuit and the first register, and there is a second buffer between the second register of the first data path circuit and the output port, after the second data path circuit is obtained, the method further comprises:

[0017] The maximum delay in the path delays corresponding to each target path in the first data path circuit is taken as a target delay.

[0018] selecting a first to-be-replaced component device and a second to-be-replaced component device whose device delays match the target delay, and replacing the first buffer in the second data path circuit with the first to-be-replaced component device and the second buffer with the second to-be-replaced component device to obtain an intermediate data path circuit;

[0019] The component device adjustment operation on the second data path circuit includes:

[0020] The component device adjustment operation on the intermediate data path circuit.

[0021] Here, the intermediate data path circuit is obtained by replacing the first buffer and the second buffer with component devices, so that the intermediate data path circuit meets the circuit design requirements.

[0022] In a possible implementation, the component device adjustment operation on the second data path circuit includes:

[0023] The component device adjustment operation on the second data path circuit includes at least one of component device replacement, component device deletion, and component device addition, to obtain an adjusted third data path circuit.

[0024] Here, the component device adjustment operation on the second data path circuit includes at least one of component device replacement, component device deletion, and component device addition, to obtain an adjusted third data path circuit, and the types of the component device adjustment operation are various, so that the adjusted third data path circuit can be obtained flexibly.

[0025] In a possible implementation, in a case where a third buffer exists between a third register and an output port of the third data path circuit, after the third data path circuit is obtained, the method further includes:

[0026] selecting a third to-be-replaced component device whose device delay matches the second clock cycle, and replacing the third buffer with the third to-be-replaced component device to obtain a fourth data path circuit.

[0027] In a possible implementation, before the first data path circuit in the integrated circuit is determined, the method further includes:

[0028] integerizing the initial device delay of each electronic component device in the integrated circuit by using an integer linear programming method, to obtain a device delay corresponding to an integer multiple target unit of each electronic component device.

[0029] Here, before determining the first data path circuit in the integrated circuit, the initial device delay of each electronic component in the integrated circuit is integerized by using the integer linear programming method, and the device delay corresponding to the integer multiple target unit of each electronic component is obtained, that is, the device delay corresponding to each electronic component is an integer, so that the subsequent path delay of the target path can be determined based on the device delay of each electronic component, and then the data path circuit can be adjusted based on the path delay to more accurately adjust the data path circuit to ensure that the adjusted data path circuit can meet the low power consumption requirement.

[0030] The effects of the following devices, electronic equipment, etc. are described in the above method, which will not be repeated here.

[0031] In a second aspect, the present disclosure provides a circuit adjustment device, comprising:

[0032] A determination module is configured to determine a first data path circuit in an integrated circuit; wherein there is a target path between different registers in the first data path circuit;

[0033] A first adjustment module is configured to insert a selected buffer in the first data path circuit based on the device delay of the electronic component included in the target path in the first data path circuit, to obtain a second data path circuit, wherein the delay of each target path in the second data path circuit is consistent;

[0034] A second adjustment module is configured to perform a component adjustment operation on the second data path circuit to obtain an adjusted third data path circuit; wherein the first clock period corresponding to the third data path circuit is less than the second clock period corresponding to the second data path circuit, and the delay of different input signals to the same logic device in the third data path circuit is different by an integer multiple of the first clock period.

[0035] In a possible implementation, the first adjustment module, when inserting a selected buffer in the first data path circuit based on the device delay of the electronic component included in the target path in the first data path circuit to obtain a second data path circuit, is configured to:

[0036] Determine the path delay corresponding to the target path in the first data path circuit based on the device delay of the electronic component included in the target path in the first data path circuit;

[0037] Take the maximum delay in the path delay corresponding to each target path in the first data path circuit as the target delay;

[0038] inserting selected buffers in the first data path circuit based on the target delay and intermediate delays between registers and logic included in the target paths in the first data path circuit, to obtain a second data path circuit.

[0039] In a possible implementation, in the case that there is a first buffer between an input port of the first data path circuit and a first register, and a second buffer between a second register of the first data path circuit and an output port, after obtaining the second data path, the apparatus further includes a first replacing module configured to:

[0040] taking a maximum delay in the path delays corresponding to each of the target paths in the first data path circuit as the target delay;

[0041] selecting a first to-be-replaced component and a second to-be-replaced component whose delays match the target delay, and replacing the first buffer in the second data path with the first to-be-replaced component and replacing the second buffer with the second to-be-replaced component, to obtain an intermediate data path circuit;

[0042] The second adjusting module is configured to, when performing a component adjustment operation on the second data path circuit:

[0043] perform a component adjustment operation on the intermediate data path circuit.

[0044] In a possible implementation, the second adjusting module is configured to, when performing a component adjustment operation on the second data path circuit to obtain an adjusted third data path circuit:

[0045] perform at least one of the following component adjustment operations on the second data path circuit: component replacement, component deletion, and component addition, to obtain an adjusted third data path circuit.

[0046] In a possible implementation, in the case that there is a third buffer between a third register of the third data path circuit and an output port, after obtaining the third data path circuit, the apparatus further includes a second replacing module configured to:

[0047] select a third to-be-replaced component whose delay matches the second clock cycle, and replace the third buffer with the third to-be-replaced component, to obtain a fourth data path circuit.

[0048] In a possible implementation, before determining the first data path circuit in the integrated circuit, the apparatus further includes a processing module configured to:

[0049] An integer linear programming method is used to integerize the initial device delay of each electronic component in the integrated circuit, to obtain a device delay corresponding to an integer multiple of a target unit for each electronic component.

[0050] In a third aspect, the present disclosure provides a data path circuit, comprising at least one component of a logic device, a register, and a buffer.

[0051] The data path circuit is generated based on the circuit adjustment method of the first aspect or any of the embodiments.

[0052] In a fourth aspect, the present disclosure provides an electronic device, comprising a processor, a memory, and a bus, wherein the memory stores machine-readable instructions executable by the processor, and the processor communicates with the memory through the bus when the electronic device is running, and the machine-readable instructions are executed by the processor to perform the steps of the circuit adjustment method of the first aspect or any of the embodiments, or the data path circuit of the third aspect.

[0053] In a fifth aspect, the present disclosure provides a computer-readable storage medium, which stores a computer program, and the computer program is executed by a processor to perform the steps of the circuit adjustment method of the first aspect or any of the embodiments.

[0054] In order to make the above objectives, features and advantages of the present disclosure more apparent, the following will specifically describe preferred embodiments in conjunction with the accompanying drawings, and a detailed description is made as follows. BRIEF DESCRIPTION OF DRAWINGS

[0055] In order to more clearly illustrate the technical solutions of the embodiments of the present disclosure, the following will briefly introduce the drawings needed to be used in the embodiments, the drawings herein are incorporated into the description and form a part of the description, which show the embodiments consistent with the present disclosure, and are used to explain the technical solutions of the present disclosure together with the description. It should be understood that the following drawings only show some embodiments of the present disclosure, and therefore should not be considered as a limitation on the scope, and for those skilled in the art, other related drawings can also be obtained without creative labor.

[0056] Figure 1 A flowchart of a circuit adjustment method provided by an embodiment of the present disclosure is shown;

[0057] Figure 2a A schematic diagram of a first data path circuit provided by an embodiment of the present disclosure is shown;

[0058] Figure 2b A schematic diagram of a second data path circuit provided by an embodiment of the present disclosure is shown;

[0059] Figure 2c A schematic diagram of an intermediate data path circuit is shown.

[0060] Figure 2d A schematic diagram of a third data path circuit is shown.

[0061] Figure 2e A schematic diagram of a fourth data path circuit is shown.

[0062] Figure 3 A schematic diagram of a circuit adjustment device is shown.

[0063] Figure 4 A schematic diagram of an electronic device is shown. DETAILED DESCRIPTION

[0064] To make the objectives, technical solutions, and advantages of the embodiments of the present disclosure clearer, the following will be combined with the accompanying drawings for the embodiments of the present disclosure to make a clear and complete description of the technical solutions of the embodiments of the present disclosure. Obviously, the described embodiments are only part of the embodiments of the present disclosure, rather than all the embodiments. The components of the embodiments of the present disclosure described and shown in the accompanying drawings can be arranged and designed in various different configurations. Therefore, the following detailed description of the embodiments of the present disclosure provided in the accompanying drawings is not intended to limit the scope of the claimed present disclosure, but only represents selected embodiments of the present disclosure. Based on the embodiments of the present disclosure, all other embodiments obtained by those skilled in the art without creative work are within the scope of protection of the present disclosure.

[0065] With the increasing integration of chips and the increasing computing power, the low-power design of chips is also paid more and more attention. Among them, the power consumption of the chip is mainly divided into static power consumption and dynamic power consumption. Static power consumption refers to the leakage power consumption of the circuit of the chip when it is maintained in an inactive state, that is, the power consumption under no load condition; dynamic power consumption is mainly the power consumption generated when the switch flips in response to input changes and / or glitches. Glitch is a false flip experienced by a logic gate before reaching the steady state value of the cycle, which is caused by the delay difference of the input path of the logic gate. Glitch not only has the risk of causing chip function error, but also causes power loss.

[0066] In order to reduce the power consumption of the chip, the embodiments of the present disclosure provide a circuit adjustment method, device, electronic equipment, storage medium and circuit.

[0067] The above-mentioned defects are the results of the inventors after practice and careful study, and therefore, the discovery process of the above-mentioned problems and the solutions proposed by the present disclosure to solve the above-mentioned problems should be the contributions of the inventors to the present disclosure.

[0068] It should be noted that similar reference numbers and letters represent similar items in the following drawings, and therefore, once an item is defined in one drawing, it does not need to be further defined and explained in subsequent drawings.

[0069] In order to facilitate the understanding of the embodiments of the present disclosure, first, a circuit adjustment method disclosed by the embodiments of the present disclosure will be introduced in detail. The execution subject of the circuit adjustment method provided by the embodiments of the present disclosure can be a chip, a server, a terminal device, etc. For example, the terminal device can be a computer, a tablet, etc.

[0070] Referring to FIG. 1, Figure 1 FIG. 1 is a flowchart of a circuit adjustment method provided by the embodiments of the present disclosure, S101-S103, wherein:

[0071] S101, determining a first data path circuit in an integrated circuit; wherein there is a target path between different registers in the first data path circuit;

[0072] S102, based on the device delay of the electronic components included in the target path in the first data path circuit, inserting a selected buffer in the first data path circuit to obtain a second data path circuit, wherein the delays of each target path in the second data path circuit are consistent;

[0073] S103, performing a component adjustment operation on the second data path circuit to obtain an adjusted third data path circuit; wherein the first clock period corresponding to the third data path circuit is less than the second clock period corresponding to the second data path circuit, and the delay of different input signals to the same logic device in the third data path circuit differs by an integer multiple of the first clock period.

[0074] In the above method, by inserting a selected buffer in the first data path circuit based on the device delay of the electronic components included in the target path in the first data path circuit, a second data path circuit is obtained, so that the delays of each target path in the second data path circuit are consistent, avoiding the generation of glitches in the second data path circuit, i.e. avoiding the generation of glitch power consumption, and reducing the power consumption of the data path circuit.

[0075] Furthermore, component adjustments are performed on the second data path circuit to obtain the adjusted third data path circuit. In the third data path circuit, the delays of different input signals arriving at the same logic unit differ by an integer multiple of the first clock cycle. This avoids glitches and reduces the static power consumption of the data path circuit. While ensuring the low power consumption requirement of the data path circuit, the clock cycle of the third data path circuit is reduced, and the clock frequency of the third data path circuit is increased, thereby ensuring the computing speed and computing power of the integrated circuit.

[0076] The following provides a detailed explanation of S101 to S103.

[0077] Regarding S101:

[0078] The first data path circuit in an integrated circuit is determined, where the first data path circuit can be a specific data path circuit to be adjusted. For example, a data path circuit in the integrated circuit that exhibits glitches can be identified as the first data path circuit; and / or, a data path circuit in the integrated circuit with a large delay can be identified as the first data path circuit, etc. The path through which data is transmitted between functional components is called a data path. Functional components (devices) can be, for example, registers, logic units, etc., and the various functional components along the transmission path constitute the data path circuit. A data path circuit exhibiting glitches can be, for example, a circuit where the delay of input signals arriving at the same logic unit from different paths is inconsistent, causing glitches.

[0079] In this circuit, target paths exist between different registers in the first data path circuit, and the circuit structure of the first data path circuit can be selected according to the actual situation. See also Figure 2a The diagram shown is a schematic of a first data path circuit. Figure 2a It includes buffer A, buffer B, AND gate logic unit C, AND gate logic unit D, buffer E, register R1, register R2, and register R3; in Figure 2a There are three target paths. The first target path is: Register R1 > AND gate C > AND gate D > Register R3; the second target path is: Register R2 > Buffer B > AND gate C > AND gate D > Register R3; the third target path is: Register R2 > Buffer B > AND gate D > Register R3. Figure 2a The number corresponding to each electronic component represents the device delay of that electronic component.

[0080] In an alternative embodiment, before determining the first data path circuit in the integrated circuit, the method further comprises: using an integer linear programming method to integerize the initial device delay of each electronic component in the integrated circuit to obtain the device delay of each electronic component corresponding to an integer multiple of a target unit.

[0081] In practice, the initial device delay of each electronic component is related to the performance, material, etc. of the electronic component. The initial device delay of each electronic component can be determined in advance, and then the initial device delay of each electronic component is integerized using an integer linear programming method to obtain the device delay of each electronic component corresponding to an integer multiple of a target unit. In addition, the initial device delay of each candidate electronic component included in the component database can also be integerized to obtain the device delay of the candidate electronic component corresponding to an integer multiple of a target unit.

[0082] For example, the initial device delay of electronic component 1 is 0.01s (second), the initial device delay of electronic component 2 is 0.05s, and the initial device delay of electronic component 3 is 0.07s. After integerization, the device delay of electronic component 1 is 1 (indicating 1 target unit of device delay), the device delay of electronic component 2 is 5 (indicating 5 target units of device delay), and the device delay of electronic component 3 is 7 (indicating 7 target units of device delay), and each target unit is 0.01s.

[0083] It can be seen that Figure 2a The buffer A in the integrated circuit corresponds to 3 target units of device delay. The size of the target unit can be set according to actual conditions.

[0084] Here, before determining the first data path circuit in the integrated circuit, the initial device delay of each electronic component in the integrated circuit is integerized using an integer linear programming method to obtain the device delay of each electronic component corresponding to an integer multiple of a target unit, i.e. the device delay corresponding to each electronic component is an integer, so that the path delay of the target path can be determined more simply and quickly based on the device delay of each electronic component, and the data path circuit can be adjusted more accurately based on the path delay, to ensure that the adjusted data path circuit can meet the low power consumption requirement.

[0085] For S102:

[0086] When the delays of different input signals arriving at the same logic device are different, the logic device will generate glitches, resulting in glitch power consumption of the circuit. Therefore, a buffer can be inserted in the circuit to avoid the generation of glitches, thereby reducing the glitch power consumption of the circuit.

[0087] In an optional implementation, in S102, the step of inserting a selected buffer into the first data path circuit based on the device delay of the electronic components included in the target path of the first data path circuit to obtain a second data path circuit may include steps A1-A3, wherein:

[0088] Step A1: Based on the device delay of the electronic components included in the target path in the first data path circuit, determine the path delay corresponding to the target path in the first data path circuit.

[0089] Step A2: Take the maximum delay among the path delays corresponding to each target path in the first data path circuit as the target delay;

[0090] Step A3: Based on the target delay and the intermediate delay between the register and the logic device included in the target path of the first data path circuit, insert a selected buffer into the first data path circuit to obtain the second data path circuit.

[0091] In implementation, for each target path in the first data path circuit, the path delay of the target path can be determined based on the device delay of each electronic component included in the target path, thus obtaining the path delay corresponding to each target path in the first data path circuit. Furthermore, the maximum delay among the path delays corresponding to each target path in the first data path circuit can be determined, and this maximum delay is taken as the target delay.

[0092] The first data path circuit is Figure 2a When the data path circuit shown is used, it can be seen that... Figure 2a The path delay of the first target path is 6 target units, the path delay of the second target path is 7 target units, and the path delay of the third target path is 3 target units. The path delay of the second target path is taken as the target delay, i.e., the target delay is 7 target units.

[0093] Determine the intermediate delay between the register and the logic unit in the target path of the first data path circuit. For example, Figure 2a The intermediate delay between register R1 and AND gate C is 0, the intermediate delay between register R2 and AND gate C is 1, the intermediate delay between register R1 and AND gate D is 6, the intermediate delay of the first path between register R2 and AND gate D is 7, and the intermediate delay of the second path is 3.

[0094] Further, the selected buffers can be inserted into the first data path circuit based on the target delay and the intermediate delays to obtain a second data path circuit. The buffers to be inserted into the first data path circuit can be selected from the component database according to the size and performance information such as the component delay of each buffer stored in the component database.

[0095] For example, after adjusting the first data path circuit in the data path circuit in Figure 2a , a second data path circuit as shown in Figure 2b is obtained, that is, a buffer a with a component delay of 1 target unit and a buffer b with a component delay of 4 target units are added to the first data path circuit, so that the delays of each target path in the second data path circuit are consistent, that is, the delay of each target path is the target delay. Among them, Figure 2b The second clock cycle of the second data path circuit shown in

[0096] Here, the selected buffers can be inserted into the first data path circuit based on the target delay and the intermediate delays between the registers and the logic components included in the target paths in the first data path circuit to obtain a second data path circuit, so that the delays of each target path in the second data path circuit are consistent, and the glitch power consumption of the data path circuit is avoided.

[0097] For S103:

[0098] In an optional embodiment, when there is a first buffer between the input port of the first data path circuit and the first register, and there is a second buffer between the second register of the first data path circuit and the output port, after obtaining the second data path, the method further comprises:

[0099] Step B1, taking the maximum delay in the path delays corresponding to each target path in the first data path circuit as the target delay;

[0100] Step B2, selecting first and second to-be-replaced components with a component delay matching the target delay, and replacing the first buffer in the second data path with the first to-be-replaced component and replacing the second buffer with the second to-be-replaced component to obtain an intermediate data path circuit.

[0101] In implementation, a first to-be-replaced component with a device delay matching the target delay is selected from the component database, and the first buffer is replaced by the first to-be-replaced component. A second to-be-replaced component with a device delay matching the target delay is selected from the component database, and the second buffer is replaced by the second to-be-replaced component. The first buffer matches the first to-be-replaced component in size, performance, etc., and the second buffer matches the second to-be-replaced component in size, performance, etc.

[0102] If the first buffer exists but the second buffer does not exist, a first to-be-replaced component with a device delay matching the target delay is selected from the component database, and the first buffer is replaced by the first to-be-replaced component. If the second buffer exists but the first buffer does not exist, a second to-be-replaced component with a device delay matching the target delay is selected from the component database, and the second buffer is replaced by the second to-be-replaced component.

[0103] In the second data path circuit shown in Figure 2b In the second data path circuit shown in Figure 2b In the second data path circuit shown in Figure 2c In the second data path circuit shown in

[0104] The component adjustment operation on the second data path circuit can include a component adjustment operation on the intermediate data path circuit.

[0105] Here, the first buffer and the second buffer are replaced by components to obtain the intermediate data path circuit, so that the intermediate data path circuit meets the circuit design requirements to ensure that the integrated circuit can work normally.

[0106] In an optional implementation, the component adjustment operation on the second data path circuit to obtain the adjusted third data path circuit includes at least one of the following component adjustment operations on the second data path circuit: component replacement, component deletion, and component addition, to obtain the adjusted third data path circuit.

[0107] Since the input of the data path circuit is a clock signal, there is a clock period, and the clock period includes multiple beat signals; and in the data path circuit, if different signals input to the same logic device are signals of the same beat in the clock signal (i.e., the delay of different signals to the same logic device differs by an integer multiple of the first clock period), the logic device in the data path circuit will not generate a glitch. Based on this, at least one of the component adjustment operations of component replacement, component deletion, and component addition can be performed on the second data path circuit using a clock skew planning method to obtain an adjusted third data path circuit. The clock skew planning method is a method of planning the clock period and components of the data path circuit such that the delay of different input signals to the same logic device differs by an integer multiple of the clock period.

[0108] For example, if the clock period is 4 seconds, and if two signals input to the same logic device are signals at the 1st second and signals at the 5th second, the signals input to the same logic device are signals of the same beat in the clock signal.

[0109] For example, a target clock period (i.e., the first clock period) can be determined, and at least one of the component adjustment operations of component replacement, component deletion, and component addition can be performed on the second data path circuit or on the intermediate data path circuit to obtain a third data path circuit, so that the clock period of the third data path circuit is the target clock period.

[0110] For example, a target clock period (i.e., the first clock period) can be determined, and at least one of the component adjustment operations of component replacement, component deletion, and component addition can be performed on the second data path circuit or on the intermediate data path circuit to obtain a third data path circuit, so that the clock period of the third data path circuit is the target clock period. Figure 2c For example, a target clock period (i.e., the first clock period) can be determined, and at least one of the component adjustment operations of component replacement, component deletion, and component addition can be performed on the second data path circuit or on the intermediate data path circuit to obtain a third data path circuit, so that the clock period of the third data path circuit is the target clock period. Figure 2d For example, a target clock period (i.e., the first clock period) can be determined, and at least one of the component adjustment operations of component replacement, component deletion, and component addition can be performed on the second data path circuit or on the intermediate data path circuit to obtain a third data path circuit, so that the clock period of the third data path circuit is the target clock period. Figure 2c For example, the buffer A1 (i.e., the first component to be replaced) in the intermediate data path circuit in

[0111] For example, the buffer A1 (i.e., the first component to be replaced) in the intermediate data path circuit in Figure 2dIt can be seen that the delay of input signal 1 to AND gate C is 0, and the delay of input signal 2 to AND gate C is 4. The difference in delay between the two input signals to AND gate C is 4, meaning the difference in delay between different input signals to AND gate C is 1 time the first clock cycle. The delay of input signal 1 to AND gate D is 4. The delay of input signal 2 to AND gate D via the first path (buffer A2 > register R2 > buffer B > AND gate C) is 8. The delay of input signal 2 to AND gate D via the second path (buffer A2 > register R2 > buffer B > buffer b) is 8. The difference in delay between the two input signals to AND gate D is 4, meaning the difference in delay between different input signals to AND gate D is 1 time the first clock cycle.

[0112] Here, at least one of the following component adjustment operations can be performed on the second data path circuit: component replacement, component deletion, and component addition to obtain the adjusted third data path circuit. The types of component adjustment operations are quite diverse, so that the adjusted third data path circuit can be obtained flexibly.

[0113] In one optional embodiment, if a third buffer exists between the third register and the output port of the third data path circuit, after obtaining the third data path circuit, the method further includes: selecting a third replacement component whose device delay matches the second clock cycle, and replacing the third buffer with the third replacement component to obtain the fourth data path circuit.

[0114] by Figure 2d Taking the third data path circuit shown as an example, when the third data path circuit includes a third buffer E1, a third replacement component E2 whose device delay matches the second clock cycle can be selected from the component database, and the third buffer can be replaced with the third replacement component E2, resulting in the following... Figure 2e The fourth data path circuit shown is designed to ensure that other data path circuits connected to the third replacement component in the integrated circuit can function properly.

[0115] Those skilled in the art will understand that, in the above-described method of the specific implementation, the order in which each step is written does not imply a strict execution order and does not constitute any limitation on the implementation process. The specific execution order of each step should be determined by its function and possible internal logic.

[0116] Based on the same concept, this disclosure also provides a circuit adjustment device, see [link to relevant documentation]. Figure 3 The diagram shown is a schematic representation of the circuit adjustment device provided in this embodiment of the present disclosure, including a determining module 301, a first adjustment module 302, and a second adjustment module 303. Specifically:

[0117] The determining module 301 is configured to determine a first data path circuit in an integrated circuit; wherein there is a target path between different registers in the first data path circuit;

[0118] The first adjusting module 302 is configured to insert selected buffers in the first data path circuit based on device delays of electronic components included in the target path in the first data path circuit, to obtain a second data path circuit; wherein the delays of each target path in the second data path circuit are consistent.

[0119] The second adjusting module 303 is configured to perform a component adjustment operation on the second data path circuit, to obtain an adjusted third data path circuit; wherein a first clock cycle corresponding to the third data path circuit is less than a second clock cycle corresponding to the second data path circuit, and the delays of different input signals to the same logic device in the third data path circuit differ by an integer multiple of the first clock cycle.

[0120] In a possible implementation, the first adjusting module 302, when inserting selected buffers in the first data path circuit based on the device delays of electronic components included in the target path in the first data path circuit, to obtain a second data path circuit, is configured to:

[0121] determine path delays corresponding to the target path in the first data path circuit based on the device delays of electronic components included in the target path in the first data path circuit;

[0122] take the maximum delay in the path delays corresponding to each target path in the first data path circuit as a target delay;

[0123] insert selected buffers in the first data path circuit based on the target delay and intermediate delays between registers and logic devices included in the target path in the first data path circuit, to obtain a second data path circuit.

[0124] In a possible implementation, in the case that there is a first buffer between an input port of the first data path circuit and a first register, and there is a second buffer between a second register and an output port of the first data path circuit, after obtaining the second data path, the apparatus further includes a first replacing module 304 configured to:

[0125] take the maximum delay in the path delays corresponding to each target path in the first data path circuit as a target delay;

[0126] Select a first replacement component and a second replacement component whose device delay matches the target delay, and replace the first buffer in the second data path with the first replacement component and the second buffer with the second replacement component to obtain an intermediate data path circuit;

[0127] The second adjustment module 303, when performing component adjustment operations on the second data path circuit, is used for:

[0128] The intermediate data path circuit is adjusted by component adjustments.

[0129] In one possible implementation, the second adjustment module 303, when performing component adjustment operations on the second data path circuit to obtain the adjusted third data path circuit, is used to:

[0130] Perform at least one of the following component adjustment operations on the second data path circuit: component replacement, component deletion, or component addition to obtain the adjusted third data path circuit.

[0131] In one possible implementation, where a third buffer exists between the third register and the output port of the third data path circuit, after obtaining the third data path circuit, the apparatus further includes: a second replacement module 305, configured to:

[0132] A third replacement component whose device delay matches the second clock cycle is selected, and the third buffer is replaced with the third replacement component to obtain the fourth data path circuit.

[0133] In one possible implementation, before determining the first data path circuit in the integrated circuit, the device further includes: a processing module 306, configured to:

[0134] By using integer linear programming, the initial device delay of each electronic component in the integrated circuit is integerized to obtain the device delay of each electronic component as an integer multiple of the target unit.

[0135] Based on the same concept, this disclosure also provides a data path circuit, including at least one component selected from logic devices, registers, and buffers; the data path circuit is generated based on the circuit adjustment method described in the above embodiments.

[0136] In some embodiments, the functions or templates of the apparatus provided in this disclosure can be used to perform the methods described in the above method embodiments. The specific implementation can be referred to the description of the above method embodiments, and for the sake of brevity, it will not be repeated here.

[0137] Based on the same technical concept, the embodiment of the present disclosure also provides an electronic device. Referring to Figure 4 As shown in FIG. 4, an electronic device provided by the embodiment of the present disclosure includes a processor 401, a memory 402, and a bus 403. The memory 402 is used to store execution instructions, including an internal memory 4021 and an external memory 4022. The internal memory 4021 is also referred to as an internal storage, and is used to temporarily store operation data in the processor 401 and exchange data with the external memory 4022 such as a hard disk. The processor 401 exchanges data with the external memory 4022 through the internal memory 4021. When the electronic device 400 is running, the processor 401 communicates with the memory 402 through the bus 403, so that the processor 401 executes the following instructions:

[0138] determining a first data path circuit in an integrated circuit; wherein there is a target path between different registers in the first data path circuit;

[0139] based on the device delay of the electronic components included in the target path in the first data path circuit, inserting a selected buffer in the first data path circuit to obtain a second data path circuit, wherein the delays of each target path in the second data path circuit are consistent;

[0140] performing a component adjustment operation on the second data path circuit to obtain an adjusted third data path circuit; wherein the first clock period corresponding to the third data path circuit is less than the second clock period corresponding to the second data path circuit, and the delay of different input signals reaching the same logic device in the third data path circuit differs by an integer multiple of the first clock period.

[0141] The specific processing procedure of the processor 401 can refer to the description of the above method embodiments, which will not be described here.

[0142] In addition, the embodiment of the present disclosure also provides a computer readable storage medium, which stores a computer program. When the computer program is run by a processor, the steps of the circuit adjustment method described in the above method embodiments are executed. The storage medium can be a volatile or non-volatile computer readable storage medium.

[0143] The embodiment of the present disclosure also provides a computer program product, which carries a program code. The instructions included in the program code can be used to execute the steps of the circuit adjustment method described in the above method embodiments. For details, please refer to the above method embodiments, which will not be described here.

[0144] The computer program product can be implemented by hardware, software or a combination thereof. In an optional embodiment, the computer program product is embodied in a computer storage medium. In another optional embodiment, the computer program product is embodied in a software product, such as a software development kit (SDK) or the like.

[0145] Those skilled in the art can clearly understand that, for the convenience and brevity of description, the specific working process of the system and device described above can refer to the corresponding process in the foregoing method embodiments, which will not be repeated here. In several embodiments provided in the present disclosure, it should be understood that the disclosed system, device and method can be implemented in other ways. The device embodiments described above are merely schematic, for example, the division of the units is only a logical function division, and actual implementation can have another division manner, for example, a plurality of units or components can be combined or integrated into another system, or some features can be omitted or not executed. In addition, the coupling or direct coupling or communication connection between the units shown or discussed can be indirect coupling or communication connection through some communication interfaces, devices or units, which can be electrical, mechanical or other forms.

[0146] The units described as separate components can or can not be physically separate, and the components shown as units can or can not be physical units, that is, they can be located in one place, or can be distributed on a plurality of network units. Part or all of the units can be selected according to actual needs to achieve the purpose of the embodiment scheme.

[0147] In addition, each functional unit in each embodiment of the present disclosure can be integrated in one processing unit, or each unit can exist physically independently, or two or more units can be integrated in one unit.

[0148] If the functions are implemented in the form of software function units and sold or used as independent products, they can be stored in a nonvolatile computer readable storage medium executable by a processor. Based on this understanding, the technical solutions of the present disclosure, essentially or in part, or parts of the technical solutions can be embodied in the form of a software product. The computer software product is stored in a storage medium, including a number of instructions to enable a computer device (which can be a personal computer, a server, or a network device, etc.) to perform all or part of the steps of the methods described in the various embodiments of the present disclosure. The aforementioned storage medium includes: U disk, mobile hard disk, read-only memory (ROM), random access memory (RAM), magnetic disk or optical disk, and various other media that can store program codes.

[0149] The above merely describes the specific embodiments of the present disclosure, but the protection scope of the present disclosure is not limited thereto. Any person skilled in the art can easily think of changes or replacements within the technical scope disclosed by the present disclosure, which shall be covered within the protection scope of the present disclosure. Therefore, the protection scope of the present disclosure shall be subject to the protection scope of the claims.

Claims

1. A circuit adjustment method characterized by comprising: The method comprises the following steps: determining a first data path circuit in an integrated circuit; wherein there is a target path between different registers in the first data path circuit; based on the device delay of the electronic components included in the target path in the first data path circuit, inserting selected buffers in the first data path circuit to obtain a second data path circuit, wherein the delays of each target path in the second data path circuit are consistent; performing component adjustment operation on the second data path circuit to obtain an adjusted third data path circuit; wherein the first clock period corresponding to the third data path circuit is smaller than the second clock period corresponding to the second data path circuit, and the delay of different input signals reaching the same logic device in the third data path circuit is different by an integer multiple of the first clock period; in the case that there is a first buffer between the input port of the first data path circuit and the first register, and a second buffer between the second register of the first data path circuit and the output port, after obtaining the second data path, the method further comprises: taking the maximum delay in the path delay corresponding to each target path in the first data path circuit as a target delay; selecting first and second to-be-replaced components whose device delays match the target delay, and replacing the first buffer in the second data path with the first to-be-replaced component and replacing the second buffer with the second to-be-replaced component to obtain an intermediate data path circuit; the component adjustment operation on the second data path circuit comprises component adjustment operation on the intermediate data path circuit.

2. The method of claim 1, wherein, the method of inserting selected buffers in the first data path circuit based on the device delay of the electronic components included in the target path in the first data path circuit to obtain a second data path circuit comprises: determining the path delay corresponding to the target path in the first data path circuit based on the device delay of the electronic components included in the target path in the first data path circuit; taking the maximum delay in the path delay corresponding to each target path in the first data path circuit as a target delay; based on the target delay and the intermediate delay between the registers and logic devices included in the target path in the first data path circuit, inserting selected buffers in the first data path circuit to obtain a second data path circuit.

3. The method according to claim 1 or 2, characterized in that, the component adjustment operation on the second data path circuit to obtain an adjusted third data path circuit comprises: performing at least one of the following component adjustment operations on the second data path circuit: component replacement, component deletion, and component addition, to obtain an adjusted third data path circuit.

4. The method according to claim 1 or 2, characterized in that, in the case that there is a third buffer between the third register of the third data path circuit and the output port, after obtaining the third data path circuit, the method further comprises: selecting a third to-be-replaced component device with a device delay matching the second clock cycle, and replacing the third buffer with the third to-be-replaced component device to obtain a fourth data path circuit.

5. The method according to claim 1 or 2, characterized in that, Before determining the first data path circuit in the integrated circuit, the method further comprises: integerizing the initial device delay of each electronic component device in the integrated circuit by using an integer linear programming method to obtain a device delay corresponding to an integer multiple target unit of each electronic component device.

6. A circuit adjustment device, characterized by comprising: comprises: a determining module configured to determine a first data path circuit in an integrated circuit; wherein there is a target path between different registers in the first data path circuit; a first adjusting module configured to insert a selected buffer in the first data path circuit based on a device delay of an electronic component device included in a target path in the first data path circuit to obtain a second data path circuit, wherein the delays of each target path in the second data path circuit are consistent; a second adjusting module configured to perform a component device adjusting operation on the second data path circuit to obtain a third data path circuit after adjustment; wherein a first clock cycle corresponding to the third data path circuit is less than a second clock cycle corresponding to the second data path circuit, and in the third data path circuit, the delays of different input signals to the same logic device differ by an integer multiple of the first clock cycle; in a case where there is a first buffer between an input port of the first data path circuit and a first register, and there is a second buffer between a second register of the first data path circuit and an output port, after obtaining the second data path, the apparatus further comprises a first replacing module configured to: take a maximum delay in the path delays corresponding to each target path in the first data path circuit as a target delay; select a first to-be-replaced component device and a second to-be-replaced component device with device delays matching the target delay, and replace the first buffer in the second data path with the first to-be-replaced component device and replace the second buffer with the second to-be-replaced component device to obtain an intermediate data path circuit; the second adjusting module, when performing the component device adjusting operation on the second data path circuit, is configured to perform a component device adjusting operation on the intermediate data path circuit.

7. A data path circuit, comprising: comprises: at least one of a logic device, a register, and a buffer; the data path circuit is generated based on the circuit adjusting method of any one of claims 1 to 5.

8. An electronic device, comprising: comprises: a processor, a memory, and a bus, the memory stores machine readable instructions executable by the processor, when the electronic device is running, the processor and the memory communicate through the bus, the machine readable instructions are executed by the processor to execute the steps of the circuit adjusting method of any one of claims 1 to 5, or the data path circuit of claim 7.

9. A computer-readable storage medium, characterized in that, The computer readable storage medium stores a computer program, which is executed by the processor to execute the steps of the circuit adjusting method of any one of claims 1 to 5. The computer readable storage medium stores a computer program, which is executed by the processor to execute the steps of the circuit adjusting method of any one of claims 1 to 5.

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