Phase interpolation circuit, reception circuit, and semiconductor integrated circuit

Abstract

To provide a phase interpolation circuit for generating an output clock signal in which phase deviation to a phase interpolation code is suppressed.SOLUTION: A phase interpolation circuit for generating a differential output clock signal having a phase according to a current control code, on the basis of first and second differential input clock signals having a first phase difference has: a first generation circuit for generating first differential intermediate current on the basis of a first differential input clock signal according to a first current control code; a second generation circuit for generating second differential intermediate current on the basis of a second differential input clock signal according to a second current control code; a synthesis circuit for synthesizing the first and second differential intermediate currents, and generating a differential output clock signal; a correction circuit for correcting the current amount of one differential intermediate current of the first and second differential intermediate currents, on the basis of correction current according to a correction code; and a common mode voltage correction circuit for correcting a common mode voltage in a differential output clock signal according to variation.SELECTED DRAWING: Figure 20

Description

Technical Field

[0001] The present invention relates to a phase interpolation circuit, a reception circuit, and a semiconductor integrated circuit.

Background Art

[0002] A reception circuit of a deserializer of a serializer / deserializer (SerDes) acquires data from a high-speed reception signal based on a clock signal. In order to adjust the phase of the clock signal so that data can be appropriately acquired from the reception signal, there is a phase interpolation (PI) circuit that generates an output clock signal having a desired phase from a plurality of input clock signals. The phase interpolation circuit is used as a phase adjustment circuit of a clock data recovery (CDR) circuit used in the reception circuit.

[0003] For example, in the reception circuit of the deserializer, as shown in FIG. 16, a comparator 1604 acquires data DT from the reception signal DTIN using a first output clock signal ICKO output from the phase interpolation circuit 1601, and a comparator 1605 acquires a boundary BD from the reception signal DTIN using a second output clock signal QCKO output from the phase interpolation circuit 1601. The first output clock signal ICKO and the second output clock signal QCKO have a predetermined phase difference (substantially 90 degrees).

[0004] The phase interpolation circuit 1601 generates output clock signals ICKO and QCKO having phases corresponding to an input phase interpolation (PI) code based on input clock signals ICKI and QCKI, respectively. The phase interpolation circuit 1601 includes a phase interpolation circuit 1602 that generates the first output clock signal ICKO and a phase interpolation circuit 1603 that generates the second output clock signal QCKO. The phase interpolation circuits 1602 and 1603 generate the output clock signals ICKO and QCKO, respectively, by weighting and synthesizing the input clock signals ICKI and QCKI based on the PI code.

[0005] A configuration example of the conventional phase interpolation circuits 1602 and 1603 is shown in FIG. 17 (see, for example, Patent Document 1). The drains of transistors 1711, 1722, 1731, and 1742 are connected to the power supply VDD via a resistor 1701. The drains of transistors 1711, 1722, 1731, and 1742 are connected to the output terminal OUTP. Also, the drains of transistors 1712, 1721, 1732, and 1741 are connected to the power supply VDD via a resistor 1702. The drains of transistors 1712, 1721, 1732, and 1741 are connected to the output terminal OUTN.

[0006] An input clock signal ICKIP is input to the gates of transistors 1711 and 1721, and an input clock signal ICKIN having an inverted phase with respect to the input clock signal ICKIP is input to the gates of transistors 1712 and 1722. Also, an input clock signal QCKIP having a predetermined phase difference from the input clock signal ICKIP is input to the gates of transistors 1731 and 1741, and an input clock signal QCKIN having an inverted phase with respect to the input clock signal QCKIP is input to the gates of transistors 1732 and 1742. The input clock signals ICKIP and ICKIN correspond to the input clock signal ICKI shown in FIG. 16, and the input clock signals QCKIP and QCKIN correspond to the input clock signal QCKI shown in FIG. 16.

[0007] The drain of transistor 1713 is connected to the sources of transistors 1711 and 1712, and the drain of transistor 1723 is connected to the sources of transistors 1721 and 1722. Also, the drain of transistor 1733 is connected to the sources of transistors 1731 and 1732, and the drain of transistor 1743 is connected to the sources of transistors 1741 and 1742. The sources of transistors 1713, 1723, 1733, and 1743 are grounded.

[0008] Gate voltages VGAP and VGAN are applied to the gates of transistors 1713 and 1723 in accordance with the PI code, and gate voltages VGBP and VGBN are applied to the gates of transistors 1733 and 1743 in accordance with the PI code. Transistors 1713, 1723, 1733, and 1743 function as current sources that pass current to the corresponding transistors in accordance with the PI code. Either transistor 1713 or 1723 and either transistor 1733 or 1743 are driven by a voltage in accordance with the PI code, whereby one of input clock signals ICKIP and ICKIN and one of input clock signals QCKIP and QCKIN are weighted and combined to generate an output clock signal.

[0009] If there is a phase mismatch (skew mismatch) between the input clock signals ICKI and QCKI input to the phase interpolator 1601, a phase mismatch also occurs between the output clock signals ICKO and QCKO. The phases of the output clock signals ICKO and QCKO vary linearly in response to the PI code, as shown by the dashed lines in an example of FIG. 18. It is desirable to maintain a constant phase difference regardless of the PI code. However, as shown by the solid lines 1801 and 1802, the phases change, resulting in a phase mismatch depending on the PI code. If the phase difference between the output clock signals ICKO and QCKO varies in this way in response to the PI code, the timing margin of the circuits using the output clock signals ICKO and QCKO is reduced, hindering high-speed operation.

[0010] 19, one way to avoid this is to provide an input clock correction circuit 1901, which has the same function as the phase interpolator 1601, in the preceding stage of the phase interpolator 1601, and generate clock signals in which the phase difference deviation has been corrected based on the input clock signals ICKI and QCKI using internal circuits 1902 and 1903, and input the clock signals to the phase interpolator 1601. This method requires the addition of a circuit for transmitting high-speed signals. [Prior art documents] [Patent documents]

[0011] [Patent Document 1] Japanese Patent Application Laid-Open No. 2014-146869 [Patent Document 2] Japanese Patent Application Publication No. 2016-219916 [Patent Document 3] US Patent Application Publication No. 2016 / 0182216 Summary of the Invention [Problem to be solved by the invention]

[0012] An object of the present invention is to provide a phase interpolation circuit that generates an output clock signal in which the phase shift relative to the phase interpolation code is suppressed. [Means for solving the problem]

[0013] One aspect of the phase interpolator circuit includes a first generation circuit that generates a first differential intermediate current based on a first differential input clock signal in accordance with a first current control code; a second generation circuit that generates a second differential intermediate current based on a second differential input clock signal that has a first phase difference from the first differential input clock signal in accordance with a second current control code; a combination circuit that combines the first differential intermediate current and the second differential intermediate current to generate an output clock signal; a correction circuit that corrects the current amount of at least one of the first intermediate current and the second intermediate current based on a correction current in accordance with a correction code that is set so that the first differential intermediate current and the second differential intermediate current cause fluctuations in the common-mode voltage in the differential output clock signal; and a common-mode voltage correction circuit that corrects the common-mode voltage in the differential output clock signal in accordance with the fluctuations. [Effects of the Invention]

[0014] The disclosed phase interpolation circuit can generate an output clock signal with reduced phase deviation relative to the phase interpolation code. [Brief explanation of the drawings]

[0015]

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[0016] Hereinafter, embodiments of the present invention will be described with reference to the drawings.

[0017] (First Embodiment) The first embodiment of the present invention will be described. FIG. 1 is a diagram showing a configuration example of a phase interpolation circuit in the first embodiment. The phase interpolation circuit in the first embodiment includes resistors 101 and 102, and transistors 111 to 113, 121 to 123, 131 to 134, and 141 to 144. The transistors 111 to 113, 121 to 123, 131 to 134, and 141 to 144 are, for example, N-type MOSFETs (Metal Oxide Semiconductor Field Effect Transistors).

[0018] The drains of transistors 111, 122, 131, and 142 are connected to the power supply VDD via the load resistor 101. Also, the connection point between the drains of transistors 111, 122, 131, and 142 and the resistor 101 is connected to the output terminal OUTP. The drains of transistors 112, 121, 132, and 141 are connected to the power supply VDD via the load resistor 102. Also, the connection point between the drains of transistors 112, 121, 132, and 141 and the resistor 102 is connected to the output terminal OUTN.

[0019] The input clock signal ICKIP is input to the gate of transistor 111, and the input clock signal ICKIN, which is the inverted phase of the input clock signal ICKIP, is input to the gate of transistor 112. The sources of transistor 111 and transistor 112 are commonly connected to the drain of transistor 113. The source of transistor 113 is grounded, and the gate voltage VGAP is applied to the gate of transistor 113 according to the phase interpolation (PI) code. Transistor 113 functions as a current source that supplies current to transistors 111 and 112 according to the PI code.

[0020] The input clock signal ICKIP is input to the gate of transistor 121, and the input clock signal ICKIN is input to the gate of transistor 122. The sources of transistor 121 and transistor 122 are commonly connected to the drain of transistor 123. The source of transistor 123 is grounded, and the gate voltage VGAN is applied to the gate of transistor 123 according to the PI code. Transistor 123 functions as a current source that supplies current to transistors 121 and 122 according to the PI code.

[0021] In the example shown in FIG. 1, the transistors 111, 112, 121, 122 and the transistors 113, 123 described above are an example of a first generation circuit that generates a first intermediate current with respect to the connection points with the resistors 101 and 102 based on the first input clock signals ICKIP and ICKIN according to the PI code.

[0022] Also, an input clock signal ICKIP having a predetermined phase difference from an input clock signal QCKIP is input to the gate of transistor 131, and an input clock signal QCKIN having a phase opposite to that of the input clock signal QCKIP is input to the gate of transistor 132. The sources of transistor 131 and transistor 132 are commonly connected to the drains of transistor 133 and transistor 134. The sources of transistor 133 and transistor 134 are grounded, a gate voltage VGBP is applied to the gate of transistor 133 according to the PI code, and a gate voltage VGCP is applied to the gate of transistor 134 according to the PI code and the correction code. Transistor 133 functions as a current source that supplies current to transistors 131 and 132 according to the PI code, and transistor 134 functions as a current source that supplies current to transistors 131 and 132 according to the PI code and the correction code.

[0023] The input clock signal QCKIP is input to the gate of transistor 141, and the input clock signal QCKIN is input to the gate of transistor 142. The sources of transistor 141 and transistor 142 are commonly connected to the drains of transistor 143 and transistor 144. The sources of transistor 143 and transistor 144 are grounded, a gate voltage VGBN is applied to the gate of transistor 143 according to the PI code, and a gate voltage VGCN is applied to the gate of transistor 144 according to the PI code and the correction code. Transistor 143 functions as a current source that supplies current to transistors 141 and 142 according to the PI code, and transistor 144 functions as a current source that supplies current to transistors 141 and 142 according to the PI code and the correction code.

[0024] In the example shown in FIG. 1, the transistors 131, 132, 141, 142 and the transistors 133, 143 described above are an example of a second generation circuit that generates a second intermediate current with respect to the connection points with the resistors 101, 102 based on the second input clock signals QCKIP, QCKIN according to the PI code.

[0025] In the example shown in FIG. 1, the resistors 101 and 102, the drains of the transistors 111, 122, 131, 142 and the connection points of the resistors 101, and the drains of the transistors 112, 121, 132, 141 and the connection points of the resistors 102 are an example of a synthesizing circuit that synthesizes the above-described first intermediate current and second intermediate current to generate an output clock signal at the output terminals OUTP and OUTN.

[0026] Note that, in the example shown in FIG. 1, the transistors (134, 144) that function as current sources for flowing current according to the correction code are provided on the side of the transistors 133 and 143 (the side of the second intermediate current) that function as current sources for flowing current according to the PI code. Instead, they may be provided on the side of the transistors 113 and 123 (the side of the first intermediate current) that function as current sources for flowing current according to the PI code in the same manner, or they may be provided on both sides thereof.

[0027] FIG. 2A is a diagram showing a configuration example of a gate voltage control circuit that controls the gate voltages VGAP and VGAN applied to the gates of the transistors 113 and 123 shown in FIG. 1. As shown in FIG. 2A, the gate voltage control circuit includes a current DAC (digital-analog converter) 201, a transistor 202, and a switch 203.

[0028] The current DAC 201 outputs a current corresponding to the absolute value of the code value of the input current control code PIA. The current control code PIA is set based on the PI code for the phase interpolation circuit, and is a code for controlling the current flowing through the transistors 113 and 123 that function as current sources for the input clock signals ICKIP and ICKIN corresponding to the PI code. The transistor 202 is diode-connected between the output terminal of the current DAC 201 and the ground. That is, the output terminal of the current DAC 201 is connected to the drain and gate of the transistor 202, and the source of the transistor 202 is grounded.

[0029] Switch 203 is connected to the gate of transistor 202, and outputs, as gate voltage VGAP or VGAN according to the sign of the current control code PIA of the current control code PIA, the voltage generated by inputting the output current of current DAC 201 to diode-connected transistor 202. When the current control code PIA is positive, switch 203 outputs, as gate voltage VGAP, the voltage corresponding to the current control code PIA generated by current DAC 201 and diode-connected transistor 202 to the gate of transistor 113. Further, when the current control code PIA is negative, switch 203 outputs, as gate voltage VGAN, the voltage corresponding to the current control code PIA generated by current DAC 201 and diode-connected transistor 202 to the gate of transistor 123.

[0030] FIG. 2B is a diagram showing a configuration example of a gate voltage control circuit that controls gate voltages VGBP and VGBN applied to the gates of transistors 133 and 143 shown in FIG. 1. As shown in FIG. 2B, the gate voltage control circuit includes a current DAC 211, a transistor 212, and a switch 213.

[0031] Current DAC 211 outputs a current according to the absolute value of the code value of the input current control code PIB. The current control code PIB is set based on the PI code for the phase interpolation circuit, and is a code for controlling the current flowing through transistors 133 and 143 that function as current sources for the input clock signals QCKIP and QCKIN corresponding to the PI code. Transistor 212 is diode-connected between the output terminal of current DAC 211 and ground. That is, the output terminal of current DAC 211 is connected to the drain and gate of transistor 212, and the source of transistor 212 is grounded.

[0032] Switch 213 is connected to the gate of transistor 212, and outputs, as gate voltage VGBP or VGBN according to the sign of the current control code PIB of the current control code PIB, the voltage generated by inputting the output current of current DAC 211 to the diode-connected transistor 212. When the current control code PIB is positive, switch 213 outputs, as gate voltage VGBP, to the gate of transistor 133 the voltage corresponding to the current control code PIB generated by current DAC 211 and the diode-connected transistor 212. Also, when the current control code PIB is negative, switch 213 outputs, as gate voltage VGBN, to the gate of transistor 143 the voltage corresponding to the current control code PIB generated by current DAC 211 and the diode-connected transistor 212.

[0033] Here, in this specification, examples will be described where the current control code PIA and the current control code PIB are integer values and are in the range of (-16) to (+16). In this case, as the output phase of the clock signal, phase control in the range of 180 degrees with 32 codes in the PI code is possible, and phase control in the range of 360 degrees with 64 codes is possible. Note that this is just an example, and the present invention is not limited to this. The number of PI codes (current control code PIA and current control code PIB) is arbitrary, and by increasing the number of codes, finer phase control is possible.

[0034] FIG. 2C is a diagram showing a configuration example of a gate voltage control circuit that controls the gate voltages VGCP and VGCN applied to the gates of the transistors 134 and 144 shown in FIG. 1. As shown in FIG. 2C, the gate voltage control circuit includes a current DAC 221, transistors 222, 223, 224, and a switch 225.

[0035] The current DAC 221 outputs a current corresponding to the absolute value of the code value of the input correction code CAL. The correction code CAL is a code related to the correction current flowing to reduce the phase error of the output clock signal. The source of the transistor 222 is connected to the power supply VDD, and the drain and gate are connected to the output terminal of the current DAC 221. The source of the transistor 223 is connected to the power supply VDD, and the gate is connected to the gate of the transistor 222. The transistors 222 and 223 constitute a current mirror circuit. The mirror ratio k of the current mirror circuit constituted by the transistors 222 and 223 is changeable and is controlled to change in proportion to the current control code PIA. Therefore, from the drain of the transistor 223, a current (|C|) that is k times the output current (|C0|) of the current DAC 221 corresponding to the correction code CAL is output according to the current control code PIA.

[0036] The transistor 224 is diode-connected between the drain of the transistor 223 and the ground. That is, the drain of the transistor 223 is connected to the drain and gate of the transistor 224, and the source of the transistor 224 is grounded.

[0037] The switch 225 is connected to the gate of the transistor 224, and outputs the voltage generated by inputting a current that is k times the output current of the current DAC 211 to the diode-connected transistor 224 as the gate voltage VGCP or VGCN according to the sign of the multiplication value of the correction code CAL and the current control code PIA. When the multiplication value of the correction code CAL and the current control code PIA is positive, the switch 225 outputs the voltage corresponding to the correction code CAL and the current control code PIA generated by the diode-connected transistor 224 as the gate voltage VGCP to the gate of the transistor 134. Also, when the multiplication value of the correction code CAL and the current control code PIA is negative, the switch 225 outputs the voltage corresponding to the correction code CAL and the current control code PIA generated by the diode-connected transistor 224 as the gate voltage VGCN to the gate of the transistor 144.

[0038] In the example shown in FIG. 1, the transistors 134 and 144 described above and the gate voltage control circuit shown in FIG. 2C are an example of a correction circuit that corrects at least one of the first intermediate current and the second intermediate current based on a correction current corresponding to a correction code.

[0039] FIG. 3A is a diagram showing a circuit configuration example of the gate voltage control circuit shown in FIG. 2A. The output terminal of a current DAC 301 that outputs a current corresponding to the absolute value of the code value of an input current control code PIA is connected to the drain and gate of a transistor 302, and the source of the transistor 302 is grounded. The gate of the transistor 302 is connected to the output terminal of a gate voltage VGAP via a transfer gate composed of transistors 303 and 304. A connection point between the transfer gate composed of transistors 303 and 304 and the output terminal of the gate voltage VGAP is grounded via a transistor 305. Further, the gate of the transistor 302 is connected to the output terminal of a gate voltage VGAN via a transfer gate composed of transistors 306 and 307. A connection point between the transfer gate composed of transistors 306 and 307 and the output terminal of the gate voltage VGAN is grounded via a transistor 308.

[0040] The transfer gate composed of transistors 303 and 304, the transfer gate composed of transistors 305, 306, and 307, and the transistor 308 are switched between a conductive state and a non-conductive state by a signal PIAS and its inverted signal / PIAS. The signal PIAS is a signal indicating the sign of the current control code PIA. When the current control code PIA is positive, the signal PIAS becomes a high level (the inverted signal / PIAS becomes a low level), and when the current control code PIA is negative, the signal PIAS becomes a low level (the inverted signal / PIAS becomes a high level).

[0041] When the signal PIAS is at a high level (inverted signal / PIAS is at a low level), that is, when the current control code PIA is positive, the transfer gate composed of transistors 303 and 304 and the transistor 308 are in a conductive state (on state), and the transfer gate composed of the transistor 305 and the transistors 306 and 307 is in a non-conductive state (off state). Therefore, when the sign of the current control code PIA is positive, the voltage corresponding to the current control code PIA is output as the gate voltage VGAP, and the gate voltage VGAN becomes the ground potential.

[0042] Also, when the signal PIAS is at a low level (inverted signal / PIAS is at a high level), that is, when the current control code PIA is negative, the transfer gate composed of the transistor 305 and the transistors 306 and 307 is in a conductive state (on state), and the transfer gate composed of the transistors 303 and 304 and the transistor 308 is in a non-conductive state (off state). Therefore, when the sign of the current control code PIA is negative, the voltage corresponding to the current control code PIA is output as the gate voltage VGAN, and the gate voltage VGAP becomes the ground potential. Note that the gate voltage control circuit shown in Fig. 2B is similarly configured.

[0043] FIG. 3B is a diagram showing a circuit configuration example of the gate voltage control circuit shown in FIG. 2C. The output terminal of a current DAC 311 that outputs a current corresponding to the absolute value of the code value of the input correction code CAL is connected to the drain and gate of a transistor 312, and the source of the transistor 312 is connected to a power supply VDD. The sources of transistors 313-i (i is a subscript and an integer from 0 to 4; the same applies hereinafter) are connected to the power supply VDD, and the gates are connected to the gate of the transistor 312 via switches 314-i. If the corresponding switches 314-i are in a conducting state (on state), the transistors 313-0 and 313-1 are configured such that a (1 / 16)-fold mirror current flows, and the transistor 313-2 is configured such that a (2 / 16)-fold mirror current flows. Similarly, the transistor 313-3 is configured such that a (4 / 16)-fold mirror current flows, and the transistor 313-4 is configured such that an (8 / 16)-fold mirror current flows. The switches 314-i are turned on / off controlled by a control signal CTL based on a current control code PIA such that the mirror ratio of the current mirror circuit formed by the transistor 312 and the transistor 313-i changes in proportion to the current control code PIA.

[0044] The drain of the transistor 313-i is connected to the drain and gate of a transistor 315, and the source of the transistor 315 is grounded. The gate of the transistor 315 is connected to the output terminal of a gate voltage VGCP via a transfer gate formed by transistors 316 and 317. The connection point between the transfer gate formed by the transistors 316 and 317 and the output terminal of the gate voltage VGCP is grounded via a transistor 318. Also, the gate of the transistor 315 is connected to the output terminal of a gate voltage VGCN via a transfer gate formed by transistors 319 and 320. The connection point between the transfer gate formed by the transistors 319 and 320 and the output terminal of the gate voltage VGCN is grounded via a transistor 321.

[0045] The transfer gate composed of transistors 316 and 317, the transfer gate composed of transistors 318, 319, and 320, and transistor 321 have their conduction states and non-conduction states switched and controlled by signal CALS and its inverted signal / CALS. Signal CALS is a signal indicating the sign of the multiplication value of correction code CAL and current control code PIA. When the multiplication value of correction code CAL and current control code PIA is positive, signal CALS is at a high level (inverted signal / CALS is at a low level). When the multiplication value of correction code CAL and current control code PIA is negative, signal CALS is at a low level (inverted signal / CALS is at a high level).

[0046] When signal CALS is at a high level (inverted signal / CALS is at a low level), that is, when the multiplication value of correction code CAL and current control code PIA is positive, the transfer gate composed of transistors 316 and 317 and transistor 321 are in a conduction state (on state), and transistor 318 and the transfer gate composed of transistors 319 and 320 are in a non-conduction state (off state). Therefore, when the sign of the multiplication value of correction code CAL and current control code PIA is positive, a voltage corresponding to correction code CAL and current control code PIA is output as gate voltage VGCP, and gate voltage VGCN becomes the ground potential.

[0047] Also, when signal CALS is at a low level (inverted signal / CALS is at a high level), that is, when the multiplication value of correction code CAL and current control code PIA is negative, transistor 318 and the transfer gate composed of transistors 319 and 320 are in a conduction state (on state), and the transfer gate composed of transistors 316 and 317 and transistor 321 are in a non-conduction state (off state). Therefore, when the sign of the multiplication value of correction code CAL and current control code PIA is negative, a voltage corresponding to correction code CAL and current control code PIA is output as gate voltage VGCN, and gate voltage VGCP becomes the ground potential.

[0048] Next, the operation of the phase interpolation circuit in this embodiment will be described. The current DACs 201 and 211 of the gate voltage control circuit shown in FIGS. 2A and 2B output currents having absolute values of currents I_A and I_B indicated by solid lines 401 and 402 in FIG. 4A according to the PI code. For the sake of convenience of explanation, the current DACs 201 and 211 are assumed to output a current having a relative value indicating a current ratio of 16 when the absolute values of the input current control codes PIA and PIB are maximum (16), and to output a current having a relative value indicating a current ratio of 0 (no output current) when the absolute values of the input current control codes PIA and PIB are minimum (0).

[0049] The current output from the current DAC 201 is converted into a voltage by the diode-connected transistor 202, and the converted voltage is supplied to the gate of one of the transistors 113 and 123 functioning as a current source according to the sign of the current control code PIA. Similarly, the current output from the current DAC 211 is converted into a voltage by the diode-connected transistor 212, and the converted voltage is supplied to the gate of one of the transistors 133 and 143 functioning as a current source according to the sign of the current control code PIB.

[0050] For example, when the PI code is 8 (output phase 45 degrees), since the current control code PIA is (+8), the current DAC201 of the gate voltage control circuit shown in FIG. 2A outputs a current of relative value 8 corresponding to the absolute value 8 of the current control code PIA. Since the sign of the current control code PIA is positive, the voltage corresponding to the current of relative value 8 is supplied as the gate voltage VGAP to the gate of the transistor 113. Also, when the PI code is 8, since the current control code PIB is (+8), the current DAC211 of the gate voltage control circuit shown in FIG. 2B outputs a current of relative value 8 corresponding to the absolute value 8 of the current control code PIB. Since the sign of the current control code PIB is positive, the voltage corresponding to the current of relative value 8 is supplied as the gate voltage VGBP to the gate of the transistor 133. At this time, the ground potential is supplied as the gate voltage VGAN to the gate of the transistor 123, and the ground potential is supplied as the gate voltage VGBN to the gate of the transistor 143.

[0051] Also, for example, when the PI code is 16 (output phase 90 degrees), since the current control code PIA is (0), the current DAC201 of the gate voltage control circuit shown in FIG. 2A outputs a current of relative value 0 corresponding to the absolute value 0 of the current control code PIA (no output current), and the voltage (ground potential) corresponding to the current of relative value 0 is supplied as the gate voltage VGAP to the gate of the transistor 113. Also, when the PI code is 16, since the current control code PIB is (+16), the current DAC211 of the gate voltage control circuit shown in FIG. 2B outputs a current of relative value 16 corresponding to the absolute value 16 of the current control code PIB. Since the sign of the current control code PIB is positive, the voltage corresponding to the current of relative value 16 is supplied as the gate voltage VGBP to the gate of the transistor 133. At this time, the ground potential is supplied as the gate voltage VGAN to the gate of the transistor 123, and the ground potential is supplied as the gate voltage VGBN to the gate of the transistor 143.

[0052] Also, for example, when the PI code is 32 (output phase 180 degrees), since the current control code PIA is (-16), the current DAC201 of the gate voltage control circuit shown in FIG. 2A outputs a current of relative value 16 corresponding to the absolute value 16 of the current control code PIA. Since the sign of the current control code PIA is negative, the voltage corresponding to the current of relative value 16 is supplied as the gate voltage VGAN to the gate of the transistor 123. Also, when the PI code is 32, since the current control code PIB is 0, the current DAC211 of the gate voltage control circuit shown in FIG. 2B outputs a current of relative value 0 corresponding to the absolute value 0 of the current control code PIB (no output current), and the voltage corresponding to the current of relative value 0 (ground potential) is supplied as the gate voltage VGBP to the gate of the transistor 133. At this time, the ground potential is supplied as the gate voltage VGAP to the gate of the transistor 113, and the ground potential is supplied as the gate voltage VGBN to the gate of the transistor 143.

[0053] Therefore, when the PI code is between 0 and 16, that is, when the current control code PIA is positive and the current control code PIB is positive, the transistors 113 and 133 of the phase interpolation circuit operate as current sources that conduct current based on the PI code. As a result, the transistor 111 generates and outputs an intermediate current based on the input clock signal ICKIP, and the transistor 112 generates and outputs an intermediate current based on the input clock signal ICKIN. Also, the transistor 131 generates and outputs an intermediate current based on the input clock signal QCKIP, and the transistor 132 generates and outputs an intermediate current based on the input clock signal QCKIN. Then, the signal obtained by synthesizing the intermediate current output from the transistor 111 and the intermediate current output from the transistor 131 on the node is output as the output clock signal from the output terminal OUTP. Also, the signal obtained by synthesizing the intermediate current output from the transistor 112 and the intermediate current output from the transistor 132 on the node is output as the output clock signal (inverted output clock signal) from the output terminal OUTN. In this way, the input clock signals ICKI (ICKIP, ICKIN) and the input clock signals QCKI (QCKIP, QCKIN) are weighted and synthesized according to the phase interpolation (PI) code, and the output clock signal is generated.

[0054] Also, when the PI code is between 17 and 32, that is, when the current control code PIA is negative and the current control code PIB is positive, the transistors 123 and 133 of the phase interpolation circuit operate as current sources that conduct current based on the PI code. As a result, the transistor 121 generates and outputs an intermediate current based on the input clock signal ICKIP, and the transistor 122 generates and outputs an intermediate current based on the input clock signal ICKIN. Also, the transistor 131 generates and outputs an intermediate current based on the input clock signal QCKIP, and the transistor 132 generates and outputs an intermediate current based on the input clock signal QCKIN. Then, a signal obtained by synthesizing the intermediate current output from the transistor 122 and the intermediate current output from the transistor 131 on the node is output as the output clock signal from the output terminal OUTP. Also, a signal obtained by synthesizing the intermediate current output from the transistor 121 and the intermediate current output from the transistor 132 on the node is output as the output clock signal (inverted output clock signal) from the output terminal OUTN.

[0055] The same applies when the PI code is between 33 and 48, or between 49 and 64. That is, when the PI code is between 33 and 48, since the current control code PIA is negative and the current control code PIB is negative, the transistors 123 and 143 of the phase interpolation circuit operate as current sources that conduct current based on the PI code, and the output clock signal is generated in the same way. Also, when the PI code is between 49 and 64, since the current control code PIA is positive and the current control code PIB is negative, the transistors 113 and 143 of the phase interpolation circuit operate as current sources that conduct current based on the PI code, and the output clock signal is generated in the same way.

[0056] Furthermore, in the phase interpolation circuit according to this embodiment, a correction current is passed to adjust the phase difference of the output clock signals (ICKO, QCKO) to a predetermined phase difference (90 degrees). In the phase interpolation circuit shown in FIG. 1, transistors 134 and 144 function as current sources for passing the correction current. In this embodiment, as shown in FIG. 4B, the phase error of the output clock signal ICKO is measured with reference to the output clock signal QCKO, and the phase of the output clock signal ICKO is corrected by passing a correction current so that the phase error becomes smaller, thereby adjusting the phase difference between the output clock signals (ICKO, QCKO). The amount of the correction current is determined by setting a predetermined PI code and measuring the phase of the output clock signal to determine a correction code for passing the correction current, and is adjusted by changing the mirror ratio of the current mirror circuit in the gate voltage control circuit according to the current control code PIA set based on the PI code.

[0057] For example, when the determined correction code CAL is (-8), the current DAC 221 of the gate voltage control circuit shown in FIG. 2C outputs a current with a relative value 8 corresponding to the absolute value 8 of the correction code CAL. Therefore, the current mirror circuit composed of transistors 222 and 223 outputs a correction current I_Bcal indicated by a solid line 403 in FIG. 4A according to the PI code. The output correction current I_Bcal is converted into a voltage by the diode-connected transistor 224, and the converted voltage is supplied to the gate of one of the transistors 134 and 144 functioning as a current source according to the sign of the multiplication value of the correction code CAL and the current control code PIA.

[0058] As an example, when the PI code is 8, since the current control code PIA is (+8), the gate voltage control circuit shown in Fig. 2C multiplies the absolute value of the correction code CAL (8) by the ratio corresponding to the current control code PIA, that is, the ratio of the current value of the absolute value of the current control code PIA (8) to its maximum value (16), to generate a current with a relative value of 4 (= 8×8 / 16). Since the sign of the multiplication value of the correction code CAL and the current control code PIA is negative, the voltage corresponding to the generated current is supplied as the gate voltage VGCN to the gate of the transistor 144. Also, when the PI code is 16, since the current control code PIA is (0), the gate voltage control circuit shown in Fig. 2C supplies the voltage corresponding to a current with a relative value of 0 (= 8×0 / 16) (ground potential) as the gate voltage VGCP to the gate of the transistor 134. Also, when the PI code is 32, since the current control code PIA is (-16), the gate voltage control circuit shown in Fig. 2C generates, for example, a current with a relative value of 8 (= 8×16 / 16) according to the ratio of the current value of the absolute value of the current control code PIA (16) to its maximum value (16) based on the absolute value of the correction code CAL (8). Since the sign of the multiplication value of the correction code CAL and the current control code PIA is positive, the voltage corresponding to the generated current is supplied as the gate voltage VGCP to the gate of the transistor 134.

[0059] As described above, in the phase interpolation circuit according to the present embodiment, control is performed according to the PI code as shown in an example in FIG. 5. Thereby, based on the correction code and the correction current according to the PI code, the amount of the intermediate current output from the transistors 131, 132, 141, and 142 is corrected, and the phase of the output clock signal obtained by synthesizing the intermediate currents is adjusted. In this way, the phase interpolation circuit according to the present embodiment adjusts the phase difference between the output clock signals (ICKO, QCKO) to a predetermined phase difference (90 degrees). As a result, the phases of the output clock signals (ICKO, QCKO) change as shown by the solid lines 601 and 602 in FIG. 6, for example, and the deviation of the phase difference in the output clock signals (ICKO, QCKO) can be suppressed. Therefore, it is possible to suppress a decrease in the timing margin of the circuit using the output clock signals (ICKO, QCKO) and to realize high-speed operation.

[0060] Next, a method for determining the correction code will be described with reference to FIGS. 7 to 9B. FIG. 7 is a diagram showing a configuration example of a phase interpolation circuit including a skew correction circuit according to the first embodiment. In FIG. 7, the phase interpolation circuit 701 generates output clock signals ICKO and QCKO having phases according to the input PI code based on the input clock signals ICKI and QCKI, respectively. The phase interpolation circuit 701 includes a phase interpolation circuit 702 that generates the first output clock signal ICKO and a phase interpolation circuit 703 that generates the second output clock signal QCKO. The phase interpolation circuits 702 and 703 are configured as shown in FIGS. 1 to 2C, and generate the output clock signals ICKO and QCKO, respectively, by weighting and synthesizing the input clock signals ICKI and QCKI based on the PI code. Note that the input clock signals ICKI and QCKI and the output clock signals ICKO and QCKO are each composed of a pair of complementary signals including a non-inverted signal (ICKIP, QCKIP, ICKOP, QCKOP) and an inverted signal (ICKIN, QCKIN, ICKON, QCKON).

[0061] Comparator 704 obtains data DT from the input signal using the first output clock signal ICKO (ICKOP, ICKON) output from the phase interpolation circuit 701. Comparator 705 obtains boundary BD from the input signal using the second output clock signal QCKO (QCKOP, QCKON) output from the phase interpolation circuit 701. One of the received signal DTIN or the internal data signal dataQ is input to the comparators 704 and 705 via the selector 708. Normally, the received signal DTIN is input to the comparators 704 and 705, and the internal data signal dataQ is input to the comparators 704 and 705 during the determination of the correction code (during the calibration operation).

[0062] The frequency division circuit 706 divides the second output clock signal QCKO (QCKOP, QCKON) output from the phase interpolation circuit 701 by two. The variable delay circuit 707 delays the output clock signal QCKOP among the second output clock signals QCKO frequency-divided by the frequency division circuit 706 and outputs it as the internal data signal dataQ. The internal data signal dataQ has a frequency that is half of the output clock signal QCKOP.

[0063] In the determination of the correction code, first, the PI code is set to 16. Thereby, the phase interpolation circuit 701 generates output clock signals ICKO and QCKO having phases (output phase 90 degrees) corresponding to the PI code based on the input clock signals ICKI and QCKI, respectively. Also, the selector 708 outputs the internal data signal dataQ, that is, the divided output clock signal QCKOP via the variable delay circuit 707. Then, the comparator 704 is used to perform edge detection of the internal data signal dataQ. At this time, based on the data DT obtained in the comparator 704 using the output clock signal ICKOP among the output clock signals ICKO and the data DT obtained in the comparator 704 using the output clock signal ICKON, for example, using the CDR circuit described later, it is determined whether the phases of the output clock signals ICKOP and ICKON are advanced or delayed with respect to the internal data signal dataQ, and the delay amount of the variable delay circuit 707 is adjusted so that, as shown in FIG. 8A, the rising edge of the output clock signal ICKOP converges to the edge of the internal data signal dataQ. During the period in which this PI code is set to 16, the correction code is maintained at 0 and no correction current is passed.

[0064] Next, set the PI code to 0. As a result, the phase interpolation circuit 701 generates output clock signals ICKO and QCKO having phases (output phase 0 degrees) corresponding to the PI code based on the input clock signals ICKI and QCKI, respectively. Also, the selector 708 outputs the internal data signal dataQ, that is, the divided output clock signal QCKOP via the variable delay circuit 707. Here, the delay amount of the variable delay circuit 707 is fixed to the delay amount when the PI code is set to 16 and the rising edge of the output clock signal ICKOP is converged to the edge of the internal data signal dataQ. Then, the edge of the internal data signal dataQ is detected using the comparator 704. At this time, based on the data DT obtained in the comparator 704 using the output clock signal ICKOP among the output clock signals ICKO and the data DT obtained in the comparator 704 using the output clock signal ICKON, for example, using a CDR circuit described later, it is determined whether the phases of the output clock signals ICKOP and ICKON are advanced or delayed with respect to the internal data signal dataQ, and the correction code is changed to adjust the amount of correction current, so that, as shown in FIG. 8B, the rising edge of the input clock signal ICKOP is converged to the edge of the internal data signal dataQ.

[0065] Since the phase relationship between the output clock signals ICKO and QCKO in the above operation is as shown in FIG. 9A, by applying half of the correction current amount when the PI code is set to 0 and the rising edge of the input clock signal ICKOP is converged to the edge of the internal data signal dataQ, as shown in FIG. 9B, the phase difference between the corrected output clock signals ICKO and QCKO becomes 90 degrees. Therefore, it is only necessary to determine the value that is half of the correction code when the PI code is set to 0 and the rising edge of the input clock signal ICKOP is converged to the edge of the internal data signal dataQ as the correction code used in the normal operation.

[0066] (Second Embodiment) Next, the second embodiment will be described. In the first embodiment, the current sources for the input clock signals ICKI (ICKIP, ICKIN) are transistors 113 and 123, and the current sources for the input clock signals QCKI (QCKIP, QCKIN) are transistors 133 and 143 in addition to transistors 134 and 144. That is, in the phase interpolation circuit according to the first embodiment, there are differences in the circuit configuration as a differential pair.

[0067] In the second embodiment, the current corresponding to the current control code PIB and the current corresponding to the correction code CAL and the current control code PIA are combined, and the voltage corresponding to the combined current is supplied to the gate of the transistor that functions as a current source. Thereby, it becomes possible to operate with one current source respectively, and the differential pair in the phase interpolation circuit has the same circuit configuration. As a result, the layout size of the differential pair can be reduced, and an increase in the capacitive load in the differential pair can be suppressed.

[0068] FIG. 10 is a diagram showing a configuration example of the phase interpolation circuit in the second embodiment. In FIG. 10, components having the same functions as those shown in FIG. 1 are denoted by the same reference numerals, and redundant descriptions are omitted. The phase interpolation circuit in the second embodiment includes resistors 101 and 102, and transistors 111 to 113, 121 to 123, 131 to 132, 141 to 142, 1031, and 1041. The transistors 111 to 113, 121 to 123, 131 to 132, 141 to 142, 1031, and 1041 are, for example, N-type MOSFETs.

[0069] The sources of transistor 131 and transistor 132 are commonly connected to the drain of transistor 1031. The source of transistor 1031 is grounded, and a gate voltage VGBP' is applied to the gate according to the PI code and the correction code. Transistor 1031 functions as a current source that supplies current to transistors 131 and 132 according to the PI code and the correction code.

[0070] The sources of transistor 141 and transistor 142 are commonly connected to the drain of transistor 1041. The source of transistor 1041 is grounded, and a gate voltage VGBN’ is applied to the gate according to the PI code and the correction code. Transistor 1041 functions as a current source that passes current to transistors 141 and 142 according to the PI code and the correction code.

[0071] In the example shown in FIG. 10, the transistors 131, 132, 141, 142 and transistors 1031, 1041 described above are an example of a second generation circuit that generates a second intermediate current with respect to the connection points with the resistors 101, 102 based on the second input clock signals QCKIP, QCKIN according to the PI code.

[0072] FIG. 11A is a diagram showing a configuration example of a gate voltage control circuit that controls the gate voltages VGAP and VGAN applied to the gates of the transistors 113 and 123 shown in FIG. 10. As shown in FIG. 11A, the gate voltage control circuit includes a current DAC 1101, a switch 1102, and transistors 1103 and 1104.

[0073] The current DAC 1101 outputs a current corresponding to the absolute value of the code value of the input current control code PIA. The switch 1102 is controlled according to the sign of the current control code PIA. When the current control code PIA is positive, the first terminal TMA1 and the second terminal TMB1 are connected. When the current control code PIA is negative, the first terminal TMA1 and the third terminal TMC1 are connected. The first terminal TMA1 of the switch 1102 is connected to the output terminal of the current DAC 1101.

[0074] Transistor 1103 is diode-connected between the second terminal TMB1 of switch 1102 and ground. That is, the drain and gate of transistor 1103 are connected to the second terminal TMB1 of switch 1102, and the source of transistor 1103 is grounded. Transistor 1104 is diode-connected between the third terminal TMC1 of switch 1102 and ground. That is, the drain and gate of transistor 1104 are connected to the third terminal TMC1 of switch 1102, and the source of transistor 1104 is grounded. The voltage generated by the diode-connected transistor 1103 is output as the gate voltage VGAP, and the voltage generated by the diode-connected transistor 1104 is output as the gate voltage VGAN.

[0075] FIG. 11B is a diagram showing a configuration example of a gate voltage control circuit that controls the gate voltages VGBP’ and VGBN’ applied to the gates of the transistors 1031 and 1041 shown in FIG. 10. As shown in FIG. 11B, the gate voltage control circuit includes current DACs 1111 and 1116, transistors 1112, 1113-i, 1118, 1119, and switches 1114-i, 1115, 1117.

[0076] The current DAC 1111 outputs a current corresponding to the absolute value of the code value of the input correction code CAL. The source of transistor 1112 is connected to the power supply VDD, and the drain and gate are connected to the output terminal of the current DAC 1111.

[0077] The source of transistor 1113-i is connected to the power supply VDD, and the gate is connected to the gate of transistor 1112 via switch 1114-i. If the corresponding switch 1114-i is in the conducting state (on state), transistors 1113-0 and 1113-1 are configured such that a mirror current of (1 / 16) times flows, and transistor 1113-2 is configured such that a mirror current of (2 / 16) times flows. Similarly, transistor 1113-3 is configured such that a mirror current of (4 / 16) times flows, and transistor 1113-4 is configured such that a mirror current of (8 / 16) times flows. Switch 1114-i is turned on / off controlled by a control signal CTL based on the current control code PIA so that the mirror ratio of the current mirror circuit composed of transistor 1112 and transistor 1113-i changes in proportion to the current control code PIA.

[0078] Switch 1115 is controlled according to the sign of the multiplication value of the correction code CAL and the current control code PIA. When the multiplication value of the correction code CAL and the current control code PIA is positive, the first terminal TMA2 and the second terminal TMB2 are connected. When the multiplication value of the correction code CAL and the current control code PIA is negative, the first terminal TMA2 and the third terminal TMC2 are connected. The drains of transistors 1113-i are commonly connected to the first terminal TMA2 of switch 1115.

[0079] Current DAC 1116 outputs a current according to the absolute value of the code value of the input current control code PIB. Switch 1117 is controlled according to the sign of the current control code PIB. When the current control code PIB is positive, the first terminal TMA3 and the second terminal TMB3 are connected. When the current control code PIB is negative, the first terminal TMA3 and the third terminal TMC3 are connected. The first terminal TMA3 of switch 1117 is connected to the output terminal of current DAC 1116.

[0080] The second terminal TMB2 of switch 1115 and the second terminal TMB3 of switch 1117 are connected. The third terminal TMC2 of switch 1115 and the third terminal TMC3 of switch 1117 are connected.

[0081] Transistor 1118 is diode-connected between the connection point of the second terminal TMB2 of switch 1115 and the second terminal TMB3 of switch 1117 and ground. That is, the drain and gate of transistor 1118 are connected to the connection point of the second terminal TMB2 of switch 1115 and the second terminal TMB3 of switch 1117, and the source of transistor 1118 is grounded. Transistor 1119 is diode-connected between the connection point of the third terminal TMC2 of switch 1115 and the third terminal TMC3 of switch 1117 and ground. That is, the drain and gate of transistor 1119 are connected to the connection point of the third terminal TMC2 of switch 1115 and the third terminal TMC3 of switch 1117, and the source of transistor 1119 is grounded.

[0082] With such a configuration, the current corresponding to the correction code CAL and the current control code PIA and the current corresponding to the current control code PIB are combined at the connection point of the second terminal TMB2 of switch 1115 and the second terminal TMB3 of switch 1117, and the voltage generated by the diode-connected transistor 1118 based on the combined current is output as the gate voltage VGBP'. Also, the current corresponding to the correction code CAL and the current control code PIA and the current corresponding to the current control code PIB are combined at the connection point of the third terminal TMC2 of switch 1115 and the third terminal TMC3 of switch 1117, and the voltage generated by the diode-connected transistor 1119 based on the combined current is output as the gate voltage VGBN'.

[0083] In the example shown in FIG. 10, the transistors 1031 and 1041 described above and the gate voltage control circuit shown in FIG. 11B are an example of a correction circuit that corrects at least one of the first intermediate current and the second intermediate current based on the correction current corresponding to the correction code.

[0084] Also in the second embodiment, based on the correction current according to the correction code and the PI code, the amount of the intermediate current output from the transistors 131, 132, 141, and 142 is corrected, and the phase of the output clock signal obtained by synthesizing the intermediate currents is adjusted. Thereby, the phase interpolation circuit adjusts the phase difference between the output clock signals (ICKO, QCKO) to a predetermined phase difference (90 degrees), and can suppress the deviation of the phase difference in the output clock signals (ICKO, QCKO). Therefore, it is possible to suppress the reduction of the timing margin of the circuit using the output clock signals (ICKO, QCKO) and to realize high-speed operation.

[0085] (Third Embodiment) Next, the third embodiment will be described. The configuration of the phase interpolation circuit in the third embodiment is the same as the configuration of the phase interpolation circuit in the second embodiment shown in FIG. 10. Also in the third embodiment, the configuration of the gate voltage control circuit that controls the gate voltages VGAP and VGAN applied to the gates of the transistors 113 and 123 shown in FIG. 10 is the same as that of the second embodiment shown in FIG. 11A. The third embodiment is different from the above-described second embodiment in that the gate voltage control circuit that controls the gate voltages VGBP' and VGBN' applied to the gates of the transistors 1031 and 1041 shown in FIG. 10. Hereinafter, the gate voltage control circuit that controls the gate voltages VGBP' and VGBN' in the third embodiment will be described.

[0086] FIG. 12A is a diagram showing a configuration example of a gate voltage control circuit that controls the gate voltages VGBP' and VGBN' applied to the gates of the transistors 1031 and 1041. As shown in FIG. 12A, the gate voltage control circuit includes current DACs 1201 and 1203, switches 1202 and 1204, and transistors 1205 and 1206.

[0087] The current DAC 1201 outputs a current corresponding to the absolute value of the code value of the input correction code CAL'. Here, the correction code CAL' is a code value calculated based on the correction code CAL and the current control code PIA. The correction code CAL' is a value obtained by multiplying the correction code CAL by a ratio corresponding to the current control code PIA, for example, the ratio of the current value of the current control code PIA corresponding to the PI code to its maximum value (corresponding to the mirror ratio in the current mirror circuit shown in FIG. 11B). The correction code CAL' is, for example, the value shown as the "Q correction current: CAL'" code in FIG. 12C. The multiplication of the ratio corresponding to the current control code PIA for the correction code CAL may be performed by, for example, a logic circuit (not shown). Also, in this embodiment, since the correction code CAL' can take a fractional value, the current DAC 1201 is preferably a current DAC with high resolution.

[0088] The switch 1202 is controlled according to the sign of the correction code CAL'. When the correction code CAL' is positive, it connects the first terminal TMA4 and the second terminal TMB4, and when the correction code CAL' is negative, it connects the first terminal TMA4 and the third terminal TMC4. The first terminal TMA4 of the switch 1202 is connected to the output terminal of the current DAC 1201.

[0089] The current DAC 1203 outputs a current corresponding to the absolute value of the code value of the input current control code PIB. The switch 1204 is controlled according to the sign of the current control code PIB. When the current control code PIB is positive, it connects the first terminal TMA5 and the second terminal TMB5, and when the current control code PIB is negative, it connects the first terminal TMA5 and the third terminal TMC5. The first terminal TMA5 of the switch 1204 is connected to the output terminal of the current DAC 1203.

[0090] The second terminal TMB4 of the switch 1202 and the second terminal TMB5 of the switch 1204 are connected. The third terminal TMC4 of the switch 1202 and the third terminal TMC5 of the switch 1204 are connected.

[0091] Transistor 1205 is diode-connected between the connection point of the second terminal TMB4 of switch 1202 and the second terminal TMB5 of switch 1204 and ground. That is, the drain and gate of transistor 1205 are connected to the connection point of the second terminal TMB4 of switch 1202 and the second terminal TMB5 of switch 1204, and the source of transistor 1205 is grounded. Transistor 1206 is diode-connected between the connection point of the third terminal TMC4 of switch 1202 and the third terminal TMC5 of switch 1204 and ground. That is, the drain and gate of transistor 1206 are connected to the connection point of the third terminal TMC4 of switch 1202 and the third terminal TMC5 of switch 1204, and the source of transistor 1206 is grounded.

[0092] With such a configuration, the current corresponding to the correction code CAL' based on the correction code CAL and the current control code PIA and the current corresponding to the current control code PIB are combined at the connection point of the second terminal TMB4 of switch 1202 and the second terminal TMB5 of switch 1204, and the voltage generated by the diode-connected transistor 1205 based on the combined current is output as the gate voltage VGBP'. Also, the current corresponding to the correction code CAL' based on the correction code CAL and the current control code PIA and the current corresponding to the current control code PIB are combined at the connection point of the third terminal TMC4 of switch 1202 and the third terminal TMC5 of switch 1204, and the voltage generated by the diode-connected transistor 1206 based on the combined current is output as the gate voltage VGBN'.

[0093] In the example shown in FIG. 10, the transistors 1031 and 1041 described above and the gate voltage control circuit shown in FIG. 12A are an example of a correction circuit that corrects at least one of the first intermediate current and the second intermediate current based on the correction current corresponding to the correction code.

[0094] Even when the gate voltage control circuit shown in FIG. 12A is applied, the amount of the intermediate current output from the transistors 131, 132, 141, and 142 is corrected according to the correction code and the PI code, and the phase of the output clock signal obtained by synthesizing the intermediate currents is adjusted. Thereby, the phase interpolation circuit can adjust the phase difference between the output clock signals (ICKO, QCKO) to a predetermined phase difference (90 degrees), and suppress the deviation of the phase difference in the output clock signals (ICKO, QCKO).

[0095] FIG. 12B is a diagram showing another configuration example of a gate voltage control circuit that controls the gate voltages VGBP' and VGBN' applied to the gates of the transistors 1031 and 1041. As shown in FIG. 12B, the gate voltage control circuit includes a current DAC 1211, a switch 1212, and transistors 1213 and 1214.

[0096] The current DAC 1211 outputs a current corresponding to the absolute value of the code value of the input current control code PIB'. Here, the current control code PIB' is a code value obtained by adding the current control code PIB and the correction code CAL' described above. That is, the current control code PIB' is a value obtained by multiplying the correction code CAL by a ratio corresponding to the current control code PIA, for example, the ratio of the current value of the current control code PIA corresponding to the PI code to its maximum value, and adding the value of the current control code PIB. The current control code PIB' is, for example, the value shown as the code of "Q correction current: PIB'" in FIG. 12C. Note that the calculation of the current control code PIB' may be performed by a logic circuit (not shown), for example. Also, in the present embodiment, since the current control code PIB' can take a fractional value, the current DAC 1211 is preferably a current DAC with high resolution.

[0097] Switch 1212 is controlled according to the sign of the current control code PIB'. When the current control code PIB' is positive, it connects the first terminal TMA6 and the second terminal TMB6. When the current control code PIB' is negative, it connects the first terminal TMA6 and the third terminal TMC6. The first terminal TMA6 of switch 1212 is connected to the output terminal of current DAC1211.

[0098] Transistor 1213 is diode-connected between the second terminal TMB6 of switch 1212 and ground. That is, the drain and gate of transistor 1213 are connected to the second terminal TMB6 of switch 1212, and the source of transistor 1213 is grounded. Transistor 1214 is diode-connected between the third terminal TMC6 of switch 1212 and ground. That is, the drain and gate of transistor 1214 are connected to the third terminal TMC6 of switch 1212, and the source of transistor 1214 is grounded.

[0099] With such a configuration, when the current control code PIB' is positive, based on the current corresponding to the current control code PIB', the voltage generated by the diode-connected transistor 1213 is output as the gate voltage VGBP'. Also, when the current control code PIB' is negative, based on the current corresponding to the current control code PIB', the voltage generated by the diode-connected transistor 1214 is output as the gate voltage VGBN'.

[0100] In the example shown in FIG. 10, the transistors 1031 and 1041 described above and the gate voltage control circuit shown in FIG. 12B are an example of a correction circuit that corrects the current amount of at least one of the first intermediate current and the second intermediate current based on the correction current corresponding to the correction code.

[0101] Even when the gate voltage control circuit shown in FIG. 12B is applied, the amount of the intermediate current output from the transistors 131, 132, 141, and 142 is corrected according to the correction code and the PI code, and the phase of the output clock signal obtained by synthesizing the intermediate currents is adjusted. As a result, the phase interpolation circuit can adjust the phase difference between the output clock signals (ICKO, QCKO) to a predetermined phase difference (90 degrees) and suppress the deviation of the phase difference in the output clock signals (ICKO, QCKO).

[0102] In the first to third embodiments described above, a correction current is caused to flow through the differential pair to which the second input clock signal QCKI (QCKIP, QCKIN) is input. However, the present invention is not limited to this, and a correction current may be caused to flow through the differential pair to which the first input clock signal ICKI (ICKIP, ICKIN) is input.

[0103] In the phase interpolation circuit in each of the above-described embodiments, like the currents I_A and I_B indicated by the solid lines 401 and 402 in FIG. 4A, the sum (absolute value sum) of the currents according to the PI code (current control codes PIA and PIB) is constant regardless of the PI code. However, since a correction current according to the correction code CAL is added, the sum (absolute value sum) of the currents changes depending on the PI code. Therefore, when the correction current increases, the common mode voltage in the output from the output terminals OUTP and OUTN of the phase interpolation circuit may deviate due to the influence of the correction current.

[0104] Hereinafter, a phase interpolation circuit having a common mode voltage correction circuit that suppresses fluctuations in the common mode voltage will be described so that the sum of the currents flowing through the phase interpolation circuit is constant and the common mode voltage at the output of the phase interpolation circuit is constant even when the correction current changes.

[0105] (Fourth Embodiment) FIG. 20 is a diagram showing a configuration example of a phase interpolation circuit in the fourth embodiment. In FIG. 20, components having the same functions as those shown in FIGS. 1 and 2C are denoted by the same reference numerals, and redundant descriptions are omitted. The phase interpolation circuit in the fourth embodiment shown in FIG. 20 is an example in which a common mode voltage correction circuit is provided in the phase interpolation circuit corresponding to the first embodiment described above. Note that a gate voltage control circuit for controlling the gate voltages VGAP and VGAN applied to the gates of the transistors 113 and 123, and a gate voltage control circuit for controlling the gate voltages VGBP and VGBN applied to the gates of the transistors 133 and 143 are not shown, but are the same as those in the first embodiment.

[0106] In the phase interpolation circuit in the fourth embodiment, the common mode voltage correction circuit includes a current source 2001 and transistors 2002 to 2008. The transistors 2002 to 2004 and 2007 to 2008 are, for example, N-type MOSFETs, and the transistors 2005 and 2006 are, for example, P-type MOSFETs.

[0107] The current source 2001 is a current source that passes a predetermined current Imax. The current Imax is, for example, the maximum value of the correction current flowing through the phase interpolation circuit, that is, a current corresponding to the absolute value of the code value of the correction code CAL. The source of the transistor 2002 is grounded, and the drain and gate are connected to the current source 2001. The source of the transistor 2003 is grounded, and the gate is connected to the gate of the transistor 2002. The transistors 2002 and 2003 form a current mirror circuit, and are configured such that a current Imax flows through the transistor 2003.

[0108] The source of transistor 2004 is grounded, and the gate is connected to the gate of transistor 224 that the gate voltage control circuit for controlling gate voltages VGCP and VGCN has. Transistor 2004 and transistor 224 constitute a current mirror circuit, and are configured such that a current Ical flows through transistor 2004. Here, in the present embodiment, the current Ical is a current (|C|) that is k times the current (|C0|) corresponding to the absolute value of the code value of correction code CAL according to current control code PIA, that is, a correction current.

[0109] The source of transistor 2005 is connected to power supply VDD, and the drain and gate are connected to the drain of transistor 2004. The source of transistor 2006 is connected to power supply VDD, and the gate is connected to the gate of transistor 2005. Transistor 2005 and transistor 2006 constitute a current mirror circuit. Therefore, a current Ical flows through transistor 2006.

[0110] The sources of transistor 2007 and transistor 2008 are commonly connected to the drain of transistor 2003 and the drain of transistor 2006. The drain of transistor 2007 is connected to output terminal OUTP, and the drain of transistor 2008 is connected to output terminal OUTN. A voltage CMVI is applied to the gates of transistor 2007 and transistor 2008. The voltage CMVI is, for example, a voltage equal to the common mode voltage of input clock signals ICKI (ICKIP, ICKIN), QCKI (QCKIP, QCKIN).

[0111] In order to correct the amount of the intermediate current output from the transistors 131, 132, 141, and 142, when a correction current corresponding to a correction code and a PI code flows in a gate voltage control circuit that controls the gate voltages VGCP and VGCN, a current mirror circuit composed of a transistor 224 and a transistor 2004 and a current mirror circuit composed of a transistor 2005 and a transistor 2006 cause a current Ical equal to the correction current corresponding to the correction code and the PI code to flow through the transistor 2006. Also, a current Imax flows through the transistor 2003 due to a current mirror circuit composed of a transistor 2002 and a transistor 2003. Therefore, a differential pair composed of a transistor 2007 and a transistor 2008, whose sources are commonly connected to the drains of the transistor 2003 and the transistor 2006, can supply a current of (Imax - Ical) to the phase interpolation circuit. As a result, by subtracting a current Ical equal to the correction current by the transistor 2006, it becomes possible to maintain the amount of current at the output terminals OUTP and OUTN constant even when the correction current changes, and it is possible to suppress fluctuations in the common mode voltage according to the correction current.

[0112] (Fifth Embodiment) FIG. 21 is a diagram showing a configuration example of a phase interpolation circuit in the fifth embodiment. In FIG. 21, components having the same functions as the components shown in FIGS. 10, 11A, and 11B are denoted by the same reference numerals, and redundant descriptions are omitted. The phase interpolation circuit in the fifth embodiment shown in FIG. 21 is an example in which a common mode voltage correction circuit is provided in the phase interpolation circuit corresponding to the second embodiment described above.

[0113] In the phase interpolation circuit in the fifth embodiment, the common mode voltage correction circuit includes a current source 2101 and transistors 2102 to 2111. The transistors 2102 to 2105, 2108 to 2111 are, for example, N-type MOSFETs, and the transistors 2106 and 2107 are, for example, P-type MOSFETs.

[0114] The current source 2101 is a current source that conducts a predetermined current Imax. The current Imax corresponds to, for example, the sum of the maximum current flowing through the phase interpolation circuit, the maximum current corresponding to the current control code PIA, the maximum current corresponding to the current control code PIB, and the maximum correction current. The source of the transistor 2102 is grounded, and the drain and gate are connected to the current source 2101. The source of the transistor 2103 is grounded, and the gate is connected to the gate of the transistor 2102. The transistors 2102 and 2103 form a current mirror circuit and are configured such that a current Imax flows through the transistor 2103.

[0115] The source of the transistor 2104 is grounded, and the gate is connected to the connection point between the second terminal TMB2 of the switch 1115 and the second terminal TMB3 of the switch 1117 in the gate voltage control circuit. The source of the transistor 2105 is grounded, and the gate is connected to the connection point between the third terminal TMC2 of the switch 1115 and the third terminal TMC3 of the switch 1117 in the gate voltage control circuit. The source of the transistor 2110 is grounded, and the gate is connected to the second terminal TMB1 of the switch 1102 in the gate voltage control circuit. The source of the transistor 2111 is grounded, and the gate is connected to the third terminal TMC1 of the switch 1102 in the gate voltage control circuit.

[0116] The source of the transistor 2106 is connected to the power supply VDD, and the drain and gate are connected to the drains of the transistors 2104, 2105, 2110, and 2111. Therefore, a current Ical' equal to the combined current of the current corresponding to the current control code PIA, the current corresponding to the current control code PIB, the correction code CAL, and the current corresponding to the current control code PIA flows through the transistor 2106. The source of the transistor 2107 is connected to the power supply VDD, and the gate is connected to the gate of the transistor 2106. The transistors 2106 and 2107 form a current mirror circuit. Therefore, the current Ical' flows through the transistor 2107.

[0117] The sources of transistor 2108 and transistor 2109 are commonly connected to the drains of transistor 2103 and transistor 2107. The drain of transistor 2108 is connected to output terminal OUTP, and the drain of transistor 2109 is connected to output terminal OUTN. Voltage CMVI is applied to the gates of transistor 2108 and transistor 2109. Voltage CMVI is, for example, a voltage equal to the common mode voltage of input clock signals ICKI (ICKIP, ICKIN), QCKI (QCKIP, QCKIN).

[0118] When a correction current corresponding to a correction code and a PI code for correcting the amount of the intermediate current output from transistors 131, 132, 141, 142 flows in a gate voltage control circuit that controls gate voltages VGBP’ and VGBN’, a current Ical’ equal to the combined current of the current corresponding to current control code PIA, the current corresponding to current control code PIB, the correction code CAL, and the correction current corresponding to current control code PIA flows through transistor 2107. Also, a current Imax flows through transistor 2103 due to a current mirror circuit composed of transistor 2102 and transistor 2103. Therefore, a differential pair composed of transistor 2108 and transistor 2109, whose sources are commonly connected to the drains of transistor 2103 and transistor 2107, can cause a current of (Imax - Ical’) to flow through the phase interpolation circuit. Here, current Ical’ is equal to the sum of the current corresponding to current control code PIA, the current corresponding to current control code PIB, the correction code CAL, and the correction current corresponding to current control code PIA. Also, the sum of the current corresponding to current control code PIA and the current corresponding to current control code PIB is constant. Therefore, by drawing current Ical’ including a current equal to the correction current through transistor 2107, it is possible to keep the amount of current at output terminals OUTP and OUTN constant even when the correction current changes, and it is possible to suppress fluctuations in the common mode voltage according to the correction current.

[0119] (Sixth Embodiment) FIG. 22 is a diagram showing a configuration example of a phase interpolation circuit according to the sixth embodiment. In FIG. 22, components having the same functions as those shown in FIGS. 10, 11A, and 12A are denoted by the same reference numerals, and redundant descriptions are omitted. The phase interpolation circuit according to the sixth embodiment shown in FIG. 22 is an example in which a common mode voltage correction circuit is provided in the phase interpolation circuit corresponding to the third embodiment to which the gate voltage control circuit shown in FIG. 12A is applied.

[0120] In the phase interpolation circuit according to the sixth embodiment shown in FIG. 22, the common mode voltage correction circuit includes a current source 2201 and transistors 2202 to 2211. The transistors 2202 to 2205 and 2208 to 2211 are, for example, N-type MOSFETs, and the transistors 2206 and 2207 are, for example, P-type MOSFETs.

[0121] The current source 2201 is a current source that passes a predetermined current Imax. The current Imax is, for example, a current corresponding to the sum of the maximum value of the current flowing through the phase interpolation circuit according to the current control code PIA, the maximum value of the current according to the current control code PIB, and the maximum value of the correction current. The source of the transistor 2202 is grounded, and the drain and gate are connected to the current source 2201. The source of the transistor 2203 is grounded, and the gate is connected to the gate of the transistor 2202. The transistors 2202 and 2203 form a current mirror circuit, and are configured such that the current Imax flows through the transistor 2203.

[0122] The source of transistor 2204 is grounded, and its gate is connected to the connection point between the second terminal TMB4 of switch 1202 and the second terminal TMB5 of switch 1204 in the gate voltage control circuit. The source of transistor 2205 is grounded, and its gate is connected to the connection point between the third terminal TMC4 of switch 1202 and the third terminal TMC5 of switch 1204 in the gate voltage control circuit. The source of transistor 2210 is grounded, and its gate is connected to the second terminal TMB1 of switch 1102 in the gate voltage control circuit. The source of transistor 2211 is grounded, and its gate is connected to the third terminal TMC1 of switch 1102 in the gate voltage control circuit.

[0123] The source of transistor 2206 is connected to power supply VDD, and its drain and gate are connected to the drains of transistor 2204, transistor 2205, transistor 2210, and transistor 2211. Therefore, a current Ical' equal to the combined current of the current corresponding to current control code PIA, the current corresponding to current control code PIB, and the current corresponding to correction code CAL' flows through transistor 2206. Here, correction code CAL' is a code value calculated based on correction code CAL and current control code PIA as described above. The source of transistor 2207 is connected to power supply VDD, and its gate is connected to the gate of transistor 2206. Transistor 2206 and transistor 2207 form a current mirror circuit. Therefore, current Ical' flows through transistor 2207.

[0124] The sources of transistor 2208 and transistor 2209 are commonly connected to the drains of transistor 2203 and transistor 2207. The drain of transistor 2208 is connected to output terminal OUTP, and the drain of transistor 2209 is connected to output terminal OUTN. Voltage CMVI is applied to the gates of transistor 2208 and transistor 2209. Voltage CMVI is, for example, a voltage equal to the common mode voltage of input clock signals ICKI (ICKIP, ICKIN), QCKI (QCKIP, QCKIN).

[0125] When a correction current corresponding to a correction code CAL’ for correcting the amount of the intermediate current output from the transistors 131, 132, 141, and 142 flows in a gate voltage control circuit that controls the gate voltages VGBP’ and VGBN’, a current Ical’ equal to the combined current of the current corresponding to the current control code PIA, the current corresponding to the current control code PIB, and the correction current corresponding to the correction code CAL’ flows through the transistor 2207. Also, a current Imax flows through the transistor 2203 by a current mirror circuit composed of the transistors 2202 and 2203. Therefore, a differential pair composed of the transistors 2208 and 2209, whose sources are commonly connected to the drains of the transistor 2203 and the transistor 2207, can flow a current of (Imax - Ical’) to the phase interpolation circuit. Here, the current Ical’ is equal to the sum of the current corresponding to the current control code PIA, the current corresponding to the current control code PIB, and the correction code CAL’, that is, the correction current corresponding to the correction code CAL and the current control code PIA. Also, the sum of the current corresponding to the current control code PIA and the current corresponding to the current control code PIB is constant. Therefore, by drawing the current Ical’ including the current equal to the correction current through the transistor 2207, it becomes possible to maintain the amount of current at the output terminals OUTP and OUTN constant even if the correction current changes, and it is possible to suppress fluctuations in the common mode voltage according to the correction current.

[0126] FIG. 23 is a diagram showing another configuration example of the phase interpolation circuit in the sixth embodiment. In FIG. 23, components having the same functions as the components shown in FIGS. 10, 11A, and 12B are denoted by the same reference numerals, and redundant descriptions are omitted. The phase interpolation circuit in the sixth embodiment shown in FIG. 23 is an example in which a common mode voltage correction circuit is provided in the phase interpolation circuit corresponding to the third embodiment to which the gate voltage control circuit shown in FIG. 12B is applied.

[0127] In the phase interpolation circuit according to the sixth embodiment shown in FIG. 23, the common mode voltage correction circuit includes a current source 2301 and transistors 2302 to 2309, 2311 to 2312. The transistors 2302 to 2305, 2308 to 2309, 2311 to 2312 are, for example, N-type MOSFETs, and the transistors 2306, 2307 are, for example, P-type MOSFETs.

[0128] The current source 2301 is a current source that supplies a predetermined current Imax. The current Imax is, for example, the maximum value of the current flowing through the phase interpolation circuit according to the current control code PIA and the maximum value of the current according to the current control code PIB'. Here, the current control code PIB' is a code value obtained by adding the current control code PIB and the correction code CAL' as described above. The source of the transistor 2302 is grounded, and the drain and gate are connected to the current source 2301. The source of the transistor 2303 is grounded, and the gate is connected to the gate of the transistor 2302. The transistors 2302 and 2303 form a current mirror circuit, and are configured such that a current Imax flows through the transistor 2303.

[0129] The source of the transistor 2304 is grounded, and the gate is connected to the second terminal TMB6 of the switch 1212 included in the gate voltage control circuit. The source of the transistor 2305 is grounded, and the gate is connected to the third terminal TMC6 of the switch 1212 included in the gate voltage control circuit. The source of the transistor 2311 is grounded, and the gate is connected to the second terminal TMB1 of the switch 1102 included in the gate voltage control circuit. The source of the transistor 2312 is grounded, and the gate is connected to the third terminal TMC1 of the switch 1102 included in the gate voltage control circuit.

[0130] The source of transistor 2306 is connected to power supply VDD, and the drain and gate are connected to the drains of transistor 2304, transistor 2305, transistor 2311, and transistor 2312. Therefore, a current Ical' equal to the combined current of the current according to current control code PIA and the current according to current control code PIB' flows through transistor 2306. The source of transistor 2307 is connected to power supply VDD, and the gate is connected to the gate of transistor 2306. Transistor 2306 and transistor 2307 form a current mirror circuit. Therefore, current Ical' flows through transistor 2307.

[0131] The sources of transistor 2308 and transistor 2309 are commonly connected to the drains of transistor 2303 and transistor 2307. The drain of transistor 2308 is connected to output terminal OUTP, and the drain of transistor 2309 is connected to output terminal OUTN. Voltage CMVI is applied to the gates of transistor 2308 and transistor 2309. Voltage CMVI is, for example, a voltage equal to the common mode voltage of input clock signals ICKI (ICKIP, ICKIN), QCKI (QCKIP, QCKIN).

[0132] When a current corresponding to a current control code PIB’ including a correction current for correcting the amount of the intermediate current output from transistors 131, 132, 141, and 142 flows in a gate voltage control circuit that controls gate voltages VGBP’ and VGBN’, a current Ical’ equal to the combined current of the current corresponding to the current control code PIA and the current corresponding to the current control code PIB’ flows through transistor 2307. Also, a current Imax flows through transistor 2303 due to a current mirror circuit composed of transistors 2302 and 2303. Therefore, a differential pair composed of transistors 2308 and 2309, whose sources are commonly connected to the drains of transistor 2303 and transistor 2307, can pass a current of (Imax - Ical’) to the phase interpolation circuit. Here, the current Ical’ is equal to the sum of the current corresponding to the current control code PIA and the current corresponding to the current control code PIB’. Also, the current control code PIB’ is a code value obtained by adding the current control code PIB and a correction code CAL’, and the sum of the current corresponding to the current control code PIA and the current corresponding to the current control code PIB is constant. Therefore, by subtracting the current Ical’ including a current equal to the correction current by transistor 2307, it becomes possible to keep the amount of current at the output terminals OUTP and OUTN constant even if the correction current changes, and it is possible to suppress fluctuations in the common mode voltage according to the correction current.

[0133] (Other Embodiments of the Present Invention) FIG. 13A is a diagram showing a configuration example of a semiconductor integrated circuit in the present embodiment. The semiconductor integrated circuit 1301 in the present embodiment includes a reception circuit 1302 having a function of a deserialization circuit that converts an input serial signal into a parallel signal, and an internal circuit 1321 such as a logic circuit that receives the parallel signal (data) from the reception circuit 1302 and performs a processing operation.

[0134] The receiving circuit 1302 includes a PLL (Phase Locked Loop) circuit 1303, a phase interpolation circuit 1304, an equalizer circuit (CTLE: Continuous Time Linear Equalizer) 1307, a selector 1308, comparators 1309 and 1311, demultiplexer circuits 1310 and 1312, a digital processing circuit 1313, frequency division circuits 1318 and 1319, a variable delay circuit 1317, and a resistor 1316.

[0135] Based on the input reference clock signal REFCK, the PLL circuit 1303 generates and outputs a clock signal to be supplied to each circuit within the semiconductor integrated circuit. For example, based on the input reference clock signal REFCK, the PLL circuit 1303 generates and outputs a first input clock signal ICKI (ICKIP, ICKIN) and a second input clock signal QCKI (QCKIP, QCKIN) having a predetermined phase difference from the first input clock signal ICKI.

[0136] Based on the input clock signals ICKI and QCKI, the phase interpolation circuit 1304 generates and outputs output clock signals ICKO and QCKO having phases corresponding to the input PI code. The phase interpolation circuit 1304 includes a phase interpolation circuit 1305 that generates the first output clock signal ICKO and a phase interpolation circuit 1306 that generates the second output clock signal QCKO. The phase interpolation circuits 1305 and 1306 are the phase interpolation circuits in the first to sixth embodiments described above, and generate the output clock signals ICKO and QCKO respectively by weighting and synthesizing the input clock signals ICKI and QCKI based on the PI code.

[0137] The equalizer circuit 1307 receives an input serial signal Input transmitted via a transmission line or the like. The selector 1308 outputs either the input serial signal Input received by the equalizer circuit 1307 or the internal data signal dataQ to the comparators 1309 and 1311 according to the control signal SEL. Normally, the input serial signal Input received by the equalizer circuit 1307 is output from the selector 1308, and the internal data signal dataQ is output from the selector 1308 at the time of determining the correction code (during the calibration operation) or the like.

[0138] The comparator 1309 acquires data DT from the input signal using the first output clock signal ICKO output from the phase interpolation circuit 1304. The demultiplexer circuit 1310 performs serial-to-parallel conversion on the output of the comparator 1309 based on the clock obtained by dividing the first output clock signal ICKO output from the phase interpolation circuit 1304 by the divider circuit 1319, and outputs a parallel data signal.

[0139] The comparator 1311 acquires a boundary BD from the input signal using the second output clock signal QCKO output from the phase interpolation circuit 1304. The demultiplexer circuit 1312 performs serial-to-parallel conversion on the output of the comparator 1311 based on the clock obtained by dividing the first output clock signal ICKO output from the phase interpolation circuit 1304 by the divider circuit 1319, and outputs a parallel boundary signal.

[0140] Note that the demultiplexer circuits 1310 and 1312 may perform serial-to-parallel conversion on the outputs of the comparators 1309 and 1311 based on the clock obtained by dividing the second output clock signal QCKO instead of the clock obtained by dividing the first output clock signal ICKO.

[0141] The digital processing circuit 1313 generates and outputs a received data signal RXOUT and a received clock signal RXCLK based on the data signal DT and the boundary signal BD output from the demultiplexer circuits 1310 and 1312. The received data signal RXOUT output from the receiving circuit 1302 is taken into the internal circuit 1321 by a flip-flop 1322 operating with the received clock signal RXCLK and processed.

[0142] Also, the digital processing circuit 1313 includes a calibration control circuit 1314 and a CDR circuit 1315. The calibration control circuit 1314 performs control related to the calibration operation for determining the correction code.

[0143] The CDR circuit 1315 appropriately controls the phases of the output clock signals ICKO and QCKO output from the phase interpolation circuit 1304 based on the signals received from the demultiplexer circuits 1310 and 1312. As shown in FIG. 15, the CDR circuit 1315 determines whether the phases of the output clock signals ICKO and QCKO output from the phase interpolation circuit 1304 are advanced or delayed with respect to the input serial signal DTIN based on the data signal DT and the boundary signal BD output from the demultiplexer circuits 1310 and 1312. Further, the CDR circuit 1315 generates and outputs a PI code for advancing or delaying the phases of the output clock signals ICKO and QCKO according to the determination result.

[0144] The frequency division circuit 1318 divides the second output clock signal QCKO output from the phase interpolation circuit 1304 by two. The variable delay circuit 1317 delays the second output clock signal QCKO divided by the frequency division circuit 1318 and outputs it as an internal data signal dataQ. The configuration of the variable delay circuit 1317 is not particularly limited, and any delay circuit capable of changing the delay amount can be applied. For example, as shown in FIG. 13B, the variable delay circuit 1317 may cascade-connect unit delay circuits 1331 (1331-1, 1331-2, 1331-3, 1331-4) each composed of an inverter circuit, a resistor, and a capacitor, and select and output one from the outputs of the unit delay circuits 1331 by a selection circuit 1332.

[0145] In the receiving circuit 1302 of the semiconductor integrated circuit 1301 shown in FIG. 13A, the internal data signal dataQ is generated by the frequency division circuit 1318 and the variable delay circuit 1317 using the second output clock signal QCKO output from the phase interpolation circuit 1304. However, it is not limited to this. For example, as shown in FIG. 14, the internal data signal dataQ may be generated by the phase interpolation circuit 1401 and the frequency division circuit 1402 using the second input clock signal QCKI output from the PLL circuit 1303. Alternatively, the internal data signal dataQ may be generated using a DLL circuit.

[0146] FIG. 14 is a diagram showing a configuration example of a semiconductor integrated circuit according to the present embodiment. In FIG. 14, components having the same functions as those shown in FIG. 13A are denoted by the same reference numerals, and redundant descriptions are omitted. The phase interpolation circuit 1401 generates and outputs a clock signal equivalent to the output clock signal QCKO with an adjusted output phase, that is, an adjusted delay amount, based on the second input clock signal QCKI output from the PLL circuit 1303. The frequency division circuit 1402 divides the clock signal output from the phase interpolation circuit 1401 by two and outputs it as an internal data signal dataQ.

[0147] Moreover, each of the above embodiments merely shows an example of the implementation of the present invention, and the technical scope of the present invention should not be construed in a limited manner by these. That is, the present invention can be implemented in various forms without departing from its technical idea or its main features.

Industrial Applicability

[0148] According to the present invention, it is possible to provide a phase interpolation circuit that generates an output clock signal with suppressed phase shift with respect to the phase interpolation code.

Claims

1. A phase interpolation circuit that generates a differential output clock signal having a phase corresponding to a first current control code and a second current control code based on a first differential input clock signal and a second differential input clock signal having a first phase difference, comprising: a first generation circuit that generates a first differential intermediate current based on the first differential input clock signal according to the first current control code; a second generation circuit that generates a second differential intermediate current based on the second differential input clock signal according to the second current control code; a synthesis circuit that synthesizes the first differential intermediate current and the second differential intermediate current to generate the differential output clock signal; a correction circuit that corrects at least one of the first differential intermediate current and the second differential intermediate current based on a correction current generated according to a correction code set such that the first differential intermediate current and the second differential intermediate current cause a variation in a common mode voltage in the differential output clock signal; and a common mode voltage correction circuit that corrects the common mode voltage in the differential output clock signal according to the variation. A phase interpolation circuit characterized by comprising the above.

2. The phase interpolation circuit according to claim 1, wherein the common mode voltage correction circuit suppresses a variation in the common mode voltage according to the correction current.

3. The phase interpolation circuit according to claim 2, wherein the common mode voltage correction circuit makes the sum of currents flowing through the phase interpolation circuit constant regardless of the correction current.

4. The phase interpolation circuit according to claim 1, wherein the common mode voltage correction circuit suppresses a variation in the common mode voltage according to the correction code.

5. The phase interpolation circuit according to claim 1, wherein the common mode voltage correction circuit suppresses a variation in the common mode voltage according to at least one of the correction code and the first current control code and the second current control code.

6. The first generation circuit has first and fourth transistors that operate as current sources and are respectively supplied with first and fourth gate voltages corresponding to the first current control code to their gates; The second generation circuit has second and fifth transistors that operate as current sources and are respectively supplied with second and fifth gate voltages corresponding to the second current control code to their gates; The correction circuit is characterized in that third and sixth gate voltages corresponding to the correction code are respectively supplied to the gates, and includes third and sixth transistors operating as current sources, according to any one of claims 1 to 5. The phase interpolation circuit described.

7. The correction circuit corrects the amount of current by generating the correction current according to at least one of the correction code, the first current control code, and the second current control code. The phase interpolation circuit according to any one of claims 1 to 6.

8. The phase interpolation circuit according to claim 6, further comprising a gate voltage control circuit that generates the third and sixth gate voltages based on at least one of the correction code, the first current control code, and the second current control code, and supplies the third and sixth gate voltages to the gates of the third and sixth transistors.

9. A phase interpolation circuit that generates a differential output clock signal having a phase corresponding to a first current control code and a second current control code based on a first differential input clock signal and a second differential input clock signal having a first phase difference, A first generation circuit that generates a first differential intermediate current based on the first differential input clock signal according to the first current control code; A second generation circuit that generates a second differential intermediate current based on the second differential input clock signal according to the second current control code, the correction code set such that the first differential intermediate current, the second differential intermediate current, and the second current control code cause fluctuations in the common mode voltage in the differential output clock signal; A synthesis circuit that synthesizes the first differential intermediate current and the second differential intermediate current to generate the differential output clock signal; And a common mode voltage correction circuit that corrects the common mode voltage in the differential output clock signal according to the fluctuation. A phase interpolation circuit characterized by comprising.

10. The common mode voltage correction circuit according to claim 9, wherein the common mode voltage correction circuit suppresses fluctuations in the common mode voltage according to a correction current generated according to the correction code.

11. The common mode voltage correction circuit according to claim 10, wherein the common mode voltage correction circuit keeps the sum of the currents flowing through the phase interpolation circuit constant regardless of the correction current.

12. The common mode voltage correction circuit according to claim 9, wherein the common mode voltage correction circuit suppresses fluctuations in the common mode voltage according to the correction code.

13. The common mode voltage correction circuit according to claim 9, wherein the common mode voltage correction circuit suppresses fluctuations in the common mode voltage according to at least one of the correction code, the first current control code, and the second current control code.

14. The first generation circuit has first and third transistors that operate as current sources, and first and third gate voltages corresponding to the first current control code are respectively supplied to the gates. The second generation circuit has second and fourth transistors that operate as current sources, and second and fourth gate voltages corresponding to the second current control code and the correction code are respectively supplied to the gates, according to any one of claims 9 to 13. The phase interpolation circuit described in the item.

15. The second generation circuit according to any one of claims 9 to 14, wherein the second generation circuit corrects the amount of the second differential intermediate current according to the correction code.

16. The phase interpolation circuit according to claim 14, further comprising a gate voltage control circuit that generates the second and fourth gate voltages based on the second current control code and the correction code and supplies them to the gates of the second and fourth transistors.

17. A phase interpolation circuit that generates a differential output clock signal having a phase corresponding to a first current control code and a second current control code based on a first differential input clock signal and a second differential input clock signal having a first phase difference, A first generation circuit that generates the first differential intermediate current based on the first differential input clock signal according to the first current control code among the first current control code and the second current control code, wherein the first differential intermediate current and the second differential intermediate current are set to cause fluctuations in the common mode voltage in the differential output clock signal; A second generation circuit that generates the second differential intermediate current based on the second differential input clock signal according to the second current control code; A synthesis circuit that synthesizes the first differential intermediate current and the second differential intermediate current to generate the differential output clock signal; A common-mode voltage correction circuit that corrects the common-mode voltage in the differential output clock signal according to the change; A phase interpolation circuit characterized by comprising the same. **Claim 18** The phase interpolation circuit according to claim 17, wherein the common-mode voltage correction circuit suppresses the change in the common-mode voltage according to the first differential intermediate current and the second differential intermediate current. **Claim 19** The phase interpolation circuit according to claim 18, wherein the common-mode voltage correction circuit makes the sum of the currents flowing through the phase interpolation circuit constant regardless of the first differential intermediate current and the second differential intermediate current. **Claim 20** The phase interpolation circuit according to claim 17, wherein the common-mode voltage correction circuit suppresses the change in the common-mode voltage according to at least one of the first current control code and the second current control code. **Claim 21** The phase interpolation circuit according to claim 17, wherein the common-mode voltage correction circuit suppresses the change in the common-mode voltage according to the first current control code and the second current control code. **Claim 22** The first generation circuit has first and third transistors that operate as current sources, to which first and third gate voltages corresponding to the first current control code are respectively supplied to the gates; The phase interpolation circuit according to any one of claims 17 to 21, wherein the second generation circuit has second and fourth transistors that operate as current sources, to which second and fourth gate voltages corresponding to the second current control code are respectively supplied to the gates. **Claim 23** A first gate voltage control circuit that generates the first and third gate voltages based on the first current control code and supplies them to the gates of the first and third transistors; A second gate voltage control circuit that generates the second and fourth gate voltages based on the second current control code and supplies them to the gates of the second and fourth transistors The phase interpolation circuit according to claim 22, further comprising the same. **Claim 24** A phase interpolation circuit that generates a differential output clock signal having a phase corresponding to a first current control code and a second current control code based on a first differential input clock signal and a second differential input clock signal having a first phase difference; A comparator that acquires data from a received signal by using the differential output clock signal generated by the phase interpolation circuit, a demultiplexer circuit that converts the output signal of the comparator into a parallel signal and has the phase interpolation circuit includes a first generation circuit that generates a first differential intermediate current based on the first differential input clock signal according to the first current control code, a second generation circuit that generates a second differential intermediate current based on the second differential input clock signal according to the second current control code, a synthesis circuit that synthesizes the first differential intermediate current and the second differential intermediate current to generate the differential output clock signal, a correction circuit that corrects at least one of the first differential intermediate current and the second differential intermediate current based on a correction current generated according to a correction code set so that the first differential intermediate current and the second differential intermediate current cause fluctuations in the common mode voltage in the differential output clock signal, and a common mode voltage correction circuit that corrects the common mode voltage in the differential output clock signal according to the fluctuations A receiving circuit characterized by comprising the above.

25. The receiving circuit according to claim 24, wherein the common mode voltage correction circuit suppresses fluctuations in the common mode voltage according to the correction current.

26. The receiving circuit according to claim 24, wherein the common mode voltage correction circuit suppresses fluctuations in the common mode voltage according to the correction code.

27. The receiving circuit according to claim 24, wherein the common mode voltage correction circuit suppresses fluctuations in the common mode voltage according to at least one of the correction code, the first current control code, and the second current control code.

28. The first generation circuit has first and fourth transistors that operate as current sources, to which first and fourth gate voltages according to the first current control code are respectively supplied to the gates, The second generation circuit has second and fifth transistors that operate as current sources, to which second and fifth gate voltages according to the second current control code are respectively supplied to the gates, The correction circuit according to any one of claims 24 to 27, characterized in that third and sixth gate voltages corresponding to the correction code are respectively supplied to the gates, and the third and sixth transistors operating as current sources are provided.

29. The correction circuit according to any one of claims 24 to 28, characterized in that the correction current is generated according to the correction code and at least one of the first current control code and the second current control code, thereby correcting the amount of current.

30. The receiving circuit according to claim 28, further comprising a gate voltage control circuit that generates the third and sixth gate voltages based on the correction code and at least one of the first current control code and the second current control code, and supplies the third and sixth gate voltages to the gates of the third and sixth transistors.

31. A phase interpolation circuit that generates a differential output clock signal having a phase corresponding to a first current control code and a second current control code based on a first differential input clock signal and a second differential input clock signal having a first phase difference; A comparator that acquires data from a received signal using the differential output clock signal generated by the phase interpolation circuit; A demultiplexer circuit that serial-parallel converts and outputs an output signal of the comparator; An internal circuit that performs a processing operation in response to an output signal of the demultiplexer circuit And having The phase interpolation circuit A first generation circuit that generates a first differential intermediate current based on the first differential input clock signal according to the first current control code; A second generation circuit that generates a second differential intermediate current based on the second differential input clock signal according to the second current control code; A synthesis circuit that synthesizes the first differential intermediate current and the second differential intermediate current to generate the differential output clock signal; A correction circuit that corrects the amount of current of at least one of the first differential intermediate current and the second differential intermediate current based on a correction current generated according to a correction code set so that the first differential intermediate current and the second differential intermediate current cause a variation in the common mode voltage in the differential output clock signal; And a common mode voltage correction circuit that corrects the common mode voltage in the differential output clock signal according to the variation A semiconductor integrated circuit characterized by having.

32. The semiconductor integrated circuit according to claim 31, wherein the common mode voltage correction circuit suppresses fluctuations in the common mode voltage according to the correction current.

33. The semiconductor integrated circuit according to claim 31, wherein the common mode voltage correction circuit suppresses fluctuations in the common mode voltage according to the correction code.

34. The semiconductor integrated circuit according to claim 31, wherein the common mode voltage correction circuit suppresses fluctuations in the common mode voltage according to at least one of the correction code, the first current control code, and the second current control code.

35. The first generation circuit has first and fourth transistors that operate as current sources, to which first and fourth gate voltages corresponding to the first current control code are respectively supplied to gates. The second generation circuit has second and fifth transistors that operate as current sources, to which second and fifth gate voltages corresponding to the second current control code are respectively supplied to gates. The semiconductor integrated circuit according to any one of claims 31 to 34, wherein the correction circuit has third and sixth transistors that operate as current sources, to which third and sixth gate voltages corresponding to the correction code are respectively supplied to gates.

36. The semiconductor integrated circuit according to any one of claims 31 to 35, wherein the correction circuit corrects the amount of current by generating the correction current according to at least one of the correction code, the first current control code, and the second current control code.

37. The semiconductor integrated circuit according to claim 35, further comprising a gate voltage control circuit that generates the third and sixth gate voltages based on at least one of the correction code, the first current control code, and the second current control code, and supplies the third and sixth gate voltages to the gates of the third and sixth transistors.

38. A phase interpolation circuit that generates a differential output clock signal having a phase corresponding to a first current control code and a second current control code based on a first differential input clock signal and a second differential input clock signal having a first phase difference; A comparator that acquires data from a received signal using the differential output clock signal generated by the phase interpolation circuit; A demultiplexer circuit that converts an output signal of the comparator into a parallel signal and having The phase interpolation circuit is a first generation circuit that generates a first differential intermediate current based on the first differential input clock signal according to the first current control code; a second generation circuit that generates a second differential intermediate current based on the second differential input clock signal according to the second current control code, the first differential intermediate current, and a correction code set so that the second differential intermediate current causes a variation in the common mode voltage in the differential output clock signal; a synthesis circuit that synthesizes the first differential intermediate current and the second differential intermediate current to generate the differential output clock signal; and a common mode voltage correction circuit that corrects the common mode voltage in the differential output clock signal according to the variation A receiving circuit characterized by comprising the same. **Claim 39** The receiving circuit according to claim 38, wherein the common mode voltage correction circuit suppresses a variation in the common mode voltage according to a correction current generated according to the correction code. **Claim 40** The receiving circuit according to claim 38, wherein the common mode voltage correction circuit suppresses a variation in the common mode voltage according to the correction code. **Claim 41** The receiving circuit according to claim 38, wherein the common mode voltage correction circuit suppresses a variation in the common mode voltage according to at least one of the correction code, the first current control code, and the second current control code. **Claim 42** The first generation circuit has first and third transistors that operate as current sources, and first and third gate voltages according to the first current control code are respectively supplied to the gates. The receiving circuit according to any one of claims 38 to 41, wherein the second generation circuit has second and fourth transistors that operate as current sources, and second and fourth gate voltages according to the second current control code and the correction code are respectively supplied to the gates. **Claim 43** The receiving circuit according to any one of claims 38 to 42, wherein the second generation circuit corrects the amount of current of the second differential intermediate current according to the correction code. **Claim 44** The receiving circuit according to claim 42, further comprising a gate voltage control circuit that generates the second and fourth gate voltages based on the second current control code and the correction code and supplies them to the gates of the second and fourth transistors. **Claim 45** Based on a first differential input clock signal having a first phase difference and a second differential input clock signal, a phase interpolation circuit that generates a differential output clock signal having a phase corresponding to a first current control code and a second current control code; A comparator that acquires data from a received signal using the differential output clock signal generated by the phase interpolation circuit; A demultiplexer circuit that serial-parallel converts and outputs the output signal of the comparator; An internal circuit that receives the output signal of the demultiplexer circuit and performs a processing operation And having The phase interpolation circuit is A first generation circuit that generates a first differential intermediate current based on the first differential input clock signal according to the first current control code; A second generation circuit that generates a second differential intermediate current based on the second differential input clock signal according to the second current control code, the first differential intermediate current, and a correction code set so that the second differential intermediate current causes a variation in the common mode voltage in the differential output clock signal; A synthesis circuit that synthesizes the first differential intermediate current and the second differential intermediate current to generate the differential output clock signal; A common mode voltage correction circuit that corrects the common mode voltage in the differential output clock signal according to the variation A semiconductor integrated circuit characterized by comprising

46. The semiconductor integrated circuit according to claim 45, wherein the common mode voltage correction circuit suppresses a variation in the common mode voltage according to a correction current generated according to the correction code.

47. The semiconductor integrated circuit according to claim 45, wherein the common mode voltage correction circuit suppresses a variation in the common mode voltage according to the correction code.

48. The semiconductor integrated circuit according to claim 45, wherein the common mode voltage correction circuit suppresses a variation in the common mode voltage according to at least one of the correction code, the first current control code, and the second current control code.

49. The first generation circuit has first and third transistors that operate as current sources, and first and third gate voltages corresponding to the first current control code are respectively supplied to the gates. The second generation circuit is characterized in that second and fourth gate voltages corresponding to the second current control code and the correction code are respectively supplied to the gates, and includes second and fourth transistors operating as current sources, according to any one of claims 45 to 48 of the semiconductor integrated circuit.

50. The semiconductor integrated circuit according to any one of claims 45 to 49, wherein the second generation circuit corrects the amount of the second differential intermediate current according to the correction code.

51. The semiconductor integrated circuit according to claim 49, further comprising a gate voltage control circuit that generates the second and fourth gate voltages based on the second current control code and the correction code and supplies them to the gates of the second and fourth transistors.

52. A phase interpolation circuit that generates a differential output clock signal having a phase corresponding to a first current control code and a second current control code based on a first differential input clock signal and a second differential input clock signal having a first phase difference; A comparator that acquires data from a received signal using the differential output clock signal generated by the phase interpolation circuit; A demultiplexer circuit that converts the output signal of the comparator into a parallel signal And having The phase interpolation circuit is A first generation circuit that generates the first differential intermediate current based on the first differential input clock signal according to the first current control code among the first current control code and the second current control code set so that the first differential intermediate current and the second differential intermediate current cause fluctuations in the common mode voltage in the differential output clock signal; A second generation circuit that generates the second differential intermediate current based on the second differential input clock signal according to the second current control code; A synthesis circuit that synthesizes the first differential intermediate current and the second differential intermediate current to generate the differential output clock signal; And a common mode voltage correction circuit that corrects the common mode voltage in the differential output clock signal according to the fluctuation A receiving circuit characterized by having.

53. The receiving circuit according to claim 52, wherein the common mode voltage correction circuit suppresses fluctuations in the common mode voltage corresponding to the first differential intermediate current and the second differential intermediate current.

54. The common mode voltage correction circuit suppresses fluctuations in the common mode voltage according to at least one of the first current control code and the second current control code, and the receiving circuit according to claim 52 is characterized in that.

55. The common mode voltage correction circuit suppresses fluctuations in the common mode voltage according to the first current control code and the second current control code, and the receiving circuit according to claim 52 is characterized in that.

56. The first generation circuit has first and third transistors that operate as current sources, to which first and third gate voltages corresponding to the first current control code are respectively supplied to the gates. The second generation circuit has second and fourth transistors that operate as current sources, to which second and fourth gate voltages corresponding to the second current control code are respectively supplied to the gates, and the receiving circuit according to any one of claims 52 to 55 is characterized in that.

57. A first gate voltage control circuit that generates the first and third gate voltages based on the first current control code and supplies them to the gates of the first and third transistors. A second gate voltage control circuit that generates the second and fourth gate voltages based on the second current control code and supplies them to the gates of the second and fourth transistors. The receiving circuit according to claim 56 further includes.

58. A phase interpolation circuit that generates a differential output clock signal having a phase according to a first current control code and a second current control code based on a first differential input clock signal and a second differential input clock signal having a first phase difference. A comparator that acquires data from the received signal using the differential output clock signal generated by the phase interpolation circuit. A demultiplexer circuit that serial-parallel converts and outputs the output signal of the comparator. An internal circuit that performs a processing operation in response to the output signal of the demultiplexer circuit. And has. The phase interpolation circuit is. A first generation circuit that generates the first differential intermediate current based on the first differential input clock signal according to the first current control code among the first current control code and the second current control code, which are set so that the first differential intermediate current and the second differential intermediate current cause fluctuations in the common mode voltage in the differential output clock signal. A second generation circuit that generates the second differential intermediate current based on the second differential input clock signal according to the second current control code; A combining circuit that combines the first differential intermediate current and the second differential intermediate current to generate the differential output clock signal; A common mode voltage correction circuit that corrects the common mode voltage in the differential output clock signal according to the variation; A semiconductor integrated circuit characterized by comprising the above.

59. The semiconductor integrated circuit according to claim 58, wherein the common mode voltage correction circuit suppresses the variation of the common mode voltage according to the first differential intermediate current and the second differential intermediate current.

60. The semiconductor integrated circuit according to claim 58, wherein the common mode voltage correction circuit suppresses the variation of the common mode voltage according to at least one of the first current control code and the second current control code.

61. The semiconductor integrated circuit according to claim 58, wherein the common mode voltage correction circuit suppresses the variation of the common mode voltage according to the first current control code and the second current control code.

62. The first generation circuit has first and third transistors that operate as current sources, and first and third gate voltages according to the first current control code are respectively supplied to the gates; The semiconductor integrated circuit according to any one of claims 58 to 61, wherein the second generation circuit has second and fourth transistors that operate as current sources, and second and fourth gate voltages according to the second current control code are respectively supplied to the gates.

63. A first gate voltage control circuit that generates the first and third gate voltages based on the first current control code and supplies them to the gates of the first and third transistors; A second gate voltage control circuit that generates the second and fourth gate voltages based on the second current control code and supplies them to the gates of the second and fourth transistors; The semiconductor integrated circuit according to claim 62, further characterized by comprising the above.

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