Display device

Abstract

To provide a display device that can limit a view angle.SOLUTION: A display device according to an embodiment comprises: a substrate; a first display element that is arranged above the substrate; a sealing layer that covers the first display element; and an optical control element overlapping the sealing layer. The optical control element comprises: a plurality of partition walls that include a pair of first partition walls which sandwich the first display element in a plan view; and an optical layer that is positioned between the pair of the first partition wall, contacts with a side surface of the first partition wall and overlaps the first display element. A refraction index of each of the partition walls is smaller than a refraction index of the optical layer.SELECTED DRAWING: Figure 4

Description

Technical Field

[0001] Embodiments of the present invention relate to a display device.

Background Art

[0002] In recent display devices, there is a demand for varying the viewing angle at which a predetermined contrast ratio can be obtained. For example, in a display device mounted on a vehicle such as an automobile, viewing angle control is required such that the display image can be viewed from the passenger seat side, while the display image cannot be viewed from the driver's seat side during driving or the like.

Prior Art Documents

Patent Documents

[0003]

Patent Document 1

Summary of the Invention

Problems to be Solved by the Invention

[0004] An object of the present invention is to provide a display device capable of restricting the viewing angle.

Means for Solving the Problems

[0005] According to one embodiment, a display device includes a substrate, a first display element disposed above the substrate, a sealing layer covering the first display element, and an optical control element superimposed on the sealing layer. The optical control element includes a plurality of partition walls including a pair of first partition walls sandwiching the first display element in a plan view, and an optical layer positioned between the pair of first partition walls, in contact with side surfaces of the first partition walls, and superimposed on the first display element. The refractive index of each of the partition walls is smaller than the refractive index of the optical layer.

[0006] According to one embodiment, a display device includes a first transparent substrate, a second transparent substrate facing the first transparent substrate, a liquid crystal layer disposed between the first transparent substrate and the second transparent substrate, a pixel electrode disposed between the first transparent substrate and the liquid crystal layer, and an optical control element disposed between the second transparent substrate and the liquid crystal layer. The optical control element includes a plurality of partition walls including a pair of first partition walls sandwiching the pixel electrode in a plan view, and an optical layer located between the pair of first partition walls, in contact with side surfaces of the first partition walls, and overlapping the pixel electrode. The refractive index of each of the partition walls is smaller than the refractive index of the optical layer.

Brief Description of Drawings

[0007]

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[0008] Some embodiments will be described with reference to the drawings. The disclosure is merely an example, and for those that can be easily conceived by those skilled in the art with appropriate modifications while maintaining the gist of the invention, they are naturally included in the scope of the present invention. Also, the drawings may schematically represent the width, thickness, shape, etc. of each part compared to the actual aspect for clearer explanation, but they are merely examples and do not limit the interpretation of the present invention. Also, in this specification and each figure, components that exhibit the same or similar functions as those described above for the previously presented figures are assigned the same reference numerals, and detailed descriptions may be appropriately omitted as needed.

[0009] In addition, in the drawings, for ease of understanding as necessary, the X-axis, Y-axis, and Z-axis that are orthogonal to each other are described. The direction along the X-axis is referred to as the first direction X, the direction along the Y-axis is referred to as the second direction Y, and the direction along the Z-axis is referred to as the third direction Z. Looking at various elements parallel to the third direction Z is referred to as a plan view.

[0010] [First Embodiment] FIG. 1 is a diagram showing a configuration example of a display device DSP according to the first embodiment. The display device DSP according to the present embodiment is an organic electroluminescence display device including an organic light-emitting diode (OLED) as a display element, and can be mounted on a television, a personal computer, in-vehicle equipment, a tablet terminal, a smartphone, a mobile phone terminal, or the like. In this specification, as an example, a display device mounted on a vehicle such as an automobile will be described.

[0011] The display device DSP includes a display panel PNL having a display area DA for displaying an image and a peripheral area SA outside the display area DA on an insulating substrate 10. The substrate 10 may be glass or a resin film having flexibility.

[0012] In FIG. 1, the shape of the substrate 10 in plan view is a rectangle having a long side parallel to the first direction X. However, the shape of the substrate 10 in plan view is not limited to this example, and may be other shapes such as a rectangle having a long side parallel to the second direction Y, a square, a circle, or an ellipse.

[0013] The display area DA includes a plurality of pixels PX arranged in a matrix in the first direction X and the second direction Y. The pixel PX includes a plurality of sub-pixels SP. In one example, the pixel PX includes a sub-pixel SP1 of a first color, a sub-pixel SP2 of a second color, and a sub-pixel SP3 of a third color. The first color, the second color, and the third color are different from each other. Note that the pixel PX may include sub-pixels SP of other colors such as white together with or instead of the sub-pixels SP1, SP2, and SP3.

[0014] The sub-pixel SP includes a pixel circuit 1 and a display element 20 driven by the pixel circuit 1. The pixel circuit 1 includes a pixel switch 2, a driving transistor 3, and a capacitor 4. The pixel switch 2 and the driving transistor 3 are switching elements formed of, for example, thin film transistors.

[0015] The gate electrode of the pixel switch 2 is connected to the scanning line GL. One of the source electrode and the drain electrode of the pixel switch 2 is connected to the signal line SL, and the other is connected to the gate electrode of the driving transistor 3 and the capacitor 4. In the driving transistor 3, one of the source electrode and the drain electrode is connected to the power supply line PL and the capacitor 4, and the other is connected to the anode of the display element 20.

[0016] Note that the configuration of the pixel circuit 1 is not limited to the illustrated example. For example, the pixel circuit 1 may include more thin film transistors and capacitors.

[0017] The display element 20 is an organic light emitting diode (OLED) as a light emitting element, and may be referred to as an organic EL element.

[0018] In the peripheral region SA, although not described in detail, terminals for connecting an IC chip and a flexible printed circuit board are provided.

[0019] FIG. 2 is a diagram showing a configuration example of the sub-pixels SP1, SP2, and SP3 according to the first embodiment. The sub-pixels SP1, SP2, and SP3 each include display elements 201, 202, and 203 as the display element 20.

[0020] The display element 201 includes a lower electrode LE1, an organic layer OR1 including a light-emitting layer EM1, an upper electrode UE, and a cap layer CP. The light-emitting layer EM1 overlaps the lower electrode LE1, the upper electrode UE overlaps the light-emitting layer EM1, and the cap layer CP overlaps the upper electrode UE. The organic layer OR1 is disposed between the lower electrode LE1 and the upper electrode UE. The light-emitting layer EM1 is formed of a material that emits light, for example, in the blue wavelength range.

[0021] The display element 202 includes a lower electrode LE2, an organic layer OR2 including a light-emitting layer EM2, an upper electrode UE, and a cap layer CP. The light-emitting layer EM2 overlaps the lower electrode LE2, the upper electrode UE overlaps the light-emitting layer EM2, and the cap layer CP overlaps the upper electrode UE. The organic layer OR2 is disposed between the lower electrode LE2 and the upper electrode UE. The light-emitting layer EM2 is formed of a material that emits light, for example, in the green wavelength range.

[0022] The display element 203 includes a lower electrode LE3, an organic layer OR3 including a light-emitting layer EM3, an upper electrode UE, and a cap layer CP. The light-emitting layer EM3 overlaps the lower electrode LE3, the upper electrode UE overlaps the light-emitting layer EM3, and the cap layer CP overlaps the upper electrode UE. The organic layer OR3 is disposed between the lower electrode LE3 and the upper electrode UE. The light-emitting layer EM3 is formed of a material that emits light, for example, in the red wavelength range.

[0023] In one example, the lower electrodes LE1, LE2, and LE3 correspond to the anodes of the respective display elements, and the upper electrode UE corresponds to the cathode or the common electrode of the respective display elements.

[0024] In the illustrated example, the organic layers OR1, OR2, and OR3 include a common layer CL1 and a common layer CL2. The common layer CL1 has, for example, a hole injection layer, a hole transport layer, an electron blocking layer, and the like. The common layer CL1 is disposed between the lower electrode LE1 and the light-emitting layer EM1, between the lower electrode LE2 and the light-emitting layer EM2, and between the lower electrode LE3 and the light-emitting layer EM3, respectively. The common layer CL2 has, for example, an electron injection layer, an electron transport layer, a hole blocking layer, etc. The common layer CL2 is disposed between the light-emitting layer EM1 and the upper electrode UE, between the light-emitting layer EM2 and the upper electrode UE, and between the light-emitting layer EM3 and the upper electrode UE, respectively.

[0025] FIG. 3 is a diagram showing a configuration example of the periphery of the pixel PX according to the first embodiment. The above-described pixel PX includes pixels PX1 and PX2 adjacent to each other along the second direction Y. In the illustrated example, in the display area DA, a row in which the pixels PX1 and PX2 are alternately arranged in the second direction Y is formed. This row is arranged in the first direction X. Each of the pixels PX1 and PX2 includes sub-pixels SP1, SP2, and SP3.

[0026] In the example of FIG. 3, the sub-pixels SP2 and SP3 are arranged in the second direction Y. Also, the sub-pixels SP1 and SP2 are arranged in the first direction X, and the sub-pixels SP1 and SP3 are arranged in the first direction X.

[0027] When the sub-pixels SP1, SP2, and SP3 are in such a layout, in the display area DA, a row in which a plurality of sub-pixels SP1 are arranged in the second direction Y and a row in which the sub-pixels SP2 and SP3 are alternately arranged in the second direction Y are formed. These rows are alternately arranged in the first direction X. Note that the layout of the sub-pixels SP1, SP2, and SP3 is not limited to the example of FIG. 3. As will be described in detail later, as another example, as shown in FIG. 14, the sub-pixels SP1, SP2, and SP3 in each pixel PX may be arranged in order in the first direction X.

[0028] The display device DSP further includes a rib 5. The rib 5 has openings AP1, AP2, and AP3 in the sub-pixels SP1, SP2, and SP3, respectively. In the illustrated example, the area of the opening AP1 is larger than the areas of the openings AP2 and AP3, and the area of the opening AP2 is equal to the area of the opening AP3. Note that the areas of the openings AP1, AP2, and AP3 may be different from each other or all the same.

[0029] The rib 5 has a plurality of ribs 5x extending along the first direction X and a plurality of ribs 5y extending along the second direction Y. The plurality of ribs 5x are respectively disposed between two adjacent openings AP1 in the second direction Y and between the adjacent opening AP2 and opening AP3 in the second direction Y. The plurality of ribs 5y are respectively disposed between the adjacent opening AP1 and opening AP2 in the first direction X and between the adjacent opening AP1 and opening AP3 in the first direction X.

[0030] In the example of FIG. 3, the ribs 5x and the ribs 5y are connected to each other. Thereby, the rib 5 is formed in a lattice shape surrounding the openings AP1, AP2, and AP3 respectively.

[0031] In the display element 201 of the sub-pixel SP1, the opening AP1 overlaps the lower electrode LE1 and the light-emitting layer EM1. The lower electrode LE1 is electrically connected to the pixel circuit 1 (see FIG. 1) of the sub-pixel SP1. The respective peripheral portions of the lower electrode LE1 and the light-emitting layer EM1 overlap the rib 5. The lower electrode LE1 and the light-emitting layer EM1 are surrounded by the rib 5.

[0032] In the display element 202 of the sub-pixel SP2, the opening AP2 overlaps the lower electrode LE2 and the light-emitting layer EM2. The lower electrode LE2 is electrically connected to the pixel circuit 1 of the sub-pixel SP2. The respective peripheral portions of the lower electrode LE2 and the light-emitting layer EM2 overlap the rib 5. The lower electrode LE2 and the light-emitting layer EM2 are surrounded by the rib 5.

[0033] In the display element 203 of the sub-pixel SP3, the opening AP3 overlaps the lower electrode LE3 and the light-emitting layer EM3. The lower electrode LE3 is electrically connected to the pixel circuit 1 of the sub-pixel SP3. The respective peripheral portions of the lower electrode LE3 and the light-emitting layer EM3 overlap the rib 5. The lower electrode LE3 and the light-emitting layer EM3 are surrounded by the rib 5.

[0034] The lower electrodes LE1, LE2, and LE3 are spaced apart from each other. Also, the light-emitting layers EM1, EM2, and EM3 are spaced apart from each other.

[0035] In the illustrated example, the outer shapes of the lower electrodes LE1, LE2, and LE3 are indicated by dotted lines, and the outer shapes of the light-emitting layers EM1, EM2, and EM3 are indicated by two-dot chain lines. Note that the respective outer shapes of the apertures AP1, AP2, AP3, the lower electrodes LE1, LE2, LE3, and the light-emitting layers EM1, EM2, and EM3 do not necessarily reflect the exact shapes.

[0036] The display device DSP further includes partition walls P11, P12, and P13 included in the optical control element OD. The partition walls P11, P12, and P13 extend in the second direction Y, which is the direction in which the pixels PX1 and PX2 are arranged. The partition walls P11 and P13 are located between two adjacent pixels PX1 in the first direction X. The partition walls P11 and P13 sandwich the pixel PX1 along the first direction X in a plan view. The partition wall P12 is located between the display element 201 and the display element 202 adjacent to each other in the first direction X in the pixel PX1, and between the display element 201 and the display element 203 adjacent to each other in the first direction X in the pixel PX1. The partition walls P11 and P12 sandwich the display element 201 along the first direction X in a plan view. The partition walls P12 and P13 sandwich the display elements 202 and 203, respectively, along the first direction X in a plan view.

[0037] The partition walls P11, P12, and P13 overlap the rib 5 in the third direction Z. The partition walls P11, P12, and P13 overlap the pixel PX1 in the third direction Z.

[0038] In the illustrated example, in the pixel PX1, the partition wall P11 overlaps the peripheral portion of the light-emitting layer EM1 in the third direction Z and does not overlap the lower electrode LE1 and the aperture AP1. Note that the partition wall P11 does not necessarily overlap the light-emitting layer EM1 in the third direction Z and may overlap the lower electrode LE1 and the aperture AP1.

[0039] Also, in pixel PX1, the partition wall P12 overlaps with the peripheral edges of the light-emitting layers EM1, EM2, and EM3 in the third direction Z, and does not overlap with the lower electrodes LE1, LE2, LE3, and the openings AP1, AP2, AP3. Note that the partition wall P12 may not overlap with the light-emitting layers EM1, EM2, and EM3 in the third direction Z, or may overlap with the lower electrodes LE1, LE2, LE3, and the openings AP1, AP2, AP3.

[0040] Also, in pixel PX1, the partition wall P13 overlaps with the peripheral edges of the light-emitting layers EM2 and EM3 in the third direction Z, and does not overlap with the lower electrodes LE2 and LE3, and the openings AP2 and AP3. Note that the partition wall P13 may not overlap with the light-emitting layers EM2 and EM3 in the third direction Z, or may overlap with the lower electrodes LE2 and LE3, and the openings AP2 and AP3.

[0041] On the other hand, the partition walls P11, P12, and P13 do not overlap with pixel PX2 in the third direction Z. That is, each of the partition walls P11, P12, and P13 extends in the second direction Y but is interrupted at pixel PX2. In plan view, there are no partition walls sandwiching the sub-pixels SP1, SP2, and SP3 of pixel PX2. That is, each of the partition walls P11, P12, and P13 has a length corresponding to one pixel in the second direction Y and is arranged with an interval corresponding to one pixel in the second direction Y.

[0042] In the example shown in FIG. 3, the partition walls overlapping the pixels are arranged at intervals of one pixel in the extending direction of the partition walls. However, when n is an integer of 2 or more, they may be arranged at intervals of n pixels. In this case, the partition walls have a length corresponding to n pixels in the extending direction of the partition walls and are arranged with an interval corresponding to n pixels in the extending direction. Note that the length of the partition walls and the interval between the partition walls do not have to match.

[0043] FIG. 4 is a cross-sectional view showing a configuration example of the display device DSP along the line A-A' of FIG. 3. Hereinafter, among the display elements 201, 202, and 203 of pixel PX1, the display elements 201 and 203 will be described, but the display element 202 is also formed to have the same cross-section as the display elements 201 and 203.

[0044] The display device DSP includes the above-described substrate 10, display elements 201 and 203 disposed above the substrate 10, a circuit layer 11, an insulating layer 12, a sealing layer 16, an optical control element OD, and a polarizing plate 17.

[0045] The circuit layer 11 is disposed on the substrate 10. The circuit layer 11 includes various circuits such as the pixel circuit 1 shown in FIG. 1 and various wirings such as a scanning line GL, a signal line SL, and a power supply line PL. The circuit layer 11 is covered by the insulating layer 12. The insulating layer 12 includes an organic insulating layer that planarizes the unevenness caused by the circuit layer 11.

[0046] The lower electrodes LE1 and LE3 are disposed on the insulating layer 12 and are spaced apart from each other. The rib 5 is disposed on the insulating layer 12 and the lower electrodes LE1 and LE3. The rib 5 is formed of an organic material or an inorganic material. The opening AP1 overlaps the lower electrode LE1, and the opening AP3 overlaps the lower electrode LE3. The peripheral portions of the lower electrodes LE1 and LE3 are covered by the rib 5. Between the lower electrodes LE1 and LE3, the insulating layer 12 is covered by the rib 5. The lower electrodes LE1 and LE3 are connected to the respective pixel circuits 1 of the sub-pixels SP1 and SP3 through contact holes provided in the insulating layer 12. Note that the contact holes in the insulating layer 12 are omitted in FIG. 4.

[0047] The common layer CL1 is disposed on the lower electrodes LE1, LE3, and the rib 5. In the illustrated example, the light-emitting layer EM1 is located directly above the lower electrode LE1 and is disposed on the common layer CL1. The light-emitting layer EM3 is located directly above the lower electrode LE3 and is disposed on the common layer CL1. The common layer CL2 is disposed on the light-emitting layers EM1 and EM3 and is also disposed on the common layer CL1 outside the light-emitting layers EM1 and EM3. The common layer CL1, the light-emitting layer EM1, and the common layer CL2 constitute the organic layer OR1 as described with reference to FIG. 2. Similarly, the common layer CL1, the light-emitting layer EM3, and the common layer CL2 constitute the organic layer OR3 as described with reference to FIG. 2.

[0048] The upper electrode UE is disposed on the common layer CL2. The upper electrode UE is formed of a metal material such as an alloy of magnesium and silver (MgAg), for example.

[0049] The cap layer CP is disposed on the upper electrode UE. The cap layer CP is a transparent multilayer body. The refractive indices of the respective layers constituting the cap layer CP are different from each other. Such a cap layer CP functions as an optical adjustment layer for adjusting the optical characteristics of the light emitted from the light emitting layers EM1 and EM3.

[0050] The sealing layer 16 is disposed on the cap layer CP. The sealing layer 16 covers the display elements 201 and 203. The sealing layer 16 includes an organic layer for flattening the unevenness caused by the rib 5 and an inorganic layer for protecting the light emitting layers EM1 and EM3 from moisture and the like.

[0051] The optical control element OD includes the above-described partition walls P11, P12, P13, a transparent optical layer OL1, and a plurality of light shielding layers BM1, BM2. The optical control element OD is superimposed on the sealing layer 16. In the illustrated example, the optical control element OD is disposed on the sealing layer 16. The polarizing plate 17 is adhered to the upper surface of the optical control element OD via an adhesive AD.

[0052] Hereinafter, the partition wall P12 among the partition walls P11, P12, P13 will be described, but the partition walls P11 and P13 are formed in the same manner as the partition wall P12.

[0053] The partition wall P12 has side surfaces S1, S2, a bottom surface P12L, and a top surface P12U. The side surface S1 of the partition wall P12 faces the partition wall P11 in the first direction X, and the side surface S2 of the partition wall P12 faces the partition wall P13 in the first direction X. The bottom surface P12L faces the sealing layer 16 in the third direction Z. The top surface P12U is located opposite to the bottom surface P12L in the partition wall P12 and faces the polarizing plate 17 in the third direction Z. The side surfaces S1, S2 of the partition wall P12 are each inclined with respect to the normal line 10N of the substrate 10 such that the width W12L of the bottom surface P12L is larger than the width W12U of the top surface P12U (W12L>W12U). Note that the width W12L is the length of the bottom surface P12L along the first direction X, and the width W12U is the length of the top surface P12U along the first direction X. That is, the partition wall P12 has a tapered cross section in which the width along the first direction X decreases as it moves away from the sealing layer 16.

[0054] In the illustrated example, the optical layer OL1 is located between a pair of partition walls P11 and P12 adjacent to each other in the first direction X and is in contact with the side surface S2 of the partition wall P11 and the side surface S1 of the partition wall P12. Further, the optical layer OL1 is located between a pair of partition walls P12 and P13 adjacent to each other in the first direction X and is in contact with the side surface S2 of the partition wall P12 and the side surface S1 of the partition wall P13. The optical layer OL1 overlaps the display elements 201 and 203 in the third direction Z. In the present embodiment, the optical layer OL1 surrounds the partition walls P11, P12, and P13.

[0055] The partition walls P11, P12, P13, and the optical layer OL1 are formed of a resin material. However, the partition walls P11, P12, P13 are formed of a material having a refractive index smaller than that of the optical layer OL1. Further, the partition walls P11, P12, P13 may be air layers. Furthermore, the partition walls P11, P12, P13 may be transparent, may be colored, or may be light absorbers. The optical layer OL1 may have a function of adhering the sealing layer 16 and the polarizing plate 17.

[0056] The plurality of light-shielding layers BM1 (first light-shielding layer) are respectively located between the sealing layer 16 and the partition walls P11, P12, and P13. The plurality of light-shielding layers BM1 respectively overlap the partition walls P11, P12, and P13. The peripheral portion of the light-shielding layer BM1 is surrounded by the optical layer OL1.

[0057] In the partition wall P12, the width WBM1 of the light-shielding layer BM1 is larger than the width W12L of the bottom surface P12L (WBM1 > W12L). That is, the light-shielding layer BM1 covers the entire bottom surface P12L. Note that the width WBM1 is the length of the light-shielding layer BM1 along the first direction X. Also, the width WBM1 may be the same as the width W12L. The light-shielding layers BM1 that overlap the partition walls P11 and P13 respectively are formed in the same shape as the light-shielding layer BM1 that overlaps the partition wall P12.

[0058] The plurality of light-shielding layers BM2 (second light-shielding layer) are respectively located between the partition walls P11, P12, P13 and the polarizing plate 17. The plurality of light-shielding layers BM2 respectively overlap the partition walls P11, P12, and P13. The peripheral portion of the light-shielding layer BM2 is surrounded by the optical layer OL1.

[0059] In the partition wall P12, the width WBM2 of the light-shielding layer BM2 is larger than the width W12U of the upper surface P12U (WBM2 > W12U). That is, the light-shielding layer BM2 covers the entire upper surface P12U. Note that the width WBM2 is the length of the light-shielding layer BM2 along the first direction X. Also, the width WBM2 may be the same as the width W12U. The light-shielding layers BM1 that overlap the partition walls P11 and P13 respectively are formed in the same shape as the light-shielding layer BM1 that overlaps the partition wall P12.

[0060] In the illustrated example, the width WBM1 of the light-shielding layer BM1 is the same as the width WBM2 of the light-shielding layer BM2. However, the width WBM1 may be different from the width WBM2.

[0061] In this embodiment, the refractive index of each of the partition walls P11, P12, and P13 is smaller than the refractive index of the optical layer OL1. Therefore, for example, when the light L1 emitted from the light-emitting layer EM1 is incident on the side surface S1 of the partition wall P12 at an angle θ1, if the angle θ1 is smaller than the critical angle, the light L1 is totally reflected at the side surface S1 of the partition wall P12. The light L1 totally reflected at the side surface S1 is emitted from the display device DSP in a direction close to the extending direction (third direction Z) of the normal line 10N of the substrate 10. As a result, when the display device DSP is viewed from the front, the light emitted from the light-emitting layer can be visually recognized, and when the display device DSP is viewed obliquely from the first direction X side, it becomes difficult to visually recognize the light emitted from the light-emitting layer. Therefore, for the pixel PX1, the viewing angle can be restricted.

[0062] Note that in order for light to be totally reflected at the boundary between the partition wall and the optical layer, it is desirable that the refractive index difference between the partition wall and the optical layer is 0.2 or more. In one example, the refractive index of the partition wall is 1.25 and the refractive index of the optical layer is 1.5.

[0063] Also, when the partition wall is formed of a light absorber, among the light emitted from the light-emitting layer, the light emitted in a direction close to the extending direction of the normal line 10N can be visually recognized, but the other light is absorbed by the partition wall which is a light absorber, so it becomes difficult to visually recognize. Therefore, also in this case, the viewing angle of the pixel PX1 can be restricted.

[0064] Also, it is desirable that the refractive index of the optical layer OL1 is equivalent to that of the encapsulation layer 16. For example, when the refractive index of the optical layer OL1 is smaller than that of the encapsulation layer 16, the light emitted from the light-emitting layer refracts at the interface between the optical layer OL1 and the encapsulation layer 16, so that more light enters the partition wall at an angle larger than the critical angle. The light that enters at an angle larger than the critical angle does not reflect off the side surface of the partition wall but passes through the partition wall, so that less light is emitted in a direction close to the extending direction of the normal line 10N. Therefore, the luminance of the display image when the display device DSP is viewed from the front may decrease. On the other hand, when the refractive index of the optical layer OL1 and the refractive index of the encapsulation layer 16 are the same or the difference in refractive index is extremely small, the light emitted from the light-emitting layer travels straight without hardly refracting at the interface between the encapsulation layer 16 and the optical layer OL1. Therefore, more light enters the partition wall at an angle smaller than the critical angle and reflects off the side surface of the partition wall. Therefore, it is possible to suppress a decrease in the luminance of the display image when the display device DSP is viewed from the front.

[0065] Also, in the display device DSP according to the present embodiment, the optical control element OD includes light-shielding layers BM1 and BM2. As illustrated in FIG. 4, the light-shielding layers BM1 and BM2 have a function of absorbing the light L2 emitted from the light-emitting layer EM1 toward the bottom surface P12L of the partition wall P12. In the absence of the light-shielding layer, the light L2 enters the bottom surface P12L, passes through the partition wall P12, and may be mixed with the light emitted from the light-emitting layer EM3 to cause color mixing. Therefore, by providing the light-shielding layers BM1 and BM2 in the optical control element OD, it is possible to prevent the occurrence of color mixing and suppress a decrease in display quality.

[0066] FIG. 5 is a cross-sectional view showing a configuration example of the display device DSP along line B-B' in FIG. 3. The optical layer OL1 overlaps the display elements 201 and 203 of the pixel PX2 in the third direction Z. In the illustrated example, the optical layer OL1 is disposed on the encapsulation layer 16. Thus, among the optical control elements OD, the optical layer OL1 overlaps the pixel PX2, and the partition wall does not overlap the pixel PX2. Therefore, for example, the light L3 emitted from the light-emitting layer EM1 travels straight without being reflected by the optical control element OD. Therefore, for the pixel PX2, a wider viewing angle can be realized as compared with the pixel PX1.

[0067] In this embodiment, as shown in FIG. 3, pixels PX1 that overlap with the partition wall and pixels PX2 that do not overlap with the partition wall are alternately arranged along the second direction Y. As shown in FIG. 4, in pixel PX1, the light emitted from the light-emitting layer is reflected by the side surface of the partition wall and guided in a direction close to the extending direction (third direction Z) of the normal line 10N. On the other hand, as shown in FIG. 5, in pixel PX2, the light emitted from the light-emitting layer passes through the optical control element OD. In such a configuration, when pixel PX1 is lit and pixel PX2 is not lit (hereinafter referred to as the first mode), when the display device DSP is viewed from the front, the image displayed in the display area DA can be visually recognized, but when the display device DSP is viewed obliquely from the first direction X side, it becomes difficult to visually recognize the image. When pixel PX1 is not lit and pixel PX2 is lit, or when both pixels PX1 and PX2 are lit (hereinafter referred to as the second mode), the image can be visually recognized when the display device DSP is viewed from the front, and the image can also be visually recognized when the display device DSP is viewed from the first direction X side.

[0068] Here, the case where the display device DSP of this embodiment is mounted on a vehicle such as an automobile will be described. It is assumed that the display device DSP is mounted in front of the passenger seat. For example, during driving, it is required to make it difficult to visually recognize the image displayed on the display device DSP from the driver's seat side, while making it possible to visually recognize the image from the passenger seat side. In this case, the image is displayed in the first mode. Then, although the visual recognition of the image is restricted from the driver's seat side, the image can be visually recognized well from the passenger seat side. On the other hand, when it is desired to be able to visually recognize the image from both the driver's seat side and the passenger seat side in the engine-off state, the image is displayed in the second mode. Then, the image can be visually recognized well from both the driver's seat side and the passenger seat side. In this way, by switching between the first mode and the second mode, the viewing angle is controlled, and in particular, it is possible to switch the visibility of the image from the driver's seat side.

[0069] In the above example, for instance, each of the display elements 201, 202, and 203 of pixel PX1 corresponds to a first display element, each of the display elements 201, 202, and 203 of pixel PX2 corresponds to a second display element, and the partition walls P11, P12, and P13 correspond to a first partition wall. When the display element 201 of pixel PX1 corresponds to the first display element, the partition walls P11 and P12 correspond to a pair of first partition walls. Also, when the display element 202 or 203 of pixel PX1 corresponds to the first display element, the partition walls P12 and P13 correspond to a pair of first partition walls.

[0070] FIG. 6 is a diagram showing another configuration example of the periphery of pixel PX according to the first embodiment. The same or similar elements as those described above are denoted by the same reference numerals, and redundant descriptions are omitted as appropriate.

[0071] The optical control element OD further includes partition walls P21 and P22. The partition walls P21 and P22 extend in the second direction Y respectively. The partition wall P21 is located between the partition walls P11 and P12 and overlaps the display element 201 in the third direction Z. The partition wall P22 is located between the partition walls P12 and P13 and overlaps the display elements 202 and 203 in the third direction Z. The partition walls P21 and P22 overlap pixel PX1 in the third direction Z but do not overlap pixel PX2.

[0072] FIG. 7 is a cross-sectional view showing a configuration example of the display device DSP along the line C-C' of FIG. 6. The partition walls P21 and P22 are formed in the same shape as the partition walls P11, P12, and P13.

[0073] The display device DSP shown in FIGS. 6 and 7 has a larger number of partition walls overlapping one pixel than the display device DSP shown in FIGS. 3 and 4. When the number of partition walls overlapping one pixel increases, among the light emitted from the light-emitting layer, the light rays reflected by the partition walls increase, and the light rays passing between adjacent partition walls are restricted. Therefore, as the number of partition walls increases, the viewing angle is further restricted.

[0074] On the one hand, when the height of the partition wall is reduced, among the light emitted from the light-emitting layer, the light rays reflected by the partition wall decrease, and the viewing angle becomes wider. Also, by reducing the height of the partition wall, the display device DSP can be made thinner.

[0075] That is, by increasing the number of partition walls overlapping one pixel and reducing the height of the partition walls, a viewing angle of the same degree can be obtained and the display device DSP can be made thinner. Also, in the display device DSP shown in FIGS. 6 and 7, by increasing the number of partition walls and reducing the height of the partition walls compared to the display device DSP shown in FIGS. 3 and 4, a viewing angle of the same degree as that of the display device DSP shown in FIGS. 3 and 4 can be obtained and the display device DSP can be made thinner.

[0076] In the above example, for example, the partition walls P11, P12, and P13 correspond to the first partition wall, and the partition walls P21 and P22 correspond to the second partition wall. When the display element 201 of the pixel PX1 corresponds to the first display element, the partition walls P11 and P12 correspond to a pair of first partition walls, and the partition wall P21 corresponds to the second partition wall. Also, when the display element 202 or 203 of the pixel PX1 corresponds to the first display element, the partition walls P12 and P13 correspond to the first partition wall, and the partition wall P22 corresponds to the second partition wall.

[0077] FIG. 8 is a diagram showing still another configuration example around the pixel PX according to the first embodiment. The display device DSP shown in FIG. 8 is different from the display device DSP shown in FIG. 3 in that it includes partition walls P31 to P35 instead of the partition walls P11, P12, and P13 shown in FIG. 3.

[0078] The optical control element OD includes the partition walls P31 to P35. The partition walls P31 to P35 each extend in the first direction X. The partition walls P31, P33, and P35 are located between the adjacent pixels PX1 and PX2 in the second direction Y. The partition wall P32 is located between the partition walls P31 and P33 and overlaps with the display element 201 of the pixel PX1 in the third direction Z. The partition wall P32 is located between the display elements 202 and 203 of the pixel PX1 in the second direction Y. The partition wall P34 is located between the partition walls P33 and 35 and overlaps with the display element 201 of the pixel PX2 in the third direction Z. The partition wall P34 is located between the display elements 202 and 203 of the pixel PX2 in the second direction Y. The partition walls P31 to P35 overlap with the rib 5 in the third direction Z.

[0079] The partition walls P31 and P33 sandwich the display element 201 of the pixel PX1 along the second direction Y in a plan view. The partition walls P32 and P33 sandwich the display element 202 of the pixel PX1 along the second direction Y in a plan view. The partition walls P31 and P32 sandwich the display element 203 of the pixel PX1 along the second direction Y in a plan view. The partition walls P33 and P35 sandwich the display element 201 of the pixel PX2 along the second direction Y in a plan view. The partition walls P34 and P35 sandwich the display element 202 of the pixel PX2 along the second direction Y in a plan view. The partition walls P33 and P34 sandwich the display element 203 of the pixel PX2 along the second direction Y in a plan view.

[0080] The light emitted from the light-emitting layer is reflected by the side surfaces of each of the partition walls P31 to P35 and travels in a direction close to the third direction Z. Therefore, in the display device DSP shown in FIG. 3, when the display device DSP is viewed obliquely from the first direction X side, the image becomes difficult to visually recognize, while in the display device DSP shown in FIG. 8, when the display device DSP is viewed obliquely from the second direction Y side, the image becomes difficult to visually recognize.

[0081] In the display device DSP shown in FIG. 8, when the display device DSP of the present embodiment is mounted on a vehicle such as an automobile, for example, it is possible to suppress an undesired reflection of an image displayed in the display area DA on the front window of the automobile.

[0082] In the above example, for instance, when the display element 201 of pixel PX1 corresponds to the first display element, the partition walls P31 and P33 correspond to a pair of first partition walls, and the partition wall P32 corresponds to the second partition wall. Further, when the display element 202 of pixel PX1 corresponds to the first display element, the partition walls P32 and P33 correspond to a pair of first partition walls. Furthermore, when the display element 203 of pixel PX1 corresponds to the first display element, the partition walls P31 and P32 correspond to a pair of first partition walls.

[0083] Similarly, when the display element 201 of pixel PX2 corresponds to the first display element, the partition walls P33 and P35 correspond to a pair of first partition walls, and the partition wall P34 corresponds to the second partition wall. Further, when the display element 202 of pixel PX2 corresponds to the first display element, the partition walls P34 and P35 correspond to a pair of first partition walls. Furthermore, when the display element 203 of pixel PX2 corresponds to the first display element, the partition walls P33 and P34 correspond to a pair of first partition walls.

[0084] FIG. 9 is a diagram showing still another configuration example of the periphery of pixel PX according to the first embodiment. The display device DSP shown in FIG. 9 includes partition walls that are a combination of the partition walls P11, P12, P13 of the display device DSP shown in FIG. 3 and the partition walls P31 to P35 of the display device shown in FIG. 8.

[0085] Each of the partition walls P31, P32, P33, and P35 intersects each of the partition walls P11, P12, and P13. In the example of FIG. 9, the partition walls P11, P12, P13 and the partition walls P31, P32, P33 are connected to each other. Also, the partition walls P11, P12, P13 and the partition wall P35 are connected to each other. In pixel PX1, the display element 201 is surrounded by the partition walls P11, P12, P31, and P33. Also, in pixel PX1, the display element 202 is surrounded by the partition walls P12, P13, P32, and P33. Also, in pixel PX1, the display element 203 is surrounded by the partition walls P12, P13, P31, and P32.

[0086] In the display device DSP shown in FIG. 9, the viewing angle in the first direction X can be changed by switching between the first mode and the second mode, and at the same time, the viewing angle in the second direction Y can be narrowed.

[0087] In the above example, for example, when the display element 201 of the pixel PX1 corresponds to the first display element, the partition walls P31 and P33 correspond to a pair of first partition walls, the partition wall P32 corresponds to the second partition wall, and the partition walls P11 and P12 correspond to a pair of third partition walls. Further, when the display element 202 of the pixel PX1 corresponds to the first display element, the partition walls P32 and P33 correspond to a pair of first partition walls, and the partition walls P12 and P13 correspond to a pair of third partition walls. Furthermore, when the display element 203 of the pixel PX1 corresponds to the first display element, the partition walls P31 and P32 correspond to a pair of first partition walls, and the partition walls P12 and P13 correspond to a pair of third partition walls.

[0088] Similarly, when the display element 201 of the pixel PX2 corresponds to the first display element, the partition walls P33 and P35 correspond to a pair of first partition walls, and the partition wall P34 corresponds to the second partition wall. Further, when the display element 202 of the pixel PX2 corresponds to the first display element, the partition walls P34 and P35 correspond to a pair of first partition walls. Furthermore, when the display element 203 of the pixel PX2 corresponds to the first display element, the partition walls P33 and P34 correspond to a pair of first partition walls.

[0089] FIG. 10 is a cross-sectional view showing another configuration example of the display device DSP along the line A-A' of FIG. 3. The display device DSP shown in FIG. 10 is different from the display device DSP shown in FIG. 4 in that the optical control element OD is formed as a multilayer body.

[0090] The optical control element OD includes a first layer L1 and a second layer L2. The second layer L2 is disposed above the first layer L1 in the third direction Z. The first layer L1 includes partition walls P11, P12, P13, an optical layer OL1, a light-shielding layer BM1, and a light-shielding layer BM2, similar to the example shown in FIG. 4. The second layer L2 includes partition walls P41, P42, P43, an optical layer OL2, and a plurality of light-shielding layers BM3.

[0091] The partition wall P41 overlaps with the partition wall P11. In the illustrated example, the partition wall P41 is located directly above the partition wall P11. The partition wall P42 overlaps with the partition wall P12. In the illustrated example, the partition wall P42 is located directly above the partition wall P12. The partition wall P43 overlaps with the partition wall P13. In the illustrated example, the partition wall P43 is located directly above the partition wall P13. Also, the partition walls P41, P42, and P43 are located on the light-shielding layer BM2.

[0092] In the illustrated example, the partition walls P41, P42, and P43 have the same shape and the same size as the partition walls P11, P12, and P13. Each of the partition walls P41, P42, and P43 has side surfaces S1 and S2 that are inclined with respect to the normal line 10N of the substrate 10, similar to the partition walls P11, P12, and P13.

[0093] The optical layer OL2 is located between a pair of adjacent partition walls P41 and P42 in the first direction X and is in contact with the side surface S2 of the partition wall P41 and the side surface S1 of the partition wall P42. Also, the optical layer OL2 is located between a pair of adjacent partition walls P42 and P43 in the first direction X and is in contact with the side surface S2 of the partition wall P42 and the side surface S1 of the partition wall P43. The optical layer OL2 overlaps the display elements 201 and 203 in the third direction Z and is disposed on the optical layer OL1. In the present embodiment, the optical layer OL2 surrounds the partition walls P41, P42, and P43.

[0094] The plurality of light-shielding layers BM3 are respectively located between the partition walls P41, P42, P43 and the polarizing plate 17. The plurality of light-shielding layers BM3 respectively overlap the partition walls P41, P42, P43. The plurality of light-shielding layers BM3 cover the upper surfaces of each of the partition walls P41, P42, P43. The peripheral portion of the light-shielding layer BM3 is surrounded by the optical layer OL2.

[0095] The optical control element OD shown in FIG. 10 is formed as a two-layer laminate. Therefore, the height of the partition wall shown in FIG. 10 can be made higher than the height of the partition wall shown in FIG. 4. When the height of the partition wall increases, among the light emitted from the light-emitting layer, the light rays reflected by the partition wall increase, and the viewing angle is further restricted. Therefore, the display device DSP shown in FIG. 10 can restrict the viewing angle more than the display device DSP shown in FIG. 4.

[0096] Also, even when the optical control element is formed as a single layer, it is possible to narrow the viewing angle by increasing the height of the partition wall. However, if the height of the partition wall is increased while maintaining the inclination angle of the side surface of the partition wall, the width of the bottom surface of the partition wall becomes large. Therefore, the width of the light-shielding layer covering the bottom surface of the partition wall becomes large, and the luminance of the display image may decrease. Also, the higher the height of the partition wall, the more difficult it is to process the partition wall.

[0097] On the other hand, when the optical control element is formed as a laminate, the width of the bottom surface of the partition wall can be made smaller than when the optical control element is formed as a single layer. Therefore, the width of the light-shielding layer covering the bottom surface of the partition wall can be made smaller, and a decrease in the luminance of the display image can be suppressed. Also, since the height of each partition wall when the optical control element is formed as a laminate is lower than the height of the partition wall when the optical control element is formed as a single layer, processing of the partition wall is relatively easy. Note that the optical control element OD may be formed as a laminate having three or more layers.

[0098] FIG. 11 is a cross-sectional view showing still another configuration example of the display device DSP along the line A-A' of FIG. 3. The display device DSP shown in FIG. 11 is different from the display device DSP shown in FIG. 10 in that it does not include the light-shielding layers BM1, BM2, and BM3 and includes a color filter layer CF and a light-shielding layer BMC instead of the polarizing plate 17.

[0099] The partition walls P11, P12, and P13 are disposed on the sealing layer 16. The partition wall P41 is disposed on the partition wall P11, the partition wall P42 is disposed on the partition wall P12, and the partition wall P43 is disposed on the partition wall P13.

[0100] The color filter layer CF is disposed on the optical control element OD. The color filter layer CF includes a color filter CF1 formed of a resin material colored blue and a color filter CF3 formed of a resin material colored red. The color filter CF1 overlaps the display element 201, and the color filter CF3 overlaps the display element 203. Although not shown, the color filter layer CF includes a color filter formed of a resin material colored green and overlapping the display element 202 shown in FIG. 3.

[0101] The light shielding layer BMC is located between color filters of different colors. In the example of FIG. 11, the light shielding layer BMC is located between the color filter CF1 and the color filter CF3 and is located between the optical control element OD and the color filter layer CF.

[0102] The light emitted from the light emitting layer EM1 may, depending on the emission angle, pass through the partition walls P12 and P42 without being reflected by the partition wall P12 like the light L4. In the absence of the color filter layer CF, the blue light L4 emitted from the light emitting layer EM1 and the red light emitted from the light emitting layer EM3 may mix, leading to a decrease in display quality.

[0103] The display device DSP shown in FIG. 11 includes a color filter layer CF. As a result, the blue light L4 emitted from the light emitting layer EM1 is absorbed by the red color filter CF3, so that the occurrence of color mixing can be prevented and a decrease in display quality can be suppressed.

[0104] In addition, the color filter layer CF has a function of suppressing a decrease in display quality due to external light reflection. Therefore, when the display device DSP includes the color filter layer CF, it may not include a polarizing plate. In this case, since there is no polarizing plate, it is possible to improve the brightness of the display device DSP.

[0105] Note that although the optical control element OD shown in FIG. 11 is formed as a two-layer multilayer body, the optical control element OD may be formed as a single layer, or may be formed as a multilayer body of three or more layers.

[0106] FIG. 12 is a diagram showing still another configuration example of the periphery of the pixel PX according to the first embodiment. In the display area DA, a partition wall 6 is arranged. The partition wall 6 overlaps with the rib 5 in plan view. The partition wall 6 is formed in a lattice shape surrounding the openings AP1, AP2, and AP3. It can also be said that the partition wall 6 has openings in the sub-pixels SP1, SP2, and SP3 similar to the rib 5. The partition wall 6 has conductivity and is electrically connected to the terminal of the common potential among the plurality of terminals provided in the peripheral area SA shown in FIG. 1.

[0107] The display element 201 of the sub-pixel SP1 includes the lower electrode LE1 and the organic layer OR1 (light-emitting layer EM1) described above, and the upper electrode UE1 overlapping the opening AP1. The display element 202 of the sub-pixel SP2 includes the lower electrode LE2 and the organic layer OR2 (light-emitting layer EM2) described above, and the upper electrode UE2 overlapping the opening AP2.

[0108] The display element 203 of the sub-pixel SP3 includes the lower electrode LE3 and the organic layer OR3 (light-emitting layer EM3) described above, and the upper electrode UE3 overlapping the opening AP3. Each of the display elements 201, 202, and 203 is surrounded by the partition wall 6 in plan view.

[0109] In the example of FIG. 12, the outer shapes of the lower electrodes LE1, LE2, and LE3 are shown by dotted lines, and the outer shapes of the organic layers OR1, OR2, OR3, and the upper electrodes UE1, UE2, and UE3 are shown by two-dot chain lines. Note that the outer shape of each of the illustrated lower electrode, organic layer, and upper electrode does not necessarily reflect the exact shape.

[0110] The lower electrodes LE1, LE2, and LE3 correspond to, for example, the anode of the display element. The upper electrodes UE1, UE2, and UE3 correspond to the cathode or the common electrode of the display element and are in contact with the partition wall 6.

[0111] The partition walls P11, P12, and P13 overlap the partition wall 6 located in the pixel PX1 in the third direction Z. In the illustrated example, in the pixel PX1, the partition wall P11 overlaps the peripheral edges of the lower electrode LE1, the organic layer OR1, and the upper electrode UE1 in the third direction Z. Also, in the pixel PX1, the partition wall P12 overlaps the peripheral edges of the lower electrodes LE1, LE2, LE3, the organic layers OR1, OR2, OR3, and the upper electrodes UE1, UE2, UE3 in the third direction Z. In the pixel PX1, the partition wall P13 overlaps the peripheral edges of the lower electrodes LE2, LE3, the organic layers OR2, OR3, and the upper electrodes UE2, UE3 in the third direction Z.

[0112] FIG. 13 is a cross-sectional view showing a configuration example of the display device DSP along the line D-D' of FIG. 12. Hereinafter, among the display elements 201, 202, and 203 of the pixel PX1, the display elements 201 and 203 will be described, but the display element 202 is also formed to have the same cross-section as the display elements 201 and 203. The partition wall 6 includes a conductive lower portion 61 disposed on the rib 5 and an upper portion 62 disposed on the lower portion 61. Both ends of the upper portion 62 protrude more than the side surface of the lower portion 61. Such a shape of the partition wall 6 is called an overhang shape.

[0113] In the illustrated example, the lower portion 61 has a first conductive layer 63 disposed on the rib 5 and a second conductive layer 64 disposed on the first conductive layer 63. For example, the first conductive layer 63 is formed thinner than the second conductive layer 64. Also, in the illustrated example, both ends of the first conductive layer 63 protrude from the side surface of the second conductive layer 64. The upper portion 62 has a thin film 65 disposed on the second conductive layer 64 and a thin film 66 disposed on the thin film 65. Both ends of the thin film 65 and the thin film 66 protrude from the side surface of the second conductive layer 64.

[0114] The organic layer OR1 contacts the lower electrode LE1 through the opening AP1, covers the lower electrode LE1 exposed from the opening AP1, and has its peripheral portion positioned on the rib 5. The upper electrode UE1 covers the organic layer OR1 and contacts the lower portion 61.

[0115] The organic layer OR3 contacts the lower electrode LE3 through the opening AP3, covers the lower electrode LE3 exposed from the opening AP3, and has its peripheral portion positioned on the rib 5. The upper electrode UE3 covers the organic layer OR3 and contacts the lower portion 61.

[0116] In the example of FIG. 13, the sub-pixel SP1 has a cap layer CP1 and a sealing layer SE1, and the sub-pixel SP3 has a cap layer CP3 and a sealing layer SE3. The cap layers CP1 and CP3 serve as optical adjustment layers for improving the light extraction efficiency of the light emitted from the organic layers OR1 and OR3, respectively. Note that the cap layers CP1 and CP3 may be omitted.

[0117] The cap layer CP1 is disposed on the upper electrode UE1. The cap layer CP3 is disposed on the upper electrode UE3.

[0118] The sealing layer SE1 is disposed on the cap layer CP1, contacts the partition wall 6, and continuously covers each member of the sub-pixel SP1. The sealing layer SE3 is disposed on the cap layer CP3, contacts the partition wall 6, and continuously covers each member of the sub-pixel SP3.

[0119] In the example of FIG. 13, a part of each of the organic layer OR1, the upper electrode UE1, and the cap layer CP1 is positioned on the partition wall 6 around the sub-pixel SP1. These portions are separated from the portions (the portions constituting the display element 201) located in the opening AP1 among the organic layer OR1, the upper electrode UE1, and the cap layer CP1. Similarly, a part of each of the organic layer OR3, the upper electrode UE3, and the cap layer CP3 is located on the partition wall 6 around the sub-pixel SP3, and these portions are separated from the portions located in the opening AP3 (the portions constituting the display element 203) among the organic layer OR3, the upper electrode UE3, and the cap layer CP3.

[0120] In the following description, the multilayer body including the organic layer OR1, the upper electrode UE1, and the cap layer CP1 is referred to as the laminated film FL1, and the multilayer body including the organic layer OR3, the upper electrode UE3, and the cap layer CP3 is referred to as the laminated film FL3.

[0121] The ends of the sealing layers SE1, SE3 and the ends of the laminated films FL1, FL3 are each located on the partition wall 6. In the example of FIG. 13, the laminated film FL1 and the sealing layer SE1 on the partition wall 6 between the sub-pixels SP1, SP3 are separated from the laminated film FL3 and the sealing layer SE3 on the partition wall 6.

[0122] The partition wall 6 and the sealing layers SE1, SE3 are covered by the resin layer 13. The resin layer 13 is covered by the sealing layer 14. The sealing layer 14 is covered by the resin layer 15.

[0123] The sealing layers SE1, SE3 and the sealing layer 14 are formed of an inorganic insulating material. The lower part 61 of the partition wall 6 is formed of a conductive material and is electrically connected to the upper electrodes UE1, UE3. The upper part 62 of the partition wall 6 is formed of, for example, a conductive material, but may be formed of an insulating material.

[0124] The optical control element OD is disposed on the resin layer 15. The partition walls P11, P12, the plurality of light-shielding layers BM1, and the plurality of light-shielding layers BM2 are respectively disposed directly above the partition wall 6.

[0125] In the display device DSP shown in FIGS. 12 and 13, the same effects as those described above can also be obtained.

[0126] FIG. 14 is a diagram showing still another configuration example around the pixel PX according to the first embodiment. The display device DSP shown in FIG. 14 is different from the display device DSP shown in FIG. 3 in that the layout of the sub-pixels SP1, SP2, and SP3 is different from the layout of the sub-pixels SP1, SP2, and SP3 shown in FIG. 3.

[0127] In the example of FIG. 14, the sub-pixels SP1, SP2, and SP3 are arranged in the first direction X. The sub-pixel SP2 is sandwiched between the sub-pixel SP1 and the sub-pixel SP3 along the first direction X. The apertures AP1, AP2, and AP3 are each formed in a rectangular shape having a long side parallel to the second direction Y. In the example of FIG. 14, the areas of the apertures AP1, AP2, and AP3 are equal.

[0128] The optical control element OD includes a partition wall P14 in addition to the partition walls P11, P12, and P13. The partition wall P14 is formed in the same manner as the partition walls P11, P12, and P13. The partition walls P11 and P12 sandwich the display element 203 of the pixel PX1 along the first direction X in a plan view. The partition walls P12 and P13 sandwich the display element 202 of the pixel PX1 along the first direction X in a plan view. The partition walls P13 and P14 sandwich the display element 201 of the pixel PX1 along the first direction X in a plan view.

[0129] The display device DSP shown in FIG. 14 can obtain the same effects as the display device DSP shown in FIG. 3. Note that the layout of the sub-pixels SP1, SP2, and SP3 is not limited to the examples shown in FIGS. 3 and 14, and various layouts can be applied.

[0130] [Second Embodiment] FIG. 15 is a diagram showing a configuration example of the display device DSP according to the second embodiment. The display device DSP according to the present embodiment is a liquid crystal display device and can be mounted on a television, a personal computer, an in-vehicle device, a tablet terminal, a smartphone, a mobile phone terminal, or the like. In this specification, as an example, a display device mounted on a vehicle such as an automobile will be described. Note that the same reference numerals are given to the same or similar elements as those of the display device DSP according to the first embodiment, and redundant descriptions are omitted.

[0131] The display device DSP includes a display panel PNL having a first substrate SUB1, a second substrate SUB2 facing the first substrate SUB1 in the third direction Z, and a liquid crystal layer LC sealed between the first substrate SUB1 and the second substrate SUB2. In the illustrated example, the shapes of the first substrate SUB1 and the second substrate SUB2 in plan view are both rectangular with long sides parallel to the first direction X. However, the shapes of the first substrate SUB1 and the second substrate SUB2 are not limited to this example, and may be, for example, rectangular with long sides parallel to the second direction Y, circular, elliptical, or the like.

[0132] The width of the first substrate SUB1 in the second direction Y is larger than the width of the second substrate SUB2 in the second direction Y. As a result, the first substrate SUB1 has a mounting area MA that does not overlap with the second substrate SUB2. An integrated circuit or a flexible circuit board (not shown) is mounted in the mounting area MA.

[0133] The display panel PNL has a display area DA for displaying an image and a frame-shaped peripheral area SA surrounding the display area DA. Both the display area DA and the peripheral area SA are formed in a portion where the first substrate SUB1 and the second substrate SUB2 overlap. The display area DA includes a plurality of pixels PX arranged in a matrix in the first direction X and the second direction Y.

[0134] As shown enlarged in FIG. 15, a plurality of scan lines GL and a plurality of signal lines SL are arranged in the display area DA. The plurality of scan lines GL extend in the first direction X and are arranged side by side in the second direction Y. The plurality of signal lines SL extend in the second direction Y and are arranged side by side in the first direction X. The plurality of signal lines SL intersect the plurality of scan lines GL.

[0135] Each pixel PX includes a switching element SW, a pixel electrode PE, a common electrode CE, and a capacitor CS. The switching element SW is constituted by, for example, a thin film transistor (TFT) and is electrically connected to a scanning line GL and a signal line SL. The pixel electrode PE is electrically connected to the switching element SW.

[0136] The liquid crystal layer LC is driven by an electric field generated between the pixel electrode PE and the common electrode CE. The capacitor CS is formed, for example, between an electrode having the same potential as the common electrode CE and an electrode having the same potential as the pixel electrode PE.

[0137] FIG. 16 is a diagram showing a configuration example around a pixel PX according to the second embodiment. The pixels PX1 and PX2 each include pixel electrodes PE1, PE2, and PE3 as the pixel electrode PE shown in FIG. 15.

[0138] In the example of FIG. 16, the pixel electrodes PE1, PE2, and PE3 are arranged in the first direction X. The pixel electrode PE2 is sandwiched between the pixel electrode PE1 and the pixel electrode PE3 along the first direction X. The pixel electrodes PE1, PE2, and PE3 are each formed in a rectangular shape having a long side parallel to the second direction Y. In the example of FIG. 16, the areas of the pixel electrodes PE1, PE2, and PE3 are equal. Note that the layout of the pixel electrodes PE1, PE2, and PE3 is not limited to the example shown in FIG. 16.

[0139] The display device DSP further includes partition walls P11, P12, P13, and P14 included in the optical control element OD. The partition walls P11, P12, P13, and P14 each extend in the second direction Y which is the direction in which the pixels PX1 and PX2 are arranged. The partition walls P11 and P12 sandwich the pixel electrode PE1 of the pixel PX1 along the first direction X in a plan view. The partition walls P12 and P13 sandwich the pixel electrode PE2 of the pixel PX1 along the first direction X in a plan view. The partition walls P13 and P14 sandwich the pixel electrode PE3 of the pixel PX1 along the first direction X in a plan view.

[0140] The adjacent partitions P11, P12, P13, and P14 overlap the pixel PX1 in the third direction Z, similar to the partitions P11, P12, and P13 according to the first embodiment shown in FIG. 3, but do not overlap the pixel PX2.

[0141] FIG. 17 is a cross-sectional view showing a configuration example of the display device DSP along the line E-E' in FIG. 16. The display device DSP includes the above-described display panel PNL, the lighting device BL, and the polarizing plates 117 and 127.

[0142] The first substrate SUB1 includes a first transparent substrate 110, insulating layers 111 and 112, a common electrode CE, a plurality of pixel electrodes PE, and an alignment film AL1. The first substrate SUB1 is disposed above the lighting device BL. The insulating layer 111 is disposed on the first transparent substrate 110. The common electrode CE is disposed on the insulating layer 111 across a plurality of pixels PX. However, the common electrode CE may be provided on the second substrate SUB2. The insulating layer 12 is disposed on the common electrode CE. The pixel electrodes PE1 and PE2 are disposed for each pixel PX on the insulating layer 12. In the illustrated example, the pixel electrodes PE1 and PE2 are disposed between the first transparent substrate 110 and the liquid crystal layer LC. The alignment film AL1 covers the pixel electrodes PE1 and PE2 and the insulating layer 112. The scanning line GL, the signal line SL, and the switching element SW shown in FIG. 15 are disposed between the first transparent substrate 110 and the common electrode CE.

[0143] The second substrate SUB2 includes a second transparent substrate 120, the above-described optical control element OD, a color filter layer CF, an overcoat layer OC1, and an alignment film AL2. The second transparent substrate 120 faces the first transparent substrate 110 in the third direction Z. The second substrate SUB2 is disposed above the first substrate SUB1. The alignment film AL2 is disposed below the second transparent substrate 120.

[0144] The optical control element OD includes the partition walls P11, P12, P13, P14 described above, a transparent optical layer OL1, and a plurality of light-shielding layers BM1, BM2. The optical control element OD is disposed between the second transparent substrate 120 and the liquid crystal layer LC. In the illustrated example, the optical control element OD is disposed under the second transparent substrate 120.

[0145] The bottom surface P12L of the partition wall P12 faces the liquid crystal layer LC in the third direction Z. The upper surface P12U of the partition wall P12 faces the second transparent substrate 120 in the third direction Z. The side surfaces S1, S2 of the partition wall P12 are each inclined with respect to the normal 110N of the first transparent substrate 110 such that the width W12L of the bottom surface P12L is larger than the width W12U of the upper surface P12U (W12L>W12U). That is, the partition wall P12 has a tapered cross section in which the width along the first direction X decreases as it moves away from the liquid crystal layer LC. The optical layer OL1 overlaps the pixel electrodes PE1, PE2 in the third direction Z.

[0146] The plurality of light-shielding layers BM2 (second light-shielding layer) are respectively located between the second transparent substrate 120 and the partition walls P11, P12, P13. The plurality of light-shielding layers BM2 overlap the partition walls P11, P12, P13 respectively. The light-shielding layer BM2 overlapping the partition wall P12 covers the entire upper surface P12U. The light-shielding layers BM2 overlapping the partition walls P11, P13 are formed in the same shape as the light-shielding layer BM2 overlapping the partition wall P12.

[0147] The color filter layer CF is disposed between the liquid crystal layer LC and the optical layer OL1. The blue color filter CF1 and the green color filter CF2 overlap the pixel electrodes PE1, PE2 respectively. Although not shown, the color filter layer CF includes a red color filter that overlaps the pixel electrode PE3. Also, the color filter layer CF may be provided on the first substrate SUB1.

[0148] The light-shielding layer BM1 (first light-shielding layer) is located between color filters of different colors. In the example of FIG. 17, the light-shielding layer BM1 is located between the color filter CF1 and the color filter CF2, and is located between the partition walls P11, P12, P13 and the color filter layer CF. The plurality of light-shielding layers BM1 are respectively superimposed on the partition walls P11, P12, P13. The light-shielding layer BM1 superimposed on the partition wall P12 covers the entire surface of the bottom surface P12L. The light-shielding layers BM1 superimposed on the partition walls P11 and P13 are formed in the same shape as the light-shielding layer BM1 superimposed on the partition wall P12.

[0149] The overcoat layer OC1 is disposed between the color filter layer CF and the liquid crystal layer LC. The overcoat layer OC1 covers the color filter layer CF. The alignment layer AL2 covers the overcoat layer OC1. The liquid crystal layer LC is disposed between the first transparent substrate 110 and the second transparent substrate 120. In the illustrated example, it is disposed between the alignment layer AL1 and the alignment layer AL2.

[0150] The polarizing plate 117 is adhered to the lower surface of the first transparent substrate 110 by the adhesive AD1. The polarizing plate 127 is adhered to the upper surface of the second transparent substrate 120 by the adhesive AD2. The polarization axes of the polarizing plates 117 and 127 are orthogonal to each other, for example, in the X-Y plane.

[0151] The first transparent substrate 110 and the second transparent substrate 120 are insulating substrates such as glass substrates and plastic substrates. The insulating layer 111 includes an inorganic insulating layer and an organic insulating layer. The insulating layer 112 is an inorganic insulating layer. The pixel electrodes PE1, PE2, and the common electrode CE are transparent electrodes. The overcoat layer OC1 is formed of a transparent resin material. The alignment layers AL1 and AL2 are horizontal alignment layers having an alignment regulating force substantially parallel to the X-Y plane, but are not limited to this example.

[0152] FIG. 18 is a cross-sectional view showing a configuration example of the display device DSP along the line E-E' of FIG. 16. The optical layer OL1 overlaps the pixel electrodes PE1 and PE2 of the pixel PX2 in the third direction Z. Thus, among the optical control elements OD, the optical layer OL1 overlaps the pixel PX2, and the partition walls do not overlap the pixel PX2.

[0153] The display device DSP according to the second embodiment can obtain the same effects as the display device DSP according to the first embodiment.

[0154] In the above example, for example, each of the pixel electrodes PE1, PE2, and PE3 of the pixel PX1 corresponds to the first pixel electrode, each of the pixel electrodes PE1, PE2, and PE3 of the pixel PX2 corresponds to the second pixel electrode, and the partition walls P11, P12, P13, and PE14 correspond to the first partition wall. When the pixel electrode PE1 of the pixel PX1 corresponds to the first pixel electrode, the partition walls P11 and P12 correspond to a pair of first partition walls. Also, when the pixel electrode PE2 of the pixel PX1 corresponds to the first pixel electrode, the partition walls P12 and P13 correspond to a pair of first partition walls. Further, when the pixel electrode PE3 of the pixel PX1 corresponds to the first pixel electrode, the partition walls P13 and P14 correspond to a pair of first partition walls.

[0155] FIG. 19 is a cross-sectional view showing another configuration example of the display device DSP along the line E-E' of FIG. 16. The display device DSP shown in FIG. 19 is different from the display device DSP shown in FIG. 17 in that the optical control element OD includes an overcoat layer OC2.

[0156] The optical control element OD further includes an overcoat layer OC2. The overcoat layer OC2 covers the partition walls P11, P12, P13 and the optical layer OL1, and is disposed between the optical layer OL1 and the color filter layer CF. The overcoat layer OC2 is formed of a transparent resin material such as an acrylic resin, for example.

[0157] The overcoat layer OC2 has a function of flattening the unevenness generated by the partition walls P11, P12, P13 and the optical layer OL1 in the optical control element OD. Also, the overcoat layer OC2 can prevent the dye of the color filter layer CF from moving to the optical layer OL1.

[0158] The display device DSP shown in FIG. 19 can obtain the same effects as the display device DSP shown in FIG. 17.

[0159] FIG. 20 is a cross-sectional view showing still another configuration example of the display device DSP along the line E-E' of FIG. 16. The display device DSP shown in FIG. 20 is different from the display device DSP shown in FIG. 17 in that the optical control element OD is formed as a multilayer body.

[0160] The optical control element OD includes a first layer L1 and a second layer L2. The configurations of each of the first layer L1 and the second layer L2 are the same as those of the first layer L1 and the second layer L2 of the display device DSP according to the first embodiment shown in FIG. 10.

[0161] The display device DSP shown in FIG. 20 can obtain the same effects as the display device DSP shown in FIG. 10.

[0162] As described above, based on the display device described as an embodiment of the present invention, all display devices that can be appropriately designed and modified by those skilled in the art also belong to the scope of the present invention as long as they include the gist of the present invention.

[0163] Within the scope of the idea of the present invention, those skilled in the art can conceive of various modifications, and these modifications are also understood to belong to the scope of the present invention. For example, for the above-described embodiments, those in which those skilled in the art appropriately add, delete, or modify the components, or add, omit, or change the conditions of the process also belong to the scope of the present invention as long as they have the gist of the present invention.

[0164] In addition, with regard to other operational effects brought about by the aspects described in the above embodiments, those that are obvious from the description of this specification or that can be appropriately conceived by those skilled in the art are naturally understood to be brought about by the present invention.

Description of Reference Numerals

[0165] DSP…display device, PNL…display panel, PX, PX1, PX2…pixel, SP, SP1, SP2, SP3…sub-pixel, 10…substrate, 5…rib, 20, 201, 202, 203…display element, EM1, EM2, EM3…light-emitting layer, L1, L2, L3, L4…light, SUB1…first substrate, SUB2…second substrate, LC…liquid crystal layer, PE1, PE2, PE3…pixel electrode, OC1, OC2…overcoat layer, CF…color filter layer, CF1, CF3…color filter, OD…optical control element, OL1, OL2…optical layer, P11~P14, P21, P22, P31~P35, P41~P43…partition wall, S1, S2…side surface, BM1, BM2, BM3, BMC…light-shielding layer.

Claims

1. A substrate, a first display element disposed above the substrate, a sealing layer covering the first display element, and an optical control element superimposed on the sealing layer, wherein the optical control element includes a plurality of partition walls including a pair of first partition walls sandwiching the first display element in plan view, and an optical layer positioned between the pair of first partition walls, in contact with side surfaces of the first partition walls, and superimposed on the first display element, wherein a refractive index of each of the partition walls is smaller than a refractive index of the optical layer, a display device.

2. The first display element includes a lower electrode, an organic layer including a light-emitting layer superimposed on the lower electrode, and an upper electrode superimposed on the organic layer, and further includes a rib surrounding the lower electrode and the light-emitting layer in plan view, wherein the first partition wall is superimposed on the rib, the display device according to claim 1.

3. Each of the partition walls has a tapered cross section whose width decreases as it moves away from the sealing layer, wherein the side surface is inclined with respect to a normal line of the substrate, the display device according to claim 1.

4. Further comprising a polarizing plate adhered to the optical control element, the display device according to claim 1.

5. Further comprising a color filter superimposed on the first display element, the display device according to claim 1.

6. The refractive index of the optical layer is equal to the refractive index of the sealing layer, the display device according to claim 1.

7. Each of the partition walls has a bottom surface facing the sealing layer, wherein the optical control element further includes a first light-shielding layer covering the bottom surface, the display device according to claim 1.

8. The plurality of partition walls further includes a second partition wall positioned between the pair of first partition walls in plan view and superimposed on the first display element, the display device according to claim 1.

9. The plurality of partition walls further includes a pair of third partition walls intersecting the pair of first partition walls in plan view and sandwiching the first display element, the display device according to claim 1 or 8.

10. Further comprising a second display element adjacent to the first display element, wherein the plurality of partition walls do not include a partition wall sandwiching the second display element in plan view, and the optical layer is superimposed on the second display element, the display device according to claim 1.

11. A first transparent substrate, a second transparent substrate facing the first transparent substrate, a liquid crystal layer disposed between the first transparent substrate and the second transparent substrate, a first pixel electrode disposed between the first transparent substrate and the liquid crystal layer, ​ An optical control element disposed between the second transparent substrate and the liquid crystal layer, and the optical control element includes a plurality of partition walls including a pair of first partition walls sandwiching the first pixel electrode in a plan view, an optical layer positioned between the pair of first partition walls, in contact with side surfaces of the first partition walls, and overlapping the first pixel electrode, and a refractive index of each of the partition walls is smaller than a refractive index of the optical layer, a display device.

12. each of the partition walls has a tapered cross section whose width decreases as it moves away from the liquid crystal layer, the side surfaces are inclined with respect to a normal line of the first transparent substrate, the display device according to claim 11.

13. Further, a color filter disposed between the liquid crystal layer and the optical layer and overlapping the first pixel electrode is provided, the display device according to claim 11.

14. Further, an overcoat layer covering the color filter and disposed between the color filter and the liquid crystal layer is provided, the display device according to claim 13.

15. the optical control element further includes an overcoat layer covering the plurality of partition walls and the optical layer and disposed between the optical layer and the color filter, the display device according to claim 13.

16. each of the partition walls has a bottom surface facing the liquid crystal layer, the optical control element further includes a first light-shielding layer covering the bottom surface, the display device according to claim 12.

17. Further, a second pixel electrode adjacent to the first pixel electrode is provided, the plurality of partition walls do not include a partition wall sandwiching the second pixel electrode in a plan view, the optical layer overlaps the second pixel electrode, the display device according to claim 11.

18. each of the partition walls further has an upper surface located opposite to the bottom surface, the optical control element further includes a second light-shielding layer covering the upper surface of the partition wall, the display device according to claim 7 or 16.

19. a refractive index difference between the partition wall and the optical layer is 0.2 or more, the display device according to claim 1 or 11.

20. the partition wall is a light absorber, the display device according to claim 1 or 11.

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