Circuit device and oscillator

Abstract

To provide a circuit device or the like capable of realizing appropriate gain correction of a DTC circuit.SOLUTION: A circuit device 20 includes: a DTC circuit 30 for adjusting a delay time of a reference clock signal based on a DTC code; a code generation circuit 40 for generating the DTC code based on division ratio setting information; a phase comparator circuit 50 for outputting a sampling voltage, having a sampling circuit 52 for sampling a slope signal based on the reference clock signal with delay time adjusted; a clock signal generation circuit 60 for generating a clock signal whose frequency is controlled based on the sampling voltage; a division circuit 70 for generating a feedback clock signal by dividing the clock signal; a slope signal generation circuit 72 for generating a slope signal based on the feedback clock signal; and a correction circuit 80 for extracting code information based on the sampling voltage, selecting the code information according to the DTC code, and generating a gain correction value of the DTC circuit based on the selected code information.SELECTED DRAWING: Figure 1

Description

[Technical Field]

[0001] The present invention relates to a circuit device, an oscillator, and the like. [Background technology]

[0002] Voltage sampling PLLs, such as sampling PLLs and subsampling PLLs, have been known for some time. For example, Non-Patent Document 1 discloses a PLL equipped with a DTC (Digital-to-Time Converter) circuit. In Non-Patent Document 1, gain correction is performed in the DTC circuit to correct an error in the delay time of a reference clock signal output by the DTC circuit. Specifically, the code information obtained by comparing a sampling voltage, which is the phase comparison result, with a reference voltage is subjected to logic processing in a DCL (Digital Correlation Loop) circuit, and the result is fed back to the DTC circuit as a gain correction value, thereby achieving gain correction in the DTC circuit. [Prior art documents] [Non-patent literature]

[0003] [Non-Patent Document 1] Chang. Et al, “A Fractional-N Divider-Less Phase-Locked Loop With a Subsampling Phase Detector”, IEEE Journal of Solid-State Circuits Vol.49, Issue: 12, p.2964-2975 (December 2014) Summary of the Invention [Problem to be solved by the invention]

[0004] In the conventional technology described in Non-Patent Document 1, weighting is performed using a DTC code in the DCL circuit. However, the result of comparing the sampled voltage with the reference voltage does not necessarily indicate a large gain error when the DTC code is large. Therefore, it was found that weighting by simply multiplying the digital code value may result in an inaccurate value being used as code information in subsequent processing. [Means for solving the problem]

[0005] One aspect of the present disclosure relates to a circuit device including: a DTC circuit that adjusts a delay time of a reference clock signal based on a DTC code; a code generation circuit that generates the DTC code based on division ratio setting information; a phase comparison circuit having a sampling circuit that samples a slope signal based on the reference clock signal with the adjusted delay time and outputs a sampling voltage of the sampling circuit; a clock signal generation circuit that generates a clock signal whose frequency is controlled based on the sampling voltage; a frequency divider circuit that divides the clock signal to generate a feedback clock signal; a slope signal generation circuit that generates the slope signal based on the feedback clock signal; and a correction circuit that extracts code information based on the sampling voltage, selects the code information in accordance with the DTC code, and generates a gain correction value that corrects a gain of the DTC circuit based on the selected code information.

[0006] Another aspect of the present disclosure relates to an oscillator including the circuit device described above and an oscillator, wherein the circuit device includes an oscillation circuit that outputs an oscillation clock signal generated by oscillating the oscillator as the reference clock signal. [Brief explanation of the drawings]

[0007] [Figure 1] 1 shows an example of the configuration of a circuit device according to an embodiment of the present invention. [Figure 2] 3 shows a detailed configuration example of the circuit device of the present embodiment. [Figure 3] 3 shows a detailed configuration example of the circuit device of the present embodiment. [Figure 4] 1 shows an example of the configuration of a slope signal generation circuit and a phase comparison circuit. [Figure 5] 5A to 5C are signal waveform diagrams illustrating the operations of a slope signal generating circuit and a phase comparison circuit. [Figure 6] Example of DTC circuit configuration. [Figure 7] FIG. 10 is an explanatory diagram of gain correction in the DTC circuit. [Figure 8] FIG. 4 is a signal waveform diagram illustrating the operation of the DTC circuit. [Figure 9] Example of DTC code and sampling voltage characteristics when there is a gain error. [Figure 10] Example of DTC code and sampling voltage characteristics when there is a gain error. [Figure 11] Example of DTC code and sampling voltage characteristics when there is a gain error. [Figure 12] Example of DTC code and sampling voltage characteristics when the gain error is 0%. [Figure 13] Example of DTC code and sampling voltage characteristics when the gain error is +10%. [Figure 14] Example of DTC code and sampling voltage characteristics when the gain error is -10%. [Figure 15] 1 shows an example of a compensation circuit configuration. [Figure 16] 10 is a flowchart illustrating the operation of the correction circuit. [Figure 17] 10 is a flowchart illustrating the operation of the correction circuit. [Figure 18] 3 shows an example of the configuration of an oscillator according to the present embodiment. DETAILED DESCRIPTION OF THE INVENTION

[0008] The present embodiment will be described below. Note that the present embodiment described below does not unduly limit the content of the claims. Furthermore, not all of the configurations described in the present embodiment are necessarily essential components.

[0009] 1.Circuit device FIG. 1 shows an example of the configuration of a circuit device 20 according to this embodiment. The circuit device 20 includes a DTC circuit 30, a code generation circuit 40, a phase comparison circuit 50, a clock signal generation circuit 60, a frequency divider circuit 70, a slope signal generation circuit 72, and a correction circuit 80. A PLL (Phase Locked Loop) circuit is realized by the circuit device 20 having this configuration. The circuit device 20 is, for example, an integrated circuit device known as an IC (Integrated Circuit). For example, the circuit device 20 is an IC manufactured by a semiconductor process, and is a semiconductor chip in which circuit elements are formed on a semiconductor substrate.

[0010] The DTC circuit 30 is a digital time conversion circuit that adjusts the delay time of the reference clock signal RFCK based on a DTC code DC. The DTC code is a digital code, and DTC stands for Digital-to-Time Converter. The reference clock signal RFCK is a clock signal that serves as a reference for phase synchronization of, for example, a PLL circuit, and is, for example, a signal based on an oscillation clock signal generated by oscillating an oscillator. The DTC circuit 30 adjusts the reference clock signal RFCK by delaying, for example, the edge timing by the delay time represented by the DTC code. For example, the DTC circuit 30 adjusts the delay time to reduce the phase error between the reference clock signal RFCK and the feedback clock signal FBCK of the PLL circuit. The DTC circuit 30 then outputs a reference clock signal RFCKD with the adjusted delay time. The edge timing of the reference clock signal RFCKD is delayed by, for example, the delay time represented by the DTC code, compared to the reference clock signal RFCK.

[0011] The code generation circuit 40 is a circuit that generates the DTC code DC. For example, the code generation circuit 40 generates the DTC code DC based on the division ratio setting information SDIV. The division ratio setting information SDIV is information for setting a division ratio for setting a multiplication factor in the PLL circuit. The division ratio setting information SDIV can also be called a division ratio setting code or a frequency control code. The division ratio setting information SDIV sets the frequency of the clock signal CK generated by the PLL circuit. For example, in the case of a fractional-N type PLL circuit, the division ratio setting information SDIV sets the integer part (N) and the decimal part (f) of the division ratio. This makes it possible to generate a clock signal CK having a frequency obtained by multiplying the frequency of the reference clock signal RFCK by any desired multiplication factor, including the decimal part.

[0012] The phase comparator circuit 50 includes a sampling circuit 52 that samples the slope signal SLP based on the reference clock signal RFCKD, the delay of which has been adjusted. The phase comparator circuit 50 outputs a sampling voltage VSA from the sampling circuit 52. This sampling voltage VSA corresponds to, for example, the phase difference between the reference clock signal RFCKD and the feedback clock signal FBCK of the PLL circuit, and indicates the phase comparison result of the phase comparator circuit 50. For example, the sampling circuit 52 samples the slope signal SLP at the timing of the edge of the reference clock signal RFCK. The phase comparator circuit 50 outputs the voltage obtained by sampling the slope signal SLP using the sampling circuit 52 as the sampling voltage VSA. Specifically, the sampling circuit 52 includes a sampling switch SS and a sampling capacitor CS. The sampling switch SS is turned on when the reference clock signal RFCKD is at a first voltage level (e.g., low level) and turned off when the reference clock signal RFCKD is at a second voltage level (e.g., high level). One end of the sampling capacitor CS is connected to a sampling node of the sampling voltage VSA. By providing such a sampling switch SS and capacitor CS, the voltage of the slope signal SLP at the timing when the reference clock signal RFCKD changes from the first voltage level to the second voltage level can be sampled as a sampling voltage VSA. This sampling voltage VSA is then held in the capacitor CS and output.

[0013] The clock signal generation circuit 60 is a circuit that generates a clock signal CK. For example, the clock signal generation circuit 60 generates a clock signal CK whose frequency is controlled based on the sampling voltage VSA. Specifically, the clock signal generation circuit 60 generates a clock signal CK whose frequency is obtained by multiplying the frequency of the reference clock signal RFCK by a multiplication factor corresponding to the division ratio of the division ratio setting information SDIV, and which is phase-synchronized with the reference clock signal RFCK.

[0014] The frequency divider circuit 70 divides the frequency of the clock signal CK to generate a feedback clock signal FBCK. For example, the frequency divider circuit 70 divides the frequency of the clock signal CK by a division ratio set by the division ratio setting information SDIV to generate the feedback clock signal FBCK and outputs it to the slope signal generation circuit 72.

[0015] The slope signal generation circuit 72 is a circuit that generates a slope signal SLP, and is, for example, a circuit called an LSG (Linear Slope Generator). For example, the slope signal generation circuit 72 generates the slope signal SLP based on the feedback clock signal FBCK. The feedback clock signal FBCK is a square-wave clock signal, and the slope signal generation circuit 72 generates a slope signal SLP having, for example, a linear slope from this square-wave feedback clock signal FBCK. For example, the slope signal generation circuit 72 generates the slope signal SLP by inclining the edge of the square-wave feedback clock signal FBCK. Note that the slope of the slope signal SLP may be approximately linear.

[0016] The correction circuit 80 corrects the gain of the DTC circuit 30. For example, the correction circuit 80 extracts sign information based on the sampled voltage VSA of the phase comparator circuit 50. For example, the correction circuit 80 compares the sampled voltage VSA with a reference voltage to extract sign information indicating whether the sampled voltage VSA is greater or less than the reference voltage. The reference voltage corresponds to the voltage output as the sampled voltage when the PLL circuit is locked, for example, and the sign information indicates whether the phase is advanced or delayed from the reference voltage at that time. The correction circuit 80 then selects the sign information based on the DTC code DC and outputs a gain correction value GC that corrects the gain of the DTC circuit 30 based on the selected sign information. The DTC circuit 30 performs digital time conversion with the gain corrected using the gain correction value GC to convert the digital value of the DTC code DC into a delay time and output a reference clock signal RFCKD in which the edge of the reference clock signal RFCK is delayed by the delay time. For example, the gain of the DTC circuit 30 can be said to be the ratio of the change in delay time to the change in the digital value of the DTC code DC, and this gain is corrected by the gain correction value GC.

[0017] As described above, in this embodiment, the code generation circuit 40 generates the DTC code DC based on the division ratio setting information SDIV, and the DTC circuit 30 adjusts the delay time of the reference clock signal RFCK based on the DTC code DC. The phase comparison circuit 50 samples the slope signal SLP from the slope signal generation circuit 72 based on the delay-adjusted reference clock signal RFCKD and outputs the sampling voltage VSA. The clock signal generation circuit 60 generates a frequency-controlled clock signal CK based on the sampling voltage VSA. The frequency divider circuit 70 divides the clock signal CK to generate the feedback clock signal FBCK. The slope signal generation circuit 72 generates the slope signal SLP based on the feedback clock signal FBCK and outputs it to the phase comparison circuit 50. This achieves a voltage sampling PLL circuit, enabling the generation of a clock signal CK phase-synchronized with the reference clock signal RFCK. In this embodiment, the correction circuit 80 extracts sign information based on the sampling voltage VSA and generates a gain correction value GC for the DTC circuit 30 based on the sign information selected according to the DTC code DC. As described above, in this embodiment, the correction circuit 80 does not multiply the sign information weighted by the DTC code DC, but rather selects whether to use the sign information at that time based on the DTC code DC. This makes it possible to calculate an accurate gain correction value GC without depending on the output characteristics of the phase comparator circuit 50, which outputs the sampling voltage VSA for extracting the sign information. Furthermore, the multiplier required in the prior art is no longer necessary, allowing the circuit device 20 to be made smaller.

[0018] 2 shows a detailed configuration example of the circuit device 20. In FIG. 2, a clock signal generating circuit 60 includes a charge pump circuit 62, a loop filter circuit 64, and a voltage controlled oscillator circuit 66.

[0019] The charge pump circuit 62 outputs a current corresponding to the sampling voltage VSA from the phase comparison circuit 50. For example, the charge pump circuit 62 outputs a current that increases as the sampling voltage VSA increases, as a charge pump current. For example, the charge pump circuit 62 has an amplifier circuit called a transconductor. This amplifier circuit is a circuit that performs voltage-to-current conversion according to, for example, transconductance Gm, and converts the sampling voltage VSA into a current and outputs it.

[0020] The loop filter circuit 64 is a filter circuit of the PLL circuit, and generates a control voltage that controls the frequency of the voltage-controlled oscillator circuit 66. The loop filter circuit 64 generates the control voltage by integrating and smoothing the charge pump current from the charge pump circuit 62. The loop filter circuit 64 can be realized, for example, by an RC low-pass filter configured with a capacitor and a resistor.

[0021] A voltage-controlled oscillator circuit 66, also known as a VCO circuit, generates an oscillation clock signal (CK) controlled by a control voltage from a loop filter circuit 64. The voltage-controlled oscillator circuit 66 may be implemented as an LC oscillator circuit using an inductor and a capacitor, or as a loop oscillator circuit with multiple inverter circuits connected in a loop. The output circuit 100 buffers the clock signal CK and outputs it to the outside as an output clock signal CKQ. For example, the output circuit 100 may output the output clock signal CKQ in a single-ended CMOS signal format. Alternatively, the output circuit 100 may output the output clock signal CKQ in a signal format such as LVDS (Low Voltage Differential Signaling) or PECL (Positive Emitter Coupled Logic).

[0022] The code generation circuit 40 includes a delta-sigma modulation circuit 42 and an integrator 44. The delta-sigma modulation circuit 42 performs delta-sigma modulation based on the decimal part (f) of the division ratio set by the division ratio setting information SDIV. The integrator 44 generates the DTC code DC by integrating the output value of the delta-sigma modulation circuit 42. Furthermore, the divider circuit 70 performs integer division based on the integer part (N) of the division ratio set by the division ratio setting information SDIV. This configuration makes it possible to realize a fractional-N type PLL circuit that can output a clock signal CK having a frequency obtained by multiplying the frequency of the input reference clock signal RFCK by any multiplication factor, including the decimal part.

[0023] For example, the delta-sigma modulation circuit 42 can be realized by a differentiator (adder) that calculates the difference between an input value and a feedback value, an integrator that performs time integration of the difference result, a quantizer that calculates the quantization error of the integration result, and a delay device that feeds back the output value. The delta-sigma modulation circuit 42 can be realized by a circuit that performs, for example, first-, second-, or third-order delta-sigma modulation. For example, the frequency divider circuit 70 and the delta-sigma modulation circuit 42 form a fractional frequency divider, which can realize a fractional-N PLL circuit. For example, the delta-sigma modulation circuit 42 performs delta-sigma modulation based on the decimal part of the division ratio of the division ratio setting information SDIV and outputs delta-sigma modulated data. For example, the delta-sigma modulation circuit 42 outputs n-bit delta-sigma modulated data. For example, suppose the delta-sigma modulation circuit 42 outputs 4-bit delta-sigma modulated data using third-order delta-sigma modulation. In this case, digital data is output such that, for example, (1101) = -3, (1110) = -2, (1111) = -1, (0000) = 0, (0001) = +1, (0010) = +2, (0011) = +3, and (0100) = +4. The integrator 44 integrates the delta-sigma modulated data value and outputs the DTC code DC. The integrator 44 also outputs a carry signal when the integrated delta-sigma modulated data value exceeds a value within a phase range of 0 to 2π, for example. The integer division ratio of the frequency divider circuit 70 is set by adding the value of the carry signal to the integer part of the frequency division ratio of the frequency division ratio setting information SDIV. In this way, the code generation circuit 40 includes a delta-sigma modulation circuit 42 that performs delta-sigma modulation based on the division ratio setting information SDIV, and generates a DTC code and sets the division ratio of the divider circuit 70 based on the delta-sigma modulation data from the delta-sigma modulation circuit 42.

[0024] 2, the correction circuit 80 includes a sign information extraction unit 82, a selection unit 86, and a correction value generation unit 90. The sign information extraction unit 82 extracts sign information based on the sampled voltage VSA from the phase comparison circuit 50. For example, the sign information extraction unit 82 extracts sign information by comparing the sampled voltage VSA with a reference voltage. The sign information extraction unit 82 generates sign information such that, when the sampled voltage VSA is higher than the reference voltage, it is +1, and when the sampled voltage VSA is lower than the reference voltage, it is -1. The selection unit 86 selects the sign information. For example, the selection unit 86 selects the sign information based on the DTC code DC. The selection of the sign information involves, for example, determining whether or not to use the sign information obtained based on the sampled voltage VSA to generate the gain correction value GC. For example, when the DTC code DC is within a predetermined range, the correction circuit 80 generates the gain correction value GC using the extracted sign information. However, when the DTC code DC is within a different range, the correction circuit 80 does not generate the gain correction value GC using the sign information. The correction value generation unit 90 generates the gain correction value GC. For example, the correction value generation unit 90 generates the gain correction value GC based on the selected code information. For example, the correction value generation unit 90 performs an averaging process on the code information and an update process on the gain correction value GC based on the result of the averaging process on the code information, thereby generating the gain correction value GC and outputting it to the DTC circuit 30.

[0025] Fig. 3 also shows a detailed configuration example of the circuit device 20 of this embodiment. In Fig. 3, in addition to the configuration described in Figs. 1 and 2, a phase comparison circuit 54 is further provided in the circuit device 20. Furthermore, a charge pump circuit 63 is further provided in the clock signal generation circuit 60. Note that the circuit device 20 is not limited to the configurations shown in Figs. 1 to 3, and various modifications are possible, such as omitting some of the components, adding other components, or changing the components to other types of components.

[0026] The phase comparator circuit 54, which is a second phase comparator circuit, outputs a phase difference signal PDS based on a phase comparison between the reference clock signal RFCK and the feedback clock signal FBCK from the frequency divider circuit 70. For example, the phase comparator circuit 54 outputs an up signal or a down signal as the phase difference signal PDS based on the phase comparison between the reference clock signal RFCK and the feedback clock signal FBCK. For example, the phase comparator circuit 54 outputs an up signal when the feedback clock signal FBCK lags behind the reference clock signal RFCK, and outputs a down signal when the feedback clock signal FBCK leads the reference clock signal RFCK.

[0027] The phase comparator circuit 54 includes a dead zone detection circuit 56. The dead zone detection circuit 56 detects whether the phase difference between the reference clock signal RFCK and the feedback clock signal FBCK of the clock signal CK falls within a dead zone. The phase difference can also be referred to as a phase error. A dead zone is an insensitive zone, e.g., a range in which the phase difference between the reference clock signal RFCK and the feedback clock signal FBCK is equal to or less than a threshold value. The dead zone detection circuit 56 generates such a dead zone and determines whether the phase difference between the reference clock signal RFCK and the feedback clock signal FBCK falls within the dead zone. The dead zone is generated based on the delay time of a delay circuit provided in the dead zone detection circuit 56. If the phase difference does not fall within the dead zone, the phase comparator circuit 54 outputs a phase difference signal PDS based on the phase comparison between the reference clock signal RFCK and the feedback clock signal FBCK.

[0028] The charge pump circuit 63, which is a second charge pump circuit, performs a charge pump operation in response to the phase difference signal PDS from the phase comparison circuit 54. For example, when an up signal is input as the phase difference signal PDS, the charge pump circuit 63 generates, as a charge pump current, an up current that flows from the high-potential side power supply to the output node of the charge pump circuit 63 during the active period of the up signal. On the other hand, when a down signal is input as the phase difference signal PDS, the charge pump circuit 63 generates, as a charge pump current, a down current that flows from the output node of the charge pump circuit 63 to the low-potential side power supply during the active period of the down signal.

[0029] The clock signal generation circuit 60 generates a clock signal CK having a frequency controlled based on the charge pump current of the charge pump circuit 62, which is a first charge pump circuit, or the charge pump current of the charge pump circuit 63, which is a second charge pump circuit. The circuit device 20 performs a first synchronization operation in a first feedback loop including the phase comparison circuit 50, the charge pump circuit 62, the loop filter circuit 64, the voltage-controlled oscillator circuit 66, the frequency divider circuit 70, and the slope signal generation circuit 72. The circuit device 20 also performs a second synchronization operation in a second feedback loop including the phase comparison circuit 54, the charge pump circuit 63, the loop filter circuit 64, the voltage-controlled oscillator circuit 66, and the frequency divider circuit 70. The first synchronization operation is, for example, a sampling phase-locked loop (SPLL) operation, and the second synchronization operation is, for example, a frequency-locked loop (FLL) operation. Here, the operation of a voltage-sampling PLL, such as a sampling PLL or a sub-sampling PLL, will be referred to as an SPLL operation, as appropriate. The clock signal generation circuit 60 generates a clock signal CK having a frequency controlled based on the charge pump current of the charge pump circuit 62 during the first synchronous operation, and generates a clock signal CK having a frequency controlled based on the charge pump current of the charge pump circuit 63 during the second synchronous operation.

[0030] For example, after power-on, the circuit device 20 performs an FLL operation, which is a second synchronization operation in the second feedback loop. For example, the phase comparator circuit 54 outputs an up signal UP and a down signal DN based on a phase comparison between the reference clock signal RFCK and the feedback clock signal FBCK, causing the charge pump circuit 63 to perform a charge pump operation. A charge pump current generated by this charge pump operation is input to the loop filter circuit 64, generating a control voltage. The voltage-controlled oscillator circuit 66 oscillates based on this control voltage to generate a clock signal CK. This clock signal CK is fed back to the phase comparator circuit 54 via the frequency divider circuit 70 as a feedback clock signal FBCK. This performs an FLL operation, which brings the frequency of the feedback clock signal FBCK closer to the frequency of the reference clock signal RFCK.

[0031] Specifically, the dead zone detection circuit 56 detects whether the phase difference between the reference clock signal RFCK and the feedback clock signal FBCK has entered the dead zone, and during the non-dead zone period when the phase difference has not entered the dead zone, the charge pump circuit 63 performs charge pump operation, thereby performing FLL operation in the second feedback loop.

[0032] This FLL operation causes the frequency of the feedback clock signal FBCK to approach the frequency of the reference clock signal RFCK, and it is detected that the phase difference has entered the dead zone. During this dead zone period when the phase difference has entered the dead zone, the charge pump circuit 62 outputs a charge pump current corresponding to the sampling voltage VSA from the phase comparison circuit 50. This charge pump current is then input to the loop filter circuit 64, which generates a control voltage. The voltage-controlled oscillator circuit 66 oscillates based on this control voltage to generate the clock signal CK. This allows phase synchronization by the SPLL to further bring the phases of the reference clock signal RFCK and the feedback clock signal FBCK closer together.

[0033] In this way, FLL operation by the second feedback loop is performed until the phase difference between the reference clock signal RFCK and the feedback clock signal FBCK enters the dead zone. Then, when it is detected that the phase difference has entered the dead zone, the PLL operation is switched from FLL operation by the second feedback loop to SPLL operation by the first feedback loop. SPLL operation by the first feedback loop allows for a larger gain in the PLL compared to FLL operation by the second feedback loop, thereby reducing in-band noise of the PLL. That is, the gain in SPLL operation is set by the slope of the slope signal SLP, the transconductance Gm of the amplifier circuit, and other factors. For example, the gain can be set higher by increasing the slope of the slope signal SLP or the transconductance Gm. This allows for sensitive response to even a slight increase in the phase difference between the reference clock signal RFCK and the feedback clock signal FBCK, bringing the phase difference closer to zero, thereby reducing in-band noise compared to FLL operation.

[0034] 2. Slope signal generation circuit, phase comparison circuit, DTC circuit FIG. 4 shows an example configuration of the slope signal generation circuit 72 and the phase comparison circuit 50. As shown in FIG. 4, the slope signal generation circuit 72 includes a P-type transistor TA1, a variable resistor RA, and an N-type transistor TA2, which are arranged in series between a high-potential power supply node and a low-potential power supply node. The high-potential power supply node is, for example, a VDD node, and the low-potential power supply node is a GND node. For example, the source of the P-type transistor TA1 is connected to the VDD node, and the drain is connected to one end of the variable resistor RA. The other end of the variable resistor RA is connected to the output node NQ of the slope signal generation circuit 72 and the drain of the N-type transistor TA2. The source of the N-type transistor is connected to the GND node. The GND voltage is the ground voltage, and GND can also be called VSS.

[0035] The gates of the P-type transistor TA1 and the N-type transistor TA2 are controlled based on the feedback clock signal FBCK. For example, in FIG. 4, a negative-logic feedback clock signal XFBCK, which is the inverse of the feedback clock signal FBCK, is input to the gates of the transistors TA1 and TA2. The sampling circuit 52 also includes a sampling switch SS and a capacitor CS. The sampling switch SS is provided between the output node NQ of the slope signal generating circuit 72 and the sampling node NS of the sampling voltage VSA, and is turned on or off based on the reference clock signal RFCKD. For example, in FIG. 4, the sampling switch SS is composed of an N-type transistor TA3, and a negative-logic reference clock signal XRFCKD, which is the inverse of the reference clock signal RFCKD, is input to the gate of this N-type transistor TA3. Therefore, when the reference clock signal RFCKD is at a low level (inactive level), the switch SS is turned on, and when the reference clock signal RFCKD is at a high level (active level), the switch SS is turned off. One end of the sampling capacitor CS is connected to the sampling node NS. The other end of the sampling capacitor CS is connected to a node at a predetermined potential, such as a GND node.

[0036] FIG. 5 is a signal waveform diagram illustrating the operation of the slope signal generation circuit 72 and the phase comparison circuit 50. When the feedback clock signal FBCK transitions from low to high at timing t1 in FIG. 5, the P-type transistor TA1 of the slope signal generation circuit 72 turns on, causing current to flow from the VDD node through the transistor TA1 and the variable resistor RA to the output node NQ of the slope signal generation circuit 72. At this time, because the reference clock signal RFCKD is low, the switch SS, which is comprised of the N-type transistor TA3, turns on. Current from the output node NQ flows to and charges the sampling capacitor CS, causing the output voltage VQ of the output node NQ to rise at a predetermined slope. This generates a slope signal SLP, whose voltage changes at a predetermined slope. The slope of the slope signal SLP, which represents the slope of the output voltage VQ over time, can be set by the resistance value of the variable resistor RA and the capacitance value of the capacitor CS. For example, decreasing the resistance value of the variable resistor RA or the capacitance value of the capacitor CS increases the slope, whereas increasing the resistance value or the capacitance value decreases the slope. By increasing the gradient of the slope signal SLP, the loop gain of the PLL increases, making it possible to reduce in-band noise.

[0037] When the reference clock signal RFCKD goes from low to high at time t2 in FIG. 5, the switch SS, comprised of an N-type transistor TA3, turns off. The output voltage VQ at time t2 when the switch SS turns off is sampled at the sampling node NS as the sampling voltage VSA. In this case, the later the reference clock signal RFCKD goes high at time t2 relative to time t1 when the feedback clock signal FBCK goes high, the larger the sampling voltage VSA. Therefore, the sampling voltage VSA corresponds to the phase difference between the reference clock signal RFCKD (RFCK) and the feedback clock signal FBCK. The larger the phase difference, the larger the sampling voltage VSA. When the feedback clock signal FBCK goes low at time t3, the P-type transistor TA1 of the slope signal generating circuit 72 turns off, and the N-type transistor TA2 turns on, thereby decreasing the output voltage VQ. When the reference clock signal RFCKD goes low at time t4, the switch SS turns on, and the sampling voltage VSA becomes approximately the same potential as the output voltage VQ.

[0038] FIG. 6 shows an example configuration of a DTC circuit 30. The DTC circuit 30 includes a current source IS, a P-type transistor TB1, an N-type transistor TB2, and a capacitor CL, which are connected in series between a high-potential power supply node and a low-potential power supply node. The DTC circuit 30 may also include a buffer circuit BF and an inverter circuit IV. In FIG. 6, the high-potential power supply node is the VDDL node, and the low-potential power supply node is the GND node. VDDL is supplied, for example, by a regulator operating based on VDD. For example, the current source IS is connected between the VDDL node and the source of transistor TB1. Transistors TB1 and TB2 are connected in series between the current source IS and the GND node. One end of the capacitor CL is connected to a node NB, which connects the drains of transistors TB1 and TB2. The other end of the capacitor CL is connected to a node at a predetermined potential, such as the GND node.

[0039] The gates of P-type transistor TB1 and N-type transistor TB2 are controlled based on the reference clock signal RFCK. For example, in Figure 6, the reference clock signal RFCK is buffered by buffer circuit BF and input to the gates of transistors TB1 and TB2. Then, signal SQ is output to node NB by current source IS and transistors TB1 and TB2. This signal is inverted by inverter circuit IV and output as reference clock signal RFCKD after adjusting the delay time. For example, when the reference clock signal RFCK changes from high to low, P-type transistor TB1 changes from off to on, and a constant current from current source IS flows to node NB via transistor TB1. This current charges capacitor CL, increasing the voltage at node NB. If the threshold voltage of inverter circuit IV is VTH, when the voltage at node NB exceeds VTH, the reference clock signal RFCKD changes from high to low. This allows the falling edge of the reference clock signal RFCK to be delayed by a delay time determined by the current value of current source IS and the capacitance of capacitor CL. Here, we will explain the case where the falling edge of the reference clock signal RFCK is delayed by a delay time that depends on the current value of the current source IS and the capacitance value of the capacitor CL, but the rising edge of the reference clock signal RFCK may also be delayed by a delay time that depends on the current value of the current source IS and the capacitance value of the capacitor CL.

[0040] In FIG. 6, the capacitor CL is a capacitor with a variable capacitance, and the current source IS is a current source with a variable current. For example, the capacitance of the capacitor CL is controlled by a DTC code DC. The current of the current source IS is controlled by a gain correction value GC. For example, the capacitance of the capacitor CL is controlled by a 7-bit (m-bit) DTC code DC, and the current of the current source IS is controlled by an 8-bit (k-bit) gain correction value GC.

[0041] For example, when the DTC code DC sets the capacitor CL to a large capacitance, the delay time of the reference clock signal RFCKD relative to the reference clock signal RFCK increases. On the other hand, when the DTC code DC sets the capacitor CL to a small capacitance, the delay time of the reference clock signal RFCKD relative to the reference clock signal RFCK decreases. Therefore, the DTC circuit 30 can adjust the delay time of the reference clock signal RFCKD based on the DTC code DC. The delay time is, for example, the delay time of an edge of the reference clock signal RFCK relative to a corresponding edge of the reference clock signal RFCKD.

[0042] Furthermore, when the current value of the current source IS is set to a small current value by the gain correction value GC, the gain of the DTC circuit 30 is set to a large gain. For example, the rate of change in the delay time relative to a change in the DTC code DC becomes large. Furthermore, when the current value of the current source IS is set to a large current value by the gain correction value GC, the gain of the DTC circuit 30 is set to a small gain. For example, the rate of change in the delay time relative to a change in the DTC code DC becomes small.

[0043] For example, let CL be the capacitance of capacitor CL with the same sign, IB be the constant current of current source IS, VTH be the threshold voltage of inverter circuit IV, and TD be the delay time set by DTC circuit 30. In the DTC circuit 30 shown in FIG. 6, capacitor CL is charged by a constant current of IB from current source IS. When the voltage at node NB exceeds threshold voltage VTH, the voltage level of reference clock signal RFCKD changes. Therefore, the relationship IB×TD=CL×VTH holds, and the delay time can be expressed as TD=(CL×VTH) / IB. The gain of DTC circuit 30 corresponds to, for example, 1 / IB. For example, DTC circuit 30 adjusts the gain, which is the sensitivity of DTC circuit 30, so that the relationship TD=(CL×VTH) / I holds.

[0044] For example, Figure 7 shows the relationship between the DTC code and delay time. B1 in Figure 7 shows the relationship between the DTC code and delay time in an ideal case. For example, the gain of the DTC circuit 30 can be expressed as the ratio of the change in delay time to the change in the DTC code, and the slope of B1 in Figure 7 corresponds to the gain of the DTC circuit 30.

[0045] However, B1 in FIG. 7 shows the characteristics when the DTC code and delay time have an ideal relationship. If an error occurs in the gain of the DTC circuit 30, the relationship deviates from the ideal, as shown in B2 and B3 in FIG. 7. For example, B2 shows an example when the gain error is +10%, and B3 shows an example when the gain error is -10%. The relationship between the DTC code and delay time may not be linear, as shown in B1 in FIG. 7, but may be nonlinear. For example, when there is a positive gain error, as shown in B2 in FIG. 7, the rate of change in the delay time of the reference clock signal RFCKD relative to a change in the DTC code becomes larger than in the ideal case of B1. Furthermore, when there is a negative gain error, as shown in B3 in FIG. 7, the rate of change in the delay time of the reference clock signal RFCKD relative to a change in the DTC code becomes smaller than in the ideal case of B1.

[0046] FIG. 8 shows example signal waveforms illustrating the operation of the DTC circuit 30. For example, when implementing a fractional-N PLL circuit using the circuit device 20 of this embodiment, the divider circuit 70 can only perform integer division. Therefore, the integer division is varied in a time-division manner to achieve fractional division on average. For example, to achieve a division of 20.5, delta-sigma modulation is used to alternate between division by 20 and division by 21. However, the phase error of the phase comparison result from the phase comparator circuit 50 varies within the range of this integer division variation. This variation is then transmitted to the voltage-controlled oscillator circuit 66, degrading the phase jitter characteristics of the clock signal CK. Using FIG. 8 as an example, the phase difference between the reference clock signal RFCK and the feedback clock signal FBCK, indicated by A1 and A2, represents the phase error.

[0047] Therefore, to reduce this phase error, the DTC circuit 30 is used. The DTC circuit 30 is a circuit that can adjust the delay time, or the amount of delay, using a digital DTC code, and can adjust the phase of the reference clock signal by the delay time. By appropriately adjusting the delay time, the reference clock signal RFCKD will have a waveform like that shown in Figure 8, and the phase error with the feedback clock signal FBCK can be reduced, ideally to zero. This improves the phase jitter characteristics of the clock signal CK.

[0048] However, this only holds true when the delay time characteristic for the DTC code input to the DTC circuit 30 is an ideal characteristic, as shown in B1 of FIG. 7. In the actual circuit device 20, a gain error occurs in the DTC circuit 30, as shown in B2 and B3 of FIG. 7, for example. Correction for this gain error can be achieved by adjusting the current value of the current source IS of the DTC circuit 30. That is, the gain error can be corrected by adjusting the current value of the current source IS based on the gain correction value GC.

[0049] In this embodiment, as described with reference to FIGS. 1 to 3, the correction circuit 80 corrects the gain of the DTC circuit 30 based on the sampling voltage output by the phase comparison circuit 50. That is, as described with reference to FIG. 5, the sampling voltage is a voltage corresponding to the phase difference between the reference clock signal RFCK and the feedback clock signal FBCK. Therefore, the clock signal generation circuit 60 controls the frequency of the clock signal CK based on the sampling voltage, thereby achieving phase synchronization between the reference clock signal RFCK and the feedback clock signal FBCK. Therefore, by monitoring the sampling voltage, gain correction can be performed to correct the gain of the DTC circuit 30 to an appropriate gain.

[0050] Specifically, the correction circuit 80 extracts sign information by comparing the sampled voltage with a reference voltage. The sign information is, for example, +1 when the sampled voltage exceeds the reference voltage, and -1 when the sampled voltage is below the reference voltage. For example, FIG. 9 shows an example of the relationship between the DTC code and the sampled voltage. For example, C1 in FIG. 9 is the characteristic when the gain error is 0%, C2 is the characteristic when the gain error is +10%, and C3 is the characteristic when the gain error is -10%.

[0051] For example, the correction circuit 80 extracts sign information by comparing the sampled voltage from the phase comparator circuit 50 with a reference voltage. The reference voltage, which is compared with the sampled voltage when extracting the sign information, corresponds to the sampled voltage in the characteristic curve shown in C1 of FIG. 9 . Therefore, when a positive gain error occurs, as shown in C2 of FIG. 9 , the sign information extracted by comparing the sampled voltage with the reference voltage is +1. When a negative gain error occurs, as shown in C3 of FIG. 9 , the sign information extracted by comparing the sampled voltage with the reference voltage is −1. Therefore, the correction circuit 80 can determine that a positive gain error has occurred when the average value of the sign information extracted from the sampled voltage is a positive value. When the average value of the sign information extracted from the sampled voltage is a negative value, the correction circuit 80 can determine that a negative gain error has occurred. Therefore, the correction circuit 80 can perform gain correction of the DTC circuit 30 by using the sign information extracted from the sampled voltage.

[0052] In the case of the characteristics shown in Figure 9, the deviation of the sampled voltage due to gain error increases as the DTC code increases. For example, the deviation of the characteristics C2 and C3 from the characteristic C1 in Figure 9 increases as the DTC code increases. For this reason, the prior art in Non-Patent Document 1 finds a gain correction value by weighting the DTC code, i.e., multiplying the code information extracted from the sampled voltage by the DTC code. In other words, gain correction is performed on the assumption that a large gain error occurs when the DTC code value is large.

[0053] However, it has been found that the relationship between the DTC code and the sampling voltage is not limited to the relationship shown in FIG. 9 and can be, for example, as shown in FIGS. 10 and 11. For example, D1 in FIG. 10 represents the characteristic when the gain error is 0%, D2 represents the characteristic when the gain error is +10%, and D3 represents the characteristic when the gain error is -10%. Also, E1 in FIG. 11 represents the characteristic when the gain error is 0%, E2 represents the characteristic when the gain error is +10%, and E3 represents the characteristic when the gain error is -10%. For example, because the phase comparator circuit 50 and the DTC circuit 30 are analog circuits, the relationship between the DTC code and the sampling voltage is not limited to the characteristic shown in FIG. 9 but can vary as shown in FIGS. 10 and 11 due to manufacturing variations in the characteristics of circuit elements such as transistors, resistors, and capacitors, as well as environmental variations such as temperature fluctuations. For this reason, the prior art described in Non-Patent Document 1, which weights code information by multiplying it with the DTC code, cannot address this issue.

[0054] For example, in the case of the characteristics in Figure 9, if the sign information extracted by comparing the sampling voltage with the reference voltage is +1, it can be determined that a positive gain error has occurred, as shown in C2, and if the sign information is -1, it can be determined that a negative gain error has occurred, as shown in C3. In other words, the reference voltage compared with the sampling voltage is the voltage corresponding to the sampling voltage in the characteristics in C1 in Figure 9, where the gain error is 0%. Therefore, if the sampling voltage is higher than the reference voltage and the sign information is +1, it can be determined that a positive gain error has occurred, as shown in C2, and if the sampling voltage is lower than the reference voltage and the sign information is -1, it can be determined that a negative gain error has occurred, as shown in C3.

[0055] However, the characteristics of the sampled voltage relative to the DTC code do not necessarily resemble those shown in Figure 9, but may resemble those shown in Figure 10. In Figure 10, in the first range R1 where the DTC code is small, if a positive gain error occurs as in the characteristic D2, the sampled voltage falls below the reference voltage corresponding to the characteristic D1, and the sign information extracted from the sampled voltage becomes -1. Also, in the first range R1, if a negative gain error occurs as in the characteristic D3, the sampled voltage exceeds the reference voltage, and the sign information becomes +1.

[0056] 10, in the second range R2 where the DTC code becomes large, if a positive gain error occurs as in the characteristic D2, the sampled voltage exceeds the reference voltage, and the sign information becomes +1. In the second range R2, if a negative gain error occurs as in the characteristic D3, the sampled voltage falls below the reference voltage, and the sign information becomes -1.

[0057] Therefore, if a gain correction value is calculated based on the sign information extracted from the sampled voltage, assuming the characteristics shown in Figure 9, and the actual characteristics are as shown in Figure 10, the gain correction value will be generated using inaccurate sign information, resulting in a problem of not being able to achieve appropriate gain correction. That is, in Figure 9, whether the DTC code is small or large, the sign information is +1 for a positive gain error and -1 for a negative gain error. In contrast, in Figure 10, in the first range R1 where the DTC code is small, the sign information is -1 for a positive gain error and +1 for a negative gain error, resulting in sign information values that differ from those in Figure 9.

[0058] Furthermore, in ranges where the deviation of the sampling voltage due to the gain error, indicated by D2 and D3, is large, such as the first range R1 and second range R2 in Figure 10, the variation in the extracted code information is small, and the gain correction value can be calculated based on accurate code information. In contrast, in a range where the deviation of the sampling voltage due to the gain error is small, such as the third range R3 in Figure 10, the variation in the extracted code information is large. Therefore, if gain correction is performed using code information with such large variations, there is a risk of incorrect gain correction being performed.

[0059] For example, Figures 12, 13, and 14 show the characteristics of Figure 10 in detail. Figure 12 shows the characteristics when the gain error is 0%, Figure 13 shows the characteristics when the gain error is +10%, and Figure 14 shows the characteristics when the gain error is -10%. Figures 12, 13, and 14 plot the characteristics of multiple circuit devices, and in these multiple circuit devices, the characteristics of circuit elements such as transistors vary due to variations in the manufacturing process, etc., which causes variations in the characteristics of the sampling voltage relative to the DTC code.

[0060] For example, when a positive gain error occurs, the characteristics are as shown in Figure 13. In the first range R1 where the DTD code is small, it is determined that a positive gain error has occurred when the code information is -1. In the second range R2 where the DTC code is large, it is determined that a positive gain error has occurred when the code information is +1. The code information of -1 indicates that the sampling voltage is below the reference voltage. In the first range R1 of Figure 13, the sampling voltage is smaller than in Figure 12 where the gain error is 0%, and the code information is -1. The code information of +1 indicates that the sampling voltage is higher than the reference voltage. In the second range R2 of Figure 13, the sampling voltage is larger than in Figure 12 where the gain error is 0%, and the code information is +1.

[0061] Furthermore, when a negative gain error occurs, the characteristics are as shown in Figure 14. Therefore, in the first range R1 where the DTC code has a small value, it is determined that a negative gain error has occurred when the sign information is +1, and in the second range R2 where the DTC code has a large value, it is determined that a negative gain error has occurred when the sign information is -1.

[0062] On the other hand, when the DTC code is in a third range R3 between the first range R1 and the second range R2, variations occur in the extraction of the code information, making it difficult to extract accurate code information. As is clear from Figures 13 and 14, in the first range R1 and the second range R2, the deviation of the characteristics of D2 and D3 from the characteristic of D1 in Figure 10 is large, so the code information can be extracted accurately. However, in the third range R3, the deviation of the characteristics of D2 and D3 from the characteristic of D1 is small, so the code information cannot be extracted accurately.

[0063] When performing gain correction of the DTC circuit 30 based on the sampled voltage, the relationship between the DTC code and the sampled voltage can vary. Therefore, the conventional technique of multiplying the sign information by the DTC code, as in Non-Patent Document 1, can accommodate the characteristics shown in Figure 9 but cannot accommodate the characteristics shown in Figures 10 and 11. In other words, the conventional technique of Non-Patent Document 1 has a problem in that, in the case of the characteristics shown in Figures 10 and 11, the gain correction value is generated using inaccurate sign information. Furthermore, as described above, in the third range R3 of Figures 13 and 14, the extracted sign information varies, making it impossible to extract accurate sign information. Therefore, generating a gain correction value using the sign information extracted in the third range R3 results in inappropriate gain correction.

[0064] Therefore, in this embodiment, a method is adopted in which code information extracted based on the sampled voltage is selected according to the DTC code, and the gain correction value of the DTC circuit 30 is calculated based on the selected code information.

[0065] For example, in the case of the characteristics shown in Fig. 9, code information in a first range R1 where the DTC code value is large is selected, and the selected code information is used to generate the gain correction value. On the other hand, code information in a range where the DTC code value is small is not selected and is not used to generate the gain correction value.

[0066] 10, code information in the first range R1 where the DTC code value is small or in the second range R2 where the DTC code value is large is selected, and the selected code information is used to generate the gain correction value.On the other hand, code information in the third range R3 where the DTC code value is small is not selected and is not used to generate the gain correction value.

[0067] 11, code information in a first range R1 where the DTC code value is small is selected, and the selected code information is used to generate the gain correction value.On the other hand, code information in a range where the DTC code value is large is not selected and is not used to generate the gain correction value.

[0068] In this manner, in this embodiment, code information is selected according to the DTC code, and the selected code information is used to generate the gain correction value for the DTC circuit 30. This prevents the generation of a gain correction value using inaccurate code information, and makes it possible to achieve appropriate gain correction using accurate code information.

[0069] As described above, in this embodiment, as shown in FIGS. 1 to 3, the circuit device 20 includes the DTC circuit 30, the code generation circuit 40, the phase comparison circuit 50, the clock signal generation circuit 60, the frequency division circuit 70, the slope signal generation circuit 72, and the correction circuit 80.

[0070] The code generation circuit 40 generates a DTC code DC, and the DTC circuit 30 adjusts the delay time of the reference clock signal RFCK using the DTC code DC. For example, as described with reference to FIGS. 6 and 8, the DTC circuit 30 adjusts the delay time to reduce the phase error with respect to the feedback clock signal FBCK, and outputs the reference clock signal RFCKD with the adjusted delay time.

[0071] The phase comparator circuit 50 samples the slope signal SLP using the reference clock signal RFCKD with the adjusted delay time, thereby outputting the sampled voltage VSA. For example, in the phase comparator circuit 50, the sampling circuit 52 samples the slope signal SLP using the reference clock signal RFCKD, for example, at timing t2 in FIG. 5, thereby outputting the sampled voltage VSA. The clock signal generator circuit 60 generates a frequency-controlled clock signal CK based on the sampled voltage VSA. For example, as shown in FIG. 2, in the clock signal generator circuit 60, the charge pump circuit 62 generates a charge pump current based on the sampled voltage VSA, the loop filter circuit 64 smooths the charge pump current to generate a control voltage, and the voltage-controlled oscillator circuit 66 controls the frequency of the clock signal CK based on the control voltage. The frequency divider circuit 70 divides the clock signal CK to output the feedback clock signal FBCK, and the slope signal generator circuit 72 generates the slope signal SLP based on the feedback clock signal FBCK. For example, as described with reference to FIGS. 4 and 5, the slope signal generating circuit 72 generates a slope signal SLP whose voltage changes at a predetermined gradient.

[0072] The correction circuit 80 then extracts sign information based on the sampled voltage VSA, selects the sign information according to the DTC code DC, and generates a gain correction value GC for the DTC circuit 30 based on the selected sign information. For example, the correction circuit 80 extracts sign information by comparing the sampled voltage VSA with a reference voltage. The correction circuit 80 then performs a process of selecting sign information according to the DTC code DC rather than always using the extracted sign information. For example, in FIG. 9 , sign information for which the DTC code DC value is in the first range R1 is selected. In FIG. 10 , sign information for which the DTC code DC value is in the first range R1 or the second range R2 is selected. In FIG. 11 , sign information for which the DTC code DC value is in the first range R1 is selected. The correction circuit 80 then generates a gain correction value GC for the DTC circuit 30 based on the selected sign information. For example, the correction circuit 80 does not use sign information that has not been selected, but instead uses the selected sign information to generate the gain correction value GC.

[0073] In this embodiment, the delay time of the reference clock signal RFCK is adjusted by the DTC circuit 30. The delay-adjusted reference clock signal RFCKD samples the slope signal SLP to generate a sampling voltage VSA, and the clock signal CK is generated based on this sampling voltage VSA. This reduces the phase error between the reference clock signal RFCK and the feedback clock signal FBCK, thereby reducing phase jitter in the clock signal CK. The DTC circuit 30, which adjusts the delay time, generates a gain error. However, the correction circuit 80 corrects this gain error. In this case, if the gain correction value GC were generated using all the code information extracted based on the sampling voltage VSA, the gain correction value GC would be generated using inaccurate code information. In this embodiment, the gain correction value GC is generated using code information selected according to the DTC code DC, thereby achieving appropriate gain correction using accurate code information.

[0074] In this embodiment, the correction circuit 80 calculates the gain correction value GC using sign information when the DTC code DC is within a first range R1. For example, if the relationship between the DTC code DC and the sampling voltage VSA has the characteristics shown in FIG. 9, the first range R1 is a range in which the DTC code DC has a large value, and sign information within the first range R1 in which the DTC code DC has a large value is selected to generate the gain correction value GC. Furthermore, sign information within the range in which the DTC code DC has a small value is not used to generate the gain correction value GC. Furthermore, if the relationship between the DTC code DC and the sampling voltage VSA has the characteristics shown in FIGS. 10 and 11, the first range R1 is a range in which the DTC code DC has a small value, and sign information within the first range R1 in which the DTC code DC has a small value is selected to generate the gain correction value GC. For example, in the case of FIG. 11, sign information within the range in which the DTC code DC has a large value is not used to generate the gain correction value GC. In this way, the gain correction value GC can be generated using code information corresponding to the first range R1 in which the code information is considered to be accurate, thereby making it possible to prevent the occurrence of a situation in which a gain correction value is generated using inaccurate code information.

[0075] Furthermore, the correction circuit 80 calculates the gain correction value GC using the sign information when the DTC code DC is within the first range R1 or the second range R2. However, the correction circuit 80 does not use the sign information when the DTC code DC is within the third range R3 between the first range R1 and the second range R2. For example, if the relationship between the DTC code DC and the sampling voltage VSA has the characteristics shown in FIG. 10, the first range R1 is the range where the DTC code DC value is small, and the second range R2 is the range where the DTC code DC value is large. The third range R3 between the first range R1 and the second range R2 is the range where the DTC code DC value is larger than the first range R1 and smaller than the second range R2. In the first range R1 and the second range R2, the deviation of the characteristics of D2 and D3 from the characteristics of D1 in FIG. 10 is large, allowing accurate extraction of the sign information. On the other hand, in the third range R3, variations in the extraction of the sign information occur, making accurate extraction of the sign information difficult. In this case, in this embodiment, when the DTC code DC is a value in the third range R3, the gain correction value GC is not generated using the sign information, but when the DTC code DC is a value in the first range R1 or the second range R2, the gain correction value GC is generated using the sign information. In this manner, the gain correction value GC is generated using the sign information corresponding to the first range R1 or the second range R2, where the sign information is considered to be accurate, while the gain correction value GC is not generated using the sign information corresponding to the third range R3, where the sign information is considered to be inaccurate. Therefore, appropriate gain correction using accurate sign information can be achieved.

[0076] Furthermore, when the DTC code DC is a value in the first range R1, the correction circuit 80 calculates the gain correction value GC using information with the sign information inverted, and when the DTC code DC is a value in the second range R2, the correction circuit 80 calculates the gain correction value GC using the sign information. In this way, it is possible to achieve gain correction using appropriate sign information whether the DTC code DC is a value in the first range R1 or a value in the second range R2.

[0077] For example, suppose a positive gain error occurs as shown in D2 in Figure 10. In this case, when the DTC code DC is within the first range R1, the sign information is extracted as -1 by comparing the sampled voltage VSA with the reference voltage, and the gain correction value GC is calculated using the sign information of +1, which is the inverse of the -1 sign information. On the other hand, when the DTC code DC is within the second range R2, the sign information is extracted as +1 by comparing the sampled voltage VSA with the reference voltage, and the gain correction value GC is calculated using the sign information of +1, which corresponds to the positive gain error. Therefore, when a positive gain error occurs, appropriate gain correction can be performed using the sign information of +1, which corresponds to the positive gain error, whether the DTC code DC is within the first range R1 or the second range R2.

[0078] Also, assume that a negative gain error occurs as shown at D3 in FIG. 10. In this case, when the DTC code DC is within the first range R1, +1 is extracted as the sign information by comparing the sampled voltage VSA with the reference voltage. The gain correction value GC is calculated using the inverted sign information of -1. When the DTC code DC is within the second range R2, -1 is extracted as the sign information by comparing the sampled voltage VSA with the reference voltage. The gain correction value GC is calculated using the inverted sign information of -1. Therefore, when a negative gain error occurs, appropriate gain correction can be performed using the sign information of -1, which corresponds to the negative gain error, whether the DTC code DC is within the first range R1 or the second range R2.

[0079] 2, the code generation circuit 40 includes a delta-sigma modulation circuit 42 that performs delta-sigma modulation based on the division ratio setting information SDIV. The code generation circuit 40 generates a DTC code DC based on the delta-sigma modulation data from the delta-sigma modulation circuit 42 and sets the division ratio of the frequency divider circuit 70. For example, the code generation circuit 40 generates the DTC code DC based on the integration result of an integrator 44 that integrates the delta-sigma modulation data. The code generation circuit 40 also sets the division ratio of the frequency divider circuit 70 based on the integer part of the division ratio setting information SDIV and the integration result of the integrator 44 that integrates the delta-sigma modulation data. This configuration allows the frequency divider circuit 70 to function as a fractional frequency divider, thereby realizing a fractional-N PLL circuit that can output a clock signal CK having a frequency obtained by multiplying the frequency of the reference clock signal RFCK by any desired multiplication factor, including a decimal part. In this fractional-N type PLL circuit, gain correction of the DTC circuit 30 is performed using an accurate gain correction value GC, making it possible to generate a clock signal CK with reduced phase jitter and the like.

[0080] 3. Correction circuit Fig. 15 shows a detailed configuration example of the correction circuit 80. The correction circuit 80 includes a code information extraction unit 82, a selection unit 86, and a correction value generation unit 90. Note that the correction circuit 80 is not limited to the configuration shown in Fig. 15, and various modifications are possible, such as omitting some of the components, adding other components, or changing the components to other types of components.

[0081] The sign information extraction unit 82 extracts sign information by comparing the sampling voltage VSA with the reference voltage VRF. For example, the sign information extraction unit 82 includes a comparison circuit 83 and a conversion unit 84. The comparison circuit 83 compares the sampling voltage VSA with the reference voltage VRF. The comparison circuit 83 can be realized, for example, by a comparator configured with an operational amplifier. The comparison circuit 83 receives the sampling voltage VSA at its first input terminal and the reference voltage VRF at its second input terminal, and outputs a comparison result signal. For example, if the sampling voltage VSA is greater than the reference voltage VRF, the comparison circuit 83 outputs a signal with a logical level of 1. For example, the comparison circuit 83 outputs a high-level signal. On the other hand, if the sampling voltage VSA is smaller than the reference voltage VRF, the comparison circuit 83 outputs a signal with a logical level of 0. For example, the comparison circuit 83 outputs a low-level signal. When the output signal of the comparison circuit 83 is at a logical level of 1, the conversion unit 84 converts it to sign information of +1. When the output signal of the comparison circuit 83 is at a logical level of 0, the conversion unit 84 converts it to sign information of −1. In this way, the sign information extraction unit 82 compares the sampling voltage VSA with the reference voltage VRF using the comparison circuit 83, thereby extracting and outputting sign information, such as +1 or −1. For example, when the sampling voltage VSA is greater than the reference voltage VRF, the conversion unit 84 outputs sign information of +1. When the sampling voltage VSA is smaller than the reference voltage VRF, the conversion unit 84 outputs sign information of −1. In this way, the sign information extracted by comparing the sampling voltage VSA with the reference voltage VRF can be used to determine whether the sampling voltage VSA is greater than or less than the reference voltage VRF. Using this sign information, when a positive or negative gain error occurs, it is possible to perform gain correction to reduce the gain error.

[0082] The selection unit 86 selects the sign information according to the DTC code DC. For example, the selection unit 86 selects whether or not to use the sign information for generating the gain correction value GC according to the range to which the value of the DTC code DC belongs. In this way, it becomes possible to determine whether or not to use the sign information for generating the gain correction value GC according to the range to which the value of the DTC code DC belongs.

[0083] The selection unit 86 includes selectors 87 and 88, a control unit 89, and an inversion unit IVB. The control unit 89 receives the DTC code DC from the code generation circuit 40. The control unit 89 controls the selectors 87 and 88 in accordance with the DTC code DC.

[0084] The selector 88 is controlled by the control unit 89 to select the first input terminal I1 when sign information is used to generate the gain correction value GC, and to select the second input terminal I2 when sign information is not used to generate the gain correction value GC. When the first input terminal I1 is selected, sign information of +1 or −1 is selected and output to the correction value generator 90. When the second input terminal I2 is selected, 0 is selected and output to the correction value generator 90. For example, when the DTC code DC is a value in the first range R1 or the second range R2, the first input terminal I1 is selected and sign information of +1 or −1 is output to the correction value generator 90. On the other hand, when the DTC code DC is a value in a third range R3 between the first range R1 and the second range R2, the second input terminal I2 is selected and 0 is output to the correction value generator 90.

[0085] The selector 87 is controlled by the control unit 89 to select the first input terminal I1 when the code information is to be inverted, and to select the second input terminal I2 when the code information is not to be inverted. When the first input terminal I1 is selected, the code information is inverted by the inversion unit IVB and output from the selector 87. When the second input terminal I2 is selected, the code information is output from the selector 87 without being inverted.

[0086] For example, suppose a positive gain error occurs as shown by D2 in Fig. 10. In this case, when the DTC code DC is a value within the first range R1, the first input terminal I1 of the selector 87 is selected, and sign information of +1, for example, which is the inverse of sign information of -1, is output from the selector 87. On the other hand, when the DTC code DC is a value within the second range R2, the second input terminal I2 is selected, and sign information of +1, for example, is output from the selector 87 as is.

[0087] 10, assume that a negative gain error occurs as indicated by D3. In this case, when the DTC code DC is within the first range R1, the first input terminal I1 of the selector 87 is selected, and code information of -1, for example, which is the inverse of code information of +1, is output from the selector 87. On the other hand, when the DTC code DC is within the second range R2, the second input terminal I2 is selected, and code information of -1, for example, is output from the selector 87 as is.

[0088] For example, suppose the DTC code DC is a 7-bit digital code whose value ranges from 0 to 127. Assume also that the relationship between the DTC code DC and the sampling voltage VSA is as shown in FIG. 10. In this case, when the value of the DTC code DC is 31 or less (in the first range R1), the selector 87 selects the first input terminal I1 and outputs information with inverted sign information. The selector 88 selects the first input terminal I1 and outputs information with inverted sign information output from the selector 87. As a result, the gain correction value GC is generated using the information with inverted sign information. When the value of the DTC code DC is 96 or more (in the second range R2), the selector 87 selects the second input terminal I2 and outputs the sign information as is. The selector 88 selects the first input terminal I1 and outputs the sign information output from the selector 87. As a result, the gain correction value GC is generated using the sign information. On the other hand, when the value of the DTC code DC is greater than 32 and less than 96 (in the third range R3), the selector 88 selects the second input terminal I2 and outputs 0. This prevents sign information from being used in generating the gain correction value GC.

[0089] In this way, the correction circuit 80 calculates the gain correction value GC using information with the inverted sign information when the DTC code DC is a value within the first range R1, and calculates the gain correction value GC using the sign information when the DTC code DC is a value within the second range R2. This makes it possible to appropriately deal with cases such as when a positive gain error occurs but the sign information is negative in the first range R1, or when a negative gain error occurs but the sign information is positive in the first range R1, as shown in Figure 10. This makes it possible to generate the gain correction value GC using accurate sign information.

[0090] The correction value generation unit 90 generates the gain correction value GC based on the selected code information. For example, when the code information extraction unit 82 extracts code information and the selection unit 86 selects the code information according to the DTC code DC, the correction value generation unit 90 generates the gain correction value GC using the selected code information. In this way, it is possible to accurately determine the gain correction value GC using the code information appropriately selected according to the DTC code DC, thereby achieving gain correction of the DTC circuit 30.

[0091] For example, the correction value generation unit 90 includes an accumulator 91, a switch 92, a binary comparator 93, a multiplier 94, and an accumulator 95. The accumulator 91 accumulates the selected code information. The switch 92 is turned on or off based on the slow clock signal SLCK to perform downsampling. The slow clock signal SLCK is, for example, a clock signal with a slower rate than the rate at which the code information is extracted. The accumulator 91 and the switch 92 perform an averaging process on the code information. For example, the slower the rate of the slow clock signal SLCK, the longer the period for measuring the average value.

[0092] The binary comparator 93 selects whether to increment the gain correction value GC by +1, -1, or not update it (+0). For example, the binary comparator 93 has a positive threshold value VTP and a negative threshold value VTM. The binary comparator 93 outputs +1 when the average value of the code information calculated by the averaging unit using the integrator 91 and switch 92 is equal to or greater than VTP, outputs -1 when the average value is equal to or less than VTM, and outputs 0 when the average value is between VTP and VTM. For example, assume that VTP is +5 and VTM is -5. In this case, +1 is output when the average value of the code information is equal to or greater than +5, -1 is output when the average value is equal to or less than -5, and 0 is output when the average value is between +5 and -5. In this way, 0 is output when the average value of the code information is between VTP and VTM, and the gain correction value GC is not updated. This prevents the gain correction value GC from being frequently updated when the average value of the code information changes slightly, for example, from +1 to -1. The multiplier 94 multiplies the output value of the binary comparator 93 by the step size STP. As a result, when the binary comparator 93 outputs +1, the multiplier 94 outputs +STP, and when the binary comparator 93 outputs -1, the multiplier 94 outputs -STP. When the binary comparator 93 outputs 0, the multiplier 94 also outputs 0. The step size STP is used to adjust the convergence time and stability after convergence. The accumulator 95 then accumulates the output value of the multiplier 94 to generate and output a gain correction value GC.

[0093] For example, when the PLL circuit is properly locked and no gain error occurs, the code information repeatedly changes between +1 and -1, for example, so that the average value of the code information falls between the thresholds VTP and VTM of the binary comparator 93, and the gain correction value GC is not updated. On the other hand, when the average value of the code information increases in the positive direction and exceeds the positive threshold VTP, or when the average value of the code information decreases in the negative direction and falls below the negative threshold VTM, the gain correction value GC is updated to +STP or -STP, and the DTC circuit 30 performs gain correction.

[0094] In the conventional technology of Non-Patent Document 1, weighting by the DTC code DC is performed by multiplying the code information extracted by the code information extraction unit 82 by the DTC code DC. However, the conventional technology of Non-Patent Document 1 cannot handle various characteristics such as those described in FIGS. 10 and 11, and there is a problem that the gain correction value GC is generated using inaccurate code information. In addition, a multiplier is required to multiply the DTC code DC, which increases the circuit size. In contrast, in this embodiment, code information is selected according to the DTC code DC, thereby preventing gain correction from being performed using inaccurate code information. Furthermore, since there is no need to provide a multiplier that multiplies the code information by the DTC code DC, the circuit size can be reduced.

[0095] FIG. 16 is a flowchart illustrating the operation of the correction circuit 80. First, the correction circuit 80 determines whether the DTC code DC is a value within the first range R1 (step S1). For example, the correction circuit 80 determines whether the DTC code DC is a value within the first range R1 as described with reference to FIGS. 9 to 11. If the DTC code DC is a value within the first range R1, the correction circuit 80 calculates the gain correction value GC using sign information (step S2). For example, the selector 88 in FIG. 15 selects the first input terminal I1, and the selected sign information (information obtained by inverting the sign information) is output to the correction value generator 90. As a result, the selector 86 selects the sign information extracted by the sign information extractor 82 and outputs it to the correction value generator 90, thereby calculating the gain correction value GC based on the selected sign information. On the other hand, if the DTC code DC is not a value within the first range R1, the correction circuit 80 does not use the extracted sign information (step S3). For example, the selector 88 in FIG. 15 selects the second input terminal I2, and the extracted sign information is not output to the correction value generator 90.

[0096] FIG. 17 is also a flowchart illustrating the operation of the correction circuit 80. First, the correction circuit 80 determines whether the DTC code DC is a value within the first range R1 (step S11). If the DTC code DC is a value within the first range R1, the correction circuit 80 calculates the gain correction value GC using information with the sign information inverted (step S12). For example, in FIG. 15, the selector 87 selects the first input terminal I1, thereby inverting the sign information. The correction circuit 80 also determines whether the DTC code DC is a value within the second range R2 (step S13). If the DTC code DC is a value within the second range R2, the correction circuit 80 calculates the gain correction value GC using the sign information (step S14). For example, in FIG. 15, the selector 87 selects the second input terminal I2. On the other hand, if the DTC code DC is a value within the first range R1 but not within the second range R2, the correction circuit 80 does not use the extracted sign information (step S15). For example, if the DTC code DC is in a third range R3 between the first range R1 and the second range R2, the extracted sign information is not used. Specifically, the selector 88 in FIG. 15 selects the second input terminal I2, and the extracted sign information is not output to the correction value generator 90.

[0097] The first range R1, the second range R2, and the third range R3 are set, for example, by a register (not shown) provided in the circuit device 20. For example, the control unit 89 in FIG. 15 performs the process shown in FIGS. 15 and 16 based on the range setting information (range setting table) set in the register and the DTC code to select the code information. The range setting information in this case may be stored in a nonvolatile storage device, such as a nonvolatile memory or a fuse circuit. In this embodiment, if the DTC code is a value within the third range R3, the extracted code information is not used. This is not a significant problem. For example, the DTC code generated by the integrator 44 in FIG. 2 may be a value within the third range R3 at a certain timing, but may subsequently change to a value within the first range R1 or the second range R2.

[0098] 4. Oscillator 18 shows a configuration example of an oscillator 4 including a circuit device 20 of this embodiment. The oscillator 4 of this embodiment includes the circuit device 20 of this embodiment and a resonator 10 for generating a reference clock signal RFCK. For example, in FIG. 18, the resonator 10 is electrically connected to the circuit device 20. The resonator 10 and the circuit device 20 are electrically connected using, for example, internal wiring, bonding wires, metal bumps, or the like of a package that houses the resonator 10 and the circuit device 20.

[0099] The vibrator 10 is an element that generates mechanical vibrations in response to an electrical signal. The vibrator 10 can be realized by a vibrating piece such as a quartz crystal vibrating piece. For example, the vibrator 10 can be realized by a quartz crystal vibrating piece that vibrates in a thickness-shear mode, such as an AT-cut or SC-cut cut angle, a tuning-fork type quartz crystal vibrating piece, or a double-ended tuning-fork type quartz crystal vibrating piece. For example, the vibrator 10 may be a vibrator built into an SPXO (Simple Packaged Crystal Oscillator), a vibrator built into a temperature-compensated crystal oscillator (TCXO) that does not have a thermostatic oven, or a vibrator built into an oven-controlled crystal oscillator (OCXO) that has a thermostatic oven. Note that the vibrator 10 of this embodiment can also be realized by various vibrating pieces, such as a vibrating piece other than a thickness-shear type, tuning-fork type, or double-ended tuning-fork type, or a piezoelectric vibrating piece made of a material other than quartz. For example, as the vibrator 10, a SAW (Surface Acoustic Wave) resonator or a MEMS (Micro Electro Mechanical Systems) vibrator as a silicon vibrator formed using a silicon substrate can be used.

[0100] The circuit device 20 includes an oscillator circuit 130, a PLL circuit 150, a control circuit 160, and an output circuit 180. Note that the circuit device 2080 is not limited to the configuration shown in Fig. 18, and various modifications are possible, such as omitting some of the components, adding other components, or changing the components to other types of components.

[0101] The oscillator circuit 130 is a circuit that oscillates the resonator 10. For example, the oscillator circuit 130 generates an oscillation signal by oscillating the resonator 10. For example, the oscillator circuit 130 can be realized by an oscillation drive circuit electrically connected to one end and the other end of the resonator 10, and passive elements such as capacitors and resistors. The drive circuit can be realized by, for example, a CMOS inverter circuit or a bipolar transistor. The drive circuit is the core circuit of the oscillator circuit 130, and the drive circuit drives the resonator 10 with voltage or current, causing it to oscillate. Various types of oscillator circuits, such as inverter type, Pierce type, Colpitts type, or Hartley type, can be used as the oscillator circuit 130. Note that the connection in this embodiment is an electrical connection. An electrical connection is a connection that allows an electrical signal to be transmitted, and is a connection that enables information to be transmitted by the electrical signal. The electrical connection may be a connection via a passive element, etc.

[0102] The PLL circuit 150 is a PLL circuit realized by the circuits of this embodiment described with reference to Figures 1 to 3, etc. A clock signal based on an oscillation signal generated by the oscillator circuit 130 oscillating the vibrator 10 is input to the PLL circuit 150 as a reference clock signal RFCK. The PLL circuit 150 then compares the phase of the reference clock signal RFCK based on the oscillation signal of the vibrator 10 with the phase of the feedback clock signal FBCK, and generates a clock signal CK by a charge pump operation or the like.

[0103] The control circuit 160 is a logic circuit that performs various control processes and arithmetic operations. For example, the control circuit 160 controls the entire circuit device 20 and the operation sequence of the circuit device 20. The control circuit 160 also performs various processes for controlling the oscillation circuit 130. The control circuit 160 can be realized by an ASIC (Application Specific Integrated Circuit) circuit using automatic placement and routing, such as a gate array. For example, the code generation circuit 40, the correction circuit 80, etc. can be realized by this control circuit 160. The control circuit 160 may also perform temperature compensation processing. For example, the control circuit 160 performs temperature compensation processing based on the temperature detection result of a temperature sensor. This can realize an oscillator 4 such as a TCXO. In this case, a variable capacitance circuit whose capacitance is controlled based on the result of the temperature compensation processing may be provided in the oscillation circuit 130.

[0104] The output circuit 180 buffers the clock signal CK from the PLL circuit 150 and outputs the output clock signal CKQ. This output clock signal CKQ becomes the external output clock signal of the oscillator 4. This output circuit 180 corresponds to the output circuit 100 in FIGS. 2 and 3. The output circuit 180 also outputs the output clock signal CKQ when, for example, an output enable signal is active. This output enable signal can be input from the outside via an external connection terminal, for example.

[0105] As described above, the circuit device of this embodiment includes a DTC circuit that adjusts the delay time of a reference clock signal based on a DTC code, a code generation circuit that generates a DTC code based on frequency division ratio setting information, and a phase comparison circuit that has a sampling circuit that samples a slope signal based on the delay-adjusted reference clock signal and outputs a sampling voltage from the sampling circuit.The circuit device also includes a clock signal generation circuit that generates a frequency-controlled clock signal based on the sampling voltage, a frequency division circuit that divides the clock signal to generate a feedback clock signal, and a slope signal generation circuit that generates a slope signal based on the feedback clock signal.The circuit device also includes a correction circuit that extracts code information based on the sampling voltage, selects the code information according to the DTC code, and generates a gain correction value that corrects the gain of the DTC circuit based on the selected code information.

[0106] In this embodiment, the delay time of the reference clock signal is adjusted by the DTC circuit, the delay-adjusted reference clock signal is used to sample the slope signal to generate a sampling voltage, and a clock signal is generated based on this sampling voltage. This reduces the phase error between the reference clock signal and the feedback clock signal, thereby reducing phase jitter in the clock signal. While a DTC circuit that adjusts the delay time generates a gain error, this embodiment generates a gain correction value using code information selected according to the DTC code, enabling appropriate gain correction using accurate code information.

[0107] In this embodiment, the correction circuit may determine the gain correction value using the code information when the DTC code is in the first range of values.

[0108] In this way, it is possible to generate a gain correction value using code information corresponding to the first range in which the code information is considered to be accurate, thereby making it possible to prevent the occurrence of a situation in which a gain correction value is generated using inaccurate code information.

[0109] In addition, in this embodiment, the correction circuit uses sign information to determine the gain correction value when the DTC code is a value in the first range or the second range, and does not need to use sign information when the DTC code is a value in a third range between the first range and the second range.

[0110] In this way, a gain correction value is generated using code information corresponding to the first range or the second range in which the code information is considered to be accurate, while a gain correction value is not generated using code information corresponding to the third range in which the code information is considered to be inaccurate, thereby making it possible to achieve appropriate gain correction using accurate code information.

[0111] In addition, in this embodiment, when the DTC code is a value in the first range, the correction circuit may determine the gain correction value using information with the sign information inverted, and when the DTC code is a value in the second range, the correction circuit may determine the gain correction value using the sign information.

[0112] In this way, it becomes possible to appropriately respond to cases where a positive gain error occurs but the sign information is negative in the first range, or where a negative gain error occurs but the sign information is positive in the first range.

[0113] In addition, in this embodiment, the code generation circuit may include a delta-sigma modulation circuit that performs delta-sigma modulation based on frequency division ratio setting information, and may generate a DTC code and set the frequency division ratio of the frequency divider circuit based on delta-sigma modulation data from the delta-sigma modulation circuit.

[0114] In this way, in a fractional-N type PLL circuit, gain correction of the DTC circuit can be performed using an accurate gain correction value, and a clock signal with reduced phase jitter and the like can be generated.

[0115] In this embodiment, the correction circuit may also include a sign information extraction unit that extracts sign information by comparing the sampled voltage with a reference voltage.

[0116] In this way, the code information extracted by comparing the sampled voltage with the reference voltage makes it possible to identify whether the sampled voltage is above or below the reference voltage, and by using this code information, it becomes possible to realize gain correction that reduces gain error.

[0117] In this embodiment, the correction circuit may include a selection unit that selects code information according to the DTC code, and a correction value generation unit that generates a gain correction value based on the selected code information.

[0118] In this way, it is possible to accurately determine the gain correction value using code information that is appropriately selected according to the DTC code, thereby achieving gain correction for the DTC circuit.

[0119] Moreover, the oscillator of this embodiment includes the circuit device described above and a vibrator, and the circuit device includes an oscillation circuit that outputs an oscillation clock signal generated by oscillating the vibrator as a reference clock signal.

[0120] Although the present embodiment has been described in detail above, those skilled in the art will readily understand that many modifications are possible without substantially departing from the novel features and advantages of the present disclosure. Therefore, all such modifications are intended to be included within the scope of the present disclosure. For example, a term described at least once in the specification or drawings together with a different term having a broader or equivalent meaning may be replaced with that different term anywhere in the specification or drawings. Furthermore, all combinations of the present embodiment and modifications are also included within the scope of the present disclosure. Furthermore, the configurations and operations of the circuit device and oscillator are not limited to those described in the present embodiment, and various modifications are possible. [Explanation of symbols]

[0121] 4...oscillator, 10...vibrator, 20...circuit device, 30...DTC circuit, 40...code generation circuit, 42...delta-sigma modulation circuit, 44...integrator, 50...phase comparison circuit, 52...sampling circuit, 54...phase comparison circuit, 56...dead zone detection circuit, 60...clock signal generation circuit, 62, 63...charge pump circuit, 64...loop filter circuit, 66...voltage controlled oscillator circuit, 70...divider circuit, 72...slope signal generation circuit, 80...correction circuit, 82...signal information extraction unit, 83...comparison circuit, 84...conversion unit, 86...selection unit, 87, 88...selector, 89...control unit, 90...correction value generation unit, 91...integrator, 92...switch, 93...binary comparator , 94... multiplier, 95... integrator, 100... output circuit, 130... oscillator circuit, 150... PLL circuit, 160... control circuit, 180... output circuit, CK... clock signal, CKQ... output clock signal, CL, CS... capacitor, DC... DTC code, FBCK... feedback clock signal, GC... gain correction value, IS... current source, R1... first range, R2... second range, R3... third range, RA... variable resistor, RFCK, RFCKD... reference clock signal, SDIV... division ratio setting information, SLCK... slow clock signal, SLP... slope signal, SS... switch, VRF... reference voltage, VSA... sampling voltage, XFBCK... feedback clock signal

Claims

1. a DTC circuit that adjusts a delay time of a reference clock signal based on the DTC code; a code generation circuit that generates the DTC code based on frequency division ratio setting information; a phase comparator circuit having a sampling circuit that samples a slope signal based on the reference clock signal whose delay time has been adjusted, and that outputs a sampling voltage of the sampling circuit; a clock signal generation circuit that generates a frequency-controlled clock signal based on the sampling voltage; a frequency divider circuit that divides the frequency of the clock signal to generate a feedback clock signal; a slope signal generating circuit that generates the slope signal based on the feedback clock signal; a correction circuit that extracts code information based on the sampled voltage, selects the code information according to the DTC code, and generates a gain correction value that corrects a gain of the DTC circuit based on the selected code information; A circuit device comprising:

2. 2. The circuit device according to claim 1, The correction circuit A circuit device characterized in that, when the DTC code is a value in a first range, the gain correction value is calculated using the code information.

3. 3. The circuit device according to claim 2, The correction circuit A circuit device characterized in that when the DTC code is a value in the first range or the second range, the gain correction value is calculated using the code information, and when the DTC code is a value in a third range between the first range and the second range, the code information is not used.

4. 4. The circuit device according to claim 3, The correction circuit A circuit device characterized in that, when the DTC code is a value in the first range, the gain correction value is calculated using information in which the sign information is inverted, and when the DTC code is a value in the second range, the gain correction value is calculated using the sign information.

5. 2. The circuit device according to claim 1, The code generation circuit a delta-sigma modulation circuit that performs delta-sigma modulation based on the frequency division ratio setting information, and that generates the DTC code and sets the frequency division ratio of the frequency divider circuit based on delta-sigma modulation data from the delta-sigma modulation circuit.

6. 2. The circuit device according to claim 1, The correction circuit a code information extracting unit that extracts the code information by comparing the sampling voltage with a reference voltage;

7. 7. The circuit device according to claim 6, The correction circuit a selection unit that selects the code information according to the DTC code; a correction value generation unit that generates the gain correction value based on the selected code information; A circuit device comprising:

8. A circuit device according to any one of claims 1 to 7; A vibrator and Including, The circuit device comprises: An oscillator comprising an oscillation circuit that outputs an oscillation clock signal generated by oscillating the vibrator as the reference clock signal.

Images