Solid-state imaging device, driving method of the solid-state imaging device, and electronic apparatus

Abstract

To provide a solid-state imaging device, a driving method of the solid-state imaging device, and an electronic apparatus, capable of realizing both a large PDFWC and an excellent charge transfer performance in a small pixel without using a special process.SOLUTION: A solid-state imaging device includes: a transfer transistor (TG-Tr) that can transfer charges accumulated in a photoelectric conversion part (PD); a transfer auxiliary gate TAG that is formed adjacent to a transfer gate of the TG-Tr on a second substrate surface side of a substrate and capable of controlling photoelectric charge transfer and accumulation processing in the PD; and an FD to which the charges accumulated in the PD are transferred through a TG. The PD includes a first region having a first depth from the second substrate surface toward a first substrate surface in a direction orthogonal to a substrate surface, and a second region having a second depth deeper than a first depth, and the transfer auxiliary gate TAG can control charge transfer and accumulation processing between the second region and the first region in the PD.SELECTED DRAWING: Figure 3

Description

[Technical Field]

[0001] The present invention relates to a solid-state imaging device, a method for driving a solid-state imaging device, and an electronic device. [Background technology]

[0002] 2. Description of the Related Art CMOS (Complementary Metal Oxide Semiconductor) image sensors are in practical use as solid-state imaging devices (image sensors) that use photoelectric conversion elements that detect light and generate electric charges. CMOS image sensors are widely used as part of various electronic devices such as digital cameras, video cameras, surveillance cameras, medical endoscopes, personal computers (PCs), and portable terminal devices (mobile devices) such as mobile phones.

[0003] A CMOS image sensor has a photodiode (photoelectric conversion element) and a floating diffusion (FD) amplifier with a floating diffusion layer for each pixel. In recent years, CMOS image sensor modules for mobile devices and IoT have become increasingly miniaturized, making it necessary to further reduce pixel size. [Prior art documents] [Patent documents]

[0004] [Patent Document 1] US 11044429 B2 [Patent Document 2] US 2016 / 0020247 A1 [Patent Document 3] US 7750382 B2 Summary of the Invention [Problem to be solved by the invention]

[0005] However, in CMOS image sensors where pixel size is becoming increasingly smaller, there is a disadvantage that the saturation of the photodiode PD decreases as pixel size becomes smaller, and the dynamic range also decreases.

[0006] Therefore, in recent years, photodiodes PD that store charges in deep regions to improve saturation of the photodiodes PD have become mainstream.

[0007] For example, in small pixels (less than 1 um), ensuring PDFWC (Full Well Capacity) is one of the important issues, and one solution to this issue is to store photocharges in a deep region.

[0008] However, in a CMOS image sensor, if charges are stored in a deep region, it becomes difficult (insufficient) to transfer the charges to the floating diffusion FD formed in a shallow region.

[0009] To address this issue, a method has been proposed in which charges are extracted from deep positions using a vertical transfer gate (VTG).

[0010] However, VTG requires special processing, which requires special processing and additional costs.

[0011] Prior art related to ensuring PDFWC in such small pixels (less than about 1 μm) is disclosed in, for example, Patent Documents 1, 2 and 3. However, even these prior art technologies may require special processing and additional costs.

[0012] The present invention provides a solid-state imaging device that can achieve both a large PDFWC and excellent charge transfer performance in a small pixel without using a special process, a method for driving the solid-state imaging device, and electronic equipment. [Means for solving the problem]

[0013] A solid-state imaging device according to a first aspect of the present invention has a pixel section in which pixels that perform photoelectric conversion are arranged, the pixel comprising: a substrate having a first substrate surface side and a second substrate surface side opposite to the first substrate surface side; a photoelectric conversion section formed so as to be embedded between the first substrate surface side and the second substrate surface side of the substrate and having a photoelectric conversion function for received light, a photocharge transfer function, and a charge accumulation function; a transfer transistor capable of transferring charges accumulated in the photoelectric conversion section; and a transfer gate formed adjacent to the transfer transistor on the second substrate surface side of the substrate, the photoelectric conversion section having a photoelectric conversion function for received light, a photocharge transfer function, and a charge accumulation function. The photoelectric conversion unit has a transfer assist gate capable of controlling the photocharge transfer and accumulation process within the conversion unit, and a floating diffusion to which charges accumulated in the photoelectric conversion unit are transferred through the transfer transistor, wherein the photoelectric conversion unit includes a first region having a first depth from the second substrate surface toward the first substrate surface in a direction perpendicular to the substrate surface, and a second region having a second depth deeper than the first depth, and the transfer assist gate is capable of controlling the charge transfer and accumulation process between the second region and the first region in the photoelectric conversion unit.

[0014] In a second aspect of the present invention, there is provided a pixel unit in which pixels that perform photoelectric conversion are arranged, the pixel comprising: a substrate having a first substrate surface side and a second substrate surface side opposite to the first substrate surface side; a photoelectric conversion unit formed so as to be embedded between the first substrate surface side and the second substrate surface side of the substrate, and having a photoelectric conversion function of received light, a photocharge transfer function, and a charge accumulation function; a transfer transistor capable of transferring charges accumulated in the photoelectric conversion unit; a transfer assist gate formed so as to be adjacent to a transfer gate of the transfer transistor on the second substrate surface side of the substrate, and capable of controlling photocharge transfer and accumulation processes in the photoelectric conversion unit; and a floating diffusion to which charges accumulated in the photoelectric conversion unit are transferred via the transfer transistor; a first region having a first depth from a substrate surface toward the first substrate surface, and a second region having a second depth deeper than the first depth, wherein the transfer assist gate is capable of controlling charge transfer and accumulation processing between the second region and the first region in the photoelectric conversion unit, the method including an exposure mode and a readout mode, and controlling the on / off states of the transfer assist gate and the transfer transistor depending on the operation mode to read out pixel signals from the pixels in the pixel unit, and when operating in the exposure mode, controlling the transfer assist gate to an off state when operating in the readout mode to transfer and accumulate charge from the second region to the first region of the photoelectric conversion unit.

[0015] An electronic device according to a third aspect of the present invention has a solid-state imaging device and an optical system for forming an image of a subject on the solid-state imaging device, and has a pixel section in which pixels for performing photoelectric conversion are arranged, the pixel comprising: a substrate having a first substrate surface side and a second substrate surface side opposite to the first substrate surface side; a photoelectric conversion section formed so as to be embedded between the first substrate surface side and the second substrate surface side of the substrate, the photoelectric conversion section having a photoelectric conversion function for received light, a photoelectric charge transfer function, and a charge accumulation function; a transfer transistor capable of transferring charges accumulated in the photoelectric conversion section; and a transfer gate of the transfer transistor adjacent to the second substrate surface side of the substrate. The photoelectric conversion unit has a transfer assist gate formed adjacent to the second substrate surface and capable of controlling photocharge transfer and accumulation processes within the photoelectric conversion unit, and a floating diffusion to which charges accumulated in the photoelectric conversion unit are transferred through the transfer transistor, wherein the photoelectric conversion unit includes a first region having a first depth from the second substrate surface toward the first substrate surface in a direction perpendicular to the substrate surface, and a second region having a second depth deeper than the first depth, and the transfer assist gate is capable of controlling charge transfer and accumulation processes between the second region and the first region in the photoelectric conversion unit. [Effects of the Invention]

[0016] According to the present invention, it is possible to achieve both a large PDFWC and excellent charge transfer performance in a small pixel without using a special process. [Brief explanation of the drawings]

[0017] [Figure 1] 1 is a block diagram showing an example of the configuration of a solid-state imaging device according to a first embodiment of the present invention. [Figure 2] 1 is a circuit diagram illustrating an example of a pixel according to a first embodiment of the present invention. [Figure 3] 1 is a simplified cross-sectional view showing an example of the configuration of a photoelectric conversion unit, a transfer assist gate, a transfer transistor, and a floating diffusion, which are essential parts of a pixel according to a first embodiment of the present invention. [Figure 4] FIG. 2 is a diagram showing an example of a layout of a main part of a pixel according to the first embodiment of the present invention. [Figure 5] 4A and 4B are diagrams for explaining an arrangement gap in a direction parallel to a substrate surface in an arrangement space between a transfer assist gate and a transfer transistor according to the first embodiment of the present invention. [Figure 6] FIG. 10 is a diagram for explaining the advantage of arranging a transfer assist gate adjacent to a transfer gate of a transfer transistor in a pixel according to the first embodiment, in comparison with a comparative example (here, a planar transfer gate (PlannerTG)). [Figure 7] FIG. 10 is a diagram for explaining the advantage of arranging a transfer assist gate adjacent to a transfer gate of a transfer transistor in a pixel according to the first embodiment, in comparison with another comparative example (here, a photogate). [Figure 8] FIG. 10 is a diagram showing the vertical and horizontal potential distributions in a pixel according to the first embodiment when the transfer transistor and the transfer assist gate are controlled on and off to transfer photoelectrons accumulated in the second region, which is a deep region of the photodiode, which is the photoelectric conversion unit, to the first region, which is a shallow region. [Figure 9] 1 is a circuit diagram showing a simplified configuration of a drive circuit system for driving a transfer transistor and a transfer assist gate in a pixel according to a first embodiment of the present invention. [Figure 10] 2 is a diagram for explaining an example of the configuration of a readout system for column outputs of a pixel unit of a solid-state imaging device according to an embodiment of the present invention; FIG. [Figure 11] FIG. 10 is a diagram showing an example of timing of a readout operation in a pixel according to an embodiment of the present invention. [Figure 12] FIG. 4 is a diagram showing another example of the layout of the main part of the pixel according to the first embodiment of the present invention. [Figure 13] FIG. 10 is a plan view showing an example of the configuration of a pixel according to a second embodiment of the present invention. [Figure 14] FIG. 10 is a circuit diagram showing a simplified configuration of a drive circuit system for driving a transfer transistor and a transfer assist gate in a pixel according to a third embodiment of the present invention. [Figure 15]1 is a diagram illustrating an example of a configuration of an electronic device to which a solid-state imaging device according to an embodiment of the present invention is applied. DETAILED DESCRIPTION OF THE INVENTION

[0018] Hereinafter, an embodiment of the present invention will be described with reference to the drawings.

[0019] (First embodiment) FIG. 1 is a block diagram showing an example of the configuration of a solid-state imaging device according to the first embodiment of the present invention. FIG. 2 is a circuit diagram showing an example of a pixel according to the first embodiment of the present invention. FIG. 3 is a simplified cross-sectional view showing an example of the configuration of a photoelectric conversion unit, a transfer assist gate, a transfer transistor, and a floating diffusion, which are essential parts of a pixel according to the first embodiment of the present invention. FIG. 4 is a diagram showing an example of the layout of a main part of a non-shared pixel according to the first embodiment of the present invention.

[0020] As shown in FIG. 1, this solid-state imaging device 10 has, as its main components, a pixel section 20 as an imaging section, a vertical scanning circuit (row scanning circuit) 30, a readout circuit (column readout circuit) 40, a horizontal scanning circuit (column scanning circuit) 50, and a timing control circuit 60. Of these components, for example, the vertical scanning circuit 30, the readout circuit 40, the horizontal scanning circuit 50, and the timing control circuit 60 constitute a pixel signal readout unit 70. In this embodiment, the solid-state imaging device 10 is configured by, for example, a back-illuminated CMOS image sensor.

[0021] In this first embodiment, the solid-state imaging device 10 has pixels (or pixel sections 20) PXL arranged in a matrix in the pixel section 20, as will be described in detail later, and the pixels PXL are formed to include a buried photodiode (PPD) as a photoelectric conversion section PD.

[0022] The pixel PXL of this first embodiment includes a substrate 210 having a first substrate surface side (e.g., a back surface side) onto which light is irradiated and a second substrate surface side (front surface side) opposite to the first substrate surface side, a photoelectric conversion unit (photodiode PD) including a first conductivity type (e.g., n-type in this embodiment) semiconductor layer (hereinafter sometimes referred to as an n layer) formed so as to be embedded between the first substrate surface side and the second substrate surface side of the substrate 210, and having a photoelectric conversion function of received light, a photocharge transfer function, and a charge storage function, a transfer transistor TG-Tr capable of transferring the charge stored in the photoelectric conversion unit PD, a transfer assist gate TAG formed adjacent to the transfer gate GTG of the transfer transistor TG-Tr on the second substrate surface side of the substrate and capable of driving and controlling the photocharge transfer and storage processes within the photoelectric conversion unit PD, and a floating diffusion FD to which the charge stored in the photoelectric conversion unit PD is transferred via the transfer transistor TG-Tr.

[0023] A second conductivity type (p type in this embodiment) semiconductor layer (hereinafter sometimes referred to as p layer) is formed at least on the side of the first conductivity type semiconductor layer of the photoelectric conversion section PD.

[0024] Furthermore, the photoelectric conversion unit PD of the pixel PXL according to this first embodiment includes a first region AR1 having a first depth DP1 from the second substrate surface 212 toward the first substrate surface 211 in a direction perpendicular to the substrate surface, and a second region AR2 having a second depth DP2 deeper than the first depth DP1. Under the control of the readout unit 70, the transfer assist gate TAG can control the charge transfer and accumulation process between the second region AR2 and the first region AR1 in the photoelectric conversion unit PD.

[0025] In the first embodiment, the transfer assist gate TAG is formed on the second substrate surface 212 side so as to have a spatial overlapping portion with at least a part of the first region AR1 of the photoelectric conversion unit PD in a direction perpendicular to the substrate surface. The transfer gate GTG of the transfer transistor TG-Tr is formed adjacent to the transfer assist gate TAG on the second substrate surface 212 side in a direction parallel to the substrate surface.

[0026] In the placement space SP1 between the transfer assist gate TAG and the transfer transistor TG-Tr, a placement gap GP1 in a direction parallel to the substrate surface is formed to include a distance that allows charge transfer at least between the transfer assist gate TAG and the transfer transistor TG-Tr.

[0027] Furthermore, in the pixel 200 (PXL) according to the first embodiment, the photoelectric conversion section (PD) including the first region AR1 and the second region AR2 is formed of a first conductivity type semiconductor layer (in this embodiment, the first conductivity type layer is an n-layer), and a second conductivity type semiconductor layer (in this embodiment, the second conductivity type layer is a p-layer) for depletion is formed on the surface of the first conductivity type semiconductor layer in the first region AR1 on the second substrate surface 212 side.

[0028] In the solid-state imaging device 10 according to the first embodiment, the readout section 70 includes an exposure mode MEXP and a readout mode MRDO as operating modes, and controls the on / off states of the transfer assist gate TAG and the transfer transistor TG1-Tr according to the operating mode to read out pixel signals from the pixel 200 (PXL) of the pixel section 20. When the readout section 70 operates in the exposure mode, it controls the transfer assist gate TAG to be in the OFF state. When operating in the read mode, the readout section 70 controls the transfer assist gate TAG to the on state when transferring and storing electric charges from the second region AR2 to the first region AR1 of the photoelectric conversion section PD.

[0029] The readout unit 70 also has operation modes including an exposure mode and a readout mode, and reads out pixel signals from the pixels of the pixel unit 20 . When the readout section 70 operates in the exposure mode and during the exposure phase, the readout section 70 controls the transfer assist gate TAG and the transfer transistor TG-Tr to be in the off state. When the read section 70 operates in the read mode and during the read phase, it controls the transfer assist gate TAG and the transfer transistor TG-Tr to an on state for a predetermined period of time, and then controls the transfer assist gate (TAG) to an off state before controlling the transfer transistor TG-Tr to an off state.

[0030] Below, we will first explain the overview of the configuration and function of each part of the solid-state imaging device 10, and then provide a detailed description of a specific configuration example of a pixel PXL having a buried diode (PPD) part, a transfer transistor TG1-Tr, a transfer assist gate TAG1, and a floating diffusion FD.

[0031] (Configuration of pixel section 20 and pixel PXL) The pixel section 20 has a plurality of pixels, each including a photodiode (photoelectric conversion element) and an in-pixel amplifier, arranged in a two-dimensional matrix of N rows and M columns.

[0032] FIG. 2 shows an example of a circuit diagram of a pixel according to the first embodiment.

[0033] This pixel PXL has, for example, a photodiode PD1 which is a photoelectric conversion unit (photoelectric conversion element). This photodiode PD1 has one transfer transistor TG1-Tr as a charge transfer gate unit (transfer element), one transfer assist gate TAG1, one reset transistor RST1-Tr as a reset element, one source follower transistor SF1-Tr as a source follower element, and one select transistor SEL1-Tr as a select element.

[0034] The photodiode PD1 generates and accumulates signal charges (electrons in this case) in an amount corresponding to the amount of incident light. In the following, the case where the signal charges are electrons and each transistor is an n-type transistor will be described, but the signal charges may be holes and each transistor may be a p-type transistor. This embodiment is also effective when a plurality of photodiodes share each transistor, or when a four-transistor (4Tr) pixel that does not have a selection transistor is used.

[0035] In each pixel PXL, a buried photodiode (PPD) is used as the photodiode PD1. The surface of the substrate on which the photodiode PD1 is formed has surface states due to defects such as dangling bonds, so a large amount of charge (dark current) is generated by thermal energy, making it impossible to read out a correct signal. In a buried photodiode (PPD), the charge storage portion of the photodiode PD1 is buried in the substrate, thereby making it possible to reduce the mixing of dark current into the signal.

[0036] The transfer transistor TG1-Tr is connected between a transfer assist gate TAG1 arranged close to the charge storage region of a buried photodiode (PPD) and a floating diffusion FD (Floating Diffusion) 1, and is controlled via a first control signal CTG. The transfer transistor TG1-Tr is selected and turned on while the first control signal CTG is at high level (H), and transfers the charges (electrons) photoelectrically converted and accumulated in the photodiode PD1 to the floating diffusion FD1.

[0037] As will be described in detail later, the transfer assist gate TAG1 is formed so as to be adjacent to the transfer gate GTG of the transfer transistor TG1-Tr on the second substrate surface 212 side of the substrate. The transfer assist gate TAG1 is controlled through a second control signal CTA.

[0038] FIG. 3 is a simplified cross-sectional view showing an example of the configuration of a photodiode (photoelectric conversion unit) PD1, a transfer assist gate TAG1, a transfer transistor TG1-Tr, and a floating diffusion FD1, which are essential parts of a pixel according to the first embodiment of the present invention. An example of the configuration of the main part of a pixel according to the first embodiment of the present invention will be described below with reference to FIG. Here, a pixel including a pinned photodiode (PPD) is denoted by reference numeral 200.

[0039] (Specific configuration example of pixel 200 (PXL)) The pixel 200 of the first embodiment includes a substrate 210 having a first substrate surface 211 side (for example, a back side) onto which light is irradiated and a second substrate surface 212 side (front side) opposite to the first substrate surface 211 side, a photodiode (photoelectric conversion unit) PD1 including a first conductivity type (for example, n-type in the present embodiment) semiconductor layer (hereinafter, sometimes referred to as an n-layer) formed so as to be embedded between the first substrate surface 211 side and the second substrate surface 212 side of the substrate 210 and having a photoelectric conversion function for received light, a photocharge transfer function, and a charge storage function, a transfer transistor TG1-Tr capable of transferring the charge stored in the photodiode PD1, a transfer assist gate TAG1 formed adjacent to the transfer gate GTG of the transfer transistor TG1-Tr on the second substrate surface 212 side of the substrate 210 and capable of driving and controlling the photocharge transfer and storage processes in the photodiode PD1, and a floating diffusion FD1 to which the charge stored in the photodiode PD1 is transferred via the transfer transistor TG1-Tr.

[0040] A second conductivity type (p type in this embodiment) semiconductor layer (hereinafter sometimes referred to as p layer) 220 is formed at least on the side of the first conductivity type semiconductor layer of the photodiode (photoelectric conversion unit) PD1.

[0041] Furthermore, in the pixel 200 according to the first embodiment, the photoelectric conversion section (PD) including the first region AR1 and the second region AR2 is formed of a first conductivity type semiconductor layer (in this embodiment, the first conductivity type layer is an n-layer), and a second conductivity type semiconductor layer for depletion (in this embodiment, the second conductivity type layer is a p-layer) is formed on the surface of the first conductivity type semiconductor layer in the first region AR1 on the second substrate surface 212 side.

[0042] Furthermore, the photodiode (photoelectric conversion unit) PD1 of the pixel 200 according to this first embodiment includes a first region AR1 having a first depth DP1 from the second substrate surface 212 toward the first substrate surface 211 in a direction perpendicular to the substrate surface, and a second region AR2 having a second depth DP2 deeper than the first depth DP1. Under the control of the readout section 70, the transfer assist gate TAG1 can control the charge transfer and accumulation process between the second region AR2 and the first region AR1 in the photodiode (photoelectric conversion section) PD1.

[0043] In this first embodiment, the transfer assist gate TAG1 is formed on the second substrate surface 212 side so as to have a spatial overlap with at least a portion of the first region AR1 of the photodiode (photoelectric conversion unit) PD1 in a direction perpendicular to the substrate surface. The transfer gate GTG of the transfer transistor TG1-Tr is formed adjacent to the transfer assist gate TAG1 on the second substrate surface 212 side in a direction parallel to the substrate surface.

[0044] FIG. 5 is a diagram for explaining a placement gap GP1 in a direction parallel to the substrate surface in the placement space SP1 between the transfer assist gate TAG1 and the transfer transistor TG1-Tr. In the solid-state imaging device 10 according to the first embodiment, in the arrangement space SP1 between the transfer assist gate TAG1 and the transfer transistor TG-Tr, an arrangement gap GP1 in a direction parallel to the substrate surface is formed to include at least a gap GP11 that enables charge transfer between the transfer assist gate TAG1 and the transfer transistor TG1-Tr.

[0045] In the example of Figure 5, when the placement space SP1 is large and the transfer transistor TG1-Tr is in the off state, no charge is collected (stored) in the placement gap GP1 region, whereas when the placement space SP1 is large and the transfer transistor TG1-Tr is in the on state, charge is collected (stored) in the placement gap GP1 region. Therefore, the placement gap GP1 region has a distance GP11 that allows charges to be collected (stored) in the placement gap GP1 region even when the transfer transistor TG1-Tr is in an off state, and this distance GP11 is preferably minimized.

[0046] As described above, in this first embodiment, the transfer assist gate TAG1 is formed on the second substrate surface 212 side so as to have a spatial overlap with at least a portion of the first region AR1 of the photodiode (photoelectric conversion unit) PD1 in a direction perpendicular to the substrate surface. The transfer gate GTG of the transfer transistor TG1-Tr is formed adjacent to the transfer assist gate TAG1 on the second substrate surface 212 side in a direction parallel to the substrate surface.

[0047] Here, the advantages of placing the transfer assist gate TAG1 adjacent to the transfer gate GTG of the transfer transistor TG1-Tr in the pixel 200 will be explained in comparison with a comparative example (here, a planar transfer gate (PlannerTG) or a photogate Photo-gate).

[0048] Figures 6(A) and (B) are diagrams for explaining the advantages of placing the transfer assist gate TAG1 close to the transfer gate GTG of the transfer transistor TG1-Tr in the pixel 200 according to the first embodiment, in comparison with a comparative example (here, a planar transfer gate (PlannerTG)). 7A and 7B are diagrams for explaining the advantage of arranging the transfer assist gate TAG1 adjacent to the transfer gate GTG of the transfer transistor TG1-Tr in the pixel 200 according to the first embodiment, in comparison with another comparative example (here, a photogate). Figure 8 is a diagram showing the vertical and horizontal potential distributions in the pixel 200 according to the first embodiment when the transfer transistor TG1-Tr and the transfer assist gate TAG1 are controlled on and off to transfer photoelectrons accumulated in the second region AR2, which is a deep region of the photodiode PD1, which is the photoelectric conversion unit, to the first region AR1, which is a shallow region.

[0049] (TAG effect) In the pixel 200 according to the first embodiment, an additional transfer assist gate TAG1 is arranged to improve both the PDFWC and the charge transfer performance without using a special process.

[0050] In the pixel 200 according to the first embodiment, the role of the transfer assist gate TAG is to transfer photoelectrons accumulated in the second region AR2, which is a deep region of the photodiode PD1, which is the photoelectric conversion unit, to the first region AR1, which is a shallow region. In this case, the transfer assist gate TAG1 is controlled to be in the ON state.

[0051] The role of the transfer transistor TG1-Tr is to transfer photoelectrons from the first region AR1, which is a shallow region, to the floating diffusion FD. In this case, the transfer transistor TG1-Tr is controlled to be in the on state.

[0052] In a small pixel of less than 1 μm, in order to increase PDFWC, it is necessary to accumulate photoelectrons not only in the first region AR1 of the shallow photoelectric conversion portion PD1 but also in the second region AR2 of the deep photoelectric conversion portion PD1. However, since the channel is formed only in the surface region, it is difficult to achieve complete charge transfer from the deep second region AR2 of the photoelectric conversion unit PD1 to the floating diffusion FD1 in the planar TG.

[0053] Also, as shown in FIG. 7, it is possible to provide a photogate PHG instead of providing a planar TG. However, the photogate PHG has a large dark current. Furthermore, in pixels to which the photogate PHG is applied, the pixels are controlled to be constantly on during exposure, and the storage region is completely depleted. In addition, the pixel 200 according to the first embodiment is controlled to be always in an off state during exposure, and the photoelectric conversion unit PD1 is completely depleted by the P+NP doping structure.

[0054] In the pixel 200 according to the first embodiment, an additional transfer assist gate TAG1 is arranged to improve both the PDFWC and the charge transfer performance without using a special process. Furthermore, as in the pixel according to the first embodiment, it is possible to transfer photoelectrons accumulated in the second region AR2, which is a deep region of the photodiode PD1, which is the photoelectric conversion unit, to the first region AR1, which is a shallow region, thereby making it possible to improve both the PDFWC and the charge transfer performance without using any special process.

[0055] For example, when photoelectrons accumulated in the second region AR2, which is a deep region of the photodiode PD1, which is a photoelectric conversion unit, are collected in the first region AR1, which is a shallow region, the transfer assist gate TAG1 is controlled to the on state. On the other hand, when photoelectrons are transferred from the first region AR1, which is a shallow region, to the floating diffusion FD, the transfer transistor TG1-Tr is controlled to be in an on state.

[0056] The photodiode (photoelectric conversion unit) PD1 of the pixel 200 (PXL) according to this first embodiment includes, as shown in FIG. 3, a first region AR1 having a first depth DP1 from the second substrate surface 212 toward the first substrate surface 211 in a direction perpendicular to the substrate surface, and a second region AR2 having a second depth DP2 deeper than the first depth DP1. Under the control of the readout section 70, the transfer assist gate TAG1 can control the charge transfer and accumulation process between the second region AR2 and the first region AR1 in the photodiode (photoelectric conversion section) PD1 through a second control signal CTA.

[0057] In the first embodiment, the transfer transistor TG1-Tr and the transfer assist gate TAG1 are driven and controlled at separate timings through different first and second control signals CTG and CTA.

[0058] FIG. 9 is a circuit diagram showing in simplified form the configuration of a drive circuit system for driving the transfer transistor and the transfer assist gate in the pixel according to the first embodiment of the present invention.

[0059] In the pixel 200 (PXL) in FIG. 9, the transfer gate GTG of the transfer transistor TG1-Tr is connected to a first control signal line SL1 to which a first control signal CTG is supplied. The transfer assist gate TAG1 is connected to a second control signal line SL2 to which a second control signal CTA is supplied. In the drive circuit 250 of FIG. 9, the first control signal line SL1 is connected to the first driver DR1, and the second control signal line SL2 is connected to the second driver DR2. In this configuration, the readout section 70 controls the on / off of the transfer transistor TG1-Tr using a first control signal CTG, and controls the on / off of the transfer assist gate TAG1 using a second control signal CTA.

[0060] In the example of FIG. 2, the reset transistor RST1-Tr is connected to, for example, a power supply potential VDD and a floating diffusion FD1, and is controlled via a third control signal RST. The reset transistor RST1-Tr is selected and turned on while the third control signal RST is at H level, and resets the floating diffusion FD1 to the power supply potential VDD.

[0061] The source follower transistor SF1-Tr and the selection transistor SEL1-Tr are connected in series between the power supply potential VDD and the vertical signal line LSGN1 to which the current source IS is connected. A floating diffusion FD1 is connected to the gate of the source follower transistor SF1-Tr, and the selection transistor SEL1-Tr is controlled via a fourth control signal SEL. The selection transistor SEL1-Tr is selected and turned on while the fourth control signal SEL is at H level, which causes the source follower transistor SF1-Tr to output a column output read signal VSL corresponding to the charge amount (potential) of the floating diffusion FD to the vertical signal line LSGN1. These operations are performed simultaneously in parallel for each pixel in one row, since the gates of the transfer transistor TG1-Tr, transfer assist gate TAG1, reset transistor RST1-Tr, and selection transistor SEL1-Tr are connected row by row.

[0062] In the pixel section 20, the pixels PXL are arranged in N rows and M columns, so there are N control lines LSEL, LRST, LTG, and LSG, and M vertical signal lines LSGN1. In FIG. 1, each of the control lines LSEL, LRST, LTG, and LSG is represented as one row scanning control line.

[0063] The vertical scanning circuit 30 drives pixels in the shutter row and readout row through row scanning control lines under the control of the timing control circuit 60 . Furthermore, the vertical scanning circuit 30 outputs a row selection signal of a read row for reading out a signal and a row address of a shutter row for resetting the charge accumulated in the photodiode PD1 in accordance with the address signal.

[0064] The readout circuit 40 may include a plurality of column signal processing circuits (not shown) arranged corresponding to the respective column outputs of the pixel section 20, and may be configured so that the plurality of column signal processing circuits are capable of performing column-parallel processing.

[0065] The readout circuit 40 can be configured to include a correlated double sampling (CDS) circuit, an ADC (analog-to-digital converter), an amplifier (AMP), a sample-and-hold (S / H) circuit, and the like.

[0066] In this way, the readout circuit 40 may be configured to include an ADC 41 that converts the readout signal VSL of each column output of the pixel section 20 into a digital signal, as shown in FIG. 10(A), for example. Alternatively, the readout circuit 40 may include an amplifier (AMP) 42 that amplifies the readout signal VSL output from each column of the pixel section 20, as shown in FIG. 10(B), for example. Furthermore, the readout circuit 40 may include a sample-and-hold (S / H) circuit 43 that samples and holds the readout signal VSL output from each column of the pixel section 20, as shown in FIG. 10(C), for example.

[0067] The horizontal scanning circuit 50 scans and transfers signals processed by a plurality of column signal processing circuits such as ADCs of the readout circuit 40 in the horizontal direction, and outputs them to a signal processing circuit (not shown).

[0068] The timing control circuit 60 generates timing signals necessary for signal processing in the pixel section 20, the vertical scanning circuit 30, the readout circuit 40, the horizontal scanning circuit 50, and the like.

[0069] 11A to 11C are diagrams showing an example of the timing of the readout operation on the pixels by the readout section 70 according to the embodiment of the present invention. FIG. 11(A) shows a first control signal CTG for driving and controlling the transfer transistor TG-Tr, and FIG. 11(B) shows a second control signal CTA for driving and controlling the transfer assist gate TAG. FIG. 11(C) shows the exposure phase and the readout phase. In the first embodiment, the transfer transistor TG-Tr and the transfer assist gate TAG1 are driven and controlled at individual timings through different first and second control signals CTG and CTA.

[0070] Furthermore, in the solid-state imaging device 10 according to the first embodiment, the readout section 70 includes an exposure mode and a readout mode as operating modes, and controls the on / off states of the transfer assist gate TAG and the transfer transistor TG1-Tr according to the operating mode to read out pixel signals from the pixels 200 of the pixel section 20. When the readout section 70 operates in the exposure mode, it controls the transfer assist gate TAG to be in the OFF state. When operating in the read mode, the readout section 70 controls the transfer assist gate TAG to the on state when transferring and storing electric charges from the second region AR2 to the first region AR1 of the photoelectric conversion section PD.

[0071] The readout unit 70 also has operation modes including an exposure mode and a readout mode, and reads out pixel signals from the pixels 200 of the pixel unit 20 . When the readout section 70 operates in the exposure mode and during the exposure phase, the readout section 70 controls the transfer assist gate TAG1 and the transfer transistor TG1-Tr to be in the off state. When the read section 70 operates in the read mode and during the read phase, it controls the transfer assist gate TAG1 and the transfer transistor TG1-Tr to an on state for a predetermined period of time, and then controls the transfer assist gate (TAG) to an off state before controlling the transfer transistor TG1-Tr to an off state.

[0072] As described above, the pixel 200 (PXL) in the solid-state imaging device according to the first embodiment has a photodiode (photoelectric conversion unit PD) region having a second region AR2 which is a deep region and a first region AR1 which is a shallow region, the transfer assist gate TAG is located on the photodiode (photoelectric conversion unit PD) region near the first region AR1 which is a shallow region, and the transfer assist gate TAB is adjacent to the transfer gate of the transfer transistor TG1-Tr. When the solid-state imaging device 10 operates in the exposure procedure, the transfer assist gate TAG is turned off. Here, the transfer assist gate TAG is turned on when the solid-state imaging device 10 operates in the readout procedure and accumulates photoelectrons (charges) from the second region AR2, which is a deep region, to the first region AR1, which is a shallow region. In this structure, the role of the transfer assist gate TAG is to transfer the photoelectrons (charges) accumulated in the second region AR2, which is a deep region, to the first region AR1, which is a shallow region. The role of the transfer transistor TG-Tr is to transfer the photoelectrons (charges) from the first region AR1, which is a shallow region, to the floating diffusion FD. This allows photoelectrons (charges) from the second region AR2, which is a deep region, and the first region AR1, which is a shallow region, to be accumulated in the floating diffusion region. As a result, both a large PDFWC and good charge transfer can be achieved. Furthermore, this structure does not require any special process for implementation, which does not incur additional costs.

[0073] That is, the solid-state imaging device 10 according to the first embodiment can improve both the PDFWC and the charge transfer performance without using any special process. Since no special process (other than the standard CMOS process) is required, the transfer assist gate TAG can be fabricated using the same process as the transfer transistor TG-Tr.

[0074] Furthermore, according to the solid-state imaging device 10 of the first embodiment, the layout design of the image sensor device can be a non-shared layout as shown in FIG. 4, but depending on the device structure, a two-pixel shared layout or a four-pixel shared layout as shown in FIGS. 12(A) and 12(B) can be adopted.

[0075] In the shared pixel 200C, one floating diffusion FD is shared by multiple (in this example, two or four) photoelectric conversion units PD, multiple transfer transistors TG-Tr, and multiple transfer assist gates TAG, and the floating diffusion FD is located in the center of the element formation region. A plurality of photoelectric conversion units PD, a plurality of transfer transistors TG-Tr, and a plurality of transfer assist gates TAG are arranged radially around the floating diffusion FD.

[0076] (Second embodiment) 13A and 13B are plan views showing an example of the configuration of a pixel according to the second embodiment of the present invention. FIG. 13(A) shows a layout pattern of a pixel according to the second embodiment, and FIG. 13(B) shows the potential characteristics in the charge transfer path of the pixel according to the second embodiment.

[0077] The pixel 200A of the second embodiment differs from the pixel 200 (FIG. 4) of the first embodiment in the following respects.

[0078] In the pixel 200A of the second embodiment, the transfer transistor TG-Tr and the transfer assist gate TAG include a pair of modulation gates arranged along the charge transfer path between the floating diffusion FD and the photoelectric conversion unit PD (and the transfer assist gate TAG), and have a lateral electric field modulation (LEFM) structure in which a lateral electric field is applied to the modulation gate whose transfer path is pinned by the second conductivity type semiconductor layer to control the potential of the photoelectric conversion unit (and the transfer assist gate TAG).

[0079] In the second embodiment, a lateral electric field modulation (LEFM) structure can be adopted, which includes a pair of first modulation gates TG1 and TG2 along the charge transfer path CTP between the floating diffusion FD and the photodiode PD (photoelectric conversion unit and transfer assist gate TAG), and in which a voltage is applied to the first modulation gates TGM1 and TGM2 whose transfer path TP is pinned by a second conductivity type (p-type) semiconductor layer to control the lateral electric field of the photodiode PD (photoelectric conversion unit).

[0080] In this LEFM-TG structure, the potential of the photodiode PD is controlled by applying a voltage. LEFM-TG has the advantage that all the transport paths TP are pinned by the p-layer, so there are no barriers in the transport paths and no traps, thus realizing low dark current.

[0081] In contrast, in the comparative example without LEFM-TG, the gate TGM is on during the exposure time, so there are many traps under the TGM gate, which causes a large dark current.

[0082] Here, the operation, efficiency, etc. of the charge transfer system in the main part of the pixel according to the comparative example and the second embodiment of the present invention will be described.

[0083] In the comparative example structure, when a low voltage such as 1.5 V is applied to the gate TGM, there is a PD-TG barrier and a barrier under the gate TG, which causes an obstruction to the transfer of electrons generated from the photodiode PD to the floating diffusion FD. Therefore, a high voltage such as 2.7V must be applied. However, when a high voltage is applied, there is a risk that electrons from the floating diffusion FD may flow back and enter under the gate TG, a phenomenon known as pumping. Furthermore, while the gate TG is on, there are no holes under the gate TG, and a large amount of dark current is generated from the traps under the gate TG.

[0084] In contrast, in the LEFM structure according to the second embodiment, even if a low voltage such as 1.5 V is applied to the gate TGM, an electric field gradient is generated in the entire region of the charge transfer path from the photodiode PD to the floating diffusion FD, allowing electric field transfer without any barriers. Therefore, there is no need to increase the potential of the charge transfer path CTP, and the problem of backflow of charges from the floating diffusion FD does not occur. In addition, even when the gate TGM of the LEFM structure is turned on, the transfer path to the floating diffusion FD is covered with a high concentration of holes, just like the PD, making it possible to prevent dark current from traps. Compared to the comparative example (conventional) structure, the LEFM structure of the second embodiment can be driven at a low voltage, which is expected to reduce power consumption, provide better charge transfer efficiency, and reduce noise by eliminating charge traps. Furthermore, according to the second embodiment, since a pair of gates TGM are provided, it is possible to unify (uniform) the bias between both gates TGM1 and TGM2.

[0085] Thus, a further advantage of the gate TGM with the LEFM structure is that it can prevent charge spillback from the gate TGM when the gate TGM is turned off (at the start of exposure). In the comparative conventional case, charge exists under the gate TGM while the gate TGM is high to drain unwanted charge to the drain node. These charges can spill over to the photodiode PD when the gate TGM gates off to begin exposure. In the LEFM structure, the transfer path TP has a large potential gap to the drain node DRN, and there is no risk of spillback.

[0086] (Third embodiment) FIG. 14 is a circuit diagram showing in simplified form the configuration of a drive circuit system for driving the transfer transistor and the transfer assist gate in a pixel according to the third embodiment of the present invention.

[0087] The pixel 200B of the solid-state imaging device 10B according to the third embodiment differs from the pixel 200 of the solid-state imaging device 10 according to the first embodiment in the following respects.

[0088] The pixel 200B of the solid-state imaging device 10B according to the third embodiment is configured to be able to generate the control signals STA and STG in common in order to reduce the number of input drivers DR and pulse signal wirings SL of each pixel 200B in the drive circuit system 250.

[0089] Specifically, in pixel 200B, the transfer gate of the transfer transistor TG1-Tr is connected to a first control signal line SL1 to which a first control signal CTG is supplied, and the transfer assist gate TAG is connected to the first control signal line SL1. A delay element DLY for delaying a signal by a predetermined time is connected to a first control signal line SL1 connected between the transfer gate and the transfer assist gate TAG. The delay element DLY is formed by, for example, a capacitor C. The second control signal CTA for controlling the transfer assist gate TAB includes a signal formed by delaying the first control signal CTG by a predetermined time using the delay element DLY.

[0090] In this way, the pixels 200B of the solid-state imaging device 10B are configured to be able to generate the control signals STA and STG in common, thereby reducing the number of input drivers DR and pulse signal wirings SL for each pixel 200B in the drive circuit system 250. Therefore, according to the third embodiment, the circuit area of the pixel can be reduced, and furthermore, the chip area and the device can be made smaller.

[0091] The solid-state imaging devices 10, 10A, and 10B described above can be applied as imaging devices to electronic devices such as digital cameras, video cameras, mobile terminals, surveillance cameras, and medical endoscope cameras.

[0092] FIG. 15 shows a camera system to which a solid-state imaging device according to an embodiment of the present invention is applied. FIG. 10 is a diagram illustrating an example of the configuration of an electronic device.

[0093] As shown in FIG. 15, the electronic device 300 includes a CMOS image sensor 310 to which the solid-state imaging devices 10, 10A, and 10B according to the present embodiment can be applied. Furthermore, the electronic device 300 has an optical system (lens or the like) 320 that guides incident light to the pixel region of the CMOS image sensor 310 (forming an image of a subject). The electronic device 300 includes a signal processing circuit (PRC) 330 that processes the output signal of the CMOS image sensor 310 .

[0094] The signal processing circuit 330 performs predetermined signal processing on the output signal of the CMOS image sensor 310 . The image signal processed by the signal processing circuit 330 can be displayed as a moving image on a monitor such as an LCD display, or output to a printer, or can be recorded directly on a recording medium such as a memory card, and various other forms are possible.

[0095] As described above, by incorporating the above-described solid-state imaging devices 10, 10A, and 10B as the CMOS image sensor 310, it is possible to provide a high-performance, small-sized, and low-cost camera system. This makes it possible to realize electronic devices such as surveillance cameras and medical endoscope cameras that are used in applications where camera installation requirements include constraints such as mounting size, number of connectable cables, cable length, and installation height. [Explanation of symbols]

[0096] 10, 10A, 10B... solid-state imaging device, 20... pixel section, PD... photoelectric conversion section (photodiode), FD... floating diffusion, TG-Tr... transfer transistor, TAB... transfer assist gate, 200 (PXL)... pixel, 30... vertical scanning circuit, 40... output circuit, 50... timing control circuit, 60... readout section, 300... electronic device, 310... CMOS image sensor, 320... optical system, 330... signal processing circuit (PRC).

Claims

1. a pixel section in which pixels that perform photoelectric conversion are arranged; The pixel is a substrate having a first substrate surface side and a second substrate surface side opposite to the first substrate surface side; a photoelectric conversion unit formed so as to be embedded between the first substrate surface side and the second substrate surface side of the substrate, the photoelectric conversion unit having a photoelectric conversion function for received light, a photoelectric charge transfer function, and a charge accumulation function; a transfer transistor capable of transferring charges accumulated in the photoelectric conversion unit; a transfer assist gate formed adjacent to the transfer gate of the transfer transistor on the second substrate surface side of the substrate, the transfer assist gate being capable of controlling photocharge transfer and accumulation processing within the photoelectric conversion unit; a floating diffusion to which the charges accumulated in the photoelectric conversion unit are transferred through the transfer transistor; and The photoelectric conversion unit is a first region having a first depth from the second substrate surface toward the first substrate surface in a direction perpendicular to the substrate surface; a second region having a second depth greater than the first depth; The transfer assist gate is The charge transfer and accumulation process between the second region and the first region in the photoelectric conversion unit can be controlled. Solid-state imaging device.

2. The transfer assist gate is the second substrate surface side is formed so as to have a spatially overlapping portion with at least a portion of the first region of the photoelectric conversion unit in a direction perpendicular to the substrate surface, The transfer gate of the transfer transistor is On the second substrate surface side, the transfer assist gate is formed adjacent to the transfer assist gate in a direction parallel to the substrate surface.

2. The solid-state imaging device according to claim 1.

3. In the arrangement space between the transfer assist gate and the transfer transistor, an arrangement gap in a direction parallel to the substrate surface is formed to include a distance that allows charge transfer at least between the transfer assist gate and the transfer transistor.

3. The solid-state imaging device according to claim 2.

4. The photoelectric conversion portion including the first region and the second region is formed of a first conductivity type semiconductor layer, and a second conductivity type semiconductor layer for depletion is formed on a surface of the first conductivity type semiconductor layer in the first region on the second substrate surface side.

4. The solid-state imaging device according to claim 3.

5. a readout unit that includes an exposure mode and a readout mode as operation modes, controls the on / off states of the transfer assist gate and the transfer transistor according to the operation mode, and reads out pixel signals from the pixels of the pixel unit; The readout unit When operating in the exposure mode, the transfer assist gate is controlled to be in an off state; When operating in the read mode, the transfer assist gate is controlled to be in an on state when charges are transferred from the second region to the first region of the photoelectric conversion unit and stored therein.

3. The solid-state imaging device according to claim 2.

6. an exposure mode and a readout mode as operation modes, and a readout unit that reads out pixel signals from the pixels of the pixel unit; The readout unit When operating in the exposure mode, during an exposure phase, the transfer assist gate and the transfer transistor are controlled to be in an off state; When operating in the read mode and during the read phase, the transfer assist gate and the transfer transistor are controlled to be in an on state for a predetermined period, and then the transfer assist gate is controlled to be in an off state before the transfer transistor is controlled to be in an off state.

3. The solid-state imaging device according to claim 2.

7. The transfer transistor and the transfer assist gate are The photoelectric conversion element has a lateral electric field modulation (LEFM) structure including a pair of modulation gates arranged along the charge transfer path between the floating diffusion and the photoelectric conversion element, and the transfer path is pinned by a first conductivity type semiconductor layer to apply a lateral electric field to the modulation gates to control the potential of the photoelectric conversion element.

7. The solid-state imaging device according to claim 5.

8. The readout unit The transfer transistor is turned on and off by a first control signal; The transfer assist gate is turned on and off by a second control signal; In the pixel, a transfer gate of the transfer transistor is connected to a first control signal line to which the first control signal is supplied; The transfer assist gate is connected to a second control signal line to which the second control signal is supplied.

7. The solid-state imaging device according to claim 5.

9. The readout unit The transfer transistor is turned on and off by a first control signal; The transfer assist gate is turned on and off by a second control signal; In the pixel, a transfer gate of the transfer transistor is connected to a first control signal line to which the first control signal is supplied; the transfer assist gate is connected to the first control signal line; a delay element that delays a signal by a predetermined time is connected to the first control signal line connected between the transfer gate and the transfer assist gate; The second control signal for controlling the transfer assist gate includes a signal formed by delaying the first control signal by a predetermined time using a delay element.

7. The solid-state imaging device according to claim 5.

10. The pixel unit Shared pixels that perform photoelectric conversion are arranged, The shared pixel is one floating diffusion is shared by a plurality of the photoelectric conversion units, a plurality of the transfer transistors, and a plurality of the transfer assist gates; The floating diffusion is disposed in the center of the element formation region, and the photoelectric conversion units, the transfer transistors, and the transfer assist gates are radially disposed around the floating diffusion.

7. The solid-state imaging device according to claim 5.

11. a pixel section in which pixels that perform photoelectric conversion are arranged; The pixel is a substrate having a first substrate surface side and a second substrate surface side opposite to the first substrate surface side; a photoelectric conversion unit formed so as to be embedded between the first substrate surface side and the second substrate surface side of the substrate, the photoelectric conversion unit having a photoelectric conversion function for received light, a photoelectric charge transfer function, and a charge accumulation function; a transfer transistor capable of transferring charges accumulated in the photoelectric conversion unit; a transfer assist gate formed adjacent to the transfer gate of the transfer transistor on the second substrate surface side of the substrate, the transfer assist gate being capable of controlling photocharge transfer and accumulation processing within the photoelectric conversion unit; a floating diffusion to which the charges accumulated in the photoelectric conversion unit are transferred through the transfer transistor; and The photoelectric conversion unit is a first region having a first depth from the second substrate surface toward the first substrate surface in a direction perpendicular to the substrate surface; a second region having a second depth greater than the first depth; The transfer assist gate is The charge transfer and accumulation process between the second region and the first region in the photoelectric conversion unit can be controlled. A method for driving a solid-state imaging device, comprising: an exposure mode and a readout mode as operation modes, and controls the on / off states of the transfer assist gate and the transfer transistor according to the operation mode to read out pixel signals from the pixels of the pixel unit; When reading out the pixel signals, When operating in the exposure mode, the transfer assist gate is controlled to be in an off state; When operating in the read mode, the transfer assist gate is controlled to be in an on state when charges are transferred from the second region to the first region of the photoelectric conversion unit and stored therein. A method for driving a solid-state imaging device.

12. a solid-state imaging device; an optical system that forms a subject image on the solid-state imaging device, a pixel section in which pixels that perform photoelectric conversion are arranged; The pixel is a substrate having a first substrate surface side and a second substrate surface side opposite to the first substrate surface side; a photoelectric conversion unit formed so as to be embedded between the first substrate surface side and the second substrate surface side of the substrate, the photoelectric conversion unit having a photoelectric conversion function for received light, a photoelectric charge transfer function, and a charge accumulation function; a transfer transistor capable of transferring charges accumulated in the photoelectric conversion unit; a transfer assist gate formed adjacent to the transfer gate of the transfer transistor on the second substrate surface side of the substrate, the transfer assist gate being capable of controlling photocharge transfer and accumulation processing within the photoelectric conversion unit; a floating diffusion to which the charges accumulated in the photoelectric conversion unit are transferred through the transfer transistor; and The photoelectric conversion unit is a first region having a first depth from the second substrate surface toward the first substrate surface in a direction perpendicular to the substrate surface; a second region having a second depth greater than the first depth; The transfer assist gate is The charge transfer and accumulation process between the second region and the first region in the photoelectric conversion unit can be controlled. electronic equipment.

Images