Light-emitting component, light-emitting device, and measuring device

Abstract

To restrain erroneous lighting as compared with a case where the same voltage is applied to an anode layer and a gate layer of a thyristor in which the anode layer, the gate layer, and a cathode layer are stacked.SOLUTION: A light emitting device includes a substrate, a plurality of light emitting elements provided on the substrate, and a plurality of thyristors that, when turned on, cause each of the plurality of light emitting elements to emit light or increase the amount of light to be emitted by each of the plurality of light emitting elements, the thyristor having an anode layer, a gate layer, and a cathode layer stacked thereon, and receiving a potential such that a first potential supplied to the gate layer is higher than a second potential supplied to the anode layer.SELECTED DRAWING: Figure 3

Description

[Technical Field]

[0001] The present invention relates to a light emitting component, a light emitting device, and a measuring device. [Background technology]

[0002] Patent document 1 describes a light-emitting device having a semiconductor substrate, a light-emitting element section formed on the semiconductor substrate and having a plurality of light-emitting elements that emit light, a signal line formed on the semiconductor substrate and that transmits a signal to the light-emitting element, and an oxide film formed along the signal line between the signal line and the semiconductor substrate. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] Japanese Patent Publication No. 2023-42123 Summary of the Invention [Problem to be solved by the invention]

[0004] A light-emitting component has multiple blocks, each having one or more light-emitting elements, and one or more thyristors that, when turned on, cause the respective light-emitting elements to emit light or increase the amount of light emitted by the light-emitting elements. In such a component, when a first block is turned on and then turned off and a second block is turned on, the first block may erroneously light up due to remaining charge in the thyristor of the first block. An object of the present invention is to suppress erroneous lighting compared to when the same voltage is applied to the anode layer and gate layer of a thyristor in which an anode layer, a gate layer, and a cathode layer are stacked. [Means for solving the problem]

[0005] The invention described in claim 1 is a light-emitting component comprising a substrate, a plurality of light-emitting elements provided on the substrate, and a plurality of thyristors that, when turned on, cause each of the plurality of light-emitting elements to emit light or increase the amount of light emitted by each of the plurality of light-emitting elements, the thyristors having an anode layer, a gate layer, and a cathode layer stacked thereon, and that receive a potential such that a first potential supplied to the gate layer is higher than a second potential supplied to the anode layer. The invention described in claim 2 is a light-emitting component described in claim 1, in which, when the thyristor is turned off, a potential is supplied such that the first potential supplied to the gate layer is higher than the second potential supplied to the anode layer, thereby creating a reverse bias state between the anode layer and the gate layer of the thyristor. The invention described in claim 3 is a light-emitting device comprising: a substrate; a plurality of light-emitting elements provided on the substrate; a plurality of thyristors that, when turned on, cause each of the plurality of light-emitting elements to emit light or increase the amount of light emitted by each of the plurality of light-emitting elements, the thyristors having an anode layer, a gate layer, and a cathode layer stacked thereon, and that receive a potential such that a first potential supplied to the gate layer is higher than a second potential supplied to the anode layer; and a drive unit provided on the substrate that drives the thyristors individually to transition them to an on state, the drive unit receiving the second potential supplied to the gate layer of the thyristors. The invention described in claim 4 is a measuring device comprising: a substrate; a plurality of light-emitting elements provided on the substrate; a plurality of thyristors that, when turned on, cause each of the plurality of light-emitting elements to emit light or increase the amount of light emitted by each of the plurality of light-emitting elements, the thyristors having an anode layer, a gate layer, and a cathode layer stacked thereon, and that receive a potential such that a first potential supplied to the gate layer is higher than a second potential supplied to the anode layer; a drive unit provided on the substrate that individually drives the thyristors to cause each of the light-emitting elements to emit light at a predetermined timing, the drive unit receiving the second potential supplied to the gate layer of the thyristor; and an acquisition unit that acquires information about an object based on light reflected from the object by light from each light-emitting region. [Effects of the Invention]

[0006] According to the inventions of claims 1, 3 and 4, it is possible to suppress erroneous lighting compared to when the same voltage is applied to the anode layer and gate layer of a thyristor in which an anode layer, a gate layer and a cathode layer are stacked. According to the invention of claim 2, the charge remaining inside the thyristor can be quickly released. [Brief explanation of the drawings]

[0007] [Figure 1] FIG. 1 is a diagram illustrating an example of a measurement device to which the present embodiment is applied. [Figure 2] 1 is a diagram illustrating a light source device to which the present embodiment is applied. [Figure 3] 1(a) and 1(b) are an example of a planar layout diagram and a cross-sectional view of a light-emitting chip to which the present embodiment is applied. [Figure 4] 1 is an example of an enlarged cross-sectional view of an island in which a VCSEL and a setting thyristor are stacked. [Figure 5] FIG. 10 is a diagram showing a path through which the charge remaining inside the setting thyristor escapes to the outside of the setting thyristor. DETAILED DESCRIPTION OF THE INVENTION

[0008] Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings. Here, a case will be described in which the light source device 1 including the light-emitting chip 10 is applied to a measurement device that measures the three-dimensional shape (hereinafter referred to as 3D shape) of an object to be measured, as an example. The light-emitting chip 10 is an example of a light-emitting component, and the light source device 1 is an example of a light-emitting device.

[0009] [Embodiment 1] (Measuring device 100) FIG. 1 is a diagram showing an example of a measurement device 100 to which this embodiment is applied. The measuring device 100 of this embodiment measures the three-dimensional shape of an object to be measured. The measuring device 100 is a device that measures the 3D shape based on the so-called ToF (Time of Flight) method, which uses the time of flight of light. The measuring device 100 includes a light source device 1 as an example of a light-emitting device including a light-emitting chip 10 and a control unit 110, and a three-dimensional sensor (hereinafter referred to as a 3D sensor) 5. The ToF method measures the time from when light is emitted from the light source device 1 to when the light is reflected by the object to be measured and received by the 3D sensor 5. The distance to the object to be measured is then calculated from the time acquired by the 3D sensor 5, and the 3D shape of the object to be measured is identified. Measuring a 3D shape may also be referred to as three-dimensional measurement, 3D measurement, or 3D sensing.

[0010] The light source device 1 emits light toward the object to be measured. The 3D sensor 5 acquires the light (reflected light) that is reflected by the object to be measured. The 3D sensor 5 outputs information (distance information) regarding the distance to the object to be measured based on the time from when the light is emitted to when the reflected light is received, measured using the ToF method. The measurement device 100 may also include a measurement control unit 200. The measurement control unit 200 is configured as a computer including a CPU, ROM, RAM, etc., and identifies the 3D shape of the object to be measured based on the distance information acquired from the 3D sensor 5.

[0011] Furthermore, the measurement device 100 can be applied to recognizing a measurement object from the identified 3D shape. For example, the measurement device 100 is installed in a portable information processing device and used to recognize the face of a user attempting to access the device. That is, the measurement device 100 acquires the 3D shape of the face of the accessing user, identifies whether or not the access is permitted, and permits use of the device (portable information processing device) only if it is recognized that the user is authorized to access the device. The measuring device 100 can also be applied to cases where the 3D shape of an object to be measured is continuously measured, such as in augmented reality (AR).

[0012] (Light source device 1) 2 is a diagram illustrating a light source device 1 to which this embodiment is applied. In FIG. 2, the right direction on the paper surface is the +x direction. Note that in the light source device 1 shown in FIG. 2, the positions of the terminals (φ1 terminal, φ2 terminal, Vga terminal, φI terminal) are not necessarily accurate. The light source device 1 shown in FIG.

[0013] (control unit 110) The control unit 110 includes a transfer signal generating unit 120 , a lighting signal generating unit 140 , a reference potential supplying unit 160 , and a power supply potential supplying unit 170 . The transfer signal generating unit 120 generates transfer signals φ1 and φ2 that sequentially transfer an ON state to a plurality of transfer thyristors T (described later). The light-up signal generating unit 140 generates a light-up signal φI that supplies a current that lights up (emits light) a plurality of VCSELs (described later). The reference potential supplying unit 160 supplies a reference potential Vsub. The power supply potential supplying unit 170 supplies a power supply potential Vga.

[0014] (Light emitting chip 10) The light-emitting chip 10 includes a light-emitting unit 11 and a transfer unit 12. The light-emitting chip 10 also includes a φ1 terminal, a φ2 terminal, a Vga terminal, a φI terminal, and a Vsub terminal. The light-emitting unit 11 includes a vertical cavity surface-emitting laser (VCSEL). Hereinafter, the vertical cavity surface-emitting laser (VCSEL) will be referred to as VCSEL. In the example shown in FIG. 2, six VCSELs, VCSEL1 to VCSEL6, will be referred to as VCSELs when no distinction is made. The light-emitting unit 11 also includes six setting thyristors S1 to S6 (when no distinction is made, will be referred to as setting thyristor S). The anodes of the VCSELs and the cathodes of the setting thyristors S are connected. In other words, the setting thyristors S and VCSELs with the same number are connected in series. Additionally, as shown in FIG. 3, which will be described later, the setting thyristors S are stacked on the VCSELs formed on the substrate 80. Hereinafter, the setting thyristors S may be referred to as thyristors. In this embodiment, each VCSEL is an example of a light-emitting element, and each setting thyristor S is an example of a thyristor.

[0015] The transfer unit 12 includes six transfer thyristors T1 to T6 (referred to as transfer thyristors T when not distinguished), and six lower diodes UD1 to UD6 (referred to as lower diodes UD when not distinguished). The transfer thyristors T1 to T6 and the lower diodes UD1 to UD6 are connected in series with the transfer thyristor T and lower diode UD of the same number. Additionally, as shown in FIG. 3(b) to be described later, the transfer thyristor T is stacked on the lower diode UD formed on the substrate 80.

[0016] The transfer unit 12 also pairs the transfer thyristors T1 to T6 in numerical order, and includes coupling diodes D1 to D5 (referred to as coupling diode D when no distinction is needed) between each pair. Furthermore, the transfer unit 12 includes power supply line resistors Rg1 to Rg6 (power supply line resistor Rg when no distinction is made).

[0017] The transfer unit 12 also includes one start diode SD. Furthermore, the transfer unit 12 includes current limiting resistors R1 and R2 that are provided to prevent excessive current from flowing through a first transfer signal line 72 to which a first transfer signal φ1 (described later) is supplied and a second transfer signal line 73 to which a transfer signal φ2 (described later) is supplied.

[0018] The VCSEL1 to VCSEL6 and setting thyristors S1 to S6 of the light-emitting unit 11, the transfer thyristors T1 to T6 of the transfer unit 12, the lower diodes UD1 to UD6, the coupling diodes D1 to D5, and the power line resistors Rg1 to Rg6 are arranged in numerical order in the light-emitting chip 10 from one side (-x direction side, left side in Figure 2) to the other side (+x direction side, right side in Figure 2).

[0019] In this embodiment, the number of VCSELs and setting thyristors S in the light-emitting unit 11, and the number of transfer thyristors T, lower diodes UD, and power line resistances Rg in the transfer unit 12 are six each. The number of coupling diodes D is five, which is one less than the number of transfer thyristors T. The numbers of VCSELs, setting thyristors S, transfer thyristors T, lower diodes UD, power line resistances Rg, and coupling diodes D are not limited to the above and may be any predetermined number. The number of transfer thyristors T may also be greater than the number of VCSELs.

[0020] The above-mentioned VCSEL, lower diode UD, coupling diode D, and start diode SD are two-terminal semiconductor elements having an anode terminal (anode) and a cathode terminal (cathode). Also, the thyristors (setting thyristor S, transfer thyristor T) are three-terminal semiconductor elements having an anode terminal (anode), a gate terminal (gate), and a cathode terminal (cathode). Note that, below, terminals may be abbreviated and written in parentheses.

[0021] In the light-emitting chip 10 of this embodiment, the VCSEL, setting thyristor S, lower diode UD, transfer thyristor T, coupling diode D, power line resistance Rg, and start diode SD are configured as an integrated circuit using a semiconductor laminate epitaxially grown on a common semiconductor substrate (hereinafter referred to as substrate 80). Here, the semiconductor laminate is configured using, for example, a III-V group compound semiconductor such as GaAs, AlGaAs, or AlAs.

[0022] Next, the electrical connections of the elements in the light-emitting chip 10 will be described. The cathodes of the VCSEL and the lower diode UD are connected to the substrate 80 (common cathode). These cathodes are supplied with a reference potential Vsub via a back electrode 91 (see FIG. 3) which is a Vsub terminal provided on the back surface of the substrate 80. The anodes of the VCSELs are connected to the cathodes of the setting thyristors S. The anodes of the lower diodes UD are connected to the cathodes of the transfer thyristors T. This connection is a configuration when an n-type substrate 80 is used, and the polarity is reversed when a p-type substrate is used.

[0023] Along the arrangement of the transfer thyristors T, the anodes of the odd-numbered transfer thyristors T1, T3, and T5 are connected to a first transfer signal line 72. The first transfer signal line 72 is connected to a φ1 terminal via a current-limiting resistor R1. A transfer signal φ1 is supplied to this φ1 terminal from the transfer signal generating unit 120 of the control unit 110. Meanwhile, along the arrangement of the transfer thyristors T, the anodes of the even-numbered transfer thyristors T2, T4, and T6 are connected to a second transfer signal line 73. The second transfer signal line 73 is connected to a φ2 terminal via a current-limiting resistor R2. A transfer signal φ2 is supplied to this φ2 terminal from the transfer signal generating unit 120 of the control unit 110.

[0024] The anodes of the setting thyristors S are connected to a light-up signal line 75. The light-up signal line 75 is connected to a φI terminal. In the light-emitting chip 10, a light-up signal φI is supplied to the φI terminal from the light-up signal generating unit 140 of the control unit 110 via a current-limiting resistor RI provided outside the light-emitting chip 10. The light-up signal φI supplies a current for lighting the VCSEL.

[0025] The gates Gt1 to Gt6 (written as gate Gt when not distinguished) of the transfer thyristors T1 to T6 are connected one-to-one to the gates Gs1 to Gs6 (written as gate Gs when not distinguished) of the setting thyristors S1 to S6 having the same numbers. Therefore, the gates Gt1 to Gt6 and the gates Gs1 to Gs6 having the same numbers are electrically at the same potential. Therefore, for example, the gate is written as gate Gt1 (gate Gs1) to indicate that the potential is the same.

[0026] Coupling diodes D1 to D5 are connected between pairs of gates Gt1 to Gt6 of the transfer thyristors T1 to T6 in numerical order. That is, the coupling diodes D1 to D5 are directly connected so that they are sandwiched between the gates Gt1 to Gt6. The coupling diode D1 is connected in the direction in which current flows from the gate Gt1 to the gate Gt2. The same applies to the other coupling diodes D2 to D5.

[0027] The gates Gt (gates Gs) of the transfer thyristors T are connected to a power supply line 71 via power supply line resistors Rg provided corresponding to the respective transfer thyristors T. The power supply line 71 is connected to a Vga terminal. A power supply potential Vga is supplied to the Vga terminal from a power supply potential supply unit 170 of the control unit 110.

[0028] The gate Gt1 of the transfer thyristor T is connected to the cathode of the start diode SD. On the other hand, the anode of the start diode SD is connected to the second transfer signal line 73.

[0029] 3(a) and 3(b) are an example of a planar layout diagram and a cross-sectional view of the light-emitting chip 10 to which this embodiment is applied. Fig. 3(a) is an example of a planar layout diagram of the light-emitting chip 10, and Fig. 3(b) is an example of a cross-sectional view taken along line IIIB-IIIB in Fig. 3(a). 3(a) and 3(b), a protective layer (protective layer 90 in FIG. 4) and a light-shielding layer (light-shielding layer 95 in FIG. 4) are omitted. Also, in FIG. 3(b), the connection wirings shown in FIG. 3(a) are omitted.

[0030] First, the cross-sectional structure of the light-emitting chip 10 will be described with reference to FIG. The light emitting chip 10 includes an n-type cathode layer 81, a light emitting layer 82, and a p-type anode layer 83, which are sequentially provided on an n-type substrate 80 (substrate 80) and constitute the VCSEL and the lower diode UD. In the light emitting chip 10 of this embodiment, the n-type cathode layer 81 and the p-type anode layer 83 are configured by a distributed Bragg reflector (DBR) (hereinafter referred to as a DBR layer) in which multiple semiconductor layers having refractive index differences are stacked. Therefore, hereinafter, the n-type cathode layer 81 will be referred to as an n-cathode (DBR) layer 81. Similarly, the p-type anode layer 83 will be referred to as a p-anode (DBR) layer 83.

[0031] In the light emitting chip 10, a tunnel junction (tunnel diode) layer 84 (tunnel junction layer 84) is provided on the p anode (DBR) layer 83. Furthermore, the light-emitting chip 10 has an n-type cathode layer 85 (n-cathode layer 85), a p-type gate layer 86 (p-gate layer 86), an n-type gate layer 87 (n-gate layer 87), and a p-type anode layer 88 (p-anode layer 88) formed in this order on the tunnel junction layer 84, which constitute the setting thyristor S, the transfer thyristor T, the coupling diode D, and the power line resistance Rg. In the following, the notation in parentheses will be used. The same applies to other cases.

[0032] Elements such as the VCSEL, lower diode UD, setting thyristor S, transfer thyristor T, and coupling diode D are composed of multiple islands separated by removing portions of each of the above layers through etching. Note that an island is sometimes referred to as a mesa, and the etching that forms the island (mesa) is sometimes referred to as mesa etching. In the light-emitting chip 10, these islands are connected to wiring such as a power supply line 71, a first transfer signal line 72, a second transfer signal line 73, and a light-up signal line 75 via through-holes (indicated by circles in FIG. 3(a)) provided in a protective layer (a protective layer 90 in FIG. 4, which will be described later). In the following explanation, a description of the protective layer and the through-holes will be omitted.

[0033] As shown in FIG. 3(b), a back surface electrode 91 that serves as a Vsub terminal is provided on the back surface of the substrate 80.

[0034] Here, the notation of the n-cathode (DBR) layer 81 and the p-anode (DBR) layer 83 corresponds to their functions when configuring the VCSEL and the lower diode UD. That is, the n-cathode (DBR) layer 81 functions as a cathode, and the p-anode (DBR) layer 83 functions as an anode. The notations of the n-cathode layer 85, p-gate layer 86, n-gate layer 87, and p-anode layer 88 correspond to the functions (operations) when configuring the setting thyristor S and the transfer thyristor T. That is, the n-cathode layer 85 functions as a cathode, the p-gate layer 86 and n-gate layer 87 function as gates, and the p-anode layer 88 functions as an anode. When the above layers constitute the coupling diode D and the power supply line resistance Rg, they have different functions as will be described later.

[0035] As will be described below, the multiple islands included in the light-emitting chip 10 include those that do not include some of the n-cathode (DBR) layer 81, the light-emitting layer 82, the p-anode (DBR) layer 83, the tunnel junction layer 84, the n-cathode layer 85, the p-gate layer 86, the n-gate layer 87, and the p-anode layer 88. For example, islands 301 and 302, which will be described later, do not include part of the p-anode layer 88.

[0036] Next, an example of a planar layout of the light-emitting chip 10 will be described with reference to FIG. The island 301 is provided with a VCSEL1 and a setting thyristor S1. The island 302 is provided with a lower diode UD1, a transfer thyristor T1, and a coupling diode D1. The island 303 is provided with a power line resistor Rg1. The island 304 is provided with a start diode SD. The island 305 is provided with a current limiting resistor R1, and the island 306 is provided with a current limiting resistor R2. The light-emitting chip 10 has a plurality of islands formed in parallel, each of which is similar to the islands 301, 302, and 303. These islands are provided with VCSEL2 to VCSEL6, setting thyristors S2 to S6, lower diodes UD2 to UD6, transfer thyristors T2 to T6, coupling diodes D2 to D5, and the like, similar to the islands 301, 302, and 303.

[0037] Here, the islands 301 to 306 will be described in detail with reference to FIGS. 3(a) and 3(b). 3(b), the VCSEL1 provided on the island 301 is composed of an n-cathode (DBR) layer 81, a light-emitting layer 82, and a p-anode (DBR) layer 83. The setting thyristor S is composed of an n-cathode layer 85, a p-gate layer 86, an n-gate layer 87, and a p-anode layer 88 stacked via a tunnel junction layer 84 stacked on the p-anode (DBR) layer 83 of the VCSEL1.

[0038] As shown in FIG. 3(b), the p-anode (DBR) layer 83 of the VCSEL includes a current confinement layer (current confinement layer 83a in FIG. 4, which will be described later) that confines the current, as indicated by the black dots in FIG. 3(b). The current confinement layer is formed by oxidizing a portion of the semiconductor layer that constitutes the n-cathode (DBR) layer, exposed by mesa etching, from the periphery. This forms a current blocking portion β, through which current does not easily flow. Meanwhile, the central portion, where the portion of the semiconductor layer that constitutes the n-cathode (DBR) layer is not oxidized, forms a current passing portion α, through which current easily flows. As shown in FIG. 4, the inside of the current confinement layer 83a is the current passing portion α, and the portion where the current confinement layer 83a is located is the current blocking portion β. Note that the current blocking portion β does not need to completely block the current flow; it is sufficient if it can concentrate the current in the current passing portion α. In other words, it is sufficient if the current blocking portion β is more difficult for current to flow than the current passing portion α. By providing the current blocking portion β, the power consumed by non-radiative recombination is reduced. By providing the current blocking portion β, it is possible to reduce power consumption and improve the light extraction efficiency. The light extraction efficiency is the amount of light that can be extracted per unit of power.

[0039] In the setting thyristor S1, a p-type ohmic electrode 321 (p ohmic electrode 321) provided on the region 311 of the p anode layer 88 serves as an anode terminal. Also, an n-type ohmic electrode 331 (n ohmic electrode 331) provided on the n gate layer 87 exposed by removing the p anode layer 88 serves as a terminal of the gate Gs1.

[0040] The lower diode UD1 provided in the island 302, like the VCSEL, is composed of an n-cathode (DBR) layer 81, a light-emitting layer 82, and a p-anode (DBR) layer 83. Like the setting thyristor S1, the transfer thyristor T1 is composed of an n-cathode layer 85, a p-gate layer 86, an n-gate layer 87, and a p-anode layer 88, which are stacked via a tunnel junction layer 84 stacked on the p-anode (DBR) layer 83 of the lower diode UD1. A p-ohmic electrode 323 provided on region 313 of p-anode layer 88 serves as an anode terminal. Furthermore, an n-ohmic electrode 332 provided on n-gate layer 87 exposed by removing p-anode layer 88 serves as a terminal of gate Gt1. Similarly, coupling diode D1 provided in island 302 is composed of an n-gate layer 87 and a p-anode layer 88. A p-ohmic electrode 324 provided on region 314 of p-anode layer 88 serves as the anode terminal. Furthermore, an n-ohmic electrode 332 provided on n-gate layer 87 exposed by removing p-anode layer 88 serves as the cathode terminal. Here, the cathode terminal of coupling diode D is the same as gate Gt1.

[0041] The power supply line resistance Rg1 provided in the island 303 is composed of the p anode layer 88. That is, the power supply line resistance Rg1 is provided with the p anode layer 88 between the p ohmic electrode 333 and the p ohmic electrode 334 provided on the p anode layer 88 as a resistor.

[0042] The start diode SD provided in the island 304 is composed of an n-gate layer 87 and a p-anode layer 88. That is, the start diode SD has an anode terminal in the form of a p-ohmic electrode 325 provided on a region 315 of the p-anode layer 88. Furthermore, the start diode SD has a cathode terminal in the form of an n-ohmic electrode 335 provided on the n-gate layer 87 exposed by removing the p-anode layer 88. The current limiting resistor R1 provided in island 305 and the current limiting resistor R2 provided in island 306 are provided in the same manner as the power line resistor Rg1 provided in island 303, and each uses the p anode layer 88 between two p ohmic electrodes (unnumbered) as a resistor.

[0043] Next, the connection relationships between the elements will be explained with reference to FIG. The light-on signal line 75 has a trunk 75a and multiple branch portions 75b. The trunk 75a is provided so as to extend in the column direction of the setting thyristors S / VCSEL. The branch portions 75b branch off from the trunk 75a and are connected to the p-ohmic electrode 321, which is the anode terminal of the setting thyristor S1 provided on the island 301. The anode terminals of the other setting thyristors S are connected in the same manner. The light-on signal line 75 is connected to the φI terminal provided on the setting thyristor S1 / VCSEL1 side.

[0044] The first transfer signal line 72 is connected to the p-ohmic electrode 323, which is the anode terminal of the transfer thyristor T1 provided in the island 302. The first transfer signal line 72 is connected to the anode terminals of other odd-numbered transfer thyristors T provided in islands similar to the island 302. The first transfer signal line 72 is connected to the φ1 terminal via a current limiting resistor R1 provided in the island 305. On the other hand, the second transfer signal line 73 is connected to a p-ohmic electrode (without reference numeral) which is the anode terminal of the even-numbered transfer thyristor T provided in the island without reference numeral. The second transfer signal line 73 is connected to the φ2 terminal via a current limiting resistor R2 provided in the island 306.

[0045] The power supply line 71 is connected to a p-ohmic electrode 334, which is one terminal of a power supply line resistor Rg1 provided on the island 303. One terminal of another power supply line resistor Rg is also connected to the power supply line 71. The power supply line 71 is connected to the Vga terminal.

[0046] The n-ohmic electrode 331 (gate terminal Gs1) of the setting thyristor S1 provided on the island 301 is connected to the n-ohmic electrode 332 (gate terminal Gt1) of the island 302 by a connection wire .

[0047] The n-ohmic electrode 332 (gate terminal Gt1) is connected to the p-ohmic electrode 333 (the other terminal of the power supply line resistance Rg1) of the island 303 by a connection wire 77. A p-ohmic electrode 324 (anode terminal of the coupling diode D1) provided on the island 302 is connected by a connection wiring 79 to an n-ohmic electrode (no reference numeral) which is the gate terminal Gt2 of the adjacent transfer thyristor T2. Although the explanation is omitted here, the same applies to other VCSELs, setting thyristors S, transfer thyristors T, coupling diodes D, etc.

[0048] The n-ohmic electrode 332 (gate terminal Gt1) of the island 302 is connected to the p-ohmic electrode 325 (cathode terminal of the start diode SD) provided on the island 304 by a connection wiring 78. The n-ohmic electrode 335 (cathode terminal of the start diode SD) is connected to a second transfer signal line 73. The above connections and configurations are for when an n-type substrate 80 is used, and when a p-type substrate is used, the polarity is reversed.

[0049] (Stacked structure of setting thyristor S and VCSEL) FIG. 4 is an example of an enlarged cross-sectional view of an island in which a setting thyristor S and a VCSEL are stacked, and is a cross-sectional view of the light-emitting chip 10 taken along line IV-IV in FIG. 3(a). FIG. 4 corresponds to a cross-sectional view of the island in which a setting thyristor S and a VCSEL are stacked, viewed from the -y direction. FIG. 4 also shows an island 301 in which a VCSEL1 and a setting thyristor S1 are stacked, and an island (without reference numerals) in which a VCSEL2 and a setting thyristor S2 are stacked. In FIG. 4, VCSEL1 and VCSEL2 are not distinguished from each other and are referred to as VCSEL. Similarly, the setting thyristor S1 and the setting thyristor S2 are not distinguished from each other and are referred to as setting thyristor S. As described above, the setting thyristor S is stacked on the VCSEL via the tunnel junction layer 84. That is, the setting thyristor S and the VCSEL are connected in series. Note that "on the VCSEL" does not only refer to a state in which the VCSEL is in direct contact with the VCSEL, but also includes a state in which the VCSEL is positioned above the VCSEL without being in direct contact with the VCSEL. The same applies to similar expressions such as "on the substrate."

[0050] As shown in FIG. 4, the VCSEL is composed of a semiconductor laminate in which an n-cathode (DBR) layer 81, a light-emitting layer 82, and a p-anode (DBR) layer 83 are epitaxially grown in this order on an n-type substrate 80. The n-cathode (DBR) layer 81 and the p-anode (DBR) layer 83 are DBR layers formed by alternately stacking multiple high-refractive-index layers and low-refractive-index layers, and are configured to reflect light emitted from the VCSEL.

[0051] The p anode (DBR) layer 83 also includes a current confinement layer 83a. In this example, the current confinement layer 83a is provided on the side of the p anode (DBR) layer 83 that faces the light emitting layer 82. The current confinement layer 83a is composed of a current passing portion α and a current blocking portion β. As shown in FIG. 4, the current passing portion α is provided in the center of the VCSEL, and the current blocking portion β is provided in the peripheral portion of the VCSEL. In other words, the portion of the current confinement layer 83a is the current blocking portion β, and the portion without the current confinement layer 83a is the current passing portion α. The current confinement layer 83a may be provided in the n-cathode (DBR) layer 81.

[0052] The light-emitting layer 82 has a quantum well structure in which well layers and barrier layers are alternately stacked. The light-emitting layer 82 may be an intrinsic (i) type layer (i layer) to which no impurities are added. The light-emitting layer 82 may also have a structure other than a quantum well structure, such as a quantum wire or a quantum dot.

[0053] The tunnel junction layer 84 is an n-type layer doped with a high concentration of n-type impurities (dopants). ++ layer and p-type impurity-doped p ++The tunnel junction layer 84 is a junction between the p-anode (DBR) layer 83 of the VCSEL and the setting thyristor S, and current flows due to the tunnel effect even when reverse bias is applied. The tunnel junction layer 84 prevents the p-anode (DBR) layer 83 of the VCSEL and the setting thyristor S from becoming reverse biased and making it difficult for current to flow. Current flows due to the tunnel effect even when reverse bias is applied.

[0054] The setting thyristor S is composed of an n-cathode layer 85, a p-gate layer 86, an n-gate layer 87, and a p-anode layer 88, which are stacked on a tunnel junction layer 84. That is, it has a four-layer pnpn structure.

[0055] These semiconductor layers are stacked by, for example, metal organic chemical vapor deposition (MOCVD), molecular beam epitaxy (MBE), or the like to form a semiconductor stack. The structures of the substrate 80, the n-cathode (DBR) layer 81, the light-emitting layer 82, and the p-anode (DBR) layer 83 that constitute the VCSEL, and the n-cathode layer 85, the p-gate layer 86, the n-gate layer 87, and the p-anode layer 88 that constitute the setting thyristor S will be described in more detail later.

[0056] The p ohmic electrode 321 is made of Au containing Zn (AuZn), which can easily make ohmic contact with a p-type semiconductor layer such as the p anode layer 88, for example. The n-ohmic electrode 331 (see FIG. 3(b)) is made of Au containing Ge (AuGe), which can easily make ohmic contact with an n-type semiconductor layer such as the n-gate layer 87, for example. The rear electrode 91 is made of, for example, AuGe, similar to the n-ohmic electrode 331 .

[0057] In the above, the n-ohmic electrode 331 is provided on the n-gate layer 87 to serve as the gate Gs of the setting thyristor S, but the p-ohmic electrode may be provided on the p-gate layer 86 to serve as the gate Gs of the setting thyristor S.

[0058] Furthermore, a protective layer 90 made of a light-transmitting insulating material is provided so as to cover the surface and side surfaces of the island on the light-emitting chip 10. The protective layer 90 is made of, for example, SiO2, SiON, SiN, or the like. Furthermore, the light-emitting chip 10 is provided with a light-shielding layer 95 for preventing light emitted from the setting thyristor S from leaking out from between the islands onto the surface of the light-emitting chip 10. The light-shielding layer 95 may be the above-mentioned wiring.

[0059] (Relationship between adjacent setting thyristors S and between VCSELs) As described above, in the light-emitting chip 10 of this embodiment, each island is formed by removing a portion of the semiconductor layers stacked on the substrate 80 in the thickness direction by mesa etching. For example, in the island (island 301) in which the setting thyristor S and the VCSEL are stacked, of the semiconductor layers stacked on the substrate 80, from the top, the p-anode layer 88, the n-gate layer 87, the p-gate layer 86, the n-cathode layer 85, the tunnel junction layer 84, the p-anode (DBR) layer 83, and the light-emitting layer 82 are removed, and also a portion of the n-cathode (DBR) layer 81 is removed. As a result, each setting thyristor S is composed of an n-cathode layer 85, p-gate layer 86, n-gate layer 87, and p-anode layer 88 that are separated from the adjacent setting thyristors S. In other words, the n-cathode layer 85, p-gate layer 86, n-gate layer 87, and p-anode layer 88 that constitute each setting thyristor S are not continuous with the adjacent setting thyristors S.

[0060] On the other hand, in the VCSEL of this embodiment, at least a portion of the semiconductor layer constituting the VCSEL (e.g., VCSEL1) corresponding to one thyristor S (e.g., thyristor S1) among the multiple thyristors S is continuous with a semiconductor layer constituting the VCSEL (e.g., VCSEL2) corresponding to another adjacent thyristor S (e.g., thyristor S2). Specifically, in the VCSEL of this embodiment, the n-cathode (DBR) layer 81, which is the lowest layer, is partially continuous between adjacent VCSELs. Note that in the VCSEL, the light-emitting layer 82 and p-anode (DBR) layer 83 stacked on the n-cathode (DBR) layer 81 are not continuous with the adjacent VCSEL. In addition, the VCSEL of this embodiment includes an n-cathode (DBR) layer 81 that is stacked on a substrate 80 and is continuous across adjacent VCSEL1 and VCSEL2. Furthermore, the VCSEL of this embodiment includes a p-anode (DBR) layer 83 that is separated between adjacent VCSEL1 and VCSEL2.

[0061] (thyristor) Next, the basic operation of the thyristors (transfer thyristor T, setting thyristor S) will be described. As described above, a thyristor is a semiconductor element having three terminals: an anode terminal (anode), a cathode terminal (cathode), and a gate terminal (gate), and is configured by stacking p-type semiconductor layers (p-gate layer 86, p-anode layer 88) and n-type semiconductor layers (n-cathode layer 85, n-gate layer 87) made of GaAs, AlGaAs, AlAs, or the like on a substrate 80. In other words, the thyristor has a pnpn structure. Here, the forward potential (diffusion potential) Vd of the pn junction formed by the p-type semiconductor layer and the n-type semiconductor layer will be described as 1.5 V, as an example.

[0062] In the following description, as an example, the reference potential Vsub supplied to the rear electrode 91 (see FIG. 3) serving as the Vsub terminal is described as a low-level potential (hereinafter referred to as "L"), 0V, and the power supply potential Vga supplied to the Vga terminal is described as a high-level potential (hereinafter referred to as "H"), 5V. Therefore, the potentials may be described as "H" (5V) and "L" (0V).

[0063] First, we will explain the operation of a single thyristor. Here, we assume that the cathode of the thyristor is 0V. A thyristor in the off state, where no current flows between the anode and cathode, transitions to the on state (turns on) when a potential lower than the threshold voltage (a negative potential with a large absolute value) is applied to the anode. Here, the threshold voltage of a thyristor is the gate potential minus the forward potential Vd (1.5V) of the pn junction. When the thyristor is turned on, the gate of the thyristor has a potential close to the potential of the cathode terminal. Here, the cathode is 0V, so the gate is assumed to be 0V. Also, the anode of the thyristor in the on state has a potential close to the potential of the cathode plus the forward potential Vd (1.5V) of the pn junction. Here, since the cathode is 0V, the anode of the thyristor in the on state has a potential close to 1.5V (a positive potential with an absolute value greater than 1.5V). The anode potential is set in relation to the power supply that supplies current to the thyristor in the on state.

[0064] A thyristor in the ON state transitions to the OFF state (turns off) when the anode reaches a potential (a positive potential with a small absolute value, 0 V, or a negative potential) lower than the potential required to maintain the ON state (a potential close to the above 1.5 V). On the other hand, if a potential higher than the potential required to maintain the on state (a positive potential with a large absolute value) is continuously applied to the anode of a thyristor in the on state and a current sufficient to maintain the on state (maintenance current) is supplied, the thyristor will maintain the on state.

[0065] Next, the operation when the setting thyristor S and the VCSEL are stacked will be described. The setting thyristor S is stacked with the VCSEL and connected in series. Therefore, the potential of the light-up signal φI is divided between the setting thyristor S and the VCSEL. Here, the explanation will be given assuming that the voltage applied to the VCSEL is 1.7 V. Then, when the setting thyristor S is in the off state, 3.3 V is applied to the setting thyristor S. As described above, when the threshold voltage of the setting thyristor S in the OFF state is lower than 3.3 V, the potential applied to the anode of the setting thyristor S is higher than the threshold voltage, so the setting thyristor S turns on. This causes current to flow through the series-connected setting thyristor S and the VCSEL, causing the VCSEL to emit light. On the other hand, when the threshold voltage of the setting thyristor S is higher than 3.3 V, the setting thyristor S does not turn on and remains in the OFF state. When the setting thyristor S turns on, the absolute value of the voltage applied to the series-connected setting thyristor S and VCSEL decreases due to the current-limiting resistor RI (see Figure 3). However, if the voltage applied to the setting thyristor S is a voltage that maintains the setting thyristor S in the on state, the setting thyristor S will maintain the on state. This allows the VCSEL to continue emitting light.

[0066] The voltages shown above are merely examples, and should be changed depending on the emission wavelength and light intensity of the VCSEL. In that case, the potential ("H") of the light-up signal φI can be adjusted.

[0067] (Operation of light source device 1) Next, the operation of the light source device 1 will be described. The first transfer signal φ1 transmitted to the φ1 terminal (see FIG. 3) and the second transfer signal φ2 transmitted to the φ2 terminal (see FIG. 3) are signals having two potentials: "H" (5 V) and "L" (0 V). The waveforms of the first transfer signal φ1 and the second transfer signal φ2 are repeated every two consecutive periods T (for example, periods T(1) and T(2)). A set of transfer signals, the first transfer signal φ1 and the second transfer signal φ2, propagates the on state of the transfer thyristors T in numerical order, thereby designating the VCSEL with the same number as the on-state transfer thyristor T as the target for lighting or non-lighting (lighting control).

[0068] The light-up signal φI supplied to the φI terminal (see FIG. 3) is a signal having two potentials: "H" (5V) and "L" (0V). When the lighting signal φI transitions from "L" to "H", the setting thyristor S corresponding to the VCSEL designated as the lighting target by the transfer signal is turned on, and the VCSEL lights up.

[0069] That is, when the transfer thyristor T is turned on, it designates the VCSEL that is the target of lighting control, and the lighting signal φI of “H” (5 V) turns on the setting thyristor S connected in series to the VCSEL that is the target of lighting control, and lights up the VCSEL. That is, in the light-emitting chip 10, the on state of the transfer thyristor T is transferred, and the VCSELs are sequentially lit up. The lighting signal φI at "L" (0V) maintains the setting thyristor S in the off state and also maintains the VCSEL in the non-lighted state. That is, the lighting signal φI sets the lighting / non-lighting of the VCSEL.

[0070] The light source device 1 of this embodiment includes a plurality of elements (transfer thyristors T1 to T6, setting thyristors S1 to S6, VCSEL1 to VDSEL6, etc.), and elements that are turned on among the plurality of elements are sequentially switched to the on state. As a result, in the light source device 1 of this embodiment, the control unit 110 controls the lighting of the plurality of transfer thyristors T1 to T6 in the transfer unit 12 of the light-emitting chip 10 to be individually turned on. When the transfer thyristors T1 to T6 are turned on, a VCSEL that is the target of lighting control is designated, and the plurality of setting thyristors S1 to S6 in the light-emitting unit 11 are individually turned on. When each setting thyristor S is turned on, the VCSEL corresponding to that setting thyristor S individually emits light. To add to this, in the light source device 1 of this embodiment, the control unit 110 and the transfer unit 12 of the light-emitting chip 10 are an example of a driver that individually drives the plurality of setting thyristors S to switch them to the on state. In the light-emitting chip 10 of this embodiment, the portion of the light-emitting layer 82 of each VCSEL that actually emits light when a current is supplied thereto is the light-emitting region of each VCSEL.

[0071] In the light-emitting chip 10 of this embodiment, when the setting thyristor S is turned on, a current can be supplied to the corresponding VCSEL. Then, when a current of a magnitude necessary for the VCSEL to emit light is actually supplied to the VCSEL, the VCSEL emits light. Depending on the configuration of the light-emitting chip 10 and the control by the control unit 110, after the setting thyristor S is turned on and a current can be supplied to the corresponding VCSEL, the on signal to the setting thyristor S may be stopped before the VCSEL emits light, while maintaining the state in which the VCSEL can emit light by supplying a current. Even in such a case, the VCSEL can be made to emit light by supplying a current of a magnitude necessary for the VCSEL to emit light after the setting thyristor S is turned off. In addition, in this case, after the setting thyristor S is turned on to make the VCSEL emit light, the setting thyristor S is in the off state when the VCSEL actually emits light. In this embodiment, "a thyristor (setting thyristor S) turning on causes a light-emitting element (VCSEL) to emit light" means that the setting thyristor S turning on causes the corresponding VCSEL to be in a state in which it can emit light when a current is supplied to it. In other words, after the setting thyristor S has turned the VCSEL into a state in which it can emit light when a current is supplied to it, the setting thyristor S may maintain the on state or may be in an off state when a current is supplied to the VCSEL and the VCSEL actually emits light.

[0072] (Relationship between power supply potential and lighting signal) In this embodiment, the voltage applied to the p-ohmic electrode 321 provided on the region 311 of the p-anode layer 88 of the setting thyristor S is lower than the voltage applied to the n-ohmic electrode 331 provided on the n-gate layer 87 of the setting thyristor S. Specifically, in this embodiment, a linear regulator 360 (see FIG. 3 ) is provided on the light-up signal line 75 to which the light-up signal φI is supplied from the light-up signal generating unit 140, thereby lowering the voltage applied to the p-ohmic electrode 321 provided on the region 311 of the p-anode layer 88 of the setting thyristor S. The linear regulator 360 is a type of power supply integrated circuit (IC) that can output a constant voltage lower than the input voltage, and an LDO (Low Drop Out) regulator, for example, is used. Because the voltage supplied by the light-up signal generating unit 140 and the voltage supplied by the power supply potential supply unit 170 are the same, the provision of the linear regulator 360 makes the voltage applied to the p-ohmic electrode 321 lower than the voltage applied to the n-ohmic electrode 331. The voltage applied to the p-ohmic electrode 321 is a voltage that allows a current to flow to the rear electrode 91 via the setting thyristor S and the corresponding VCSEL, and is not, for example, 0V.

[0073] When a VCSEL that is in a lit state transitions to a non-lit state, the charge does not flow but remains inside the setting thyristor S corresponding to the VCSEL. The cathode of the VCSEL is connected to the substrate 80, and a reference potential Vsub is supplied via a back electrode 91, which is a Vsub terminal provided on the back surface of the substrate 80. If charge remains inside the setting thyristor S, it will be pulled by the reference potential Vsub and flow to the back electrode 91 even when the setting thyristor is in the off state. Since a reverse bias is applied between the p-gate layer 86 and n-gate layer 87 of the setting thyristor S, no current should normally flow, but if charge remains, the charge will flow to the back electrode 91, causing the setting thyristor S to turn on. If charge remains inside the setting thyristor S in this way, there is a risk of erroneous lighting occurring when the setting thyristor S is turned on. Therefore, it is preferable that the setting thyristor S is configured to quickly release the charge remaining inside the setting thyristor S.

[0074] As described above, in this embodiment, the voltage applied to the p anode layer 88 of the setting thyristor S is lower than the voltage applied to the n gate layer 87 of the setting thyristor S. By creating a difference in voltage between the anode layer and the gate layer of the setting thyristor S in this way, it is possible to quickly remove the charge remaining inside the setting thyristor S and to prevent erroneous lighting from occurring. Note that the voltage applied to the p anode layer 88 of the setting thyristor S is an example of the second potential, and the voltage applied to the n gate layer 87 of the setting thyristor S is an example of the first potential.

[0075] Next, the movement of the charge remaining inside the setting thyristor S will be explained. FIG. 5 is a diagram showing a path through which the charge remaining inside the setting thyristor S escapes to the outside of the setting thyristor S. As shown in FIG. As shown in FIG. 5, the charge 350 remaining inside the setting thyristor S flows from the n-gate layer 87 of the setting thyristor S through the signal line connected to the n-ohmic electrode 331 to the power supply potential supply unit 170 (see FIG. 2), and is thereby discharged from the setting thyristor S. When the setting thyristor S is turned off, current stops flowing from the light-up signal generating unit 140 (see FIG. 2) to the back electrode 91, turning off the corresponding VCSEL. At this time, current cannot flow through the setting thyristor S, and a charge 350 remains inside the setting thyristor S. In this embodiment, in this state, a voltage higher than the voltage applied to the p anode layer 88 of the setting thyristor S is applied to the n gate layer 87 of the setting thyristor S. This voltage application creates a reverse bias state between the p anode layer 88 and the n gate layer 87 of the setting thyristor S. This allows the charge 350 to be moved at high speed, and the charge 350 remaining inside the setting thyristor S can be quickly discharged from the n gate layer 87 of the setting thyristor S to the power supply potential supply unit 170.

[0076] In this way, the charge 350 remaining inside the setting thyristor S is quickly drained from the signal line connected to the n-ohmic electrode 331 to the outside of the setting thyristor S, thereby being removed from the inside of the setting thyristor S. This makes it possible to prevent the charge 350 remaining inside the setting thyristor S from being drawn to the reference potential Vsub and flowing to the back electrode 91, and to prevent the setting thyristor S in the off state from being turned on and the corresponding VCSEL from erroneously lighting up.

[0077] The linear regulator 360 is not limited to the above configuration as long as it can reduce the voltage applied to the p ohmic electrode 321. In this embodiment, the linear regulator 360 is provided on the substrate 80, but it may be provided between the light-up signal generating unit 140 and the φI terminal.

[0078] (Addendum) (1) A substrate; a plurality of light-emitting elements provided on the substrate; a plurality of thyristors that, when turned on, cause each of the plurality of light-emitting elements to emit light or increase the amount of light emitted by each of the plurality of light-emitting elements, each of the thyristors having an anode layer, a gate layer, and a cathode layer stacked thereon, and that receive a potential such that a first potential supplied to the gate layer is higher than a second potential supplied to the anode layer; A light-emitting component comprising: (2) The light-emitting component described in (1) above, wherein when the thyristor is turned off, a potential is supplied such that a first potential supplied to the gate layer is higher than a second potential supplied to the anode layer, thereby creating a reverse bias state between the anode layer and the gate layer of the thyristor. (3) A substrate; a plurality of light-emitting elements provided on the substrate; a plurality of thyristors that, when turned on, cause each of the plurality of light-emitting elements to emit light or increase the amount of light emitted by each of the plurality of light-emitting elements, each of the thyristors having an anode layer, a gate layer, and a cathode layer stacked thereon, and that receive a potential such that a first potential supplied to the gate layer is higher than a second potential supplied to the anode layer; a driving unit provided on the substrate, which drives the thyristors individually to transition them to an ON state, and to which the second potential is supplied to the gate layer of the thyristor; A light emitting device comprising: (4) A substrate; a plurality of light-emitting elements provided on the substrate; a plurality of thyristors that, when turned on, cause each of the plurality of light-emitting elements to emit light or increase the amount of light emitted by each of the plurality of light-emitting elements, each of the thyristors having an anode layer, a gate layer, and a cathode layer stacked thereon, and that receive a potential such that a first potential supplied to the gate layer is higher than a second potential supplied to the anode layer; a driving unit provided on the substrate, which drives the thyristors individually to cause each of the light-emitting elements to emit light at a predetermined timing, and to which the second potential is supplied to the gate layer of the thyristor; an acquisition unit that acquires information about the object based on light reflected by the object from each light-emitting region; A measuring device comprising:

[0079] According to the inventions (1), (3), and (4), it is possible to suppress erroneous lighting compared to when the same voltage is applied to the anode layer and gate layer of a thyristor in which an anode layer, a gate layer, and a cathode layer are stacked. According to the invention (2), the charge remaining inside the thyristor can be quickly discharged. [Explanation of symbols]

[0080] 1...light source device, 5...3D sensor, 10...light-emitting chip, 11...light-emitting section, 12...transfer section, 110...control section, 80...substrate, 81...n-cathode (DBR) layer, 82...light-emitting layer, 83...p-anode (DBR) layer, 84...tunnel junction layer, 85...n-cathode layer, 86...p-gate layer, 87...n-gate layer, 88...p-anode layer, 100...measurement device, 200...measurement control section, S...setting thyristor, T...transfer thyristor, VCSEL...vertical-cavity surface-emitting laser

Claims

1. A substrate; a plurality of light-emitting elements provided on the substrate; a plurality of thyristors that, when turned on, cause the plurality of light-emitting elements to emit light or increase the amount of light emitted by the plurality of light-emitting elements, each thyristor having an anode layer, a gate layer, and a cathode layer stacked thereon, and that receive a potential such that a first potential supplied to the gate layer is higher than a second potential supplied to the anode layer; A light-emitting component comprising:

2. 2. The light-emitting component of claim 1, wherein when the thyristor is turned off, a potential is supplied to the gate layer such that a first potential supplied to the gate layer is higher than a second potential supplied to the anode layer, thereby creating a reverse bias state between the anode layer and the gate layer of the thyristor.

3. A substrate; a plurality of light-emitting elements provided on the substrate; a plurality of thyristors that, when turned on, cause the plurality of light-emitting elements to emit light or increase the amount of light emitted by the plurality of light-emitting elements, each thyristor having an anode layer, a gate layer, and a cathode layer stacked thereon, and that receive a potential such that a first potential supplied to the gate layer is higher than a second potential supplied to the anode layer; a driving unit provided on the substrate, which drives the thyristors individually to transition them to an ON state, and to which the second potential is supplied to the gate layer of the thyristor; A light emitting device comprising:

4. A substrate; a plurality of light-emitting elements provided on the substrate; a plurality of thyristors that, when turned on, cause the plurality of light-emitting elements to emit light or increase the amount of light emitted by the plurality of light-emitting elements, each thyristor having an anode layer, a gate layer, and a cathode layer stacked thereon, and that receive a potential such that a first potential supplied to the gate layer is higher than a second potential supplied to the anode layer; a driving unit provided on the substrate, which drives the thyristors individually to cause each of the light-emitting elements to emit light at a predetermined timing, the driving unit receiving the second potential supplied to the gate layer of the thyristor; an acquisition unit that acquires information about the object based on light reflected by the object from each light-emitting region; A measuring device comprising:

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