Processing unit, network node, client device and method thereof

Abstract

To provide a processing unit generating a second synchronous signal sequence used with a first synchronous signal sequence for synchronization.SOLUTION: A processing unit is configured such that a first circulation shift and a second circulation shift are determined at least on the basis of, a cell ID, at least one of the first circulation shift and the second circulation shift being associated with a first synchronous signal sequence by being determined also on the basis of an index of the first synchronous signal sequence. The processing unit is configured to generate a second synchronous signal sequence on the basis of a sum, with 2 as a modulus, of a first binary sequence cyclically shifted by the amount of the first circulation shift and a second binary sequence cyclically shifted by the amount of the second circulation shift. If two second synchronous signal sequences generated in association with the first synchronous signal sequence are cyclically shifted to each other, the generated two second synchronous signal sequences are non-sequentially shifted to each other.SELECTED DRAWING: Figure 2

Description

[Technical Field]

[0001] The present disclosure relates to a processing device, and to a network node and a client device comprising such a processing device. Further, the present disclosure also relates to a corresponding method and computer program. [Background technology]

[0002] Synchronization is fundamental to most communication systems, e.g., those based on Long Term Evolution (LTE) or LTE Advanced. To enable client devices to synchronize with the network, at least one transmit-receive point (TRP) in each cell of the network transmits multiple periodic synchronization signals. These synchronization signals are detected by nearby client devices and used by each client device to identify the appropriate cell as the serving cell. Synchronization thus enables a client device to connect to a TRP and track the connection between them for subsequent data communication.

[0003] In an LTE cellular system, synchronization signals include a primary synchronization signal (PSS) and a secondary synchronization signal (SSS). Each PSS and SSS is transmitted within each period, i.e., every 5 ms, using a unique orthogonal frequency division multiplexing (OFDM) code. There are three PSSs and 168 SSSs that are used together to convey 3 x 168 = 504 cell identities (IDs). The 168 SSSs are further scrambled by a PSS sequence index and are also scrambled to indicate the first and second half-frame timing. Different PSS and SSS sequence pairs convey different cell IDs and are transmitted by TRPs in different cells. First, a client device obtains rough time and frequency synchronization by detecting the PSS in the time domain, and also detects the index conveyed in the PSS.

[0004]

number

[0005] Then, the client device receives the indicator transmitted by the SSS.

[0006]

number

[0007] is obtained by detecting the SSS in the frequency domain. Then, the cell ID is

[0008]

number

[0009] Specifically, the PSS sequence is constructed based on Zadoff-Chu (ZC) sequences of length 63 with three different root indices, and the SSS sequence is constructed by inter-concatenating two m-sequences of length 31 with different cyclic shifts m0 and m1. These two short m-sequences have

[0010]

number

[0011] That is, there are 168 SSS sequences associated with each PSS sequence, and the second m-sequence is scrambled based on a cyclic shift of the first m-sequence. Cell ID N ID is the indicator

[0012]

number

[0013] and indicators

[0014]

number

[0015] , and a unique invertible mapping between the circular shifts m0 and m1 in the SSS sequence.

[0016] The 3rd Generation Partnership Project (3GPP) is currently working on defining New Radio (NR) access technology. It has been agreed that NR synchronization should use 3NR PSS sequences, based on m-sequences modulated with pure binary phase-shift keying (BPSK) at three different cyclic shifts. Furthermore, the number of NR SSS sequences will be approximately 1000 after scrambling. That is, each PSS sequence corresponds to approximately 333 SSS sequences. Therefore, 3 NR PSSs will yield approximately 3 × 333 ≒ 1000 cell IDs, which is approximately twice the number of cell IDs available in LTE.

[0017] Current LTE SSS designs concatenate two short m-sequences and are therefore at risk of high cross-correlation, since there are many SSS sequence pairs in which one of the two short m-sequences has the same cyclic shift. This high risk of cross-correlation can lead to a high probability of inaccurate cell ID detection, especially during handover procedures. Summary of the Invention [Means for solving the problem]

[0018] It is an object of embodiments of the present invention to provide a solution that alleviates or overcomes the drawbacks and problems of conventional solutions.

[0019] These and further objects are achieved by the subject matter of the independent claims. Further advantageous implementations of the invention can be found in the dependent claims.

[0020] According to a first aspect of the present invention, the above and other objects are achieved by a processing device for generating a second synchronization signal sequence to be used together with a first synchronization signal sequence for synchronization, the processing device comprising: The processing unit calculates the first cyclic shift m0 and the second cyclic shift m1 for at least cell ID N IDAt least one of the first cyclic shift m0 and the second cyclic shift m1 is determined based on an index of the first synchronization signal sequence.

[0021]

number

[0022] and is associated with the primary synchronization signal sequence by being determined based on The processing device is configured to generate a second synchronization signal sequence based on a modulo-2 sum of a first binary sequence cyclically shifted by a first cyclic shift m0 and a second binary sequence cyclically shifted by a second cyclic shift m1, and if two second synchronization signal sequences generated in association with the first synchronization signal sequence are cyclically shifted from one another, the two generated second synchronization signal sequences are non-sequentially shifted from one another.

[0023] Thus, two generated second synchronization signal sequences associated with a first synchronization signal sequence that are mutually circularly shifted cannot be mutually sequentially shifted. In other words, a first generated second synchronization signal sequence and a second generated second synchronization signal sequence, both associated with one and the same first synchronization signal sequence, where the first generated second synchronization signal sequence may be obtained by circularly shifting the second generated second synchronization signal sequence and / or the second generated second synchronization signal sequence may be obtained by circularly shifting the first generated second synchronization signal sequence, are only possible if the first and second generated second synchronization signal sequences are mutually non-sequentially shifted. That is, the first generated second synchronization signal sequence may be obtained only by circularly shifting the second generated second synchronization signal sequence by two or more steps and / or the second generated second synchronization signal sequence may be obtained only by circularly shifting the first generated second synchronization signal sequence by two or more steps.

[0024] The processing device according to the first aspect offers several advantages over conventional solutions: The advantage of the processing device is that the secondary synchronization signal SSS sequence is generated in a simple and efficient manner, such that low complexity and efficient encoding of the cell ID is provided.

[0025] Reducing the cross-correlation between secondary synchronization signal SSS sequences taking frequency offset into account can be achieved by generating secondary synchronization signal SSS sequences that improve the reliability of secondary synchronization signal SSS sequence detection in client devices, thereby reducing cell search time.

[0026] Furthermore, efficient, low-complexity mapping functions can be coded and decoded in closed form to obtain a sequence index from a cell ID, and vice versa, by generating and utilizing secondary synchronization signal SSS sequences. This reduces the complexity of the network node and the client device, and provides a fast and efficient method for determining the cell ID. At the client device, the descrambled received signal is efficiently detected, for example, by utilizing a fast Walsh-Hadamard transform (FWHT).

[0027] Thus, the described embodiments allow for efficient encoding of the cell ID into the secondary synchronized SSS sequence, thereby ensuring low cross-correlation between the SSS sequences even at large residual frequency offsets, while simplifying the mapping of the cell ID to the first and second cyclic shift values and vice versa.

[0028] In one implementation of the processing device according to the first aspect, the first and second binary sequences are one of a group, and the group is m-sequence, and m-sequences, where the generated secondary synchronization signal sequence belongs to a set of Gold sequences It consists of the following.

[0029] An advantage of this implementation is that it ensures low cross-correlation between the generated SSS sequences when the first and second binary sequences used to generate the secondary synchronization signal SSS sequence are m-sequences, particularly when they are m-sequences such that the generated secondary synchronization signal SSS sequence belongs to a set of Gold sequences.

[0030] In one implementation of the processing device according to the first aspect, one of the first and second binary sequences utilized to generate the second synchronization signal SSS sequence is the same binary sequence, for example the same pseudo-random maximum length sequence, and is used to generate one or more first synchronization signal PSS sequences.

[0031] In one implementation of the processing device according to the first aspect, the number of first synchronization signal sequences available for synchronization is one in a group, and the group includes: one primary synchronization signal sequence, two or more primary synchronization signal sequences, and Three primary synchronization signal sequences, It consists of the following.

[0032] An advantage of this implementation is that synchronization signal generation is flexible and adaptable to multiple cell IDs. Using one primary synchronization signal PSS sequence reduces the complexity of primary synchronization signal detection. Using two or more, e.g., three, primary synchronization signal PSS sequences allows a subset of secondary synchronization signal SSS sequences to be associated with each primary synchronization signal PSS sequence. Thus, after successful detection of the primary synchronization signal, only a subset of secondary synchronization signal SSS sequences needs to be detected, thereby reducing the complexity of secondary synchronization signal SSS detection. Therefore, this implementation is advantageous because it provides a trade-off between the detection complexity of the primary and secondary synchronization signals.

[0033] In one implementation of the processing device according to the first aspect, the generated second synchronization signal sequence has a length L of 127, where L=127.

[0034] An advantage of this implementation is that secondary synchronization signal (SSS) generation may be available for many currently available and soon to be available wireless systems.

[0035] In one implementation of the processing device according to the first aspect, the processing device is configured to: ID and a processing unit further configured to determine a first cyclic shift m0 and a second cyclic shift m1 associated with The first cyclic shift m0 is equal to the second cyclic shift m1, m0=m1, The first cyclic shift m0 and the second cyclic shift m1 are different from each other, m0≠m1, The first circular shift m0 is greater than the second circular shift m1, m0>m1; The first cyclic shift m0 is smaller than the second cyclic shift m1. <m1、 Two cyclic shift pairs (m0,m1) and (m0',m1') satisfy at most one of m0'=m0+1 and m1'=m1+1. Two pairs of circular shifts (m0, m1) and (m0', m1') satisfy at most one of m0'=m0+1 and m1'=m1+1, and the first circular shift m0 is greater than the second circular shift m1, i.e., m0>m1. Two pairs of circular shifts (m0, m1) and (m0', m1') satisfy at most one of m0'=m0+1 and m1'=m1+1, and the first circular shift m0 is smaller than the second circular shift m1. <m1、 Two cyclic shift pairs (m0, m1) and (m0', m1') that satisfy both m0'=m0+1 and m1'=m1+1 are associated with different first synchronization signal sequence indices. Two pairs of cyclic shifts (m0, m1) and (m0', m1') that satisfy both m0'=m0+1 and m1'=m1+1 are associated with different first synchronization signal sequence indices, and the first cyclic shift m0 is greater than the second cyclic shift m1, m0>m1; and Two pairs of cyclic shifts (m0, m1) and (m0', m1') that satisfy both m0'=m0+1 and m1'=m1+1 are associated with different first synchronization signal sequence indexes, and the first cyclic shift m0 is smaller than the second cyclic shift m1. <m1、 It consists of the following.

[0036] An advantage of this implementation is that it allows for flexible generation of the secondary synchronization signal SSS sequence, making it robust to large frequency offsets, which is also advantageous as it allows for further encoding of the 5 ms timing and / or adding other information to the secondary synchronization signal SSS sequence.

[0037] In one implementation of the processing device according to the first aspect, the processing device calculates the first cyclic shift m0 and the second cyclic shift m1 as:

[0038]

number

[0039] and further configured to determine: where: g is an integer greater than 1, L' is a positive integer equal to or less than the length L of the secondary synchronization signal sequence,

[0040]

number

[0041] is the index of the secondary synchronization signal sequence,

[0042]

number

[0043]

number

[0044] is the index of the primary synchronization signal sequence,

[0045]

number

[0046]

number

[0047] is the floor function, mod is the modulus operation.

[0048] The advantage of this implementation is that it ensures robustness against large frequency offsets. It also enables the full utilization of all cyclic shifts m1 of the second binary sequence. For example, by setting L' = L, the number of candidate cyclic shifts m0 of the first binary sequence can be minimized given the total number of cell IDs encoded into the secondary synchronization signal SSS sequence. This is advantageous because detection of the secondary synchronization signal SSS sequence in the client device can be implemented with such low complexity. In other words, the client device can first descramble the received signal sequence using a minimum number of assumed cyclic shifts of the first binary sequence. After descrambling, given the correct cyclic shift of the first binary sequence, the remaining received signal sequence is only the second binary sequence at an unknown cyclic shift, which can be detected using low-cost Fast Walsh-Hadamard Transform (FWHT) calculations.

[0049] In one implementation of the processing device according to the first aspect, the processing device calculates the first cyclic shift m0 and the second cyclic shift m1 as:

[0050]

number

[0051] and further configured to determine: where: g is an integer greater than 1, L' is a positive integer equal to or less than the length L of the secondary synchronization signal sequence,

[0052]

number

[0053] is the index of the secondary synchronization signal sequence,

[0054]

number

[0055]

number

[0056] is the index of the primary synchronization signal sequence,

[0057]

number

[0058]

number

[0059] is the floor function, mod is the modulus operation.

[0060] The advantage of this implementation is that it ensures robustness against large frequency offsets. This also enables the client device to detect the secondary synchronization signal SSS sequence at low cost based on descrambling and FWHT calculation. Furthermore, this implementation reduces the m0<m1(またはm0> This generates a first cyclic shift m0 and a second cyclic shift m1 that all satisfy the following condition (and equivalently m1). This allows for further encoding of the 5 ms timing and / or adding other information to the secondary synchronization signal SSS sequence by simply swapping the values of m0 and m1. Alternatively, a time-varying solution can be constructed if it is deemed useful to increase the number of assumptions in the secondary synchronization signal SSS sequence at a later date.

[0061] In one implementation of the processing device according to the first aspect, the processing device calculates the first cyclic shift m0 and the second cyclic shift m1 as:

[0062]

number

[0063] and further configured to determine: where: g is an integer equal to or greater than 1, L' is a positive integer equal to or less than the length L of the secondary synchronization signal sequence,

[0064]

number

[0065] is the index of the secondary synchronization signal sequence,

[0066]

number

[0067]

number

[0068] is the index of the primary synchronization signal sequence,

[0069]

number

[0070]

number

[0071] is the floor function, mod is the modulus operation.

[0072] An advantage of this implementation is that it ensures robustness against large frequency offsets. It also enables low-cost detection of the secondary synchronization signal SSS sequence at the client device based on descrambling and FWHT calculations. Furthermore, when g=1, this implementation allows selecting two cyclic shift pairs (m0,m1) and (m0',m1') that satisfy both m0'=m0+1 and m1'=m1+1, while associating the generated two corresponding pairs of secondary synchronization signal SSS sequences with different primary synchronization signal PSS sequence indices. In this way, a more effective value of the cyclic shift pair (m0,m1) can be selected, potentially enabling encoding of more cell IDs into the secondary synchronization signal SSS sequence without increasing the SSS sequence length.

[0073] In one implementation of the processing device according to the first aspect, the processing device calculates the first cyclic shift m0 and the second cyclic shift m1 as:

[0074]

number

[0075] and further configured to determine: where: g is an integer equal to or greater than 1, L' is a positive integer equal to or less than the length L of the secondary synchronization signal sequence,

[0076]

number

[0077] is the index of the secondary synchronization signal sequence,

[0078]

number

[0079]

number

[0080] is the index of the primary synchronization signal sequence,

[0081]

number

[0082]

number

[0083] is the floor function, mod is the modulus operation.

[0084] An advantage of this implementation is that it ensures robustness against large frequency offsets. This also enables the client device to detect the secondary synchronization signal SSS sequence at low cost based on descrambling and FWHT calculations. Furthermore, when g=1, this implementation allows selecting two cyclic shift pairs (m0,m1) and (m0',m1') that satisfy both m0'=m0+1 and m1'=m1+1, while associating the generated corresponding pairs of two secondary synchronization signal SSS sequences with different primary synchronization signal PSS sequence indices. In this way, a more effective value of the cyclic shift pair (m0,m1) can be selected, potentially enabling more cell IDs to be encoded into the secondary synchronization signal SSS sequence without increasing the SSS sequence length. Furthermore, this implementation allows selecting two cyclic shift pairs (m0,m1) that satisfy both m0'=m0+1 and m1'=m1+1, while associating the generated corresponding pairs of two secondary synchronization signal SSS sequences with different primary synchronization signal PSS sequence indices. This allows selecting a more effective value of the cyclic shift pair (m0,m1), potentially enabling encoding more cell IDs into the secondary synchronization signal SSS sequence without increasing the SSS sequence length.<m1(またはm0> This generates a first cyclic shift m0 and a second cyclic shift m1 that all satisfy the following condition (and equivalently m1). This allows for further encoding of the 5 ms timing and / or adding other information to the secondary synchronization signal SSS sequence by simply swapping the values of m0 and m1. Alternatively, a time-varying solution can be constructed if it is deemed useful to increase the number of assumptions in the secondary synchronization signal SSS sequence at a later date.

[0085] According to a second aspect of the present invention, the above and other objects are achieved in a network node comprising: a processing device configured to generate a second synchronization signal sequence according to any implementation according to the first aspect or according to the first aspect itself; a transceiver configured to transmit a synchronization signal based on the first synchronization signal sequence and the second synchronization signal sequence; Prepare.

[0086] The network node according to the second aspect offers several advantages over conventional solutions: The advantage of the network node is that it allows for a simple and efficient way of generating secondary synchronisation signal SSS sequences.

[0087] According to a third aspect of the present invention, the above and other objects are achieved in a client device comprising: a processing device configured to generate a second synchronization signal sequence according to any implementation according to the first aspect or according to the first aspect itself; a transceiver configured to receive a second synchronization signal by utilizing the generated second synchronization signal sequence; Based on the first cyclic shift m0 and the second cyclic shift m1 determined based on the received first synchronization signal and the received second synchronization signal, a cell ID N ID and a processing unit further configured to determine Prepare.

[0088] The client device according to the third aspect provides several advantages over conventional solutions. The advantages of the client device include a simple and efficient way to generate the secondary synchronization signal SSS sequence, a low complexity technique for detecting the secondary synchronization signal SSS sequence, and a method for determining a cell ID N from a first cyclic shift m0 and a second cyclic shift m1 from the detected secondary synchronization signal SSS sequence. ID The goal is to enable a simple and efficient way to decode the

[0089] According to a fourth aspect of the present invention, the above and other objects are achieved by a method for determining a secondary synchronization sequence to be used together with a primary synchronization signal sequence for synchronization, the method comprising: The first cyclic shift m0 and the second cyclic shift m1 are ID and determining the first cyclic shift m0 and the second cyclic shift m1 based on an index of the primary synchronization signal sequence.

[0090]

number

[0091] and associating the first synchronization signal sequence with the first synchronization signal sequence by determining the first synchronization signal sequence based on the first synchronization signal sequence. generating a second synchronization signal sequence based on a modulo-2 sum of a first binary sequence cyclically shifted by a first cyclic shift m0 and a second binary sequence cyclically shifted by a second cyclic shift m1, wherein if two second synchronization signal sequences generated in association with the first synchronization signal sequence are cyclically shifted from one another, the two generated second synchronization signal sequences are non-sequentially shifted from one another.

[0092] In one implementation of the method according to the fourth aspect, the first and second binary sequences are one of a group, and the group comprises: m-sequence, and m-sequences, where the generated secondary synchronization signal sequence belongs to a set of Gold sequences It consists of the following.

[0093] In one implementation of the method according to the fourth aspect, the number of first synchronization signal sequences usable for synchronization is one in a group, and the group is one primary synchronization signal sequence, two or more primary synchronization signal sequences, and Three primary synchronization signal sequences, It consists of the following.

[0094] In one implementation of the method according to the fourth aspect, the generated second synchronization signal sequence has a length L of 127, where L=127.

[0095] In one implementation of the method according to the fourth aspect, the method comprises: ID and determining a first cyclic shift m0 and a second cyclic shift m1 associated with The first cyclic shift m0 is equal to the second cyclic shift m1, m0=m1, The first cyclic shift m0 and the second cyclic shift m1 are different from each other, m0≠m1, The first circular shift m0 is greater than the second circular shift m1, m0>m1; The first cyclic shift m0 is smaller than the second cyclic shift m1. <m1、 Two cyclic shift pairs (m0,m1) and (m0',m1') satisfy at most one of m0'=m0+1 and m1'=m1+1. Two pairs of circular shifts (m0, m1) and (m0', m1') satisfy at most one of m0'=m0+1 and m1'=m1+1, and the first circular shift m0 is greater than the second circular shift m1, i.e., m0>m1. Two pairs of circular shifts (m0, m1) and (m0', m1') satisfy at most one of m0'=m0+1 and m1'=m1+1, and the first circular shift m0 is smaller than the second circular shift m1. <m1、 Two cyclic shift pairs (m0, m1) and (m0', m1') that satisfy both m0'=m0+1 and m1'=m1+1 are associated with different first synchronization signal sequence indices. Two pairs of cyclic shifts (m0, m1) and (m0', m1') that satisfy both m0'=m0+1 and m1'=m1+1 are associated with different first synchronization signal sequence indices, and the first cyclic shift m0 is greater than the second cyclic shift m1, m0>m1; and Two pairs of cyclic shifts (m0, m1) and (m0', m1') that satisfy both m0'=m0+1 and m1'=m1+1 are associated with different first synchronization signal sequence indexes, and the first cyclic shift m0 is smaller than the second cyclic shift m1. <m1、 It consists of the following.

[0096] In one implementation of the method according to the fourth aspect, the method comprises:

[0097]

number

[0098] and further comprising determining the where: g is an integer greater than 1, L' is a positive integer equal to or less than the length L of the secondary synchronization signal sequence,

[0099]

number

[0100] is the index of the secondary synchronization signal sequence,

[0101]

number

[0102]

number

[0103] is the index of the primary synchronization signal sequence,

[0104]

number

[0105]

number

[0106] is the floor function, mod is the modulus operation.

[0107] In one implementation of the method according to the fourth aspect, the method comprises:

[0108]

number

[0109] and further comprising determining the where: g is an integer greater than 1, L' is a positive integer equal to or less than the length L of the secondary synchronization signal sequence,

[0110]

number

[0111] is the index of the secondary synchronization signal sequence,

[0112]

number

[0113]

number

[0114] is the index of the primary synchronization signal sequence,

[0115]

number

[0116]

number

[0117] is the floor function, mod is the modulus operation.

[0118] In one implementation of the method according to the fourth aspect, the method comprises:

[0119]

number

[0120] and further comprising determining the where: g is an integer equal to or greater than 1, L' is a positive integer equal to or less than the length L of the secondary synchronization signal sequence,

[0121]

number

[0122] is the index of the secondary synchronization signal sequence,

[0123]

number

[0124]

number

[0125] is the index of the primary synchronization signal sequence,

[0126]

number

[0127]

number

[0128] is the floor function, mod is the modulus operation.

[0129] In one implementation of the method according to the fourth aspect, the method comprises:

[0130]

number

[0131] and further comprising determining the where: g is an integer equal to or greater than 1, L' is a positive integer equal to or less than the length L of the secondary synchronization signal sequence,

[0132]

number

[0133] is the index of the secondary synchronization signal sequence,

[0134]

number

[0135]

number

[0136] is the index of the primary synchronization signal sequence,

[0137]

number

[0138]

number

[0139] is the floor function, mod is the modulus operation.

[0140] The advantages of any method according to the fourth aspect are the same as the advantages of the corresponding processing device of the claim according to the first aspect.

[0141] According to a fifth aspect of the present invention, the above and other objects are achieved by a method for a network node, the method comprising: generating a second synchronization signal sequence by a method according to a fourth aspect; and transmitting a synchronization signal based on the first synchronization signal sequence and the second synchronization signal sequence.

[0142] The advantages of any method according to the fifth aspect are the same as the advantages of the corresponding network node of the claim according to the second aspect.

[0143] According to a sixth aspect of the present invention, the above and other objects are achieved by a method for a client device, the method comprising: generating a second synchronization signal sequence by a method according to a fourth aspect; receiving a secondary synchronization signal by utilizing the generated secondary synchronization signal sequence; Based on the first cyclic shift m0 and the second cyclic shift m1 determined based on the received first synchronization signal and the received second synchronization signal, a cell ID N ID and determining:

[0144] The advantages of any method according to the sixth aspect are the same as the advantages of the corresponding client device of the claim according to the third aspect.

[0145] The present disclosure also relates to a computer program characterized by code means which, when executed by a processing means, causes the processing means to perform any of the methods according to the present disclosure. Furthermore, the present disclosure also relates to a computer program product, the computer program product comprising a computer readable medium and the computer program as defined above, the computer program being contained in the computer readable medium and comprising one or more from the group of: Read-Only Memory (ROM), Programmable ROM (PROM), Erasable PROM (EPROM), Flash memory, Electrically EPROM (EEPROM) and hard disk.

[0146] Further applications and advantages of the present disclosure will become apparent from the following detailed description.

[0147] The accompanying drawings are intended to clearly illustrate various embodiments of the present invention. [Brief explanation of the drawings]

[0148] [Figure 1] FIG. 1 illustrates a processing device according to an embodiment of the present invention. [Figure 2] FIG. 1 illustrates a method for a processing device according to an embodiment of the present invention. [Figure 3] FIG. 2 illustrates a network node according to an embodiment of the present invention. [Figure 4] FIG. 1 illustrates a method for a network node according to an embodiment of the present invention. [Figure 5] FIG. 2 illustrates a client device according to an embodiment of the present invention. [Figure 6] FIG. 2 illustrates a method for a client device according to an embodiment of the present invention. [Figure 7] 1 illustrates a wireless system according to an embodiment of the present invention; [Figure 8] FIG. 10 is an illustration of a determined cyclic shift according to an embodiment of the present invention. [Figure 9] FIG. 10 is another illustration of a determined cyclic shift according to an embodiment of the present invention. [Figure 10] FIG. 10 is another illustration of a determined cyclic shift according to an embodiment of the present invention. [Figure 11] FIG. 10 is another illustration of a determined cyclic shift according to an embodiment of the present invention. [Figure 12] FIG. 10 is another illustration of a determined cyclic shift according to an embodiment of the present invention. [Figure 13] FIG. 10 is another illustration of a determined cyclic shift according to an embodiment of the present invention. DETAILED DESCRIPTION OF THE INVENTION

[0149] 1 illustrates a processing device 100 according to an embodiment of the present invention. The processing device 100 includes a processor 102 coupled to a memory 104. The processor 102 and the memory 104 are connected to each other by communication means 106 known in the art. In one embodiment, the processor 102 may be a dedicated processor solely for performing secondary synchronization signal SSS sequence generation according to an embodiment of the present invention. In some embodiments, the processor 102 may alternatively be shared with other processors in a network node or client device to perform additional processing.

[0150] The processing device 100 is for generating a secondary synchronization signal SSS sequence to be used together with the primary synchronization signal PSS sequence for synchronization, for example by the processor 102, based on at least cell ID N ID where at least one of the first cyclic shift m0 and the second cyclic shift m1 is determined based on an index of the primary synchronization signal PSS sequence.

[0151]

number

[0152] The PSS sequence is associated with the primary synchronization signal PSS sequence by being determined based on the PSS sequence.

[0153] The processing device 100 is further configured, for example, by the processor 102, to generate a second synchronization signal SSS sequence based on a modulo-2 sum of a first binary sequence cyclically shifted by a first cyclic shift m0 and a second binary sequence cyclically shifted by a second cyclic shift m1, such that if two generated second synchronization signal SSS sequences associated with a first synchronization signal PSS sequence are cyclically shifted versions of each other, then these two generated second synchronization signal SSS sequences are non-sequentially shifted versions of each other.

[0154] FIG. 2 shows a flowchart of a corresponding method 200 that may be implemented in a processing device 100 such as that shown in FIG.

[0155] The method 200 calculates the first cyclic shift m0 and the second cyclic shift m1 for at least one cell ID N ID wherein at least one of the first cyclic shift m0 and the second cyclic shift m1 is determined based on an index of the primary synchronization signal PSS sequence.

[0156]

number

[0157] The PSS sequence is associated with the primary synchronization signal PSS sequence by being determined based on the PSS sequence.

[0158] The method also includes a second step 204 of generating a second synchronization signal SSS sequence based on a modulo-2 sum of a first binary sequence cyclically shifted by a first cyclic shift m0 and a second binary sequence cyclically shifted by a second cyclic shift m1, such that if two generated second synchronization signal SSS sequences associated with a first synchronization signal PSS sequence are cyclically shifted versions of each other, then these two generated second synchronization signal SSS sequences are non-sequentially shifted versions of each other.

[0159] Figure 3 illustrates a network node 300 according to an embodiment of the present invention. In the embodiment shown in Figure 3, the network node 300 comprises a processing unit 100, a transceiver unit 302 and a memory 304. The processing unit 100 is connected to the transceiver unit 302 and the memory 304 by communication means 306 known in the art. Furthermore, the network node 300 comprises an antenna 308 connected to the transceiver unit 302, meaning that the network node 300 is configured for wireless communication in a wireless communication system.

[0160] The processing unit 100 of the network node 300 is configured to generate the secondary synchronization signal SSS sequence according to any one of the embodiments of the method 200 described herein. The transceiver unit 302 of the network node 300 is configured to transmit a synchronization signal based on the primary synchronization signal PSS sequence and the secondary synchronization signal SSS sequence.

[0161] Figure 4 shows a flowchart of a corresponding method 400 that may be performed in a network node 300 such as that shown in Figure 3. The method 400 comprises a first step 402 of generating a secondary synchronization signal SSS sequence according to any one of the embodiments of the method 200 described herein. The method further comprises a second step 404 of transmitting a synchronization signal based on the primary synchronization signal PSS sequence and the secondary synchronization signal SSS sequence.

[0162] Figure 5 illustrates a client device 500 according to an embodiment of the present invention. In the embodiment illustrated in Figure 5, the client device 500 comprises a processing unit 100, a transceiver 502, and a memory 504. The processing unit 100 is connected to the transceiver 502 and the memory 504 by communication means 506 known in the art. Additionally, the client device 500 comprises an antenna 508 connected to the transceiver 502, meaning that the client device 500 is configured for wireless communication in a wireless communication system.

[0163] The processing unit 100 of the client device 500 is configured to generate a secondary synchronization signal SSS sequence according to any one of the embodiments described herein. The transceiver unit 502 of the client device 500 is configured to receive a secondary synchronization signal SSS by using the generated secondary synchronization signal SSS sequence. Furthermore, the processing unit 100 determines a cell ID N based on a first cyclic shift m0 and a second cyclic shift m1 determined based on the received primary synchronization signal PSS and the received secondary synchronization signal SSS. ID is configured to determine

[0164] Figure 6 shows a flowchart of a corresponding method 600 that may be performed in a client device 500 such as that shown in Figure 5. The method 600 includes a first step 602 of generating a secondary synchronization signal SSS sequence according to any of the embodiments of the method 200 described herein. The method further includes a second step 604 of receiving a secondary synchronization signal SSS by utilizing the generated secondary synchronization signal SSS sequence. The method also includes a step 605 of receiving a cell ID N based on a first cyclic shift m0 and a second cyclic shift m1 determined based on the received primary synchronization signal PSS and the received secondary synchronization signal SSS. ID A third step 606 is determining:

[0165] 7 illustrates a wireless communication system 700 according to one embodiment. The wireless communication system 700 includes a network node 300 and a client device 500 configured to operate in the wireless communication system 700. Furthermore, the network node 300 and the client device 500 each include a processing unit 100. In the wireless communication system 700, a synchronization signal is transmitted by the network node 300 and received by the client device 500. Based on the synchronization signal, the client device 500 synchronizes with the network node 300 and acquires the cell ID of the network node 300, as described herein. The synchronization signal includes a first synchronization signal PSS sequence and a second synchronization signal SSS sequence, where the second synchronization signal SSS sequence is generated by the processing unit 100 in the network node 300. The client device 500 receives the synchronization signal using the second synchronization signal SSS sequence generated by the processing unit 100 in the client device 500, e.g., for correlation purposes, as described herein.

[0166] For simplicity, the wireless communication system 700 shown in Figure 7 includes only one network node 300 and one client device 500. However, the wireless communication system 700 may include any number of network nodes 300 and any number of client devices 500 without departing from the scope of the present invention.

[0167] The network node 300 herein may also be referred to as a radio network node, an access network node, an access point, or a base station, e.g., a Radio Base Station (RBS). Certain networks may also be referred to as transmitters, "gNBs," "eNBs," "eNodeBs," "NodeBs," or "B nodes," depending on the technology and terminology used. Radio network nodes may be classified into various categories, e.g., macro eNodeBs, home eNodeBs, or pico base stations, based on transmit power and thus cell size. The radio network node may also be a station (STA). The station (STA) is any device that includes an IEEE 802.11-compliant media access control (MAC) and a physical layer (PHY) interface to the wireless medium (WM). The network node 300 may also be a base station compatible with a fifth-generation wireless system.

[0168] The client device 500 herein may also be referred to as a user device, user equipment (UE), mobile station, Internet of Things (IoT) device, sensor device, wireless terminal, and / or mobile terminal, and may be capable of wireless communication over a wireless communication system, sometimes referred to as a cellular wireless system. Furthermore, a UE may also be referred to as a wirelessly-enabled mobile phone, cellular telephone, computer tablet, or laptop. In this context, a UE may be a portable, pocketable, handheld, computer-implemented, or vehicle-mounted device capable of communicating voice and / or data with others, such as other receivers or servers, over a wireless access network. A UE may also be a station (STA), which is any device that includes an IEEE 802.11-compliant media access control (MAC) and physical layer (PHY) interface to a wireless medium (WM). Client device 500 may also be configured for communication over fifth generation wireless technologies such as 3GPP related LTE and LTE Advanced, WiMAX and its evolution, and New Radio.

[0169] Furthermore, any method according to the embodiments of the present invention may be implemented in a computer program having code means, which, when executed by a processing means, causes the processing means to perform each step of the method. The computer program may be included in a computer-readable medium of a computer program product. The computer-readable medium may substantially include any memory, such as a read-only memory (ROM), a programmable read-only memory (PROM), an erasable programmable read-only memory (EPROM), a flash memory, an electrically erasable programmable read-only memory (EEPROM), or a hard disk drive.

[0170] Furthermore, it will be understood by those skilled in the art that embodiments of the present processing device 100, network node 300, and client device 500 include the necessary communication capabilities to perform the present solution, for example in the form of functions, means, units, elements, etc. Other examples of such means, units, elements, functions, etc. are processors, memories, buffers, control logic, encoders, decoders, rate matchers, de-rate matchers, mapping units, multipliers, decision units, selection units, switches, interleavers, de-interleavers, modulators, demodulators, inputs, outputs, antennas, amplifiers, receiving units, transmitting units, DSPs, MSDs, TCM encoders, TCM decoders, feeding units, feeding lines, communication interfaces, communication protocols, etc., suitably arranged together to perform the present solution.

[0171] In particular, the processors of the devices and nodes may comprise, for example, one or more instances of a central processing unit (CPU), processing unit, processing circuit, processor, application specific integrated circuit (ASIC), microprocessor, or other processing logic that may interpret and execute instructions. Thus, the term "processor" may refer to processing circuitry that includes, for example, multiple processing circuits, such as some, some, or all of the above. The processing circuitry may further perform data processing functions for inputting, outputting, and processing data, including data buffering and device control functions, such as call processing control, user interface control, etc.

[0172] In one embodiment, the first and second binary sequences utilized to generate the secondary synchronization signal SSS sequence are pseudo-random maximal length sequences, or m-sequences.

[0173] In one embodiment, the first and second binary sequences utilized to generate the secondary synchronization signal SSS sequences are pseudo-random maximal length sequences, i.e., m-sequences, and the generated secondary synchronization signal SSS sequences belong to a set of Gold sequences based on the m-sequences to ensure low cross-correlation between the generated SSS sequences. Gold sequences are described in more detail below.

[0174] In one embodiment, one of the first and second binary sequences used to generate the secondary synchronization signal SSS sequence is the same binary sequence, for example the same pseudo-random maximum length sequence, that is used to generate one or more primary synchronization signal PSS sequences.

[0175] As described below, in various embodiments, various numbers of primary synchronization signal PSS sequences may be available for the synchronization signal, such as one primary synchronization signal PSS sequence, two or more primary synchronization signal PSS sequences, and three primary synchronization signal PSS sequences. Thus, the generation of secondary synchronization signal SSS sequences described herein may be used with different numbers of primary synchronization signal PSS sequences, making the generation of synchronization signals flexible and adaptable to multiple cell IDs and / or wireless systems.

[0176] In one embodiment, as illustrated below, the generated secondary synchronization signal SSS sequence has a length L of 127. L=127, which is compatible with several currently available and soon to be available wireless systems in which the embodiments described herein may be implemented.

[0177] One embodiment of the present invention discloses SSS sequences, d(k), k=0, 1, 2,..., L-1, which can be constructed based on the modulo-2 sum of two length-L binary sequences with different cyclic shifts m0 and m1. According to one embodiment, BPSK modulation is used, i.e. d(k)=1-2((s0((k+m0) mod L)+s1((k+m1) mod L)) mod 2), k=0, 1, 2,…, L-1 (Formula 1)

[0178] The two binary sequences may be chosen, for example, as two m-sequences of the same length L with carefully chosen generator polynomials, such that all generated SSS sequences belong to the same set of Gold sequences, which ensures low cross-correlation between the generated SSS sequences.

[0179] For example, the generator polynomials are g0(x)=x 7 +x 4 +1 and g1(x)=x 7 +x+1. This generates a set of Gold sequences of length L = 127, of which n = 7 is the highest order in g0(x) and g1(x), and the absolute inner product of any two sequences is 1, 2. (n+1) / 2 -1=15 or 2 (n+1) / 2 +1=17.

[0180] According to one embodiment, one of the first and second binary sequences used to generate the second synchronization signal SSS sequence may be selected as the same binary sequence, e.g., the same pseudo-random maximum length sequence, and used to generate the first synchronization signal PSS sequence. Thus, the same binary sequence, e.g., the same m-sequence, may be used to generate both the first synchronization signal PSS sequence and one of the first and second binary sequences used to generate the second synchronization signal SSS sequence. For example, both the generated first synchronization signal PSS sequence and the generated second synchronization signal SSS sequence may belong to the same set of Gold sequences, thereby ensuring low cross-correlation between the generated second synchronization signal SSS sequence and the generated first synchronization signal PSS sequence.

[0181] Cell ID

[0182]

number

[0183] are the series indices of SSS and PSS, i.e.,

[0184]

number

[0185] and

[0186]

number

[0187] The PSS sequence is conveyed by the PSS code, which is encoded into a first m0 and a second m1 circular shift of two binary sequences, e.g., two m-sequences. For multiple PSS sequences, at least one of the first m0 and second m1 circular shifts depends on the PSS sequence index. Furthermore, if the generated SSS sequences are associated with the same PSS sequence index, low cross-correlation is guaranteed even with a large residual frequency offset. This is because one SSS sequence cannot be obtained by circularly shifting another SSS sequence associated with the same PSS index in one step.

[0188] According to one embodiment, there are no two determined cyclic shift pairs (m0,m1) and (m0',m1') that satisfy both m0'=m0+1 and m1'=m1+1. In other words, this may be expressed as any two SSS cyclic shift pairs (m0,m1) and (m0',m1'), which may satisfy at most one of m0'=m0+1 and m1'=m1+1. This ensures advantageous robustness against large frequency offsets. The cyclic shift pairs according to this embodiment may be obtained, for example, by encoding the sequence index conveyed in the PSS, i.e.,

[0189]

number

[0190] may be obtained as only one cyclic shift of the two binary sequences, e.g., the first cyclic shift m0, and any two candidate values of the first cyclic shift m0 must be separated from each other by more than one (1) cyclic shift step. In this way, sequential cyclic shifts of the first binary sequence are not selected simultaneously. This also means that only non-sequential cyclic shifts of the first binary sequence are selected. The total number of candidate values of the first cyclic shift m0 is kept at a minimum here so that SSS detection based on the low-complexity / cost scrambling FWHT can be utilized in the client device 500.

[0191] The sequence index conveyed by the SSS, i.e.,

[0192]

number

[0193] may be encoded as both a first m0-th and a second m1-th cyclic shift for the first and second binary sequences, where the second cyclic shift m1 can span all or most of its valid values {0, 1, 2, ..., L-1}. Such an SSS design prevents one SSS sequence from being obtainable by cyclically shifting another SSS sequence by one cyclic shift step, thereby ensuring robustness against large frequency offsets.

[0194] In addition, the PSS series index

[0195]

number

[0196] as the first circular shift m0, the index of the SSS sequence

[0197]

number

[0198] as the first cyclic shift m0 and the second cyclic shift m1 may be coded in any manner. For example, m0 and m1 may be interchanged in the following equation: Given a value of the first cyclic shift m0, the number of candidate values of the second cyclic shift m1 may be the same as or different from the various values of the first cyclic shift m0.

[0199] According to one implementation of this embodiment, the index of the SSS sequence

[0200]

number

[0201] and PSS series indicators

[0202]

number

[0203] The encoding of m into the first m0-th and second m1-th cyclic shifts is obtained as follows: That is, the first cyclic shift m0 and the second cyclic shift m1 are determined as follows:

[0204]

number

[0205] where g is the minimum cyclic shift step size between candidate values of the first cyclic shift m0 and is an integer greater than 1. L' is a positive integer less than or equal to the length L of the SSS sequence, where L'≦L, which is also the maximum number of candidate values of the second cyclic shift m1 for a given first cyclic shift m0. Here, and in this document,

[0206]

number

[0207] denotes the floor function, and mod denotes the modulo operation. Since g>1, the cyclic shift of any two SSS sequences (m0, m1) and (m0', m1') satisfies at most one of m0'=m0+1 and m1'=m1+1.

[0208] As a non-limiting example, if L=127 and

[0209]

number

[0210] It can be said that this example of the present embodiment may be implemented for the implementation of the New Radio synchronization signal. For example, g=2,

[0211]

number

[0212] and L'=112, a total of 336×3=1008 cell IDs are transmitted.

[0213] A schematic and non-limiting description of this example in this embodiment is:

[0214]

number

[0215]

number

[0216] , L=15, g=2, and L'=8 are presented in Figure 8. Because g=2, there are no two circular shift pairs (m0,m1) and (m0',m1') that satisfy both m0'=m0+1 and m1'=m1+1. This is illustrated in Figure 8, where all second positions along the diagonal direction are left unused. That is, positions that can be selected (black dots) are separated in the diagonal direction by positions that cannot be selected (white dots). In this document, the diagonal direction associated with the figure includes all lines / directions that satisfy m0=m1+c, where c is any integer. Thus, in the description of Figure 8, m0'=m0+1 and m1'=m1+1 cannot be satisfied simultaneously. In Figure 8, PSS series indicators

[0217]

number

[0218] is on the y-axis, where both m0=0 and m0=2 have the same PSS sequence index.

[0219]

number

[0220] That is, both m0=0 and m0=2 have the same PSS sequence index.

[0221]

number

[0222] Accordingly, both m0=4 and m0=6 are associated with the same PSS sequence index.

[0223]

number

[0224] It is related to the PSS series index.

[0225]

number

[0226] to the first circular shift m0, and the SSS index

[0227]

number

[0228] The association of m0 and m1 is not restricted to the order shown in Figure 8. Other than that, any other order is also possible.

[0229] Furthermore, cell ID N ID may be determined based on the first cyclic shift m0 and the second cyclic shift m1, according to an embodiment, which is calculated from the first m0 and second m1 cyclic shift values as PSS

[0230]

number

[0231] and SSS

[0232]

number

[0233] This is possible because there exists a simple inverse mapping to the sequence indices, which may be written, for example, as follows:

[0234]

number

[0235]

number

[0236] Based on the first m0 and second m1 circular shifts, the PSS and SSS sequence indices are thus

[0237]

number

[0238] and

[0239]

number

[0240] The simplified determination of m0 th and m1 th alleviates the need to implement large tables in the client device to determine the cell ID from the cyclic shifts of the first m0th and second m1th.

[0241] According to one embodiment, there are no two determined cyclic shift pairs (m0,m1) and (m0',m1') that satisfy both m0'=m0+1 and m1'=m1+1. That is, two cyclic shift pairs (m0,m1) and (m0',m1') may satisfy at most one of m0'=m0+1 and m1'=m1+1, and at the same time, the determined cyclic shift pair does not satisfy m0<m1(またはm0> m1 (and equivalently m1) always satisfies this, which ensures advantageous robustness against large frequency offsets.

[0242] According to one implementation of this embodiment, PSS

[0243]

number

[0244] The series indicators conveyed by SSS

[0245]

number

[0246] The encoding of the sequence index conveyed in into the first m0-th and second m1-th cyclic shifts is given as follows: That is, the first cyclic shift m0 and the second cyclic shift m1 are determined as follows:

[0247]

number

[0248] Here, g>1 is the minimum step size between candidate values of the first cyclic shift m0, and L'≦L is the maximum number of candidate values of the second cyclic shift m1 for a given first cyclic shift m0. Since g>1, any two cyclic shift pairs of SSS sequences, e.g., (m0, m1) and (m0', m1'), satisfy at most one of m0'=m0+1 and m1'=m1+1. Also, the generated cyclic shift pairs are generated by<m1(またはm0> m1) is always satisfied. If the SSS is transmitted twice every 10 ms, i.e. once in each half-frame, this is advantageous as it makes it possible to indicate 5 ms timing using the SSS sequence (as is done for example in LTE) by simply swapping the values m0 and m1 during one half-frame. Alternatively, this implementation provides a solution that is future proof for future New Radio releases, for example if it is deemed useful to later increase the number of assumptions in the SSS.

[0249] As a non-limiting example, assume L=127 and

[0250]

number

[0251] For example, when g=2, this implementation may be implemented.

[0252]

number

[0253] and L'=115, a total of 336 x 3 = 1008 cell IDs are transmitted.

[0254] A non-limiting example of this implementation is:

[0255]

number

[0256]

number

[0257] , for L=15, g=2 and L'=8, is presented in Figure 9. In Figure 9, PSS series indicators

[0258]

number

[0259] is on the y-axis, where both m0=0 and m0=2 have the same PSS sequence index.

[0260]

number

[0261] That is, both m0=0 and m0=2 have the same PSS sequence index.

[0262]

number

[0263] Accordingly, both m0=4 and m0=6 are associated with the same PSS sequence index.

[0264]

number

[0265] It is related to the PSS series index.

[0266]

number

[0267] to the first circular shift m0, and the SSS sequence index

[0268]

number

[0269] The association of the first m0 and second m1 cyclic shifts is not limited to the order shown in FIG. 9, and for example, any other order is also possible.

[0270] Furthermore, cell ID N ID may be determined based on the first cyclic shift m0 and the second cyclic shift m1, according to an embodiment, which is calculated from the first m0 and second m1 cyclic shift values as PSS

[0271]

number

[0272] and SSS

[0273]

number

[0274] This is possible because there exists a simple inverse mapping to the sequence indices, which may be written, for example, as follows:

[0275]

number

[0276] Based on the first m0 and second m1 circular shifts, the PSS

[0277]

number

[0278] and SSS

[0279]

number

[0280] The simplified determination of the sequence index alleviates the need to implement extensive tables in the client device to determine the cell ID from the cyclic shifts of the first m0th and second m1th.

[0281] According to one implementation of this embodiment, the index of the SSS sequence

[0282]

number

[0283] and PSS series indicators

[0284]

number

[0285] Coding m0 into the first m0-th and second m1-th cyclic shifts is obtained as follows: That is, the first cyclic shift m0 and the second cyclic shift m1 are determined as follows:

[0286]

number

[0287] where g is the minimum cyclic shift step size between candidate values of the first cyclic shift m0 and is an integer greater than 1, g>1. L' is a positive integer less than or equal to the length L of the SSS sequence, L'≦L, which is also the maximum number of candidate values of the second cyclic shift m1 for a given first cyclic shift m0. Since g>1, any two SSS sequence cyclic shift pairs, (m0, m1) and (m0', m1'), satisfy at most one of m0'=m0+1 and m1'=m1+1.

[0288] As a non-limiting example, if L=127 and

[0289]

number

[0290] It can be said that this example of the present embodiment may be implemented for the implementation of the New Radio synchronization signal. For example, g=2,

[0291]

number

[0292] Assuming that L'=112, a total of 336×3=1008 cell IDs are transmitted.

[0293] A schematic and non-limiting description of this example in this embodiment is:

[0294]

number

[0295]

number

[0296] , L=15, g=2, and L'=8 are presented in FIG. 10. Because g=2, there are no two cyclic shift pairs (m0,m1) and (m0',m1') that satisfy both m0'=m0+1 and m1'=m1+1. This is illustrated in FIG. 10, where every second position along the diagonal is left unused. That is, positions that can be selected (black dots) are diagonally separated by positions that cannot be selected (white dots). Thus, in the illustration of FIG. 10, m0'=m0+1 and m1'=m1+1 cannot be simultaneously satisfied. In FIG. 10, PSS series indicators

[0297]

number

[0298] is on the y-axis, where m0=0 and m0=4 both have the same PSS sequence index.

[0299]

number

[0300] That is, both m0=0 and m0=4 have the same PSS sequence index.

[0301]

number

[0302] Accordingly, both m0=2 and m0=6 are associated with the same PSS sequence index.

[0303]

number

[0304] It is related to the PSS series index.

[0305]

number

[0306] to the first circular shift m0, and the SSS index

[0307]

number

[0308] The association of m0 and m1 with cell ID N is not restricted to the order shown in FIG. 10. Alternatively, any other order is possible. ID may be determined based on the first cyclic shift m0 and the second cyclic shift m1, according to an embodiment, which is calculated from the first m0 and second m1 cyclic shift values as PSS

[0309]

number

[0310] and SSS

[0311]

number

[0312] This is possible because there exists a simple inverse mapping to the sequence index, which may be written, for example, as follows:

[0313]

number

[0314] Based on the first m0 and second m1 circular shifts, the PSS

[0315]

number

[0316] and SSS

[0317]

number

[0318] The simplified determination of the sequence index alleviates the need to implement extensive tables in the client device to determine the cell ID from the cyclic shifts of the first m0th and second m1th.

[0319] According to one implementation of this embodiment, PSS

[0320]

number

[0321] The series indicators conveyed by SSS

[0322]

number

[0323] Encoding the sequence index conveyed in into the first m0-th and second m1-th cyclic shifts can be obtained as follows: That is, the first cyclic shift m0 and the second cyclic shift m1 are determined as follows:

[0324]

number

[0325] Here, g>1 is the minimum step size between candidate values of the second cyclic shift m1, and L'≦L is the maximum number of candidate values of the second cyclic shift m1 for a given first cyclic shift m0. Since g>1, any two cyclic shift pairs of SSS sequences, e.g., (m0, m1) and (m0', m1'), satisfy at most one of m0'=m0+1 and m1'=m1+1. Also, the generated / selected cyclic shift pair is m0.<m1(またはm0> m1) is always satisfied. If the SSS is transmitted twice every 10 ms, i.e. once in each half-frame, this is advantageous as it makes it possible to indicate 5 ms timing using the SSS sequence (as is done for example in LTE) by simply swapping the values m0 and m1 during one half-frame. Alternatively, this implementation provides a solution that is future proof for future New Radio releases, for example if it is deemed useful to increase the number of assumptions in the SSS later.

[0326] As a non-limiting example, if L=127 and

[0327]

number

[0328] For example, when g=2, this implementation may be implemented.

[0329]

number

[0330] and L'=115, a total of 336 x 3 = 1008 cell IDs are transmitted.

[0331] A non-limiting example of this implementation is:

[0332]

number

[0333]

number

[0334] , for L=15, g=2 and L'=8, is presented in Figure 11. In Figure 11, PSS series indicators

[0335]

number

[0336] is on the y-axis, where m0=0 and m0=4 both have the same PSS sequence index.

[0337]

number

[0338] That is, both m0=0 and m0=4 have the same PSS sequence index.

[0339]

number

[0340] Accordingly, both m0=2 and m0=6 are associated with the same PSS sequence index.

[0341]

number

[0342] It is related to the PSS series index.

[0343]

number

[0344] to the first circular shift m0, and the SSS sequence index

[0345]

number

[0346] The association of the first m0 and second m1 cyclic shifts is not limited to the order shown in FIG. 11, and for example, any other order is also possible.

[0347] Furthermore, cell ID N ID may be determined based on the first cyclic shift m0 and the second cyclic shift m1, according to an embodiment, which is calculated from the first m0 and second m1 cyclic shift values as PSS

[0348]

number

[0349] and SSS

[0350]

number

[0351] This is possible because there exists a simple inverse mapping to the sequence index, which may be written, for example, as follows:

[0352]

number

[0353] Based on the first m0 and second m1 circular shifts, the PSS

[0354]

number

[0355] and SSS

[0356]

number

[0357] The simplified determination of the sequence index alleviates the need to implement extensive tables in the client device to determine the cell ID from the cyclic shifts of the first m0th and second m1th.

[0358] According to one embodiment, the two circular shift pairs (m0, m1) and (m0', m1') are different PSS sequence indices.

[0359]

number

[0360] , two cyclic shift pairs (m0,m1) and (m0',m1') can satisfy both m0'=m0+1 and m1'=m1+1, which ensures robustness against large frequency offsets.

[0361] The circular shift pair according to this embodiment may be obtained, for example, by encoding the sequence index conveyed in the PSS, i.e., for non-sequential circular shifts of one of the two binary sequences:

[0362]

number

[0363] For example, any two candidate values of the first cyclic shift m0, i.e., the first cyclic shift m0 associated with the same primary synchronization signal PSS sequence index, are separated from each other by more than one (1) cyclic shift step and are associated with different PSS sequence indexes.

[0364]

number

[0365] can be coded into sequential values of the first cyclic shift m. The total number of first cyclic shifts m is kept to a minimum so that SSS detection based on low-cost / complexity scrambling FWHT can be utilized in the client device 500.

[0366] The series indicators conveyed by SSS, i.e.,

[0367]

number

[0368] may be coded as both a circular shift of two m-sequences m0 and m1, where m1 can span all or most of its valid values {0, 1, 2, ..., L-1}. Such an SSS design may lead to one SSS sequence being obtainable by circularly shifting another SSS sequence by one cycle shift step. However, according to an embodiment, such an SSS sequence pair may be coded using different PSS sequence indices.

[0369]

number

[0370] and will not be co-detected after successful detection of the PSS in the client device 500.

[0371] In addition, the PSS series index

[0372]

number

[0373] as the first circular shift m0, the index of the SSS sequence

[0374]

number

[0375] as the first cyclic shift m0 and the second cyclic shift m1 may be coded in any manner, i.e., m0 and m1 may be swapped in the following equation: Given a value of the first cyclic shift m0, the number of candidate values of the second cyclic shift m1 may be the same as or different from the various values of the first cyclic shift m0.

[0376] According to one implementation of this embodiment, the sequence index

[0377]

number

[0378] and

[0379]

number

[0380] Coding ⁢ ⁢ m ⁢ ...

[0381]

number

[0382] This is a restriction / limitation of the coding scheme in equations (10) and (11) above, since g is now limited to the value 1, and g=1. According to an implementation, two SSS sequences whose cyclic shift pairs (m0,m1) and (m0',m1') satisfy both m0'=m0+1 and m1'=m1+1 can coexist if they are associated with different PSS indices according to equations (18) and (19). This is advantageous because a more efficient value of the cyclic shift pair (m0,m1) can be selected, potentially allowing for encoding of more cell IDs and possibly adding other information to the SSS sequence without increasing the SSS sequence length.

[0383] As a non-limiting example, if L=127 and

[0384]

number

[0385] It can be said that this implementation form may be used for the implementation of the New Radio synchronization signal. For example,

[0386]

number

[0387] Assuming that L'=112, a total of 336×3=1008 cell IDs are transmitted.

[0388] The explanation for this example is as follows:

[0389]

number

[0390]

number

[0391] , for L=15 and L'=8 are given in FIG. 12. In FIG. PSS series indicators

[0392]

number

[0393] is on the y-axis, where both m0=0 and m0=2 have the same PSS sequence index.

[0394]

number

[0395] That is, both m0=0 and m0=2 have the same PSS sequence index.

[0396]

number

[0397] Accordingly, both m0=1 and m0=3 are associated with the same PSS sequence index.

[0398]

number

[0399] It is related to the PSS series index.

[0400]

number

[0401] to the first circular shift m0, and the SSS sequence index

[0402]

number

[0403] The association of the first m0 and second m1 cyclic shifts is not restricted to the order shown in FIG. 12.

[0404]

number

[0405] Any other ordering is possible as long as the cyclic shift pairs of any two SSS sequences associated with m, e.g., (m0,m1) and (m0',m1') satisfy at most one of m0'=m0+1 and m1'=m1+1.

[0406] Furthermore, cell ID N ID may be determined based on the first cyclic shift m0 and the second cyclic shift m1, according to an embodiment, which is calculated from the first m0 and second m1 cyclic shift values as PSS

[0407]

number

[0408] and SSS

[0409]

number

[0410] This is possible because there exists a simple inverse mapping to the sequence index, which may be written, for example, as follows:

[0411]

number

[0412] This is a restricted / limited version of the inverse mapping in equations (12) and (13) above, where g = 1, for a value of g of 1. This alleviates the need to implement large tables in client device 500 to determine the cell ID from the first m0 and second m1 cyclic shift values.

[0413] According to one embodiment, the two circular shift pairs (m0, m1) and (m0', m1') are different PSS sequence indices.

[0414]

number

[0415] , two circular shift pairs (m0,m1) and (m0',m1') can satisfy both m0'=m0+1 and m1'=m1+1, and the generated circular shift pair is m0<m1(または、m0> m1) is always satisfied.

[0416] According to one implementation of this embodiment, the sequence index

[0417]

number

[0418] and

[0419]

number

[0420] Coding ⁢ ⁢ m ⁢ ...

[0421]

number

[0422] This is a restriction / limitation of the coding scheme in the above equations (14) and (15) since g is now limited to the value 1, and g = 1. According to the implementation, two SSS sequences whose cyclic shift pairs (m0,m1) and (m0',m1') satisfy both m0' = m0 + 1 and m1' = m1 + 1 are associated with different PSS indices according to equations (22) and (23), and the generated cyclic shift pair always satisfies m0<m1(またはm0> Coexistence is possible if the SSS sequence satisfies the above conditions (and m1 is equivalent). This is advantageous as explained above, since it allows the SSS sequence to indicate 5 ms timing by swapping the values of m0 and m1, as used in LTE for example. Alternatively, this constitutes a non-obsolete solution for future New Radio releases, in case it is deemed useful to increase the number of assumptions in the SSS later.

[0423] As a non-limiting example, if L=127 and

[0424]

number

[0425] It can be said that this implementation form may be used for the implementation of the New Radio synchronization signal. For example,

[0426]

number

[0427] and L'=112, conveying a total of 336 x 3 = 1008 cell IDs. A non-limiting illustration of one such implementation is:

[0428]

number

[0429]

number

[0430] , for L=15 and L'=8 are presented in Figure 13. In Figure 13, the PSS sequence index

[0431]

number

[0432] is on the y-axis, where both m0=0 and m0=2 have the same PSS sequence index.

[0433]

number

[0434] That is, both m0=0 and m0=2 have the same PSS sequence index.

[0435]

number

[0436] Accordingly, both m0=1 and m0=3 are associated with the same PSS sequence index.

[0437]

number

[0438] It is related to the PSS series index.

[0439]

number

[0440] to the first circular shift m0, and the SSS sequence index

[0441]

number

[0442] The association of the first m0 and second m1 cyclic shifts is not restricted to the order shown in FIG. 13.

[0443]

number

[0444] Any other ordering is possible as long as the cyclic shift pairs of any two SSS sequences associated with m, e.g., (m0, m1) and (m0', m1') satisfy at most one of m0'=m0+1 and m1'=m1+1, and the generated cyclic shift pairs always satisfy m0< m1 (or m0>m1).

[0445] Furthermore, cell ID N ID may be determined based on the first cyclic shift m0 and the second cyclic shift m1, according to an embodiment, which is calculated from the first m0 and second m1 cyclic shift values as PSS

[0446]

number

[0447] and SSS

[0448]

number

[0449] This is possible because there exists a simple inverse mapping to the sequence index, which may be written, for example, as follows:

[0450]

number

[0451] This is a restriction / limitation of the inverse mapping in equations (16) and (17) above, where g is now restricted to the value 1, so g = 1. This alleviates the need to implement large tables in client device 500 to determine the cell ID from the first m0 and second m1 cyclic shift values.

[0452] As mentioned above, at least one cell ID N ID The first cyclic shift m0 and the second cyclic shift m1 associated with m may be determined according to any number of embodiments described herein, and thereby be related to each other in various ways.

[0453] According to some embodiments described herein, for example those described in Figures 8, 10 and 12, the first m0 and second m1 circular shifts may be determined such that the first circular shift m0 and the second circular shift m1 are equal, m0 = m1, i.e. there are available positions diagonally through the origin of the coordinates.

[0454] According to some embodiments described herein, for example those described in Figures 9, 11 and 13, the first m0 and second m1 circular shifts may be determined such that the first circular shift m0 and the second circular shift m1 are different from each other, m0 ≠ m1, and there are no available positions diagonally through the origin of the coordinates.

[0455] According to some embodiments described herein, the first m0 and second m1 circular shifts may be determined such that the first circular shift m0 is greater than the second circular shift m1, m0>m1, i.e., there are only available positions diagonally above through the origin of the coordinate system.

[0456] According to some embodiments described herein, such as those described in FIGS. 9, 11, and 13, the first cyclic shift m0 and the second cyclic shift m1 may be determined such that the first cyclic shift m0 is less than the second cyclic shift m1, i.e., m0 < m1, such that there are available positions only below the diagonal direction passing through the origin of the coordinates.

[0457] According to some embodiments described herein, such as those described in FIGS. 8, 9, 10, and 11, the first cyclic shift m0 and the second cyclic shift m1 may be determined such that at most one of the two cyclic shift pairs (m0, m1) and (m0', m1') satisfies m0' = m0 + 1 and m1' = m1 + 1. That is, there is always an unused position between the available positions in the diagonal direction.

[0458] According to some embodiments described herein, the first cyclic shift m0 and the second cyclic shift m1 may be determined such that at most one of the two cyclic shift pairs (m0, m1) and (m0', m1') satisfies m0' = m0 + 1 and m1' = m1 + 1, and the first cyclic shift m0 is greater than the second cyclic shift m1, i.e., m0 > m1, such that there is always an unused position between the available positions in the diagonal direction and there are available positions only above the diagonal direction passing through the origin of the coordinates.

[0459] According to some embodiments described herein, such as those described in FIGS. 9 and 11, the first cyclic shift m0 and the second cyclic shift m1 may be determined such that at most one of the two cyclic shift pairs (m0, m1) and (m0', m1') satisfies m0' = m0 + 1 and m1' = m1 + 1, and the first cyclic shift m0 is less than the second cyclic shift m1, i.e., m0 < m1, such that there is always an unused position between the available positions in the diagonal direction and there are available positions only below the diagonal direction passing through the origin of the coordinates.

[0460] According to some embodiments described herein, for example, those described in FIG. 12 and FIG. 13, the first m0 and second m1 cyclic shifts are such that two cyclic shift pairs (m0, m1) and (m0', m1') satisfying both m0'=m0+1 and m1'=m1+1 are different primary synchronization signal PSS sequence coordinates.

[0461]

number

[0462] It may be determined to be associated with

[0463] According to some embodiments described herein, the first m0 and second m1 cyclic shifts are such that two cyclic shift pairs (m0, m1) and (m0', m1') satisfying both m0'=m0+1 and m1'=m1+1 are different primary synchronization signal PSS sequence indices.

[0464]

number

[0465] and the first circular shift m0 may be determined to be greater than the second circular shift m1, such that m0>m1. That is, there are only available positions diagonally upward through the origin of the coordinate system.

[0466] According to some embodiments described herein, such as those illustrated in FIG. 13, the first m0 and second m1 cyclic shifts are such that two cyclic shift pairs (m0, m1) and (m0', m1') satisfying both m0'=m0+1 and m1'=m1+1 are different primary synchronization signal (PSS) sequence indices.

[0467]

number

[0468] It may be determined to be associated with a first cyclic shift m0 being smaller than a second cyclic shift m1, such that m0 < m1. That is, there are positions that can be used only below the diagonal direction passing through the origin of coordinates.

[0469] Finally, it should be understood that the present invention is not limited to the above embodiments, but also relates to and includes all embodiments within the scope of the appended independent claims.

Explanation of Signs

[0470] 100 Processing device 102 Processor 104 Memory 106 Communication means 200 Method 300 Network node 302 Transceiver 304 Memory 306 Communication means 308 Antenna 400 Method 500 Client device 502 Transceiver 504 Memory 506 Communication means 508 Antenna 600 Method 700 Wireless communication system

Claims

1. First circular shift m 0 and the second circular shift m 1 determining a A secondary synchronization signal (SSS) sequence for an SSS (secondary synchronization signal) is shifted by the first cyclic shift m 0 and the second cyclic shift m 1 and generating a signal based on the received signal, m 0 and m 1 teeth, [Equation 1] Fulfilling where: g is an integer equal to or greater than 1, L' is 112, [Equation 2] and [Equation 3] A wireless communication method.

2. The SSS sequence for the SSS is shifted by the first cyclic shift m 0 and the second cyclic shift m 1 The step of generating based on The first cyclic shift m 0 the first binary sequence cyclically shifted by m 1 and a second binary sequence cyclically shifted by a first sigma-shifted integer multiple of 1, wherein the first binary sequence and the second binary sequence have the same length.

3. The method of claim 2 , wherein the first and second binary sequences are m-sequences.

4. The generating polynomial of the first binary sequence is g 0 (x)=x 7 +x 4 +1, and the generator polynomial of the second binary sequence is g 1 (x)=x 7 4. The method of claim 2 or 3, wherein +x+1.

5. The method further includes generating a primary synchronization signal sequence for a primary synchronization signal (PSS), the PSS sequence comprising: [Equation 4] 5. The method according to claim 1, associated with

6. The method of claim 5 , wherein the PSS sequence is generated based on one of the first and second binary sequences.

7. 7. The method according to claim 5, wherein a generator polynomial of the PSS sequence is the same as one of the generator polynomials of the first and second binary sequences.

8. 8. The method of claim 5, wherein the PSS sequence is one in a group of three PSS sequences.

9. 9. The method according to claim 1, wherein the length L of the SSS sequence is 127. 【Request 10】 【Number 5】 is 3, [Equation 6] 10. The method according to any one of claims 1 to 9, wherein 【Request 11】 【Number 7】 is 336, [Equation 8] 11. The method according to any one of claims 1 to 10, wherein

12. The first cyclic shift m 0 and the second cyclic shift m 1 is the cell ID N ID Associated with [Equation 9] 12. The method according to any one of claims 1 to 11, wherein

13. A processing device for wireless communication, said processing device configured to perform the method of any one of claims 1 to 12.

14. A processing device configured to generate a secondary synchronization signal (SSS) sequence for SSS according to any one of claims 1 to 12; a transmitter configured to transmit the second synchronization signal based on the SSS sequence; A network node equipped with

15. 1. A client device for wireless communication, comprising: a transceiver configured to receive a communication signal including a primary synchronization signal (PSS) and a secondary synchronization signal (SSS); a first cyclic shift m determined based on the received PSS and SSS; 0 and the second circular shift m 1 Based on the cell identification (ID) N ID and a processing unit configured to determine The first cyclic shift m 0 and the second cyclic shift m 1 teeth, [Equation 10] Fulfilling where: g is an integer equal to or greater than 1, L' is 112, [0011] and [0012] The client device.

16. The SSS sequence for the SSS is the first cyclic shift m 0 and the first binary sequence corresponding to the second cyclic shift m 1 and a second binary sequence corresponding to said first binary sequence, said first binary sequence and said second binary sequence having the same length.

17. The generating polynomial of the first binary sequence is g 0 (x)=x 7 +x 4 +1, and the generator polynomial of the second binary sequence is g 1 (x)=x 7 +x+1.

18. The processing device is ID the first cyclic shift m associated with 0 and the second cyclic shift m 1 and determining the cell ID N ID the first cyclic shift m 0 and the second circular shift m 1 configured to determine from [0013] 18. The client device according to any one of claims 15 to 17, wherein:

19. The PSS series for PSS is [0014] 19. A client device according to any one of claims 15 to 18, associated with

20. 20. The client device of claim 15, wherein the PSS is generated based on one of three PSS sequences for synchronization.

21. 21. The client device of claim 15, wherein the processing unit is configured to obtain an SSS sequence for synchronization by performing descrambling and a fast Walsh-Hadamard transform (FWHT) operation based on the SSS.

22. The processing unit performs the first cyclic shift m 0 and the second cyclic shift m 1 22. A client device according to any one of claims 15 to 21, configured to generate an SSS sequence based on: 【Request 23】 【Number 15】 is 3, [0016] 23. The client device of any one of claims 15 to 22, wherein: 【Request 24】 【Number 17】 is 336, [Equation 18] 24. The client device of claim 15, wherein:

25. 25. The client device of claim 15, wherein the SSS sequence for the SSS has a length L of 127.

26. A processing device for wireless communication, comprising: Obtain a primary synchronization signal (PSS) generated based on the PSS sequence and a secondary synchronization signal (SSS) generated based on the SSS sequence; a first cyclic shift m determined based on the received PSS and SSS; 0 and the second circular shift m 1 Based on the cell identification (ID) N ID a processor configured to determine The first cyclic shift m 0 and the second cyclic shift m 1 teeth, [Equation 19] Fulfilling where: g is an integer equal to or greater than 1, L' is 112, [Equation 20] and [Equation 21] That is, a processing device.

27. The SSS sequence for the SSS is the first cyclic shift m 0 and the first binary sequence corresponding to the second cyclic shift m 1 and a second binary sequence corresponding to said first binary sequence, said first binary sequence and said second binary sequence having the same length.

28. The generating polynomial of the first binary sequence is g 0 (x)=x 7 +x 4 +1, and the generator polynomial of the second binary sequence is g 1 (x)=x 7 +x+1.

29. The processor calculates the first cyclic shift m 0 and the second cyclic shift m 1 and determining the cell ID N ID the first cyclic shift m 0 and the second cyclic shift m 1 configured to determine from [Equation 22] 29. The processing device according to any one of claims 26 to 28, wherein

30. The PSS sequence for the PSS is: [Equation 23] 30. The processing device according to any one of claims 26 to 29, associated with

31. 31. The processing device according to any one of claims 26 to 30, wherein the PSS is generated based on one of three PSS sequences for synchronization.

32. 32. The processing device of claim 26, wherein the processor is configured to obtain an SSS sequence for synchronization by performing descrambling and a Fast Walsh-Hadamard Transform (FWHT) operation based on the SSS.

33. The processor calculates the first cyclic shift m 0 and the second cyclic shift m 1 33. The processing device of any one of claims 26 to 32, configured to generate an SSS sequence based on: 【Request 34】 【Number 24】 is 3, [Equation 25] 34. The processing device according to any one of claims 26 to 33, wherein: 【Request 35】 【Number 26】 is 336, [0000] 35. The processing device according to any one of claims 26 to 34, wherein:

36. 36. The processing device according to any one of claims 26 to 35, wherein the SSS sequence for the SSS has a length L of 127.

37. receiving a communication signal including a primary synchronization signal (PSS) and a secondary synchronization signal (SSS); a first cyclic shift m determined based on the received PSS and SSS; 0 and the second circular shift m 1 Based on the cell identification (ID) N ID and determining The first cyclic shift m 0 and the second cyclic shift m 1 teeth, [0000] Fulfilling where: g is an integer equal to or greater than 1, L' is 112, [0000] and [Equation 30] A wireless communication method.

38. The SSS sequence for the SSS is the first cyclic shift m 0 and the first binary sequence corresponding to the second cyclic shift m 1 and a second binary sequence corresponding to said first binary sequence, said first binary sequence and said second binary sequence having the same length.

39. The generating polynomial of the first binary sequence is g 0 (x)=x 7 +x 4 +1, and the generator polynomial of the second binary sequence is g 1 (x)=x 7 39. The method of claim 38, wherein +x+1.

40. First circular shift m 0 and the second circular shift m 1 Based on the cell identification (ID) N ID The step of determining said cell ID N ID the first cyclic shift m associated with 0 and the second cyclic shift m 1 and determining the cell ID N ID the first cyclic shift m 0 and the second cyclic shift m 1 determining from [Equation 31] 40. The method of any one of claims 37 to 39, wherein

41. The PSS series for PSS is [Equation 32] 41. The method of any one of claims 37 to 40, wherein the method is associated with

42. 42. The method of claim 37, wherein the PSS is generated based on one of three PSS sequences for synchronization.

43. 43. The method of claim 37, further comprising the step of obtaining an SSS sequence for synchronization by descrambling and performing a Fast Walsh-Hadamard Transform (FWHT) operation based on the SSS.

44. The first cyclic shift m 0 and the second cyclic shift m 1 44. The method of any one of claims 37 to 43, further comprising generating an SSS sequence based on: 【Request 45】 【Number 33】 is 3, [Equation 34] 45. The method of any one of claims 37 to 44, wherein 【Request 46】 【Number 35】 is 336, [Equation 36] 46. The method of any one of claims 37 to 45, wherein

47. 47. The method of claim 37, wherein the SSS sequence for the SSS has a length L of 127.

48. 48. A computer readable medium containing a computer program which, when executed by a computer, causes the computer to perform the method of any one of claims 1 to 12 and 37 to 47.

49. A communication system comprising a network node according to claim 14 and a client device according to any one of claims 15 to 25.

50. A processing device (100) for generating a secondary synchronization signal (SSS) sequence to be used together with a primary synchronization signal (PSS) sequence for synchronization, comprising: The processing unit (100) performs a first cyclic shift m 0 and the second circular shift m 1 , at least cell ID N ID and configured to determine the first cyclic shift m 0 and the second cyclic shift m 1 At least one of the above is an index of the primary synchronization signal (PSS) sequence. [Equation 37] and the PSS sequence is associated with the PSS sequence by being determined based on the PSS sequence. The processing unit (100) performs a first cyclic shift m 0 The first binary sequence is cyclically shifted by m 1 and a second binary sequence circularly shifted by a factor of 0.001, wherein the processing device (100) is configured to generate the secondary synchronization signal (SSS) sequence based on a modulo-2 sum of a primary synchronization signal (PSS) sequence and a second binary sequence circularly shifted by a factor of 0.001, such that if two secondary synchronization signal (SSS) sequences generated in association with a primary synchronization signal (PSS) sequence are circularly shifted versions of each other, the two generated secondary synchronization signal (SSS) sequences are non-sequentially shifted versions of each other.

51. The first and second binary sequences are one in a group, and the group is m-sequence, and m-sequences such that the generated secondary synchronization signal (SSS) sequence belongs to a set of Gold sequences It consists of 51. The processing device (100) of claim 50.

52. The number of primary synchronization signal (PSS) sequences that can be used for synchronization is one primary synchronization signal (PSS) sequence, Two or more Primary Synchronization Signal (PSS) sequences, and Three primary synchronization signal (PSS) sequences 52. The processing device (100) of claim 50 or 51, which is one in the group consisting of:

53. 53. The processing device (100) of any one of claims 50 to 52, wherein the length L of the generated secondary synchronization signal (SSS) sequence is 127, where L=127.

54. The processing unit (100) selects at least one cell ID N according to one or more of the groups. ID the first cyclic shift m associated with 0 and the second cyclic shift m 1 wherein the group is further configured to determine The first cyclic shift m 0 and the second cyclic shift m 1 and is equal to m 0 =m 1 , The first cyclic shift m 0 and the second cyclic shift m 1 and are different from each other, m 0 ≠m 1 , The first cyclic shift m 0 is the second cyclic shift m 1 greater than, m 0 >m 1 , The first cyclic shift m 0 is the second cyclic shift m 1 Less than, m 0 <m 1 , Two circular shift pairs (m 0 ,m 1 ) and (m 0 ',m 1 ') but m 0 '=m 0 +1 and m 1 '=m 1 +1, or Two circular shift pairs (m 0 ,m 1 ) and (m 0 ',m 1 ') but m 0 '=m 0 +1 and m 1 '=m 1 +1, and the first cyclic shift m 0 is the second cyclic shift m 1 greater than m 0 >m 1 , Two circular shift pairs (m 0 ,m 1 ) and (m 0 ',m 1 ') but m 0 '=m 0 +1 and m 1 '=m 1 +1, and the first cyclic shift m 0 is the second cyclic shift m 1 smaller than m 0 <m 1 , m 0 '=m 0 +1 and m 1 '=m 1 +1, two pairs of circular shifts (m 0 ,m 1 ) and (m 0 ',m 1 ') are separate primary synchronization signal (PSS) sequence indexes [Equation 38] is associated with m 0 '=m 0 +1 and m 1 '=m 1 +1, two pairs of circular shifts (m 0 ,m 1 ) and (m 0 ',m 1 ') are separate primary synchronization signal (PSS) sequence indexes [Number 39] and the first cyclic shift m 0 is the second cyclic shift m 1 greater than m 0 >m 1 , and m 0 '=m 0 +1 and m 1 '=m 1 +1, two pairs of circular shifts (m 0 ,m 1 ) and (m 0 ',m 1 ') are separate primary synchronization signal (PSS) sequence indexes [Equation 40] and the first cyclic shift m 0 is the second cyclic shift m 1 smaller than m 0 <m 1 , It consists of 54. A processing device (100) according to any one of claims 50 to 53.

55. The processing unit (100) performs the first cyclic shift m 0 and the second cyclic shift m 1 of, [Equation 41] [0.001] and further configured to determine: where: g is an integer greater than 1, L' is a positive integer equal to or less than the length L of the secondary synchronization signal (SSS) sequence, [Equation 43] is an index of the secondary synchronization signal (SSS) sequence, [Equation 44] [Equation 45] is the index of the primary synchronization signal (PSS) sequence, [Equation 46] [Equation 47] is the floor function, mod is the modulus operation, 55. A processing device (100) according to any one of claims 50 to 54.

56. The processing unit (100) performs the first cyclic shift m 0 and the second cyclic shift m 1 of, [Number 48] and further configured to determine: where: g is an integer greater than 1, L' is a positive integer equal to or less than the length L of the secondary synchronization signal (SSS) sequence, [Number 49] is an index of the secondary synchronization signal (SSS) sequence, [Number 50] [0.51] is the index of the primary synchronization signal (PSS) sequence, [Number 52] [Number 53] is the floor function, mod is the modulus operation, 56. A processing device (100) according to any one of claims 50 to 55.

57. The processing unit (100) performs the first cyclic shift m 0 and the second cyclic shift m 1 of, [Number 54] and further configured to determine: where: g is an integer equal to or greater than 1, L' is a positive integer equal to or less than the length L of the secondary synchronization signal (SSS) sequence, [Number 55] is an index of the secondary synchronization signal (SSS) sequence, [Number 56] [Number 57] is the index of the primary synchronization signal (PSS) sequence, [Number 58] [Number 59] is the floor function, mod is the remainder operation, 57. A processing device (100) according to any one of claims 50 to 56.

58. The processing unit (100) performs the first cyclic shift m 0 and the second cyclic shift m 1 of, [Number 60] and further configured to determine: where: g is an integer equal to or greater than 1, L' is a positive integer equal to or less than the length L of the secondary synchronization signal (SSS) sequence, [Number 61] is an index of the secondary synchronization signal (SSS) sequence, [Number 62] [Number 63] is the index of the primary synchronization signal (PSS) sequence, [Number 64] [Number 65] is the floor function, mod is the modulus operation, 58. A processing device (100) according to any one of claims 50 to 57.

59. A processing device (100) according to any one of claims 50 to 58, configured to generate a secondary synchronization signal (SSS) sequence; a transceiver (302) configured to transmit a synchronization signal based on a first synchronization signal (PSS) sequence and the second synchronization signal (SSS) sequence; A network node (300) is provided.

60. A processing device (100) according to any one of claims 50 to 58, configured to generate a secondary synchronization signal (SSS) sequence; a transceiver (502) configured to receive a secondary synchronization signal (SSS) by utilizing the generated secondary synchronization signal (SSS) sequence; a first cyclic shift m determined based on the received primary synchronization signal (PSS) and the received secondary synchronization signal (SSS); 0 and the second circular shift m 1 Based on cell ID N ID the processing device (100) further configured to determine A client device (500) equipped with the

61. 1. A method (200) for determining a secondary synchronization (SSS) sequence to be utilized in conjunction with a primary synchronization signal (PSS) sequence for synchronization, the method (200) comprising: First circular shift m 0 and the second circular shift m 1 , at least cell ID N ID determining (202) based on the first cyclic shift m 0 and the second cyclic shift m 1 At least one of the above is an index of the primary synchronization signal (PSS) sequence. [Number 66] and determining the PSS sequence based on the PSS sequence. First circular shift m 0 The first binary sequence is cyclically shifted by m 1 and (204) generating the secondary synchronization signal (SSS) sequence based on a modulo-2 sum of a first binary sequence and a second binary sequence cyclically shifted by a factor of 1, wherein if two secondary synchronization signal (SSS) sequences generated in association with a first synchronization signal (PSS) sequence are cyclically shifted versions of each other, then the two generated secondary synchronization signal (SSS) sequences are non-sequentially shifted versions of each other. Includes a method (200).

62. A method (400) for a network node (300), comprising: generating a secondary synchronization signal (SSS) sequence according to claim 61 (402); and transmitting (404) a synchronization signal based on the first synchronization signal (PSS) sequence and the second synchronization signal (SSS) sequence. A method (400) comprising:

63. A method (600) for a client device (500), comprising: generating a secondary synchronization signal (SSS) sequence according to claim 61 (602); receiving (604) a secondary synchronization signal (SSS) by utilizing the generated secondary synchronization signal (SSS) sequence; a first cyclic shift m determined based on the received primary synchronization signal (PSS) and the received secondary synchronization signal (SSS); 0 and the second circular shift m 1 Based on cell ID N ID and a step (606) of determining Includes a method (600).

64. 64. A computer program having a program code for performing the method according to any one of claims 1 to 12, 37 to 47 and 61 to 63, when the computer program runs on a computer.

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