Operational amplifier

Abstract

To provide an operational amplifier that can be used in high-voltage applications.SOLUTION: A first high breakdown voltage transistor Mhv1 has a source connected to a drain of a first transistor M1 and to a gate thereof, a first bias voltage Vbn2 is applied. A second high breakdown voltage transistor Mhv2 has a source connected to a drain of a second transistor M2 and to a gate thereof, the first bias voltage Vbn2 is applied. An assist circuit 240 includes a first current source CS1 that is connected to the drain of the first transistor M1 and outputs a current Ia1 in an enable state, and a second current source CS2 that is connected to the drain of the second transistor M2 and outputs a current Ia2 in an enable state. When an input voltage VIN1 generated at a first input terminal IN1 is in a predetermined voltage range, the assist circuit 240 sets the first current source CS1 and the second current source CS2 to the enable state.SELECTED DRAWING: Figure 4

Description

[Technical Field]

[0001] The present disclosure relates to operational amplifiers. [Background technology]

[0002] An operational amplifier (differential amplifier) is used to amplify the difference between two input voltages. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] Japanese Patent Application Publication No. 2019-96970

[0004] [overview] The present disclosure has been made in this context, and one exemplary purpose of an embodiment thereof is to provide an operational amplifier that can be used in high-voltage applications.

[0005] The present disclosure relates to an operational amplifier having an input stage and an output stage. The input stage includes a first input terminal, a second input terminal, an input differential pair including a first transistor of a first polarity whose gate is connected to the first input terminal, and a second transistor of the first polarity whose gate is connected to the second input terminal, a tail current source including a third transistor of the first polarity whose drain is connected to the input differential pair, a first high-voltage transistor of the first polarity whose source is connected to the drain of the first transistor and whose gate is applied with a first bias voltage, and a second transistor of the second polarity whose source is connected to the drain of the second transistor and whose gate is applied with a first bias voltage. The power supply includes an assist circuit including a second high-voltage transistor of a first polarity, an active load connected to the drain of the first high-voltage transistor and the drain of the second high-voltage transistor, a first current source connected to the drain of the first transistor and outputting a current in an enabled state, and a second current source connected to the drain of the second transistor and outputting a current in an enabled state, and which enables the first current source and the second current source when an input voltage generated at one of the first input terminal and the second input terminal falls within a predetermined voltage range.

[0006] Any combination of the above elements, or mutual substitution of elements or expressions between methods, devices, systems, etc., are also valid aspects of the present invention or the present disclosure. Furthermore, the description in this section (Means for Solving the Problems) does not explain all essential features of the present invention, and therefore, subcombinations of the described features may also constitute the present invention. [Brief explanation of the drawings]

[0007] [Figure 1] Figure 1 is a circuit diagram of an operational amplifier. [Figure 2] FIG. 2 is a circuit diagram of an input stage according to the comparison technique. [Figure 3] FIG. 3 is a diagram showing the relationship between the input voltage VIN and the drain voltage Vd1 of the first transistor M1 in the input stage of FIG. [Figure 4]FIG. 4 is a circuit diagram of an input stage according to the embodiment. [Figure 5] FIG. 5 is a circuit diagram of an input stage according to the first embodiment. [Figure 6] FIG. 6 is a diagram showing the relationship between the input voltage VIN and the drain voltage Vd1 of the first transistor M1 in the input stage of FIG. 5 (Example 1). [Figure 7] FIG. 7 is a diagram showing the relationship between several currents (Ia1, Ia2, Ic3, Ictrl, Itail) and the input voltage VIN in the input stage of FIG. 5 (Example 1). [Figure 8] FIG. 8 is a circuit diagram of an assist circuit according to the second embodiment. [Figure 9] FIG. 9 is a circuit diagram of an assist circuit according to the third embodiment. [Figure 10] FIG. 10 is a circuit diagram of an assist circuit according to the fourth embodiment. [Figure 11] FIG. 11 is a circuit diagram of an input stage according to the fifth embodiment.

[0008] [Detailed explanation] (Outline of the embodiment) A summary of some exemplary embodiments of the present disclosure is provided. This summary is intended to provide a simplified overview of some concepts of one or more embodiments in order to provide a basic understanding of the embodiments as a prelude to the more detailed description that follows. It is not intended to limit the scope of the invention or disclosure. This summary is not an exhaustive overview of all possible embodiments, and is not intended to identify key elements of all embodiments or to delineate the scope of some or all aspects. For convenience, the term "one embodiment" may refer to one embodiment (example or variant) or multiple embodiments (examples or variants) disclosed herein.

[0009] An operational amplifier according to one embodiment has an input stage and an output stage. The input stage includes a first input terminal, a second input terminal, an input differential pair including a first transistor of a first polarity whose gate is connected to the first input terminal and a second transistor of the first polarity whose gate is connected to the second input terminal, a tail current source including a third transistor of the first polarity whose drain is connected to the input differential pair, a first high-voltage transistor of the first polarity whose source is connected to the drain of the first transistor and whose gate is applied with a first bias voltage, and a second transistor of the second polarity whose source is connected to the drain of the second transistor and whose gate is applied with the first bias voltage. The power supply includes an assist circuit including a second high-voltage transistor of a first polarity, an active load connected to the drain of the first high-voltage transistor and the drain of the second high-voltage transistor, a first current source connected to the drain of the first transistor and outputting a current in an enabled state, and a second current source connected to the drain of the second transistor and outputting a current in an enabled state, and which enables the first current source and the second current source when an input voltage generated at one of the first input terminal and the second input terminal falls within a predetermined voltage range.

[0010] According to this embodiment, when the input differential pair is cut off, an assist current flows through the assist circuit, keeping the first high-voltage transistor and the second high-voltage transistor in the saturation region, thereby preventing a high voltage from being applied to the input differential pair or the tail current source.

[0011] In one embodiment, the assist circuit includes: a third current source; a third high-voltage transistor of a second polarity having a source connected to the third current source and a gate to which a second bias voltage is applied; a first current mirror circuit having an input node connected to the drain of the third high-voltage transistor, a first output node connected to the drain of the first transistor, and a second output node connected to the drain of the second transistor; and a voltage detection circuit connected to the input node of the first current mirror circuit and generating a control current such that the input current of the first current mirror circuit is reduced when the input voltage is outside a predetermined voltage range and is increased when the input voltage is within the predetermined voltage range, and the first current mirror circuit may function as both the first current source and the second current source.

[0012] In one embodiment, the voltage detection circuit includes a fourth current source, a fourth high-voltage transistor of a second polarity having a source connected to the fourth current source and a gate to which a second bias voltage is applied, a fifth high-voltage transistor of a first polarity having a drain connected to the drain of the fourth high-voltage transistor and a gate connected to one of the first input terminal and the second input terminal, and a second current mirror circuit having an input node connected to the source of the fifth high-voltage transistor and an output node connected to an input node of the first current mirror circuit, and an output current of the second current mirror circuit may be the control current.

[0013] In one embodiment, the voltage detection circuit may further include a sixth high-voltage transistor of the first polarity, having a drain connected to the drain of the fourth high-voltage transistor, a gate connected to the second input terminal, and a source connected to the input node of the second current mirror circuit.

[0014] In one embodiment, the voltage detection circuit includes: a fourth current source; a fourth high-voltage transistor of a second polarity, the source of which is connected to the fourth current source and the gate of which is applied with a second bias voltage; a seventh high-voltage transistor of a first polarity, the drain of which is connected to the drain of the fourth high-voltage transistor and the gate of which is applied with a third bias voltage; a fourth transistor of the first polarity, the drain of which is connected to the drain of the seventh high-voltage transistor and the gate of which is connected to one of the first input terminal and the second input terminal; and a second current mirror circuit, the input node of which is connected to the source of the fourth transistor and the output node of which is connected to the input node of the first current mirror circuit, wherein the output current of the second current mirror circuit may be the control current.

[0015] In one embodiment, the voltage detection circuit may further include a fifth transistor of the first polarity, having a drain connected to the drain of the fourth high-voltage transistor, a gate connected to the other of the first input terminal and the second input terminal, and a source connected to the input node of the second current mirror circuit.

[0016] In one embodiment, the voltage detection circuit may include a voltage comparator that compares the voltage at one of the first input terminal and the second input terminal with a threshold voltage.

[0017] In one embodiment, the power supply may further include a bias circuit that generates a first bias voltage. The bias circuit may include a fifth current source, an eighth high-voltage transistor of a second polarity having a source connected to the fifth current source and a gate to which a second bias voltage is applied, and a constant-voltage source including a plurality of constant-voltage elements connected in series and connected to the drain of the eighth high-voltage transistor, wherein the voltage drops across the plurality of constant-voltage elements may be the first bias voltage.

[0018] In one embodiment, the operational amplifier may be monolithically integrated on a single semiconductor substrate. "Monolithically integrated" includes cases where all of the circuit components are formed on a semiconductor substrate, and cases where the main circuit components are monolithically integrated, and some resistors, capacitors, etc. for adjusting the circuit constants may be provided outside the semiconductor substrate.

[0019] (Embodiment) Preferred embodiments will be described below with reference to the drawings. The same or equivalent components, parts, and processes shown in each drawing will be given the same reference numerals, and redundant explanations will be omitted as appropriate. Furthermore, the embodiments are examples and do not limit the disclosure and invention, and all features and combinations thereof described in the embodiments are not necessarily essential to the disclosure and invention.

[0020] In this specification, "a state in which component A is connected to component B" includes not only a case in which component A and component B are directly physically connected to each other, but also a case in which component A and component B are indirectly connected to each other via other components that do not substantially affect the electrical connection between them or that do not impair the function or effect achieved by their connection.

[0021] Similarly, "a state in which component C is connected (provided) between component A and component B" includes not only a case in which component A and component C, or component B and component C, are directly connected, but also a case in which they are indirectly connected via other components that do not substantially affect the electrical connection state between them or that do not impair the function or effect achieved by their combination.

[0022] In addition, in this specification, symbols attached to electrical signals such as voltage signals and current signals, or circuit elements such as resistors, capacitors, and inductors, represent the respective voltage values, current values, or circuit constants (resistance values, capacitance values, inductances) as necessary.

[0023] First, the basic configuration of an operational amplifier will be described with reference to FIG.

[0024] 1 is a circuit diagram of an operational amplifier 100. The operational amplifier 100 receives differential input signals Vp and Vn at differential input terminals INP and INN, and outputs an amplified output signal from an output terminal OUT. The operational amplifier 100 may be a voltage output type or a current output type transconductance amplifier. A power supply voltage V DD is supplied to the ground terminal GND, and the ground terminal GND is grounded.

[0025] The operational amplifier 100 includes an input stage 200 and an output stage 300. The input stage 200 may include a differential input stage that amplifies the potential difference between differential input signals Vp and Vn to generate a differential current, and a gain stage that further amplifies the differential current to generate an intermediate signal Vm.

[0026] The output stage 300 generates a signal corresponding to the intermediate signal Vm at the output terminal OUT. The output stage 300 functions as a buffer to prevent the operational amplifier 100 from being affected by a load (not shown) connected to the output terminal OUT.

[0027] The inventors of the present invention have considered increasing the withstand voltage of the input stage 200 and have come to recognize the following problem. Figure 2 is a circuit diagram of an input stage 200R according to a comparative technique. The input stage 200R operates using the voltage VDD of the power supply line 202 and the voltage VSS of the ground line 204 as rails.

[0028] The input stage 200R includes an input differential pair 210, a tail current source 220, an active load 230, a first high-voltage transistor Mhv1, and a second high-voltage transistor Mhv2. The semiconductor integrated circuit according to the present disclosure is configured by combining high-voltage transistors with a relatively high drain-source breakdown voltage and normal-voltage transistors with a relatively low drain-source breakdown voltage. The high-voltage transistors have a breakdown voltage of, for example, several tens of volts, and the normal-voltage transistors have a breakdown voltage of several volts.

[0029] The input differential pair 210 includes a first transistor M1 and a second transistor M2, which are N-channel MOSFETs. The first transistor M1 and the second transistor M2 are normal voltage transistors, and their gates are connected to a first input terminal IN1 and a second input terminal IN2, respectively. The first input terminal IN1 is one of the differential inputs INP and INN of the operational amplifier 100, and the second input terminal IN2 is the other of the differential inputs INP and INN. The tail current source 220 includes a third transistor M3, and a bias voltage Vbn1 is applied to its gate so that a predetermined amount of tail current Itail flows.

[0030] A differential current corresponding to the potential difference between the input voltages VIN1 and VIN2 flows through the input differential pair 210. The differential currents Id1 and Id2 are supplied to the active load 230.

[0031] To increase the withstand voltage of the input stage 200R, a first high-voltage transistor Mhv1 and a second high-voltage transistor Mhv2 are added between the input differential pair 210 and the output stage 300. The first high-voltage transistor Mhv1 and the second high-voltage transistor Mhv2 are N-channel MOSFETs, and a predetermined voltage Vbn2 is supplied to their gates. The first high-voltage transistor Mhv1 and the second high-voltage transistor Mhv2 function as clamp elements that clamp the source voltages (i.e., the drain voltages of the first transistor M1 and the second transistor M2) so that they do not exceed Vlim = Vbn2 - Vgs. This limits the drain-source voltages of the first transistor M1 and the second transistor M2, thereby protecting the first transistor M1 and the second transistor M2.

[0032] The active load 230 is a folded cascode amplifier circuit and includes normal voltage transistors M11 to M16 and high voltage transistors Mhv11, Mhv12, Mhv13, and Mhv14. The high voltage transistors Mhv11 and Mhv12 clamp the drain voltage of the transistors M13 and M14 so that it does not exceed a clamp level determined by Vbn1-Vgs. The high voltage transistors Mhv13 and Mhv14 clamp the drain voltage of the transistors M15 and M16 so that it does not exceed a clamp level determined by Vbp+Vgs. The output terminal OUT of the active load 230 is connected to the output stage 300 located downstream. The active load 230 may be a current mirror circuit.

[0033] The above is the configuration of input stage 200R according to the comparative technique. The present inventors have studied input stage 200R in Fig. 2 and have come to recognize the following problem.

[0034] The operating condition for the VSS rail side of the input differential pair 210 is that the gate-source voltage Vgs1 (Vgs2) of the first transistor M1 (and the second transistor M2) and the drain-source voltage Vds3(sat) of the third transistor M3 are ensured, and the following relational expression must be satisfied: VIN>Vgs1+Vds3(sat)

[0035] FIG. 3 shows the relationship between the input voltage V and the drain voltage Vd1 of the first transistor M1 in the input stage 200R of FIG. 2. In this example, Vgs1 + Vds(sat) is approximately 0.4 V. As the input voltage V decreases, the drain-source voltage Vds3 of the third transistor M3 becomes smaller than the pinch-off voltage Vds3(sat), and the tail current Itail decreases. When the tail current Itail reaches zero, the input differential pair 210 is cut off. At this time, the first high-voltage transistor Mhv1 leaves the saturation region, enters the linear region, and enters the subthreshold region, entering a high-impedance state. As a result, the high voltage on the drain side of the first high-voltage transistor Mhv1 is applied to the drain of the first transistor M1. Because the input differential pair 210 and the tail current source 220 are composed of normal-voltage transistors, applying a high voltage to them reduces reliability. A similar problem occurs on the second transistor M2 side.

[0036] Next, the input stage 200 according to the embodiment will be described.

[0037] 4 is a circuit diagram of an input stage 200 according to an embodiment. The input stage 200 includes an input differential pair 210, a tail current source 220, an active load 230, a first high-voltage transistor Mhv1, a second high-voltage transistor Mhv2, and an assist circuit 240. That is, the input stage 200 according to the embodiment further includes the assist circuit 240 in addition to the input stage 200R according to the comparative technology. Components other than the assist circuit 240 have already been described in relation to the input stage 200R, so repeated description will be omitted.

[0038] The assist circuit 240 includes a first current source CS1, a second current source CS2, and a voltage detection circuit 250. The first current source CS1 is connected to the drain of the first transistor M1 and outputs (sinks) an assist current Ia1 in an enabled state. The second current source CS2 is connected to the drain of the second transistor M2 and outputs (sinks) an assist current Ia2 in an enabled state. The assist circuit 240 is configured to enable the first current source CS1 and the second current source CS2 when the input voltage VIN generated at one of the first input terminal IN1 and the second input terminal IN2 falls within a predetermined voltage range.

[0039] The voltage detection circuit 250 monitors the input voltage VIN at one of the first input terminal IN1 and the second input terminal IN2 and switches the enabled and disabled states of the first current source CS1 and the second current source CS2. In this example, when the input voltage VIN falls within the voltage range in which the input differential pair 210 is cut off, that is, when VIN < Vgs1 + Vds3(sat), the voltage detection circuit 250 enables the first current source CS1 and the second current source CS2.

[0040] The above is the configuration of the input stage 200. Next, its operation will be described.

[0041] As described above, when VIN < Vgs1 + Vds3(sat), the tail current Itail becomes zero and the input differential pair 210 is cut off. In the comparative technique, at this time, the sources of the first high breakdown voltage transistor Mhv1 and the second high breakdown voltage transistor Mhv2 become a high impedance state and a high voltage is generated. On the other hand, in the embodiment, when VIN < Vgs1 + Vds3(sat), the first current source CS1 and the second current source CS2 are enabled, so that instead of the tail current Itail, the assist currents Ia1 and Ia2 flow through the first high breakdown voltage transistor Mhv1 and the second high breakdown voltage transistor Mhv2, and the first high breakdown voltage transistor Mhv1 and the second high breakdown voltage transistor Mhv2 can continue to operate in the saturation region. Thereby, it is possible to prevent a high voltage on the drain side of the first high breakdown voltage transistor Mhv1 and the second high breakdown voltage transistor Mhv2 from being generated on the source side of the first high breakdown voltage transistor Mhv1 and the second high breakdown voltage transistor Mhv2, and to protect the input differential pair 210 and the tail current source 220.

[0042] The present disclosure is understood as the circuit diagram of FIG. 4, or extends to various apparatuses and methods derived from the above description, and is not limited to a specific configuration. Hereinafter, in order to help understand the essence and operation of the present disclosure and the present invention, and to clarify them, rather than narrowing the scope of the present disclosure, more specific configuration examples and embodiments will be described.

[0043] (Example 1) FIG. 5 is a circuit diagram of an input stage 200A according to Example 1. In this example, the active load 230 is a folded cascode amplifier circuit, and includes transistors M11 to M16 and high breakdown voltage transistors Mhv11 to Mhv14.

[0044] The bias voltage source 260 generates a bias voltage Vbn2 for the first high-voltage transistor Mhv1 and the second high-voltage transistor Mhv2. The bias voltage source 260 includes a fifth current source CS5, an eighth high-voltage transistor Mhv8, and a constant voltage source 262. The fifth current source CS5 includes a P-channel MOSFET transistor M18 biased to pass a constant current Ic5. The constant voltage source 262 generates a constant voltage Vbn2 according to the constant current Ic5. The eighth high-voltage transistor Mhv8 is a P-channel MOSFET and is connected between the drain of the transistor M18 and the constant voltage source 262. A bias voltage Vbp is applied to the gate of the eighth high-voltage transistor Mhv8. The eighth high-voltage transistor Mhv8 clamps the drain voltage of the transistor M18 so that it does not fall below a clamp level Vbp+Vgs. The constant voltage source 262 includes multiple constant voltage elements connected in series. The constant voltage element can be configured as a Zener diode, a diode, a transistor, a resistor, or a combination of these.

[0045] The assist circuit 240A includes a first current mirror circuit CM1, a third high-voltage transistor Mhv3, a third current source CS3, and a voltage detection circuit 250A.

[0046] The third current source CS3 includes a transistor M17 which is a P-channel MOSFET biased so that a constant current Ic3 flows. The first current mirror circuit CM1 includes transistors M21, M22, M23 which are N-channel MOSFETs with normal breakdown voltage and has two output nodes. The first output (the drain of M22) of the first current mirror circuit CM1 is connected to the drain of the first transistor M1, and the second output (the drain of M23) is connected to the drain of the second transistor M2. The first current mirror circuit CM1 copies and folds back the constant current Ic3 and outputs assist currents Ia1, Ia2. The third high breakdown voltage transistor Mhv3 is a P-channel MOSFET and is connected between the drain of the transistor M17 and the input node (the drain of M21) of the first current mirror circuit CM1. A bias voltage Vbp is applied to the gate of the third high breakdown voltage transistor Mhv3. The voltage at the drain of the transistor M17 is clamped by the third high breakdown voltage transistor Mhv3 so as not to fall below the clamp level Vbp + Vgs.

[0047] The voltage detection circuit 250A is connected to the input node (the drain of M21) of the first current mirror circuit CM1 and generates a control current Ictrl such that the input current I21 of the first current mirror circuit CM1 becomes small when the input voltage VIN is outside a predetermined voltage range (VIN > Vgs1 + Vds3(sat)). Specifically, when VIN > Vgs1 + Vds3(sat), a control current Ictrl(dis) that satisfies the following relationship is generated. Ictrl(dis) > Ic3 When Ictrl(dis) flows, I21 = 0, and the assist currents Ia'1, Ia' are not flowing. That is, the first current source CS1 and the second current source CS2 are in a disabled state.

[0048] The voltage detection circuit 250A generates a control current Ictrl(en) such that the input current I21 of the first current mirror circuit CM1 becomes large when the input voltage VIN is within a predetermined voltage range (VIN < Vgs1 + Vds3(sat)). Ictrl(en) < Ic3 For example, Ictrl(en) may be 0. When Ictrl(dis) is 0, I21=Ic3, and assist currents Ia1 and Ia2 proportional to the constant current Ic3 are generated. In other words, the first current source CS1 and the second current source CS2 are enabled.

[0049] The configuration of the voltage detection circuit 250A is not particularly limited, but may include, for example, a fourth current source CS4, a fourth high-voltage transistor Mhv4, a fifth high-voltage transistor Mhv5, and a second current mirror circuit CM2. The fourth current source CS4 includes a transistor M16, which is a P-channel MOSFET biased so that a constant current Ic4 flows. A fourth high-voltage transistor Mhv4 is provided to protect the transistor M16. The fourth high-voltage transistor Mhv4 is a P-channel MOSFET, and its source is connected to the fourth current source CS4 and its gate is applied with a second bias voltage Vbp.

[0050] The fifth high-voltage transistor Mhv5 is an N-channel MOSFET, with its drain connected to the drain of the fourth high-voltage transistor Mhv4 and its gate connected to one of the first input terminal IN1 and the second input terminal IN2 (IN1 in this embodiment).

[0051] The second current mirror circuit CM2 includes transistors M24 and M25, which are normal voltage N-channel MOSFETs. The input node (the drain of M24) of the second current mirror circuit CM2 is connected to the source of the fifth high voltage transistor Mhv5, and the output node (the drain of M25) is connected to the input node of the first current mirror circuit CM1.

[0052] Next, the operation of the assist circuit 240A will be described.

[0053] When the input voltage VIN is higher than Vgs5 + Vgs24, the fifth high breakdown voltage transistor Mhv5 conducts. At this time, the constant current Ic4 is input to the second current mirror circuit CM2, a control current Ictrl(dis) flows, and the first current source CS1 and the second current source CS2 are in the disabled state. Vgs5 is the gate-source voltage of the fifth high breakdown voltage transistor Mhv5, and Vgs24 is the gate-source voltage of the transistor M24.

[0054] When the input voltage VIN becomes lower than Vgs5 + Vgs24, the fifth high breakdown voltage transistor Mhv5 turns off. At this time, since the constant current Ic4 is no longer input to the second current mirror circuit CM2, the control current Ictrl(en) = 0, and the first current source CS1 and the second current source CS2 are in the enabled state.

[0055] Here, when comparing Vgs5 + Vgs24 with Vgs1 + Vds3(sat), the relationship Vgs5 + Vgs24 > Vgs1 + Vds3(sat) holds. Therefore, the voltage detection circuit 250A can enable the first current source CS1 and the second current source CS2 before the input differential pair 210 turns off.

[0056] FIG. 6 is a diagram showing the relationship between the input voltage VIN and the drain voltage Vd1 of the first transistor M1 in the input stage 200A of FIG. 5 (Example 1). In the comparative technique, when VIN < Vgs1 + Vds3(sat), the drain voltage Vd1 increased. However, in Example 1, even when VIN < Vgs1 + Vds3(sat), assist currents Ia1 and Ia2 flow, so the increase in the drain voltage Vd1 can be suppressed.

[0057] FIG. 7 is a diagram showing the relationship between several currents (Ia1, Ia2, Ic3, Ictrl, Itail) and the input voltage VIN in the input stage 200A of FIG. 5 (Example 1). Since the assist currents Ia1 and Ic2 are zero when the input voltage VIN is within the common-phase input voltage range, the assist circuit 240A does not affect the operation of the operational amplifier 100 during normal operation and does not cause an undesirable input offset voltage or the like.

[0058] (Example 2) FIG. 8 is a circuit diagram of the assist circuit 240B according to Example 2. The voltage detection circuit 250B includes a sixth high breakdown voltage transistor Mhv6 in addition to the assist circuit 240A of FIG. 5. The gate of the sixth high breakdown voltage transistor Mhv6 is connected to the second input terminal IN2.

[0059] Considering the general use of an operational amplifier, since an imaginary short is established in the steady state, the input voltages VIN of the first input terminal IN1 and the second input terminal IN2 are equal. Therefore, in some applications, the voltage detection circuit 250A of FIG. 5 that monitors only the voltages of the first input terminal IN1 and the second input terminal IN2 functions sufficiently.

[0060] On the other hand, in the transient state, a situation may occur where the voltage VIN1 of the first input terminal IN1 is different from the voltage VIN2 of the second input terminal IN2. In the voltage detection circuit 250B of FIG. 8, even in a situation where the voltage VIN2 of the second input terminal IN2 satisfies VIN2 < Vgs6 + Vgs24, the first current source CS1 and the second current source CS2 can be enabled.

[0061] (Example 3) FIG. 9 is a circuit diagram of the assist circuit 240C according to Example 3. The voltage detection circuit 250C includes a fourth current source CS4, a fourth high breakdown voltage transistor Mhv4, a seventh high breakdown voltage transistor Mhv7, a fourth transistor M4, a fifth transistor M5, and a second current mirror circuit CM2.

[0062] The fourth transistor M4 and the fifth transistor M5 are normal breakdown voltage N-channel MOSFETs. The gate of the fourth transistor M4 is connected to the first input terminal IN1, and the gate of the fifth transistor M5 is connected to the second input terminal IN2. The seventh high breakdown voltage transistor Mhv7 is an N-channel MOSFET and is provided to protect the normal breakdown voltage fourth transistor M4 and fifth transistor M5.

[0063] This voltage detection circuit 250C can enable the first current source CS1 and the second current source CS2 when VIN1 < Vgs4 + Vgs24 or when VIN2 < Vgs5 + Vgs24. In FIG. 9, one of the fourth transistor M4 and the fifth transistor M5 may be omitted.

[0064] (Embodiment 4) FIG. 10 is a circuit diagram of an assist circuit 240D according to Embodiment 4. The voltage detection circuit 250D includes a voltage comparator COMP1 and a reference voltage source 252. The reference voltage source 252 generates a threshold voltage Vth. The voltage comparator COMP1 compares the voltage VIN of one of the first input terminal IN1 and the second input terminal IN2 with the threshold voltage Vth.

[0065] In this embodiment, the voltage comparator COMP1 includes transistors M31 to M36 which are normally-rated MOSFETs and a high-voltage transistor Mhv31. The voltage comparator COMP1 has an open-drain output format, and the drain of the output transistor M36 is connected to the input node of the first current mirror circuit CM1.

[0066] When VIN > Vth, the output transistor M36 is on, a control current Ictrl (> Ic3) flows, and the first current source CS1 and the second current source CS2 are in a disabled state. When VIN < Vth, the output transistor M36 turns off, the control current Ictrl = 0, and the first current source CS1 and the second current source CS2 are in an enabled state.

[0067] (Embodiment 5) In the previous descriptions, the case where the input differential pair 210 is an N-channel MOSFET has been described. However, the technology according to the present disclosure is also applicable to an operational amplifier 100 having a P-channel MOSFET input differential pair 210.

[0068] 11 is a circuit diagram of an input stage 200E according to a fifth embodiment. The input stage 200E has a configuration in which the top and bottom (power supply line VDD and ground line VSS) of the input stage 200 in FIG. 4 are inverted, and the P-channel is changed to an N-channel and the N-channel is changed to a P-channel. The first current source CS1 and the second current source CS2 of the assist circuit 240E generate (source) assist currents Ia1 and Ia2 in the enabled state.

[0069] The voltage detection circuit 250E enables the first current source CS1 and the second current source CS2 when the input voltages VIN1 and VIN2 are within a predetermined voltage range. Specifically, the voltage detection circuit 250E enables the first current source CS1 and the second current source CS2 when the input differential pair 210 is in a cutoff state, i.e., VIN>VDD-Vds3(sat)-Vgs1 When the following expression is satisfied, the first current source CS1 and the second current source CS2 are enabled.

[0070] Those skilled in the art will naturally understand how to configure the active load 230 and the assist circuit 240E in the input stage 200E of FIG. 11 based on the configurations described in the first to fourth embodiments.

[0071] The embodiments merely illustrate the principles and applications of the present invention, and many modifications and changes in arrangement are permitted to the embodiments as long as they do not deviate from the spirit of the present invention as defined in the claims.

[0072] (Addendum) The present specification discloses the following techniques.

[0073] (Item 1) 1. An operational amplifier having an input stage and an output stage, The input stage comprises: a first input terminal; a second input terminal; an input differential pair including a first transistor of a first polarity whose gate is connected to the first input terminal and a second transistor of a first polarity whose gate is connected to the second input terminal; a tail current source including a third transistor of a first polarity, the drain of which is connected to the input differential pair; a first high-voltage transistor of the first polarity, the source of which is connected to the drain of the first transistor and the gate of which is applied with a first bias voltage; a second high-voltage transistor of the first polarity, the source of which is connected to the drain of the second transistor and the gate of which is applied with the first bias voltage; an active load connected to the drain of the first high-voltage transistor and the drain of the second high-voltage transistor; an assist circuit including a first current source connected to the drain of the first transistor and outputting a current in an enabled state, and a second current source connected to the drain of the second transistor and outputting a current in an enabled state, the assist circuit enabling the first current source and the second current source when an input voltage generated at one of the first input terminal and the second input terminal falls within a predetermined voltage range; An operational amplifier comprising:

[0074] (Item 2) The assist circuit is a third current source; a third high-voltage transistor of a second polarity, the source of which is connected to the third current source and the gate of which is applied with a second bias voltage; a first current mirror circuit having an input node connected to the drain of the third high-voltage transistor, a first output node connected to the drain of the first transistor, and a second output node connected to the drain of the second transistor; a voltage detection circuit connected to the input node of the first current mirror circuit, the voltage detection circuit generating a control current such that the input current of the first current mirror circuit decreases when the input voltage is outside the predetermined voltage range, and increases when the input voltage is within the predetermined voltage range; 2. The operational amplifier of claim 1, wherein the first current mirror circuit functions as the first current source and the second current source.

[0075] (Item 3) The voltage detection circuit a fourth current source; a fourth high-voltage transistor of a second polarity, the source of which is connected to the fourth current source and the gate of which receives the second bias voltage; a fifth high-voltage transistor of the first polarity, the drain of which is connected to the drain of the fourth high-voltage transistor and the gate of which is connected to the one of the first input terminal and the second input terminal; a second current mirror circuit having an input node connected to the source of the fifth high-voltage transistor and an output node connected to the input node of the first current mirror circuit; 3. The operational amplifier according to item 2, comprising: an output current of the second current mirror circuit being the control current.

[0076] (Item 4) The voltage detection circuit 4. The operational amplifier according to item 3, further comprising a sixth high-voltage transistor of the first polarity, the sixth high-voltage transistor having a drain connected to the drain of the fourth high-voltage transistor, a gate connected to the second input terminal, and a source connected to the input node of the second current mirror circuit.

[0077] (Item 5) The voltage detection circuit a fourth current source; a fourth high-voltage transistor of a second polarity, the source of which is connected to the fourth current source and the gate of which receives the second bias voltage; a seventh high-voltage transistor of the first polarity, the drain of which is connected to the drain of the fourth high-voltage transistor and the gate of which is applied with a third bias voltage; a fourth transistor of the first polarity, the drain of which is connected to the drain of the seventh high-voltage transistor and the gate of which is connected to the one of the first input terminal and the second input terminal; a second current mirror circuit having an input node connected to the source of the fourth transistor and an output node connected to the input node of the first current mirror circuit; 3. The operational amplifier according to item 2, comprising: an output current of the second current mirror circuit being the control current.

[0078] (Item 6) The voltage detection circuit 6. The operational amplifier according to item 5, further comprising: a fifth transistor of the first polarity, the fifth transistor having a drain connected to the drain of the fourth high-voltage transistor, a gate connected to the other of the first input terminal and the second input terminal, and a source connected to the input node of the second current mirror circuit.

[0079] (Item 7) 3. The operational amplifier according to claim 2, wherein the voltage detection circuit includes a voltage comparator that compares the voltage of one of the first input terminal and the second input terminal with a threshold voltage.

[0080] (Item 8) further comprising a bias circuit for generating the first bias voltage; The bias circuit a fifth current source; an eighth high-voltage transistor of a second polarity, the source of which is connected to the fifth current source and the gate of which is applied with a second bias voltage; a constant voltage source including a plurality of constant voltage elements connected in series and connected to the drain of the eighth high-voltage transistor; 8. The operational amplifier according to any one of items 1 to 7, wherein the voltage drops of the plurality of constant voltage elements are the first bias voltage.

[0081] (Item 9) 9. The operational amplifier according to any one of items 1 to 8, which is monolithically integrated on a single semiconductor substrate. [Explanation of symbols]

[0082] 100 Op-Amps 200 input stages 300 output stage 202 Power Line 204 Ground Line Mhv1 First high voltage transistor Mhv2 Second high voltage transistor Mhv3 3rd high voltage transistor Mhv4 4th high voltage transistor Mhv5 5th high voltage transistor Mhv6 6th high voltage transistor Mhv7 7th high voltage transistor Mhv8 8th high voltage transistor M1 First transistor M2 Second transistor M3 Third transistor M4 4th transistor M5 Fifth transistor M6 6th transistor 210 Input differential pair 220 Tail Current Source 230 Active Load 240 Assist Circuit 250 Voltage detection circuit CS1 1st current source CS2 2nd current source CS3 3rd current source CS4 4th current source CM1 First current mirror circuit CM2 Second current mirror circuit 260 Bias Voltage Source

Claims

1. 1. An operational amplifier having an input stage and an output stage, The input stage comprises: a first input terminal; a second input terminal; an input differential pair including a first transistor of a first polarity whose gate is connected to the first input terminal and a second transistor of a first polarity whose gate is connected to the second input terminal; a tail current source including a third transistor of a first polarity, the drain of which is connected to the input differential pair; a first high voltage transistor of the first polarity, the source of which is connected to the drain of the first transistor and the gate of which is applied with a first bias voltage; a second high-voltage transistor of the first polarity, the source of which is connected to the drain of the second transistor and the gate of which is applied with the first bias voltage; an active load connected to the drain of the first high-voltage transistor and the drain of the second high-voltage transistor; an assist circuit including: a first current source connected to the drain of the first transistor and outputting a current in an enabled state; and a second current source connected to the drain of the second transistor and outputting a current in an enabled state, the assist circuit enabling the first current source and the second current source when an input voltage generated at one of the first input terminal and the second input terminal falls within a predetermined voltage range; An operational amplifier comprising:

2. The assist circuit is a third current source; a third high voltage transistor of a second polarity, the source of which is connected to the third current source and the gate of which is applied with a second bias voltage; a first current mirror circuit having an input node connected to the drain of the third high-voltage transistor, a first output node connected to the drain of the first transistor, and a second output node connected to the drain of the second transistor; a voltage detection circuit connected to the input node of the first current mirror circuit, the voltage detection circuit generating a control current such that the input current of the first current mirror circuit is reduced when the input voltage is outside the predetermined voltage range, and the input current of the first current mirror circuit is increased when the input voltage is within the predetermined voltage range; 2. The operational amplifier of claim 1, wherein the first current mirror circuit functions as the first current source and the second current source.

3. The voltage detection circuit a fourth current source; and a fourth high-voltage transistor of a second polarity, the source of which is connected to the fourth current source and the gate of which is applied with the second bias voltage; a fifth high-voltage transistor of the first polarity, the fifth high-voltage transistor having a drain connected to the drain of the fourth high-voltage transistor and a gate connected to one of the first input terminal and the second input terminal; a second current mirror circuit having an input node connected to the source of the fifth high-voltage transistor and an output node connected to the input node of the first current mirror circuit; 3. The operational amplifier of claim 2, wherein an output current of the second current mirror circuit is the control current.

4. The voltage detection circuit 4. The operational amplifier according to claim 3, further comprising a sixth high-voltage transistor of the first polarity, the sixth high-voltage transistor having a drain connected to the drain of the fourth high-voltage transistor, a gate connected to the second input terminal, and a source connected to the input node of the second current mirror circuit.

5. The voltage detection circuit a fourth current source; and a fourth high-voltage transistor of a second polarity, the source of which is connected to the fourth current source and the gate of which is applied with the second bias voltage; a seventh high-voltage transistor of the first polarity, the drain of which is connected to the drain of the fourth high-voltage transistor and the gate of which is applied with a third bias voltage; a fourth transistor of the first polarity, the drain of which is connected to the drain of the seventh high-voltage transistor and the gate of which is connected to one of the first input terminal and the second input terminal; a second current mirror circuit having an input node connected to the source of the fourth transistor and an output node connected to the input node of the first current mirror circuit; 3. The operational amplifier of claim 2, wherein an output current of the second current mirror circuit is the control current.

6. The voltage detection circuit 6. The operational amplifier according to claim 5, further comprising a fifth transistor of the first polarity, the fifth transistor having a drain connected to the drain of the fourth high-voltage transistor, a gate connected to the other of the first input terminal and the second input terminal, and a source connected to the input node of the second current mirror circuit.

7. 3. The operational amplifier according to claim 2, wherein the voltage detection circuit includes a voltage comparator that compares the voltage at one of the first input terminal and the second input terminal with a threshold voltage.

8. a bias circuit for generating the first bias voltage; The bias circuit a fifth current source; and an eighth high-voltage transistor of a second polarity, the source of which is connected to the fifth current source and the gate of which is applied with a second bias voltage; a constant voltage source including a plurality of constant voltage elements connected in series, the constant voltage source being connected to the drain of the eighth high-voltage transistor; 8. The operational amplifier according to claim 1, wherein the voltage drops of the plurality of constant voltage elements are the first bias voltage.

9. 8. The operational amplifier according to claim 1, which is monolithically integrated on a single semiconductor substrate.

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