Display device and display system

Abstract

To provide a display device and a display system that can improve the transmittance even if the pixel is increased in definition.SOLUTION: A display device includes an array substrate, a counter substrate, and a liquid crystal layer. The array substrate includes a signal line, a scan line, a common electrode overlapping with a plurality of pixel electrodes, and a light-blocking conductive layer in a lattice form. The conductive layer includes a frame part overlapping with the scan line and the signal line, and a divisional line part that divides pixels into a first section and a second section. The common electrode includes a first slit and a second slit for each pixel. The distance between a first side and a second side of the first slit is gradually smaller as getting closer to the second slit, and the distance between a third side and a fourth side of the second slit is gradually smaller as getting closer to the first slit. The divisional line part is disposed between the first side and the third side, and between the second side and the fourth side.SELECTED DRAWING: Figure 10

Description

[Technical Field]

[0001] The present disclosure relates to a display device and a display system. [Background technology]

[0002] Patent Documents 1 and 2 disclose display devices that improve response speed and transmittance. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] Japanese Patent Application Laid-Open No. 2014-232136 [Patent Document 2] Japanese Patent Application Publication No. 2019-113584 Summary of the Invention [Problem to be solved by the invention]

[0004] In Patent Document 1, as pixel resolution increases, it becomes difficult to form comb-shaped electrodes. In Patent Document 2, multiple liquid crystal domains and multiple dark regions where there is almost no change in the alignment of liquid crystal molecules are formed. In Patent Document 2, the slits are contained within openings surrounded by signal lines and scanning lines. However, in Patent Document 2, as pixel resolution increases, the slits may overlap the signal lines or scanning lines, resulting in a decrease in transmittance.

[0005] An object of the present disclosure is to provide a display device and a display system that improve transmittance even when pixels have higher resolution. [Means for solving the problem]

[0006] A display device according to one embodiment includes an array substrate, an opposing substrate opposed to the array substrate, and a liquid crystal layer containing liquid crystal molecules between the array substrate and the opposing substrate, wherein the array substrate includes a plurality of signal lines spaced apart in a first direction, a plurality of scanning lines spaced apart in a second direction, a plurality of pixel electrodes arranged at each opening of a pixel surrounded by two adjacent signal lines and two adjacent scanning lines, a plurality of semiconductors arranged at each pixel, a common electrode overlapping the plurality of pixel electrodes via an insulating film, and a lattice-shaped, light-shielding conductive layer directly stacked on the common electrode, the conductive layer including a frame portion overlapping the scanning lines and the signal lines, and a first section and a second section. and a dividing line portion dividing the pixel into two sections, and the common electrode has, for each pixel, at least a first side and a second side opposite to the first side in a planar view, a first slit arranged in the first section, and at least a third side and a fourth side opposite to the third side in a planar view, and a second slit arranged in the second section, the distance between the first side and the second side gradually decreases as the pixel approaches the second slit, and the distance between the third side and the fourth side gradually decreases as the pixel approaches the first slit, and the dividing line portion is arranged between the first side and the third side and between the second side and the fourth side.

[0007] A display system according to one aspect includes the display device described above and a control device that outputs an image to the display device. [Brief explanation of the drawings]

[0008] [Figure 1] FIG. 1 is a configuration diagram showing an example of a display system according to the first embodiment. [Figure 2] FIG. 2 is a schematic diagram showing an example of the relative relationship between the display device and the user's eyes. [Figure 3] FIG. 3 is a block diagram showing an example of the configuration of the display system according to the first embodiment. [Figure 4] FIG. 4 is a circuit diagram showing a pixel arrangement in a display area according to the first embodiment. [Figure 5] FIG. 5 is a schematic diagram illustrating an example of a display panel according to the first embodiment. [Figure 6] FIG. 6 is a schematic diagram showing an enlarged view of a part of the display area in the first embodiment. [Figure 7] FIG. 7 is a cross-sectional view schematically showing a cross section taken along line VII-VII' in FIG. [Figure 8] FIG. 8 is a cross-sectional view schematically showing the boundary between the display region and the peripheral region according to the first embodiment. [Figure 9] FIG. 9 is a cross-sectional view schematically showing a cross section taken along line IX-IX' in FIG. [Figure 10] FIG. 10 is a plan view schematically showing the relationship between the slits and the liquid crystal domains. [Figure 11] FIG. 11 is a plan view schematically showing the relationship between the slits and the liquid crystal domains in the comparative example. [Figure 12] FIG. 12 is a schematic diagram showing an enlarged view of a part of the display area in the second embodiment. [Figure 13] FIG. 13 is a cross-sectional view schematically showing a cross section taken along line XIII-XIII' in FIG. DETAILED DESCRIPTION OF THE INVENTION

[0009] Modes for carrying out the invention (embodiments) will be described in detail with reference to the drawings. The present disclosure is not limited to the contents described in the following embodiments. Furthermore, the components described below include those that can be easily imagined by a person skilled in the art and those that are substantially identical. Furthermore, the components described below can be combined as appropriate. Note that the disclosure is merely an example, and any appropriate modifications that a person skilled in the art can easily conceive while maintaining the gist of the invention are naturally included within the scope of the present disclosure. Furthermore, for clarity of explanation, the drawings may show the width, thickness, shape, etc. of each part schematically compared to the actual embodiment. However, these are merely examples and are not intended to limit the interpretation of the present disclosure. Furthermore, in this specification and each figure, elements similar to those previously described with reference to the preceding figures may be designated by the same reference numerals, and detailed descriptions may be omitted as appropriate.

[0010] (Embodiment 1) Fig. 1 is a configuration diagram showing an example of a display system according to embodiment 1. Fig. 2 is a schematic diagram showing an example of the relative relationship between a display device and a user's eyes.

[0011] In this embodiment, the display system 1 is a display system that changes the display in accordance with the movement of a user. For example, the display system 1 is a VR system that stereoscopically displays a VR (Virtual Reality) image showing a three-dimensional object or the like in a virtual space and changes the stereoscopic display in accordance with the direction (position) of the user's head, thereby creating a sense of virtual reality for the user.

[0012] The display system 1 includes, for example, a display device 100 and a control device 200. The display device 100 and the control device 200 are configured to be able to input and output information (signals) via a cable 300. The cable 300 includes, for example, a cable such as a USB (Universal Serial Bus) or an HDMI (registered trademark) (High-Definition Multimedia Interface). The display device 100 and the control device 200 may be configured to be able to input and output information via wireless communication.

[0013] Furthermore, the display device 100 is supplied with power from the control device 200 via a cable 300. For example, the display device 100 may have a power receiving unit to which power is supplied from a power supply unit of the control device 200 via the cable 300, and each component of the display device 100, such as the display panel 110 and the sensor 120, may be driven using the power supplied from the control device 200. In this way, a battery or the like can be removed from the display device 100, making it possible to provide a cheaper and lighter display device 100. Note that a battery may be provided in the mounting member 400 or the display device 100 and supplied to the display device.

[0014] The display device 100 has a display panel, which is, for example, a liquid crystal display.

[0015] The display device 100 is fixed to a wearing member 400. Examples of the wearing member 400 include a headset, goggles, a helmet or a mask that covers both of the user's eyes, etc. The wearing member 400 is worn on the user's head. When worn, the wearing member 400 is positioned in front of the user so as to cover both of the user's eyes. The wearing member 400 functions as an immersive wearing member by positioning the display device 100 fixed inside in front of the user's eyes. The wearing member 400 may have an output unit that outputs sound signals and the like output from the control device 200. The wearing member 400 may also have a structure that incorporates the functions of the control device 200.

[0016] 1 shows the display device 100 being slotted into the mounting member 400, but it may also be fixed to the mounting member 400. In other words, the display system may be composed of the mounting member 400, a wearable display device including the display device 100, and the control device 200.

[0017] As shown in FIG. 2, the wearing member 400 has, for example, lenses 410 corresponding to both eyes of the user. The lenses 410 are magnifying lenses for focusing an image on the user's eyes. When the wearing member 400 is worn on the user's head, the lenses 410 are positioned in front of the user's eyes E. The user views the display area of the display device 100 magnified by the lenses 410. Therefore, the display device 100 needs to have high resolution to clearly display an image (screen). Note that although the present disclosure has been described using an example in which one lens is used, the display device 100 may have, for example, multiple lenses, and the display device 100 may be positioned in a position other than in front of the user's eyes.

[0018] The control device 200, for example, causes an image to be displayed on the display device 100. The control device 200 can be, for example, an electronic device such as a personal computer or a game console. The virtual image includes, for example, computer graphic images, 360-degree live-action images, and the like. The control device 200 outputs a three-dimensional image that utilizes the parallax between the user's eyes to the display device 100. The control device 200 outputs images for the right eye and the left eye that follow the direction of the user's head to the display device 100.

[0019] 3 is a block diagram showing an example of the configuration of the display system according to embodiment 1. As shown in FIG. 3, the display device 100 includes two display panels 110, a sensor 120, an image separation circuit 150, and an interface 160.

[0020] The display device 100 is composed of two display panels 110, one of which is used as the display panel 110 for the left eye and the other as the display panel 110 for the right eye.

[0021] Each of the two display panels 110 has a display area AA and a display control circuit 112. The display panel 110 has a light source device (not shown) that illuminates the display area AA from behind.

[0022] In the display area AA, P0 x Q0 pixels Pix (P0 in the row direction and Q0 in the column direction) are arranged in a two-dimensional matrix (row and column shape). In this embodiment, P0 = 2880 and Q0 = 1700. FIG. 3 shows a schematic representation of the arrangement of the pixels Pix, and the detailed arrangement of the pixels Pix will be described later. Since the pixels of the display device are viewed through a lens, the pixel pitch is, for example, between 3 μm and 10 μm, and the display area AA has a high-resolution arrangement of pixels Pix. The display area AA is surrounded by a peripheral area GA.

[0023] The display panel 110 has scan lines extending in the X direction and signal lines extending in the Y direction intersecting the X direction. For example, the display panel 110 has 2880 signal lines SL and 1700 scan lines GL. In the display panel 110, pixels Pix are arranged in an area surrounded by the signal lines SL and the scan lines GL. Each pixel Pix has a switching element SW (TFT: Thin Film Transistor) connected to the signal line SL and the scan line GL, and a pixel electrode connected to the switching element SW. A single scan line GL is connected to a plurality of pixels Pix arranged along the extension direction of the scan line GL. A single signal line SL is connected to a plurality of pixels Pix arranged along the extension direction of the signal line SL.

[0024] Of the two display panels 110, the display area AA of one display panel 110 is for the right eye, and the display area AA of the other display panel 110 is for the left eye. In the first embodiment, a case will be described in which the display panel 110 has two display panels 110, one for the left eye and one for the right eye. However, the display device 100 is not limited to the structure using two display panels 110 as described above. For example, there may be one display panel 110, and the display area of the single display panel 110 may be divided into two so that an image for the right eye is displayed in the right half area and an image for the left eye is displayed in the left half area.

[0025] The display control circuit 112 includes a driver IC (Integrated Circuit) 115, a signal line connection circuit 113, and a scanning line drive circuit 114. The signal line connection circuit 113 is electrically connected to the signal lines SL. The driver IC 115 controls the ON / OFF of switching elements (e.g., TFTs) for controlling the operation (light transmittance) of the pixels Pix via the scanning line drive circuit 114. The scanning line drive circuit 114 is electrically connected to the scanning lines GL.

[0026] The sensor 120 detects information that enables estimation of the orientation of the user's head. For example, the sensor 120 detects information that indicates the movement of the display device 100 or the wearing member 400, and the display system 1 estimates the orientation of the head of the user wearing the display device 100 on their head based on the information that indicates the movement of the display device 100 or the wearing member 400.

[0027] The sensor 120 detects information that enables estimation of the gaze direction using, for example, at least one of the angle, acceleration, angular velocity, orientation, and distance of the display device 100 or the wearing member 400. The sensor 120 may use, for example, a gyro sensor, an acceleration sensor, an orientation sensor, or the like. The sensor 120 may use, for example, a gyro sensor to detect the angle and angular velocity of the display device 100 or the wearing member 400. The sensor 120 may use, for example, an acceleration sensor to detect the direction and magnitude of acceleration acting on the display device 100 or the wearing member 400. The sensor 120 may use, for example, an orientation sensor to detect the orientation of the display device 100 or the wearing member 400. The sensor 120 may use, for example, a distance sensor, a GPS (Global Positioning System) receiver, or the like to detect movement of the display device 100 or the wearing member 400. The sensor 120 may use another sensor, such as an optical sensor, as long as it is a sensor for detecting the orientation of the user's head, changes in gaze, movement, etc., or may use a combination of multiple sensors. The sensor 120 is electrically connected to an image separation circuit 150 via an interface 160, which will be described later.

[0028] The image separation circuit 150 receives image data for the left eye and image data for the right eye sent from the control device 200 via the cable 300, sends the image data for the left eye to the display panel 110 that displays the image for the left eye, and sends the image data for the right eye to the display panel 110 that displays the image for the right eye.

[0029] The interface 160 includes a connector to which a cable 300 (FIG. 1) is connected. A signal from the control device 200 is input to the interface 160 via the connected cable 300. The image separation circuit 150 outputs a signal input from the sensor 120 to the control device 200 via the interface 160 and the interface 240. Here, the signal input from the sensor 120 includes information that enables the above-mentioned gaze direction to be estimated. Alternatively, the signal input from the sensor 120 may be output directly to the control unit 230 of the control device 200 via the interface 160. The interface 160 may be, for example, a wireless communication device, and may transmit and receive information to and from the control device 200 via wireless communication.

[0030] The control device 200 includes an operation unit 210 , a storage unit 220 , a control unit 230 , and an interface 240 .

[0031] The operation unit 210 accepts operations from the user. The operation unit 210 can use input devices such as a keyboard, buttons, or a touch screen. The operation unit 210 is electrically connected to the control unit 230. The operation unit 210 outputs information according to the operation to the control unit 230.

[0032] The storage unit 220 stores programs and data. The storage unit 220 temporarily stores processing results of the control unit 230. The storage unit 220 includes a storage medium. The storage medium includes, for example, a ROM, a RAM, a memory card, an optical disk, or a magneto-optical disk. The storage unit 220 may store data of images to be displayed on the display device 100.

[0033] The storage unit 220 stores, for example, a control program 211, a VR application 212, etc. The control program 211 can provide, for example, various control functions for operating the control device 200. The VR application 212 can provide a function for displaying a virtual reality image on the display device 100. The storage unit 220 can store, for example, various information input from the display device 100, such as data indicating the detection results of the sensor 120.

[0034] The control unit 230 includes, for example, an MCU (Micro Control Unit), a CPU (Central Processing Unit), etc. The control unit 230 can comprehensively control the operation of the control device 200. Various functions of the control unit 230 are realized based on the control of the control unit 230.

[0035] The control unit 230 includes, for example, a GPU (Graphics Processing Unit) that generates images to be displayed. The GPU generates images to be displayed on the display device 100. The control unit 230 outputs the images generated by the GPU to the display device 100 via the interface 240. In this embodiment, a case will be described in which the control unit 230 of the control device 200 includes a GPU, but this is not limiting. For example, the GPU may be provided in the display device 100 or the image separation circuit 150 of the display device 100. In this case, the display device 100 acquires data from, for example, the control device 200, an external electronic device, etc., and the GPU generates images based on the data.

[0036] The interface 240 includes a connector to which a cable 300 (see FIG. 1) is connected. A signal from the display device 100 is input to the interface 240 via the cable 300. The interface 240 outputs a signal input from the control unit 230 to the display device 100 via the cable 300. The interface 240 may be, for example, a wireless communication device, and may transmit and receive information to and from the display device 100 via wireless communication.

[0037] When the control unit 230 executes the VR application 212, it causes the display device 100 to display an image according to the movement of the user (display device 100). When the control unit 230 detects a change in the user (display device 100) while an image is being displayed on the display device 100, it changes the image displayed on the display device 100 to an image in the changed direction. When starting to create an image, the control unit 230 creates an image based on a reference viewpoint and a reference line of sight in the virtual space, and when it detects a change in the user (display device 100), it changes the viewpoint or line of sight when creating the displayed image from the reference viewpoint or reference line of sight direction according to the movement of the user (display device 100), and causes the display device 100 to display an image based on the changed viewpoint or line of sight.

[0038] For example, the control unit 230 detects a movement of the user's head to the right based on the detection result of the sensor 120. In this case, the control unit 230 changes the image currently being displayed to an image obtained when the user's line of sight is shifted to the right. The user can view an image to the right of the image being displayed on the display device 100.

[0039] For example, when the control unit 230 detects movement of the display device 100 based on the detection result of the sensor 120, it changes the image in accordance with the detected movement. When the control unit 230 detects that the display device 100 has moved forward, it changes the currently displayed image to an image that would appear if the display device 100 had moved forward. When the control unit 230 detects that the display device 100 has moved backward, it changes the currently displayed image to an image that would appear if the display device 100 had moved backward. The user can visually recognize an image in the direction of their own movement from the image displayed on the display device 100.

[0040] Fig. 4 is a circuit diagram showing a pixel array in a display region according to embodiment 1. Fig. 5 is a schematic diagram showing an example of a display panel according to embodiment 1. In the present disclosure, the scanning lines GL and the signal lines SL do not necessarily intersect at right angles, but for convenience of explanation, in Fig. 4, the scanning lines GL and the signal lines SL are shown as intersecting at right angles.

[0041] In the display area AA, switching elements SW, signal lines SL, scanning lines GL, etc. of the pixels PixR, PixG, and PixB shown in Fig. 4 are formed. The signal lines SL are wirings for supplying pixel signals to the pixel electrodes PE (see Fig. 6). The scanning lines GL are wirings for supplying gate signals that drive the switching elements SW.

[0042] As shown in Fig. 4, each of the pixels PixR, PixG, and PixB has a switching element SW and a capacitance of a liquid crystal layer LC. The switching element SW is configured with a thin film transistor, and in this example, it is configured with an n-channel MOS (Metal Oxide Semiconductor) TFT. An insulating film is provided between the pixel electrode PE and the common electrode CE, which will be described later, and a storage capacitance Cs shown in Fig. 4 is formed between the pixel electrode PE and the common electrode CE.

[0043] The color filters CFR1, CFG1, and CFB1 shown in FIG. 5 have color regions periodically arranged in three colors, for example, red (first color: R), green (second color: G), and blue (third color: B). The three color regions of R, G, and B correspond to the pixels PixR, PixG, and PixB shown in FIG. 4 described above. A set of pixels PixR, PixG, and PixB corresponding to the three color regions constitutes a pixel. A color filter may include color regions of four or more colors. The pixels PixR, PixG, and PixB may also be referred to as subpixels.

[0044] The color filters CFR1, CFG1, and CFB1 shown in FIG. 5 are disposed in an opening surrounded by two signal lines SL and two scanning lines GL.

[0045] As shown in Figures 4 and 5, in the direction Vx (first direction), pixel PixR is sandwiched between pixels PixB and PixG, and in the direction Vy (second direction), pixel PixR is sandwiched between pixels PixB and PixG.

[0046] Furthermore, in the direction Vx, the pixel PixG is sandwiched between the pixels PixR and PixB, and in the direction Vy, the pixel PixG is sandwiched between the pixels PixR and PixB.

[0047] In addition, pixel PixB is sandwiched between pixel PixG and pixel PixR in the direction Vx, and pixel PixB is sandwiched between pixel PixG and pixel PixR in the direction Vy.

[0048] In the direction Vx, the pixels PixR, PixG, and PixB are repeatedly arranged in this order. In the direction Vy, the pixels PixR, PixB, and PixG are repeatedly arranged in this order. Note that the arrangement in the direction Vy may be such that the pixels PixR, PixG, and PixB are repeatedly arranged in this order.

[0049] The color filters CFR1 are connected to each other by the same red color filter CFR2, and when the color filters CFR1 and CFR2 are connected, color filters of the same color are arranged in diagonal directions that intersect with the directions Vx and Vy. Similarly, the color filters CFG1 are connected to each other by the same green color filter CFG2, and the color filters CFB1 are connected to each other by the same blue color filter CFB2.

[0050] Because color filters CFR1 and CFR2 are integrally formed, for convenience of explanation, when color filters CFR1 and CFR2 are not distinguished, they will hereinafter be referred to as color filters CFR. Similarly, when color filters CFG1 and CFG2 are not distinguished, they will hereinafter be referred to as color filters CFG. When color filters CFB1 and CFB2 are not distinguished, they will hereinafter be referred to as color filters CFB. Furthermore, when color filters CFR, CFG, and CFB are not distinguished, color filters CFR, CFG, and CFB will be referred to as color filters CF.

[0051] The spacer SP shown in FIG. 5 is a member that regulates the distance between the array substrate SUB1 and the counter substrate SUB2. The spacer SP is made of, for example, acrylic resin. The spacer SP is cylindrical, and FIG. 5 shows the maximum diameter of the spacer SP. Note that the shape of the spacer SP is not limited to a cylindrical shape, and it may be formed as a spacer having a rectangular prism shape, for example. Although FIG. 5 shows one spacer as an example, in reality, multiple spacers are arranged.

[0052] Fig. 6 is a schematic diagram showing an enlarged view of a portion of the display area in embodiment 1. The pixel Pix shown in Fig. 6 is any one of pixel PixR, pixel PixG, and pixel PixB. Hereinafter, when there is no need to distinguish between pixel PixR, pixel PixG, and pixel PixB, pixel PixR, pixel PixG, and pixel PixB will be referred to as pixel Pix.

[0053] The signal lines SL are arranged at intervals in the direction Vx. The scanning lines GL are arranged at intervals in the direction Vy. The conductive layer TL overlaps the signal lines SL and the scanning lines GL in a planar view, forming a lattice pattern. The common electrode CE is octagonal and island-shaped. The common electrode CE is made of a light-transmitting conductive material such as ITO (Indium Tin Oxide), IZO (Indium Zinc Oxide), or IGO (Indium Gallium Oxide). The conductive layer TL overlaps the common electrode CE. The conductive layer TL electrically connects the island-shaped common electrodes CE. Because the conductive layer TL has a lower resistance than the common electrode CE, voltage drop suppresses variations in voltage distribution among the pixels Pix.

[0054] As shown in FIG. 6, the conductive layer TL of the first embodiment includes a first frame portion TLB overlapping with multiple signal lines SL in a planar view, a second frame portion TLC overlapping with multiple scanning lines GL in a planar view, and a dividing line portion TLA located between two adjacent scanning lines GL (second frame portion TLC). The dividing line portion TLA divides the pixel Pix into a first section Pixd1 and a second section Pixd2. As a result, the light-transmitting region of the aperture of the pixel Pix becomes two regions surrounded by the scanning lines GL and the dividing line portion TLA (conductive layer TL). As shown in FIG. 6, the second section Pixd2 is smaller than the first section Pixd1.

[0055] The first frame portion TLB has a width TLWX1 in the Vx direction narrowed to a width TLWX2 in the Vx direction at the portion where it connects with the second frame portion TLC. The width TLWX2 in the Vx direction is greater than the width of the signal line SL in the Vx direction. The width of the second frame portion TLC in the Vy direction is greater than the width of the scanning line GL in the Vy direction.

[0056] In each pixel Pix, a pixel electrode PE and a switching element SW are arranged in each opening surrounded by two signal lines SL and two scanning lines GL. A common electrode CE is an electrode common to multiple pixels Pix. The common electrode CE has a first slit CES1, a second slit CES2, and a third slit CES3 in each opening surrounded by two signal lines SL and two scanning lines GL.

[0057] The first slit CES1, the second slit CES2, and the third slit CES3 are portions of the common electrode CE that are not covered with the light-transmitting conductive material. The first slit CES1, the second slit CES2, and the third slit CES3 overlap with the pixel electrode PE. In the following description, the first slit CES1, the second slit CES2, and the third slit CES3 may be collectively referred to as slits CES. The first slit CES1 is disposed in the first partition Pixd1, and the second slit CES2 is disposed in the second partition Pixd2.

[0058] The substantial slit in the first section Pixd1 is an area where the common electrode CE and the conductive layer TL are not present. Part of the first frame portion TLB is present inside the first slit CES1. This creates recesses TLn11 and TLn12 in the narrow portion of the first frame portion TLB. The substantial slit in the first section Pixd1 has a shape that combines a trapezoidal region and a rectangular region.

[0059] The substantial slit in the second section Pixd2 is an area where the common electrode CE and the conductive layer TL are not present. Part of the first frame portion TLB is present inside the second slit CES2. This creates recesses TLn21 and TLn22 in the narrow portion of the first frame portion TLB. The substantial slit in the second section Pixd2 has a shape that combines a trapezoidal region and a rectangular region.

[0060] The third slit CES3, which is an area of the common electrode CE where there is no conductive material, connects the first slit CES1 and the second slit CES2. The third slit CES3 is covered with a dividing line portion TLA, and the first slit CES1 and the second slit CES2 are separated by the dividing line portion TLA. The third slit CES3 is covered with the dividing line portion TLA and does not actually become a slit. The third slit CES3 is rectangular.

[0061] As shown in Fig. 6, the semiconductor SC is formed in a U-shape. The signal line SL and the semiconductor SC are electrically connected via a contact hole CH1. The semiconductor SC and the relay electrode RE are electrically connected via a contact hole CH2. The relay electrode RE and the pixel electrode PE are electrically connected via a contact hole CH3.

[0062] A contact hole CH3 is arranged in the first section Pixd1, and the area of the first section Pixd1 is larger than the area of the second section Pixd2.

[0063] Fig. 7 is a cross-sectional view schematically showing a cross section taken along line VII-VII' in Fig. 6. In the first embodiment, as shown in Fig. 5, a color filter CF is provided on an array substrate SUB1. The display device 100 has a so-called COA (Color Filter On Array) structure in which the color filter CF, pixel electrodes PE, and common electrode CE are arranged on the array substrate SUB1.

[0064] 7, the array substrate SUB1 is based on a first insulating substrate 10 having light-transmitting properties, such as a glass substrate or a resin substrate. The array substrate SUB1 includes, on the side of the first insulating substrate 10 facing the counter substrate SUB2, a first layer GL1 of the scanning line GL, a first insulating film 11, a second insulating film 12, a third insulating film 13, a fourth insulating film 14, a color filter CF, a fifth insulating film 15, a pixel electrode PE, a sixth insulating film 16, a seventh insulating film 17, a conductive layer TL, a common electrode CE, a first alignment film AL1, and the like. In the following description, the direction from the array substrate SUB1 toward the counter substrate SUB2 will be referred to as "upward" or simply "upward."

[0065] The first layer GL1 of the scanning line GL is located on the first insulating substrate 10. The first insulating film 11 is located on the first layer GL1 of the scanning line GL and the inner side surface 10A of the first insulating substrate 10. The second insulating film 12 is located on the first insulating film 11. The semiconductor SC is located on the second insulating film 12. The third insulating film 13 is located on the semiconductor SC and the second insulating film 12. The second layer GL2 of the scanning line GL is located on the third insulating film 13. Note that the portions of the first layer GL1 and second layer GL2 of the scanning line GL that overlap the semiconductor SC act as gate electrodes.

[0066] The fourth insulating film 14 is located on the second layer GL2 of the scanning line GL and the third insulating film 13. A contact hole CH1 is formed by opening a hole in the third insulating film 13 and the fourth insulating film 14 at a position overlapping the semiconductor SC, and the signal line SL formed on the fourth insulating film 14 is electrically connected to the semiconductor SC via the contact hole CH1.

[0067] A contact hole CH2 is formed by drilling a hole in the third insulating film 13 and the fourth insulating film 14 at a position overlapping the semiconductor SC, and a relay electrode RE formed on the fourth insulating film 14 is electrically connected to the semiconductor SC via the contact hole CH2.

[0068] The fifth insulating film 15 is located on the signal lines SL, the relay electrodes RE, and the fourth insulating film 14. The color filters CF are located on the fifth insulating film 15. The sixth insulating film 16 is located on the color filters CF and the fifth insulating film 15.

[0069] A contact hole CH3 is formed in the fifth insulating film 15 and the sixth insulating film 16 at a position overlapping the relay electrode RE, and the pixel electrode PE formed on the sixth insulating film 16 is electrically connected to the relay electrode RE through the contact hole CH3. The pixel electrode PE is made of a light-transmitting conductive material such as ITO, IZO, or IGO.

[0070] The common electrode CE is located on the seventh insulating film 17. The common electrode CE is formed of a light-transmitting conductive material such as ITO, IZO, or IGO.

[0071] The conductive layer TL is located on the seventh insulating film 17. The conductive layer TL is a conductor and is electrically connected to the common electrode CE, so the resistance value per unit area of the common electrode CE and the conductive layer TL is small. The conductive layer TL may be a single layer of metal such as aluminum (Al), but it may also be formed of multiple metal layers such as titanium / aluminum / titanium or molybdenum / aluminum / molybdenum by arranging titanium (Ti) and molybdenum (Mo) above and below the aluminum.

[0072] The common electrode CE and the seventh insulating film 17 exposed through the first slits CES1 and the second slits CES2 are covered with the first alignment film AL1.

[0073] The counter substrate SUB2 is based on a second insulating substrate 20 having light-transmitting properties, such as a glass substrate or a resin substrate. The counter substrate SUB2 is provided with an overcoat layer 21 and a second alignment film AL2 on the side of the second insulating substrate 20 facing the array substrate SUB1.

[0074] The array substrate SUB1 and counter substrate SUB2 are arranged such that the first alignment film AL1 and the second alignment film AL2 face each other. The liquid crystal layer LC is sealed between the first alignment film AL1 and the second alignment film AL2. The first alignment film AL1 and the second alignment film AL2 align the long axes of the liquid crystal molecules so that they are perpendicular or parallel to the initial alignment direction AD shown in FIG. 6. The liquid crystal layer LC is made of a negative-type liquid crystal material with a negative dielectric anisotropy or a positive-type liquid crystal material with a positive dielectric anisotropy. The liquid crystal layer LC is stable in alignment when a voltage is applied to the liquid crystal layer LC, making it easy to maintain a fast response of the liquid crystal molecules. If the liquid crystal layer LC is made of a positive-type liquid crystal material, the long axes of the liquid crystal molecules are aligned in a direction parallel to the initial alignment direction AD shown in FIG. 6. If the liquid crystal layer LC is made of a negative-type liquid crystal material, the long axes of the liquid crystal molecules are aligned in a direction perpendicular to the initial alignment direction AD shown in FIG. 6.

[0075] The array substrate SUB1 faces the backlight unit, and the counter substrate SUB2 faces the display surface. Various types of backlight units are applicable, but detailed explanation of their structures will be omitted.

[0076] The first optical element OD1 including the first polarizer PL1 is disposed on the outer surface 10B of the first insulating substrate 10 or on the surface facing the backlight unit. The second optical element OD2 including the second polarizer PL2 is disposed on the outer surface 20B of the second insulating substrate 20 or on the surface on the viewing position side. The first polarization axis of the first polarizer PL1 and the second polarization axis of the second polarizer PL2 are in a crossed Nicol positional relationship in the Vx-Vy plane, for example. The first optical element OD1 and the second optical element OD2 may include other optically functional elements such as retardation plates.

[0077] Fig. 8 is a cross-sectional view schematically showing the boundary between the display region and the peripheral region according to the first embodiment. Fig. 9 is a cross-sectional view schematically showing the cross section taken along line IX-IX' in Fig. 8. As shown in Figs. 8 and 9, in the peripheral region GA, a wiring COM for supplying a common potential is disposed on a fourth insulating film 14. A fifth insulating film 15 covers and protects the wiring COM. A contact hole CHG is provided in a part of the fifth insulating film 15, and the wiring COM is electrically connected to a conductive layer TL and a common electrode CE extending from the display region AA via the contact hole CHG.

[0078] 8 and 9, in the peripheral area GA, a light-shielding layer BM is provided on the counter substrate SUB2, and the light-shielding layer BM can hide the peripheral area GA of the array substrate SUB1. In the example shown in FIGS. 7 and 9, the light-shielding layer BM is not provided on the counter substrate SUB2 in the display area AA, but it may be provided. The light-shielding layer BM is made of a black resin material.

[0079] Unlike Embodiment 1, in the structure of the comparative example in which color filters and light-shielding layers at the boundaries between the colors of the color filters are provided on the counter substrate SUB2, the smaller the pixel Pix, the more likely it is that the opening of the pixel Pix in the array substrate will overlap with the position of the light-shielding layer in the display area AA of the counter substrate SUB2. In contrast, in the COA structure of Embodiment 1 shown in Figures 8 and 9, the display area AA of the counter substrate SUB2 does not have color filters CF and light-shielding layers at the boundaries between the colors of the color filters CF, so the required level of overlay accuracy between the array substrate SUB1 and the counter substrate SUB2 can be lowered.

[0080] FIG. 10 is a plan view schematically showing the relationship between slits and liquid crystal domains. FIG. 11 is a plan view schematically showing the relationship between slits and liquid crystal domains in a comparative example. The conductive layer TL of embodiment 1 shown in FIG. 10 has parting line portions TLA, while the conductive layer TL of the comparative example shown in FIG. 11 does not have parting line portions TLA. As a result, dark regions NDMC that are not present in the pixels of embodiment 1 shown in FIG. 10 are generated in the pixels of embodiment 1 shown in FIG. 11. As a result, the liquid crystal domains DM are more stable in embodiment 1 shown in FIG. 10 than in the comparative example shown in FIG. 11. Furthermore, the parting line portions TLA block light more effectively than the dark regions NDMC, so embodiment 1 shown in FIG. 10 has improved contrast compared to the comparative example shown in FIG. 11.

[0081] The first slit CES1 is a polygon having a first trapezoidal region CEST1 and rectangular regions CESB11 and CESB12. Similarly, the second slit CES2 is a polygon having a second trapezoidal region CEST2 and rectangular regions CESB21 and CESB22. As described above, the first slit CES1 and the second slit CES2 each include a trapezoidal shape in the opening portion of the pixel Pix (see FIG. 6).

[0082] 10, the parting line portion TLA is disposed between the first side Qt11 and the third side Qt21, and between the second side Qt12 and the fourth side Qt22. As a result, the fifth side Qa1 and the sixth side Qa2 extend in the direction in which the parting line portion TLA extends.

[0083] As shown in FIG. 10, the first trapezoidal region CEST1 has a first side Qt11, a second side Qt12, a fifth side Qa1, and a seventh side Qb3. In the first embodiment, the fifth side Qa1 is along the dividing line portion TLA. The fifth side Qa1 is the top side of the trapezoid and connects the first side Qt11 and the second side Qt12. The seventh side Qb3 is the bottom side of the trapezoid and connects the first side Qt11 and the second side Qt12. The first side Qt11 and the second side Qt12 face each other and are not parallel to each other. The distance between the first side Qt11 and the second side Qt12 decreases as the region approaches the fifth side Qa1. As a result, the distance between the first side Qt11 and the second side Qt12 gradually decreases as the region approaches the second slit CES2.

[0084] The second trapezoidal region CEST2 has a third side Qt21, a fourth side Qt22, a sixth side Qa2, and an eighth side Qb4. In embodiment 1, the sixth side Qa2 is along the dividing line portion TLA. The sixth side Qa2 is the top side of the trapezoid and connects the third side Qt21 and the fourth side Qt22. The eighth side Qb4 is the bottom side of the trapezoid and connects the third side Qt21 and the fourth side Qt22. The third side Qt21 and the fourth side Qt22 face each other and are non-parallel. The distance between the third side Qt21 and the fourth side Qt22 decreases as the region approaches the sixth side Qa2. As a result, the distance between the third side Qt21 and the fourth side Qt22 gradually decreases as the region approaches the first slit CES1.

[0085] 10, because the second trapezoidal region CEST2 is smaller than the first trapezoidal region CEST1, the angle α between the direction Vy (second direction) and the second side Qt12 is smaller than the angle β between the direction Vy (second direction) and the fourth side Qt22. Similarly, the angle between the direction Vy (second direction) and the first side Qt11 is smaller than the angle between the direction Vy (second direction) and the third side Qt21. In plan view, portions of the first side Qt11, second side Qt12, third side Qt21, and fourth side Qt22 intersect with the dividing line TLA and first frame portion TLB, and the portion surrounded by any one of the first side Qt11, second side Qt12, third side Qt21, and fourth side Qt22, the dividing line TLA, and the first frame portion TLB forms a triangle. This stabilizes the liquid crystal domains DM along the first side Qt11, the second side Qt12, the third side Qt21, and the fourth side Qt22, thereby improving the transmittance.

[0086] The rectangular region CESB12 has a seventh side Qb3, a ninth side Qb1, an eleventh side Qs11, and a twelfth side Qs12. The eleventh side Qs11 and the twelfth side Qs12 are edges of the first frame portion TLB that are shorter than the shortest distance in the Vx direction between the first side Qt11 and the second side Qt12 of the adjacent first frame portion TLB. The seventh side Qb3 and the ninth side Qb1 are parallel. The eleventh side Qs11 and the twelfth side Qs12 are parallel. The eleventh side Qs11 and the twelfth side Qs12 are straight lines along the first frame portion TLB. The ninth side Qb1 is a straight line connecting the corners Qbp11 and Qbp12 of the first frame portion TLB that are adjacent to the recesses TLn11 and TLn12.

[0087] The rectangular region CESB22 has an eighth side Qb4, a tenth side Qb2, a thirteenth side Qs21, and a fourteenth side Qs22. The eighth side Qb4 and the tenth side Qb2 are parallel to each other. The thirteenth side Qs21 and the fourteenth side Qs22 are edges of the first frame portion TLB that are shorter than the shortest distance in the Vx direction between the first side Qt11 and the second side Qt12 of the adjacent first frame portion TLB. The thirteenth side Qs21 and the fourteenth side Qs22 are parallel to each other. The thirteenth side Qs21 and the fourteenth side Qs22 are straight lines along the first frame portion TLB. The tenth side Qb2 is a straight line connecting the corners Qbp21 and Qbp22 of the first frame portion TLB that are adjacent to the recesses TLn21 and TLn22.

[0088] The rectangular region CESB11 has a ninth side Qb1, a fifteenth side Qd1, a seventeenth side Qc11, and an eighteenth side Qc12. The ninth side Qb1 and the fifteenth side Qd1 are parallel to each other. The seventeenth side Qc11 and the eighteenth side Qc12 are parallel to each other. The seventeenth side Qc11 is a straight line that runs along the bottom of the recess TLn11. The eighteenth side Qc12 is a straight line that runs along the bottom of the recess TLn12.

[0089] The rectangular region CESB21 has a tenth side Qb2, a sixteenth side Qd2, a nineteenth side Qc21, and a twentieth side Qc22. The tenth side Qb2 and the sixteenth side Qd2 are parallel to each other. The nineteenth side Qc21 and the twentieth side Qc22 are parallel to each other. The nineteenth side Qc21 is a straight line that runs along the bottom of the recess TLn11. The twentieth side Qc22 is a straight line that runs along the bottom of the recess TLn22.

[0090] In the first embodiment, the length of the first side Qt11 is equal to the length of the second side Qt12. As a result, the first trapezoidal region CEST1 has an isosceles trapezoid shape. The length of the third side Qt21 is equal to the length of the fourth side Qt22. As a result, the second trapezoidal region CEST2 has an isosceles trapezoid shape. The first trapezoidal region CEST1 may be an asymmetric trapezoid in which the length of the first side Qt11 is different from the length of the second side Qt12. The second trapezoidal region CEST2 may be an asymmetric trapezoid in which the length of the third side Qt21 is different from the length of the fourth side Qt22.

[0091] 10, for example, when no voltage is applied to the liquid crystal layer LC, the liquid crystal molecules near the first edge Qt11 and the second edge Qt12 are initially aligned with their long axes pointing inward toward the first slit CES1. The liquid crystal molecules near the first edge Qt11 and the second edge Qt12 are tilted in opposite directions relative to the direction Vy. Similarly, when no voltage is applied to the liquid crystal layer LC, the liquid crystal molecules near the third edge Qt21 and the fourth edge Qt22 are initially aligned with their long axes pointing inward toward the second slit CES2. The liquid crystal molecules near the third edge Qt21 and the fourth edge Qt22 are tilted in opposite directions relative to the direction Vy.

[0092] On the other hand, when a voltage is applied to the liquid crystal layer LC, that is, when an electric field is formed between the pixel electrode PE and the common electrode CE, the liquid crystal molecules are affected by the electric field and their alignment changes. Liquid crystal domains DM are generated near the first edge Qt11 and the second edge Qt12, and their transmittance is controlled according to the voltage. Similarly, liquid crystal domains DM are generated near the third edge Qt21 and the fourth edge Qt22, and their transmittance is controlled according to the voltage. Within the liquid crystal domains DM, dark regions NDM occur where the alignment of the liquid crystal molecules hardly changes even when a voltage is applied to the liquid crystal layer LC.

[0093] When a voltage is applied between the pixel electrode PE and the common electrode CE, the liquid crystal molecules in the area near the first side Qt11 and the area near the second side Qt12 rotate in opposite directions. When a voltage is applied between the pixel electrode PE and the common electrode CE, the liquid crystal molecules in the area near the third side Qt21 and the area near the fourth side Qt22 rotate in opposite directions.

[0094] For example, when a voltage is applied between the pixel electrode PE and the common electrode CE, the long axis direction of the liquid crystal molecules rotates clockwise in the region near the first edge Qt11 and counterclockwise in the region near the second edge Qt12. When a voltage is applied between the pixel electrode PE and the common electrode CE, the long axis direction of the liquid crystal molecules rotates clockwise in the region near the fourth edge Qt22 and counterclockwise in the region near the third edge Qt21. Thus, when a voltage is applied between the pixel electrode PE and the common electrode CE, the polarization state of the incident linearly polarized light changes depending on the alignment state of the liquid crystal molecules as it passes through the liquid crystal layer LC. Note that the rotation direction of the long axis direction of the liquid crystal molecules may be opposite to that described above.

[0095] The two liquid crystal domains DM are separated by a dark region NDM, and the liquid crystal molecules in the liquid crystal domain DM respond faster than those in horizontal electric field type liquid crystal displays such as FFS (Fringe Field Switching) and IPS (In Plane Switching).

[0096] The presence of rectangular regions CESB11, CESB12, CESB21, and CESB22 stabilizes the liquid crystal domain DM. In the display device of embodiment 1, even if the pixel Pix becomes smaller due to higher resolution, the area of the liquid crystal domain DM can be secured. Therefore, in the display device of embodiment 1, the transmittance is improved.

[0097] As explained above, the distance between the first side Qt11 and the second side Qt12 gradually decreases as one approaches the second slit CES2. The distance between the third side Qt21 and the fourth side Qt22 gradually decreases as one approaches the first slit CES1. This improves the stability of the liquid crystal alignment and stabilizes the behavior of the liquid crystal molecules in the first slit CES1 compared to when the first side Qt11 and the second side Qt12 are parallel. The stability of the liquid crystal alignment and stabilizes the behavior of the liquid crystal molecules in the second slit CES2 improves the stability of the liquid crystal alignment and stabilizes the behavior of the liquid crystal molecules compared to when the third side Qt21 and the fourth side Qt22 are parallel.

[0098] It should be noted that there is no light-shielding layer in the display area AA of the counter substrate SUB2, which reduces the influence of misalignment between the array substrate SUB1 and the counter substrate SUB2.

[0099] The display device 100 of the first embodiment includes an array substrate SUB1, a counter substrate SUB2 facing the array substrate SUB1, and a liquid crystal layer LC containing liquid crystal molecules between the array substrate SUB1 and the counter substrate SUB2. The array substrate SUB1 includes a plurality of signal lines SL arranged at intervals in the direction Vx, a plurality of scanning lines GL arranged at intervals in the direction Vy, a plurality of pixel electrodes PE arranged at each opening of a pixel Pix surrounded by two adjacent signal lines SL and two adjacent scanning lines GL, a plurality of semiconductors SC arranged for each pixel Pix, a common electrode CE overlapping the plurality of pixel electrodes PE via a seventh insulating film 17, and a lattice-shaped light-shielding conductive layer TL stacked directly on the common electrode CE.

[0100] The conductive layer TL has a dividing line portion TLA that divides the pixel Pix into two sections, a first section Pixd1 and a second section Pixd2, a first frame portion TLB that overlaps the signal line SL, and a second frame portion TLC that overlaps the scanning line GL. The common electrode CE has a first slit CES1 and a second slit CES2 for each pixel Pix. The first slit CES1 is located in the first section Pixd1 and has at least a first side Qt11 and a second side Qt12 that faces the first side Qt11 in a planar view. The second slit CES2 is located in the second section Pixd2 and has at least a third side Qt21 and a fourth side Qt22 that faces the third side Qt21 in a planar view.

[0101] The distance between the first side Qt11 and the second side Qt12 gradually decreases as one approaches the second slit CES2. Similarly, the distance between the third side Qt21 and the fourth side Qt22 gradually decreases as one approaches the first slit CES1. The dividing line portions TLA are disposed between the first side Qt11 and the third side Qt21, and between the second side Qt12 and the fourth side Qt22.

[0102] As a result, the pixel Pix of embodiment 1 is multi-domained, which suppresses the influence of the dark area NDM between the first slit CES1 and the second slit CES2, stabilizes the behavior of the liquid crystal molecules near any of the first side Qt11, the second side Qt12, the third side Qt21, and the fourth side Qt22, and improves the transmittance.

[0103] (Embodiment 2) Fig. 12 is a schematic diagram illustrating an enlarged view of a portion of the display region in the second embodiment. Fig. 13 is a cross-sectional view illustrating a cross section taken along line XIII-XIII' in Fig. 12. In the following description, the same components as those in the first embodiment may be denoted by the same reference numerals. Furthermore, redundant description will be omitted. In the first embodiment, the third slit CES3 is provided, connecting the first slit CES1 and the second slit CES2 in a portion of the common electrode CE where there is no translucent conductive material. However, in the second embodiment, the common electrode is also provided in a region overlapping with the dividing line portion TLA, and the first slit CES1 and the second slit CES2 are separated by the conductive material of the common electrode CE, which is different from the first embodiment.

[0104] As shown in FIGS. 12 and 13, the slit CES for each pixel Pix has a first slit CES1 and a second slit CES2.

[0105] In contrast, in the first slit CES1 of embodiment 2, the intersection of the first side Qt11 and the fifth side Qa1 and the intersection of the second side Qt12 and the fifth side Qa1 tend to be rounded due to wraparound of the exposure light. In the second slit CES2 of embodiment 1, the intersection of the third side Qt21 and the sixth side Qa2 and the intersection of the fourth side Qt22 and the sixth side Qa2 tend to be rounded due to wraparound of the exposure light. In contrast, in embodiment 1, the first slit CES1, the second slit CES2, and the third slit CES3 are formed collectively. As a result, without the parting line portion TLA, there is no intersection point between the first side Qt11 and the fifth side Qa1, between the second side Qt12 and the fifth side Qa1, between the third side Qt21 and the sixth side Qa2, or between the fourth side Qt22 and the sixth side Qa2, so the shapes of the first side Qt11, the second side Qt12, the third side Qt21, and the fourth side Qt22 are less likely to become rounded, and their straight shapes are stabilized. Then, when the parting line portion TLA is formed to cover the third slit CES3, the intersection line between the parting line portion TLA and the first slit CES1 becomes the fifth side Qa1, and the intersection line between the parting line portion TLA and the second slit CES2 becomes the sixth side Qa2.

[0106] Although preferred embodiments have been described above, the present disclosure is not limited to such embodiments. The contents disclosed in the embodiments are merely examples, and various modifications are possible within the scope of the present disclosure. Appropriate modifications made within the scope of the present disclosure also naturally fall within the technical scope of the present disclosure. [Explanation of symbols]

[0107] 1 Display System 10 First insulating substrate 20 Second insulating substrate 100 display device 110 Display panel 112 Display control circuit 200 control device 410 lens AA display area BM light shielding layer CE common electrode CES Slit CES1 1st slit CES2 2nd slit CES3 3rd slit CESB11, CESB12, CESB21, CESB22 rectangular area CEST1 First trapezoid area CEST2 Second trapezoid area GA peripheral area GL scanline LC liquid crystal layer Lcm liquid crystal molecule LS light shielding layer PE pixel electrode Pix, PixB, PixG, PixR pixels Pixd1 Section 1 Pixd2 Section 2 Qt11 First side Qt12 second side Qt21 Third side Qt22 4th side Qa1 5th side Qa2 Side 6 Qb3 7th side Qb4 8th side Qb1 9th side Qb2 10th side Qs11 11th side Qs12 12th side Qs21 Side 13 Qs22 Side 14 Qd1 Side 15 Qd2 Side 16 Qc11 Side 17 Qc12 Side 18 Qc21 Side 19 Qc22 20th side Qbp11, Qbp12, Qbp21, Qbp22 Corner SL signal line SUB1 array board SUB2 opposing substrate TL Conductive Layer TLA dividing line part TLB 1st frame TLC 2nd frame

Claims

1. an array substrate; a counter substrate facing the array substrate, and a liquid crystal layer containing liquid crystal molecules between the array substrate and the counter substrate; The array substrate comprises: a plurality of signal lines spaced apart in a first direction; a plurality of scan lines spaced apart in a second direction; a plurality of pixel electrodes arranged in each pixel aperture surrounded by two adjacent signal lines and two adjacent scanning lines; A plurality of semiconductors arranged for each pixel; a common electrode overlapping the plurality of pixel electrodes via an insulating film; a lattice-shaped light-shielding conductive layer directly stacked on the common electrode; the conductive layer has a frame portion overlapping the scanning lines and the signal lines, and a dividing line portion dividing the pixel into two sections, a first section and a second section; the common electrode has, for each pixel, a first slit that has at least a first side and a second side opposite to the first side in a plan view and is arranged in the first section, and a second slit that has at least a third side and a fourth side opposite to the third side in a plan view and is arranged in the second section; the distance between the first side and the second side gradually decreases toward the second slit, the distance between the third side and the fourth side gradually decreases toward the first slit, The dividing line portion is disposed between the first side and the third side and between the second side and the fourth side. Display device.

2. The display device according to claim 1 , wherein the connection between the semiconductor and the pixel electrode is disposed in the first section, and the area of the first section is larger than the area of the second section.

3. 2. The display device according to claim 1, wherein, in a plan view, the first side, the second side, the third side, and the fourth side intersect with the frame portion, and a portion surrounded by any one of the first side, the second side, the third side, and the fourth side, the dividing line portion, and the frame portion is a triangle.

4. The display device according to claim 1 , wherein the adjacent frame portions have a portion that is smaller than the area between the first side and the second side or the area between the third side and the fourth side.

5. 2. The display device of claim 1, wherein the first slit includes a trapezoidal shape, a fifth side connecting the first side and the second side is along the dividing line portion, and the second slit includes a trapezoidal shape, and a sixth side connecting the third side and the fourth side is along the dividing line portion.

6. The display device according to claim 1 , wherein the first slit and the second slit are connected by a third slit, and the third slit is covered by the dividing line portion.

7. 2. The display device of claim 1, wherein when a voltage is applied between the pixel electrode and the common electrode, the long axis directions of the liquid crystal molecules rotate in opposite directions in the regions near the first side and the third side, and in opposite directions in the regions near the second side and the fourth side.

8. Lenses and A display device according to any one of claims 1 to 7; a control device that outputs an image to the display device, Display system.

Images