Transistor for high frequency

Abstract

To provide a transistor for high frequency capable of improving a transistor performance while suppressing an increase in cost.SOLUTION: A plurality of unit transistors 5 connected in parallel with each other are provided on a semiconductor substrate 1. A plurality of capacitors 7 are connected to gate electrodes 6 of the plurality of unit transistors 5, respectively. A plurality of resistors 9 are connected in parallel to the plurality of capacitors 7. First and second pads 10 and 11 are provided on a top face of the semiconductor substrate 1 and connected to one end and the other end of the resistor 9 which is connected to at least the unit transistor 5 at a central part of the plurality of unit transistors 5 disposed in a row. A silicon substrate 12 is disposed above the semiconductor substrate 1. First and second conductors 13 and 14 are provided in the silicon substrate 12. A bump 15 connects the first pad 10 with one end of the first conductor 13. A bump 16 connects the second pad 11 with one end of the second conductor 14. The other end of the first conductor 13 and the other end of the second conductor 14 are brought into contact with a bottom face of the silicon substrate 12 and opposed while being separated from each other.SELECTED DRAWING: Figure 1

Description

[Technical Field]

[0001] The present disclosure relates to a high frequency transistor for amplifying a high frequency signal. [Background technology]

[0002] In recent years, advances have been made in the expansion of information communications capacity using high-frequency signals with frequencies above 1 GHz, the resolution of radar, and the detection distance of searched objects. Higher performance is required for the high-frequency transistors used as amplifiers in these communications equipment and radar systems. High-frequency transistors are required to have improved gain, which is the power amplification factor of the high-frequency signal, saturated output power, and power-added efficiency. Low gain in high-frequency transistors requires a driver amplifier to pre-amplify the power of the high-frequency signal input to the high-frequency transistor. Improving the gain of high-frequency transistors can reduce the number of driver amplifiers, thereby simplifying and reducing the cost of communications equipment and radar systems. Furthermore, to amplify high-frequency signals, a DC bias voltage must be applied to the high-frequency transistor to supply DC power. However, not all of the supplied DC power is converted into RF signal energy; much of it is converted into heat energy. Therefore, communications equipment and radar systems require cooling devices to cool the high-frequency transistors. Improving the power-added efficiency of high-frequency transistors can reduce the proportion of the supplied DC power that becomes heat energy, thereby reducing the need for cooling devices. This also allows for lower costs and smaller sizes of communication equipment and radar devices.

[0003] High-frequency transistors with high gain can oscillate simply by applying a DC bias voltage, even without inputting a high-frequency signal. This results in the generation of unnecessary high-frequency signals, which can disrupt the operation of communications equipment and radar devices. To address this issue, a CR circuit, consisting of a resistor and capacitor connected in parallel, is connected to the gate electrode of each transistor as a stabilization circuit. This stabilization circuit intentionally reduces the gain of the high-frequency transistor, suppressing oscillation.

[0004] A semiconductor substrate is provided with multiple unit transistors connected in parallel. Typically, several of these transistors are grouped together to form a block. Each block is connected to a gate wiring that serves as an input terminal for electrical signals. Hereinafter, this block will be referred to as a unit transistor.

[0005] If the characteristics of multiple unit transistors differ, the high-frequency signals output from them cannot be properly combined, resulting in a decrease in saturated output power and power-added efficiency. Therefore, it is desirable for multiple unit transistors to have the same characteristics and operate uniformly. However, when a high-power high-frequency signal is input, the unit transistors generate heat and their temperature rises. The heated unit transistors then warm the other unit transistors around them. This results in an uneven temperature distribution, with the unit transistor located in the center becoming hotter and the unit transistors on both sides becoming cooler. Because transistor characteristics change with temperature, multiple unit transistors operate unevenly, resulting in a decrease in power-added efficiency and other characteristics. If the temperature unevenness becomes significant, the unit transistor in the center can become extremely hot and be damaged.

[0006] In response to this, it has been proposed to vary the resistance value of the stabilization circuit for each unit transistor (see, for example, Patent Document 1). By lowering the resistance value of the stabilization circuit for the unit transistors in the center to further attenuate the power of the high-frequency signal, it is possible to suppress heat generation in the unit transistors in the center and make the temperature of multiple unit transistors uniform. [Prior art documents] [Patent documents]

[0007] [Patent Document 1] Patent No. 6399267 Summary of the Invention [Problem to be solved by the invention]

[0008] However, the amount of temperature rise in a transistor varies depending on the applied voltage, environmental temperature, etc. Therefore, changing the resistance value of the stabilization circuit for each unit transistor may worsen the non-uniform operation of the transistors.

[0009] Another proposal is to provide multiple unit transistors with their own bias circuits and built-in thermistors. It is expected that high-frequency transistors will operate uniformly if the bias circuits change the gate bias voltage in response to the temperature detected by the thermistors. However, placing thermistors in close proximity to heat-generating areas is difficult due to the physical size of the unit transistors themselves. Furthermore, adding a thermistor increases the area of expensive semiconductor substrates, such as silicon carbide or gallium nitride. Providing a bias circuit and thermistor for each unit transistor significantly increases the substrate area. Furthermore, since multiple unit transistors each require a different bias circuit, the bias circuits must have a specific configuration. This poses the problem of significantly increasing costs.

[0010] The present disclosure has been made to solve the above-mentioned problems, and its object is to obtain a high-frequency transistor that can improve transistor performance while suppressing increases in cost. [Means for solving the problem]

[0011] a first bump connecting the first pad to one end of the first conductor, and a second bump connecting the second pad to one end of the second conductor; and a second bump connecting the second pad to one end of the second conductor, wherein the other end of the first conductor and the other end of the second conductor are in contact with the silicon substrate and face each other at a distance from each other. [Effects of the Invention]

[0012] In this disclosure, the other end of the first conductor and the other end of the second conductor are electrically connected to each other via a silicon substrate heated by heat from the corresponding unit transistor. Because this creates a state in which a path is connected in parallel to the resistor, the resistance of the resistors that make up the stabilization circuit decreases, further attenuating high-frequency signals. This behavior occurs more significantly in the central unit transistors and their stabilization circuits, which become hotter, so that multiple unit transistors approach the same temperature. This makes it possible to suppress temperature nonuniformity among multiple unit transistors. This allows for improved transistor performance while suppressing cost increases. [Brief explanation of the drawings]

[0013] [Figure 1] 1 is a cross-sectional view showing a high-frequency transistor according to a first embodiment. [Figure 2] 1 is a circuit diagram of a high-frequency transistor according to a first embodiment. [Figure 3] FIG. 10 is a cross-sectional view showing a high-frequency transistor according to a comparative example. [Figure 4]FIG. 10 is a circuit diagram of a high-frequency transistor according to a comparative example. [Figure 5] FIG. 10 is a cross-sectional view showing a high-frequency transistor according to a second embodiment. [Figure 6] FIG. 10 is a bottom view showing a silicon substrate according to a second embodiment. [Figure 7] FIG. 10 is a cross-sectional view showing a high-frequency transistor according to a third embodiment. [Figure 8] FIG. 10 is a top view showing a silicon substrate according to a third embodiment. DETAILED DESCRIPTION OF THE INVENTION

[0014] High frequency transistors according to embodiments will be described with reference to the drawings. The same or corresponding components will be designated by the same reference numerals, and repeated description may be omitted.

[0015] Embodiment 1 Fig. 1 is a cross-sectional view showing a high-frequency transistor according to embodiment 1. Fig. 2 is a circuit diagram of the high-frequency transistor according to embodiment 1.

[0016] A semiconductor layer 2 is formed on a semiconductor substrate 1. The material of the semiconductor substrate 1 is silicon, silicon carbide, gallium arsenide, gallium nitride, etc. For example, the semiconductor substrate 1 is a silicon carbide substrate, and the semiconductor layer 2 is a gallium nitride layer. The semiconductor substrate 1 is mounted on a ground metal 4 of a package with solder 3.

[0017] A plurality of unit transistors 5 are provided in a semiconductor layer 2 on a semiconductor substrate 1. The unit transistors 5 are connected in parallel to one another. In FIG. 2, four unit transistors 5 are connected in parallel. The unit transistors 5 are high electron mobility transistors or metal-oxide-semiconductor field effect transistors, etc.

[0018] Each unit transistor 5 has a gate electrode 6, a drain electrode, and a source electrode disposed on the semiconductor layer 2. The gate electrode 6 is disposed between the drain electrode and the source electrode. The gate electrode 6, drain electrode, and source electrode are formed on the semiconductor layer 2 using a vacuum deposition method or a sputtering method, using a metal such as gold.

[0019] A plurality of capacitors 7 are connected to the gate electrodes 6 of the plurality of unit transistors 5 via gate wiring 8. A plurality of resistors 9 are connected in parallel to the plurality of capacitors 7. A CR circuit in which the capacitors 7 and resistors 9 are connected in parallel functions as a stabilization circuit that suppresses oscillation.

[0020] Pads 10 and 11 are provided on the upper surface of semiconductor substrate 1 and are connected to one end and the other end of resistor 9, respectively. Silicon substrate 12 is disposed above semiconductor substrate 1. Pads 13 and 14 are provided on silicon substrate 12. Gold bump 15 connects pad 10 to pad 13. Gold bump 16 connects pad 11 to pad 14. Pads 13 and 14 contact the lower surface of silicon substrate 12 and face each other with a space between them. The distance between pads 13 and 14 is approximately the same as the length of resistor 9, for example, 10 microns to 300 microns. Pads 10, 11, 13, and 14 are made of the same metal as gate wiring 8.

[0021] Unlike substrates used in CMOS and other devices, silicon substrate 12 is used as a lid for wafer-level chip-size packages, and therefore is not intentionally doped with impurities. Therefore, silicon substrate 12 is insulating at room temperature, so no current flows between pads 13 and 14 even when a high-frequency signal or bias voltage is input to pads 10 and 11. On the other hand, when silicon substrate 12 is heated by unit transistors 5 that have reached a high temperature, silicon substrate 12 becomes more conductive. Therefore, path 17, through which an electrical signal passes, is generated on the surface of silicon substrate 12 between pads 13 and 14, as shown by the dotted line in Figure 1. This connects path 17 in parallel with resistor 9, thereby reducing the resistance of the resistors that make up the stabilization circuit.

[0022] If the resistance value of the resistor in the stabilization circuit is high, the input high-frequency signal will preferentially pass through the capacitor 7, which has low loss. This allows the corresponding unit transistor 5 to maintain a high gain. On the other hand, if the resistance value of the resistor in the stabilization circuit is low, the input high-frequency signal will preferentially pass through the resistor and be attenuated, resulting in a low gain for the corresponding unit transistor 5.

[0023] Next, the effects of this embodiment will be explained in comparison with a comparative example. Fig. 3 is a cross-sectional view of a high-frequency transistor according to the comparative example. Fig. 4 is a circuit diagram of a high-frequency transistor according to the comparative example. The comparative example does not have pads 10, 11 and a silicon substrate 12. Of the multiple unit transistors 5 arranged in a row, the unit transistor 5 located in the center becomes hot, while the unit transistors 5 on both ends become cold, resulting in an uneven temperature distribution. Because transistor characteristics change with temperature, the multiple unit transistors 5 operate unevenly, resulting in a decrease in power added efficiency, etc. If the temperature unevenness becomes significant, the unit transistor 5 in the center may become extremely hot, potentially causing damage.

[0024] In contrast, in this embodiment, pads 13 and 14 are electrically connected to each other via the lower surface layer of silicon substrate 12, which is heated by the heat from the corresponding unit transistors 5. This connects path 17 in parallel to resistor 9, reducing the resistance of the resistors that make up the stabilization circuit and further attenuating the high-frequency signal. This behavior occurs more significantly in the central unit transistor 5 and its stabilization circuit, which become hotter, so that multiple unit transistors 5 approach the same temperature. This makes it possible to suppress temperature non-uniformity in multiple unit transistors 5, thereby improving transistor performance such as power added efficiency.

[0025] Furthermore, if a bias circuit including a thermistor were provided for every unit transistor, as in the prior art, the area of the semiconductor substrate would increase by several hundred to several thousand microns square in total. In contrast, in this embodiment, it is only necessary to provide pads 10, 11, each several tens of microns square, on semiconductor substrate 1 for mounting gold bumps 15, 16, so the increase in area of expensive semiconductor substrate 1, such as silicon carbide or gallium nitride, is minimal. This makes it possible to improve transistor performance while suppressing increases in cost.

[0026] In this embodiment, there is no need to precisely predict the amount of temperature rise of the unit transistors 5 during operation, and the temperatures of multiple unit transistors 5 automatically approach uniformity regardless of the ambient temperature, bias voltage, etc. Furthermore, this embodiment is not dependent on the type and configuration of the bias circuit that drives the transistors, so the type and configuration of the bias circuit can be freely selected.

[0027] If it is desired to suppress the reduction in gain of the entire high-frequency transistor, pads 10, 11 and gold bumps 15, 16 may be provided only on the stabilization circuit connected to the central unit transistor 5. In other words, pads 10, 11 and gold bumps 15, 16 should be provided on at least the stabilization circuit connected to the central unit transistor 5 among the multiple unit transistors 5 arranged in a row.

[0028] The resistance value of resistor 9 in the stabilization circuit at which the attenuation rate of the high-frequency signal begins to decrease depends on the frequency of the high-frequency signal, the capacitance value of capacitor 7 in the stabilization circuit, and the load impedance around the stabilization circuit. If the frequency of the high-frequency signal is 10 GHz and the capacitance value of capacitor 7 in the stabilization circuit is 10 picofarads, the attenuation rate of the high-frequency signal will decrease when the resistance value of resistor 9 in the stabilization circuit decreases to about 1 ohm. Therefore, for the attenuation rate of the high-frequency signal to begin to decrease, the resistance of path 17 inside silicon substrate 12 must decrease to at least the order of 1 ohm. However, in reality, the resistance of path 17 in silicon substrate 12 does not decrease to the order of 1 ohm. For example, suppose pads 13 and 14 are spaced 20 micrometers apart, forming path 17 with a cross-sectional area of 1,000 square micrometers. In this case, for the resistance of path 17 to decrease to 1 ohm, the conductivity of silicon substrate 12 must increase to 20,000 siemens per meter. When the intrinsic carrier concentration and conductivity in silicon are calculated using the band gap of silicon, 1.1 electron volts, this conductivity is reached when the silicon substrate 12 is heated to approximately 1000°C. However, the temperature at which a transistor generates heat and is damaged is at most about 300°C, and the silicon substrate 12 does not heat up to 1000°C. In this way, since the temperature of the transistor does not rise to a temperature at which the attenuation rate of a high-frequency signal begins to decrease, it is not necessary to consider the reversal of the attenuation rate from an increase to a decrease in this embodiment.

[0029] Semiconductor chips that form high-frequency transistors are encapsulated in packages made of metal or other materials to prevent moisture intrusion. In many cases, these metal packages have an area several times larger than that of the semiconductor chip. In recent years, packages have been created in which the semiconductor chip and silicon substrate are bonded together with gold bumps. These packages have the same area as the semiconductor chip and are called wafer-level chip-size packages. By tightly mounting gold bumps around the periphery of the semiconductor chip, a gold wall that prevents moisture intrusion is created. In this embodiment, gold bumps that do not pass electrical signals may also be mounted tightly to bond the periphery of semiconductor substrate 1 and the periphery of silicon substrate 12 together. On the other hand, if the entire device is sealed in a metal package, gold bumps around the periphery of the chip are not necessarily required.

[0030] Embodiment 2 Fig. 5 is a cross-sectional view showing a high-frequency transistor according to embodiment 2. Fig. 6 is a bottom view showing a silicon substrate according to embodiment 2. The area surrounded by a dashed line in Fig. 6 indicates the position where unit transistors 5 covered by silicon substrate 12 are arranged.

[0031] Metal wirings 18 and 19 are provided on the underside of the silicon substrate 12 and are arranged so as not to contact each other. One end of the metal wiring 18 is connected to the pad 13. One end of the metal wiring 19 is connected to the pad 14. The other ends of the metal wirings 18 and 19 are arranged directly above the corresponding unit transistors 5, contact the underside of the silicon substrate 12, and face each other at a distance.

[0032] Because the gold bumps 15, 16 are spherical with a diameter of several tens of microns, the distance between the unit transistor 5 and the silicon substrate 12 is also several tens of microns. Air exists between the unit transistor 5 and the silicon substrate 12. Although air has low thermal conductivity, the unit transistor 5 and the silicon substrate 12 are close to each other, so heat is transferred from the unit transistor 5 to the silicon substrate 12 via the air. Therefore, the temperature of the lower surface layer of the silicon substrate 12 directly above the unit transistor 5 reacts sensitively to a rise in temperature of the unit transistor 5.

[0033] The other ends of the metal wiring 18 and the other ends of the metal wiring 19 are electrically connected to each other via the lower surface layer of the silicon substrate 12 that is heated by the heat from the corresponding unit transistors 5. This provides the function of suppressing temperature non-uniformity among the multiple unit transistors 5, as in the first embodiment. Note that by adjusting the diameter of the gold bumps 15, 16, it is possible to adjust the temperature at which the temperature equalization function begins to function.

[0034] Furthermore, one of the factors that determine the resistance value of the path 17 between the other end of the wiring metal 18 and the other end of the wiring metal 19 is the length of the path 17. In the first embodiment, the path length is the distance between the pads 10 and 11, and is generally determined by the length of the resistor 9. On the other hand, in the present embodiment, the length of the path 17 is the distance between the other end of the wiring metal 18 and the other end of the wiring metal 19 at their closest points. Therefore, the length and resistance value of the path 17 can be adjusted by changing the shapes of the wiring metals 18 and 19. The resistance value of the path 17 can be reduced by bringing the wiring metals 18 and 19 closer to each other within the range permitted by the process rules. The distance between the other end of the wiring metal 18 and the other end of the wiring metal 19 at their closest points is, for example, 1 to 2 microns or more.

[0035] The shape of the metal wiring 18, 19 can also be changed to change the distance between the transistor and the location where the path 17 is formed. This can also change the temperature of the unit transistor 5 at which the temperature equalization function begins to operate. Note that the shapes of the metal wiring 18, 19 do not need to be the same for all unit transistors 5. For example, by locating the location where the path 17 is formed directly above the heat-generating area in the central unit transistor 5 and locating the location where the path 17 is formed away from the heat-generating area in the unit transistors 5 on both ends, it is possible to cause a stronger reduction in gain in the central unit transistor 5.

[0036] Embodiment 3 Fig. 7 is a cross-sectional view showing a high-frequency transistor according to embodiment 3. Fig. 8 is a top view showing a silicon substrate according to embodiment 3. Metal wirings 18 and 19 are formed on the top surface of silicon substrate 12 and are arranged so as not to contact each other.

[0037] Through holes that penetrate from the top surface to the bottom surface are formed by processing the silicon substrate 12. The vias 20 to 23 are cylindrical metals that fill the insides of the through holes that penetrate the silicon substrate 12 from top to bottom, or cylindrical metals that are plated onto the side surfaces of the through holes.

[0038] Via 20 connects one end of wiring metal 18 on the upper surface of the substrate to pad 13 on the lower surface of the substrate. Via 21 connects one end of wiring metal 19 on the upper surface of the substrate to pad 14 on the lower surface of the substrate. The upper end of via 22 is connected to the other end of wiring metal 18. The upper end of via 23 is connected to the other end of wiring metal 19.

[0039] The bottom ends of vias 22 and 23 are located directly above the corresponding unit transistors 5 on the underside of silicon substrate 12, in contact with silicon substrate 12, and facing each other with a gap between them. The rest of the configuration is the same as in embodiment 1 or 2.

[0040] The bottom ends of the vias 22 and 23 are electrically connected to each other via the lower surface layer of the silicon substrate 12, which is heated by the heat from the corresponding unit transistors 5. This provides the same function as in the first embodiment of the present invention of suppressing temperature non-uniformity among the plurality of unit transistors 5.

[0041] Forming the wiring metals 18 and 19 on the top surface of the silicon substrate 12 facilitates wire bonding. For example, by wire bonding to the wiring metal on the top surface of the substrate, a high-frequency signal or gate bias voltage can be input to the transistor from the upper wire instead of a pad. This increases the degree of freedom in how high-frequency transistors are mounted in communications equipment or radar devices.

[0042] Furthermore, by forming the wiring metals 18 and 19 on the upper surface of the silicon substrate 12, it becomes possible to add surface-mount devices such as chip resistors or chip capacitors. Therefore, even after the wafer-level chip-size package is fabricated and the semiconductor substrate 1 is covered with the silicon substrate 12, the resistance value or capacitance value of the stabilization circuit can be changed.

[0043] One of the wiring metals 18 and 19 may be formed on the upper surface of the silicon substrate 12, and the other may be formed on the lower surface of the silicon substrate 12. That is, if the pad 13, the wiring metal 18, and the vias 20 and 22 are defined as a first conductor, and the pad 14, the wiring metal 19, and the vias 21 and 23 are defined as a second conductor, it is sufficient that a part of the first conductor or the second conductor extends on the upper surface of the silicon substrate 12.

[0044] Although the preferred embodiments have been described above in detail, the present disclosure is not limited to the above-described embodiments, and various modifications and substitutions can be made to the above-described embodiments without departing from the scope of the claims. Various aspects of the present disclosure are summarized below as appendices. (Appendix 1) a semiconductor substrate; a plurality of unit transistors provided on the semiconductor substrate and connected in parallel; a plurality of capacitors respectively connected to the gate electrodes of the plurality of unit transistors; a plurality of resistors connected in parallel to the plurality of capacitors, respectively; first and second pads provided on the upper surface of the semiconductor substrate and connected to one end and the other end, respectively, of the resistor connected to at least a central unit transistor among the plurality of unit transistors arranged in a row; a silicon substrate disposed above the semiconductor substrate; first and second conductors provided on the silicon substrate; a first bump connecting the first pad and one end of the first conductor; a second bump connecting the second pad and one end of the second conductor; a high frequency transistor, wherein the other end of the first conductor and the other end of the second conductor are in contact with the silicon substrate and are spaced apart from each other and face each other; (Appendix 2) The high-frequency transistor according to claim 1, wherein the other end of the first conductor and the other end of the second conductor are electrically connected to each other via the silicon substrate heated by heat from the corresponding unit transistor. (Appendix 3) 3. The high-frequency transistor according to claim 1, wherein the other end of the first conductor and the other end of the second conductor are disposed directly above the corresponding unit transistor. (Appendix 4) 4. The high frequency transistor according to any one of claims 1 to 3, wherein a part of the first conductor or the second conductor extends onto an upper surface of the silicon substrate. [Explanation of symbols]

[0045] 1 Semiconductor substrate, 5 Unit transistor, 6 Gate electrode, 7 Capacitor, 9 Resistor, 10, 11, 13, 14 Pad, 12 Silicon substrate, 15, 16 Gold bump, 18, 19 Wiring metal, 20-23 Via

Claims

1. a semiconductor substrate; a plurality of unit transistors provided on the semiconductor substrate and connected in parallel; a plurality of capacitors respectively connected to the gate electrodes of the plurality of unit transistors; a plurality of resistors connected in parallel to the plurality of capacitors, respectively; first and second pads provided on the upper surface of the semiconductor substrate and connected to one end and the other end, respectively, of the resistor connected to at least a central unit transistor among the plurality of unit transistors arranged in a row; a silicon substrate disposed above the semiconductor substrate; first and second conductors provided on the silicon substrate; a first bump connecting the first pad and one end of the first conductor; a second bump connecting the second pad and one end of the second conductor; a second end of the first conductor and a second end of the second conductor contacting the silicon substrate and facing each other with a gap therebetween;

2. 2. The high-frequency transistor according to claim 1, wherein the other end of the first conductor and the other end of the second conductor are electrically connected to each other via the silicon substrate heated by heat from the corresponding unit transistor.

3. 3. A high frequency transistor according to claim 1, wherein the other end of the first conductor and the other end of the second conductor are disposed directly above the corresponding unit transistor.

4. 3. The high frequency transistor according to claim 1, wherein a portion of the first conductor or the second conductor extends onto an upper surface of the silicon substrate.

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