Operational amplifier circuit

Abstract

To provide an operational amplifier circuit capable of operating in a wide input voltage range.SOLUTION: A third transistor M3 is connected between a first transistor M1 which is one of a differential pair 112 and a load circuit 116, and a fourth transistor M4 is connected between a second transistor M2 which is the other of the differential pair 112 and the load circuit 116. A first control circuit 150 supplies a gate voltage Vg3 which has a positive correlation with a first input signal Vinp to a gate of the third transistor M3, and supplies a gate voltage Vg4 which has a positive correlation with a second input signal Vinn to a gate of the fourth transistor M4. A second control circuit 160 turns on a fifth transistor M5 and a sixth transistor M6 if at least one of the first input signal Vinp and the second input signal Vinn is lower than a predetermined threshold value.SELECTED DRAWING: Figure 1

Description

[Technical Field]

[0001] The present disclosure relates to operational amplifier circuits. [Background technology]

[0002] An operational amplifier has a differential input stage and an output stage. The circuit format of the differential input stage is selected and designed depending on the desired operating range.

[0003] In an input stage that uses P-type (P-channel) MOS transistors as differential inputs, if you want to expand the operating voltage range toward the ground voltage, the drain voltage of the differential input transistor is generally fixed low. [Prior art documents] [Patent documents]

[0004] [Patent Document 1] Japanese Patent Application Publication No. 2023-134535

[0005] In such a configuration, if it is desired to widen the operating voltage range to the power supply voltage side, the differential input transistors must be configured with high-voltage elements, which is a factor in increasing costs.

[0006] A similar problem can occur in an input stage that uses N-type (N-channel) MOS transistors as differential inputs.

[0007] [overview] The present disclosure has been made in this situation, and one exemplary purpose of an embodiment thereof is to provide an operational amplifier circuit that can operate over a wide input voltage range.

[0008] An operational amplifier circuit according to an embodiment of the present disclosure includes a differential input stage including a differential pair including a first P-type transistor receiving at its gate a first input signal that is one of the differential input signals and a second P-type transistor receiving at its gate a second P-type input signal that is the other of the differential input signals, a tail current source that sources a tail current, a load circuit, a third P-type transistor connected between the first transistor and the load circuit, a fourth P-type transistor connected between the second transistor and the load circuit, a fifth transistor connected in parallel with the third transistor, and a sixth transistor connected in parallel with the fourth transistor, a first control circuit that supplies a gate voltage that is positively correlated with the first input signal to the gate of the third transistor and a gate voltage that is positively correlated with the second input signal to the gate of the fourth transistor, and a second control circuit that turns on the fifth and sixth transistors when at least one of the first and second input signals is lower than a predetermined threshold.

[0009] Another embodiment of the present disclosure is also an operational amplifier circuit comprising a differential input stage including a differential pair including a first N-type transistor receiving at its gate a first input signal that is one of differential input signals and a second N-type transistor receiving at its gate a second input signal that is the other of the differential input signals, a tail current source that sinks a tail current, a load circuit, a third N-type transistor connected between the first transistor and the load circuit, a fourth N-type transistor connected between the second transistor and the load circuit, a fifth transistor connected in parallel with the third transistor, and a sixth transistor connected in parallel with the fourth transistor, a first control circuit that supplies a gate voltage that has a positive correlation with the first input signal to the gate of the third transistor and a gate voltage that has a positive correlation with the second input signal to the gate of the fourth transistor, and a second control circuit that turns on the fifth transistor and the sixth transistor when at least one of the first input signal and the second input signal is higher than a predetermined threshold.

[0010] Any combination of the above components, or mutual substitution of components or expressions between methods, devices, systems, etc. are also valid aspects of the present invention. [Brief explanation of the drawings]

[0011] [Figure 1] FIG. 1 is a circuit diagram of an operational amplifier circuit according to an embodiment. [Figure 2] FIG. 2 is a circuit diagram of an operational amplifier circuit according to a comparative technique. [Figure 3] FIG. 3 is a circuit diagram of an operational amplifier circuit according to the first embodiment. [Figure 4] FIG. 4 is a circuit diagram of an operational amplifier circuit according to a second embodiment. [Figure 5] FIG. 5 is a circuit diagram of an operational amplifier circuit according to a third embodiment.

[0012] [Detailed explanation] (Outline of the embodiment) A summary of some exemplary embodiments of the present disclosure is provided. This summary is intended to provide a simplified overview of some concepts of one or more embodiments in order to provide a basic understanding of the embodiments as a prelude to the more detailed description that follows. It is not intended to limit the scope of the invention or disclosure. This summary is not an exhaustive overview of all possible embodiments, and is not intended to identify key elements of all embodiments or to delineate the scope of some or all aspects. For convenience, the term "one embodiment" may refer to one embodiment (example or variant) or multiple embodiments (examples or variants) disclosed herein.

[0013] An operational amplifier circuit according to one embodiment includes a differential input stage including a differential pair including a first P-type transistor receiving at its gate a first input signal that is one of the differential input signals and a second P-type transistor receiving at its gate a second input signal that is the other of the differential input signals, a tail current source that sources a tail current, a load circuit, a third P-type transistor connected between the first transistor and the load circuit, a fourth P-type transistor connected between the second transistor and the load circuit, a fifth transistor connected in parallel with the third transistor, and a sixth transistor connected in parallel with the fourth transistor, a first control circuit that supplies a gate voltage that is positively correlated with the first input signal to the gate of the third transistor and a gate voltage that is positively correlated with the second input signal to the gate of the fourth transistor, and a second control circuit that turns on the fifth and sixth transistors when at least one of the first and second input signals is lower than a predetermined threshold.

[0014] According to this embodiment, the first transistor, which is one of the differential pair, adjusts the gate voltage of the third transistor in response to the first input signal. When the first input signal rises, the drain voltage of the first transistor rises in response to the gate voltage of the first input signal. This prevents a high voltage from being applied to the first transistor, allowing the first transistor to be configured using a low-voltage element. On the other hand, when the first input signal falls, the fifth transistor turns on, bypassing the third transistor, allowing the stage to operate similarly to a conventional differential input stage. The same applies to the other member of the differential pair.

[0015] In one embodiment, the first control circuit may include a first source follower circuit including an N-type seventh transistor that receives the first input signal at its gate and supplies a source voltage of the seventh transistor to the gate of the third transistor, and a second source follower circuit including an N-type eighth transistor that receives the second input signal at its gate and supplies a source voltage of the eighth transistor to the gate of the fourth transistor.

[0016] In one embodiment, the first source follower circuit may include a first current source connected to the source of the seventh transistor and configured to sink a constant current, and the second source follower circuit may include a second current source connected to the source of the eighth transistor and configured to sink a constant current.

[0017] In one embodiment, the second control circuit includes a third current source that sources a constant current, a P-type ninth transistor having a gate that receives the first input signal, a source connected to the third current source, and a drain that is grounded, and a P-type tenth transistor having a gate that receives the second input signal, a source connected to the third current source, and a drain that is grounded, and may turn on the fifth transistor and the sixth transistor when a detection voltage generated at the commonly connected sources of the ninth transistor and the tenth transistor is lower than a predetermined voltage.

[0018] In one embodiment, the second control circuit may include a comparator that compares the detected voltage with a predetermined voltage, and may control the fifth transistor and the sixth transistor according to the output of the comparator.

[0019] In one embodiment, the second control circuit may include an inverter that receives the detection voltage, and control the fifth transistor and the sixth transistor according to the output of the inverter.

[0020] In one embodiment, the fifth and sixth transistors may be N-type.

[0021] An operational amplifier circuit according to one embodiment includes a differential input stage including a differential pair including a first N-type transistor receiving at its gate a first input signal that is one of the differential input signals and a second N-type transistor receiving at its gate a second input signal that is the other of the differential input signals, a tail current source that sinks a tail current, a load circuit, a third N-type transistor connected between the first transistor and the load circuit, a fourth N-type transistor connected between the second transistor and the load circuit, a fifth transistor connected in parallel with the third transistor, and a sixth transistor connected in parallel with the fourth transistor, a first control circuit that supplies a gate voltage that is positively correlated with the first input signal to the gate of the third transistor and a gate voltage that is positively correlated with the second input signal to the gate of the fourth transistor, and a second control circuit that turns on the fifth and sixth transistors when at least one of the first and second input signals is higher than a predetermined threshold.

[0022] According to this embodiment, the first transistor, which is one of the differential pair, adjusts the gate voltage of the third transistor in response to the first input signal. When the first input signal decreases, the drain voltage of the first transistor decreases in accordance with the gate voltage of the first input signal. This prevents a high voltage from being applied to the first transistor, allowing the first transistor to be configured as a low-voltage element. On the other hand, when the first input signal increases, the fifth transistor turns on, bypassing the third transistor, and operating in the same manner as a conventional differential input stage. The same is true for the other of the differential pair.

[0023] In one embodiment, the first control circuit may include a first source follower circuit including a P-type seventh transistor that receives the first input signal at its gate and supplies a source voltage of the seventh transistor to the gate of the third transistor, and a second source follower circuit including a P-type eighth transistor that receives the second input signal at its gate and supplies a source voltage of the eighth transistor to the gate of the fourth transistor.

[0024] In one embodiment, the first source follower circuit may include a first current source connected to the source of the seventh transistor and configured to source a constant current, and the second source follower circuit may include a second current source connected to the source of the eighth transistor and configured to source a constant current.

[0025] In one embodiment, the second control circuit includes a third current source that sources a constant current, a P-type ninth transistor having a gate that receives the first input signal, a source connected to the third current source, and a drain connected to a power supply line, and a P-type tenth transistor having a gate that receives the second input signal, a source connected to the third current source, and a drain connected to the power supply line, and may turn on the fifth transistor and the sixth transistor when a detection voltage generated at the commonly connected sources of the ninth transistor and the tenth transistor is higher than a predetermined voltage.

[0026] In one embodiment, the second control circuit may include a comparator that compares the detected voltage with a predetermined voltage, and may control the fifth transistor and the sixth transistor according to the output of the comparator.

[0027] In one embodiment, the second control circuit may include an inverter that receives the detection voltage, and control the fifth transistor and the sixth transistor according to the output of the inverter.

[0028] In one embodiment, the fifth and sixth transistors may be P-type.

[0029] (Embodiment) The present disclosure will be described below with reference to the drawings based on preferred embodiments. The same or equivalent components, parts, and processes shown in each drawing will be given the same reference numerals, and redundant explanations will be omitted as appropriate. Furthermore, the embodiments are examples rather than limitations on the invention or disclosure, and all features and combinations thereof described in the embodiments are not necessarily essential to the invention or disclosure.

[0030] In this specification, "a state in which component A is connected to component B" includes not only a case in which component A and component B are directly physically connected to each other, but also a case in which component A and component B are indirectly connected to each other via other components that do not substantially affect the electrical connection between them or impair the functions or effects achieved by their combination.

[0031] Similarly, "a state in which component C is provided between component A and component B" includes not only a case in which component A and component C, or component B and component C, are directly connected, but also a case in which they are indirectly connected via other components that do not substantially affect the electrical connection state between them or impair the functions or effects achieved by their combination.

[0032] 1 is a circuit diagram of an operational amplifier circuit 100 according to an embodiment. The operational amplifier circuit 100 includes a differential input stage 110 and an output stage 130. A gain stage may be inserted between the differential input stage 110 and the output stage 130.

[0033] The differential input stage 110 includes a differential pair 112, a tail current source 114, a load circuit 116, a third transistor M3, a fourth transistor M4, a fifth transistor M5, a sixth transistor M6, a first control circuit 150, and a second control circuit 160.

[0034] The differential pair 112 includes a first transistor M1 and a second transistor M2, both of which are P-type (P-channel MOSFETs). A first input signal Vinp, which is one of the differential input signals, is input to the gate of the first transistor M1, and a second input signal Vinn, which is the other of the differential input signals, is input to the gate of the second transistor M2.

[0035] The tail current source 114 is connected to the sources of the first transistor M1 and the second transistor M2 and sources a tail current It.

[0036] The load circuit 116 is a current mirror load or a resistive load, and is connected to the ground line.

[0037] The third transistor M3 is of the same type as the first transistor M1, i.e., P-type, and is connected between the first transistor M1 and the load circuit 116. The fourth transistor M4 is of the same type as the second transistor M2, i.e., P-type, and is connected between the second transistor M2 and the load circuit 116.

[0038] The fifth transistor M5 is connected in parallel with the third transistor M3. The sixth transistor M6 is connected in parallel with the fourth transistor M4. In this embodiment, the fifth transistor M5 and the sixth transistor M6 are N-type.

[0039] The first control circuit 150 supplies a gate voltage Vg3, which has a positive correlation with the first input signal Vinp, to the gate of the third transistor M3. That is, when the first input signal Vinp increases, the first control circuit 150 increases the gate voltage Vg3 of the third transistor M3 in accordance with the first input signal Vinp.

[0040] Similarly, the first control circuit 150 supplies a gate voltage Vg4 having a positive correlation with the second input signal Vinn to the gate of the fourth transistor M4. That is, when the second input signal Vinn rises, the first control circuit 150 raises the gate voltage Vg4 of the fourth transistor M3 in accordance with the second input signal Vinn.

[0041] The second control circuit 160 turns on the fifth transistor M5 and the sixth transistor M6 when at least one of the first input signal Vinp and the second input signal Vinn is lower than a predetermined threshold value.

[0042] The above is the configuration of the operational amplifier circuit 100. Next, its operation will be explained in comparison with the comparative technology.

[0043] 2 is a circuit diagram of an operational amplifier circuit 100R according to a comparative technique. In a differential input stage 110R of the operational amplifier circuit 100R, a load circuit 116 is directly connected to the drain of a first transistor M1. It should be noted that the operational amplifier circuit 100R operates in a state where the potential difference between differential input signals Vinp and Vinn is small.

[0044] When the input voltage Vinp rises, the source voltage Vs1 of the first transistor M1 rises. On the other hand, the drain voltage Vd1 of the first transistor M1 is set low so that the transistor M1 can operate even when the input voltages Vinp and Vinn are low. Therefore, when the input voltage Vinp rises, the drain-source voltage of the first transistor M1 increases. For this reason, the first transistor M1 must be configured with a high-voltage element. The same applies to the second transistor M2.

[0045] Returning to FIG. 1, the operation of the operational amplifier circuit 100 according to the embodiment will be described.

[0046] In this embodiment, when the first input voltage Vinp increases, the first control circuit 150 increases the gate voltage Vg3 of the third transistor M3. This increases the source voltage of the third transistor M3, i.e., the drain voltage Vd1 of the first transistor M1. This prevents the drain-source voltage of the first transistor M1 from increasing when the first input voltage Vinp increases. This eliminates the need for a high-voltage element in the first transistor M1. Eliminating the need for a high-voltage element is advantageous in terms of high-speed operation and also in terms of cost, as it enables the selection of an inexpensive manufacturing process.

[0047] The same applies to the second transistor M2.

[0048] The present disclosure covers various devices and methods that can be understood as the block diagram or circuit diagram of Figure 1 or derived from the above description, and is not limited to a specific configuration. Below, more specific configuration examples and examples will be described not to narrow the scope of the present disclosure, but to aid in understanding and clarify the essence and operation of the present disclosure and the present invention.

[0049] Example 1 FIG. 3 is a circuit diagram of an operational amplifier circuit 100A according to the first embodiment.

[0050] The first control circuit 150 includes a first source follower circuit 152 and a second source follower circuit 154. The first source follower circuit 152 includes a seventh transistor M7. A first input signal Vinp is input to the gate of the seventh transistor M7, and a first current source CS1 that sinks a constant current is connected to the source of the seventh transistor M7 as a load. The load may be a resistive load. The first source follower circuit 152 supplies a source voltage Vd7 of the seventh transistor M7 to the gate of the third transistor M3. Vd7=Vinp-Vgs Vgs is the gate-source voltage of the seventh transistor M7.

[0051] The second source follower circuit 154 includes an eighth transistor M8. A second input signal Vinn is input to the gate of the eighth transistor M8, and a second current source CS2 that sinks a constant current is connected to the source of the eighth transistor M8 as a load. The load may be a resistive load. The second source follower circuit 154 supplies a source voltage Vd8 of the eighth transistor M8 to the gate of the fourth transistor M4. Vd8=Vinn-Vgs Vgs is the gate-source voltage of the eighth transistor M8.

[0052] The first control circuit 150A controls the gate voltage of the third transistor M3 in response to the first input signal Vinp, thereby enabling the drain voltage of the first transistor M1 to follow the first input signal Vinp. Similarly, the first control circuit 150A controls the gate voltage of the fourth transistor M4 in response to the second input signal Vinn, thereby enabling the drain voltage of the second transistor M2 to follow the second input signal Vinn.

[0053] The second control circuit 160A includes a third current source CS3, a ninth transistor M9, a tenth transistor M10, and a comparator COMP1. The third current source CS3 sources a constant current. The ninth transistor M9 receives the first input signal Vinp at its gate, has a source connected to the third current source CS3, and a drain grounded. The tenth transistor M10 receives the second input signal Vinn at its gate, has a source connected to the third current source CS3, and a drain grounded.

[0054] The second control circuit 160A turns on the fifth transistor M5 and the sixth transistor M6 when the detection voltage Vs generated at the commonly connected sources of the ninth transistor M9 and the tenth transistor M10 is lower than a predetermined voltage Vth. The comparator COMP1 compares the detection voltage Vs with the predetermined voltage Vth and calculates the difference between Vs<Vthのときにハイ、Vs> The control signal / BYPASS is supplied to the gates of the fifth transistor M5 and the sixth transistor M6.

[0055] When the first input signal Vinp and the second input signal Vinn are both relatively high, the ninth transistor M9 and the tenth transistor M10 are both off, the detection voltage Vs is high, and the control signal / BYPASS output from the comparator COMP1 is low, turning off the fifth transistor M5 and the sixth transistor M6.

[0056] When at least one of the first input signal Vinp and the second input signal Vinn drops, the ninth transistor M9 or the tenth transistor M10 becomes conductive, causing the detection voltage Vs to drop. When the detection voltage Vs drops below the threshold voltage Vth, the control signal / BYPASS goes high, turning on the fifth transistor M5 and the sixth transistor M6. This bypasses the third transistor M3 and the fourth transistor M4, causing the differential input stage 110A to operate in the same manner as the differential input stage 110R according to the comparative technique.

[0057] The comparator COMP1 may be replaced with an inverter (negation gate).

[0058] Example 2 4 is a circuit diagram of an operational amplifier circuit 100B according to Example 2. The operational amplifier circuit 100B has a configuration in which the P-type and N-type transistors of the operational amplifier circuit 100 in FIG. 1 are swapped and the top and bottom (power supply line and ground line) are inverted.

[0059] The first control circuit 150B supplies a gate voltage Vg3 having a positive correlation with the first input signal Vinp to the gate of the third transistor M3, and supplies a gate voltage Vg4 having a positive correlation with the second input signal Vinn to the gate of the fourth transistor M4.

[0060] The second control circuit 160B turns on the fifth transistor M5 and the sixth transistor M6 when at least one of the first input signal Vinp and the second input signal Vinn is higher than a predetermined threshold value.

[0061] In the second embodiment, when the first input voltage Vinp decreases, the first control circuit 150B decreases the gate voltage Vg3 of the third transistor M3. This decreases the source voltage of the third transistor M3, i.e., the drain voltage Vd1 of the first transistor M1. This prevents the drain-source voltage of the first transistor M1 from increasing when the first input voltage Vinp decreases. This eliminates the need for a high-voltage element in the first transistor M1. Eliminating the need for a high-voltage element is advantageous in terms of high-speed operation and also in terms of cost, since it allows for the selection of an inexpensive manufacturing process. The same applies to the second transistor M2.

[0062] Example 3 5 is a circuit diagram of an operational amplifier circuit 100C according to Example 3. The operational amplifier circuit 100C has a configuration in which the P-type and N-type transistors of the operational amplifier circuit 100A according to Example 2 are swapped and the top and bottom (power supply line and ground line) are inverted.

[0063] The embodiments are merely examples, and it will be understood by those skilled in the art that there are various variations in the combination of each component and each treatment process, and that such variations are also included in the present disclosure and can constitute the scope of the present invention.

[0064] (Addendum) The present specification discloses the following techniques.

[0065] (Item 1) a differential input stage, the differential input stage comprising: a differential pair including a P-type first transistor receiving at its gate a first input signal which is one of differential input signals, and a P-type second transistor receiving at its gate a second input signal which is the other of the differential input signals; a tail current source for sourcing a tail current; A load circuit; a third P-type transistor connected between the first transistor and the load circuit; a fourth P-type transistor connected between the second transistor and the load circuit; a fifth transistor connected in parallel with the third transistor; a sixth transistor connected in parallel with the fourth transistor; a first control circuit that supplies a gate voltage having a positive correlation with the first input signal to a gate of the third transistor and supplies a gate voltage having a positive correlation with the second input signal to a gate of the fourth transistor; a second control circuit that turns on the fifth transistor and the sixth transistor when at least one of the first input signal and the second input signal is lower than a predetermined threshold; An operational amplifier circuit comprising:

[0066] (Item 2) The first control circuit is a first source follower circuit including an N-type seventh transistor receiving the first input signal at its gate, the first source follower circuit supplying a source voltage of the seventh transistor to the gate of the third transistor; a second source follower circuit including an N-type eighth transistor receiving the second input signal at its gate, the second source follower circuit supplying a source voltage of the eighth transistor to the gate of the fourth transistor; Item 2. The operational amplifier circuit of item 1, comprising:

[0067] (Item 3) the first source follower circuit is connected to a source of the seventh transistor and includes a first current source that sinks a constant current; 3. The operational amplifier circuit of claim 2, wherein the second source follower circuit includes a second current source connected to the source of the eighth transistor and sinking a constant current.

[0068] (Item 4) The second control circuit is a third current source that sources a constant current; a ninth P-type transistor having a gate receiving the first input signal, a source connected to the third current source, and a drain grounded; a tenth P-type transistor having a gate receiving the second input signal, a source connected to the third current source, and a drain grounded; and turning on the fifth transistor and the sixth transistor when a detection voltage generated at the commonly connected sources of the ninth transistor and the tenth transistor is lower than a predetermined voltage.

[0069] (Item 5) 5. The operational amplifier circuit of claim 4, wherein the second control circuit includes a comparator that compares the detection voltage with the predetermined voltage and controls the fifth transistor and the sixth transistor according to the output of the comparator.

[0070] (Item 6) 5. The operational amplifier circuit of claim 4, wherein the second control circuit includes an inverter that receives the detection voltage and controls the fifth transistor and the sixth transistor according to the output of the inverter.

[0071] (Item 7) 7. The operational amplifier circuit of any one of items 1 to 6, wherein the fifth transistor and the sixth transistor are N-type.

[0072] (Item 8) a differential input stage, the differential input stage comprising: a differential pair including a first N-type transistor receiving at its gate a first input signal which is one of the differential input signals, and a second N-type transistor receiving at its gate a second input signal which is the other of the differential input signals; a tail current source that sinks the tail current; A load circuit; a third N-type transistor connected between the first transistor and the load circuit; a fourth N-type transistor connected between the second transistor and the load circuit; a fifth transistor connected in parallel with the third transistor; a sixth transistor connected in parallel with the fourth transistor; a first control circuit that supplies a gate voltage having a positive correlation with the first input signal to a gate of the third transistor and supplies a gate voltage having a positive correlation with the second input signal to a gate of the fourth transistor; a second control circuit that turns on the fifth transistor and the sixth transistor when at least one of the first input signal and the second input signal is higher than a predetermined threshold; An operational amplifier circuit comprising:

[0073] (Item 9) The first control circuit is a first source follower circuit including a P-type seventh transistor receiving the first input signal at its gate, the first source follower circuit supplying a source voltage of the seventh transistor to the gate of the third transistor; a second source follower circuit including an eighth P-type transistor receiving the second input signal at its gate, the second source follower circuit supplying a source voltage of the eighth transistor to the gate of the fourth transistor; 9. The operational amplifier circuit of claim 8, comprising:

[0074] (Item 10) the first source follower circuit is connected to a source of the seventh transistor and includes a first current source that sources a constant current; 10. The operational amplifier circuit of claim 9, wherein the second source follower circuit includes a second current source connected to the source of the eighth transistor and sourcing a constant current.

[0075] (Item 11) The second control circuit is a third current source that sources a constant current; a ninth P-type transistor having a gate receiving the first input signal, a source connected to the third current source, and a drain connected to a power supply line; a tenth P-type transistor having a gate receiving the second input signal, a source connected to the third current source, and a drain connected to the power supply line; and turning on the fifth transistor and the sixth transistor when a detection voltage generated at the commonly connected sources of the ninth transistor and the tenth transistor is higher than a predetermined voltage.

[0076] (Item 12) 12. The operational amplifier circuit of claim 11, wherein the second control circuit includes a comparator that compares the detection voltage with the predetermined voltage and controls the fifth transistor and the sixth transistor according to the output of the comparator.

[0077] (Item 13) 12. The operational amplifier circuit of claim 11, wherein the second control circuit includes an inverter that receives the detection voltage and controls the fifth transistor and the sixth transistor according to the output of the inverter.

[0078] (Item 14) 14. The operational amplifier circuit of any of items 8 to 13, wherein the fifth transistor and the sixth transistor are P-type. [Explanation of symbols]

[0079] 100 Op-amp Circuits 110 Differential Input Stage 112 differential pair 114 Tail Current Source 116 Load circuit 130 Output Stage M1 First transistor M2 Second transistor M3 Third transistor M4 4th transistor M5 Fifth transistor M6 6th transistor M7 Seventh transistor M8 8th transistor M9 9th transistor M10 10th transistor 150 First control circuit CS1 1st current source CS2 2nd current source 152 First source follower circuit 154 Second Source Follower Circuit 160 Second control circuit CS3 Third current source COMP1 comparator

Claims

1. a differential input stage, the differential input stage comprising: a differential pair including a P-type first transistor receiving at its gate a first input signal which is one of differential input signals, and a P-type second transistor receiving at its gate a second input signal which is the other of the differential input signals; a tail current source for sourcing a tail current; A load circuit; a P-type third transistor connected between the first transistor and the load circuit; a fourth P-type transistor connected between the second transistor and the load circuit; a fifth transistor connected in parallel with the third transistor; a sixth transistor connected in parallel with the fourth transistor; a first control circuit that supplies a gate voltage having a positive correlation with the first input signal to a gate of the third transistor and supplies a gate voltage having a positive correlation with the second input signal to a gate of the fourth transistor; a second control circuit that turns on the fifth transistor and the sixth transistor when at least one of the first input signal and the second input signal is lower than a predetermined threshold; An operational amplifier circuit comprising:

2. The first control circuit a first source follower circuit including an N-type seventh transistor receiving the first input signal at its gate, the first source follower circuit supplying a source voltage of the seventh transistor to the gate of the third transistor; a second source follower circuit including an N-type eighth transistor receiving the second input signal at its gate, the second source follower circuit supplying a source voltage of the eighth transistor to the gate of the fourth transistor; 2. The operational amplifier circuit of claim 1, comprising:

3. the first source follower circuit is connected to a source of the seventh transistor and includes a first current source that sinks a constant current; 3. The operational amplifier circuit of claim 2, wherein the second source follower circuit includes a second current source connected to the source of the eighth transistor and sinking a constant current.

4. The second control circuit is a third current source that sources a constant current; a ninth P-type transistor having a gate receiving the first input signal, a source connected to the third current source, and a drain grounded; a tenth P-type transistor having a gate receiving the second input signal, a source connected to the third current source, and a drain grounded; and turning on the fifth transistor and the sixth transistor when a detection voltage generated at a commonly connected source of the ninth transistor and the tenth transistor is lower than a predetermined voltage.

5. 5. The operational amplifier circuit according to claim 4, wherein the second control circuit includes a comparator that compares the detected voltage with the predetermined voltage, and controls the fifth transistor and the sixth transistor according to an output of the comparator.

6. 5. The operational amplifier circuit according to claim 4, wherein the second control circuit includes an inverter that receives the detection voltage, and controls the fifth transistor and the sixth transistor in response to an output of the inverter.

7. 4. The operational amplifier circuit according to claim 1, wherein the fifth transistor and the sixth transistor are N-type.

8. a differential input stage, the differential input stage comprising: a differential pair including a first N-type transistor receiving at its gate a first input signal which is one of differential input signals, and a second N-type transistor receiving at its gate a second input signal which is the other of the differential input signals; a tail current source that sinks the tail current; A load circuit; a third N-type transistor connected between the first transistor and the load circuit; a fourth N-type transistor connected between the second transistor and the load circuit; a fifth transistor connected in parallel with the third transistor; a sixth transistor connected in parallel with the fourth transistor; a first control circuit that supplies a gate voltage having a positive correlation with the first input signal to a gate of the third transistor and supplies a gate voltage having a positive correlation with the second input signal to a gate of the fourth transistor; a second control circuit that turns on the fifth transistor and the sixth transistor when at least one of the first input signal and the second input signal is higher than a predetermined threshold; An operational amplifier circuit comprising:

9. The first control circuit a first source follower circuit including a P-type seventh transistor receiving the first input signal at its gate, the first source follower circuit supplying a source voltage of the seventh transistor to the gate of the third transistor; a second source follower circuit including an eighth P-type transistor receiving the second input signal at its gate, the second source follower circuit supplying a source voltage of the eighth transistor to the gate of the fourth transistor; 9. The operational amplifier circuit of claim 8, comprising:

10. the first source follower circuit is connected to a source of the seventh transistor and includes a first current source that sources a constant current; 10. The operational amplifier circuit of claim 9, wherein the second source follower circuit includes a second current source connected to the source of the eighth transistor and sourcing a constant current.

11. The second control circuit is a third current source that sources a constant current; a ninth P-type transistor having a gate receiving the first input signal, a source connected to the third current source, and a drain connected to a power supply line; a tenth P-type transistor having a gate receiving the second input signal, a source connected to the third current source, and a drain connected to the power supply line; and turning on the fifth transistor and the sixth transistor when a detection voltage generated at a commonly connected source of the ninth transistor and the tenth transistor is higher than a predetermined voltage.

12. 12. The operational amplifier circuit according to claim 11, wherein the second control circuit includes a comparator that compares the detected voltage with the predetermined voltage, and controls the fifth transistor and the sixth transistor according to an output of the comparator.

13. 12. The operational amplifier circuit according to claim 11, wherein the second control circuit includes an inverter that receives the detection voltage, and controls the fifth transistor and the sixth transistor in response to an output of the inverter.

14. 11. The operational amplifier circuit according to claim 8, wherein the fifth transistor and the sixth transistor are P-type.

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