Modulation device

Abstract

To change a baud rate.SOLUTION: A modulation device comprises: a reception unit 32 that receives a setting of a multiplication value (an integer of 2 or more) for upsampling; a filter generation unit 33 that generates a polyphase filter 331 having a number of subfilters equal to the multiplication value received by the reception unit 32; a clock generation unit 1 that generates a sampling clock having a frequency obtained by multiplying a value of the frequency of a symbol clock corresponding to the baud rate of target data by the multiplication value; a data creation unit 4 that creates upsampled serial data of the target data by sequentially acquiring the target data passed through each subfilter constituting the polyphase filter 331 in synchronization with the sampling clock; and a digital-to-analog converter 5 that performs analog conversion on the serial data.SELECTED DRAWING: Figure 1

Description

[Technical Field]

[0001] The present invention relates to a modulation device for modulating data. [Background technology]

[0002] Data is commonly transmitted via a serial bus. Patent Document 1 describes setting the baud rate of the serial bus to a value that is higher than the speed at which data characters are written to a data buffer. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] Japanese Patent Application Publication No. 11-355382 Summary of the Invention [Problem to be solved by the invention]

[0004] The document described in Patent Document 1 has a problem in that the baud rate of the serial bus cannot be changed.

[0005] The present invention has been made in view of the above problems, and has as its object to provide a modulation device capable of changing the baud rate. [Means for solving the problem]

[0006] A modulation device according to a first aspect of the present invention includes a receiving unit that receives a setting of a multiplier value (an integer equal to or greater than 2) for upsampling; a filter generating unit that generates a polyphase filter having the same number of stages of sub-filters as the multiplier value received by the receiving unit; a clock generating unit that generates a sampling clock having a frequency obtained by multiplying the frequency value of a symbol clock corresponding to the baud rate of target data by the multiplier value; a data generating unit that generates serial data obtained by upsampling the target data by sequentially acquiring the target data that has passed through each of the sub-filters constituting the polyphase filter in synchronization with the sampling clock; and a digital-to-analog converter that converts the serial data into analog data.

[0007] The modulation device may further include a storage unit that stores the number of stages of sub-filters that constitute the polyphase filter and a plurality of filter coefficients of each sub-filter that constitutes the polyphase filter, in association with each other, and the filter generation unit may generate the polyphase filter, each of which has sub-filters to which the filter coefficients associated with the same number of stages as the multiplier value are applied.

[0008] The clock generating unit may generate the sampling clock based on an external clock, and may generate the symbol clock by dividing the sampling clock by the multiple value. [Effects of the Invention]

[0009] The present invention has the effect of making it possible to change the baud rate of a modulated signal output by a modulation device. [Brief explanation of the drawings]

[0010] [Figure 1] 1 shows the configuration of a modulation device according to an embodiment. [Figure 2] 1 shows the configuration of a polyphase filter generated by a filter generation unit. [Figure 3]An example of the filter coefficients of each sub-filter 40 that constitutes the polyphase filter is shown below. DETAILED DESCRIPTION OF THE INVENTION

[0011] [Modulator configuration] 1 shows the configuration of a modulation device 100 of this embodiment. The modulation device 100 controls the baud rate when modulating target data to an arbitrary value. The modulation device 100 includes a clock generation unit 1, a storage unit 2, a control unit 3, a data creation unit 4, and a DAC (Digital / Analog Converter) 5. The control unit 3 includes a data acquisition unit 31, a reception unit 32, and a filter generation unit 33.

[0012] The clock generation unit 1 generates a symbol clock CLK1 and a sampling clock CLK2. The frequency of the sampling clock CLK2 is obtained by multiplying the frequency value of the symbol clock CLK1 corresponding to the baud rate of the target data by a predetermined multiplier value d. The multiplier value d is specified by the reception unit 32. The symbol clock CLK1 is supplied to the data acquisition unit 31 and the polyphase filter 331, and the sampling clock CLK2 is supplied to the data creation unit 4 and the DAC 5.

[0013] The clock generating unit 1 includes a PLL (Phase-Locked Loop) 11 and a frequency divider 12. An external clock is input to the PLL 11. The PLL 11 generates a sampling clock CLK2 based on the input external clock. As an example, the PLL 11 generates a sampling clock CLK2 that has the same frequency as the external clock and is synchronized with the external clock.

[0014] PLL 11 generates symbol clock CLK1 by having frequency divider 12 divide the sampling clock CLK2 using the multiple value d instructed by reception unit 32 as the frequency division value. PLL 11 supplies the symbol clock CLK1 generated by frequency divider 12 to data acquisition unit 31 and polyphase filter 331. PLL 11 supplies the generated sampling clock CLK2 to data creation unit 4 and DAC 5.

[0015] The storage unit 2 includes storage media such as a ROM (Read Only Memory), a RAM (Random Access Memory), and a hard disk. The storage unit 2 stores programs executed by the control unit 3. The storage unit 2 stores filter coefficient data that associates the number of stages of sub-filters that make up the polyphase filter with multiple filter coefficients of each sub-filter that makes up the polyphase filter.

[0016] The control unit 3 is, for example, a digital signal processor. The control unit 3 executes a program stored in the storage unit 2, thereby functioning as a data acquisition unit 31, a reception unit 32, and a filter generation unit 33.

[0017] The data acquisition unit 31 acquires target data to be upsampled. As an example, the data acquisition unit 31 acquires audio data as target data via a microphone (not shown). The data acquisition unit 31 may acquire the target data from an external device via a network, or may acquire the target data from an external storage medium such as a flash memory. The data acquisition unit 31 acquires the target data in synchronization with the symbol clock CLK1. The data acquisition unit 31 outputs the acquired target data to the filter generation unit 33.

[0018] The reception unit 32 receives the setting of a multiplier value d (an integer equal to or greater than 2) for upsampling. For example, the reception unit 32 receives the setting of the multiplier value d by the user via a touch panel (not shown). The reception unit 32 may also receive the setting of the multiplier value d by the user via a network. The reception unit 32 instructs the frequency divider 12 and the filter generation unit 33 with the received multiplier value d.

[0019] The filter generation unit 33 generates a polyphase filter 331 having sub-filters with the same number of stages as the multiple value d received by the reception unit 32. For example, the filter generation unit 33 reads from the storage unit 2 filter coefficient data that associates the number of stages of the sub-filters that make up the polyphase filter 331 with multiple filter coefficients of each of the sub-filters that make up the polyphase filter 331.

[0020] The filter generation unit 33 refers to the read filter coefficient data and identifies multiple filter coefficients of each sub-filter constituting the polyphase filter 331, which are associated with the same number of stages as the multiplier value d accepted by the acceptance unit 32. The filter generation unit 33 applies the filter coefficients identified by a counter (to be described later) to each sub-filter of the polyphase filter 331, thereby generating the polyphase filter 331.

[0021] FIG. 2 shows the configuration of the polyphase filter 331 generated by the filter generation unit 33. The polyphase filter 331 includes a counter 301 and d-stage sub-filters 40(1) to 40(d). The sub-filter 40(1) includes k (k is the number of taps) delay elements 41-1(1) to 41-k(1), k multipliers 42-1(1) to 42-k(1), and a sigma calculator 43(1). The other sub-filters 40(2) to 40(d) are similar to the sub-filter 40(1), and therefore their description will be omitted. In the example of FIG. 2, the d-stage sub-filters 40(1) to 40(d) operate in synchronization with the symbol clock CLK1. The data generation unit 4 operates in synchronization with the sampling clock CLK2.

[0022] Counter 301 applies a plurality of filter coefficients stored in storage unit 2 to each of multipliers 42-1(1) to 42-k(1), 42-1(2) to 42-k(2), ..., 42-1(d) to 42-k(d). Counter 301 reads filter coefficient data from storage unit 2. Counter 301 references the read filter coefficient data and identifies a plurality of filter coefficients of each of sub-filters 40(1) to 40(d) constituting polyphase filter 331 that are associated with the same number of stages as multiplier value d accepted by acceptance unit 32. Counter 301 applies the identified filter coefficient to the corresponding multiplier.

[0023] The delay elements 41-1(1) to 41-k(1) delay signals. The delay element 41-1(1) inputs the delayed signal to the next delay element 41-2(1) and multiplier 42-1(1). The delay element 41-2(1) inputs the delayed signal to the next delay element 41-3(1) and multiplier 42-2(1). The delay element 41-k(1) inputs the delayed signal to the multiplier 42-k(1). The other delay elements such as the delay element 41-3(1) are similar to the delay elements 41-1(1) and 41-2(1).

[0024] Multiplier 42-1(1) performs an operation of multiplying the value input by delay element 41-1(1) by the filter coefficient applied by counter 301. Multiplier 42-2(1) performs an operation of multiplying the value input by delay element 41-2(1) by the filter coefficient applied by counter 301. The other multipliers are similar to multiplier 42-1(1) and multiplier 42-2(1).

[0025] The sigma calculators 43(1) to 43(d) calculate the sum of the calculation results of all the multipliers of the corresponding sub-filters. For example, the sigma calculator 43(1) calculates the sum of the calculation results of the multipliers 42-1(1) to 42-k(1). The sigma calculator 43(2) calculates the sum of the calculation results of the multipliers 42-1(2) to 42-k(2). The other sigma calculators are similar to the sigma calculators 43(1) and 43(2).

[0026] The data creation unit 4 is a functional block executed by, for example, a processor that operates in synchronization with a sampling clock CLK2 having a frequency different from that of the symbol clock CLK1 supplied to the control unit 3. The data creation unit 4 sequentially acquires the target data that has passed through each of the sub-filters 40(1) to 40(d) that make up the polyphase filter 331 in synchronization with the sampling clock CLK2, thereby creating serial data by up-sampling the target data.

[0027] The data creation unit 4 sequentially acquires the calculation results of the sigma calculators 43(1) to 43(d). More specifically, the data creation unit 4 acquires the calculation results in the order of sigma calculator 43(1), sigma calculator 43(2), ..., sigma calculator 43(d), and then repeats the process of acquiring the next calculation result from sigma calculator 43(1), sigma calculator 43(2), ..., sigma calculator 43(d). The data creation unit 4 outputs the acquired calculation results as serial data.

[0028] The data generator 4 operates in synchronization with a sampling clock CLK2 having a frequency d times that of the symbol clock CLK1. Therefore, the process by which the data generator 4 sequentially acquires the target data that has passed through the sub-filters 40(1) to 40(d) and creates serial data is equivalent to the process of up-sampling the target data d times. Because the data generator 4 acquires the data that has passed through the sub-filters 40(1) to 40(d), it is possible to suppress aliasing caused by up-sampling.

[0029] Fig. 3 shows an example of filter coefficients of the sub-filters 40(1) to 40(k) that make up the polyphase filter 331. Fig. 3 shows an example in which the polyphase filter 331 has three sub-filters 40(1) to 40(3).

[0030] Fig. 3(a) shows a plurality of filter coefficients that counter 301 applies to k multipliers 42-1(1) through 42-k(1) of sub-filter 40(1). Fig. 3(b) shows a plurality of filter coefficients that counter 301 applies to k multipliers 42-1(2) through 42-k(2) of sub-filter 40(2). Fig. 3(c) shows a plurality of filter coefficients that counter 301 applies to each of multipliers 42-1(3) through 42-k(3) of sub-filter 40(3).

[0031] The horizontal axis of Fig. 3(a) indicates each multiplier 42-1(1) to 42-k(1) to which a filter coefficient is applied, from the left of the graph, in the order in which the target data is acquired. The vertical axis of Fig. 3(a) indicates the filter coefficient. Similarly, the horizontal axes of Fig. 3(b) and Fig. 3(c) indicate each multiplier 42-1(2) to 42-k(2) and multiplier 42-1(3) to 42-k(3) to which a filter coefficient is applied, from the left of the graph, in the order in which the target data is acquired.

[0032] Data generator 4 executes the processing of three sub-filters 40(1)-40(3) in parallel, thereby reducing the time required for filter processing by one-third. Meanwhile, data generator 4 operates in synchronization with sampling clock CLK2, which has a frequency three times that of symbol clock CLK1 supplied to sub-filters 40(1)-40(3). In this way, sub-filters 40(1)-40(d) and data generator 4 can generate serial data at any baud rate corresponding to multiplier value d accepted by acceptor 32.

[0033] Returning to the explanation of Fig. 1, the DAC 5 converts the serial data created by the data creation unit 4 into analog data. For example, the DAC 5 converts the serial data into analog data for wireless transmission. The present invention is not limited to the DAC 5 converting the serial data into analog data for wireless transmission, and the DAC 5 may convert the serial data into analog data for purposes other than wireless transmission.

[0034] [Effects of the Modulation Device of the Present Embodiment] According to the modulation device 100 of this embodiment, the clock generation unit 1 generates a sample clock CLK2 having a frequency obtained by multiplying the frequency of the symbol clock CLK1 by the multiple value d received by the reception unit 32, and the data creation unit 4 creates serial data in synchronization with this sampling clock CLK2. In this way, the clock generation unit 1 and the data creation unit 4 can output serial data at any baud rate corresponding to the multiple value d received by the reception unit 32.

[0035] The present invention has been described above using embodiments, but the technical scope of the present invention is not limited to the scope described in the above embodiments, and various modifications and changes are possible within the scope of the gist of the present invention. For example, all or part of the device can be configured by functionally or physically distributing or integrating any unit. Furthermore, new embodiments resulting from any combination of multiple embodiments are also included in the embodiments of the present invention. The effects of the new embodiments resulting from the combination also have the effects of the original embodiments. [Explanation of symbols]

[0036] 1. Clock generation unit 2 Storage section 3. Control Unit 4. Data Creation Department 5 Digital-to-Analog Converter 11 PLL 12 frequency divider 31 Data Acquisition Section 32 Reception Department 33 Filter generation unit 40 Sub-filters 100 Modulator 301 Counter 331 Polyphase Filter

Claims

1. a reception unit that receives a setting of a multiplier value (an integer equal to or greater than 2) for upsampling; a filter generation unit that generates a polyphase filter having sub-filters with the same number of stages as the multiplication factor value received by the reception unit; a clock generating unit that generates a sampling clock having a frequency obtained by multiplying the frequency value of a symbol clock corresponding to the baud rate of the target data by the multiple value; a data generation unit that generates serial data by upsampling the target data by sequentially acquiring the target data that has passed through each of the sub-filters that constitute the polyphase filter in synchronization with the sampling clock; a digital-to-analog converter that converts the serial data into an analog signal; A modulation device having:

2. a storage unit that stores the number of stages of sub-filters that constitute the polyphase filter and a plurality of filter coefficients of each sub-filter that constitutes the polyphase filter in association with each other; the filter generation unit generates the polyphase filter, each of which has sub-filters to which the filter coefficients associated with the same number of stages as the multiplication factor are applied.

2. The modulation device of claim 1.

3. the clock generating unit generates the sampling clock based on an external clock, and generates the symbol clock by dividing the sampling clock by the multiplier value; 3. A modulation device according to claim 1 or 2.

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