Computing device

Abstract

To execute matrix operations of floating-point data with multiple precisions while suppressing an increase in a circuit scale.SOLUTION: A computing device capable of executing matrix multiplication of mantissa parts of floating-point data comprises: a plurality of product sum arithmetic circuits each including a plurality of multipliers that multiply the data pair of the mantissa part, and a first adder that adds multiplication results of the plurality of multipliers and correction values; and an addition circuit that adds operation results output from the plurality of product sum arithmetic circuits, and outputs the addition result as a matrix multiplication result of the data of the mantissa part in one of a plurality of types of floating-point formats.SELECTED DRAWING: Figure 2

Description

[Technical Field]

[0001] The present disclosure relates to a computing device. [Background technology]

[0002] The computing devices used in applications that perform processes such as deep learning require high computing performance to perform a large number of matrix operations. For this reason, ASICs (Application Specific Integrated Circuits) equipped with a large number of matrix operation circuits are often used as computing devices to enhance the computing performance of the computing devices.

[0003] There is an upper limit to the number and size of matrix operation circuits that can be implemented in an ASIC such as a processor chip. For example, if an application requires matrix operations on floating-point number data with multiple precisions, it is preferable to install a matrix operation circuit for each precision on the processor chip. However, due to limitations on circuit size, it may be difficult to install multiple matrix operation circuits with the required precision on a processor chip. Furthermore, an increase in circuit size may result in increased power consumption.

[0004] As an example of floating-point number data, a block floating-point number format is known, in which the exponent parts of multiple floating-point number data are made common among multiple data. In the block floating-point number format, for example, the exponent parts of multiple floating-point number data in a matrix may be made common by using the exponent of the largest floating-point number data in the matrix. Summary of the Invention [Problem to be solved by the invention]

[0005] In the present disclosure, matrix operations are performed on floating-point number data with multiple precisions while suppressing an increase in circuit size. [Means for solving the problem]

[0006] An arithmetic device according to an embodiment of the present invention is an arithmetic device capable of performing matrix multiplication of mantissa parts of floating-point number data, and includes a plurality of product-sum calculation circuits, each including a plurality of multipliers that multiply data pairs of the mantissa parts and a first adder that adds the multiplication results of the plurality of multipliers and a correction value, and an addition circuit that adds the calculation results output from the plurality of product-sum calculation circuits and outputs the addition result as a matrix multiplication result of the mantissa part data of one of a plurality of floating-point number formats. [Brief explanation of the drawings]

[0007] [Figure 1] 1 is a block diagram showing an example of the configuration of a calculation device according to a first embodiment of the present invention. [Figure 2] 2 is a circuit block diagram showing an example of a multiplication execution unit in FIG. 1. [Figure 3] 1A and 1B are diagrams illustrating examples of half-precision, pseudo-single-precision, single-precision, and double-precision floating-point number formats. [Figure 4] 3 is a diagram illustrating an example of matrix multiplication of mantissas of half-precision data executed by the multiplication execution unit in FIG. 2. FIG. [Figure 5] 3 is a diagram illustrating an example of matrix multiplication of mantissas of pseudo single-precision data executed by the multiplication execution unit of FIG. 2; [Figure 6] 3 is a diagram illustrating an example of matrix multiplication of mantissas of single-precision data executed by the multiplication execution unit in FIG. 2. [Figure 7] FIG. 10 is a diagram illustrating an example of substitution with a correction value when performing matrix multiplication of single-precision data. [Figure 8] 3 is a diagram illustrating an example of matrix multiplication of mantissas of double-precision data executed by the multiplication execution unit of FIG. 2. FIG. [Figure 9] 3 is a diagram illustrating an example of the flow of calculation when the multiplication execution unit in FIG. 2 executes matrix multiplication of mantissas of double-precision data. [Figure 10] 10A and 10B are diagrams illustrating an example of substitution with correction values when matrix multiplication of double-precision data is performed; [Figure 11] FIG. 10 is a block diagram showing an example of the configuration of a calculation device according to a second embodiment of the present invention. [Figure 12]12 is a diagram illustrating an example of matrix multiplication of mantissas of pseudo single-precision data executed by the multiplication execution unit of FIG. 11. FIG. [Figure 13] 12 is a diagram illustrating an example of matrix multiplication of mantissas of single-precision data executed by the multiplication execution unit in FIG. 11. [Figure 14] 12 is a diagram illustrating an example of matrix multiplication of mantissas of double-precision data executed by the multiplication execution unit in FIG. 11. [Figure 15] 12 is a diagram illustrating an example of matrix multiplication of mantissas of double-precision data executed by the multiplication execution unit in FIG. 11. [Figure 16] 2 is a block diagram showing an example of a hardware configuration of a computer in which the arithmetic device shown in FIG. 1 is installed. FIG. DETAILED DESCRIPTION OF THE INVENTION

[0008] Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings. Although not particularly limited, the arithmetic device may be a processor installed in a computer such as a server, and may execute a program (instruction) to perform convolution operations or the like in training or inference of a deep neural network. The arithmetic device described below may also be used for scientific and technical calculations.

[0009] Fig. 1 is a block diagram showing an example of the configuration of an arithmetic device according to a first embodiment of the present invention. For example, the arithmetic device 100 shown in Fig. 1 may be formed by hardware (circuits). The arithmetic device 100 may include an instruction memory 110, an instruction supply circuit 120, an instruction decoder 130, an arithmetic unit 140, and a register file 150. The arithmetic device 100 may be a processor in the form of a chip.

[0010] The instruction memory 110 may hold instructions transferred from the external memory 200 and sequentially output the held instructions to the instruction supply circuit 120. The instruction supply circuit 120 may sequentially supply the instructions transferred from the instruction memory 110 to the instruction decoder 130. The instruction decoder 130 may decode the instructions received from the instruction supply circuit 120 to generate control information required for executing the instructions, and output the generated control information to the arithmetic unit 140. The instruction decoder 130 is an example of an instruction output circuit that outputs control information identifying the type of matrix multiplication to be performed and the floating-point number format, together with a data pair of the mantissa parts of the floating-point number data, to the multiplication execution unit 141.

[0011] The arithmetic unit 140 may include multiple multiplication execution units 141 capable of multiplying the mantissas of floating-point number data or block floating-point number data. The arithmetic unit 140 may also include other multiplication execution units capable of multiplying data in formats other than the floating-point number format or the block floating-point number format. The arithmetic unit 140 may also include one or more execution units that perform operations other than multiplication. Hereinafter, the description of the multiplication of the mantissas of floating-point number data performed by the multiplication execution unit 141 can also be applied to the multiplication of the mantissas of block floating-point number data, as appropriate. Also, the description of the multiplication of the mantissas of block floating-point number data can also be applied to the multiplication of the mantissas of floating-point number data, as appropriate. The multiplication execution unit 141 may also include an arithmetic circuit that calculates the exponent and sign of the floating-point number data or the block floating-point number data.

[0012] The register file 150 may hold data to be operated on by the operation unit 140 and data resulting from the operation executed by the operation unit 140. The operation device 100 may have an internal memory (not shown) connected to the register file 150. The internal memory may be capable of transferring data to and from the register file 150, or may be capable of transferring data directly or indirectly to and from the external memory 200. The circuit configuration of the operation device 100 shown in FIG. 1 is an example, and the operation device 100 is required to have at least the multiplication execution unit 141.

[0013] 2 is a circuit block diagram showing an example of the multiplication execution unit 141 of FIG. 1. The multiplication execution unit 141 may have a plurality of product-sum calculation circuits PS1 and a plurality of adders b, c, and d connected to the outputs of the product-sum calculation circuits PS1. Although not particularly limited, the multiplication execution unit 141 may have 32 product-sum calculation circuits PS1, 16 adders b, 8 adders c, and 2 adders d. The adders b, c, and d are examples of a third adder, a fourth adder, and a fifth adder, respectively. The adders b, c, and d are examples of addition circuits.

[0014] Each product-sum operation circuit PS1 may have eight multipliers indicated by rectangles with a sign x, a shifter SFT connected to the output of each multiplier, a correction value generation circuit CVGEN that generates a correction value CV, an adder a, and a shifter SFT arranged on a supply path of a carry C to the adder a. The adder a may add an output value from the shifter SFT connected to each multiplier, the correction value CV from the correction value generation circuit CVGEN, and the carry C bit-shifted by the shifter SFT. The adder a is an example of a first adder. Note that the number of multipliers included in each product-sum operation circuit PS1 may be, but is not limited to, 2 to the power of i (i is a positive integer greater than or equal to 2).

[0015] Each multiplier may multiply a 9-bit data pair indicating the mantissa part of the floating-point number data, or a 9-bit partial mantissa data pair obtained by dividing each of the mantissa part data pairs, and output the multiplication result to the shifter SFT.

[0016] The correction value generation circuit CVGEN may determine whether to generate a correction value CV based on, for example, information indicating the precision (half precision, single precision, etc.) of the floating-point number data included in the control information supplied from the instruction decoder 130. When single-precision and double-precision floating-point number data are supplied, the correction value generation circuit CVGEN may generate a correction value CV based on a partial mantissa data pair not assigned to a multiplier. For example, if one of the partial mantissa data pairs is zero, the correction value generation circuit CVGEN may output a fixed correction value CV such as "0." Alternatively, the correction value generation circuit CVGEN may output the average of the maximum and minimum values that the partial mantissa data pair can take as the fixed correction value CV. The correction value generation circuit CVGEN that outputs a fixed correction value CV may be a data holding circuit such as a register. By generating a correction value CV based on a partial mantissa data pair not assigned to a multiplier, the correction value generation circuit CVGEN can suppress a decrease in the precision of the matrix multiplication result even when multiplication of the partial mantissa data pair is not performed.

[0017] When single-precision and double-precision floating-point number data is not supplied, i.e., when half-precision or pseudo-single-precision floating-point number data is supplied, the correction value generation circuit CVGEN may output "0" without generating a correction value CV. As a result, even when one multiplication execution unit 141 is used for matrix multiplication of mantissa parts of floating-point number data of multiple precisions, a correction value CV can be generated when a matrix multiplication requires a correction value CV, and generation of a correction value CV can be suppressed when a matrix multiplication does not require a correction value CV. As a result, malfunction of the arithmetic device 100 due to erroneous generation of a correction value CV can be suppressed.

[0018] For example, the outputs of two multiply-accumulate circuits PS1 may be connected to the inputs of adder b, and the outputs of two adders b may be connected to the inputs of adder c. The outputs of four adders c may be connected to the inputs of adder d.

[0019] As will be explained with reference to Figures 4 to 9, each adder b can output a matrix multiplication result HALF of the mantissa parts of half-precision floating-point number data. Each adder c can output a matrix multiplication result SSNGL of the mantissa parts of pseudo single-precision floating-point number data or a matrix multiplication result SNGL of the mantissa parts of single-precision floating-point number data. Pseudo single precision will be explained with reference to Figure 3. Each adder d can output a multiplication result DBL of the mantissa parts of double-precision floating-point number data. In other words, the arithmetic device 100 can perform matrix multiplication of the mantissas of floating-point number data of multiple types of precision using the multiplication execution unit 141.

[0020] 3 shows examples of floating-point number formats for half-precision, pseudo single-precision, single-precision, and double-precision. Half-precision floating-point number data has a 1-bit sign bit, a 9-bit mantissa, and a 6-bit exponent that is common to multiple half-precision data. Pseudo single-precision floating-point number data has a 1-bit sign bit, a 23-bit (effectively 18-bit) mantissa with the lower 5 bits set to "0," and an 8-bit exponent that is common to multiple pseudo single-precision data. The symbols H and L shown in the mantissa part of the pseudo single-precision data indicate the upper 9 bits and lower 9 bits of the mantissa part.

[0021] Single-precision floating-point data has a 1-bit sign bit, a 23-bit mantissa, and an 8-bit exponent that is common to multiple single-precision data. The symbols H, M, and L shown in the mantissa of the single-precision data indicate the upper 9 bits, middle 9 bits, and lower 5 bits of the mantissa.

[0022] Double-precision floating-point data has a 1-bit sign bit, a 52-bit mantissa, and an 11-bit exponent that is common to multiple double-precision data. The symbols HH, HL, MH, ML, LH, and LL shown in the mantissa of double-precision data each represent the 9 most significant bits of the mantissa (7 bits for LL).

[0023] Hereinafter, the mantissa data of half-precision, pseudo-single-precision, single-precision, and double-precision floating-point number data may also be simply referred to as half-precision data, pseudo-single-precision data, single-precision data, and double-precision data, respectively.

[0024] Fig. 4 is a diagram showing an example of matrix multiplication of mantissas of half-precision data executed by the multiplication execution unit 141 of Fig. 2. In Fig. 4, matrix multiplication of mantissas of 16 rows of half-precision data between a 16-row x 16-column matrix A and a 16-row x 1-column matrix B may be executed. Data of the mantissa parts of each element of matrix A and matrix B is an example of a data pair. For example, matrix A may be data to be subjected to a convolution operation, and matrix B may be a weight to be used in the convolution operation.

[0025] The multiplication result HALF of the matrix multiplication of the mantissa of each row of matrix A can be obtained by performing 16 multiplications of 9-bit mantissas using two multiply-accumulate circuits PS1. Therefore, the multiplication execution unit 141 in Fig. 2 can obtain 16 multiplication results HALF, which are the matrix multiplication of 16 rows of matrix A with 16 rows x 16 columns and matrix B with 16 rows x 1 column.

[0026] Fig. 5 is a diagram showing an example of matrix multiplication of mantissas of pseudo single-precision data executed by the multiplication execution unit 141 in Fig. 2. In Fig. 5, matrix multiplication of mantissas of 8 rows of pseudo single-precision data between an 8-row x 8-column matrix A and an 8-row x 1-column matrix B may be executed. In the description of bit groups H and L in Fig. 5, row numbers and column numbers are omitted.

[0027] 3, in the pseudo single-precision data, the mantissa part of each element of matrix A and matrix B may be divided into two parts, a bit group H of the most significant 9 bits and a bit group H of the least significant 9 bits, in accordance with the bit width of the multiplier of the multiply-accumulate circuit PS1. Therefore, in the mantissa of the pseudo single-precision data, the multiplication result of one element of matrix multiplication can be obtained by performing four 9-bit multiplications.

[0028] In each element of matrix A and matrix B, bit groups H and L of the mantissa part are an example of partial mantissa data. A combination of bit group H or bit group L of matrix A and bit group H or bit group L of matrix B is an example of a partial mantissa data pair. Note that the four multiplication results of the partial mantissa data pairs may be aligned using a shifter SFT in the product-sum calculation circuit PS1 and then added by an adder a.

[0029] The multiplication result SSNGL of the matrix multiplication of one row (=8 elements) of the mantissa of the pseudo single-precision data can be obtained by executing 9-bit multiplication 32 times using four product-accumulation circuits PS1. Therefore, using the multiplication execution unit 141 in Figure 2, it is possible to obtain eight multiplication results SSNGL, which are the results of the matrix multiplication of 8 rows of the 8-row x 8-column matrix A of the pseudo single-precision data and the 8-row x 1-column matrix B.

[0030] Fig. 6 is a diagram showing an example of matrix multiplication of mantissas of single-precision data executed by the multiplication execution unit 141 in Fig. 2. In Fig. 6, matrix multiplication of mantissas of 8 rows of single-precision data between an 8-row x 4-column matrix A and a 4-row x 1-column matrix B may be executed. In the description of bit groups H, M, and L in Fig. 6, row numbers and column numbers are omitted.

[0031] In the case of single-precision data, as shown in FIG. 3, the mantissa part of each element of matrix A and matrix B may be divided into three parts: a bit group H of the most significant 9 bits, a bit group M of the middle 9 bits, and a bit group L of the least significant 9 bits (actually, the least significant 5 bits) in accordance with the bit width of the multiply-accumulate circuit PS1.

[0032] The bit groups A_H, A_M, and A_L in each element of matrix A and the bit groups BH, BM, and BL in each element of matrix B are examples of partial mantissa data. A combination of any of the bit groups A_H, A_M, and A_L of matrix A and any of the bit groups BH, BM, and BL of matrix B is an example of a partial mantissa data pair.

[0033] Because the mantissa of each element is divided into three, the multiplication result of one element of the mantissa of single-precision data can be obtained by performing nine 9-bit multiplications. Therefore, the multiplication result SNGL of one row (four elements) of single-precision data can be obtained by performing 36 9-bit multiplications. However, in this case, to obtain eight multiplication results SNGL of eight rows of matrix multiplication, 288 9-bit multipliers are required, which cannot be performed by the multiplication execution unit 141 of FIG. 2, which has 256 9-bit multipliers.

[0034] To obtain eight multiplication results SNGL of the matrix multiplication for eight rows in the multiplication execution unit 141, the correction value CV may be used instead of the multiplication of bit groups A_L and BL among the nine multiplications of each element, and the multiplication of each element may be executed eight times. That is, each multiply-accumulate circuit PS1 may execute the multiplication of data pairs of bit groups of more significant bit combinations among the bit groups of matrices A and B using multiple multipliers, and may use the correction value CV instead of the data pairs of bit groups not assigned to the multipliers. This allows matrix multiplication of one row of matrix A to be executed by four multiply-accumulate circuits PS1.

[0035] 2, eight multiplication results SNGL can be obtained, which are the results of matrix multiplication of eight rows of single-precision data matrix A having 8 rows and 4 columns by matrix B having 4 rows and 1 column. Note that the eight multiplication results of the partial mantissa data pairs of the respective elements may be aligned using the shifter SFT in the product-sum calculation circuit PS1 and then added by the adder a.

[0036] Fig. 7 is a diagram showing an example of substitution with a correction value when performing matrix multiplication of single-precision data. In the matrix multiplication of single-precision data shown in Fig. 6, as shown in the dashed frame, a correction value CV may be applied instead of performing multiplication of bit group A_L of matrix A by bit group BL of matrix B for each element. In this case, the correction value CV may be generated based on bit groups A_L and BL, or may be set to a fixed value (e.g., "0").

[0037] As another example of a correction value, if the accuracy of matrix multiplication can be satisfied, the operation of multipliers that perform the multiplication of bit group A_M of matrix A by bit group BL of matrix B and the multiplication of bit group A_L of matrix A by middle-order bit group BM of matrix B for each element may be stopped, as shown in the dashed-dotted box on the right side of FIG. 7. Then, instead of performing the multiplication of bit groups A_M and BL, the multiplication of bit groups A_L and BM, and the multiplication of bit groups A_L and BL, a correction value CV may be provided. The correction value CV may be generated based on one or more of the pair of bit groups A_M and BL, the pair of bit groups A_L and BM, and the pair of bit groups A_L and BL, or may be set to a fixed value (e.g., "0").

[0038] In this case, the number of operating multipliers can be reduced compared to the example shown in Fig. 6, thereby reducing the power consumption of the multiplication execution unit 141 and the arithmetic device 100. The number of multipliers that are stopped may be seven or less. For example, information (position or number) of multipliers that are stopped by the multiply-accumulate circuit PS1 may be included in the control information supplied from the instruction decoder 130 (Fig. 1). Note that, even when performing matrix multiplication of the mantissa parts of half-precision or pseudo-single-precision floating-point number data shown in Figs. 4 and 5, the operation of some multipliers may be stopped.

[0039] Fig. 8 is a diagram showing an example of matrix multiplication of mantissas of double-precision data executed by the multiplication execution unit 141 of Fig. 2, and Fig. 9 is a diagram showing an example of the flow of calculations when the multiplication execution unit 141 of Fig. 2 executes matrix multiplication of mantissas of double-precision data. In Fig. 8 and Fig. 9, matrix multiplication of the mantissas of two rows of double-precision data between a 2-row x 4-column matrix A and a 4-row x 1-column matrix B may be executed. In the description of the bit groups HH, HL, MH, ML, LM, and LL in Fig. 8, row numbers and column numbers are omitted.

[0040] In double precision, as shown in FIG. 3, the mantissa part of each element of matrix A and matrix B may be divided into six bit groups, HH, HL, MH, ML, LH, and LL (in practice, the bit group LL is 7 bits), each of which is 9 bits from the most significant side, in accordance with the bit width of the multiply-accumulate circuit PS1.

[0041] In each element of matrix A and matrix B, bit groups A_HH, A_HL, A_MH, A_ML, A_LH, and A_LL and bit groups BHH, BHL, BMH, BML, BLH, and BLL are examples of partial mantissa data. A combination of any of bit groups A_HH, A_HL, A_MH, A_ML, A_LH, and A_LL of matrix A and any of bit groups BHH, BHL, BMH, BML, BLH, and BLL of matrix B is an example of a partial mantissa data pair.

[0042] Because the mantissa of each element is divided into 6, the multiplication result of one element of the double-precision data mantissa can be obtained by executing 36 9-bit multiplications. Therefore, the multiplication result DBL of one row (four elements) of double-precision matrix multiplication can be obtained by executing 144 9-bit multiplications. However, in this case, 288 9-bit multipliers are required to obtain two multiplication results DBL of two rows of matrix multiplication, which cannot be performed by the multiplication execution unit 141 in FIG. 2, which has 256 9-bit multipliers.

[0043] Therefore, among the 36 multiplications of each element, the correction value CV may be used instead of the multiplication of bit groups A_LH and BLH, the multiplication of bit groups A_LH and BLL, the multiplication of bit groups LL and BLH, and the multiplication of bit groups A_LL and BLL. This allows the matrix multiplication of one row of matrix A to be executed by 16 multiply-accumulate circuits PS1.

[0044] 2, two multiplication results DBL can be obtained, which are the results of matrix multiplication of two rows of a 2-row x 4-column matrix A of double-precision data and a 4-row x 1-column matrix B. Note that the 32 multiplication results of the partial mantissa data pairs of each element may be aligned using a shifter SFT in the product-sum calculation circuit PS1 and then added by an adder a.

[0045] 10 is a diagram showing an example of substitution with a correction value when matrix multiplication of double-precision data is performed. In the matrix multiplication of double-precision data shown in FIG. 8, as shown in the dashed frame, instead of performing multiplication of bit groups A_LH and BLH, multiplication of bit groups A_LH and BLL, multiplication of bit groups A_LL and BLH, and multiplication of bit groups A_LL and BLL for each element, a correction value CV may be provided. In this case, the correction value CV may be generated based on one or more of the pair of bit groups A_LH and BLH, the pair of bit groups A_LH and BLL, the pair of bit groups A_LL and BLH, and the pair of bit groups A_LL and BLL, or may be set to a fixed value (e.g., "0").

[0046] As another example of a correction value, if the accuracy of matrix multiplication can be satisfied, a correction value CV may be applied instead of performing multiplication of bit groups A_MH and BLL, multiplication of bit groups A_ML and BLH, multiplication of bit groups A_ML and BLL, multiplication of bit groups A_LH and BML, multiplication of bit groups A_LH and BLH, multiplication of bit groups A_LH and BLL, multiplication of bit groups A_LL and BMH, multiplication of bit groups A_LL and BML, multiplication of bit groups A_LL and BLH, and multiplication of bit groups A_LL and BLL, as shown in the dashed-dotted box on the right side of Figure 10.

[0047] The correction value CV may be generated based on one or more of the pair of bit groups A_MH, BLL, the pair of bit groups A_ML, BLH, the pair of bit groups A_ML, BLL, the pair of bit groups A_LH, BML, the pair of bit groups A_LH, BLH, the pair of bit groups A_LH, BLL, the pair of bit groups A_LL, BMH, the pair of bit groups A_LL, BML, the pair of bit groups A_LL, bit BLH, and the pair of bit groups A_LL, BLL, or may be set to a fixed value (e.g., "0").

[0048] 8, it is possible to reduce the number of operating multipliers, thereby reducing the power consumption of the multiplication execution unit 141 and the arithmetic device 100. Note that the number of multipliers that stop operating may be 31 or less.

[0049] As described above, in the first embodiment, the arithmetic device 100 can perform matrix multiplication of mantissas of floating-point number data of multiple types of precision using the common multiplication execution unit 141. For example, each multiplication execution unit 141 can perform matrix multiplication of mantissas of floating-point number data of half precision, pseudo single precision, single precision, and double precision.

[0050] In the mantissa part of single-precision and double-precision floating-point number data, among a plurality of bit groups divided according to the number of bits of the multiplier, the correction value CV may be used in place of a data pair of a lower-order bit group not assigned to the multiplier. This makes it possible to perform matrix multiplication of the mantissas of single-precision and double-precision floating-point number data using the multiplication execution unit 141 that performs matrix multiplication of the mantissas of half-precision or pseudo-single-precision floating-point number data.

[0051] The correction value generation circuit CVGEN provided in each multiply-add circuit PS1 generates a correction value CV based on the lower-order partial mantissa data pair that is not assigned to the multiplier, thereby suppressing a decrease in the accuracy of the matrix multiplication result even when multiplication of the lower-order partial mantissa data pair is not performed.

[0052] Furthermore, the correction value generation circuit CVGEN generates the correction value CV based on control information supplied from the instruction decoder 130, and therefore can determine whether to generate the correction value CV depending on the precision of the floating-point number data. In other words, the correction value CV can be generated only when matrix multiplication of single-precision and double-precision floating-point number data is performed.

[0053] Therefore, even when one multiplication execution unit 141 is used for matrix multiplication of mantissa parts of floating-point number data of multiple precisions, a correction value CV can be generated when a matrix multiplication requires a correction value CV, and generation of a correction value CV can be prevented when a matrix multiplication does not require a correction value CV. As a result, malfunction of the arithmetic device 100 due to erroneous generation of a correction value CV can be prevented.

[0054] Stopping the operation of some of the multipliers in the product-sum calculation circuit PS1 can reduce the power consumption of the multiplication execution unit 141 and the arithmetic device 100. By receiving the positions or number of multipliers to be stopped as control information from the instruction decoder 130, the product-sum calculation circuit PS1 can appropriately control the power consumption of the arithmetic device 100 according to the precision of the floating-point number data, the characteristics of the floating-point number data for which matrix multiplication is performed, or the execution scale of the matrix multiplication.

[0055] Fig. 11 is a block diagram showing an example of the configuration of an arithmetic device according to the second embodiment of the present invention. Elements similar to those in Fig. 2 are given the same reference numerals, and detailed description thereof will be omitted. For example, the multiplication execution unit 141 shown in Fig. 11 may be mounted on the arithmetic unit 140 of the arithmetic device 100 of Fig. 1. The configuration of the multiplication execution unit 141 shown in Fig. 11 is the same as the configuration of the multiplication execution unit 141 shown in Fig. 2, except that it has a product-sum operation circuit PS2 instead of the product-sum operation circuit PS1 of Fig. 2.

[0056] Each multiply-accumulate circuit PS2 may have eight multipliers indicated by rectangles with a sign x, two adders e connected to the outputs of the four multipliers, respectively, a shifter SFT connected to the output of each adder e, a correction value generation circuit CVGEN that generates a correction value CV, and an adder a. The adder a may add data from each shifter SFT, the correction value CV from the correction value generation circuit CVGEN, and a carry C. The adder e is an example of a second adder.

[0057] Each multiplier may multiply a 9-bit data pair indicating the mantissa of the block floating-point number data, or a 9-bit partial mantissa data pair obtained by dividing each of the mantissa data pairs, and output the multiplication result to adder e. An example of matrix multiplication of the mantissa of half-precision block floating-point number data having a 9-bit mantissa is the same as that shown in Figure 4. Therefore, hereinafter, examples of matrix multiplication of the mantissa of pseudo-single-precision, single-precision, and double-precision block floating-point number data will be described.

[0058] FIG. 12 is a diagram showing an example of matrix multiplication of mantissas of pseudo single-precision data executed by the multiplication execution unit 141 of FIG. 11. Detailed descriptions of elements and operations similar to those in FIG. 5 will be omitted. In the description of bit groups H and L in FIG. 12, row and column numbers will be omitted. FIG. 12 shows an example of matrix multiplication of the first row (left side of FIG. 12) and the second row (right side of FIG. 12) in matrix A of pseudo single-precision data shown in FIG. 5. In FIG. 12, the multipliers of each product-sum calculation circuit PS2 are shown by multiplication formulas.

[0059] 12 may multiply partial mantissa data of matrix A having the same digit position with partial mantissa data of matrix B having the same digit position in the pseudo single-precision data. That is, each of the four multipliers connected to each adder e in each of the multiplier-accumulator circuits PS2 may multiply one of the bit groups A_H and A_L of matrix A by one of the bit groups BH and BL of matrix B. Then, the four multiplier-accumulator circuits PS2 (32 multipliers) can generate a matrix multiplication result SSNGL of the mantissa part of the pseudo single-precision block floating-point number data.

[0060] Because the digit positions of the multiplication results from the four multipliers connected to each adder e can be made the same, the shifters SFT of the product-sum calculation circuit PS2 can be connected to the output of the adder e, rather than to the outputs of the eight multipliers. As a result, the number of shifters SFT included in each product-sum calculation circuit PS2 can be reduced to one-fourth the number of shifters SFT included in each product-sum calculation circuit PS1 in FIG. 3. Therefore, the circuit scale of the product-sum calculation circuit PS2 can be made smaller than that of the product-sum calculation circuit PS1, and the circuit scale of the multiplication execution unit 141 can be reduced. Since the circuit scale of the multiplication execution unit 141 can be reduced, the cost of the arithmetic device 100 can be reduced. Furthermore, by reducing the number of shifters SFT, the power consumption of the product-sum calculation circuit PS2 and the multiplication execution unit 141 can be reduced.

[0061] FIG. 13 is a diagram showing an example of matrix multiplication of mantissas of single-precision data executed by the multiplication execution unit 141 of FIG. 11. Detailed descriptions of elements and operations similar to those in FIG. 6 will be omitted. In the description of bit groups H, M, and L in FIG. 13, row and column numbers will be omitted. FIG. 13 shows an example of matrix multiplication of the first row (left side of FIG. 13) and the second row (right side of FIG. 13) in matrix A of pseudo single-precision data shown in FIG. 6. In FIG. 13 as well, the multipliers of each product-sum calculation circuit PS2 are shown by multiplication formulas.

[0062] In FIG. 13 as well, the four multipliers connected to the input of the adder e of each multiply-add circuit PS2 may multiply partial mantissa data of matrix A having the same digit position with partial mantissa data of matrix B having the same digit position in single-precision data.

[0063] That is, each multiply-accumulate circuit PS2 may perform multiplication of one of the bit groups A_H, A_M, and A_L of matrix A by one of the bit groups BH, A_M, and BL of matrix B for each of the four multipliers connected to each adder e (however, excluding the multiplication of bit groups A_L and BL). Because multiplication of bit group A_L of matrix A by bit group BL of matrix B is not performed, the matrix multiplication result SNGL of the mantissa part of the single-precision block floating-point number data can be generated by the four multiply-accumulate circuits PS2 (32 multipliers).

[0064] Similar to the matrix multiplication of pseudo single-precision data in FIG. 12, the digit positions of the multiplication results by the four multipliers connected to each adder e can be made the same, so the number of shifters SFT included in each product-sum calculation circuit PS2 can be reduced to one-fourth the number of shifters SFT included in each product-sum calculation circuit PS1 in FIG. 3.

[0065] Figures 14 and 15 are diagrams showing an example of matrix multiplication of mantissas of double-precision data executed by the multiplication execution unit of Figure 11. Detailed descriptions of elements and operations similar to those of Figures 8 and 9 will be omitted. In the descriptions of bit groups HH, HL, MH, ML, LM, and LL in Figures 14 and 15, row and column numbers will be omitted. Figures 14 and 15 show an example of matrix multiplication of the first row of matrix A of double-precision data shown in Figure 8.

[0066] 14 and 15, the four multipliers connected to the input of the adder e of each multiply-add circuit PS2 may multiply partial mantissa data of matrix A having the same digit position with partial mantissa data of matrix B having the same digit position in double-precision data.

[0067] That is, each multiply-accumulate circuit PS2 may perform, for each of four multipliers connected to each adder e, multiplication of one of the bit groups A_HH, A_HL, A_MH, A_ML, A_LH, and A_LL of matrix A by one of the bit groups BHH, BHL, BMH, BML, BLH, and BLL of matrix B (excluding multiplication of bit groups A_LH and BLH, bit groups A_LH and BLL, bit groups A_LL and BLH, and bit groups A_LL and BLL).Since multiplication of bit groups A_LH and BLH, bit groups A_LH and BLL, bit groups A_LL and BLH, and bit groups A_LL and BLL is not performed, the matrix multiplication result DBL of the mantissa part of the double-precision block floating-point number data can be generated by 16 multiply-accumulate circuits PS2 (128 multipliers).

[0068] Similar to the matrix multiplication of the mantissa parts of pseudo single-precision data in FIG. 12 and the matrix multiplication of the mantissa parts of single-precision data in FIG. 13, the digit positions of the multiplication results by the four multipliers can be made the same, so the number of shifters SFT included in each product-sum calculation circuit PS2 can be reduced to one-fourth the number of shifters SFT included in each product-sum calculation circuit PS1 in FIG. 3.

[0069] 14 and 15 may output partial sums DBL0, DBL1, DBL2, and DBL3 of the multiplication results of the 32 sets of partial mantissa data of matrices A and B to adder d in Fig. 15. Adder d (Fig. 15) may add the partial sums DBL0, DBL1, DBL2, and DBL3 and output the multiplication result DBL of the mantissa part of the double-precision block floating-point number data.

[0070] As described above, the second embodiment can also achieve the same effects as the first embodiment. For example, the arithmetic device 100 can perform matrix multiplication of block floating-point number data of multiple types of precision using a common multiplication execution unit 141. For example, each multiplication execution unit 141 can perform matrix multiplication of block floating-point number data of half precision, pseudo single precision, single precision, and double precision.

[0071] By using the correction value CV instead of the data pairs of the lower-order bit group not assigned to the multiplier of the multiply-accumulate circuit PS2, it is possible to suppress a decrease in the accuracy of the matrix multiplication result even when multiplication of the lower-order partial mantissa data pairs is not performed. Also, even when one multiplication execution unit 141 is used for matrix multiplication of the mantissa parts of block floating-point number data of multiple precisions, the correction value generation circuit CVGEN can prevent the correction value CV from being generated during matrix multiplication when the correction value CV is not required, thereby suppressing malfunction of the arithmetic device 100.

[0072] By stopping the operation of some of the multipliers in the product-sum calculation circuit PS2, the power consumption of the multiplication execution unit 141 and the calculation device 100 can be reduced.

[0073] Furthermore, in the second embodiment, by connecting a shifter SFT to the output of adder e, which adds the multiplication results from multiple multipliers, the number of shifters SFT included in each product-sum calculation circuit PS2 can be reduced compared to when a shifter SFT is connected to the output of each multiplier.As a result, the circuit scale of the product-sum calculation circuit PS2 can be made smaller than that of the product-sum calculation circuit PS1, and the circuit scale of the multiplication execution unit 141 can be reduced.In addition, by reducing the number of shifters SFT, the power consumption of the product-sum calculation circuit PS2 and the multiplication execution unit 141 can be reduced.

[0074] Fig. 16 is a block diagram showing an example of the hardware configuration of a computer equipped with the arithmetic device 100 shown in Fig. 1. In Fig. 16, the computer may be realized as a computer 500 including, for example, the arithmetic device 100, a main storage device 30 (memory), an auxiliary storage device 40 (memory), a network interface 50, and a device interface 60, which are connected via a bus 510. For example, the main storage device 30 may be the external memory 200 shown in Fig. 1.

[0075] Although the computer 500 in FIG. 16 includes one of each component, it may also include multiple of the same component. Also, while FIG. 16 shows one computer 500, the software may be installed on multiple computers, and each of the multiple computers may execute the same or different parts of the software's processing. In this case, a form of distributed computing may be used in which each computer communicates with the other computers via a network interface 50 or the like to execute processing. In other words, a system may be configured in which one or more computers 500 execute instructions stored in one or more storage devices to achieve a function. Furthermore, a configuration may be used in which information transmitted from a terminal is processed by one or more computers 500 provided on a cloud, and the processing results are then transmitted to the terminal.

[0076] Various computations may be executed in parallel using one or more computation devices 100 installed in the computer 500, or using multiple computers 500 via a network. Furthermore, various computations may be distributed to multiple computation cores within the computation device 100 and executed in parallel. Furthermore, some or all of the processes, means, etc. disclosed herein may be realized by at least one of a processor and a storage device provided on a cloud that can communicate with the computer 500 via a network. In this way, each device in the above-described embodiment may be in the form of parallel computing using one or multiple computers.

[0077] The computing device 100 may be an electronic circuit (processing circuit, processing circuitry, CPU, GPU, FPGA, ASIC, etc.) that performs at least one of computer control and calculation. The computing device 100 may also be a general-purpose processor, a dedicated processing circuit designed to perform a specific calculation, or a semiconductor device that includes both a general-purpose processor and a dedicated processing circuit. The computing device 100 may also include an optical circuit or a calculation function based on quantum computing.

[0078] The arithmetic device 100 may perform arithmetic processing based on data or software input from each device or the like configured internally of the computer 500, and may output arithmetic results or control signals to each device or the like. The arithmetic device 100 may control each component constituting the computer 500 by executing an OS (Operating System) of the computer 500, an application, or the like.

[0079] The main memory device 30 may store instructions executed by the arithmetic device 100 and various data, and information stored in the main memory device 30 may be read by the arithmetic device 100. The auxiliary memory device 40 is a memory device other than the main memory device 30. Note that these memory devices refer to any electronic component capable of storing electronic information, and may be semiconductor memory. The semiconductor memory may be either volatile memory or non-volatile memory. A memory device for saving various data, etc. in the computer 500 may be realized by the main memory device 30 or the auxiliary memory device 40, or may be realized by an internal memory built into the arithmetic device 100.

[0080] When the computer 500 is configured with at least one storage device (memory) and at least one arithmetic device 100 connected (coupled) to this at least one storage device, at least one arithmetic device 100 may be connected to one storage device. Also, at least one storage device may be connected to one arithmetic device 100. Also, a configuration may be included in which at least one arithmetic device 100 out of multiple arithmetic devices 100 is connected to at least one storage device out of multiple storage devices. Also, this configuration may be realized by storage devices and arithmetic devices 100 included in multiple computers 500. Furthermore, a configuration in which a storage device is integrated with the arithmetic device 100 (for example, a cache memory including an L1 cache and an L2 cache) may be included.

[0081] The network interface 50 is an interface for connecting to the communication network 600 wirelessly or via a wire. The network interface 50 may be an appropriate interface, such as one that conforms to an existing communication standard. Information may be exchanged with an external device 710 connected via the communication network 600 through the network interface 50. The communication network 600 may be any one of a wide area network (WAN), a local area network (LAN), a personal area network (PAN), etc., or a combination thereof, as long as information is exchanged between the computer 500 and the external device 710. An example of a WAN is the Internet, an example of a LAN is IEEE802.11 or Ethernet (registered trademark), and an example of a PAN is Bluetooth (registered trademark) or NFC (Near Field Communication), etc.

[0082] The device interface 60 is an interface such as a USB that directly connects to an external device 720 .

[0083] The external device 710 is a device connected to the computer 500 via a network. The external device 720 is a device directly connected to the computer 500.

[0084] For example, the external device 710 or the external device 720 may be an input device. The input device is, for example, a device such as a camera, a microphone, a motion capture device, various sensors, a keyboard, a mouse, or a touch panel, and provides acquired information to the computer 500. Alternatively, the external device 710 or the external device 720 may be a device including an input unit, a memory, and a processor, such as a personal computer, a tablet terminal, or a smartphone.

[0085] Furthermore, the external device 710 or the external device 720 may be, for example, an output device. The output device may be, for example, a display device such as an LCD (Liquid Crystal Display) or an organic EL (Electro Luminescence) panel, or may be a speaker that outputs sound or the like. Alternatively, the output device may be a device including an output unit, a memory, and a processor, such as a personal computer, a tablet terminal, or a smartphone.

[0086] Furthermore, the external device 710 or the external device 720 may be a storage device (memory). For example, the external device 710 may be a network storage or the like, and the external device 720 may be a storage such as an HDD.

[0087] Furthermore, external device 710 or external device 720 may be a device having some of the functions of the components of computer 500. In other words, computer 500 may transmit some or all of the processing results to external device 710 or external device 720, or may receive some or all of the processing results from external device 710 or external device 720.

[0088] In this specification (including the claims), when the expression "at least one of a, b, and c" or "at least one of a, b, or c" (including similar expressions) is used, it includes any of a, b, c, ab, ac, bc, or abc. It may also include multiple instances of any element, such as aa, abb, aabbcc, etc. Furthermore, it also includes the addition of elements other than the enumerated elements (a, b, and c), such as having d, as in abcd.

[0089] In this specification (including claims), when expressions such as "using data as input / based on / according to / in response to data" (including similar expressions) are used, unless otherwise specified, this includes cases where the data itself is used, or where data that has been processed in some way (e.g., data with noise added, normalized data, features extracted from data, intermediate representations of data, etc.) is used. Furthermore, when a statement is made that a result is obtained "using data as input / based on / according to / in response to data" (including similar expressions), this includes cases where the result is obtained based solely on the data, or where the result is influenced by other data, factors, conditions, and / or states other than the data itself, unless otherwise specified. Furthermore, when a statement is made that "data is output" (including similar expressions), this includes cases where the data itself is used as output, or where data that has been processed in some way (e.g., data with noise added, normalized data, features extracted from data, intermediate representations of various data, etc.) is used as output, unless otherwise specified.

[0090] When the terms "connected" and "coupled" are used in this specification (including the claims), they are intended as open-ended terms that encompass any of direct connection / coupling, indirect connection / coupling, electrically connection / coupling, communicatively connection / coupling, functionally connection / coupling, and physically connection / coupling. These terms should be interpreted appropriately according to the context in which they are used, but any form of connection / coupling that is not intentionally or naturally excluded should be interpreted as being included in these terms without limitation.

[0091] In this specification (including the claims), the expression "A configured to B" may include the physical structure of element A having a configuration capable of performing operation B, and the permanent or temporary setting / configuration of element A being configured / set to actually perform operation B. For example, if element A is a general-purpose processor, it is sufficient that the processor has a hardware configuration capable of performing operation B, and is configured to actually perform operation B by setting a permanent or temporary program (instruction). Also, if element A is a dedicated processor, dedicated arithmetic circuit, etc., it is sufficient that the circuit structure, etc. of the processor is implemented to actually perform operation B, regardless of whether control instructions and data are actually attached.

[0092] Whenever words implying containing or possessing (e.g., "comprising / including," "having," etc.) are used in this specification (including the claims), they are intended to be open-ended terms that include the inclusion or possession of things other than the object designated by the object of the term. When the object of such words implying containing or possessing does not specify a quantity or suggests a singular number (e.g., expressions using the articles "a" or "an"), the expression should be construed as not being limited to a specific number.

[0093] In this specification (including the claims), even if expressions such as "one or more" and "at least one" are used in some places and expressions that do not specify a quantity or that imply a singular number (expressions using the articles "a" or "an") are used in other places, the latter expressions are not intended to mean "one." In general, expressions that do not specify a quantity or that imply a singular number (expressions using the articles "a" or "an") should be interpreted as not necessarily being limited to a specific number.

[0094] In this specification, when a particular advantage / result is described as being obtained with respect to a particular configuration of an embodiment, it should be understood that the same advantage / result can also be obtained with one or more other embodiments having the same configuration, unless otherwise stated. However, it should be understood that the presence or absence of the effect generally depends on various factors, conditions, and / or circumstances, and that the effect is not necessarily obtained with the configuration. The effect is merely obtained by the configuration described in the embodiment when various factors, conditions, and / or circumstances are satisfied, and the effect does not necessarily occur in a claimed invention that defines the same or a similar configuration.

[0095] In this specification (including claims), when multiple pieces of hardware perform a predetermined process, the pieces of hardware may cooperate to perform the predetermined process, or some of the hardware may perform all of the predetermined process. Furthermore, some of the hardware may perform part of the predetermined process, and other hardware may perform the rest of the predetermined process. In this specification (including claims), when an expression such as "one or more pieces of hardware perform a first process, and the one or more pieces of hardware perform a second process" (including similar expressions) is used, the hardware performing the first process and the hardware performing the second process may be the same or different. In other words, it is sufficient that the hardware performing the first process and the hardware performing the second process are included in the one or more pieces of hardware. Note that hardware may include electronic circuits, devices including electronic circuits, etc.

[0096] In this specification (including the claims), when multiple storage devices (memories) store data, each of the multiple storage devices may store only a portion of the data, or may store the entire data. Also, a configuration in which only some of the multiple storage devices store data may be included.

[0097] Although the embodiments of the present disclosure have been described in detail above, the present disclosure is not limited to the individual embodiments described above. Various additions, modifications, substitutions, partial deletions, etc. are possible within the scope of the conceptual idea and spirit of the present invention, which is derived from the content defined in the claims and their equivalents. For example, when numerical values or formulas are used in the above-described embodiments, they are shown for illustrative purposes and do not limit the scope of the present disclosure. Furthermore, the order of each operation shown in the embodiments is also illustrative and does not limit the scope of the present disclosure.

[0098] The disclosed technology may take the following forms as described below. (Appendix 1) An arithmetic unit capable of performing matrix multiplication of mantissa parts of floating-point number data, comprising: a plurality of product-sum calculation circuits each including a plurality of multipliers that multiply the data pairs of the mantissa parts, and a first adder that adds the multiplication results of the plurality of multipliers and a correction value; an adder circuit that adds the operation results output from the plurality of multiply-add operation circuits and outputs the addition result as a matrix multiplication result of data of mantissa parts in any one of a plurality of floating-point number formats; Computing device. (Appendix 2) each of the plurality of multiply-accumulate circuits includes a plurality of second adders connected to the multiplier, and a shifter connected between the plurality of second adders and the first adder; 10. The computing device of claim 1. (Appendix 3) when the number of bits of each of the data pairs of the mantissa parts supplied to the multiply-accumulate operation circuit is greater than the number of bits that can be processed by each of the plurality of multipliers, the plurality of multipliers assign to the plurality of multipliers multiplication of the partial mantissa data pairs of combinations of more significant bits among a plurality of partial mantissa data pairs each obtained by dividing each of the data pairs of the mantissa parts, the correction value is input to the first adder in place of the partial mantissa data pairs not assigned to the plurality of multipliers; 10. The computing device of claim 1. (Appendix 4) the multiply-accumulate operation circuit includes a correction value generation circuit that generates the correction value based on the partial mantissa data pairs that are not assigned to the plurality of multipliers; 4. The computing device of claim 3. (Appendix 5) an instruction output circuit for outputting control information for identifying a type of matrix multiplication to be performed and the floating-point number format together with a data pair of a mantissa part of the floating-point number data to the multiply-add operation circuit; the correction value generation circuit determines whether to generate the correction value based on the control information. 5. The computing device of claim 4. (Appendix 6) the multiply-accumulate circuit stops operations of some of the multipliers based on the control information; 6. The computing device of claim 5. (Appendix 7) The adding circuit a plurality of third adders that add two operation results output from the two product-sum operation circuits, respectively; a plurality of fourth adders that add the addition results output from the two third adders; when a pair of data of mantissa parts in a first floating-point number format is supplied to each of the multiply-accumulate circuits, the third adder outputs a matrix multiplication result of the data of mantissa parts in the first floating-point number format; when a data pair of mantissa parts in a second floating-point number format, the number of bits of which is greater than the number of bits of the mantissa parts of the first floating-point number format, is supplied to each of the multiply-add calculation circuits, the fourth adder outputs a matrix multiplication result of the data of the mantissa parts in the second floating-point number format. 7. The computing device according to claim 1, (Appendix 8) each of the plurality of multipliers is a 9-bit multiplier; the first floating-point number format is a half-precision floating-point number format; the second floating-point number format is a single-precision floating-point number format or a pseudo-single-precision floating-point number format in which the number of bits of a mantissa is greater than the number of bits of a mantissa of a half-precision floating-point number format and less than the number of bits of a mantissa of a single-precision floating-point number format; 8. The computing device of claim 7. (Appendix 9) the adder circuit further includes a plurality of fifth adders that add the addition results output from the four fourth adders; When a pair of data of mantissa parts in double-precision floating-point number format is supplied to each of the multiply-add calculation circuits, the fifth adder outputs a matrix multiplication result of the data of mantissa parts in double-precision floating-point number format. 9. The computing device of claim 8. (Appendix 10) The multipliers include 2 to the power i (i is a positive integer of 2 or more), 10. The computing device according to any one of claims 1 to 9. [Explanation of symbols]

[0099] 30 Main memory 40 Auxiliary storage 50 Network Interface 60 Device Interfaces 100 Computing equipment 110 instruction memory 120 Instruction supply circuit 130 Instruction Decoder 140 computing units 141 Multiplication execution unit 150 Register File 200 external memory 500 computers 510 Bus 600 Communication Network 710, 720 External device C Carrie CV correction value CVGEN Correction value generation circuit DBL Matrix multiplication result for double precision data DBL0, DBL1, DBL2, DBL3 partial sum HALF Result of matrix multiplication of half-precision data PS1, PS2 multiply-and-accumulate circuits SFT Shifter SNGL Result of matrix multiplication of single precision data SSNGL Result of matrix multiplication of pseudo single precision data

Claims

1. An arithmetic unit capable of performing matrix multiplication of mantissa parts of floating-point number data, comprising: a plurality of product-sum calculation circuits each including a plurality of multipliers that multiply the data pairs of the mantissa parts, and a first adder that adds the multiplication results of the plurality of multipliers and a correction value; an adder circuit that adds the operation results output from the plurality of multiply-add operation circuits and outputs the addition result as a matrix multiplication result of data of mantissa parts in any one of a plurality of floating-point number formats; Computing device.

2. each of the plurality of multiply-accumulate circuits includes a plurality of second adders connected to the multiplier, and a shifter connected between the plurality of second adders and the first adder; The computing device of claim 1 .

3. when the number of bits of each of the data pairs of the mantissa parts supplied to the multiply-accumulate operation circuit is greater than the number of bits that can be processed by each of the plurality of multipliers, the plurality of multipliers assign to the plurality of multipliers multiplication of the partial mantissa data pairs of combinations of more significant bits among a plurality of partial mantissa data pairs each obtained by dividing each of the data pairs of the mantissa parts, the correction value is input to the first adder in place of the partial mantissa data pairs not assigned to the plurality of multipliers; The computing device of claim 1 .

4. the multiply-accumulate operation circuit includes a correction value generation circuit that generates the correction value based on the partial mantissa data pairs that are not assigned to the plurality of multipliers; The computing device according to claim 3 .

5. an instruction output circuit for outputting control information for identifying a type of matrix multiplication to be performed and the floating-point number format together with a data pair of a mantissa part of the floating-point number data to the multiply-add operation circuit; the correction value generation circuit determines whether to generate the correction value based on the control information. The computing device according to claim 4.

6. the multiply-accumulate circuit stops operations of some of the multipliers based on the control information; The computing device according to claim 5 .

7. The adding circuit a plurality of third adders that add two operation results output from the two product-sum operation circuits, respectively; a plurality of fourth adders that add the addition results output from the two third adders; when a pair of data of mantissa parts in a first floating-point number format is supplied to the multiply-accumulate operation circuits, the third adder outputs a matrix multiplication result of the data of mantissa parts in the first floating-point number format; when a data pair of mantissa parts in a second floating-point number format, the number of bits of which is greater than the number of bits of the mantissa parts of the first floating-point number format, is supplied to each of the multiply-add calculation circuits, the fourth adder outputs a matrix multiplication result of the data of the mantissa parts in the second floating-point number format. The computing device according to any one of claims 1 to 6.

8. each of the plurality of multipliers is a 9-bit multiplier; the first floating-point number format is a half-precision floating-point number format; the second floating-point number format is a single-precision floating-point number format or a pseudo-single-precision floating-point number format in which the number of bits of a mantissa is greater than the number of bits of a mantissa of a half-precision floating-point number format and less than the number of bits of a mantissa of a single-precision floating-point number format; The computing device according to claim 7.

9. the adder circuit further includes a plurality of fifth adders that add the addition results output from the four fourth adders; when a pair of data of mantissa parts in double-precision floating-point number format is supplied to each of the multiply-add calculation circuits, the fifth adder outputs a matrix multiplication result of the data of mantissa parts in double-precision floating-point number format. The computing device according to claim 8 .

10. The multiplier includes 2 to the power i (i is a positive integer of 2 or more), The computing device according to any one of claims 1 to 6.

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