Protection circuit and semiconductor device

Abstract

To provide a protection circuit and a semiconductor device that can prevent an internal circuit from floating while suppressing current consumption to be low.SOLUTION: A protection circuit 1A includes: an NMOS transistor 11 including a first end (source) connected to one end of a current path P1 formed by parasitic diodes 6_1 to 6_n of semiconductor elements included in an internal circuit 6, a second end (drain) connected to a GND terminal 4, and a control end (gate); and a current limiting circuit 5A connected in parallel with the NMOS transistor 11.SELECTED DRAWING: Figure 1

Description

[Technical Field]

[0001] The present invention relates to a protection circuit and a semiconductor device. [Background technology]

[0002] A power supply device (e.g., a secondary battery) that supplies power to a semiconductor device may apply a power supply voltage of the opposite polarity (hereinafter simply referred to as "reverse polarity") to the polarity applied in a steady state due to reverse connector connection, noise, etc. Typical semiconductor devices are configured to include a parasitic diode that is forward biased with respect to the reverse polarity power supply voltage. Therefore, when a reverse polarity power supply voltage is applied to a semiconductor device that is not designed to be subjected to the application of a reverse polarity power supply voltage, an excessive forward current flows through the parasitic diode, which may damage elements that constitute the semiconductor device. From the perspective of preventing damage to elements due to the application of such a reverse polarity power supply voltage, a technology for protecting integrated circuits has been disclosed (see, for example, Patent Document 1).

[0003] A protection circuit to which the technology disclosed in Patent Document 1 is applied has an NPN bipolar transistor including a base connected via a resistor to a VCC terminal that supplies a power supply voltage VCC (≠0V), a collector connected to an internal circuit to be protected (hereinafter referred to as the "protected object" or "protected circuit"), and an emitter connected to a GND terminal that supplies a power supply voltage of 0V.

[0004] When no reverse polarity power supply voltage is applied, i.e., in a steady state where the power supply voltage VCC is a positive voltage (VCC > 0), if the power supply voltage VCC is sufficiently higher than the forward voltage Vf of the base-emitter diode of the NPN bipolar transistor, the current driving force increases and the collector-emitter voltage can be considered to be approximately 0 V. Therefore, in steady state, the internal circuit can be considered to be directly connected to the GND terminal.

[0005] On the other hand, when a reverse-polarity power supply voltage is applied, i.e., when the power supply voltage VCC is a negative voltage (VCC<0), the base voltage follows the power supply voltage VCC and no base current flows. As a result, the NPN bipolar transistor in the protection circuit enters a cutoff state, blocking the collector current. Blocking the collector current blocks excessive forward current through the parasitic diode, which can damage elements when the internal circuit is directly connected to the GND terminal. This ultimately protects the protected device from damage caused by the application of a reverse-polarity power supply voltage. [Prior art documents] [Patent documents]

[0006] [Patent Document 1] Japanese Patent Application Publication No. 10-289956 Summary of the Invention [Problem to be solved by the invention]

[0007] However, in the case of a conventional protection circuit employing the technology disclosed in Patent Document 1 and a semiconductor device equipped with such a protection circuit, the internal circuit becomes floating when the NPN bipolar transistor in the protection circuit is in the cut-off state. A floating internal circuit can have undesirable effects, and there is room for improvement. More specifically, a floating internal circuit increases the possibility of electrostatic breakdown due to charge accumulation and discharge in the protected object, and increases the possibility of malfunction due to electromagnetic noise interference.

[0008] On the other hand, if a base current is passed through the NPN bipolar transistor in the protection circuit, the NPN bipolar transistor will not be cut off and the internal circuit will not be floating. However, passing a base current through the NPN bipolar transistor is not desirable because it hinders the reduction of current consumption.

[0009] The present invention has been made in consideration of the above circumstances, and an object of the present invention is to provide a protection circuit and a semiconductor device that can prevent an internal circuit from floating while suppressing current consumption. [Means for solving the problem]

[0010] A protection circuit according to an embodiment of the present invention is characterized by comprising a protection transistor including a first end connected to one end of a current path formed by a parasitic diode of a semiconductor element included in an internal circuit, a second end connected to a first power supply terminal, and a control end, and a current limiting circuit connected in parallel with the protection transistor. [Effects of the Invention]

[0011] According to the present invention, it is possible to prevent the internal circuit from floating while suppressing current consumption. [Brief explanation of the drawings]

[0012] [Figure 1] 1 is a circuit diagram showing a configuration example (first configuration example) of a protection circuit and a semiconductor device according to a first embodiment of the present invention. [Figure 2] 1A is a circuit diagram showing a first configuration example of a step-down circuit provided in a semiconductor device according to a first embodiment, the step-down circuit having a load including a constant current source; FIG. 1B is a circuit diagram showing a first configuration example of a constant current source as a load; and FIG. 1C is a circuit diagram showing a second configuration example of a constant current source as a load. [Figure 3] 4 is a circuit diagram showing a configuration example (second configuration example) of the protection circuit and semiconductor device according to the first embodiment. FIG. [Figure 4] 10A, 10B, and 10C are circuit diagrams showing second, third, and fourth configuration examples of the load of the step-down circuit in the semiconductor device according to the first embodiment, respectively. [Figure 5] FIG. 10 is a circuit diagram showing a modification (third configuration example) of the protection circuit and the semiconductor device according to the second embodiment. [Figure 6]FIG. 10 is a circuit diagram showing a modification (fourth configuration example) of the protection circuit and the semiconductor device according to the second embodiment. [Figure 7] 10A, 10B, and 10C are circuit diagrams showing a first configuration example, a second configuration example, and a third configuration example of a current / voltage conversion circuit included in a step-down circuit in a semiconductor device according to a second embodiment. [Figure 8] 10A and 10B are circuit diagrams showing a first configuration example and a second configuration example, respectively, of a constant current source provided in a step-down circuit in a semiconductor device according to a second embodiment. [Figure 9] FIG. 10 is a circuit diagram showing a portion of a modified example (second configuration example) of the step-down circuit in the protection circuit according to the second embodiment. DETAILED DESCRIPTION OF THE INVENTION

[0013] DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS A protection circuit and a semiconductor device according to an embodiment of the present invention will be described below with reference to the drawings.

[0014] [First embodiment] FIG. 1 is a circuit diagram of a protection circuit 1A, which is an example of a protection circuit according to the first embodiment, and a semiconductor device 10A, which is an example of a semiconductor device according to the first embodiment.

[0015] The semiconductor device 10A includes a protection circuit 1A and a protected circuit 2A that is the object of protection by the protection circuit 1A. The protection circuit 1A and the protected circuit 2A are configured as semiconductor integrated circuits. The semiconductor device 10A includes a first end connected to a VDD terminal 3 that supplies a voltage VDD, which is an example of a power supply voltage, and a second end connected to a GND terminal 4 that is a ground terminal that supplies a ground voltage GND, which is an example of a power supply voltage different from the voltage VDD. Here, the connection point between the first end of the semiconductor device 10A and the VDD terminal 3 is referred to as node N1, and the connection point between the second end of the semiconductor device 10A and the GND terminal 4 is referred to as node N2.

[0016] The protected circuit 2A is connected to the node N1 and includes a first terminal corresponding to the first terminal of the semiconductor device 10A, a second terminal connected to the GND terminal 4 if the protection circuit 1A is not present, and an output terminal that supplies a gate voltage Vg to the protection circuit 1A. The protection circuit 1A includes a first terminal connected to the second terminal of the protected circuit 2A, a second terminal connected to the GND terminal 4, and an input terminal that receives the gate voltage Vg from the protected circuit 2A. Here, the connection point between the protection circuit 1A (first terminal) and the protected circuit 2A (second terminal) is referred to as a node N3.

[0017] The protection circuit 1A includes an NMOS transistor 11, which is an example of an N-type field effect transistor (FET), and a current limiting circuit 5A connected in parallel with the NMOS transistor 11 as a protection transistor.

[0018] The NMOS transistor 11 includes a source as a first terminal, a drain as a second terminal, and a gate as an input terminal. The source of the NMOS transistor 11 corresponds to the first terminal of the protection circuit 1A and is connected to the second terminal of the protected circuit 2A. The drain of the NMOS transistor 11 corresponds to the second terminal of the protection circuit 1A and is connected to the GND terminal 4. The gate of the NMOS transistor 11 is connected to the output terminal of the protected circuit 2A.

[0019] The current limiting circuit 5A has, for example, a depletion-type NMOS transistor 51 whose gate and source are connected together. In the depletion-type NMOS transistor 51, the drain is connected to the drain of the NMOS transistor 11. The source is connected to the source of the NMOS transistor 11 and the gate of the depletion-type NMOS transistor 51. The gate is connected to the source of the NMOS transistor 11. In other words, the depletion-type NMOS transistor 51 includes a drain as a first end connected to the drain of the NMOS transistor 11, a source as a second end connected to the source of the NMOS transistor 11, and a gate as a control end connected to its own source (the depletion-type NMOS transistor 51).

[0020] The protected circuit 2A includes an internal circuit 6 using a semiconductor element such as an FET, and a source follower 7 connected in parallel to the internal circuit 6 as a step-down circuit.

[0021] Since the semiconductor element includes a parasitic diode, in the internal circuit 6 to which the semiconductor element is applied, a current path P1 is formed by one parasitic diode 6_1 or a plurality of n (n is an integer of 2 or more) parasitic diodes 6_1 to 6_n, which electrically connects the node N3 and the node N1. That is, both ends of the current path P1 correspond to both ends of the internal circuit 6. Here, of the both ends of the current path P1 and the internal circuit 6, the end connected to the node N1 is referred to as a first end, and the end connected to the node N3 is referred to as a second end.

[0022] The source follower 7 has a depletion-mode NMOS transistor 70, a load 71, a control terminal 73, and an output terminal 74. The depletion-mode NMOS transistor 70 and the load 71 are connected in series between the node N1 and the node N3.

[0023] A depletion-mode NMOS transistor 70 serving as a step-down transistor includes a drain as a first end, a source as a second end, and a gate as a control end. A load 71 includes a first end connected to the second end of the current path P1, i.e., a node N3, and a second end connected to the source of the depletion-mode NMOS transistor 70. Here, the connection point between the depletion-mode NMOS transistor 70 (source) and the load 71 (second end) is referred to as a node N4.

[0024] In the depletion-mode NMOS transistor 70, the drain is connected to the first end of the current path P1, i.e., the node N1, the source is connected to the second end of the load 71 and the output terminal 74, and the gate is connected to the control terminal 73.

[0025] The control terminal 73 is connected to any node outside the source follower 7 that can supply a predetermined bias voltage Vbias, such as a node in the internal circuit 6. Connecting the control terminal 73 to a node in the internal circuit 6 is advantageous in that it allows the bias voltage Vbias to be supplied without adding a new circuit. The output terminal 74 is connected outside the source follower 7 to the gate of the NMOS transistor 11 that corresponds to the input terminal of the protection circuit 1A.

[0026] Next, the constant current source 711, which is a first configuration example of the load 71, will be described. Fig. 2(A) is a circuit diagram showing a first example configuration of load 71 including constant current source 711. Fig. 2(B) is a circuit diagram showing the first example configuration of constant current source 711, and Fig. 2(C) is a circuit diagram showing a second example configuration of constant current source 711.

[0027] The constant current source 711 includes a first terminal connected to the node N4 and a second terminal connected to the node N3, and is configured to be able to supply a constant current I1 (see FIG. 2A). The constant current source 711 has, for example, a depletion-type NMOS transistor 31 as a depletion-type FET whose source and gate are connected, and is configured to pass the constant current I1 through the drain of the depletion-type NMOS transistor 31 (see FIG. 2B).

[0028] The constant current source 711 may be configured to include a current mirror circuit 32 configured by connecting two NMOS transistors 321 and 322, and a constant current source 33 that supplies a constant current I2 to the drain of the NMOS transistor 322. The current mirror circuit 32 is configured by connecting the gate of the NMOS transistor 322 to its own drain and the gate of the NMOS transistor 321. The constant current source 711 having the current mirror circuit 32 and the constant current source 33 can supply a constant current I1 (=m1×I2) that is a copy of the constant current I2 that flows to the drain of the NMOS transistor 322 at a predetermined mirror ratio m1 (m1 is an arbitrary positive number) to the drain of the NMOS transistor 321.

[0029] Next, the circuit operations of the protection circuit 1A and the semiconductor device 10A will be explained in order, dividing them into (1) a state in which the power supply is connected correctly and a positive power supply voltage VDD (>0V) is supplied from the VDD terminal 3 (hereinafter referred to as the "steady state"), (2) a state in which the power supply is connected in reverse and a negative power supply voltage VDD (<0V) is supplied from the VDD terminal 3 (hereinafter referred to as the "reverse connection state"), (3) a state in which the internal circuit 6 is in standby mode (hereinafter simply referred to as the "standby state"), and (4) a state in which no voltage VDD is supplied from the VDD terminal 3 (hereinafter referred to as the "VDD terminal open state").

[0030] (1) Steady state The current flowing in the internal circuit 6 flows in the direction from the VDD terminal 3 to the GND terminal 4, i.e., from node N1 to node N3. When the NMOS transistor 11 is controlled by supplying a gate voltage Vg from the source follower 7, a bias voltage Vbias, which is the gate voltage of the depletion-type NMOS transistor 70, is set so that the gate voltage Vg of the NMOS transistor 11 is higher than its threshold voltage Vth. When the bias voltage Vbias set in this way is applied to the gate of the depletion-type NMOS transistor 70, the NMOS transistor 11 turns on and a current flows from the source (node N3) to the drain (node N2) of the NMOS transistor 11.

[0031] The gate voltage Vg can be approximated by the following equation (1) using the bias voltage Vbias, the gate-source voltage Vgs of the depletion-mode NMOS transistor 70, and the threshold voltage Vth_sf of the depletion-mode NMOS transistor 70. Vg=Vbias-Vgs≒Vbias-Vth_sf>Vth ---(1)

[0032] Here, when a depletion-type NMOS transistor 70, which is a depletion-type FET having a negative threshold voltage, is used as the step-down transistor of the source follower 7, the gate voltage Vg is set to be larger than the bias voltage Vbias, that is, the following equation (2) is satisfied: Vg≧Vbias ---(2) The source follower 7 can be configured so as to satisfy the above formula (2). By configuring the source follower 7 to satisfy the above formula (2), the NMOS transistor 11 can be easily turned on.

[0033] On the other hand, the depletion-mode NMOS transistor 51, whose gate and source are connected (short-circuited), can be regarded as a diode-connected FET in the steady state, and therefore allows current to flow from the source to the drain when on. To ensure stable operation of the internal circuit 6, it is preferable to operate the internal circuit 6 at a voltage close to the ground voltage GND, which is the voltage of the GND terminal 4, at the reference node, node N3. When the voltage of node N3 is close to the ground voltage GND, both the NMOS transistor 11 and the depletion-mode NMOS transistor 51 operate in a resistance region where the drain-source voltage is close to 0V. Therefore, the current flowing from node N1, which is connected to the VDD terminal 3, to node N3 flows to the GND terminal 4 via the on-resistance of the NMOS transistor 11 and the depletion-mode NMOS transistor 51.

[0034] Here, the voltage of node N3, the on-resistance of NMOS transistor 11, the on-resistance of depletion-type NMOS transistor 51, the combined resistance obtained by connecting the on-resistance of NMOS transistor 11 and the on-resistance of depletion-type NMOS transistor 51 in parallel, and the current flowing from node N3 to node N4 can be expressed by the following equation (3), respectively: VN3=(Ron_prt / / Ron_dep)×Iope_gnd =Ron×Iope_gnd ---(3)

[0035] Here, from the above formula (3), if the combined resistance Ron is designed to be sufficiently small by increasing the aspect ratio of the NMOS transistor 11 and the depletion-type NMOS transistor 51 or by setting the gate voltage Vg supplied to the gate of the NMOS transistor 11 higher, the internal circuit 6 can be brought closer to a state connected to the GND terminal 4, i.e., a grounded state. By bringing the internal circuit 6 closer to a grounded state, it is possible to prevent the internal circuit 6 from floating.

[0036] (2) Reverse connection When a negative voltage is applied to the VDD terminal 3, the gate voltage Vg of the NMOS transistor 11 and the voltage VN3 of the node N3 decrease following the voltage VDD due to the forward bias of the parasitic diodes 6_1 to 6_n in the internal circuit 6. When the gate voltage Vg of the NMOS transistor 11 and the voltage VN3 of the node N3 decrease and the gate-source voltage Vgs11 of the NMOS transistor 11 falls below the threshold voltage Vth, the NMOS transistor 11 turns off.

[0037] On the other hand, the depletion-mode NMOS transistor 51, whose gate and source are connected (short-circuited), can be regarded as a constant current source, and can therefore limit the current in the direction from the drain connected to node N2 to the source connected to node N3. Here, the threshold voltage VTND of the depletion-mode NMOS transistor 51 is negative (VTND<0V) and the gate-source voltage Vgs51 is 0V (Vgs51=0V), so when the drain-source voltage is equal to or greater than the absolute value |VTND| of the threshold voltage, the transistor operates in the saturation region based on equation (4), a general transistor equation. VDS≧VGS-VTH ---(4) VDS: Drain-source voltage VGS: Gate-source voltage VTH: Threshold voltage

[0038] Here, if the current flowing from the drain to the source of the depletion-mode NMOS transistor 51 is defined as a reverse current Irev and the transconductance coefficient Kdep of the depletion-mode NMOS transistor 51 is defined as a constant, the reverse current Irev can be expressed by the following equation (5) because it is the drain current of the depletion-mode NMOS transistor 51. Irev=Kdep×|VTND| 2 ---(5)

[0039] The reverse current Irev is generally undesirable because it flows to the VDD terminal 3 via the protected circuit 2A (more specifically, the internal circuit 6 or the source follower 7). However, the transconductance coefficient Kdep can be reduced by, for example, reducing the aspect ratio of the depletion-mode NMOS transistor 51. By setting the transconductance coefficient Kdep to a small value, the depletion-mode NMOS transistor 51 can be configured to limit the reverse current Irev to an allowable current value.

[0040] (3) Standby state In the standby state, the current flowing through the source follower 7 is cut off to reduce current consumption. With the current flowing through the source follower 7 cut off, the gate voltage Vg of the NMOS transistor 11 drops below the threshold voltage Vth of the NMOS transistor 11, turning the NMOS transistor 11 off. On the other hand, the depletion-type NMOS transistor 51, whose gate and source are connected (short-circuited), can be regarded as a diode-connected FET, as in the (1) steady state, and operates in the resistance region of its on-resistance, resistance Ron_dep.

[0041] Here, (3) if the current flowing from the internal circuit 6 in the standby state is a standby current Istb, the voltage VN3 of the node N3 can be expressed by the following equation (6). VN3=Ron_dep×Istb ---(6) From equation (6), if the combined resistance Rdep is designed to be sufficiently small, for example by increasing the aspect ratio of the depletion-mode NMOS transistor 51, then even in the standby state in which current consumption is reduced, the internal circuit 6 can be brought closer to the state in which it is connected to the GND terminal 4, i.e., the ground state, just as in the steady state (1). By bringing the internal circuit 6 closer to the ground state, it is possible to prevent the internal circuit 6 from floating.

[0042] (4) VDD pin open state When the VDD terminal is open, the voltage VDD is not supplied from the VDD terminal 3 to the node N1, so the NMOS transistor 11 is turned off. On the other hand, the depletion-mode NMOS transistor 51, whose gate and source are connected (short-circuited), can be regarded as a diode-connected FET, as in the (1) steady state and the (3) standby state, and operates in the resistance region of its on-resistance, resistance Ron_dep. Therefore, as in the (1) steady state and the (3) standby state, the internal circuit 6 can be brought closer to the ground state. By bringing the internal circuit 6 closer to the ground state, floating of the internal circuit 6 can be prevented.

[0043] Here, we will explain an example of a design procedure for bringing the internal circuit 6 closer to the ground state in (1) the steady state, (3) the standby state, and (4) the VDD terminal open state, and for limiting the reverse current Irev to an allowable current value in (2) the reverse connection state.

[0044] First, the aspect ratio of the depletion-mode NMOS transistor 51 is determined using the above-mentioned equations (5) and (6) so that the reverse current Irev and the voltage VN3 (=Ron_dep×Istb) at the node N3 in the standby state have desired values. When determining the aspect ratio of the depletion-mode NMOS transistor 51, if it is desired to reduce the reverse current Irev, the aspect ratio of the depletion-mode NMOS transistor 51 is set to a small value. After the aspect ratio of the depletion-mode NMOS transistor 51 is determined, the aspect ratio and gate voltage Vg of the NMOS transistor 11 are then determined using the above-mentioned equation (3) so that (1) the voltage VN3 at the node N3 in the steady state has a desired value.

[0045] By designing in this manner, the protection circuit and semiconductor device according to this embodiment can bring the internal circuit 6 closer to a grounded state in (1) a steady state, (3) a standby state, and (4) a VDD terminal open state, and can be configured so that the reverse current Irev can be limited to an allowable current value in (2) a reverse connection state.

[0046] As described above, according to the protection circuit 1A and the semiconductor device 10A, the protection circuit 1A is configured to include the current limiting circuit 5A connected in parallel with the NMOS transistor 11, so that even when the NMOS transistor 11 is in an off state, a current path can be secured between the internal circuit 6 and the GND terminal 4. Therefore, a current path can be secured between the internal circuit 6 and the GND terminal 4, and floating of the internal circuit 6 can be prevented.

[0047] Furthermore, since the protection circuit 1A is configured to include the current limiting circuit 5A connected in parallel with the NMOS transistor 11, the protection circuit 1A and the semiconductor device 10A can bring the internal circuit 6 closer to a grounded state in (1) a steady state, (3) a standby state, and (4) a VDD terminal open state, and can limit the reverse current Irev to an allowable current value in (2) a reverse connection state.

[0048] The protection circuit and semiconductor device according to the first embodiment are not limited to the above-described protection circuit 1A and semiconductor device 10A. Next, other configuration examples (modifications) of the protection circuit 1A and the semiconductor device 10A will be described.

[0049] FIG. 3 is a circuit diagram showing a protection circuit 1B and a semiconductor device 10B which are a modification (second configuration example) of the protection circuit and the semiconductor device according to the first embodiment.

[0050] The semiconductor device 10B differs from the semiconductor device 10A in that it includes a protection circuit 1B instead of the protection circuit 1A, but is otherwise substantially the same. The protection circuit 1B differs from the protection circuit 1A in that it includes a current limiting circuit 5B instead of the current limiting circuit 5A, but is otherwise substantially the same. The current limiting circuit 5B differs from the current limiting circuit 5A in that it further includes a resistor 52 connected between the source of the depletion-mode NMOS transistor 51 and the node N3.

[0051] In the current limiting circuit 5B, the depletion-mode NMOS transistor 51 includes a drain connected to the drain of the NMOS transistor 11, a source serving as a second terminal, and a gate serving as a control terminal. The resistor 52 includes a first terminal connected to the source of the depletion-mode NMOS transistor 51, and a second terminal connected to the source of the NMOS transistor 11 and the gate of the depletion-mode NMOS transistor 51. In other words, the resistor 52 electrically connects the source of the depletion-mode NMOS transistor 51 to the source of the NMOS transistor 11 connected to the gate of the depletion-mode NMOS transistor 51.

[0052] According to the protection circuit 1B and the semiconductor device 10B configured in this manner, although the resistance value between both ends of the current limiting circuit 5B, i.e., between the node N2 and the node N3, is different from the resistance value between both ends of the current limiting circuit 5A, the protection circuit 1B and the semiconductor device 10B operate in the same manner as the protection circuit 1A and the semiconductor device 10A.

[0053] In the protection circuit 1B and the semiconductor device 10B, the resistor 52 and the depletion-mode NMOS transistor 51 appear to be connected in series, and so the above-described equations (3) and (6) are obtained by replacing "Ron_dep" in the above-described equations (3) and (6) with "Ron_dep+R52." Here, "R52" is the resistance value of the resistor 52. Also, in the (2) reverse connection state, the voltage drop across the resistor 52 is approximately the absolute value |VTND| of the threshold voltage of the depletion-mode NMOS transistor 51. Therefore, the reverse current Irev is calculated by dividing the absolute value |VTND| of the threshold voltage of the depletion-mode NMOS transistor 51, which corresponds to the voltage drop across the resistor 52, by the resistance value "R52," as shown in the following equation (7): Irev=|VTND| / R52 ---(7)

[0054] According to the protection circuit 1B and the semiconductor device 10B, the protection circuit 1B is configured to include the current limiting circuit 5B connected in parallel with the NMOS transistor 11, so that even when the NMOS transistor 11 is in an off state, a current path can be secured between the internal circuit 6 and the GND terminal 4. Therefore, a current path can be secured between the internal circuit 6 and the GND terminal 4, and floating of the internal circuit 6 can be prevented.

[0055] Furthermore, since the protection circuit 1B is configured to include the current limiting circuit 5B connected in parallel with the NMOS transistor 11, the protection circuit 1A and the semiconductor device 10A can bring the internal circuit 6 closer to the ground state in (1) the steady state, (3) the standby state, and (4) the VDD terminal open state, and can limit the reverse current Irev to an allowable current value in (2) the reverse connection state.

[0056] In the first embodiment, an example of the load 71 that is the constant current source 711 (first configuration example: see FIGS. 2A to 2C) has been described so far, but the load 71 is not limited to the above-mentioned constant current source 711. For example, the load 71 may be configured as shown in FIGS. 4A, 4B, and 4C, which will be described later.

[0057] 4A, 4B, and 4C are circuit diagrams showing a resistor 712, which is a second configuration example of the load 71, a Zener diode 713, which is a third configuration example of the load 71, and a transistor circuit 714, which is a fourth configuration example of the load 71, respectively.

[0058] In this embodiment, the load 71 may be, for example, a resistor 712 (second configuration example: see FIG. 4A), a Zener diode 713 (third configuration example: see FIG. 4B), or a transistor circuit 714 including at least one diode-connected MOS transistor 714_1 (fourth configuration example: see FIG. 4C). Note that the transistor circuit 714 is not limited to including one diode-connected MOS transistor 714_1, and may be configured by connecting a plurality of diode-connected MOS transistors including the MOS transistor 714_1 in series.

[0059] [Second embodiment] 5 and 6 are examples of a semiconductor device according to the second embodiment, and are respectively a circuit diagram showing a semiconductor device 10C including a protection circuit 1A and a circuit diagram showing a semiconductor device 10D including a protection circuit 1B.

[0060] The semiconductor devices 10C and 10D differ from the semiconductor devices 10A (see FIG. 1) and 10B (see FIG. 3) in that they include a protected circuit 2B instead of the protected circuit 2A (see FIGS. 3 and 4), and more specifically, a step-down circuit 9 instead of the source follower 7 as a step-down circuit. However, they are essentially the same in other respects. Therefore, in the description of this embodiment, differences from the above-described embodiments will be mainly described, and redundant description will be omitted. The differences between the semiconductor devices 10C and 10D are essentially the same as the differences between the semiconductor devices 10A and 10B. Therefore, in the description of the semiconductor device 10C described below, the protection circuit 1A, the current limiting circuit 5A, and the semiconductor device 10C will be replaced with the protection circuit 1B, the current limiting circuit 5B, and the semiconductor device 10D, respectively, and description thereof will be omitted.

[0061] The semiconductor device 10C includes a protection circuit 1A and a protected circuit 2B that is an object to be protected by the protection circuit 1A. The protection circuit 1A and the protected circuit 2B are configured as semiconductor integrated circuits.

[0062] The protected circuit 2B includes an internal circuit 6 and a step-down circuit 9 connected in parallel to the internal circuit 6. The protected circuit 2B also includes a first end connected to the node N1 and corresponding to the first end of the semiconductor device 10C, a second end connected to the GND terminal 4 if the protection circuit 1A is not present, and an output end that supplies a gate voltage Vg to the protection circuit 1A.

[0063] The step-down circuit 9 according to the first configuration example includes a current-voltage conversion circuit (hereinafter referred to as "I / V conversion circuit") 90, a constant current source 91, and an output terminal 94. Here, the connection point between the constant current source 91 and the I / V conversion circuit 90 is referred to as node N5.

[0064] The constant current source 91 includes a first terminal connected to the node N1 and a second terminal connected to the node N5, and is configured to be able to supply a constant current I3. The I / V conversion circuit 90 includes a first terminal connected to the node N3 and a second terminal connected to the node N5, and is configured to convert the constant current I3 supplied from the constant current source 91 into a gate voltage Vg and output it to the node N5. The output terminal 94 is connected to the node N5 within the step-down circuit 9. On the other hand, the output terminal 94 is connected to the gate of the NMOS transistor 11 outside the step-down circuit 9.

[0065] Next, a configuration example of the I / V conversion circuit 90 will be described. Figures 7(A), 7(B), and 7(C) are circuit diagrams showing a first configuration example of the I / V conversion circuit 90 having a resistor 901, a second configuration example having a Zener diode 902, and a third configuration example having a transistor circuit 903, respectively.

[0066] The I / V conversion circuit 90 is configured by, for example, a resistor 901 (first configuration example: see FIG. 7(A)), a Zener diode 902 (second configuration example: see FIG. 7(B)), or a transistor circuit 903 (fourth configuration example: see FIG. 7(C)) including at least one diode-connected MOS transistor 903_1. Note that the transistor circuit 903 is not limited to including one diode-connected MOS transistor 903_1, and may be configured by connecting a plurality of diode-connected MOS transistors including the MOS transistor 903_1 in series.

[0067] Next, an example of the configuration of the constant current source 91 will be described. 8(A) and 8(B) are circuit diagrams showing a first configuration example of a constant current source 91 having a depletion-type NMOS transistor 912 with its gate and source connected, and a second configuration example of a constant current source 35 and a current mirror circuit 36, respectively.

[0068] The constant current source 91 has, for example, a depletion-type NMOS transistor 912 as a depletion-type FET whose source and gate are connected, and is configured to pass a constant current I3 through the drain of the depletion-type NMOS transistor 912 (see FIG. 8A).

[0069] The constant current source 91 is configured to include a current mirror circuit 36 configured by connecting two NMOS transistors 361, 362, and a constant current source 35 that flows a constant current I4 to the drain of the NMOS transistor 362. The current mirror circuit 36 is configured by connecting the gate of the NMOS transistor 362 to its own drain and the gate of the NMOS transistor 361. The constant current source 91, which includes the current mirror circuit 36 and the constant current source 35, can pass a constant current I3 (=m2×I4), which is a copy of the constant current I4 flowing to the drain of the NMOS transistor 362 at a predetermined mirror ratio m2 (m2 is an arbitrary positive number), to the drain of the NMOS transistor 361.

[0070] Next, the circuit operations of the protection circuit 1A and the semiconductor device 10C will be explained in order, dividing them into (1) a steady state, (2) a reverse connection state, (3) a standby state, and (4) a VDD terminal open state. Note that in explaining the circuit operations of the semiconductor device 10C, explanations that overlap with those of the semiconductor device 10A will be appropriately simplified or omitted.

[0071] (1) Steady state The current flowing in the internal circuit 6 flows from node N1 to node N3. The constant current I3 of the constant current source 91 is set so that the gate voltage Vg of the NMOS transistor 11 from the step-down circuit 9 is higher than its threshold voltage Vth. The constant current I3 set in this manner is supplied to the I / V conversion circuit 90, thereby generating a gate voltage Vg that easily turns on the NMOS transistor 11 and supplying it to the gate of the NMOS transistor 11. In other respects, the circuit operations are similar to those of the protection circuit 1A and the semiconductor device 10A.

[0072] (2) Reverse connection The reverse current Irev in the protection circuit 1A and the semiconductor device 10C differs from the reverse current Irev in the protection circuit 1A and the semiconductor device 10A in that it is a current that flows to the VDD terminal 3 via the protected circuit 2B (more specifically, the internal circuit 6 or the step-down circuit 9). However, the circuit operation of the protection circuit 1A and the semiconductor device 10C is similar to the circuit operation of the protection circuit 1A and the semiconductor device 10A.

[0073] (3) Standby state The semiconductor device 10C includes a switch (not shown) that cuts off the current flowing through the step-down circuit 9 to transition to a standby state. In the standby state, the switch is turned off to cut off the current flowing through the step-down circuit 9 in order to reduce current consumption. With the current flowing through the step-down circuit 9 cut off, the gate voltage Vg of the NMOS transistor 11 drops below the threshold voltage Vth of the NMOS transistor 11, turning off the NMOS transistor 11. In other respects, the circuit operations are similar to those of the protection circuit 1A and the semiconductor device 10A.

[0074] (4) VDD pin open state In the VDD terminal open state, the circuit operations of the protection circuit 1A and the semiconductor device 10C are the same as those of the protection circuit 1A and the semiconductor device 10A.

[0075] As described above, the protection circuit 1A and the semiconductor device 10C can provide the same effects as the protection circuit 1A and the semiconductor device 10A. That is, the protection circuit 1A and the semiconductor device 10C can ensure a current path between the internal circuit 6 and the GND terminal 4, thereby preventing the internal circuit 6 from floating. Furthermore, the internal circuit 6 can be brought closer to a grounded state in (1) the steady state, (3) the standby state, and (4) the VDD terminal open state, and the reverse current Irev can be limited to an allowable current value in (2) the reverse connection state.

[0076] Furthermore, the protection circuit 1B and the semiconductor device 10D can provide the same effects as the protection circuit 1B and the semiconductor device 10B. That is, the protection circuit 1B and the semiconductor device 10D can ensure a current path between the internal circuit 6 and the GND terminal 4, thereby preventing the internal circuit 6 from floating. Furthermore, the internal circuit 6 can be brought closer to a grounded state in (1) the steady state, (3) the standby state, and (4) the VDD terminal open state, and the reverse current Irev can be limited to an allowable current value in (2) the reverse connection state.

[0077] Although the second embodiment has described an example of the step-down circuit 9 including the constant current source 91 and the I / V conversion circuit 90, the step-down circuit 9 is not limited to this example. For example, the step-down circuit 9 may be configured as shown in FIG. 9, which will be described later.

[0078] FIG. 9 is a circuit diagram showing a resistor 92, which is a part of a second configuration example of a step-down circuit 9 having a resistor 92 and an I / V conversion circuit 90. In FIG.

[0079] The step-down circuit 9 according to the second configuration example differs from the step-down circuit 9 according to the first configuration example in that it has a resistor 92 instead of a constant current source 91, but is otherwise substantially the same. Like the step-down circuit 9 according to the first configuration example, the step-down circuit 9 according to the second configuration example generates a gate voltage Vg from an output terminal 94. The gate voltage Vg is supplied to the protection circuit 1A. The operation of the protection circuit 1A is as described above.

[0080] It should be noted that the present invention is not limited to the above-described embodiments, and can be implemented in various forms other than the above-described examples at the implementation stage, and various omissions, additions, substitutions, or modifications can be made without departing from the spirit of the invention. For example, the above-described protection circuits 1A and 1B are examples in which the source follower 7 or the step-down circuit 9 is not included, but the protection circuits 1A and 1B may be configured to further include the source follower 7 or the step-down circuit 9.

[0081] In the above embodiment, the depletion-type NMOS transistor 70 is used as an example of the step-down transistor, but the step-down transistor is not limited to this. The step-down transistor may be an enhancement-type transistor.

[0082] The semiconductor device according to this embodiment has been described taking as an example the case where the voltage VDD is a positive voltage in a steady state, but the protection circuit and semiconductor device according to this embodiment may be obtained by interchanging the polarity (P-type and N-type) of elements having polarity, such as the depletion-type NMOS transistor 11, and the polarity (positive and negative) of the power supply voltage.

[0083] The MOS transistor of the protection circuit and semiconductor device according to this embodiment is an example of a field-effect transistor (FET), and any type of FET can be used. In other words, in addition to MOSFETs, other field-effect transistors such as junction FETs (JFETs) and metal-insulator-semiconductor FETs (MISFETs) may be appropriately selected.

[0084] These embodiments and their variations are included in the scope and spirit of the invention, and are included in the scope of the invention and its equivalents described in the claims. [Explanation of symbols]

[0085] 10A, 10B, 10C, 10D Semiconductor device 1A,1B protection circuit 2A,2C Protected circuit 3 VDD pin 4 GND terminal 5A,5C current limit circuit 6 Internal circuit 6_1~6_n Parasitic diodes 7 Source follower (step-down circuit) 9. Step-down circuit 11 NMOS transistor (protection transistor) 70 Depletion-type NMOS transistor (step-down transistor) 71 Load 73 (Step-down circuit) control terminal 74,94 (Step-down circuit) output terminal 90 I / V conversion circuit 91 Constant current source 92 Resistance 94 Output terminal P1 current path

Claims

1. a protection transistor including a first end connected to one end of a current path formed by a parasitic diode of a semiconductor element included in the internal circuit, a second end connected to a first power supply terminal, and a control end; a current limiting circuit connected in parallel with the protection transistor; A protection circuit comprising:

2. further comprising a step-down circuit connected in parallel with the internal circuit; the step-down circuit includes a load including a first end connected to one end of the current path and a second end; a step-down transistor including a first end connected to the other end of the current path, a second end connected to a second end of the load, and a control end; a control terminal connected to the control end of the step-down transistor; an output terminal connected to the second end of the load and the second end of the step-down transistor; 2. The protection circuit of claim 1, comprising:

3. The control terminal of the step-down circuit is connected to any one of the nodes included in the internal circuit.

3. The protection circuit of claim 2.

4. further comprising a step-down circuit connected in parallel with the internal circuit; the step-down circuit includes a current-voltage conversion circuit including a first terminal connected to a first terminal of the protection transistor and a second terminal of the internal circuit, and a second terminal; a constant current source including a first terminal connected to a first terminal of the internal circuit and a second terminal connected to a second terminal of the current-voltage conversion circuit; an output terminal connected to a second terminal of the constant current source and a second terminal of the current-voltage conversion circuit; 2. The protection circuit of claim 1, comprising:

5. further comprising a step-down circuit connected in parallel with the internal circuit; the step-down circuit includes a current-voltage conversion circuit including a first terminal connected to a first terminal of the protection transistor and a second terminal of the internal circuit, and a second terminal; a resistor including a first terminal connected to a first terminal of the internal circuit and a second terminal connected to a second terminal of the current-voltage conversion circuit; 2. The protection circuit of claim 1, comprising:

6. The current limiting circuit a depletion-type field-effect transistor including a first terminal connected to the second terminal of the protection transistor, a second terminal connected to the first terminal of the protection transistor, and a control terminal connected to its second terminal; 2. The protection circuit of claim 1, comprising:

7. The current limiting circuit a depletion-type field effect transistor including a first end connected to the second end of the protection transistor, a second end, and a control end; a resistor having a first terminal connected to the second terminal of the depletion-mode field-effect transistor, and a second terminal connected to the first terminal of the protection transistor and the control terminal of the depletion-mode field-effect transistor; 2. The protection circuit of claim 1, comprising:

8. A protection circuit according to any one of claims 1 to 7; a protected circuit having the internal circuit; A semiconductor device comprising:

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