Non-volatile memory cell array formed in p-well in deep n-well in p-substrate

Abstract

To reduce a peak positive voltage that needs to be applied to a cell to erase a memory cell.SOLUTION: A non-volatile memory system 500 includes an array 501, a row decoder 502, and a high voltage decoder 503. The array 501 is formed in a p-well 504 formed in a deep n-well 505, and the deep n-well 505 is formed in a p-substrate 580. Therefore, the p-well 504 is separated from the p-substrate 580 by the deep n-well 505 and thus can receive a negative voltage. In an erase operation, the p-substrate 580 can be biased at 0 V, the deep n-well 505 can be biased at 0 to 2 V, and the p-well 504 can be biased at 0.1 V to 10 V. These bias voltages are generated by a bias generator 409 or another voltage source.SELECTED DRAWING: Figure 5

Description

[Technical Field]

[0001] (Priority Claim) This application claims priority to U.S. Provisional Patent Application No. 63 / 190,200, filed May 18, 2021, entitled "Non-Volatile Memory Cell Array with Substrate Capable of Receiving Negative Voltage During Erase Operations," and U.S. Patent Application No. 17 / 461,981, filed August 30, 2021, entitled "Non-Volatile Memory Cell Array Formed in a P-Well in a Deep N-Well in a P-Substrate," both of which are incorporated herein by reference.

[0002] FIELD OF THE INVENTION Numerous embodiments are disclosed of a non-volatile memory cell array formed in a p-well within a deep n-well within a p-substrate. During an erase operation, a negative voltage is applied to the p-well to reduce the peak positive voltage required to erase the cells in the array. [Background technology]

[0003] Different types of nonvolatile memory are well known. For example, U.S. Pat. No. 5,029,130 (the "'130 patent"), incorporated herein by reference, discloses an array of split-gate nonvolatile memory cells, which are a type of flash memory cell. Such a memory cell 110 is shown in FIG. 1. Each memory cell 110 includes a source region 14 and a drain region 16 formed in a semiconductor substrate 12, with a channel region 18 between the source region 14 and the drain region 16. A floating gate 20 is formed over and insulated from a first portion of the channel region 18 (and controls the conductivity of the first portion of the channel region 18) and over a portion of the source region 14. A word line terminal 22 (typically coupled to a word line) has a first portion disposed over and insulated from a second portion of the channel region 18 (and controls the conductivity of the second portion of the channel region 18), and a second portion extending upward above the floating gate 20. A floating gate 20 and a wordline terminal 22 are insulated from the substrate 12 by a gate oxide. A bitline 24 is coupled to the drain region 16.

[0004] The memory cell 110 is erased (electrons are removed from the floating gate) by applying a high positive voltage (with respect to the substrate 12) to the word line terminal 22, which causes electrons in the floating gate 20 to pass via Fowler-Nordheim (FN) tunneling from the floating gate 20 to the word line terminal 22 through the insulator between them.

[0005] The memory cell 110 is programmed by hot electron source side injection (SSI) (electrons are added to the floating gate) by applying a positive voltage to the word line terminal 22 (with respect to the substrate 12) and a positive voltage to the source region 14. Electrons flow from the drain region 16 toward the source region 14. The electrons accelerate and heat up when they reach the gap between the word line terminal 22 and the floating gate 20. Some of the heated electrons are injected into the floating gate 20 through the gate oxide due to electrostatic attraction from the floating gate 20.

[0006] The memory cell 110 is read by applying a positive read voltage (with respect to the substrate 12) to the drain region 16 and the word line terminal 22 (turning on the portion of the channel region 18 below the word line terminal). When the floating gate 20 is positively charged (i.e., erased with electrons), the portion of the channel region 18 below the floating gate 20 is also turned on, and current flows through the channel region 18, which is sensed as an erased or "1" state. When the floating gate 20 is negatively charged (i.e., programmed with electrons), the portion of the channel region 18 below the floating gate 20 is mostly or completely off, and no (or very little) current flows through the channel region 18, which is sensed as a programmed or "0" state.

[0007] Table 1 shows typical voltage / current ranges that can be applied to the terminals of memory cell 110 to perform read, erase, and program operations. [Table 1]

[0008] The voltages in Table 1 are referenced to the substrate 12, which receives 0V during a read, erase, or program operation.

[0009] Other types of flash memory cells are known, including other split-gate memory cell configurations.

[0010] For example, FIG. 2 shows a four-gate memory cell 210 including a source region 14, a drain region 16, a floating gate 20 above a first portion of a channel region 18, a select gate 22 (typically coupled to a word line, WL) above a second portion of the channel region 18, a control gate 28 above the floating gate 20, and an erase gate 30 above the source region 14. This configuration is described in U.S. Pat. No. 6,747,310, which is incorporated herein by reference for all purposes. Here, all gates, except for the floating gate 20, are non-floating gates, i.e., they are electrically connected or connectable to a voltage source. Programming is performed by heated electrons from the channel region 18 being injected through the gate oxide into the floating gate 20 due to electrostatic attraction from the floating gate 20. Erasing is performed by electrons tunneling from the floating gate 20 to the erase gate 30.

[0011] Table 2 shows typical voltage / current ranges that can be applied to the terminals of memory cell 210 to perform read, erase, and program operations. [Table 2]

[0012] A voltage of 0V is applied to the substrate 12 during a read, erase, or program operation.

[0013] Figure 3 shows another type of flash memory cell, a three-gate memory cell 310. Memory cell 310 is identical to memory cell 210 of Figure 2, except that memory cell 310 does not have a separate control gate. Erase and read operations (erasure occurs through the use of an erase gate) are similar to those of memory cell 210 of Figure 2, except that no control gate bias is applied. Programming operations are also performed without a control gate bias, and as a result, a higher voltage must be applied to the source line during a program operation to compensate for the lack of control gate bias.

[0014] Table 3 shows typical voltage / current ranges that can be applied to the terminals of memory cell 310 to perform read, erase, and program operations. [Table 3]

[0015] A voltage of 0V is applied to the substrate 12 during a read, erase, or program operation.

[0016] Space within a semiconductor die is at a premium. In the prior art systems described above, significant space is required for circuitry external to the array required for read, program, and / or erase operations. For example, the high voltages required for erase operations require special high-voltage generation and regulation circuitry, which in turn require high-voltage transistors that require large areas on the semiconductor die due to thicker gate oxides, longer channel lengths, and wider physical spacing.

[0017] What is needed is a new architecture for arrays of non-volatile memory cells that reduces the voltage required for erase operations and in turn reduces the space required for high voltage generation and regulation circuitry. Summary of the Invention

[0018] Numerous embodiments are disclosed of a non-volatile memory cell array formed in a p-well formed in a deep n-well formed in a p-substrate. During an erase operation, a negative voltage is applied to the p-well to reduce the peak positive voltage that needs to be applied to the cells to erase them.

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[0026] [Brief explanation of the drawings]

[0027] [Figure 1] 1 shows a prior art split-gate flash memory cell. [Figure 2] 1 illustrates another prior art split-gate flash memory cell. [Figure 3] 1 illustrates another prior art split-gate flash memory cell. [Figure 4] 1 illustrates a non-volatile memory system. [Figure 5] 1 shows a non-volatile memory system with a p-well surrounding the array. [Figure 6] 1 illustrates a non-volatile memory system with multiple p-wells surrounding an array, a low voltage decoder circuit, and a high voltage decoder circuit. [Figure 7] 1 illustrates a non-volatile memory system comprising a first array, a second array, a low voltage decoder circuit, and a plurality of p-wells surrounding a high voltage decoder circuit. [Figure 8]1 illustrates a non-volatile memory system comprising a first array, a second array, a first low voltage decoder circuit, a second low voltage decoder circuit, a first high voltage decoder circuit, and a plurality of p-wells surrounding the second high voltage decoder circuit. [Figure 9] 1 shows a cross section of a non-volatile memory system with a p-well surrounding the array. DETAILED DESCRIPTION OF THE INVENTION

[0028] The embodiments described herein allow a negative voltage to be applied to the p-well surrounding certain components to allow lower voltages to be used during erase operations of non-volatile memory cells.

[0029] 4 shows a block diagram of a non-volatile memory system 400. The non-volatile memory system 400 includes an array 401, a row decoder 402, a high-voltage decoder 403, a column decoder 404, a bit line driver (also known as a column driver) 405 (for controlling program (current) on the bit line terminals), an output circuit 407, control logic 408, and a bias generator 409. The non-volatile memory system 400 further includes a high-voltage generation block 410, which includes a charge pump 411, a charge pump regulator 412, and a high-voltage level generator 413. The non-volatile memory system 400 further includes a (program / erase or weight adjustment) algorithm controller 414, analog circuitry 415, a control engine 416 (which may include, but is not limited to, specialized functions such as arithmetic functions, startup functions, or embedded microcontroller logic), and test control logic 417.

[0030] The output circuit 407 may include circuits such as digital sensing circuits for converting cell currents into logic "1" or "0" or analog sensing circuits such as ADCs (analog-to-digital converters), AACs (analog-to-analog converters) such as current-to-voltage converters, logarithmic converters, APCs (analog-to-pulse converters), analog-to-time modulated pulse converters, or any other type of converters for converting neuron analog outputs into digital bits. The output circuit 407 may perform activation functions such as a rectified linear activation function (ReLU) or a sigmoid. The output circuit 407 may perform statistical normalization, regularization, up / down scaling / gain functions, statistical rounding, or arithmetic functions (e.g., addition, subtraction, division, multiplication, shift, log) of the neuron outputs. The output circuit 407 may perform temperature compensation functions for the bit line outputs.

[0031] 5-9, the array, and optionally other components, are surrounded by a deep n-well and disposed in a p-well on top of the deep n-well. A negative voltage is then applied to the p-well relative to the p-substrate by bias generator 409 or another voltage source during certain operations, such as erase operations of the non-volatile memory cells. This reduces the maximum voltage required for the erase operation, thereby reducing the overall size and power of high voltage generation block 410.

[0032] FIG. 5 shows a plan view of a nonvolatile memory system 500. The nonvolatile memory system 500 includes an array 501, a row decoder 502 (an example of the row decoder 402 of FIG. 4), and a high-voltage decoder 503 (an example of the high-voltage decoder 403 of FIG. 4). The array 501 is formed in a p-well 504 formed in a deep n-well 505, which is formed in a p-substrate 580. Thus, the p-well 504 is separated from the p-substrate 580 by the deep n-well 505 and can receive different voltages (including, but not limited to, negative voltages). For example, the p-substrate 580 can be biased at 0V, the deep n-well 505 can be biased between 0 and 2V, and the p-well 504 can be biased between −0.1V and −10V. These bias voltages can be generated by the bias generator 409 or another voltage source.

[0033] 6 shows a non-volatile memory system 600. The non-volatile memory system 600 includes an array 601, a row decoder 602 (an example of the row decoder 402 in FIG. 4), and a high-voltage decoder 603 (an example of the high-voltage decoder 403 in FIG. 4).

[0034] The array 601 is formed in a p-well 604 , which is formed in a deep n-well 605 .

[0035] The row decoder 602 is formed in a p-well 608 , which is formed in a deep n-well 609 .

[0036] The high voltage decoder 603 is formed in a p-well 606 which is formed in a deep n-well 607 .

[0037] Deep n-wells 605, 607, and 609 are each formed in (and on top of) p-substrate 680. Optionally, deep n-wells 605, 607, and 609 can be separate deep n-wells or part of a common deep n-well.

[0038] Thus, the p-well 604 containing the array 601 is separated from the p-substrate 680 by the deep n-well 605 and can be driven at a negative voltage with respect to the p-substrate 680 by the bias generator 409 or another voltage source.

[0039] Thus, the p-well 606 containing the high voltage decoder 603 is separated from the p-substrate 680 by the deep n-well 607 and can be driven at a negative voltage with respect to the p-substrate 680 by the bias generator 409 or another voltage source.

[0040] For example, p-substrate 680 may be biased at 0 V, deep n-wells 605, 607, and 609 may be biased at 0 to 3 V, and p-wells 604, 606, and 608 may be biased at −0.1 V to −10 V. These bias voltages may be generated by bias generator 409 or another voltage source.

[0041] 7 shows a non-volatile memory system 700. The non-volatile memory system 700 includes an array 701, an array 702, a low-voltage decoder 703, and a high-voltage decoder 704. The array 701 is formed in a p-well 705, which is formed in a deep n-well 706. The array 702 is formed in a p-well 707, which is formed in a deep n-well 708. The low-voltage decoder 703 is formed in a p-well 709, which is formed in a deep n-well 710. The high-voltage decoder 704 is formed in a p-well 711, which is formed in a deep n-well 712. Optionally, the deep n-wells 706, 708, 710, and 712 can be separate deep n-wells or can be part of a common deep n-well. The p-substrate PSUB 780 is the substrate on which all the circuits, ie, array 701, array 702, low voltage decoder 703, and high voltage decoder 704 are formed.

[0042] 8 shows a non-volatile memory system 800. The non-volatile memory system 800 includes an array 801, an array 802, a low-voltage decoder 803, a low-voltage decoder 804, a high-voltage decoder 805, and a high-voltage decoder 806. The array 801 is formed in a p-well 807, which is formed in a deep n-well 808. The array 802 is formed in a p-well 809, which is also formed in a deep n-well 808. The low-voltage decoder 803 is formed in a p-well 810, which is formed in a deep n-well 811. The low-voltage decoder 804 is formed in a p-well 812, which is formed in a deep n-well 813. The high-voltage decoder 805 is formed in a p-well 814, which is formed in a deep n-well 815. High-voltage decoder 806 is formed in p-well 816, which is formed in deep n-well 817. Optionally, deep n-wells 808, 811, 815, 813, and 817 can be separate deep n-wells or part of a common deep n-well. P-substrate 880 is the substrate on which all circuitry, i.e., array 801, array 802, low-voltage decoder 803, low-voltage decoder 804, high-voltage decoder 805, and high-voltage decoder 806, is formed.

[0043] Thus, p-wells 807 or 809 can be independently driven to negative voltages with respect to p-substrate 880 by bias generator 409 or another voltage source because they are separated from p-substrate 880 by deep n-well 808. Similarly, p-wells 810, 812, 814, 816 can be independently driven to negative voltages with respect to p-substrate 880 by bias generator 409 or another voltage source because they are separated from p-substrate 880 by respective deep n-wells 811, 813, 815, and 817.

[0044] FIG. 9 shows a cross section 900. An array 901 or low-voltage decoder, a row decoder 902, or a high-voltage decoder 903 (which respectively represent the array, row decoder, and high-voltage decoder shown in FIGS. 5-8 ) is formed in a p-well 904, which is formed in a deep n-well 905, which is formed in a p-substrate 980. A p-well terminal 906 provides access to the p-well 904 and may be used to apply a negative voltage (relative to the p-substrate 980) to the p-well 904 by, for example, a bias generator 409 or another voltage source during an erase operation. An n-well terminal 907 is used to apply a bias voltage to the deep n-well 905, and a p-substrate terminal 908 is used to apply a bias voltage (which may include 0V) to the p-substrate 980. The p-substrate 980 is the substrate on which all circuitry, i.e., the array 901 or low-voltage decoder, a row decoder 902, or a high-voltage decoder 903, is formed.

[0045] Optionally, the p-substrate 980 of FIGS. 5-9 can be biased by bias generator 409 or another voltage source at a negative voltage, such as −0.1V to −3V, instead of 0V.

[0046] 5-9 , the following operating voltages may be used to perform read, program, and erase operations on the nonvolatile memory cells 110, 210, and 310 of FIGS. 1-3 , with it being understood that substrate 12 of FIGS. 1-3 (which is a p-substrate) is modified to include a p-well within a deep n-well, as shown in cross section 900 of FIG. 9 , so that substrate 12 then becomes a p-substrate 980, a deep n-well 905 is formed in substrate 12, a p-well 904 is formed in deep n-well 905, and an array of memory cells 110, 210, and 310 is formed in p-well 904. Further, as shown in FIG. 9 , p-well 904 is accessed using p-well terminal 906, deep n-well 905 is accessed using n-well terminal 907, and p-substrate 980 is accessed using p-substrate 980. In this configuration, p-well 904 serves as a (virtual) p-substrate for the memory cells and other components of the array.

[0047] Tables 4-10 below include exemplary operating voltages applied to memory cells 110, 210, and 310 when configured as in Figure 9. In these examples, bias generator 409 or another voltage source applies a voltage of 0V to p-substrate 980 (substrate 12) via p-substrate terminal 908, a voltage of 0 to 2V to deep n-well 905 via n-well terminal 907, and a voltage of -0.1V to -12V to p-well 904 via p-well terminal 906.

[0048] Table 4 shows a first set of operating voltages (defined with respect to substrate 12) for memory cell 110 of FIG. 1 when substrate 12 is modified to include a p-well 904 within a deep n-well 905 within substrate 12. [Table 4]

[0049] Table 5 shows a second set of operating voltages for memory cell 110 of FIG. 1 when the substrate includes a p-well within a deep n-well. [Table 5]

[0050] The p-well 904 is particularly advantageous in situations where a negative voltage is applied to one or more terminals of the cell during an erase operation because in that situation, applying a negative voltage to the p-well 904 using the bias generator 409 or another voltage source reduces stress on the gate oxide region when a negative voltage is applied to the terminals because the p-well 904 acts as a virtual substrate for the cell that is biased to a negative voltage.

[0051] Table 4 is appropriate when stress on the gate oxide region is not an issue, while Table 5 is appropriate when stress on the gate oxide region is an issue. In Table 4, a word line voltage of 0V is applied to unselected cells during an erase operation, while in Table 5, a word line voltage of −2.5V is applied to unselected cells during an erase operation due to the fact that it is desirable to reduce stress on the gate oxide region of memory cell 110 as well as the peripheral (decoding) transistors for the 2.5V gate oxide. In the operation of Table 4, stress on the gate oxide region of the decoding circuit is not an issue because the absolute voltage required does not cause the voltage across the gate oxide region to exceed the gate oxide breakdown voltage of both the decoding circuit and the cell, and as a result, an isolated p-subwell 904 is not needed for the decoding circuit. In contrast, in the embodiment of Table 5, bias generator 409 or another voltage source applies a negative voltage to a particular terminal to reduce stress on the gate oxide region, and as a result, an isolated p-subwell 904 is beneficial to the decoding circuit.

[0052] Table 6 shows a first set of operating voltages for memory cell 210 of FIG. 2 when the substrate includes a p-well within a deep n-well. [Table 6]

[0053] Table 7 shows a second set of operating voltages for memory cell 210 of FIG. 2 when the substrate includes a p-well within a deep n-well. [Table 7]

[0054] Table 8 shows a first set of operating voltages for memory cell 310 of FIG. 3 when the substrate includes a p-well within a deep n-well. [Table 8]

[0055] For the same reasons as discussed above with respect to Tables 5 and 6, the use of p-well 904 is particularly advantageous for Table 8, and even more so than for Table 7.

[0056] Table 9 shows a second set of operating voltages for memory cell 310 of FIG. 3 when the substrate includes a p-well within a deep n-well. [Table 9] [Table 10]

[0057] For the same reasons as discussed above with respect to Tables 5 and 6, the use of p-well 904 is particularly advantageous for Table 10, and even more so than for Table 9.

[0058] It should be noted that, as used herein, both the terms "over" and "on" are inclusive of "directly" (with no intermediate material, element, or gap disposed therebetween) and "indirectly" (with an intermediate material, element, or gap disposed therebetween). Similarly, the term "adjacent" includes "directly adjacent" (with no intermediate material, element, or gap disposed therebetween) and "indirectly adjacent" (with an intermediate material, element, or gap disposed therebetween); "attached" includes "directly attached" (with no intermediate material, element, or gap disposed therebetween) and "indirectly attached" (with an intermediate material, element, or gap disposed therebetween); and "electrically coupled" includes "directly electrically coupled" (with no intermediate material or element disposed therebetween that electrically connects the elements together) and "indirectly electrically coupled" (with an intermediate material or element disposed therebetween that electrically connects the elements together). For example, forming an element "over a substrate" can include forming the element directly on the substrate with no intermediate materials / elements therebetween, and forming the element indirectly on the substrate with one or more intermediate materials / elements therebetween.

Claims

1. 1. A non-volatile memory system, comprising: a deep n-well formed in the semiconductor die; a p-well formed within the deep n-well; an array of non-volatile memory cells formed in the p-well, each non-volatile memory cell including a floating gate and a plurality of terminals; a bias generator for applying a negative voltage to the p-well during an erase operation of one or more of the plurality of non-volatile memory cells.

2. 2. The non-volatile memory system of claim 1, wherein the plurality of terminals of each non-volatile memory cell includes a bit line terminal, a source line terminal, and a word line terminal.

3. 3. The non-volatile memory system of claim 2, wherein the plurality of terminals of each non-volatile memory cell further includes an erase gate terminal.

4. 4. The non-volatile memory system of claim 3, wherein the plurality of terminals of each non-volatile memory cell further includes a control gate terminal.

5. 5. The non-volatile memory system of claim 4, wherein the bias generator applies a negative voltage to control gate terminals of selected memory cells during an erase operation.

6. a row decoder circuit; 10. The non-volatile memory system of claim 1 further comprising: a high voltage decoder circuit.

7. 7. The non-volatile memory system of claim 6, wherein said row decoder circuitry is formed in said p-well.

8. 8. The non-volatile memory system of claim 7, wherein said high voltage decoder circuitry is formed in said p-well.

9. 7. The non-volatile memory system of claim 6, wherein said row decoder circuitry is formed in a second p-well, said second p-well being formed in said deep n-well.

10. The non-volatile memory system of claim 9 , wherein the deep n-well is formed in a p-substrate.

11. 10. The non-volatile memory system of claim 9, wherein said high voltage decoder circuitry is formed in a third p-well, said third p-well being formed in said deep n-well.

12. The non-volatile memory system of claim 11 , wherein the deep n-well is formed in a p-substrate.

13. 7. The non-volatile memory system of claim 6, wherein the low voltage decoder circuitry is formed in a second p-well, said second p-well being formed in a second deep n-well.

14. 14. The non-volatile memory system of claim 13, wherein the second deep n-well is formed in a p-substrate.

15. 14. The non-volatile memory system of claim 13, wherein said high voltage decoder circuitry is formed in a third p-well, said third p-well being formed in a third deep n-well.

16. 16. The non-volatile memory system of claim 15, wherein the third deep n-well is formed in a p-substrate.

17. 10. The non-volatile memory system of claim 1, wherein the bias generator applies a voltage of 0V to word lines of unselected non-volatile memory cells during read, erase, and programming operations.

18. 10. The nonvolatile memory system of claim 1, wherein the bias applies a voltage to the word lines of unselected nonvolatile memory cells, the voltage being selected to reduce stress across the gate oxide of the cells during read, erase, and programming operations.

19. 1. A non-volatile memory system, comprising: a deep n-well formed in the semiconductor die; a first p-well formed within the deep n-well; a second p-well formed within the deep n-well; an array of first non-volatile memory cells formed in the first p-well, each non-volatile memory cell in the first array including a floating gate and a plurality of terminals; an array of second non-volatile memory cells formed in the second p-well, each non-volatile memory cell in the second array including a floating gate and a plurality of terminals; a bias generator for applying a negative voltage to the first p-well during an erase operation of one or more of the plurality of non-volatile memory cells in the first array, and for applying a negative voltage to the second p-well during an erase operation of one or more of the plurality of non-volatile memory cells in the second array.

20. 20. The nonvolatile memory system of claim 19, wherein the plurality of terminals of each nonvolatile memory cell in the first array and the second array include a bit line terminal, a source line terminal, and a word line terminal.

21. 21. The non-volatile memory system of claim 20, wherein the plurality of terminals of each non-volatile memory cell in the first array and the second array further includes an erase gate terminal.

22. 22. The non-volatile memory system of claim 21, wherein the plurality of terminals of each non-volatile memory cell in the first array and the second array further includes a control gate terminal.

23. a row decoder circuit; 20. The non-volatile memory system of claim 19, further comprising: a high voltage decoder circuit.

24. 24. The non-volatile memory system of claim 23 wherein said row decoder circuitry is formed in a third p-well formed in said deep n-well.

25. 24. The non-volatile memory system of claim 23 wherein the row decoder circuitry is formed in a third p-well formed in a second deep n-well.

26. 26. The non-volatile memory system of claim 25, wherein said high voltage decoder circuitry is formed in a formed fourth p-well, said fourth p-well being formed in a second deep n-well.

27. 20. The non-volatile memory system of claim 19, wherein the bias generator applies a voltage of 0V to word lines of unselected non-volatile memory cells during read, erase, and programming operations.

28. 20. The nonvolatile memory system of claim 19, wherein the bias generator applies voltages to word lines of unselected nonvolatile memory cells, the voltages being selected to reduce stress across gate oxides of the cells during read, erase, and programming operations.

29. 20. The non-volatile memory system of claim 19, wherein the bias generator applies a negative voltage to control gate terminals of selected memory cells during an erase operation.

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