Semiconductor device

Abstract

To provide a semiconductor device in which the influence of variation in threshold voltage of a transistor is relieved to make it accurate and easy to distinguish a plurality of states, and a manufacturing method and a driving method for the semiconductor device.SOLUTION: A semiconductor device includes a source line SL, a bit line BL, a word line WL, a memory cell 200 connected to the bit line and the word line, a driving circuit for a plurality of second signal lines S2 and the word lines that drives the second signal lines and the word lines so as to select a memory cell designated by an input address signal, a writing circuit that outputs a writing potential to a first signal line S1, a readout circuit that compares a potential of the bit line input from the bit line connected to the designated memory cell and a plurality of readout potentials, a control circuit that selects any of a plurality of correction voltages on the basis of the result of comparing the potential of the bit line and the readout potentials, and a potential generation circuit that generates a writing potential and a plurality of readout potentials and supplies the potentials to the writing circuit and the readout circuit.SELECTED DRAWING: Figure 14

Description

[Technical Field]

[0001] The disclosed invention relates to a semiconductor device using a semiconductor element, a manufacturing method thereof, and a driving method thereof. It is related to. [Background technology]

[0002] Memory devices that use semiconductor elements are volatile memory devices that lose their contents when the power supply is cut off. and non-volatile memory devices, which retain their contents even when the power supply is cut off. can be.

[0003] A typical example of a volatile memory device is a DRAM (Dynamic Random Access Memory). DRAM is a memory element that can be selected from transistors. By storing charge in the capacitor, information is stored.

[0004] Based on the above principle, in DRAM, when information is read, the charge in the capacitor is lost. Therefore, every time data is read, a write operation is required again. The transistors that make up the transistors have leakage current, and when the transistors are not selected, Therefore, the data retention period is short. A write operation (refresh operation) is required, and power consumption must be reduced sufficiently. Furthermore, if the power supply is cut off, the memory contents are lost, making it difficult to store long-term memories. To store the data, a separate storage device using magnetic or optical materials is required.

[0005] Another example of a volatile memory device is SRAM (Static Random Access Memory). SRAM uses circuits such as flip-flops to store the memory contents. In order to retain data, no refresh operation is required, which is an advantage over DRAM. However, because it uses circuits such as flip-flops, the cost per unit of memory capacity is high. In addition, there is a problem that the memory contents are lost when the power supply is cut off. In this regard, there is no difference with DRAM.

[0006] A typical example of a nonvolatile memory device is flash memory. A floating gate is provided between the gate electrode of the transistor and the channel forming region, Since memory is stored by holding an electric charge in the floating gate, the data retention period is extremely long. The advantage is that it lasts for a very long time (semi-permanent) and does not require the refresh operations required for volatile storage devices. The point is as follows (see, for example, Patent Document 1).

[0007] However, the gate insulating layer that constitutes the memory element is damaged by the tunnel current that occurs during writing. This causes a problem in that the memory element will stop functioning after a certain number of writes. To mitigate the effect of this problem, for example, the number of writes to each storage element is made uniform. However, to achieve this, complex peripheral circuits are required. However, even if such a method is adopted, the fundamental problem of lifespan will not be resolved. Therefore, flash memory is not suitable for applications where information needs to be rewritten frequently.

[0008] Also, to hold charge on the floating gate or to remove that charge. High voltages are required for this. Furthermore, it takes a relatively long time for the charge to be retained or removed. There is also the problem that it takes time to write and erase data, and it is not easy to speed up the writing and erasing.

[0009] Furthermore, in a so-called multi-value memory, which stores multiple states in one memory element, To ensure accuracy, complex circuits are required, which slows down the operation speed. There is also the problem of... [Prior art documents] [Patent documents]

[0010] [Patent Document 1] Japanese Patent Publication No. 57-105889 Summary of the Invention [Problem to be solved by the invention]

[0011] In view of the above-mentioned problems, one embodiment of the disclosed invention provides a method for storing stored contents even when power is not supplied. To provide a semiconductor device having a new structure that can retain data and has no limit on the number of times it can be written. This is one of the purposes of the organization.

[0012] Alternatively, the influence of variations in the threshold voltage of a transistor can be mitigated, and multiple states (e.g., One of the objects of the present invention is to provide a semiconductor device that can accurately and easily distinguish between three or more states. do. [Means for solving the problem]

[0013] One embodiment of the present invention is a transistor formed using an oxide semiconductor and a transistor formed using other materials. The semiconductor device has a stacked structure with a transistor formed using the same.

[0014] Alternatively, one embodiment of the present invention may perform correction based on a comparison result between the potential of the bit line and the read potential. By having a circuit for selecting the voltage, it is possible to distinguish between multiple states (e.g., three or more states). This is a semiconductor device that is both accurate and easy to manufacture.

[0015] For example, the following configuration can be adopted.

[0016] One aspect of the present invention is a transistor including a source line, a bit line, a word line, and a transistor connected to the bit line and the word line. The memory cell designated by the input address signal is selected. The second signal lines and the word lines are driven by the second signal lines and the word lines. a drive circuit, a write circuit that outputs a write potential to a first signal line, and a designated memory The potential of the bit line input from the bit line connected to the cell is compared with a plurality of read potentials. and a read circuit for comparing the potential of the bit line with the plurality of read potentials. a control circuit for selecting one of the correction voltages; and a control circuit for generating a write potential and a plurality of read potentials. a potential generating circuit for generating a potential and supplying the potential to the write circuit and the read circuit. It is a device.

[0017] Another aspect of the present invention is a semiconductor device including a source line, a bit line, a word line, and a transistor connected to the bit line and the word line. The memory cell connected to the address signal and the memory cell specified by the input address signal are selected. a plurality of second signal lines and a plurality of word lines are driven so as to a driver circuit for a first signal line, and a driver circuit for outputting a first write potential to the first signal line in a first write operation; In the second write operation, one of the plurality of second write potentials is applied to the first signal line. A write circuit that outputs a signal and a write circuit that outputs a signal connected to a specified memory cell in a first read operation. The potential of the first bit line input from the selected bit line is compared with a plurality of first read potentials. In comparison, in the second read operation, the input is taken from the bit line connected to the specified memory cell. The potential of the second bit line is compared with a plurality of second read potentials to determine the potential of the memory cell. a read circuit for reading data from the first bit line; a potential of the first read One of the plurality of correction voltages is selected based on the result of the comparison of the potentials, and a plurality of second write voltages are selected. a control circuit for selecting one of the first write potential, a plurality of second write potentials, A plurality of first read potentials and a plurality of second read potentials are generated to be read by a write circuit and and a potential generating circuit that supplies a potential to the read circuit.

[0018] Another aspect of the present invention is a semiconductor memory device including a source line, a bit line, a first signal line, and a plurality of second signal lines; a plurality of word lines, a plurality of memory cells connected in parallel between a source line and a bit line; , a plurality of second memory cells are selected so as to select memory cells designated by the input address signal. a second signal line and word line drive circuit for driving the signal line and the plurality of word lines; a write circuit that outputs a write potential to a first signal line; A read circuit that compares the potential of the bit line input from the bit line with a plurality of read potentials. and selecting one of a plurality of correction voltages based on a comparison result between the potential of the bit line and a plurality of read potentials. a control circuit for selecting one of the write potentials and a plurality of read potentials; a potential generating circuit for supplying a potential to the read circuit and the read circuit, and one of the plurality of memory cells a first transistor having a first gate electrode, a first source electrode, and a first drain electrode; a second gate electrode, a second source electrode, and a second drain electrode; a second transistor having a third gate electrode, a third source electrode, and a third drain electrode; a third transistor having a polarity, the first transistor being formed on a substrate including a semiconductor material; The second transistor is provided on the first gate electrode and includes an oxide semiconductor layer. The source electrode and one of the second source electrode and the second drain electrode are electrically connected to each other. The first source electrode is electrically connected to the first drain electrode, and the third source electrode is electrically connected to the first drain electrode. The bit line and the third drain electrode are electrically connected. The first signal line is electrically connected to the other of the second source electrode and the second drain electrode. One of the plurality of second signal lines is electrically connected to the second gate electrode. The semiconductor device is one in which one of the gate lines and the third gate electrode are electrically connected.

[0019] Another aspect of the present invention is a semiconductor memory device including a source line, a bit line, a first signal line, and a plurality of second signal lines; a plurality of word lines, a plurality of memory cells connected in parallel between a source line and a bit line; , a plurality of second memory cells are selected so as to select memory cells designated by the input address signal. a second signal line and word line driver circuit for driving the signal line and the plurality of word lines; In the write operation, a first write potential is output to the first signal line, and in the second write operation, a write circuit that outputs one of a plurality of second write potentials to a first signal line; In the first read operation, an input is received from a bit line connected to a specified memory cell. The potential of the first bit line is compared with a plurality of first read potentials, and a second read In operation, a second bit is input from a bit line connected to a specified memory cell. comparing the potential of the line with a plurality of second read potentials to read data from the memory cell; A read circuit and a read operation based on a comparison result between the potential of the first bit line and the plurality of first read potentials. and selecting one of a plurality of second write potentials. a control circuit for controlling a first write potential, a plurality of second write potentials, and a plurality of first read potentials; and generating a plurality of second read potentials to be supplied to the write circuit and the read circuit. and a potential generating circuit for supplying a voltage to the memory cells. a first transistor having a first source electrode and a first drain electrode; a second transistor having a second source electrode and a second drain electrode; and a third a third transistor having a gate electrode, a third source electrode, and a third drain electrode; and a first transistor provided on a substrate including a semiconductor material, and a second transistor The gate electrode is formed of an oxide semiconductor layer and has a first gate electrode and a second source electrode. The source line is electrically connected to one of the second drain electrodes, and the first source electrode is electrically connected to the source line. , electrically connected, and the first drain electrode and the third source electrode are electrically connected. The bit line and the third drain electrode are electrically connected, and the first signal line and the second source electrode are electrically connected. The second signal line is electrically connected to the other of the source electrode and the second drain electrode. The second gate electrode is electrically connected to one of the plurality of word lines. A pole is an electrically connected semiconductor device.

[0020] In the above, the first transistor is a channel-forming transistor provided in a substrate including a semiconductor material. a region, impurity regions provided so as to sandwich the channel forming region, and a region on the channel forming region a first gate insulating layer; a first gate electrode on the first gate insulating layer; and an impurity region and an electric and a first source electrode and a first drain electrode electrically connected to the first source electrode.

[0021] In the above, the second transistor has a second gate electrode on a substrate including a semiconductor material. a second gate insulating layer on the second gate electrode; and an oxide semiconductor layer on the second gate insulating layer. a second source electrode and a second drain electrode electrically connected to the oxide semiconductor layer; and,

[0022] In the above, the substrate containing a semiconductor material may be a single crystal semiconductor substrate or an SOI substrate. It is preferable to use a plate, and it is particularly preferable that the semiconductor material is silicon.

[0023] In the above, the oxide semiconductor layer is made of an In-Ga-Zn-O based oxide semiconductor material. The oxide semiconductor layer preferably contains In2Ga2ZnO7 crystals. Furthermore, the hydrogen concentration in the oxide semiconductor layer may be 5×10 19 atoms / cm 3 The off-state current of the second transistor is preferably 1×10 or less. -13 It is preferable to set it to A or less.

[0024] Another aspect of the present invention is a semiconductor memory device including a source line, a bit line, a word line, a first signal line, and a second signal line. 2 signal line and the first signal line to select the memory cell designated by the input address signal. a second signal line and word line drive circuit for driving the second signal line and word line; a read circuit, a control circuit, a potential generating circuit, a source line, a bit line, a word line, a memory cell connected to a first signal line and a second signal line, In the first write operation, a write potential is applied from the write circuit to a designated memory cell. In the first read operation, the read circuit outputs the specified signal to the first signal line connected to the a potential of a first bit line input from a bit line connected to a plurality of memory cells; and a control circuit that selects one of a plurality of correction voltages based on the comparison result. and in the second write operation, a write potential corrected based on the correction voltage is selected. to a first signal line connected to a specified memory cell. do.

[0025] Another aspect of the present invention is a semiconductor memory device including a source line, a bit line, a word line, a first signal line, and a second signal line. line and a second signal to select a memory cell designated by the input address signal. a second signal line and word line driver circuit for driving the signal line and the word line; and a write circuit; A read circuit, a control circuit, a potential generating circuit, a source line, a bit line, a word line, a first signal line, a memory cell connected to a first signal line and a second signal line, In a write operation, a write potential is applied from the write circuit to the specified memory cell. In the first read operation, the read circuit outputs the specified first signal line. A potential of a first bit line input from a bit line connected to a memory cell and a potential of a plurality of first The control circuit compares the read potential with the voltage of the voltage read from the capacitor, and selects one of a plurality of correction voltages based on the comparison result. In the second write operation, a write potential corrected based on the correction voltage is selected. In the second read operation, the read signal is output to a first signal line connected to the memory cell. The second bit input from the bit line connected to the specified memory cell in the read circuit A semiconductor device that compares the potential of the line with a plurality of second read potentials to read data from the memory cell. A method for driving a semiconductor device.

[0026] In this specification, the terms "above" and "below" refer to the positional relationship of the components "directly above" and "below." For example, the term "the first layer on the gate insulating layer" is not limited to "directly under" the first layer. The expression "gate electrode" means that other components are included between the gate insulating layer and the gate electrode. In addition, the terms "upper" and "lower" are merely expressions used for the convenience of explanation. Unless otherwise specified, the terms "top" and "bottom" are interchangeable.

[0027] In addition, in this specification, the terms "electrode" and "wiring" are used to refer to these components functionally. For example, an "electrode" may be used as part of a "wiring." Furthermore, the terms "electrode" and "wire" are used interchangeably to refer to the plural "electrodes." This also includes cases where "wires" and "circuits" are formed integrally.

[0028] Also, the functions of "source" and "drain" may differ depending on whether transistors with different polarities are used or not. However, they may be swapped when the direction of current changes during circuit operation. In this specification, the terms "source" and "drain" are used interchangeably. It is assumed that this is possible.

[0029] In this specification, "electrically connected" means "something that has some kind of electrical effect." This includes cases where the device is connected via a " is not subject to any particular restrictions as long as it enables the transmission and reception of electrical signals between connected objects.

[0030] For example, "something that has some kind of electrical effect" includes not only electrodes and wiring, but also transistors. Switching elements such as transistors, resistive elements, inductors, capacitors, and other various devices This includes elements that have functions such as:

[0031] Generally, an "SOI substrate" is a substrate with a silicon semiconductor layer on an insulating surface. However, in this specification and the like, a semiconductor layer made of a material other than silicon is provided on an insulating surface. In other words, the semiconductor that "SOI substrate" has is used as a concept that includes the substrate with the structure. The layer is not limited to a silicon semiconductor layer. Not only semiconductor substrates such as silicon wafers, but also glass substrates, quartz substrates, sapphire substrates, and metal substrates In other words, it also includes non-semiconductor substrates such as a conductive substrate with an insulating surface or a semiconductor on an insulator plate. The term "SOI substrate" broadly includes those having a layer made of a material. In this context, the term "semiconductor substrate" does not only refer to a substrate made of semiconductor material alone, but also refers to a substrate made of semiconductor material. In other words, in this specification, the term "SOI substrate" is also used broadly. Included in "semiconductor substrate." [Effects of the Invention]

[0032] In one embodiment of the present invention, a transistor including a material other than an oxide semiconductor is provided in a lower portion, and A semiconductor device including a transistor including an oxide semiconductor is provided.

[0033] Since a transistor using an oxide semiconductor has an extremely small off-state current, It is possible to retain the memory contents for a much longer period of time. This eliminates the need for refresh operations or makes it possible to reduce the frequency of refresh operations to an extremely low level. Therefore, power consumption can be reduced sufficiently. , it is possible to retain the stored contents for a long period of time.

[0034] Furthermore, no high voltage is required to write information, and there is no problem of element degradation. Information is written depending on the on / off state of the transistor, allowing for high-speed operation. This can be easily achieved. Another advantage is that no action is required to erase the information. .

[0035] In addition, transistors using materials other than oxide semiconductors are called transistors using oxide semiconductors. Compared to conventional memory controllers, it is possible to operate at higher speeds, so by using this, it is possible to read and write the stored contents. It is possible to perform reading at high speed.

[0036] Alternatively, in one embodiment of the present invention, the potential of the bit line is compensated based on a comparison result between the potential of the bit line and the read potential. By selecting a positive voltage, multiple states (e.g., three or more states) can be distinguished accurately and This makes it possible to provide a multi-value semiconductor device with excellent characteristics. can.

[0037] In this way, transistors using materials other than oxide semiconductors and transistors using oxide semiconductors By integrating the transistor, the potential of the bit line and the read potential are compared. By having a circuit for selecting a correction voltage based on A conductor device can be realized. [Brief explanation of the drawings]

[0038] [Figure 1]FIG. 1 is a circuit diagram illustrating a semiconductor device. [Figure 2] 1A and 1B are a cross-sectional view and a plan view illustrating a semiconductor device. [Figure 3] 1A to 1C are cross-sectional views illustrating a manufacturing process of a semiconductor device. [Figure 4] 1A to 1C are cross-sectional views illustrating a manufacturing process of a semiconductor device. [Figure 5] 1A to 1C are cross-sectional views illustrating a manufacturing process of a semiconductor device. [Figure 6] FIG. 10 is a cross-sectional view of a transistor including an oxide semiconductor. [Figure 7] Energy band diagram (schematic diagram) at the A-A' cross section in Figure 6. [Figure 8] (A) shows the state where a positive potential (VG>0) is applied to the gate (GE1), and (B) shows the state where a negative potential (VG<0) is applied to the gate (GE1). [Figure 9] A diagram showing the relationship between the vacuum level, the work function of a metal (φM), and the electron affinity of an oxide semiconductor (χ). [Figure 10] 1 is a cross-sectional view illustrating a semiconductor device. [Figure 11] 1 is a cross-sectional view illustrating a semiconductor device. [Figure 12] 1 is a cross-sectional view illustrating a semiconductor device. [Figure 13] 1 is a cross-sectional view illustrating a semiconductor device. [Figure 14] FIG. 1 is a diagram illustrating a memory cell. [Figure 15] FIG. 10 is a diagram for explaining a writing circuit. [Figure 16] FIG. 2 is a diagram for explaining a read circuit. [Figure 17] FIG. [Figure 18] FIG. [Figure 19] FIG. 10 is a flowchart illustrating the operation. [Figure 20] 10A and 10B are diagrams showing an example of a state after data is written when no correction is performed and an example of a state after data is written when correction is performed. [Figure 21]1A to 1C are diagrams illustrating a semiconductor device. [Figure 22] 1A and 1B are diagrams illustrating electronic devices. DETAILED DESCRIPTION OF THE INVENTION

[0039] An example of an embodiment of the present invention will be described below with reference to the drawings. and the present invention is not limited to the above description, and may be modified in various forms and forms without departing from the spirit and scope of the present invention. It will be readily apparent to those skilled in the art that various modifications may be made to the details. The present invention is not to be construed as being limited to the description of the embodiment shown in the accompanying drawings.

[0040] In addition, the position, size, range, etc. of each component shown in the drawings etc. are for ease of understanding. Therefore, the actual position, size, range, etc. may not necessarily be represented in the drawings, etc. The present invention is not limited to the position, size, range, etc. disclosed in the above.

[0041] In this specification, ordinal numbers such as "first," "second," and "third" are used to avoid confusion of components. It should be noted that the numbers are added to avoid confusion and are not intended to limit the number.

[0042] (Embodiment 1) In this embodiment, a structure and a manufacturing method of a semiconductor device according to one embodiment of the disclosed invention will be described. This will be described with reference to FIGS. 1 to 13.

[0043] <Circuit configuration of semiconductor device> FIG. 1 shows an example of a circuit configuration of a semiconductor device. The transistor 160 is made of a material and the transistor 162 is made of an oxide semiconductor. Note that FIG. 1 clearly shows that an oxide semiconductor is used for the transistor 162. Therefore, the OS code is also used.

[0044] Here, the gate electrode of transistor 160 and the source electrode or drain of transistor 162 are The first line (1st Line) is electrically connected to one of the drain electrodes. The second line (also referred to as a source line) and the source electrode of the transistor 160 are electrically connected to each other. The wiring (2nd Line: also called bit line) and the drain electrode of the transistor 160 are electrically connected. The third wiring (3rd Line: also referred to as the first signal line) The transistor 162 is electrically connected to the other of the source electrode and the drain electrode. A fourth line (also called a second signal line) and the transistor 162 It is electrically connected to the gate electrode.

[0045] The transistor 160 using a material other than an oxide semiconductor is a transistor using an oxide semiconductor. Compared to the conventional memory, it can operate at a higher speed, so by using it, the contents of the memory can be In addition, a transistor using an oxide semiconductor can be used. The transistor 162 has a feature of having an extremely small off-state current. By turning off the transistor 62, the potential of the gate electrode of the transistor 160 is maintained for a very long time. It is possible to maintain the

[0046] By utilizing the feature that the potential of the gate electrode can be maintained, It is possible to write, hold, and read data.

[0047] First, writing and holding of information will be explained. First, the potential of the fourth wiring is set to The potential is set to turn on the transistor 162, thereby turning on the transistor 162. As a result, the potential of the third wiring is applied to the gate electrode of the transistor 160 (write After that, the potential of the fourth wiring is set to a potential at which the transistor 162 is turned off. By turning off the transistor 162, the gate electrode of the transistor 160 The potential is maintained (retention).

[0048] Since the off-state current of the transistor 162 is extremely small, the gate electrode of the transistor 160 For example, if the potential of the gate electrode of transistor 160 is If the potential is such that the transistor 160 is turned on, the transistor 160 will remain on for a long time. The potential of the gate electrode of the transistor 160 is maintained for a certain period of time. If the potential is such that the transistor 160 is turned off, the transistor 160 will remain in the off state for a long time. is maintained over time.

[0049] Next, the reading of information will be described. As described above, when the transistor 160 is in the ON state, Alternatively, when the off state is maintained, a predetermined potential (low potential) is applied to the first wiring. When the transistor 160 is turned on, the potential of the second wiring changes depending on whether the transistor 160 is turned on or off. For example, when the transistor 160 is on, the potential of the first wiring is In response to this, the potential of the second wiring is reduced. In this case, the potential of the second wiring does not change.

[0050] In this way, in the state where the information is held, the potential of the second wiring is compared with a predetermined potential. This allows the information to be read out.

[0051] Next, the rewriting of information will be described. That is, the potential of the fourth wiring is held when the transistor 162 is turned on. This turns on the transistor 162. (the potential related to the new information) is applied to the gate electrode of the transistor 160. The potential of the fourth wiring is set to a potential at which the transistor 162 is turned off. By turning off 62, the new information is held.

[0052] In this way, the semiconductor device according to the disclosed invention can directly write information again. It is possible to rewrite information. This is why it is necessary for flash memory etc. This eliminates the need for an erase operation, and can suppress a decrease in operation speed due to the erase operation. That is, high-speed operation of the semiconductor device is realized.

[0053] The above explanation is for n-type transistors (n-channel transistors) in which electrons are the majority carriers. This is about using a large number of hole-capacitors instead of n-type transistors. It goes without saying that a p-type transistor can be used as a carrier.

[0054] It goes without saying that further elements may be added to the above configuration. For example, The gate electrode of transistor 160 and the source or drain electrode of transistor 162 Even if a capacitance element is connected to one of the electrodes to increase the tolerance for potential fluctuations, good.

[0055] <Plane and cross-sectional configurations of semiconductor device> 2A and 2B show an example of the configuration of the semiconductor device. 2(B) shows a plan view of the semiconductor device. These correspond to the cross sections taken along lines A1-A2 and B1-B2 in FIG. 2(A) and FIG. 2(B). The semiconductor device shown in FIG. 1 has a transistor 160 using a material other than an oxide semiconductor in the lower part. The transistor 162 includes an oxide semiconductor in the upper portion. Transistor 160 and transistor 162 are both described as n-type transistors. However, a p-type transistor may also be used. In particular, the transistor 160 is preferably a p-type transistor. It is easy to do this.

[0056] The transistor 160 includes a channel forming region 11 provided in a substrate 100 including a semiconductor material. 6, and the impurity region 114 and the high concentration impurity region 115 provided so as to sandwich the channel forming region 116. The pure region 120 (collectively referred to as the impurity region) and the channel forming region 11 6, and a gate electrode provided on the gate insulating layer 108. 110 and a source or drain electrode 130a electrically connected to the impurity region 114. , and a source electrode or a drain electrode 130b.

[0057] Here, a sidewall insulating layer 118 is provided on the side surface of the gate electrode 110. In addition, in the region of the substrate 100 that does not overlap with the sidewall insulating layer 118 in a plan view, a high A high concentration impurity region 120 is provided, and a metal compound region 124 is provided on the high concentration impurity region 120. In addition, an element isolation insulating layer 106 is formed on the substrate 100 so as to surround the transistor 160. The transistor 160 is covered with an interlayer insulating layer 126 and an interlayer insulating film. A source or drain electrode 130a, a source or drain electrode 130b, a The drain electrode 130b is formed through an opening formed in the interlayer insulating layer 126 and the interlayer insulating layer 128. That is, the source electrode or the drain electrode is electrically connected to the metal compound region 124. The source or drain electrode 130a and the source or drain electrode 130b are formed in the metal compound region 124. The high concentration impurity region 120 and the impurity region 114 are electrically connected via the The gate electrode 110 is provided with a source or drain electrode 130a and a source or drain electrode 130b. An electrode 130c provided similarly to the drain electrode 130b is electrically connected to the drain electrode 130b.

[0058] The transistor 162 includes a gate electrode 136d provided on the interlayer insulating layer 128 and a gate A gate insulating layer 138 is provided on the electrode 136d, and a gate insulating layer 138 is provided on the gate insulating layer 138. an oxide semiconductor layer 140; and a metal oxide film provided on the oxide semiconductor layer 140. The source or drain electrode 142a is electrically connected to the source or drain electrode 142b. and an inner electrode 142b.

[0059] Here, the gate electrode 136d is embedded in the insulating layer 132 formed on the interlayer insulating layer 128. Similarly to the gate electrode 136d, the source electrode or The electrode 136a is in contact with the drain electrode 130a, and the source or drain electrode 130b Electrode 136b is formed in contact with electrode 130c, and electrode 136c is formed in contact with electrode 130c. do.

[0060] In addition, a protective film is formed on the transistor 162 so as to be in contact with part of the oxide semiconductor layer 140. An insulating layer 144 is provided, and an interlayer insulating layer 146 is provided on the protective insulating layer 144. Here, the protective insulating layer 144 and the interlayer insulating layer 146 are provided with a source electrode or a drain electrode. An opening is provided that reaches the source electrode 142a and the source or drain electrode 142b. Through the openings, the electrodes 150d and 150e are connected to the source and drain electrodes. The electrode 142a is formed in contact with the source electrode or the drain electrode 142b. As well as electrodes 150d and 150e, gate insulating layer 138, protective insulating layer 144, interlayer insulating layer The electrodes 136a, 136b, and 136c are in contact with each other through openings provided in the layer 146. Electrodes 150a, 150b, and 150c are formed.

[0061] Here, the oxide semiconductor layer 140 is highly purified by sufficiently removing impurities such as hydrogen. Specifically, the hydrogen concentration of the oxide semiconductor layer 140 is preferably 5×10 19 atoms / cm 3 Below 5×10 18 atoms / cm 3 Below, more hope Preferably 5 x 10 17 atoms / cm 3 In addition, the hydrogen concentration is sufficiently reduced. In the oxide semiconductor layer 140 that has been highly purified by this method, the carrier concentration is 1×10 12 / cm 3 less than , preferably 1×10 11 / cm 3 In this way, the hydrogen concentration is sufficiently reduced. By using an oxide semiconductor that has been highly purified and made i-type or substantially i-type, Therefore, the transistor 162 can have excellent off-state current characteristics. When Vd is +1V or +10V, the gate voltage Vg is in the range of -5V to -20V. In this range, the off-state current is 1×10 -13 A or less. In this way, the hydrogen concentration is sufficiently reduced. The oxide semiconductor layer 140 is highly purified by the above-mentioned method, and the off-state current of the transistor 162 is reduced. By reducing the amount of oxidation, a semiconductor device with a new configuration can be realized. The hydrogen concentration in the compound semiconductor layer 140 was measured by secondary ion mass spectroscopy (SIMS). The results were measured using ion mass spectroscopy (Ion Mass Spectroscopy).

[0062] An insulating layer 152 is provided on the interlayer insulating layer 146, and a buried insulating layer 152 is provided on the insulating layer 152. Electrodes 154a, 154b, 154c, and 154d are provided so that the electrodes are embedded in the Here, electrode 154a is in contact with electrode 150a, and electrode 154b is in contact with electrode 150a. b, electrode 154c is in contact with electrode 150c and electrode 150d, and electrode 1 54d is in contact with electrode 150e.

[0063] That is, in the semiconductor device shown in FIG. 2, the gate electrode 110 of the transistor 160 and the The source electrode or drain electrode 142a of the transistor 162 is connected to the electrode 130c, the electrode 1 36c, electrode 150c, electrode 154c and electrode 150d. do.

[0064] <Method for manufacturing semiconductor device> Next, an example of a method for manufacturing the semiconductor device will be described. The method for fabricating the transistor 160 will be explained with reference to FIG. A method for manufacturing the capacitor 162 will be described with reference to FIGS.

[0065] <Method for manufacturing the lower transistor> First, a substrate 100 containing a semiconductor material is prepared (see FIG. 3(A)). The plate 100 may be a single crystal semiconductor substrate such as silicon or silicon carbide, or a polycrystalline semiconductor substrate. Compound semiconductor substrates such as silicon germanium, SOI substrates, etc. can be used. Here, the substrate 100 containing a semiconductor material is a single crystal silicon substrate. An example will be shown below. Generally, an "SOI substrate" is a substrate in which silicon semiconductor is formed on an insulating surface. It refers to a substrate having a structure in which a conductor layer is provided, but in this specification, it refers to a substrate having a silicon layer on an insulating surface. The concept also includes substrates having semiconductor layers made of materials other than those mentioned above. The semiconductor layer of the "SOI substrate" is not limited to a silicon semiconductor layer. The substrate is configured such that a semiconductor layer is provided on an insulating substrate such as a glass substrate via an insulating layer. This includes:

[0066] A protective layer 102 is formed on the substrate 100 to serve as a mask for forming an element isolation insulating layer. (See FIG. 3(A)). The protective layer 102 may be made of, for example, silicon oxide or silicon nitride. An insulating layer made of silicon nitride oxide or the like can be used. In order to control the threshold voltage of the transistor, impurities that give n-type conductivity are used. The substrate 100 may be doped with an impurity element that imparts p-type conductivity or a metal element that imparts p-type conductivity. In the case of silicon, impurities that give n-type conductivity include phosphorus and arsenic. In addition, impurities that impart p-type conductivity include, for example, boron and aluminum. Sodium, gallium, etc. can be used.

[0067] Next, etching is performed using the protective layer 102 as a mask, and the The part of the substrate 100 in the area where the semiconductor substrate 100 is not exposed is removed. The conductive region 104 is formed (see FIG. 3(B)). It is preferable to use an etching gas or an etchant, but wet etching may also be used. The etching liquid can be appropriately selected depending on the material to be etched.

[0068] Next, an insulating layer is formed so as to cover the semiconductor region 104, and the region overlapping the semiconductor region 104 is The insulating layer is selectively removed to form an element isolation insulating layer 106 (see FIG. 3(B)). The insulating layer is formed using silicon oxide, silicon nitride, silicon nitride oxide, etc. The insulating layer can be removed by polishing such as CMP or etching. After the semiconductor region 104 is formed or after the element isolation insulating film is formed, After the layer 106 is formed, the protective layer 102 is removed.

[0069] Next, an insulating layer is formed on the semiconductor region 104, and a layer containing a conductive material is formed on the insulating layer. do.

[0070] The insulating layer will later become the gate insulating layer and is obtained using a method such as CVD or sputtering. Silicon oxide, silicon nitride oxide, silicon nitride, hafnium oxide, aluminum oxide It is preferable to use a single layer or multilayer structure of a film containing aluminum, tantalum oxide, etc. The surface of the semiconductor region 104 is oxidized or nitrided by plasma treatment or thermal oxidation treatment. The insulating layer may be formed by the high density plasma treatment. Using a mixture of rare gases such as Xe and oxygen, nitrogen oxide, ammonia, nitrogen, and hydrogen The thickness of the insulating layer is not particularly limited, but may be, for example, 1 nm or more and 10 nm or less. It can be 0 nm or less.

[0071] The layer containing the conductive material is made of a metal material such as aluminum, copper, titanium, tantalum, or tungsten. Also, the insulating film can be formed using a semiconductor material such as polycrystalline silicon containing a conductive material. The method for forming the conductive material is not particularly limited, and examples thereof include vapor deposition, C Various film formation methods such as VD method, sputtering method, and spin coating method can be used. In this embodiment mode, the layer containing a conductive material is formed using a metal material. The following information will be provided.

[0072] Thereafter, the insulating layer and the layer containing the conductive material are selectively etched to form the gate insulating layer 108. Then, the gate electrode 110 is formed (see FIG. 3(C)).

[0073] Next, an insulating layer 112 is formed to cover the gate electrode 110 (see FIG. 3(C)). Phosphorus (P) or arsenic (As) is added to the conductive region 104 to form a shallow junction with the substrate 100. In this case, an n-type transistor is formed. However, when forming a p-type transistor, Impurity elements such as boron (B) and aluminum (Al) can be added. By forming the region 114, a channel-forming region is formed below the gate insulating layer 108 in the semiconductor region 104. A region 116 is formed (see FIG. 3C). Here, the concentration of the added impurity is set appropriately. However, when semiconductor elements are highly miniaturized, the concentration can be increased. In this case, after the insulating layer 112 is formed, impurities are introduced. The process of forming the region 114 is adopted, but after forming the impurity region 114, the insulating layer 1 This may be a process for forming 12.

[0074] Next, a sidewall insulating layer 118 is formed (see FIG. 3(D)). The layer 118 is formed by forming an insulating layer to cover the insulating layer 112 and then adding a highly anisotropic By applying a simple etching process, it can be formed in a self-aligned manner. Then, the insulating layer 112 is partially etched to expose the upper surface of the gate electrode 110 and the impurity region 1 It is advisable to expose the top surface of 14.

[0075] Next, a layer is formed so as to cover the gate electrode 110, the impurity region 114, the sidewall insulating layer 118, etc. An insulating layer is formed on the impurity region 114. Then, phosphorus ( By adding ions such as P and arsenic (As), a high concentration impurity region 120 is formed (see FIG. 3(E)). After that, the insulating layer is removed, and the gate electrode 110, the sidewall insulating layer 118, A metal layer 122 is formed so as to cover the high concentration impurity region 120 and the like (see FIG. 3(E)). The metal layer 122 can be formed by various film forming methods such as vacuum deposition, sputtering, and spin coating. The metal layer 122 can be formed using the semiconductor material that constitutes the semiconductor region 104. It is desirable to form the electrode using a metal material that reacts with the electrode to form a low-resistance metal compound. Such metal materials include, for example, titanium, tantalum, tungsten, nickel, and cobalt. Examples include platinum and platinum.

[0076] Next, a heat treatment is performed to react the metal layer 122 with the semiconductor material. A metal compound region 124 is formed in contact with the high concentration impurity region 120 (see FIG. 3(F)). When polycrystalline silicon or the like is used as the gate electrode 110, the gate electrode 110 A metal compound region is also formed in the portion in contact with the metal layer 122.

[0077] The heat treatment may be, for example, a heat treatment by irradiation with a flash lamp. Of course, other heat treatment methods may be used, but the chemical reaction involved in the formation of metal compounds In order to improve the controllability of the heat treatment, it is desirable to use a method that can realize a very short time of heat treatment. The metal compound region is preferably formed by a reaction between a metal material and a semiconductor material. The metal compound region is formed in a region where the conductivity is sufficiently increased. This can sufficiently reduce the electrical resistance and improve the device characteristics. After forming region 124, metal layer 122 is removed.

[0078] Next, an interlayer insulating layer 126 and an interlayer insulating layer 127 are formed to cover the respective components formed by the above-described steps. The interlayer insulating layer 126 and the interlayer insulating layer 128 are formed by oxidation. Silicon, silicon oxide nitride, silicon nitride, hafnium oxide, aluminum oxide, titanium oxide The insulating layer can be formed using a material containing an inorganic insulating material such as palladium. It is also possible to form the insulating layer using an organic insulating material such as acrylic. Although the structure is a two-layer structure of an edge layer 126 and an interlayer insulating layer 128, the structure of the interlayer insulating layer is not limited to this. After the interlayer insulating layer 128 is formed, the surface is not subjected to a CMP or etching process. Therefore, it is desirable to flatten it.

[0079] Thereafter, an opening is formed in the interlayer insulating layer so as to reach the metal compound region 124. The source or drain electrode 130a and the source or drain electrode 130b are The source or drain electrode 130a and the source or drain electrode 130b are formed (see FIG. 3(H)). The drain electrode 130b is formed by, for example, using a PVD method or a CVD method in the region including the opening. After forming the conductive layer, a part of the conductive layer is removed by etching or CMP. It can be formed by removing the

[0080] In addition, a part of the conductive layer is removed to form the source electrode or drain electrode 130a and the source electrode Alternatively, when forming the drain electrode 130b, the surface thereof is processed to be flat. For example, after forming a thin titanium film or titanium nitride film in the region including the opening, When a tungsten film is formed to fill the opening, the inclusions are removed by the subsequent CMP. It removes the necessary tungsten film, titanium film, titanium nitride film, etc., and also maintains the flatness of the surface. In this way, the source electrode or drain electrode 130a, By planarizing the surface including the source or drain electrode 130b, it is possible to This makes it possible to form good electrodes, wiring, insulating layers, semiconductor layers, and the like.

[0081] Here, the source electrode or drain electrode 130 in contact with the metal compound region 124 Although only the gate electrode 130a and the source electrode or the drain electrode 130b are shown, The electrode in contact with the port electrode 110 (for example, the electrode 130c in FIG. 2) is also formed. The source or drain electrode 130a, the source or drain electrode There are no particular limitations on the material that can be used for the electrode 130b, and various conductive materials can be used. For example, molybdenum, titanium, chromium, tantalum, tungsten, Conductive materials such as aluminum, copper, neodymium, and scandium can be used.

[0082] In this manner, the transistor 160 is formed using the substrate 100 containing a semiconductor material. After the above steps, electrodes, wiring, insulating layers, etc. may be further formed. In addition, by adopting a multilayer wiring structure consisting of a laminated structure of interlayer insulating layers and conductive layers, Therefore, it is possible to provide a highly integrated semiconductor device.

[0083] <How to make the upper transistor> Next, referring to FIGS. 4 and 5, a process for forming a transistor 162 on the interlayer insulating layer 128 will be described. 4 and 5 show various electrodes and transistors on the interlayer insulating layer 128. Since the figure shows the manufacturing process of the transistor 162, the The transistor 160 and other components that correspond to it are omitted.

[0084] First, an interlayer insulating layer 128, a source electrode or drain electrode 130a, and a source electrode or drain electrode 130b are formed. An insulating layer 132 is formed on the drain electrode 130b and the electrode 130c (see FIG. 4(A)). The edge layer 132 can be formed by using a PVD method, a CVD method, or the like. silicon nitride oxide, silicon nitride, hafnium oxide, aluminum oxide, tantalum oxide The insulating film 10 can be formed using a material containing an inorganic insulating material such as silica.

[0085] Next, the source or drain electrode 130a, the source or drain electrode 130b, and the insulating layer 132 are Openings are formed that reach the drain electrode 130b and the electrode 130c. An opening is also formed in the region where the gate electrode 136d is to be formed. A conductive layer 134 is formed to fill the opening (see FIG. 4B). The mask can be formed by a method such as etching using a photomask. It can be formed by exposure or other methods. Wet etching is also used. Either etching or dry etching may be used, but from the viewpoint of fine processing, dry etching is preferred. The conductive layer 134 is preferably formed by a deposition method such as PVD or CVD. The conductive layer 134 can be formed by a film method. , molybdenum, titanium, chromium, tantalum, tungsten, aluminum, copper, neodymium Conductive materials such as ZnO, ZnS, and scandium, as well as alloys and compounds thereof (e.g., nitrides), are examples of such materials. can be done.

[0086] More specifically, for example, a thin titanium film is formed in the area including the opening by the PVD method, and then CV After forming a thin titanium nitride film by the D method, a tungsten film is formed to fill the opening. Here, the titanium film formed by the PVD method is The outer electrode (here, the source electrode or the drain electrode 130a, the source electrode or the drain electrode The oxide film at the interface with the lower electrode (electrode 130b, electrode 130c, etc.) is reduced to reduce the contact resistance with the lower electrode. The titanium nitride film formed afterwards also serves to reduce the diffusion of conductive materials. It also has a barrier function that suppresses the formation of a barrier film made of titanium or titanium nitride. Afterwards, a copper film may be formed by plating.

[0087] After the conductive layer 134 is formed, the conductive layer 13 is removed by etching, CMP, or other methods. 4 is removed to expose the insulating layer 132, and the electrodes 136a, 136b, and 13 6c, a gate electrode 136d is formed (see FIG. 4(C)). The electrode 136a, the electrode 136b, the electrode 136c, and the gate electrode 136d are formed by removing the portions. When forming the insulating layer 132, it is desirable to process it so that the surface is flat. , the surfaces of the electrodes 136a, 136b, 136c, and gate electrode 136d are planarized. This allows for the formation of good electrodes, wiring, insulating layers, semiconductor layers, etc. in subsequent processes. This makes it possible to:

[0088] Next, the insulating layer 132, the electrode 136a, the electrode 136b, the electrode 136c, and the gate electrode 136d The gate insulating layer 138 is formed to cover the gate insulating layer 138 (see FIG. 4(D)). The gate insulating layer can be formed by using a CVD method, a sputtering method, or the like. 138 is silicon oxide, silicon nitride, silicon oxynitride, silicon nitride oxide, aluminum oxide, oxide It is preferable to form the gate insulating film so as to contain hafnium, tantalum oxide, etc. The layer 138 may have a single layer structure or a multilayer structure. Silicon oxynitride was produced by plasma CVD using silane (SiH4), oxygen, and nitrogen. The thickness of the gate insulating layer 138 is not particularly limited. However, it can be, for example, 10 nm or more and 500 nm or less. For example, a first gate insulating layer having a film thickness of 50 nm or more and 200 nm or less and a first gate insulating layer It is preferable to laminate a second gate insulating layer having a thickness of 5 nm to 300 nm on the layer.

[0089] Note that an oxide semiconductor (high-temperature oxide semiconductor) that has been made i-type or substantially i-type by removing impurities is Since the purified oxide semiconductor is extremely sensitive to the interface states and the interface charges, When such an oxide semiconductor is used for the oxide semiconductor layer, the interface with the gate insulating layer is important. That is, the gate insulating layer 138 in contact with the highly purified oxide semiconductor layer has a high-quality oxide semiconductor layer. Quality will be required.

[0090] For example, the high density plasma CVD method using microwaves (2.45GHz) produces dense and high dielectric strength materials. This is advantageous in that a high quality gate insulating layer 138 can be formed. The close contact between the conductor layer and the high-quality gate insulating layer reduces the interface state and improves the interface characteristics. Because it can be made into a good one.

[0091] Of course, if it can form a good insulating layer as a gate insulating layer, highly purified Even when an oxide semiconductor layer is used, other methods such as sputtering and plasma CVD are used. In addition, the film quality and the oxide semiconductor layer can be improved by heat treatment after the formation. Alternatively, an insulating layer may be applied to modify the interface properties of the gate insulating layer 138. The film quality as a gate insulating film is good, and the interface state density with the oxide semiconductor layer is reduced, resulting in a good interface. All that is required is to form something that can form a surface.

[0092] Furthermore, at 85°C, 2 × 10 6 V / cm, 12-hour gate bias thermal stress test (B In the T test, when impurities are added to an oxide semiconductor, the impurities and the oxide semiconductor The bond with the main component of is broken by a strong electric field (B: bias) and high temperature (T: temperature), and The dangling bonds induce a drift in the threshold voltage (Vth).

[0093] In response to this, impurities in the oxide semiconductor, especially hydrogen and water, are eliminated as much as possible, and the gate electrode is By improving the interface characteristics with the base insulating layer, a stable transistor is produced even during BT tests. It is possible to obtain data.

[0094] Next, an oxide semiconductor layer is formed over the gate insulating layer 138 and etched using a mask. The oxide semiconductor layer is processed by the above method to form an island-shaped oxide semiconductor layer 140. (See FIG. 4(E)).

[0095] The oxide semiconductor layer is made of quaternary metal oxides such as In-Sn-Ga-Zn-O and ternary metal oxides such as In-Sn-Ga-Zn-O. In-Ga-Zn-O, In-Sn-Zn-O, In-Al-Zn- O, Sn-Ga-Zn-O, Al-Ga-Zn-O, Sn-Al-Zn-O, and binary alloys Metal oxides such as In-Zn-O, Sn-Zn-O, Al-Zn-O, Zn-Mg-O, and S Oxide semiconductors using n-Mg-O, In-Mg-O, In-O, Sn-O, Zn-O, etc. A conductive layer can be applied. In addition, SiO2 may be contained in the oxide semiconductor layer. stomach.

[0096] The oxide semiconductor layer is InMO3(ZnO) m Use a thin film expressed as (m>0) Here, M can be one or more selected from Ga, Al, Mn and Co. It represents a metal element. For example, M can be Ga, Ga and Al, Ga and Mn, or Ga and Co, etc. InMO3(ZnO)m Oxide semiconductor film with a structure represented by (m>0) Among these, oxide semiconductors with a structure containing Ga as M are called In-Ga-Zn-O oxide semiconductors. The thin film is called an In-Ga-Zn-O oxide semiconductor film (In-Ga-Zn-O amorphous membrane).

[0097] In this embodiment, an oxide semiconductor layer is formed using an In-Ga-Zn-O system oxide semiconductor film forming method. An amorphous oxide semiconductor layer is formed by a sputtering method using a target. Note that adding silicon to an amorphous oxide semiconductor layer can suppress crystallization of the layer. Therefore, for example, a target containing 2% by weight or more and 10% by weight or less of SiO2 is used. The oxide semiconductor layer may be formed by

[0098] Examples of targets for forming an oxide semiconductor layer by sputtering include oxide A target of a metal oxide containing zinc as the main component can be used. and Zn-containing oxide semiconductor film deposition target (composition ratio: In2O3:Ga2O 3:ZnO=1:1:1[mol ratio], In:Ga:Zn=1:1:0.5[atom %]) can also be used. In addition, an oxide semiconductor material containing In, Ga, and Zn can also be used. The film target was In2O3:Ga2O3:ZnO=1:1:2 [molar ratio]. Or a tantalum having a composition ratio of In2O3:Ga2O3:ZnO=1:1:4 [molar ratio] The filling rate of the oxide semiconductor film forming target is 90% or more. 0% or less, preferably 95% or more (for example, 99.9%). By using a target for bulk film formation, a dense oxide semiconductor layer is formed.

[0099] The oxide semiconductor layer is formed in a rare gas (typically, argon) atmosphere, an oxygen atmosphere, or Alternatively, it is preferable to use a mixed atmosphere of rare gas (typically argon) and oxygen. In practice, the concentration of impurities such as hydrogen, water, hydroxyl groups, or hydrides is approximately several ppm. It is preferable to use a high purity gas in which the concentration has been reduced to a level of preferably about several ppb.

[0100] When forming the oxide semiconductor layer, the substrate is held in a treatment chamber kept in a reduced pressure state. The temperature is set to 100°C or higher and 600°C or lower, preferably 200°C or higher and 400°C or lower. By forming the oxide semiconductor layer while heating, the impurity concentration in the oxide semiconductor layer can be reduced. Damage caused by sputtering can also be reduced. The residual moisture in the metal oxide layer is removed, and a sputtering gas from which hydrogen and water have been removed is introduced. The oxide semiconductor layer is formed using a target of It is preferable to use an adsorption type vacuum pump. For example, a cryopump or an ion pump A titanium sublimation pump can be used. A cryopump with a cold trap may be used. The deposition chamber is filled with, for example, hydrogen atoms, compounds containing hydrogen atoms such as water (H2O) (preferably Since the oxide semiconductor formed in the film formation chamber is exhausted, The concentration of impurities contained in the layer can be reduced.

[0101] The formation conditions are, for example, a distance of 100 mm between the substrate and the target, a pressure of 0.6 Pa, DC power 0.5kW, oxygen atmosphere (oxygen flow rate 100%), The following conditions can be applied. When a pulsed direct current (DC) power supply is used, film formation can be performed. This reduces the amount of powdery material (also called particles or dust) that is generated at times, and the film thickness distribution is uniform. The thickness of the oxide semiconductor layer is preferably 2 nm or more and 200 nm or less, more preferably 5 nm or less. The thickness is from 100 nm to 30 nm. The appropriate thickness varies depending on the oxide semiconductor material used. Therefore, the thickness may be appropriately selected depending on the material used.

[0102] Before forming the oxide semiconductor layer by sputtering, argon gas was introduced to Reverse sputtering is performed to generate a smear, and dust adhering to the surface of the gate insulating layer 138 is removed. Here, the reverse sputtering is a method of removing the sputtering Instead of bombarding the target with ions, the treatment surface is bombarded with ions. The method of bombarding the treated surface with ions is as follows: A high frequency voltage is applied to the surface to be treated in an argon atmosphere to generate plasma near the substrate. In addition, nitrogen atmosphere, helium atmosphere, oxygen atmosphere, etc. can be used instead of argon atmosphere. An atmosphere or the like may also be used.

[0103] The oxide semiconductor layer can be etched by either dry etching or wet etching. Of course, both can be used in combination. To enable matching, etching conditions (etching gas, etching solution, etc.) are set according to the material. The etching time, temperature, etc. are set appropriately.

[0104] The etching gas used in dry etching is, for example, a gas containing chlorine (chlorine-based gas, For example, chlorine (Cl2), boron chloride (BCl3), silicon chloride (SiCl4), carbon tetrachloride ( CCl4) and other gases containing fluorine (fluorine-based gases, such as carbon tetrafluoride). Fluorine (CF4), sulfur hexafluoride (SF6), nitrogen trifluoride (NF3), trifluoromethane (C HF3), hydrogen bromide (HBr), oxygen (O2), and helium (He) in these gases Alternatively, a gas containing a rare gas such as argon (Ar) may be used.

[0105] As a dry etching method, parallel plate type RIE (Reactive Ion Etch) ing) method and ICP (Inductively Coupled Plasma) A plasma-coupled plasma etching method can be used. As shown in the figure, the etching conditions (the amount of power applied to the coil-type electrode, the amount of power applied to the electrode on the substrate side) The amount of power, the temperature of the electrode on the substrate, etc. are set appropriately.

[0106] The etching solution used for wet etching is a mixture of phosphoric acid, acetic acid, and nitric acid. Ammonia peroxide water (31% by weight hydrogen peroxide: 28% by weight ammonia water: water = 5:2:2) In addition, etching solutions such as ITO07N (manufactured by Kanto Chemical Co., Ltd.) can be used. It's fine.

[0107] Next, the oxide semiconductor layer is preferably subjected to first heat treatment. The oxide semiconductor layer can be dehydrated or dehydrogenated by the first heat treatment. The temperature is set to 300°C or higher and 750°C or lower, preferably 400°C or higher and lower than the strain point of the substrate. For example, The substrate is placed in an electric furnace using a resistance heating element or the like, and the oxide semiconductor layer 140 is heated in a nitrogen atmosphere. Heat treatment is performed at 450° C. in air for 1 hour. Avoid contact to prevent recontamination with water or hydrogen.

[0108] The heat treatment device is not limited to an electric furnace, and may be any device that uses heat conduction from a medium such as heated gas, or It may also be a device that heats the object to be treated by thermal radiation. For example, a GRTA (Gas Rapid Thermal Anneal) equipment, LRTA (Lamp Rapid RTA (Rapid Thermal Anneal) equipment, etc. The LRTA device can be equipped with halogen lamps, metal halide lamps, etc. Lamps, xenon arc lamps, carbon arc lamps, high-pressure sodium lamps, high-pressure water A device that heats the object to be treated by radiating light (electromagnetic waves) emitted from a lamp such as a silver lamp. The GRTA device is a device that performs heat treatment using high-temperature gas. An inert gas that does not react with the material to be treated by heat treatment, such as a rare gas such as argon or nitrogen. A gas is used.

[0109] For example, in the first heat treatment, the substrate is immersed in an inert gas heated to a high temperature of 650°C to 700°C. After heating for several minutes, the substrate is taken out of the inert gas (GRTA) treatment. GRTA treatment allows high-temperature heat treatment in a short time. Because it is a heat treatment, it can be applied even at temperatures exceeding the distortion point of the substrate.

[0110] The first heat treatment is performed in a gas atmosphere containing nitrogen or a rare gas (helium, neon, argon, etc.) as the main component. It is desirable to carry out the process in an atmosphere that does not contain water, hydrogen, etc. The purity of nitrogen or rare gases such as helium, neon, and argon introduced into the heat treatment device is 6N (99.9999%) or more, preferably 7N (99.99999%) or more (i.e. The impurity concentration is 1 ppm or less, preferably 0.1 ppm or less.

[0111] Depending on the conditions of the first heat treatment or the material of the oxide semiconductor layer, the oxide semiconductor layer may be crystallized. For example, the crystallinity may be 90% or more, or 80% or more. % or more of a microcrystalline oxide semiconductor layer. Depending on the material of the oxide semiconductor layer, it may become an amorphous oxide semiconductor layer that does not contain crystalline components. There are also cases where this is the case.

[0112] In addition, microcrystals (grain size of 1 nm or less) are formed on the amorphous oxide semiconductor (for example, on the surface of the oxide semiconductor layer). The oxide semiconductor layer is a mixture of the upper 20 nm or less (typically 2 nm to 4 nm). There are cases like this.

[0113] In addition, the electrical characteristics of the oxide semiconductor layer can be changed by arranging microcrystals in the amorphous state. For example, an In-Ga-Zn-O oxide semiconductor film formation target can be used. When forming an oxide semiconductor layer using In2Ga2ZnO7 By forming a microcrystalline portion in which the crystal grains are oriented, the electrical characteristics of the oxide semiconductor layer can be changed. It is possible.

[0114] More specifically, for example, the c-axis of In2Ga2ZnO7 is perpendicular to the surface of the oxide semiconductor layer. By orienting the oxide semiconductor layer in this direction, the conductivity in the direction parallel to the surface of the oxide semiconductor layer is improved. This can improve the insulating properties in the direction perpendicular to the surface of the oxide semiconductor layer. The microcrystalline portion has a function of suppressing the penetration of impurities such as water and hydrogen into the oxide semiconductor layer. It has.

[0115] The oxide semiconductor layer having the above-described microcrystalline portion is formed by GRTA treatment. It can be formed by surface heating. Also, the content of Zn is higher than the content of In or Ga. A more suitable formation can be achieved by using a smaller sputtering target.

[0116] The first heat treatment on the oxide semiconductor layer 140 is performed to process the oxide semiconductor layer 140 into an island-shaped oxide semiconductor layer 140. In this case, the first heat treatment is performed on the oxide semiconductor layer. The substrate is then removed and subjected to a photolithography process.

[0117] The first heat treatment has the effect of dehydrating and dehydrogenating the oxide semiconductor layer 140. Therefore, it can also be called dehydration treatment, dehydrogenation treatment, etc. The hydrogenation treatment is carried out after forming the oxide semiconductor layer, by forming a source electrode or a drain electrode on the oxide semiconductor layer 140. After laminating the source electrode and drain electrode, a protective insulating layer is formed on the source electrode or drain electrode. In addition, such dehydration treatment, dehydration The oxidation treatment may be carried out not only once but also multiple times.

[0118] Next, a source electrode or drain electrode 142a, The source or drain electrode 142b is formed (see FIG. 4(F)). The drain electrode 142a and the source or drain electrode 142b are formed on the oxide semiconductor layer 1 After forming a conductive layer to cover 40, the conductive layer is selectively etched. It can be formed.

[0119] The conductive layer is formed using PVD methods such as sputtering, or CVD methods such as plasma CVD. The conductive layer can be formed using a material such as aluminum, chromium, copper, An element selected from tantalum, titanium, molybdenum, and tungsten, or the above-mentioned elements Alloys containing manganese, magnesium, zirconium, and beryllium can be used. Alternatively, one or more materials selected from the group consisting of arsenic, thorium, and arsenic may be used. Aluminum, titanium, tantalum, tungsten, molybdenum, chromium, neodymium, scum A material containing a single element selected from indium or a combination of multiple elements may also be used.

[0120] The conductive layer may be formed of a conductive metal oxide. Indium oxide (In2O3), tin oxide (SnO2), zinc oxide (ZnO), indium oxide In2O3-SnO2 alloy (sometimes abbreviated as ITO), indium oxide In2O3-ZnO alloys or silicon or zinc oxide alloys Alternatively, one containing silicon oxide can be used.

[0121] The conductive layer may have a single layer structure or a laminated structure of two or more layers. Single layer structure of aluminum film containing titanium, and two layer structure of titanium film laminated on aluminum film. and a three-layer structure in which a titanium film, an aluminum film and another titanium film are laminated.

[0122] Here, the exposure to light when forming the mask used for etching is ultraviolet light, KrF laser light, or ArF Preferably, a laser beam is used.

[0123] The channel length (L) of the transistor is the distance from the bottom end of the source or drain electrode 142a to the , is determined by the distance between the lower end of the source electrode or drain electrode 142b. When exposure is performed with a channel length (L) of less than 25 nm, the channel length is extremely small, ranging from several nm to several tens of nm. Extreme ultraviolet light with extremely short wavelengths is used to create a mask-shaped Extreme ultraviolet light exposure provides high resolution and a large depth of focus. The channel length (L) of the formed transistor is set to 10 nm or more and 1000 nm or less. Furthermore, the off-state current is extremely small, This avoids a large power consumption.

[0124] When etching the conductive layer, the oxide semiconductor layer 140 is not removed. The materials and etching conditions are adjusted appropriately. In this step, a part of the oxide semiconductor layer 140 is etched to form a groove (a recess ) may be formed as an oxide semiconductor layer.

[0125] In addition, between the oxide semiconductor layer 140 and the source electrode or the drain electrode 142a, An oxide conductive layer is formed between the conductive layer 140 and the source or drain electrode 142b. The oxide conductive layer and the source or drain electrode 142a or the source or drain electrode 142b may be The metal layer for forming the drain electrode 142b is formed continuously (continuous film formation). The oxide conductive layer can function as a source region or a drain region. By providing such an oxide conductive layer, it is possible to reduce the resistance of the source region or the drain region. This allows the transistor to operate at high speed.

[0126] In order to reduce the number of masks used and the number of processes, an exposure method is used in which the transmitted light has multiple intensities. A resist mask is formed using a multi-tone mask, which is a mask, and an etching process is performed using this. The resist mask formed using the multi-tone mask has a plurality of thicknesses. The shape becomes stepped, and the shape can be further deformed by ashing. It can be used for multiple etching processes to process different patterns. A multi-tone mask allows for resist masks that correspond to at least two different patterns. Therefore, the number of exposure masks can be reduced, and the corresponding photomasks can be formed. The lithography process can also be eliminated, simplifying the process.

[0127] After the above process, plasma treatment using gas such as N2O, N2, or Ar may be performed. It is preferable that the plasma treatment is performed on the exposed surface of the oxide semiconductor layer. Adhered water and other substances are removed. In addition, plasma treatment is performed using a mixture of oxygen and argon gas. You may go.

[0128] Next, the protective insulating layer 14 in contact with a part of the oxide semiconductor layer 140 is removed without being exposed to the air. 4 is formed (see Figure 4(G)).

[0129] The protective insulating layer 144 is formed by a method such as sputtering, which does not mix impurities such as water or hydrogen into the protective insulating layer 144. The thickness of the film should be at least 1 nm. The protective insulating layer 144 can be formed of a material such as silicon oxide, silicon nitride, or the like. Silicon oxynitride, silicon nitride oxide, etc. The structure may be a single layer structure, The substrate temperature when the protective insulating layer 144 is formed is equal to or higher than room temperature and equal to or higher than 300° C. The atmosphere is preferably a rare gas (typically argon) atmosphere or an oxygen atmosphere. Alternatively, a mixed atmosphere of a rare gas (typically argon) and oxygen is preferably used.

[0130] If hydrogen is contained in the protective insulating layer 144, the hydrogen may penetrate into the oxide semiconductor layer or the oxide semiconductor layer may be damaged by the hydrogen. Oxygen is extracted from the oxide semiconductor layer by the oxide semiconductor layer. Therefore, the protective insulating layer 1 may have a low resistance and a parasitic channel may be formed. It is important to avoid using hydrogen in the formation method so that 44 does not contain as much hydrogen as possible. is.

[0131] In addition, it is preferable to form the protective insulating layer 144 while removing residual moisture in the processing chamber. The compound semiconductor layer 140 and the protective insulating layer 144 are formed so as not to contain hydrogen, hydroxyl groups, or water. This is because.

[0132] To remove residual moisture from the processing chamber, it is preferable to use an adsorption type vacuum pump. For example, a cryopump, an ion pump, or a titanium sublimation pump can be used. The exhaust means is preferably a turbo pump with a cold trap added. The film formation chamber evacuated using a cryopump may contain, for example, hydrogen atoms and water (H2 O) and other compounds containing hydrogen atoms are removed, The concentration of impurities contained in the layer 144 can be reduced.

[0133] The sputtering gas used when forming the protective insulating layer 144 is hydrogen, water, a hydroxyl group, or The concentration of impurities such as hydrides is reduced to a few ppm (preferably a few ppb). It is preferable to use high purity gases that have been removed.

[0134] Then, a second heat treatment (preferably 20 It is desirable to carry out the heating at a temperature of 0°C or higher and 400°C or lower, for example, 250°C or higher and 350°C or lower. Then, a second heat treatment is performed at 250° C. for 1 hour in a nitrogen atmosphere. This can reduce variations in the electrical characteristics of the transistors.

[0135] In addition, even if heat treatment is performed in air at 100°C to 200°C for 1 hour to 30 hours, This heat treatment can be carried out by maintaining a constant heating temperature, or by heating from room temperature to 100°C or higher. Repeat the heating process several times to a temperature of 200°C or less and then to room temperature. This heat treatment may also be carried out under reduced pressure before the formation of the protective insulating layer. When the heat treatment is performed under reduced pressure, the heating time can be shortened. This may be carried out instead of the second heat treatment, or may be carried out before or after the second heat treatment.

[0136] Next, an interlayer insulating layer 146 is formed on the protective insulating layer 144 (see FIG. 5(A)). The edge layer 146 can be formed by using a PVD method, a CVD method, or the like. silicon nitride oxide, silicon nitride, hafnium oxide, aluminum oxide, tantalum oxide The interlayer insulating layer 146 can be formed using a material containing an inorganic insulating material such as silica. After that, it is desirable to flatten the surface by a method such as CMP or etching. It's nice.

[0137] Next, the electrode 1 is formed on the interlayer insulating layer 146, the protective insulating layer 144, and the gate insulating layer 138. 36a, electrode 136b, electrode 136c, source or drain electrode 142a, source An opening is formed so as to reach the electrode or drain electrode 142b, and a conductive layer is formed so as to be embedded in the opening. A conductive layer 148 is formed (see FIG. 5B). The opening is formed by etching using a mask or the like. The mask can be formed by a method such as exposure using a photomask. The etching can be wet etching or dry etching. However, from the viewpoint of fine processing, it is recommended to use dry etching. The conductive layer 148 is preferably formed by a film forming method such as a PVD method or a CVD method. Materials that can be used to form the conductive layer 148 include molybdenum, titanium, and the like. Tantalum, chromium, tantalum, tungsten, aluminum, copper, neodymium, scandium, etc. Examples include any conductive material, their alloys, and compounds (e.g., nitrides).

[0138] Specifically, for example, a thin titanium film is formed in the area including the opening by the PVD method, and then a CVD method is applied. After forming a thin titanium nitride film by this method, a tungsten film is formed so as to fill the opening. Here, the titanium film formed by the PVD method is Electrodes (here, electrode 136a, electrode 136b, electrode 136c, source electrode or drain electrode) The oxide film at the interface with the electrode 142a, the source electrode or the drain electrode 142b is reduced. The titanium nitride formed after that has the function of reducing the contact resistance with the external electrode. It has a barrier function that suppresses the diffusion of conductive materials. After forming the barrier film, a copper film may be formed by plating.

[0139] After the conductive layer 148 is formed, the conductive layer 148 is removed by etching, CMP, or other methods. A portion of the interlayer insulating layer 146 is removed to expose the electrodes 150a, 150b, and 150c. Electrode 150c, electrode 150d, and electrode 150e are formed (see FIG. 5(C)). 48 is removed to form electrodes 150a, 150b, 150c, 150d, and When forming 150e, it is desirable to process it so that the surface is flat. Next, an interlayer insulating layer 146, an electrode 150a, an electrode 150b, an electrode 150c, an electrode 150d, an electrode By flattening the surface of the electrode 150e, it is possible to obtain good electrodes, wiring, and insulation in the subsequent processes. It is possible to form a layer, a semiconductor layer, etc.

[0140] Furthermore, an insulating layer 152 is formed, and the electrodes 150a, 150b, and 150c are attached to the insulating layer 152. 50c, the electrode 150d, and the electrode 150e are formed, and the insulating layer 150 is embedded in the opening. After forming the conductive layer as shown above, a part of the conductive layer is removed by a method such as etching or CMP. , the insulating layer 152 is exposed, and the electrodes 154a, 154b, 154c, and 154 This step is the same as that for forming the electrodes 150a and the like. Therefore, I will omit the details.

[0141] When the transistor 162 is manufactured by the above method, the hydrogen concentration in the oxide semiconductor layer 140 is Degrees are 5 x 10 19 atoms / cm 3 and the off-current of the transistor 162 is is 1 x 10 -13 A or less. In this way, the hydrogen concentration is sufficiently reduced and the resulting product is highly purified. By using the oxide semiconductor layer 140, the transistor 162 can have excellent characteristics. In addition, a transistor 160 using a material other than an oxide semiconductor is provided in the lower portion, and A semiconductor device with excellent characteristics having a transistor 162 using an oxide semiconductor in a portion thereof is manufactured. It is possible.

[0142] In addition, examples of semiconductor materials that can be compared with oxide semiconductors include silicon carbide (e.g., 4H Oxide semiconductors and 4H-SiC have several things in common. The intrinsic carrier density of oxide semiconductors at room temperature is 10 -7 / cm 3 This is estimated to be about 6.7 × 10 in 4H-SiC. -11 / cm 3 and This is also an extremely low value. The intrinsic carrier density of silicon (1.4 × 10 10 / cm 3 Process When compared to the degree of

[0143] The energy band gap of oxide semiconductors is 3.0 to 3.5 eV, and 4H-S The energy band gap of iC is 3.26 eV, so it is called a wide-gap semiconductor. Oxide semiconductors and silicon carbide have in common this point as well.

[0144] On the other hand, there is a significant difference between oxide semiconductors and silicon carbide. The semiconductor process using silicon carbide requires, for example, 1000 s to activate the dopant. Since heat treatment at 500℃ to 2000℃ is required, it is different from semiconductor elements using other semiconductor materials. At such high temperatures, semiconductor substrates and semiconductor elements may be destroyed. On the other hand, oxide semiconductors are heated to temperatures between 300°C and 500°C (glass transition temperature It can be produced by heat treatment at a maximum temperature of about 700°C, and is comparable to other semiconductor materials. It is possible to form an integrated circuit using the oxide semiconductor and then form a semiconductor element using the oxide semiconductor. become.

[0145] In addition, unlike silicon carbide, it is possible to use a substrate with low heat resistance, such as a glass substrate. Furthermore, it has the advantage that it does not require high-temperature heat treatment, making it more energy efficient than silicon carbide. This has the advantage that the energy cost can be sufficiently reduced.

[0146] Although many studies have been conducted on the physical properties of oxide semiconductors, these studies have focused on the energy The present invention does not include the idea of sufficiently reducing the localized levels in the energy gap. In one embodiment, water or hydrogen that may cause localized levels is removed from an oxide semiconductor, This is because the localized level in the energy gap itself is This is based on the idea of sufficiently reducing the It allows for the production of industrial products.

[0147] When removing hydrogen and water, oxygen may also be removed at the same time. Therefore, oxygen is supplied to the dangling bonds of the metal that are generated due to oxygen deficiency, and the localization caused by oxygen vacancies By reducing the intrinsic level, a more highly purified (i-type) oxide semiconductor can be obtained. For example, an oxide film containing excess oxygen may be formed in close proximity to the channel formation region. By performing heat treatment at a temperature of 200 to 400°C, typically around 250°C, By supplying oxygen from the oxide film, it is possible to reduce localized levels due to oxygen defects.

[0148] The second heat treatment is followed by precipitation in an oxygen atmosphere or an atmosphere from which hydrogen and water have been sufficiently removed. Oxygen can also be supplied to the oxide semiconductor through a heating process.

[0149] Donors in oxide semiconductors are formed in shallow intermediate states 0.1 eV to 0.2 eV below the conduction band due to excess hydrogen. These defects are thought to be caused by the lack of oxygen and the deep levels due to the lack of oxygen. The technical idea of thoroughly removing hydrogen and providing sufficient oxygen to reduce the This is probably the case.

[0150] In addition, although oxide semiconductors are generally n-type, in one embodiment of the disclosed invention, In particular, the i-type is achieved by removing water and hydrogen. It is not an i-type product made by adding impurities, so it can be said to include a technological concept that has not been seen before. .

[0151] <Conduction mechanism of transistors using oxide semiconductors> Here, the conduction mechanism of a transistor using an oxide semiconductor will be explained with reference to FIGS. 6 to 9. In the following explanation, an ideal situation is assumed for ease of understanding. Not all of the information provided reflects the actual situation. It is noted that this is merely an inventive step and does not affect the validity of the invention.

[0152] FIG. 6 is a cross-sectional view of a transistor (thin film transistor) using an oxide semiconductor. An oxide semiconductor layer (OS) is provided on the gate electrode (GE1) via a gate insulating layer (GI). A source electrode (S) and a drain electrode (D) are provided thereon. An insulating layer is provided to cover the drain electrode (D).

[0153] FIG. 7 shows an energy band diagram (schematic diagram) in the cross section A-A' of FIG. The black circles (●) in 7 represent electrons, and the white circles (○) represent holes, each with a charge (-q, +q ) and a positive voltage (V D >0) is applied, and the dashed line indicates the gate voltage When no voltage is applied to the electrode (V G =0), the solid line indicates a positive voltage (V G >0) When no voltage is applied to the gate electrode, the high potential barrier This indicates an off state in which no carriers (electrons) are injected from the electrode to the oxide semiconductor, and no current flows. On the other hand, when a positive voltage is applied to the gate, the potential barrier decreases, and the on-state in which current flows is established. Indicates the state.

[0154] FIG. 8 shows an energy band diagram (schematic diagram) in the cross section taken along line BB' in FIG. FIG. 8(A) shows the gate electrode (GE1) with a positive voltage (V G >0) is a given state, This shows the on-state where carriers (electrons) flow between the source electrode and the drain electrode. FIG. 8B shows a case where a negative voltage (V G <0) is applied. This shows the case where the transistor is in the off state (a state in which minority carriers do not flow).

[0155] Figure 9 shows the relationship between the vacuum level and the work function (φ M ) and the electron affinity (χ) of the oxide semiconductor. show.

[0156] At room temperature, electrons in metals are degenerate, and the Fermi level is located within the conduction band. Conventional oxide semiconductors are n-type, and their Fermi level (E F ) is located in the center of the band gap The intrinsic Fermi level (E i ) and is located closer to the conduction band. It is known that some hydrogen atoms act as donors in semiconductors, which is one of the factors that cause them to become n-type. There are.

[0157] In contrast, an oxide semiconductor according to one embodiment of the disclosed invention can convert hydrogen, which is a factor in making the oxide semiconductor n-type, into an oxide. The oxide semiconductor is made of a material that contains as few impurity elements as possible, other than the main components of the oxide semiconductor. By purifying it to such a high level, it becomes genuine (type i) or is intended to become genuine. In other words, instead of adding impurity elements to make it i-type, impurities such as hydrogen and water are removed as much as possible. By doing so, it is possible to obtain a highly purified i-type (intrinsic semiconductor) or something close to it. This results in the Fermi level (E F ) is the intrinsic Fermi level (E i ) It is possible.

[0158] The band gap (E g ) is 3.15 eV, and the electron affinity (χ) is 4.3 V It is said that the work function of titanium (Ti) that constitutes the source and drain electrodes is is approximately equal to the electron affinity (χ) of the oxide semiconductor. In this case, In this case, no Schottky barrier is formed for electrons.

[0159] At this time, the electrons are transported between the gate insulating layer and the highly purified oxide semiconductor layer as shown in FIG. The electrons move near the interface with the oxide semiconductor (the lowest energetically stable part of the oxide semiconductor).

[0160] Also, as shown in FIG. 8B, when a negative potential is applied to the gate electrode (GE1), Since the number of holes, which are carriers, is substantially zero, the current is a value that is infinitely close to zero.

[0161] In this way, high purity oxide semiconductors are used to minimize the inclusion of elements (impurity elements) other than the main components of the oxide semiconductor. By this, the gate insulating layer becomes intrinsic (i-type) or substantially intrinsic. Therefore, the gate insulating layer must have a good interface with the oxide semiconductor. Specifically, for example, power frequencies from the VHF band to the microwave band are required. Insulating layers are produced by CVD using high-density plasma generated by a large number of processes, and by sputtering. It is preferable to use an insulating layer manufactured by a method such as the above.

[0162] The oxide semiconductor is highly purified while the interface between the oxide semiconductor and the gate insulating layer is improved. For example, the channel width (W) of a transistor can be reduced to 1×10 4 μm, channel length When (L) is 3 μm, 10 -13 Off-state current of less than A, sub- A threshold swing value (S value) (gate insulating layer thickness: 100 nm) can be achieved.

[0163] In this way, the oxide semiconductor is highly oxidized so that elements other than the main components (impurity elements) are not included as much as possible. Purification can improve the operation of the transistor.

[0164] <Modification> 10 to 13 show modified examples of the configuration of the semiconductor device. Therefore, a case where the configuration of the transistor 162 is different from that described above will be described. The configuration of register 160 is the same as above.

[0165] In FIG. 10, a gate electrode 136d is provided under the oxide semiconductor layer 140, and a source electrode or The drain electrode 142a and the source or drain electrode 142b are formed on the oxide semiconductor layer 1. The transistor 162 is configured to be in contact with the oxide semiconductor layer 140 on the lower surface of the transistor 162. The planar structure can be changed as needed to correspond to the cross section. Here, only the cross section will be shown.

[0166] The major difference between the configuration shown in FIG. 10 and the configuration shown in FIG. 2 is that the source electrode or drain electrode The electrode 142a and the source or drain electrode 142b are connected to the oxide semiconductor layer 140. That is, in the configuration shown in FIG. The source electrode or drain electrode 142a and the source electrode or drain electrode 142b 10, the lower surface of the oxide semiconductor layer 140 is in contact with the , the source electrode or drain electrode 142a, the source electrode or drain electrode 142b, Due to this difference in contact, the arrangement of other electrodes, insulating layers, etc. may differ. The details of each component are the same as in Figure 2.

[0167] Specifically, the semiconductor device includes a gate electrode 136d provided on the interlayer insulating layer 128, and a gate a gate insulating layer 138 provided on the gate electrode 136d; In addition, the source electrode or drain electrode 142a, the source electrode or drain electrode 142b, , on the source or drain electrode 142a, the source or drain electrode 142b and an oxide semiconductor layer 140 in contact with the side surface.

[0168] Here, the gate electrode 136d is embedded in the insulating layer 132 formed on the interlayer insulating layer 128. Similarly to the gate electrode 136d, the source electrode or The electrode 136a is in contact with the drain electrode 130a, and the source or drain electrode 130b Electrode 136b is formed in contact with electrode 130c, and electrode 136c is formed in contact with electrode 130c. do.

[0169] In addition, a protective film is formed on the transistor 162 so as to be in contact with part of the oxide semiconductor layer 140. An insulating layer 144 is provided, and an interlayer insulating layer 146 is provided on the protective insulating layer 144. Here, the protective insulating layer 144 and the interlayer insulating layer 146 are provided with a source electrode or a drain electrode. An opening is provided that reaches the source electrode 142a and the source or drain electrode 142b. Through the openings, the electrodes 150d and 150e are connected to the source and drain electrodes. The electrode 142a is formed in contact with the source electrode or the drain electrode 142b. As well as electrodes 150d and 150e, gate insulating layer 138, protective insulating layer 144, interlayer insulating layer The electrodes 136a, 136b, and 136c are in contact with each other through openings provided in the layer 146. Electrodes 150a, 150b, and 150c are formed.

[0170] An insulating layer 152 is provided on the interlayer insulating layer 146, and a buried insulating layer 152 is provided on the insulating layer 152. Electrodes 154a, 154b, 154c, and 154d are provided so that the electrodes are embedded in the Here, electrode 154a is in contact with electrode 150a, and electrode 154b is in contact with electrode 150a. b, electrode 154c is in contact with electrode 150c and electrode 150d, and electrode 1 54d is in contact with electrode 150e.

[0171] FIG. 11 shows an example of a configuration in which a gate electrode 136d is provided on an oxide semiconductor layer 140. FIG. 11(A) shows the source or drain electrode 142a and the source or drain electrode 142b. The drain electrode 142b is connected to the lower surface of the oxide semiconductor layer 140. 11B shows an example of a structure in which the source electrode or drain electrode 142a and The source electrode or drain electrode 142b is formed on the upper surface of the oxide semiconductor layer 140. 10. This is an example of a configuration in contact with the oxide semiconductor layer 140.

[0172] 11. The major difference between the configurations shown in FIGS. 2 and 10 and the configuration shown in FIG. 11 is that the oxide semiconductor layer 140 11(A) and 11(B). ) is that the source electrode or drain electrode 142a and the source electrode Alternatively, the drain electrode 142b may be formed on either the lower surface or the upper surface of the oxide semiconductor layer 140. And due to these differences, other electrical The arrangement of the electrodes, insulating layers, etc. is different. The details of each component are the same as in Figure 2. is.

[0173] Specifically, the semiconductor device shown in FIG. 11A has a source a source or drain electrode 142a, a source or drain electrode 142b, and a source electrode The upper surfaces of the source or drain electrodes 142a and 142b are connected to the electrodes. and a gate insulating layer 138 provided on the oxide semiconductor layer 140. and a gate electrode 136d on the gate insulating layer 138 in a region overlapping with the oxide semiconductor layer 140. and,

[0174] 11B, the semiconductor device shown in FIG. 11B is a semiconductor device including an oxide semiconductor layer formed over an interlayer insulating layer 128. a source electrode or a gate electrode provided in contact with the upper surface of the oxide semiconductor layer 140; The drain electrode 142a, the source or drain electrode 142b, and the oxide semiconductor layer 1 40, source electrode or drain electrode 142a, and source electrode or drain electrode The gate insulating layer 138 provided on the gate insulating layer 142b and the oxide semiconductor layer on the gate insulating layer 138 and a gate electrode 136d in an area overlapping with 140.

[0175] In the configuration shown in FIG. 11, compared to the configuration shown in FIG. 2, some components can be omitted. In this case, the manufacturing process can be simplified. Of course, this is not essential in the configuration shown in Figure 2, etc. It goes without saying that some components can be omitted.

[0176] FIG. 12 shows a case where the size of the element is relatively large, and a gate electrode is provided under the oxide semiconductor layer 140. In this case, the flatness of the surface and the coverage are important. Since the requirements are relatively mild, wiring and electrodes are formed by embedding them in the insulating layer. For example, the gate electrode 13 can be formed by patterning the conductive layer after it is formed. Although not shown here, it is possible to form the transistor 16 0 can also be produced in the same way.

[0177] The major difference between the configuration shown in FIG. 12(A) and the configuration shown in FIG. 12(B) is that the source electrode or The drain electrode 142a and the source or drain electrode 142b are formed on the oxide semiconductor layer 1. 40. Due to these differences, the arrangement of other electrodes, insulating layers, etc. also differs. The details of each component are the same as those in FIG. 2 and the like.

[0178] Specifically, the semiconductor device shown in FIG. 12A has a gate insulating film formed on an interlayer insulating layer 128. an electrode 136d, a gate insulating layer 138 provided on the gate electrode 136d, and a gate insulating layer A source or drain electrode 142a, a source or drain electrode, is provided on the layer 138. A drain electrode 142b and a source or drain electrode 142a and a source or drain electrode and an oxide semiconductor layer 140 in contact with the upper surface of the inner electrode 142b.

[0179] 12B, the semiconductor device shown in FIG. 12B has a gate electrode 1 provided on an interlayer insulating layer 128. 36d, a gate insulating layer 138 provided on the gate electrode 136d, and a gate insulating layer 13 an oxide semiconductor layer 140 provided in a region overlapping with the gate electrode 136d on the oxide semiconductor layer 140; A source electrode or drain electrode 14 is provided in contact with the upper surface of the semiconductor layer 140. 2a and a source or drain electrode 142b.

[0180] In addition, in the configuration shown in FIG. 12, compared to the configuration shown in FIG. 2, some components can be omitted. In this case, too, the effect of simplifying the manufacturing process can be obtained.

[0181] FIG. 13 shows a case where the size of the element is relatively large, in which a gate electrode is formed on the oxide semiconductor layer 140. In this case, too, the flatness of the surface and the coverage are important. Since the requirements for this are relatively low, it is possible to embed wiring and electrodes in the insulating layer. For example, by performing patterning after forming the conductive layer, the gate electrode Although not shown here, it is possible to form a transistor 136d. 160 can also be produced in the same manner.

[0182] The major difference between the configuration shown in FIG. 13(A) and the configuration shown in FIG. 13(B) is that the source electrode or The drain electrode 142a and the source or drain electrode 142b are formed on the oxide semiconductor layer 1. 40. Due to these differences, the arrangement of other electrodes, insulating layers, etc. also differs. The details of each component are the same as those in FIG. 2 and the like.

[0183] Specifically, the semiconductor device shown in FIG. 13A has a source a source or drain electrode 142a, a source or drain electrode 142b, and a source electrode The upper surfaces of the source or drain electrodes 142a and 142b are connected to the electrodes. The oxide semiconductor layer 140, the source electrode or drain electrode 142a, and the a drain electrode 142b, a gate insulating layer 138 provided on the oxide semiconductor layer 140, A gate electrode 1 is provided on the gate insulating layer 138 in a region overlapping with the oxide semiconductor layer 140. 36d and has.

[0184] 13B, the semiconductor device shown in FIG. 13B is an oxide semiconductor film formed on an interlayer insulating layer 128. a source electrode or a gate electrode provided in contact with the upper surface of the oxide semiconductor layer 140; The drain electrode 142a, the source or drain electrode 142b, and the source or The drain electrode 142a, the source or drain electrode 142b, and the oxide semiconductor layer 140 a gate insulating layer 138 provided thereon; and an oxide semiconductor layer 140 on the gate insulating layer 138. and a gate electrode 136d provided in the overlapping region.

[0185] In addition, in the configuration shown in FIG. 13, compared to the configuration shown in FIG. 2, some components can be omitted. In this case, too, the effect of simplifying the manufacturing process can be obtained.

[0186] As described above, one embodiment of the disclosed invention realizes a semiconductor device with a novel structure. In this embodiment, the transistor 160 and the transistor 162 are stacked. However, the configuration of the semiconductor device is not limited to this example. In this configuration, the channel lengths of the transistors 160 and 162 are perpendicular to each other. The positional relationship between the transistor 160 and the transistor 162 is the same as in the above example. Furthermore, the transistor 160 and the transistor 162 may be overlapped. It may be provided.

[0187] For ease of understanding, the present embodiment will be described with reference to a semiconductor device with a minimum storage unit (1 bit). However, the configuration of the semiconductor device is not limited to this. By appropriately connecting the components, it is possible to construct a more advanced semiconductor device. By using multiple devices, it is possible to configure a NAND or NOR type semiconductor device. The configuration is not limited to that shown in FIG. 1 and can be modified as appropriate.

[0188] The semiconductor device according to this embodiment has a very low off-state current due to the low off-state current of the transistor 162. It is possible to retain information for a long time. No refresh operation is required, which reduces power consumption. It can be used as a non-volatile memory device.

[0189] In addition, since information is written by the switching operation of the transistor 162, It does not require high voltage and does not have the problem of element degradation. Therefore, since information can be written and erased, high-speed operation can be easily realized. This means that there is no need to erase the information required in flash memory, etc. There are also benefits to this.

[0190] In addition, a transistor using a material other than an oxide semiconductor is Compared to the conventional memory, it can operate at a higher speed, so by using it, the contents of the memory can be It is possible to perform reading at high speed.

[0191] The structures, methods, and the like described in this embodiment may be combined as appropriate with the structures, methods, and the like described in other embodiments. They can be used in combination.

[0192] (Embodiment 2) In this embodiment, a circuit configuration and operation of a semiconductor device according to one embodiment of the present invention will be described. do.

[0193] FIG. 14 shows an example of a circuit diagram of a semiconductor device (hereinafter also referred to as a memory cell). The memory cell 200 is connected to a source line SL, a bit line BL, a first signal line S1, and a second signal line S2. S2, word line WL, transistor 201, transistor 202, and transistor The transistor 201 and the transistor 203 are made of an oxide The transistor 201 is formed using a material other than a semiconductor, and the transistor 202 is formed using an oxide semiconductor. It is formed.

[0194] Here, the gate electrode of the transistor 201 and the source electrode or drain of the transistor 202 are The source line SL is electrically connected to one of the drain electrodes of the transistor. The source electrode of the transistor 201 is electrically connected to the drain electrode of the transistor 201. The source electrode of the transistor 203 is electrically connected to the bit line BL. The drain electrode of the transistor 203 is electrically connected to the first signal line S1. The other of the source electrode and the drain electrode of the transistor 202 is electrically connected to the second signal line. The word line S2 and the gate electrode of the transistor 202 are electrically connected to each other. , and is electrically connected to the gate electrode of the transistor 203 .

[0195] FIG. 15 shows an example of the write circuit 211. The first signal line S1 is connected to the write The switch is electrically connected to the write potential Vwrite or Vs1_0. It is controlled by signals Φw1 and Φw2.

[0196] FIG. 16 shows an example of the read circuit 212. The read circuit 212 includes a sense amplifier circuit. The read circuit 212 is electrically connected to the bit line BL. It is connected to one terminal of resistor R via a switch. The other terminal of resistor R is connected to Vdd. The resistance ratio between the resistor R and the load connected to the bit line BL is determined. The potential Vin is input to one of the input terminals of the sense amplifier circuit. One of the input terminals of the circuit is connected to the bit line BL via a switch or the like, and the potential Vin is also called the bit line potential. The resistor R is not limited to a resistive element, but can be any resistor that effectively functions as a resistor. Often, transistors are diode-connected, or the gate electrode is controlled by another signal. The input terminal of the sense amplifier circuit may be a transistor or other circuit. The other terminal of the bit line BL is connected to a read potential Vread. The switch is connected to the potential VBL_0 via the signals Φr1 and Φr2. Therefore, it is controlled.

[0197] Next, the write and read operations of the memory cell 200 shown in FIG. The memory cell 200 operates in response to the charge or potential stored at node A. The effective resistance of the transistor changes, so it can assume various states. Since the off-current of the capacitor 202 is extremely small or substantially zero, the charge on node A, Alternatively, the potential is maintained for a long time. This refers to transferring the memory cell to a specified state by charging or discharging node A of the memory cell. Reading means comparing the potential determined according to the state of the memory cell with a predetermined potential. Depending on the context, the words "write" and "read" can also mean the following: Data writing refers to a series of operations for writing predetermined data into a memory cell. Or, data reading refers to a series of operations for reading data stored in a memory cell. cormorant.

[0198] When writing to the memory cell 200, the source line SL is set to 0V and the word line WL is set to 0V. The second signal line S2 is set to Vdd to turn on the transistor 203. The read circuit 212 connected to the bit line BL outputs a signal Φr2 to the As a result, the bit line B A potential VBL_0 is applied to the write circuit 211 connected to the first signal line S1. Then, the signal Φw2 is deasserted and the signal Φw1 is asserted, resulting in a write state. As a result, a write potential Vwrite corresponding to the data to be written is applied to the first signal line. When writing is completed, the potential of the second signal line S1 is changed before the potential of the first signal line S2 is changed. 2 is set to 0V, turning off transistor 202.

[0199] As a result, a charge corresponding to the potential Vwrite of the first signal line is accumulated at node A, and the data The off-state current of the transistor 202 is extremely small, or Since the potential of the gate electrode of the transistor 201 is substantially 0, the potential of the gate electrode of the transistor 201 is maintained for a long time. It will be held.

[0200] When reading from the memory cell 200, the source line SL is set to 0V and the word line WL is set to Vd d, the transistor 203 is turned on, and the second signal line S2 is set to 0V. The write circuit 211 connected to the first signal line S1 outputs a signal Φw As a result, VS1_0 is applied to the first signal line. The read circuit 212 connected to the bit line BL deasserts the signal Φr2. The signal Φr1 is asserted to set the read operation state.

[0201] As a result, depending on the state of node A of memory cell 200, the transistor of memory cell 200 The effective resistance value of the transistor 201 is determined by the read circuit 212. A potential Vin (bit line potential Vin) determined according to the effective resistance value of the resistor 201; Reading is performed by comparing the read potential Vread.

[0202] The bit line potential Vin (potential Vin) to be compared during reading includes the This includes the potential of the node at the input terminal of the sense amplifier circuit connected to the bit line via a switch or the like. In other words, the potential compared in the read circuit is strictly the potential of the bit line. It does not need to be the same as

[0203] Next, a write operation according to one embodiment of the present invention will be described. As shown in FIG. 17, the first write (write for obtaining variation information) (reading to obtain variation information), the second write (reading to obtain the data to be stored) Each step is explained below.

[0204] The first write is for the purpose of initializing the memory cell and writing the memory cell to a predetermined state. Specifically, Vwi (initialization potential) is used as the write potential Vwrite, and The write operation is performed.

[0205] The first read is intended to obtain variation information of the memory cell. The threshold voltage of the transistor 201 varies depending on the memory cell, and for example, has a distribution as shown in FIG. 18(A). has the distribution shown.

[0206] As a result, when the above-described read operation is performed after the first write, the potential Vin of the node at the input terminal of the sense amplifier circuit (or the potential of the bit line BL), which is determined according to the effective resistance value of the memory cell, also varies depending on the memory cell, and for example, has a distribution as shown in FIG. 18(B). has the distribution shown. Therefore, in the first read, in order to acquire the variation information of the memory cell, a detailed read of the potential Vin of the bit line BL related to the read is performed. Specifically, a comparison between Vin and Vri_j is made using a potential Vri_j selected from a plurality of potentials Vri_0 to Vri_m (m is an integer greater than 0), where Vri_j is given as the read potential Vread applied to the sense amplifier circuit in the read circuit 212, and j is an integer less than or equal to m and greater than or equal to 0. This comparison is performed multiple times by changing j in Vri_j. As a result, it is determined which interval (the interval delimited by Vri_j and Vri_(j + 1)) the potential Vin of the bit line related to the read belongs to. has the distribution shown.

[0207] Each of the plurality of potentials Vri_j (j is an integer from 0 to m) is determined so that Vri_j < Vin < Vri_(j + 1) in a memory cell where the threshold voltage Vth of the transistor 201 satisfies V0 + j×ΔVth < Vth < V0 + (j + 1)×ΔVth. Among the intervals delimited by V0 + j×ΔVth (j is an integer from 0 to m), the interval delimited by V0 + i×ΔVth and V0 + (i + 1)×ΔVth is referred to as interval i (i is an integer greater than or equal to 0). Therefore, in the first read, in order to acquire the variation information of the memory cell, a detailed read of the potential Vin of the bit line BL related to the read is performed. Specifically, a comparison between Vin and Vri_j is made using a potential Vri_j selected from a plurality of potentials Vri_0 to Vri_m (m is an integer greater than 0), where Vri_j is given as the read potential Vread applied to the sense amplifier circuit in the read circuit 212, and j is an integer less than or equal to m and greater than or equal to 0. This comparison is performed multiple times by changing j in Vri_j. As a result, it is determined which interval (the interval delimited by Vri_j and Vri_(j + 1)) the potential Vin of the bit line related to the read belongs to. 2 in the sense amplifier circuit in the read circuit 21 0 to Vri_m (m is an integer greater than 0), and the comparison between Vin and Vri_j is performed. This comparison is performed multiple times by changing j in Vri_j. As a result, it is determined which interval (the interval delimited by Vri_j and Vri_(j + 1)) the potential Vin of the bit line related to the read belongs to. At Vri_j is changed, and the comparison is performed multiple times. As a result, it is determined which interval (the interval delimited by Vri_j and Vri_(j + 1)) the potential Vin of the bit line related to the read belongs to. delimited by Vri_j and Vri_(j + 1)) belongs to.

[0208] Each of the plurality of potentials Vri_j (j is an integer from 0 to m) is determined so that, for example, in a memory cell where the threshold voltage Vth of the transistor 201 satisfies V0 + j×ΔVth < Vth < V0 + (j + 1)×ΔVth, Vri_j < Vin < Vri_(j + 1). is determined so that Vri_j < Vin < Vri_(j + 1). Among the intervals delimited by V0 + j×ΔVth (j is an integer from 0 to m), the interval delimited by V0 + i×ΔVth and V0 + (i + 1)×ΔVth is interval i (i is an integer greater than or equal to 0). Vri_j that satisfies this is called, for example, It can be determined through simulation and experiment.

[0209] V0, m, ΔVth are the threshold voltages of the transistor 201 of a normal memory cell. , is determined so as to be included in the range of V0 to V0+(m+1)×ΔVth. ΔVth is ΔVth is the amount that determines the distribution width of the memory cell state after writing. The distribution of memory cell states after writing is narrower. It is determined taking into consideration "n" and power supply potential, etc.

[0210] The variation in Vri is mainly due to the variation in Vth of the transistor 201. In other words, even if the Vth of the transistor 201 is fixed, The potential Vin is still considered to have a narrow distribution. For example, Vri_j may be set to a representative value of the distribution of Vri_j.

[0211] In the first readout, a plurality of potentials Vri_0 to Vri_m (m is an integer greater than 0) A method of making a multiple comparison using multiple potentials Vri_1 to Vri_2 will be described below with an example. Vri_(m-1) is compared m-1 times in order. It is possible to determine which section the threshold voltage Vth of 1 belongs to.

[0212] In addition, as shown in Figure 19, a method is adopted in which the comparison results are fed back and compared repeatedly. It is also possible to use Figure 19 to compare the memory size three times for the case of m=8. A method for determining which section the threshold voltage Vth of the transistor 201 of the memory cell belongs to Explain the law.

[0213] First, as the read potential Vread, a potential near the center of the plurality of potentials Vri_0 to Vri_8 is set. The potential Vri_4 is used to perform a first comparison with the potential Vin. As a result of the comparison, the output of the sense amplifier circuit is "0" (SA_OUT="0"), that is, the potential Vi When n<potential Vri_4, the potential is near the center of the multiple potentials Vri_1 to Vri_4. The potential Vri_2 is read as the potential Vread and compared with the potential Vin for the second time. Also, when the output of the sense amplifier circuit is "1" (SA_OUT="1"), that is, the potential Vin In the case of potential Vri_4, it is a potential near the center of the multiple potentials Vri_4 to Vri_7. The potential Vri_6 is used as the read potential Vread and is compared with the potential Vin for the second time.

[0214] The potential Vri_2 is set as the read potential Vread. As a result of the comparison, SA_OUT="0", That is, when the potential Vin is smaller than the potential Vri_2, the potential Vri_1 is read out and set to the potential Vread. Similarly, SA_OUT="1", that is, the potential Vin is compared with SA_OUT for the third time. When Vin>Vri_2, the potential Vri_3 is set as the read potential Vread, and the potential Similarly, the potential Vri_6 is compared with Vin for the third time. As a result of the comparison, if SA_OUT="0", that is, if the potential Vin is less than the potential Vri_6, Vri_5 is set as the read potential Vread and compared with the potential Vin for the third time. If SA_OUT="1", that is, if the potential Vin is greater than the potential Vri_6, then the potential Vri_7 is set as the read potential Vread and compared with the potential Vin for the third time.

[0215] As a result of the third comparison, if the potential Vin is less than the potential Vri_1, the transistor 2 of the memory cell The threshold voltage Vth of 01 can be determined to belong to section 0. If the potential Vin is greater than the potential Vri_1, the section is set to section 1. If the potential Vin is less than the potential Vri_3, the section is set to section 2. If the potential Vin is greater than the potential Vri_3, the section 3 is selected; if the potential Vin is less than the potential Vri_5, the section 4 is selected; If the potential Vin is greater than the potential Vri_5, the section 5 is selected; if the potential Vin is less than the potential Vri_7, the section 6 is selected; If the potential Vin is greater than the potential Vri_7, the threshold voltage of the transistor 201 of the memory cell is in the section 7. As described above, the comparison result is fed back. By repeatedly comparing the intervals, M Even in the case of individual items, the number of comparisons is reduced to M. The readout can be performed with reduced power consumption.

[0216] When multiple comparisons are performed in the first read, the bit Since no charging or discharging of the lines is involved, high-speed readout is possible.

[0217] In the first readout, a plurality of potentials VVri_0 to Vri_m (m is greater than 0) are set. As a comparison method using a small integer, an example of multiple comparisons was explained. Specifically, the read circuit has m-1 sense amplifier circuits. Just set it up.

[0218] Next, in the second write (writing of data to be stored), the desired data is written to the memory cell. The data to be written is n values of "0", "1", ... "n-1". In addition, the threshold voltage of the transistor 201 of the memory cell is the typical value Vth_typ. The write potential when writing data "i" (i=an integer from 0 to n) to the memory cell is set to Vw_i.

[0219] In the second write, when writing data “i” to a memory cell, it is determined which division the memory cell is in. Write is performed using a write potential that is corrected based on whether the write potential falls within the range. The section including the representative value Vth_typ of the threshold voltage of the resistor 201 is defined as section i0. Then, the correction voltage in the section i0+k (k is an integer between -i0 and m-1-i0) is k×ΔVth. Table 1 shows the threshold voltage ranges of the transistor 201. The voltage and the correction voltage are shown.

[0220] [Table 1]

[0221] For example, in section i0, the correction voltage is 0, and in the adjacent section which is larger than section i0 by ΔVth, the correction voltage is The voltage is ΔVth, and in the adjacent section that is ΔVth smaller than section i0, the correction voltage is -ΔV If the memory cell belongs to the section (i0+k), the corrected write voltage is Write is performed using Vw_i+k×ΔVth, which is the value.

[0222] By performing such writing, it is possible to narrow the distribution of states after writing. As a result, it is possible to improve the degree of multi-value. In the verify operation, the data is written and read once at the first time, so it is different from the conventional verify write. This allows for faster writes compared to repeating write and read operations multiple times. It is possible.

[0223] Figure 20 shows the data when no correction is performed (i.e., when all correction voltages are set to 0V). An example of the data after writing (Fig. 20(A)) and an example of the data after writing when correction is performed (Fig. 20(B)) In FIG. 20(A), the write potential is independent of the memory cell. The state after writing is constant, and the distribution of the threshold voltage of the transistor 201 is similar to that of the transistor 201. As a result, for example, a memory cell can only store four or fewer states. On the other hand, in FIG. 20B, the write potential is corrected for each memory cell, so The latter state has a narrow distribution of about ΔVth. As a result, for example, the memory cell has 16 values The state can be stored.

[0224] Next, regarding a read operation (a read operation of stored data) according to one embodiment of the present invention, explain.

[0225] To read out n values of "0", "1", ... "n-1" as data, A plurality of potentials Vr_j to Vr_n-2 (n-2 is an integer greater than 0) as the potential Vread A potential Vr_j (j=an integer from 0 to n-2) selected from the above is used to make multiple comparisons. The read potential Vr_j is the value of the potential Vin when the memory cell of data "j" is read. When the memory cell of data "j+1" is read, the potential Vin is set to a value between the values of Vin and Vin. I decide to go with sea urchin.

[0226] Multiple comparisons using multiple potentials Vr_j to Vr_n-2 (n-2 is an integer greater than 0) A method for performing this will be described below with an example. For example, a plurality of potentials Vr_j (j=an integer from 0 to n-2) ) are compared n-1 times in order, the state of the memory cell becomes data "0", "1", ... In addition, the first read operation can determine which state of “n” the memory cell is in. It is also possible to use a method similar to that described using 9. Furthermore, by providing n-1 sense amplifier circuits, it is possible to read data in one comparison. It is also possible to read it out by

[0227] An example of a specific operating voltage (potential) is shown in Table 2. For example, if the degree of multi-value is n=16 and the power supply voltage is The voltage level is Vdd=2V, and the typical value of the threshold voltage of transistor 201 is Vth_typ=0. 3V, the section width of the threshold voltage of the transistor 201 is ΔVth=0.04V, The number of sections of the threshold voltage of the capacitor 201 and the number of sections of the read potential Vin of the first read operation The number of periods is m=8, and the write potential of the first write operation is Vwi=0.98V. .

[0228] [Table 2]

[0229] The correction voltages corresponding to the ranges of the threshold voltage of the transistor 201 are shown in Table 3. The value is set as read potentials Vri_0 to Vri_8 (i=an integer from 0 to 8) for the first read. ) are the values shown in Table 4, and the pre-correction write potentials Vw_0 to Vw_15 (i= The value shown in Table 5 is used as the read potential V The values shown in Table 6 can be used for r_0 to Vr_14. By using this, write and read operations can be performed at a potential of Vdd=2V or less. can be done.

[0230] [Table 3]

[0231] [Table 4]

[0232] [Table 5]

[0233] [Table 6]

[0234] As described above, the writing in one aspect of the present invention is the first writing (for obtaining variation information). write), first read (read to obtain variation information), second write (Writing data to be stored) By performing the second write, the variation information of the memory cell is obtained. The specified data is written to the memory using a write voltage corrected based on the variation information of the memory cells. As a result, the distribution of states after writing is narrowed. This makes it possible to:

[0235] FIG. 21 shows a semiconductor device according to one embodiment of the present invention having a kr×(kc×kw) memory cell array. For example, if the degree of multi-value is n=4, the memory capacity is The amount is 2 × kr × (kc × kw) bits, and if n = 16, the memory capacity is 4 × kr × (kc × kw) bits. Generally, n=2 k (k is an integer greater than or equal to 1), then the binary case is In comparison, the memory capacity is k times larger.

[0236] The semiconductor device shown in FIG. 21 has kr word lines WL and second signal lines S2, and kc×kw The bit lines BL(1_1) to BL(kw_kc) and the first signal lines S1(1_1) to S1( kw_kc) and a plurality of memory cells 200(1, 1) to 200(kr, kw_kc) are arranged vertically. A matrix of kr (rows) x (kc x kw) (columns) (kr, kc, kw are natural numbers) a memory cell array 210 arranged in a row, a read circuit 212, a write circuit 211, and a multiplexer 219, a driver circuit 213 for the second signal lines and word lines, a column decoder 21 4, address buffer 215, data buffer 218, potential generating circuit 217, control circuit 2 16. Other peripheral circuits include a refresh circuit, etc. where kc is the number of columns that can be independently selected by the column decoder 214, kw is the number of columns that are selected simultaneously.

[0237] The memory cell 200 can use the circuit shown in FIG. Consider a memory cell 200(i, j), where i is an integer between 1 and kr, and j is kc×kw (an integer between 1 and kc×kw) is the bit line BL(j), the first signal line S1(j), the word The line WL(i) and the second signal line S2(i) are connected to the source wiring, respectively. The bit lines BL(1_1) to BL(kw_kc) and the first signal lines S1(1_1) to S1(k w_kc) are connected to the multiplexer 219. r) and second signal lines S2(1) to S2(kr) are connected to the word line and second signal line drive circuit 21. 3 are connected to each other.

[0238] Next, each circuit will be explained. The write circuit 211 and the read circuit 212 are respectively The circuits shown in Figures 15 and 16 can be used.

[0239] The multiplexer 219 receives the output signal of the column decoder 214 as a control signal and outputs the kc A bit line selected from the bit lines kc is connected to the read circuit 212. One of the control signals is asserted, and the bit controlled by the asserted control signal is The multiplexer 219 also connects the kc first signal lines S1 to BL_S. The first signal line selected from the kc control lines is connected to the write circuit 211. When one of the signals is asserted, the first signal line controlled by the asserted control signal is Connect to the S1_S line.

[0240] The column decoder 214 receives the column address output from the address buffer 215 and the control circuit 2 The control signal output from 16 is used as an input signal, and one output signal specified by the address is used as an address. asserts one output signal and deasserts the other output signal.

[0241] In the case of a semiconductor device with a configuration of kc=1, the column decoder 214 and the multiplexer In this case, the write circuit 211 and the first signal line S1 are directly connected. Then, the read circuit 212 and the bit line BL can be directly connected.

[0242] The second signal line and word line driver circuit 213 receives the row address output from the address buffer 215. The address and the control signal output from the control circuit 216 are used as input signals. The word lines and second signal lines that correspond to the word lines and the second signal lines are supplied with predetermined potentials, respectively. is applied.

[0243] The potential generating circuit 217 generates a write potential in accordance with the control signal output from the control circuit 216. Vwrite, read potential Vread, VBL_0, VS1_0, etc. are output. The write potential Vwrite is Vwi in the first write operation and Vwrite in the second write operation. The write potential (Vw_j(j=0 The read potential Vread is V In the first read operation, any one of the potentials Vri_r_j (j=an integer from 0 to n-2) is set to Vri_r_j. j (j=integer from 0 to m+1) is output. These potentials are It is specified by the output signal. For example, a digital signal representing the voltage level output from the control circuit. The device may have a digital-to-analog converter (DAC) that receives the signal as an input signal.

[0244] The potential generating circuit 217 generates a plurality of write potentials Vwrite and a plurality of read potentials Vwrite. For example, if there are multiple write circuits 211, If different potentials need to be written to each, multiple write potentials Vwrite can be used. Therefore, an appropriate potential can be supplied to each of the write circuits 211. For example, in the case where there are a plurality of read circuits 212, the comparison results are fed as shown in FIG. When the method of repeatedly comparing the read potential Vread is used, Thus, an appropriate potential can be supplied to each read circuit 212.

[0245] The address buffer 215 receives address signals input to the semiconductor device and signals output from the control signal circuit. The control signal is used as an input signal, and a predetermined column address is selected at a predetermined timing according to the control signal. The address register may be included.

[0246] The data buffer 218 receives the Din signal input to the semiconductor device and the data from the read circuit 212. and a control signal output from the control circuit 216 as input signals. 1, the Dout signal output from the semiconductor device, and the signal input to the control circuit 216 The data buffer 218 has a data register and outputs a signal according to the control signal. The control circuit 216 stores various input signals in the data register at a predetermined timing. The input output signal is used to select the write potential Vwrite or the read potential Vread. These signals are necessary for writing data to memory cells and reading data from memory cells. be.

[0247] The control circuit 216 controls signals such as WE, RE, CLK, etc. input to the semiconductor device and data buffers. The output signal from the address buffer 215 is used as an input signal. , a data buffer 218, a column decoder 214, a second signal line and word line driver circuit 213 The control signals are used to control data write and read operations. It is a control signal that contains information such as timing control signals for execution and potentials to be used. In the second write operation, the write potential is corrected based on the information on the write potential and the information on the correction voltage. The control circuit 216 generates and outputs information on the write potential. It may have a ROM for generating corrected write potential information from voltage information. For example, the write potential information is 4 bits, the correction voltage information is 3 bits, and the corrected write If the write potential is expressed in 6 bits, an 8 kbit ROM may be provided. A calculation is performed to generate corrected write potential information from the write potential information and the correction voltage information. The control circuit may include a calculation circuit.

[0248] In this embodiment, the read potential Vread is generated by the potential generating circuit 217. However, the read potential Vread can be generated by other configurations. For example, a reference circuit having the same configuration as the memory cell and the circuit that generates Vin is provided, and the By controlling the potential of node A of the memory cell, Vread can be generated. Although the read circuit 212 has one sense amplifier circuit, it may have multiple sense amplifier circuits. The read circuit 212 may have a plurality of sense amplifier circuits. By doing so, it is possible to reduce the number of read operations.

[0249] The semiconductor device according to this embodiment has an extremely low off-state current due to the low off-state current of the transistor 202. It is possible to retain information for a long time. No refresh operation is required, which reduces power consumption. It can be used as a non-volatile memory device.

[0250] In addition, since information is written by the switching operation of the transistor 202, It does not require high voltage and does not have the problem of element degradation. Therefore, since information can be written and erased, high-speed operation can be easily realized. By controlling the potential input to the transistor, data can be directly rewritten. This eliminates the need for the erase operation required in flash memories and the like. This can suppress the decrease in operating speed caused by the operation.

[0251] In addition, transistors using materials other than oxide semiconductors are called transistors using oxide semiconductors. Compared to conventional memory controllers, it is possible to operate at higher speeds, so by using this, it is possible to read and write the stored contents. It is possible to perform reading at high speed.

[0252] In addition, since the semiconductor device according to this embodiment is a multi-value type, it is possible to increase the storage capacity per area. Therefore, it is possible to achieve miniaturization and high integration of the semiconductor device.

[0253] As described above, the variation information of the memory cells is acquired, and the write voltage is set according to the variation information. By writing a value to the memory cell, the distribution of the memory cell state after writing is narrowed. As a result, it is possible to improve the degree of multi-value. In the write operation, the potential of the floating node can be directly controlled. Therefore, the three-step write process is: first write, first read, and second write. This operation allows for highly accurate threshold voltage control. Faster than writing and reading multiple times in a write operation. Writing can be achieved.

[0254] (Embodiment 3) In this embodiment, an example of an electronic device equipped with the semiconductor device obtained in the above embodiment will be described. The semiconductor device obtained in the above embodiment is a semiconductor device that does not require power supply. Even if the data is written or erased, it is possible to retain the data. Furthermore, the operation is also fast. Therefore, it is possible to use this semiconductor device to develop new electrical circuits. It is possible to provide a sub-device. The semiconductor device is then mounted on a circuit board or the like and installed inside various electronic devices.

[0255] FIG. 22A shows a notebook personal computer including the semiconductor device according to the above embodiment. The computer is composed of a main body 301, a housing 302, a display unit 303, a keyboard 304, etc. The semiconductor device according to one embodiment of the present invention is implemented in a notebook personal computer. By applying this technology, it is possible to retain information even when there is no power supply. There is no deterioration due to writing and erasing. Furthermore, the operation is fast. The semiconductor device according to the present invention is preferably applied to a notebook personal computer. is.

[0256] FIG. 22B shows a personal digital assistant (PDA) including the semiconductor device according to the above embodiment. The main body 311 includes a display unit 313, an external interface 315, an operation button 314, etc. The stylus 312 is also provided as an accessory for operation. By applying the semiconductor device according to the present invention to a PDA, information can be retained even when there is no power supply. In addition, there is no deterioration due to writing and erasing. Therefore, it is preferable to apply the semiconductor device according to one aspect of the present invention to a PDA. is.

[0257] FIG. 22C shows an example of electronic paper including the semiconductor device according to the above embodiment. The electronic book 320 is shown. The electronic book 320 is made up of two housings, housing 321 and housing 323. The housing 321 and the housing 323 are integrated by a shaft portion 337. The opening and closing operation can be performed around the axis 337. The semiconductor device 320 can be used like a paper book. By applying this technology to electronic paper, it is possible to retain information even when there is no power supply. In addition, there is no deterioration due to writing and erasing. Furthermore, the operation is fast. For this reason, it is preferable to apply a semiconductor device according to one embodiment of the present invention to electronic paper. do.

[0258] The housing 321 incorporates a display unit 325, and the housing 323 incorporates a display unit 327. The display unit 325 and the display unit 327 may be configured to display a continuous screen, or may be configured to display different screens. By configuring to display different screens, for example, The text is displayed on the right display unit (display unit 325 in FIG. 22(C)), and the text is displayed on the left display unit (display unit 325 in FIG. 22(C)). In (C), an image can be displayed on the display unit 327).

[0259] FIG. 22C shows an example in which an operation unit and the like are provided on the housing 321. The body 321 includes a power supply 331, operation keys 333, a speaker 335, etc. You can turn the page by pressing the arrow 333. In addition, there is a keyboard and a pointer on the same surface as the display unit of the housing. The back and sides of the housing may be provided with an external Connection terminals (earphone jack, USB terminal, AC adapter and USB cable, etc.) terminals that can be connected to various cables, a recording medium insertion section, etc. Furthermore, the electronic book 320 may be configured to have the function of an electronic dictionary.

[0260] The electronic book 320 may also be configured to be able to send and receive information wirelessly. It is also possible to purchase and download desired book data from the child book server. It is possible.

[0261] Electronic paper can be applied to any field that displays information. For example, in addition to e-books, posters, advertisements on trains and other vehicles, credit cards, etc. The present invention can be applied to displays on various cards such as gift cards.

[0262] FIG. 22D shows a mobile phone including the semiconductor device according to the above embodiment. The phone is made up of two housings, housing 340 and housing 341. Housing 341 has a front display panel 342, speaker 343, microphone 344, pointing device 3 46, a camera lens 347, an external connection terminal 348, etc. The mobile phone includes a solar cell 349 for charging the mobile phone, an external memory slot 350, etc. The antenna is built into the housing 341. By applying the body device to a mobile phone, information can be retained even when there is no power supply. In addition, there is no deterioration due to writing and erasing. Therefore, it is preferable to apply the semiconductor device according to one embodiment of the present invention to a mobile phone. be.

[0263] The display panel 342 has a touch panel function, and in FIG. 22(D) an image is displayed. The multiple operation keys 345 are shown by dotted lines. A boost circuit is implemented to boost the voltage output by 9 to the voltage required for each circuit. In addition to the above configuration, it may be configured to incorporate a contactless IC chip, a small recording device, etc. It is also possible.

[0264] The display direction of the display panel 342 changes appropriately depending on the usage mode. The camera lens 347 is located on the same surface as the camera 42, making it possible to make video calls. The speaker 343 and microphone 344 are not limited to voice calls, but also video calls, recording, playback Furthermore, the housing 340 and the housing 341 can be slid, and as shown in FIG. It can be folded from the unfolded state to the overlapping state, making it possible to make it compact and portable. It is Noh.

[0265] The external connection terminal 348 can be connected to various cables such as an AC adapter or a USB cable. The external memory slot 350 can store a recording medium. It can insert and store and move larger amounts of data. In addition to the above functions, It may also be equipped with infrared communication functions, television reception functions, etc.

[0266] FIG. 22E shows a digital camera including the semiconductor device according to the previous embodiment. The digital camera comprises a main body 361, a display unit (A) 367, an eyepiece 363, and an operation switch 364. , a display unit (B) 365, a battery 366, etc. By applying the semiconductor device according to the present invention to a digital camera, information can be stored even when there is no power supply. In addition, there is no deterioration due to writing and erasing. Therefore, the semiconductor device according to one embodiment of the present invention is suitable for a digital camera. It is preferable to use

[0267] FIG. 22F shows a television set including the semiconductor device according to the above embodiment. In the vision device 370, a display unit 373 is built into a housing 371. In this case, the stand 375 is used to hold the case in place. 371 is shown in the supporting configuration.

[0268] The television device 370 can be operated using an operation switch provided on the housing 371 or a separate remote control. This can be done by operating the operating device 380. The remote control operating device 380 has an operating key 379. This allows you to control the channel and volume, and to operate the image displayed on the display unit 373. In addition, the remote control operation device 380 can receive the output from the remote control operation device 380. A display unit 377 for displaying information may be provided. By applying this device to a television set, information can be retained even when there is no power supply. In addition, there is no deterioration due to writing and erasing. Therefore, the semiconductor device according to one embodiment of the present invention is applied to a television set. This is preferable.

[0269] It is preferable that the television device 370 is configured to include a receiver, a modem, etc. The receiver can receive general television broadcasts. By connecting to a wired or wireless communication network, The purpose of this communication is to communicate information between two parties (one party) or two-way (between a sender and a receiver, or between receivers). It is possible to do this.

[0270] The structures, methods, and the like described in this embodiment may be combined as appropriate with the structures, methods, and the like described in other embodiments. Can be used in combination [Explanation of symbols]

[0271] 100 boards 102 Protective layer 104 Semiconductor Area 106 Element isolation insulating layer 108 Gate insulating layer 110 gate electrode 112 Insulating layer 114 Impurity region 116 Channel formation region 118 Sidewall insulating layer 120 High concentration impurity region 122 Metal layer 124 Metal compound area 126 Interlayer insulation layer 128 Interlayer Insulation Layer 130a Source electrode or drain electrode 130b Source electrode or drain electrode 130c electrode 132 Insulating layer 134 Conductive layer 136a electrode 136b Electrode 136c electrode 136d Gate electrode 138 Gate insulating layer 140 Oxide semiconductor layer 142a Source electrode or drain electrode 142b Source electrode or drain electrode 144 Protective Insulation Layer 146 Interlayer insulation layer 148 Conductive Layer 150a electrode 150b electrode 150c electrode 150d electrode 150e electrode 152 Insulating layer 154a electrode 154b electrode 154c electrode 154d electrode 160 transistors 162 transistors 200 memory cells 201 Transistor 202 Transistor 203 Transistor 210 memory cell array 211 Write circuit 212 readout circuit 213 Drive Circuit 214 Column Decoder 215 Address Buffer 216 Control circuit 217 Potential generation circuit 218 Data Buffer 219 Multiplexer 301 Main Unit 302 Case 303 Display section 304 keyboard 311 Main Unit 312 Stylus 313 Display section 314 Operation Button 315 External Interface 320 e-books 321 Case 323 Case 325 Display section 327 Display section 331 Power supply 333 Operation Key 335 Speaker 337 Shaft 340 Case 341 Case 342 Display Panel 343 Speaker 344 Microphone 345 Operation Key 346 Pointing Device 347 Camera Lenses 348 External connection terminal 349 Solar Cells 350 external memory slot 361 Main Unit 363 Eyepiece 364 Operation Switch 365 Display section (B) 366 Battery 367 Display section (A) 370 Television Equipment 371 Case 373 Display section 375 Stand 377 Display section 379 Operation Key 380 Remote Controlled Device

Claims

1. a first transistor and a second transistor; a semiconductor device in which one of a source and a drain of the second transistor is electrically connected to a gate of the first transistor, a silicon semiconductor layer; a first insulating layer having a region located above the silicon semiconductor layer; a first electrode having a region in contact with an upper surface of the first insulating layer; a second electrode having a region in contact with the upper surface of the first insulating layer; a third electrode having a region in contact with the upper surface of the first insulating layer; an oxide semiconductor layer having a region located above the second electrode; a second insulating layer having a region located above the oxide semiconductor layer; a fourth electrode having a region located above the second insulating layer; the silicon semiconductor layer has a channel formation region of the first transistor, the oxide semiconductor layer has a channel formation region of the second transistor, the first electrode has a region overlapping with the silicon semiconductor layer, the first electrode does not have a region overlapping with a channel formation region of the second transistor; the second electrode has a region overlapping with a channel formation region of the second transistor, The third electrode has a region overlapping with the fourth electrode.

2. a first transistor and a second transistor; a semiconductor device in which one of a source and a drain of the second transistor is electrically connected to a gate of the first transistor, a silicon semiconductor layer; a first insulating layer having a region located above the silicon semiconductor layer; a first electrode having a region in contact with an upper surface of the first insulating layer; a second electrode having a region in contact with the upper surface of the first insulating layer; a third electrode having a region in contact with the upper surface of the first insulating layer; an oxide semiconductor layer having a region located above the second electrode; a second insulating layer having a region located above the oxide semiconductor layer; a fourth electrode having a region located above the second insulating layer; the silicon semiconductor layer has a channel formation region of the first transistor, the oxide semiconductor layer has a channel formation region of the second transistor, the first electrode has a region overlapping with the silicon semiconductor layer, the first electrode does not have a region overlapping with a channel formation region of the second transistor; the second electrode has a region overlapping with a channel formation region of the second transistor, the third electrode has an area overlapping with the fourth electrode, A semiconductor device in which a channel formation region of the first transistor does not overlap a channel formation region of the second transistor.

3. a first transistor and a second transistor; a semiconductor device in which one of a source and a drain of the second transistor is electrically connected to a gate of the first transistor, a silicon semiconductor layer; a first insulating layer having a region located above the silicon semiconductor layer; a first electrode having a region in contact with an upper surface of the first insulating layer; a second electrode having a region in contact with the upper surface of the first insulating layer; a third electrode having a region in contact with the upper surface of the first insulating layer; an oxide semiconductor layer having a region located above the second electrode; a second insulating layer having a region located above the oxide semiconductor layer; a fourth electrode having a region located above the second insulating layer; the silicon semiconductor layer has a channel formation region of the first transistor, the oxide semiconductor layer has a channel formation region of the second transistor, the first electrode has a region overlapping with the silicon semiconductor layer, the first electrode does not have a region overlapping with a channel formation region of the second transistor; the second electrode has a region overlapping with a channel formation region of the second transistor, the second electrode does not have an area overlapping with the fourth electrode; The third electrode has a region overlapping with the fourth electrode.

4. a first transistor and a second transistor; a semiconductor device in which one of a source and a drain of the second transistor is electrically connected to a gate of the first transistor, a silicon semiconductor layer; a first insulating layer having a region located above the silicon semiconductor layer; a first electrode having a region in contact with an upper surface of the first insulating layer; a second electrode having a region in contact with the upper surface of the first insulating layer; a third electrode having a region in contact with the upper surface of the first insulating layer; an oxide semiconductor layer having a region located above the second electrode; a second insulating layer having a region located above the oxide semiconductor layer; a fourth electrode having a region located above the second insulating layer; the silicon semiconductor layer has a channel formation region of the first transistor, the oxide semiconductor layer has a channel formation region of the second transistor, the first electrode has a region overlapping with the silicon semiconductor layer, the first electrode does not have a region overlapping with a channel formation region of the second transistor; the second electrode has a region overlapping with a channel formation region of the second transistor, the second electrode does not have an area overlapping with the fourth electrode; the third electrode has an area overlapping with the fourth electrode, A semiconductor device in which a channel formation region of the first transistor does not overlap a channel formation region of the second transistor.

5. In any one of claims 1 to 4, The oxide semiconductor layer includes In, M (M is Ga, Al, Mn, or Co), and Zn.

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