Semiconductor device

Abstract

To provide a semiconductor device capable of the product-sum operation with lower consumption power.SOLUTION: A semiconductor device includes circuits MC and MCr. The circuit MC includes a holding part HC and a first transistor and the circuit includes a holding part HCr and a second transistor. The respective circuits are electrically connected to first and second input wires X1L and X2L and first and second wires OL and OLB. The holding part HC has a function of holding a first current flowing in the first transistor. The holding part HCr has a function of holding a second current flowing in the second transistor. The first and second currents are determined in accordance with first data. By the input of potentials in accordance with second data to the first and second input wires, the circuit MC outputs current to one of the first wire and the second wire and the circuit MCr outputs current to the other of the first wire and the second wire. The amount of current output from the circuits to the first wire or the second wire is determined in accordance with the first data and the second data.SELECTED DRAWING: Figure 9

Description

[Technical Field]

[0001] One embodiment of the present invention relates to a semiconductor device and an electronic device.

[0002] Note that one embodiment of the present invention is not limited to the above technical fields. The technical field relates to an article, a method, or a manufacturing method. Process, machine, manufacture, or composition of matter Therefore, the technology of one embodiment of the present invention disclosed in this specification more specifically relates to the above. Fields include semiconductor devices, display devices, liquid crystal display devices, light-emitting devices, power storage devices, imaging devices, Storage device, signal processing device, processor, electronic device, system, driving method thereof, Examples of the manufacturing method and the inspection method thereof are as follows. [Background technology]

[0003] Currently, the development of integrated circuits that mimic the mechanisms of the human brain is progressing vigorously. The brain's mechanisms are incorporated as electronic circuits, and the brain's "neurons" and "systems" are connected. Therefore, such an integrated circuit is called a "neuromorph." It is also sometimes called "brain-morphic," "brain-inspired," or "brain-morphic." The integrated circuit has a non-von Neumann architecture, and power consumption decreases as processing speed increases. Compared to the larger von Neumann architecture, parallel processing can be performed with extremely low power consumption. It is expected that this will be possible.

[0004] The information processing model that mimics a neural network with "neurons" and "synapses" is called artificial neural network. These are called neural networks (ANNs). For example, see Non-Patent Document 1 and Non-Patent Document 2 uses SRAM (Static Random Access Memory) The document discloses a computing device that configures an artificial neural network. [Prior art documents] [Non-patent literature]

[0005] [Non-Patent Document 1] M. Kang et al., “IEEE Journal Of Solid-State Circuits”, 2018, Volume 53, No.2, p.642-655. [Non-patent document 2] J. Zhang et al., “IEEE Journal Of Solid-State Circuits”, 2017, Volume 52, No.4, p.915-924. Summary of the Invention [Problem to be solved by the invention]

[0006] In artificial neural networks, the strength of the synapse that connects two neurons is called the Multiply the signal transmitted between two neurons by the degree (sometimes called a weighting coefficient) In particular, in a hierarchical artificial neural network, the first layer consists of multiple first The strength of each synaptic connection between the neuron and one of the second neurons in layer 2, Each signal input from multiple first neurons in the first layer to one of the second neurons in the second layer It is necessary to multiply and add the numbers, and depending on the scale of the artificial neural network, For example, the number of connection strengths and the number of parameters that represent the signal are determined. The more layers and neurons in a neural network, the more "neurons" and The number of circuits corresponding to each "synapse" can increase, and the amount of calculations can become enormous. .

[0007] As the number of circuits that make up a chip increases, power consumption also increases, and the amount of electricity generated when the device is running also increases. The amount of heat also increases. In particular, the higher the amount of heat generated, the more the characteristics of the circuit elements included in the chip deteriorate. Therefore, the circuits that make up the chip must have circuit elements that are less susceptible to temperature changes. In addition, the characteristics of the transistors and current sources included in the chip vary. If this occurs, the calculation results will vary.

[0008] One aspect of the present invention is a semiconductor device in which a hierarchical artificial neural network is constructed. Another object of one embodiment of the present invention is to provide a semiconductor device with low power consumption. Another object of the present invention is to provide a method for manufacturing a semiconductor device that is not affected by the temperature of the environment. Another object of the present invention is to provide a semiconductor device or the like that is less susceptible to cracking. One of the objectives is to provide a semiconductor device that is less susceptible to variations in transistor characteristics. Another embodiment of the present invention is a semiconductor device that is not easily affected by variations in characteristics of a current source. Another object of the present invention is to provide a novel semiconductor device, etc. One of our goals is to provide the following.

[0009] Note that the problems of one embodiment of the present invention are not limited to the above-listed problems. This does not preclude the existence of other problems. Problems not mentioned in this section are problems that a person skilled in the art would be able to solve by understanding the specification or can be derived from the descriptions in the drawings, etc., and can be extracted appropriately from these descriptions. One aspect of the present invention is to achieve at least one of the above-listed objects and other objects. One aspect of the present invention is to solve the above-listed problems and other problems. You don't need to solve all of them. [Means for solving the problem]

[0010] (1) One embodiment of the present invention is a semiconductor device including a first circuit and a second circuit, The second circuit has a first holding unit and a first drive transistor, and the second circuit has a second holding unit and a second a driving transistor, and the first circuit includes a first input wiring, a second input wiring, a first wiring, and and the second circuit is electrically connected to the first input wiring, the second input wiring, the first wiring, and the second wiring, and the first holding unit is electrically connected to the first driving transistor from the first wiring. The second capacitor has a function of maintaining a first potential according to a first current flowing between the source and drain of the second capacitor. The holding section is configured to hold a second current flowing from the second wiring between the source and drain of the second drive transistor. The first driving transistor has a function of holding a second potential according to the first driving transistor. and a function of causing a first current to flow between the source and drain of the semiconductor device in accordance with the first potential held therebetween. , the second driving transistor is held between the source and drain of the second driving transistor. The first circuit has a function of supplying a second current corresponding to the second potential supplied thereto, and the first circuit supplies a first level to the first input wiring. When the first level potential is input to the second input wiring and the second level potential is input to the second input wiring, the first current to the first wiring, and the second level potential is input to the first input wiring and the second input a function of outputting a first current to a second wiring when a first level potential is input to the wiring; A second level potential is input to the input wiring, and a second level potential is input to the second input wiring. When the first current is output to the first wiring and the second wiring, the second circuit has a function of not outputting the first current to the first wiring and the second wiring. A first level potential is input to the first input wiring, and a second level potential is input to the second input wiring. When a second current is input to the second wiring, the second current is output to the second wiring. When a second level potential is input to the first input wiring, the second current is output to the second wiring. When a first level potential is input to the second input wiring, a second current is supplied to the first wiring. The function of outputting a second level potential is input to the first input wiring and the second level potential is input to the second input wiring. a function of not outputting the second current to the first wiring and the second wiring when a bell potential is input; the first current and the second current each have a current amount according to the first data, and the first input The first level voltages input to the wiring, the second input wiring, the third input wiring, and the fourth input wiring are The first level potential is determined according to second data.

[0011] (2) Another embodiment of the present invention is a semiconductor device including a first circuit and a second circuit, The first circuit has a first holding unit and a first drive transistor, and the second circuit has a second holding unit and and a second driving transistor, and the first circuit has a first input wiring, a second input wiring, and a first wiring. The second circuit is electrically connected to the first input wiring, the second input wiring, and the The first holding unit is electrically connected to the first wiring and the second wiring, and the first driving transistor is connected to the first wiring. The transistor has a function of maintaining a first potential according to a first current flowing between the source and drain of the transistor. The second holding section is a second current flowing from the second wiring between the source and drain of the second drive transistor. The first driving transistor has a function of holding a second potential according to the current. A function of causing a first current to flow between the source and drain of the transistor according to the first potential maintained. and the second driving transistor has a source-drain The first circuit has a function of supplying a second current corresponding to the second potential held, and the first circuit supplies a second current during the first period. A first level potential is input to the first input wiring, and a second level potential is input to the second input wiring. When the first current is detected, the first current is output to the first wiring. During the first period, the second level is output to the first input wiring. When the first level potential is input to the second input wiring, and the first level potential is input to the second input wiring, the first current is generated. A function of outputting to the second wiring, and a function of inputting a second level potential to the first input wiring during the first period, When a second level potential is input to the second input wiring, a first current flows through the first wiring and the second wiring. and a function of not outputting to the first input wiring, and the second circuit applies a first level voltage to the first input wiring during the first period. When a second level potential is input to the second input wiring and a second level potential is input to the second input wiring, the second current is a function of outputting to the wiring, and a function of inputting a second level potential to the first input wiring during the first period and When the first level potential is input to the second input wiring, the second current is output to the first wiring. During the first period, a second level potential is input to the first input wiring, and a second level potential is input to the second input wiring. and a function of not outputting the second current to the first wiring and the second wiring when a voltage of the capacitor is input. The first current and the second current each have a current amount according to the first data, and the first input distribution The first level potential, the second level potential, and the first level potential are input to the first input wiring, the second input wiring, respectively. The length of the gap is determined according to the second data.

[0012] (3) Alternatively, in one aspect of the present invention, in the configuration (2), the first period is and the first input wiring is connected to both the first circuit and the second circuit in the second period. The second input wiring has a function of applying a first level potential or a second level potential, and and a function of outputting a first level potential or a second level potential to both the first circuit and the second circuit. The first input wiring supplies a first level voltage to both the first circuit and the second circuit in the third period. The second input wiring has a function of applying a first or second level potential during the third period. The third circuit has a function of outputting a first level potential or a second level potential to both the first circuit and the second circuit. The length of the period is twice the length of the second period.

[0013] (4) Alternatively, one aspect of the present invention is a method for manufacturing a semiconductor device according to any one of the above (1) to (3), wherein the first The circuit includes a first transistor, a second transistor, a third transistor, and a first capacitor. the second circuit includes a fourth transistor, a fifth transistor, a sixth transistor, and a the first holding unit has a first transistor and a first capacitor, and the second holding unit has a first transistor and a first capacitor. The first terminal of the first transistor is connected to a first capacitor. a first terminal of the capacitor electrically connected to the gate of the first drive transistor; The second terminal of the first driving transistor is electrically connected to the first wiring, and the first terminal of the first driving transistor is electrically connected to the first wiring. a first terminal of the second transistor and a first terminal of the third transistor; The second terminal of the second transistor is electrically connected to the first wiring, and the gate of the second transistor is is electrically connected to the first input wiring, and the second terminal of the third transistor is electrically connected to the second wiring. The gate of the third transistor is electrically connected to the second input wiring, and the gate of the fourth transistor is electrically connected to the second input wiring. The first terminal of the transistor is electrically connected to the first terminal of the second capacitor and to the gate of the second drive transistor. a second terminal of the fourth transistor electrically connected to the second wiring; The first terminal of the transistor is connected to the first terminal of the fifth transistor and the first terminal of the sixth transistor. The second terminal of the fifth transistor is electrically connected to the second wiring. The gate of the fifth transistor is electrically connected to the first input wiring, and the gate of the sixth transistor is electrically connected to the first input wiring. The second terminal of the sixth transistor is electrically connected to the first wiring, and the gate of the sixth transistor is electrically connected to the second input wiring. The semiconductor device is electrically connected to the wiring.

[0014] (5) Alternatively, in one aspect of the present invention, in the configuration (4), the first circuit includes a seventh transistor the second circuit includes an eighth transistor, and the first terminal of the seventh transistor is connected to the first driver a first terminal of the driving transistor, a first terminal of the second transistor, and a first terminal of the third transistor; the second terminal of the seventh transistor is electrically connected to the first terminal of the first transistor; the first terminal of the eighth transistor is electrically connected to one of the first terminal and the second terminal of the eighth transistor; a first terminal of the driving transistor, a first terminal of the fifth transistor, and a first terminal of the sixth transistor; the second terminal of the eighth transistor is electrically connected to the first terminal of the fourth transistor; the gate of the first transistor is electrically connected to one of the first terminal and the second terminal, and the gate of the first transistor is electrically connected to the fourth terminal. The gate of the seventh transistor, the gate of the eighth transistor, The semiconductor device is electrically connected to the semiconductor device.

[0015] (6) Alternatively, one aspect of the present invention is a method for manufacturing a semiconductor device according to any one of the above (1) to (3), wherein the first The circuit includes a first transistor, a second transistor, a third transistor, and a first capacitor. The second circuit includes a fourth transistor, a fifth transistor, a sixth transistor, a second capacitor, and , the first holding unit has a first transistor and a first capacitance, and the second holding unit has a a first terminal of the first transistor and a second capacitor, a first terminal electrically connected to the gate of the first driving transistor; The first terminal is connected to the second terminal of the first transistor, the first terminal of the second transistor, and the third terminal of the a first terminal of the first transistor electrically connected to the first wiring; and a second terminal of the second transistor electrically connected to the first wiring. the gate of the second transistor is electrically connected to the first input wiring, The second terminal of the third transistor is electrically connected to the second wiring, and the gate of the third transistor The first terminal of the fourth transistor is electrically connected to the second input wiring, and the first terminal of the fourth transistor is electrically connected to the first terminal of the second capacitor. the first terminal is electrically connected to the gate of the second driving transistor, and the second driving transistor The first terminal is connected to the second terminal of the fourth transistor, the first terminal of the fifth transistor, and the sixth transistor. a first terminal of the fifth transistor electrically connected to the second wiring; the gate of the fifth transistor is electrically connected to the first input wiring, The second terminal of the sixth transistor is electrically connected to the first wiring, and the gate of the sixth transistor The input terminal is a semiconductor device electrically connected to the second input wiring.

[0016] (7) Alternatively, one aspect of the present invention is a method for manufacturing a semiconductor device according to any one of the above (1) to (3), wherein the first The first circuit has a third holding unit and a third driving transistor, and the second circuit has a fourth holding unit and a a fourth driving transistor, the first circuit being electrically connected to the third wiring, and the second circuit being , and the third holding unit is electrically connected to the third wiring, and the third holding unit is connected to the third wiring. a fourth holding section having a function of holding a third potential according to a third current flowing between the source and drain; is a value corresponding to a fourth current flowing from the second wiring between the source and drain of the fourth drive transistor. The third driving transistor has a function of holding the fourth potential. The third current flows between the source and drain in accordance with the third potential held therebetween. The driving transistor is held between the source and drain of the fourth driving transistor. The fourth wiring has a function of causing a fourth current to flow according to a fourth potential, and the first wiring has a function of causing a fourth current to flow according to a signal input to the third wiring. A first current flowing through one of the wiring and the second wiring is switched to a third current, and The semiconductor device has a function of switching the second current flowing through the other wiring to a fourth current.

[0017] (8) Alternatively, one aspect of the present invention is a third embodiment in any one of the above-described structures (1) to (7). a third circuit, a fourth circuit, and a fifth circuit, and the third circuit is connected to the first circuit via the first wiring; a function of supplying a first current according to the first data to a second circuit via a second wiring; a fourth circuit for supplying a second current according to the second data; a function of inputting a first level potential or a second level potential to the line, and a function of inputting a second level potential to the line according to second data; The fifth circuit has a function of inputting a first level potential or a second level potential to the input wiring. , the current flowing from the first wiring and the second wiring is compared, and the output terminal of the fifth circuit The semiconductor device has a function of outputting a potential corresponding to the product of the first data and the second data. do.

[0018] (9) Another embodiment of the present invention is a semiconductor device including a first circuit and a second circuit, the one circuit has a first holding unit, a first drive transistor, and a third drive transistor; The second circuit includes a second holding unit, a second drive transistor, and a fourth drive transistor. , the first circuit includes a first input wiring, a second input wiring, a third input wiring, a fourth input wiring, a first wiring, and a second circuit electrically connected to the first input wiring, the second input wiring, the third input wiring, and the third input wiring. the first holding unit is electrically connected to the first input wiring, the fourth input wiring, the first wiring, and the second wiring; A first current flowing from the first wiring to the source-drain of the first drive transistor The second holding unit has a function of holding a potential, and the second holding unit is connected from the second wiring to the source of the second drive transistor. - a first driving transistor having a function of maintaining a second potential according to a second current flowing between the drains; The first drive transistor is connected to the first potential held between the source and drain of the first drive transistor. The second driving transistor has a function of passing a first current in response to the second driving transistor's The second current flows between the source and drain in accordance with the second potential held therebetween. The third drive transistor is held between the source and drain of the third drive transistor. The fourth driving transistor has a function of passing a third current according to the first potential. A fourth current corresponding to the second potential held between the source and drain of the transistor is caused to flow. The first circuit has a function of inputting a first level potential to a first input wiring and A function of outputting a first current to a first wiring when a second level potential is input, and a function of outputting a first current to a first input wiring When the second level potential is input to the line and the first level potential is input to the second input wiring, , a function of outputting a first current to a second wiring, and a function of inputting a second level potential to a first input wiring, When a second level potential is input to the second input wiring, a first current flows through the first wiring and the second wiring. The function of not outputting to the line, and the first level potential is input to the third input wiring and When the second level potential is input, a third current is output to the first wiring, and a third input wiring is When the second level potential is input to the line and the first level potential is input to the fourth input line, , a function of outputting a third current to the second wiring, and a function of inputting a second level potential to the third input wiring, and when a second level potential is input to the fourth input wiring, a third current is supplied to the first wiring and the second wiring. The second circuit has a function of not outputting a first level potential to the first input wiring. and when a second level potential is input to the second input wiring, a second current is output to the second wiring. The second level potential is input to the first input wiring, and the first level potential is input to the second input wiring. When a second level is input, the second current is output to the first wiring, and the second level is input to the first input wiring. When the second level potential is input to the second input wiring, the second current is generated. The function of not outputting to the first wiring and the second wiring, and the function of inputting the first level potential to the third input wiring. and when a second level potential is input to the fourth input wiring, a fourth current is output to the second wiring. The function of inputting the second level potential to the third input wiring and the first level potential to the fourth input wiring is also When a level is input, the fourth current is output to the first wiring, and the second level is output to the third input wiring. When the 4th input wiring is connected to the 2nd level potential, the 4th current is and a function of not outputting to the first wiring and the second wiring, and a first current, a second current, a third current, Each of the fourth currents has a current amount according to the first data, and the first input wiring, the second input wiring , the first level potential and the second level potential input to the third input wiring and the fourth input wiring, respectively. is a semiconductor device determined according to the second data.

[0019] (10) Another embodiment of the present invention is a semiconductor device including a first circuit and a second circuit, the one circuit has a first holding unit, a first drive transistor, and a third drive transistor; The second circuit includes a second holding unit, a second drive transistor, and a fourth drive transistor. , the first circuit includes a first input wiring, a second input wiring, a third input wiring, a fourth input wiring, a first wiring, and a second circuit electrically connected to the first input wiring, the second input wiring, the third input wiring, and the third input wiring. the first holding unit is electrically connected to the first input wiring, the fourth input wiring, the first wiring, and the second wiring; A first current flowing from the first wiring to the source-drain of the first drive transistor The second holding unit has a function of holding a potential, and the second holding unit is connected from the second wiring to the source of the second drive transistor. - a first driving transistor having a function of maintaining a second potential according to a second current flowing between the drains; The first drive transistor is connected to the first potential held between the source and drain of the first drive transistor. The second driving transistor has a function of passing a first current in response to the second driving transistor's The second current flows between the source and drain in accordance with the second potential held therebetween. The third drive transistor is held between the source and drain of the third drive transistor. The fourth driving transistor has a function of passing a third current according to the first potential. A fourth current corresponding to the second potential held between the source and drain of the transistor is caused to flow. The first circuit has a function of inputting a first level potential to a first input wiring during a first period, and 2. When the second level potential is input to the input wiring, the first current is output to the first wiring. During the first period, a second level potential is input to the first input wiring, and a first level potential is input to the second input wiring. When a voltage potential is input, the first current is output to the second wiring. When the second level potential is input to the first input wiring and the second level potential is input to the second input wiring, a function of not outputting the first current to the first wiring and the second wiring during the first period; When the first level potential is input to the line and the second level potential is input to the fourth input line, , a function of outputting a third current to the first wiring, and a function of outputting a second level potential to the third input wiring during the first period. When the first level potential is input to the fourth input wiring, the third current is input to the second wiring. During the first period, the second level potential is input to the third input wiring and the fourth input When a second level potential is input to the input wiring, a third current is output to the first wiring and the second wiring. The second circuit has a function of inputting a first level potential to the first input wiring during the first period. When a second level potential is input to the second input wiring, a second current is output to the second wiring. and a function of inputting a second level potential to the first input wiring and a second level potential to the second input wiring during the first period. When a first level potential is input to the line, a second current is output to the first wiring. During this time, a second level potential is input to the first input wiring and a second level potential is input to the second input wiring. When the second current is input, the second current is not output to the first wiring and the second wiring. , the first level potential is input to the third input wiring, and the second level potential is input to the fourth input wiring. When the fourth current is input, the fourth current is output to the second wiring. During the first period, the second current is output to the third input wiring. When a level potential is input to the fourth input wiring and the first level potential is input to the fourth input wiring, The second level potential is input to the third input wiring during the first period. and when a second level potential is input to the fourth input wiring, a fourth current is supplied to the first wiring, and The first current, the second current, the third current, and the fourth current each have a function of not outputting to the second wiring. This has a current amount according to the first data, and is connected to a first input wiring, a second input wiring, a third input wiring, The first level potential, the second level potential, and the first period potential are input to the fourth input wirings, respectively. The length is determined according to the second data.

[0020] (11) Alternatively, in one aspect of the present invention, in the configuration (10), the first period is and a third period, and the first input wiring is connected to both the first circuit and the second circuit in the second period. The second input wiring has a function of applying a first level potential or a second level potential. and a function of applying a first level potential or a second level potential to both the first circuit and the second circuit. and a third input wiring supplies a first level voltage to both the first circuit and the second circuit during a second period. The fourth input wiring has a function of applying a first or second level potential during the second period. The first input has a function of applying a first level potential or a second level potential to both the first input and the second input. In the third period, the input wiring supplies the first level potential or the second level potential to both the first circuit and the second circuit. The second input wiring has a function of applying a bell potential to the first circuit and the second circuit during the third period. The third input wiring has the function of applying a first level potential or a second level potential to both the first and second input wirings. In the third period, the first level potential or the second level potential is applied to both the first circuit and the second circuit. The fourth input wiring has a function of supplying the first and second circuits with the third input signal during the third period. The third period has a function of applying a first level potential or a second level potential, and the length of the third period is the same as the length of the second period. It is a semiconductor device that is twice the size of the conventional one.

[0021] (12) Alternatively, one aspect of the present invention is any one of the above structures (9) to (11), wherein the third a third circuit, a fourth circuit, and a fifth circuit, and the third circuit is connected to the first circuit via a first wiring. a function of supplying a first current according to the first data to a second circuit via a second wiring; The fourth circuit has the function of supplying the second current according to the data, and the fourth circuit has the function of supplying the second current according to the data to the first input wiring. The second input wiring has a function of inputting a first level potential or a second level potential according to the The third input wiring has a function to input the first or second level potential depending on the data. a function of inputting a first level potential or a second level potential according to the second data; and a function of inputting a first level potential or a second level potential to the line in accordance with second data. The fifth circuit compares the currents flowing from the first wiring and the second wiring, and determines the fifth The circuit has a function of outputting a potential corresponding to the product of the first data and the second data from the output terminal. It is a semiconductor device.

[0022] (13) Another embodiment of the present invention is a semiconductor device including a first circuit and a second circuit, The first circuit has a first holding unit and a first drive transistor, and the second circuit has a second holding unit and and a second drive transistor, and the first circuit is electrically connected to the first input wiring and the first wiring. the second circuit is electrically connected to the first input wiring and the second wiring, and the first holding unit is a voltage corresponding to a first current flowing from the first wiring between the source and drain of the first drive transistor. The second holding unit has a function of holding the first potential, and the second holding unit is configured to connect the second wiring to the second drive transistor. The second drive transistor has a function of maintaining a second potential according to a second current flowing between the source and drain. The transistor transfers the first voltage held between the source and drain of the first drive transistor. The second driving transistor has a function of passing a first current according to the potential of the second driving transistor. and a second current corresponding to the second potential held between the source and drain of the The first circuit generates a first current through the first wiring when a first level potential is input to the first input wiring. and when the second level potential is input to the first input wiring, the first current is output to the first The second circuit has a function of not outputting to the wiring, and the first level potential is input to the first input wiring. When a second current is input to the second wiring, the second current is output to the second wiring. When a second level potential is input to the first input wiring, the second current is output to the second wiring. and a function of not outputting the second current to the second wiring when the first current and the second current are input. Each of the first input wiring and the second input wiring has a current amount according to the first data. The first level potential and the second level potential input thereto are determined in accordance with the second data. It is a conductor device.

[0023] (14) Another embodiment of the present invention is a semiconductor device including a first circuit and a second circuit, The first circuit has a first holding unit and a first drive transistor, and the second circuit has a second holding unit and and a second drive transistor, and the first circuit is electrically connected to the first input wiring and the first wiring. the second circuit is electrically connected to the first input wiring and the second wiring, and the first holding unit is a voltage corresponding to a first current flowing from the first wiring between the source and drain of the first drive transistor. The second holding unit has a function of holding the first potential, and the second holding unit is configured to connect the second wiring to the second drive transistor. The second drive transistor has a function of maintaining a second potential according to a second current flowing between the source and drain. The transistor transfers the first voltage held between the source and drain of the first drive transistor. The second driving transistor has a function of passing a first current according to the potential of the second driving transistor. and a second current corresponding to the second potential held between the source and drain of the When a first level potential is input to the first input wiring during the first period, the first circuit A function of outputting a current to the first wiring and a function of inputting a second level potential to the first input wiring during the first period. and a function of not outputting the first current to the first wiring when the first current is A function that outputs a second current to the second wiring when a first level potential is input to the first input wiring. During the first period, when a second level potential is input to the first input wiring, a second current is supplied to the second wiring. and a function of not outputting the first current to the line, and each of the first current and the second current is The first and second input wirings have a current amount, and a first level potential and a second level potential are input to the first and second input wirings, respectively. The two-level potential is determined according to the second data in the semiconductor device.

[0024] (15) Alternatively, in the configuration (14), the first period may be a period including a second period and a third period. and a third period, and the first input wiring is connected to both the first circuit and the second circuit in the second period. The first input wiring has a function of applying a first level potential or a second level potential, and in the third period, and a function of applying a first level potential or a second level potential to both the first circuit and the second circuit. The length of the third period is twice the length of the second period.

[0025] (16) Alternatively, one embodiment of the present invention is any one of the above structures (13) to (15), The first circuit has a first transistor, a second transistor, and a first capacitor, and the second circuit has , a fourth transistor, a fifth transistor, and a second capacitor, and the first holding unit the second holding unit has a fourth transistor and a second capacitor; , and the first terminal of the first transistor is connected to the first terminal of the first capacitance and the first drive transistor. The second terminal of the first transistor is electrically connected to the gate of the first transistor, and the second terminal of the first transistor is electrically connected to the first wiring. and a first terminal of the first drive transistor is electrically connected to a first terminal of the second transistor. a second terminal of the second transistor electrically connected to the first wiring; The gate of the fourth transistor is electrically connected to the first input wiring, and the first terminal of the fourth transistor is electrically connected to the second input wiring. a fourth transistor electrically connected to the first terminal of the capacitor and the gate of the second drive transistor; The second terminal of the second driving transistor is electrically connected to the second wiring, and the first terminal of the second driving transistor is electrically connected to the first wiring. a second terminal of the fifth transistor electrically connected to the first terminal of the fifth transistor; The gate of the fifth transistor is electrically connected to the first input wiring. It is a semiconductor device.

[0026] (17) Another embodiment of the present invention is a semiconductor device comprising: a semiconductor device according to any one of (1) to (16); and an electronic device that performs neural network calculations using a semiconductor device.

[0027] In this specification, a semiconductor device is a device that utilizes semiconductor characteristics. Circuits containing semiconductor elements (transistors, diodes, photodiodes, etc.) It also refers to any device that can function by utilizing the properties of semiconductors. For example, Integrated circuits, chips with integrated circuits, and electronic components that house chips in packages are semiconductors. In addition, a storage device, a display device, a light-emitting device, a lighting device, an electronic device, etc. It may itself be a semiconductor device and may contain a semiconductor device.

[0028] In addition, in this specification, when it is stated that X and Y are connected, it means that X and Y are connected. When X and Y are electrically connected, when X and Y are functionally connected, and when X and The case where Y is directly connected is also considered to be disclosed in this specification. Therefore, the present invention is not limited to predetermined connection relationships, for example, connection relationships shown in drawings or text, but may be applied to connections shown in drawings or text. Connections other than those shown in the figure or text are also considered to be disclosed. The object (e.g., device, element, circuit, wiring, electrode, terminal, conductive film, layer, etc.) .

[0029] An example of the case where X and Y are electrically connected is The elements that function as One or more devices (diode, display device, light-emitting device, load, etc.) are connected between X and Y. The switch has a function to control on / off. This means that the switch is either in a conducting state (ON state) or a non-conducting state (OFF state), and the current It has the function of controlling whether or not to let water flow.

[0030] An example of a case where X and Y are functionally connected is when the functional connection between X and Y is possible. Circuits that perform functions (e.g., logic circuits (inverters, NAND circuits, NOR circuits, etc.)), signal Conversion circuits (digital-analog conversion circuits, analog-to-digital conversion circuits, gamma correction circuits, etc.) ), potential level conversion circuits (power supply circuits (booster circuits, step-down circuits, etc.), voltage sources, current sources, switching circuits, amplifier circuits (such as level shifter circuits that can Circuits that can increase the amount of current, operational amplifiers, differential amplifier circuits, source follower circuits, buffer circuits, etc. There are one or more circuits between X and Y (e.g., a power supply circuit, a signal generating circuit, a memory circuit, a control circuit, etc.) It is possible to connect X and Y. For example, if another circuit is inserted between X and Y, However, if the signal output from X is transmitted to Y, then X and Y are functionally connected. It shall be.

[0031] When it is explicitly stated that X and Y are electrically connected, it means that X and Y are electrically connected. When X and Y are electrically connected (i.e., when another element or circuit is inserted between X and Y) X and Y are functionally connected (i.e., there is no connection between X and Y) When X and Y are connected directly, the two are functionally connected via another circuit. (That is, when X and Y are connected without any other element or circuit between them) In other words, when it is explicitly stated that something is electrically connected, it is not simply The same applies if the document is explicitly stated as being connected to the

[0032] Also, for example, "X and Y and the source (or first terminal, etc.) and drain ( or the second terminal, etc.) are electrically connected to each other, and X is the source of the transistor (or first terminal, etc.), the drain (or second terminal, etc.) of the transistor, and Y in that order. It can be expressed as "electrically connected to the source ( or the first terminal) is electrically connected to X, and the drain (or second terminal, etc.) is electrically connected to Y, and X, the source (or first terminal, etc.) of the transistor. , the drain (or second terminal, etc.) of the transistor, Y, are electrically connected in this order. Alternatively, "X is the source (or first terminal) of the transistor." The transistor is electrically connected to Y through the drain (or second terminal, etc.) and the transistor is electrically connected to X. The source (or first terminal, etc.) of the transistor, the drain (or second terminal, etc.) of the transistor (e.g., Y is provided in this connection order). By using a similar expression method to specify the order of connections in a circuit configuration, The source (or first terminal, etc.) and drain (or second terminal, etc.) of the transistor are connected to each other. The technical scope can be determined by distinguishing between the two. Note that these methods of expression are merely examples. , and is not limited to these representation methods. Here, X and Y represent objects (e.g., devices, elements, circuits, wiring, electrodes, terminals, conductive films, layers, etc.).

[0033] Note that the circuit diagram shows independent components as if they are electrically connected to each other. Even if one component has the functions of multiple components, For example, when a part of the wiring also functions as an electrode, one conductive film functions as both the wiring and the electrode. Therefore, the present invention has the functions of both the electrode and the electrode. Electrical connection means that one conductive film has the functions of multiple components. This case will also be included in that category.

[0034] In addition, in this specification, the term "resistance element" refers to a circuit element, wiring, etc. that has a resistance value. Therefore, in this specification, the term "resistance element" refers to a wiring having a resistance value, a source- This includes transistors, diodes, coils, etc., through which current flows between the drains. Therefore, the term "resistive element" is used in place of "resistance," "load," and "area with a resistive value." Conversely, the terms "resistance," "load," and "area with resistance" can be used interchangeably. The resistance value may be, for example, Preferably, the resistance is 1 mΩ or more and 10 Ω or less, more preferably 5 mΩ or more and 5 Ω or less, and even more preferably 10 mΩ or more. Ω or more and 1Ω or less. For example, it can be 1Ω or more and 1×10 9 Even below Ω good.

[0035] In this specification, the term "capacitive element" refers to a circuit element having a capacitance value, The capacitance may be a wiring area, a parasitic capacitance, or a gate capacitance of a transistor. Therefore, in this specification and the like, a "capacitance element" refers to a pair of electrodes and a capacitor included between the electrodes. Not only the circuit elements including dielectrics, but also the parasitic capacitance that appears between wirings, This includes the gate capacitance that appears between the gate and either the source or drain of the capacitor. In addition, terms such as "capacitance element," "parasitic capacitance," and "gate capacitance" are used in place of "capacitance." Conversely, the term "capacitance" can be translated as "capacitive element," "parasitic capacitance," or " The term "gate capacitance" can be used interchangeably with "pair of electrodes" in "capacitance." The term "pair of conductors," "pair of conductive regions," "pair of regions," etc. The capacitance value should be, for example, between 0.05 fF and 10 pF. Alternatively, the capacitance may be set to, for example, 1 pF or more and 10 μF or less.

[0036] In this specification, a transistor is referred to as a gate, a source, and a drain. The gate is a control terminal that controls the conduction state of the transistor. The two terminals that function as the source and drain are the input and output terminals of the transistor. The two input / output terminals are used to select the transistor conductivity type (n-channel, p-channel) and the Depending on the potential applied to the three terminals of the transistor, one becomes the source and the other becomes the drain. Therefore, in this specification and the like, the terms source and drain can be interchanged. In addition, in this specification and the like, when describing the connection relationship of a transistor, "One of the source and drain" (or first electrode, or first terminal), "the source or drain The term "second electrode" or "second terminal" is used. In some cases, a back gate is provided in addition to the three terminals described above. In this specification, either the gate or the back gate of a transistor is referred to as a first gate. The other of the gate or back gate of the transistor is sometimes called the second gate. Furthermore, the terms "gate" and "backgate" are interchangeable for the same transistor. In addition, if a transistor has three or more gates, In this specification, each gate is referred to as a first gate, a second gate, a third gate, etc. It is sometimes called.

[0037] In this specification, a node may be a terminal, a wiring, or the like depending on the circuit configuration, device structure, etc. It can be called a line, an electrode, a conductive layer, a conductor, an impurity region, etc. Wiring and the like can be called nodes in other words.

[0038] In addition, in this specification, the terms "voltage" and "potential" can be interchanged as appropriate. "Voltage" refers to the potential difference from a reference potential. For example, If we consider the ground potential as the earth potential, we can change the word "voltage" to "potential." The potential does not necessarily mean 0V. Note that the potential is relative and the reference Depending on the potential, the potential applied to the wiring etc. may be changed.

[0039] "Current" refers to the movement of electric charges (electrical conduction), for example, The statement "electrical conduction of negative charges is occurring in the opposite direction" should be interpreted as "electrical conduction of negative charges is occurring in the opposite direction." Therefore, in this specification, the term "current" is not particularly limited. Unless otherwise specified, the term refers to the phenomenon of charge transfer (electrical conduction) that accompanies the movement of carriers. The carriers mentioned here include electrons, holes, anions, cations, complex ions, etc., and the current The carriers differ depending on the system they flow in (e.g., semiconductor, metal, electrolyte, vacuum, etc.). In addition, the "direction of current" in wiring, etc. is the direction in which positive carriers move, and the amount of positive current is In other words, the direction in which negative carriers move is opposite to the direction of the current, Therefore, in this specification, the positive and negative currents (or the direction of the current) ), unless otherwise specified, a statement such as "current flows from element A to element B" should be interpreted as "current flows from element B to element B." This can be rephrased as "current flows from element A to element B." A description such as "current is input" can be rephrased as "current is output from element A" This shall be the case.

[0040] In addition, in this specification, the ordinal numbers "first," "second," and "third" are used to indicate constituent elements. Therefore, it does not limit the number of components. In addition, the order of the components is not limited. The element referred to as "first" in the above may be used in other embodiments or in the claims. In addition, for example, in the present specification, A component referred to as "first" in one embodiment may be used in other embodiments or in particular It may be omitted within the scope of the claims.

[0041] In addition, in this specification, terms indicating arrangement such as "above" and "below" refer to the relationship between components. The positional relationship may be used for convenience in explaining the configuration with reference to the drawings. The positional relationship between them changes depending on the direction in which each component is depicted. The terms are not limited to those explained in the detailed instructions, but can be rephrased appropriately depending on the situation. For example, the expression "insulator on top of conductor" means that the orientation of the drawing shown is rotated 180 degrees. By turning it around, it can be rephrased as "an insulator located on the underside of a conductor."

[0042] In addition, the terms "above" and "below" refer to the positional relationship of the components directly above or below and directly connected to each other. For example, if the expression is "electrode B on insulating layer A," The electrode B does not need to be formed directly on the insulating layer A, and the insulating layer A and the electrode B This does not exclude the inclusion of other components in between.

[0043] In addition, in this specification and the like, the terms "film" and "layer" may be used interchangeably depending on the situation. For example, the term "conductive layer" can be changed to the term "conductive film." Or, for example, the term "insulating film" may be changed to "insulating layer." In some cases, or depending on the circumstances, it may be possible to change the term to " For example, terms such as "film" and "layer" can be omitted and replaced with other terms. For example, the term "conductive layer" or "conductive film" may be changed to the term "conductor." Alternatively, for example, the terms "insulating layer" and "insulating film" may be changed to "insulator." It may be possible to change the term to

[0044] In addition, in this specification, terms such as "electrode," "wiring," and "terminal" refer to these components. It does not limit the function of the element. For example, "electrode" is used as part of "wiring." Furthermore, the terms "electrode" and "wiring" may be used interchangeably, and vice versa. This also includes cases where the "electrodes" and "wiring" are integrally formed. "Terminal" may be used as part of "wiring" or "electrode", and vice versa. Furthermore, the term "terminal" refers to a combination of multiple "electrodes," "wiring," "terminals," etc. For example, "electrode" is a "wiring" or a "terminal." For example, a "terminal" can be a part of a "wiring" or an "electrode." In addition, terms such as "electrode," "wiring," and "terminal" may be used interchangeably with terms such as "area." Which term may be substituted?

[0045] In addition, in this specification, terms such as "wiring," "signal line," and "power line" may be used interchangeably. Depending on the situation, they can be interchanged. For example, "wiring" It may be possible to change the term to "signal line". In some cases, it may be possible to change the term "wiring" to a term such as "power line." And vice versa, terms such as "signal line" and "power line" have been changed to "wiring." It may be possible to change terms such as "power line" to terms such as "signal line". In some cases, it is possible to use "signal line" instead of "power line." In addition, the term "potential" applied to the wiring can be changed to "voltage". In some cases or depending on the situation, the term "signal" may be changed to "signal" or similar. And vice versa, terms such as "signal" may be used in conjunction with "potential." It may be possible to change the term to something like this.

[0046] In this specification, impurities in a semiconductor are, for example, substances other than the main components constituting a semiconductor layer. For example, elements with a concentration of less than 0.1 atomic percent are considered impurities. This can result in the formation of DOS (Density of States) in semiconductors. In some cases, the carrier mobility may decrease, or the crystallinity may decrease. When the semiconductor is an oxide semiconductor, impurities that change the properties of the semiconductor include, for example, , Group 1 elements, Group 2 elements, Group 13 elements, Group 14 elements, Group 15 elements, other than the main component Transition metals, especially hydrogen (which is also contained in water), lithium, sodium, Silicon, boron, phosphorus, carbon, nitrogen, etc. Specifically, if the semiconductor is a silicon layer, In this case, impurities that change the properties of the semiconductor include, for example, oxygen and group 1 elements excluding hydrogen. These include the elements of Group 2, Group 13, and Group 15.

[0047] In this specification, a switch is a device that can be in a conducting state (ON state) or a non-conducting state (OFF state). It is a device that has the function of controlling whether or not current flows by entering a state where it is in a switched state. A switch is a device that has the function of selecting and switching the path through which current flows. , electrical switches, mechanical switches, etc. can be used. The device is not limited to a specific one as long as it can control the current.

[0048] An example of an electrical switch is a transistor (e.g., a bipolar transistor, MOS transistors, etc.), diodes (e.g., PN diodes, PIN diodes, Schottky diode, MIM (Metal Insulator Metal) die MIS (Metal Insulator Semiconductor) die diode-connected transistors, etc.), or logic circuits that combine these When using a transistor as a switch, the "conduction state" of the transistor This means that the source and drain electrodes of the transistor are considered to be electrically short-circuited. The "non-conducting state" of a transistor refers to the state in which the source electrode and drain electrode of the transistor are in a non-conducting state. This refers to a state in which the input electrode can be considered to be electrically disconnected. When operating as a switch, the polarity (conductivity type) of the transistor is not particularly limited.

[0049] An example of a mechanical switch is a MEMS (microelectromechanical system). There are switches that use stem technology. These switches are electrically operated switches that can be mechanically operated. It has poles, and the movement of these electrodes controls conduction and non-conduction.

[0050] In this specification, "parallel" means that two straight lines are arranged at an angle of -10° or more and 10° or less. Therefore, it includes the case where the angle is between -5° and 5°. "Parallel" or "approximately parallel" means that two straight lines are arranged at an angle of between -30° and 30°. Also, "perpendicular" means that two straight lines are arranged at an angle of 80° or more and 100° or less. Therefore, it also includes the case where the angle is between 85° and 95°. "Almost perpendicular" or "roughly perpendicular" means that two straight lines are arranged at an angle of 60° or more and 120° or less. This refers to a state in which something is happening. [Effects of the Invention]

[0051] According to one aspect of the present invention, a semiconductor device in which a hierarchical artificial neural network is constructed is provided. According to one embodiment of the present invention, a semiconductor device with low power consumption can be provided. Alternatively, according to one aspect of the present invention, it is possible to provide a device or the like that can reduce the influence of the temperature of the environment. According to one embodiment of the present invention, a semiconductor device or the like that is less susceptible to shock can be provided. It is possible to provide a semiconductor device that is less susceptible to variations in transistor characteristics. Alternatively, according to one embodiment of the present invention, a semiconductor device or the like that is less susceptible to variations in characteristics of a current source may be provided. Alternatively, one embodiment of the present invention can provide a novel semiconductor device or the like. It can be provided.

[0052] The effects of one embodiment of the present invention are not limited to the effects listed above. This does not preclude the existence of other effects. Other effects may be affected by this item, as described below. The effects not mentioned in this section are obvious to a person skilled in the art from the description or can be derived from the descriptions in the drawings, etc., and can be extracted appropriately from these descriptions. One aspect of the present invention is to achieve at least one of the effects listed above and other effects. Therefore, one aspect of the present invention may have the above-listed effects. In some cases, it may not have [Brief explanation of the drawings]

[0053] [Figure 1] 1A and 1B are diagrams illustrating a hierarchical neural network. [Figure 2] FIG. 2 is a circuit diagram showing an example of the configuration of a semiconductor device. [Figure 3] FIG. 3 is a circuit diagram showing an example of the configuration of a semiconductor device. [Figure 4] FIG. 4 is a circuit diagram showing an example of the configuration of a semiconductor device. [Figure 5] 5A, 5B, 5C, 5D, 5E, and 5F are circuit diagrams showing examples of the configuration of circuits included in the semiconductor device. [Figure 6] 6A, 6B, 6C, 6D, 6E, and 6F are circuit diagrams showing examples of the configuration of circuits included in the semiconductor device. [Figure 7] FIG. 7 is a circuit diagram showing an example of the configuration of a semiconductor device. [Figure 8] 8A, 8B, and 8C are circuit diagrams showing examples of the configuration of circuits included in the semiconductor device. [Figure 9] 9A, 9B, 9C, 9D, 9E, and 9F are circuit diagrams showing examples of the configuration of circuits included in the semiconductor device. [Figure 10] FIG. 10 is a circuit diagram showing an example of the configuration of a circuit included in a semiconductor device. [Figure 11] FIG. 11 is a circuit diagram showing an example of the configuration of a semiconductor device. [Figure 12] FIG. 12 is a circuit diagram showing an example of the configuration of a semiconductor device. [Figure 13] FIG. 13 is a circuit diagram showing an example of the configuration of a semiconductor device. [Figure 14] FIG. 14 is a circuit diagram showing an example of the configuration of a semiconductor device. [Figure 15] 15A, 15B, and 15C are circuit diagrams showing examples of the configuration of circuits included in the semiconductor device. [Figure 16] 16A and 16B are circuit diagrams showing examples of the configuration of circuits included in a semiconductor device. [Figure 17] 17A, 17B, and 17C are circuit diagrams showing examples of the configuration of circuits included in the semiconductor device. [Figure 18] 18A, 18B, and 18C are timing charts illustrating an example of the operation of the semiconductor device. [Figure 19] 19A, 19B, and 19C are timing charts illustrating an example of the operation of the semiconductor device. [Figure 20] 20A, 20B, and 20C are timing charts illustrating an example of the operation of the semiconductor device. [Figure 21] 21A and 21B are circuit diagrams showing examples of the configuration of circuits included in a semiconductor device. [Figure 22] 22A and 22B are circuit diagrams showing examples of the configuration of circuits included in a semiconductor device. [Figure 23] 23A and 23B are circuit diagrams showing examples of the configuration of circuits included in a semiconductor device. [Figure 24]FIG. 24 is a circuit diagram showing an example of the configuration of a circuit included in a semiconductor device. [Figure 25] FIG. 25 is a circuit diagram showing an example of the configuration of a circuit included in a semiconductor device. [Figure 26] FIG. 26 is a circuit diagram showing an example of the configuration of a circuit included in a semiconductor device. [Figure 27] FIG. 27 is a circuit diagram showing an example of the configuration of a circuit included in a semiconductor device. [Figure 28] FIG. 28 is a circuit diagram showing an example of the configuration of a circuit included in a semiconductor device. [Figure 29] FIG. 29 is a circuit diagram showing an example of the configuration of a circuit included in a semiconductor device. [Figure 30] 30A and 30B are circuit diagrams showing examples of the configuration of circuits included in a semiconductor device. [Figure 31] FIG. 31 is a circuit diagram showing an example of the configuration of a circuit included in a semiconductor device. [Figure 32] FIG. 32 is a circuit diagram showing an example of the configuration of a circuit included in a semiconductor device. [Figure 33] FIG. 33 is a circuit diagram showing an example of the configuration of a circuit included in a semiconductor device. [Figure 34] FIG. 34 is a circuit diagram showing an example of the configuration of a circuit included in a semiconductor device. [Figure 35] FIG. 35 is a circuit diagram showing an example of the configuration of a circuit included in a semiconductor device. [Figure 36] FIG. 36 is a circuit diagram showing an example of the configuration of a circuit included in a semiconductor device. [Figure 37] FIG. 37 is a circuit diagram showing an example of the configuration of a circuit included in a semiconductor device. [Figure 38] FIG. 38 is a circuit diagram showing an example of the configuration of a circuit included in a semiconductor device. [Figure 39] FIG. 39 is a circuit diagram showing an example of the configuration of a circuit included in a semiconductor device. [Figure 40] FIG. 40 is a circuit diagram showing an example of the configuration of a circuit included in a semiconductor device. [Figure 41] 41A, 41B, and 41C are circuit diagrams showing examples of the configuration of circuits included in the semiconductor device. [Figure 42] FIG. 42 is a circuit diagram showing an example of the configuration of a circuit included in a semiconductor device. [Figure 43] FIG. 43 is a circuit diagram showing an example of the configuration of a circuit included in a semiconductor device. [Figure 44] FIG. 44 is a circuit diagram showing an example of the configuration of a circuit included in a semiconductor device. [Figure 45] FIG. 45 is a circuit diagram showing an example of the configuration of a circuit included in a semiconductor device. [Figure 46] FIG. 46 is a circuit diagram showing an example of the configuration of a circuit included in a semiconductor device. [Figure 47] 47A and 47B are circuit diagrams showing examples of the configuration of a circuit included in a semiconductor device. [Figure 48] 48A, 48B, and 48C are timing charts illustrating an example of the operation of the semiconductor device. [Figure 49] 49A, 49B, and 49C are timing charts illustrating an example of the operation of the semiconductor device. [Figure 50] FIG. 50 is a circuit diagram showing an example of the configuration of a circuit included in a semiconductor device. [Figure 51] FIG. 51 is a circuit diagram showing an example of the configuration of a circuit included in a semiconductor device. [Figure 52] FIG. 52 is a circuit diagram showing an example of the configuration of a circuit included in a semiconductor device. [Figure 53] FIG. 53 is a circuit diagram showing an example of the configuration of a circuit included in a semiconductor device. [Figure 54] 54A and 54B are circuit diagrams showing examples of the configuration of circuits included in a semiconductor device. [Figure 55] 55A, 55B, and 55C are circuit diagrams showing examples of the configuration of circuits included in the semiconductor device. [Figure 56] 56A and 56B are circuit diagrams showing examples of the configuration of circuits included in a semiconductor device. [Figure 57] FIG. 57 is a circuit diagram showing an example of the configuration of a circuit included in a semiconductor device. [Figure 58] FIG. 58 is a circuit diagram showing an example of the configuration of a circuit included in a semiconductor device. [Figure 59]FIG. 59 is a circuit diagram showing an example of the configuration of a circuit included in a semiconductor device. [Figure 60] FIG. 60 is a circuit diagram showing an example of the configuration of a circuit included in a semiconductor device. [Figure 61] FIG. 61 is a cross-sectional view illustrating the configuration of a semiconductor device. [Figure 62] FIG. 62 is a cross-sectional view illustrating the configuration of a semiconductor device. [Figure 63] 63A, 63B, and 63C are cross-sectional schematic views illustrating the configuration of a semiconductor device. [Figure 64] 64A and 64B are cross-sectional schematic views illustrating examples of the configuration of a transistor. [Figure 65] FIG. 65 is a schematic cross-sectional view illustrating an example of the configuration of a semiconductor device. [Figure 66] 66A and 66B are cross-sectional schematic views illustrating examples of the configuration of a transistor. [Figure 67] FIG. 67 is a schematic cross-sectional view illustrating an example of the configuration of a semiconductor device. [Figure 68] FIG. 68A is a top view showing an example of the configuration of a capacitor, and FIGS. 68B and 68C are cross-sectional perspective views showing an example of the configuration of a capacitor. [Figure 69] FIG. 69A is a top view showing an example of the configuration of a capacitor, FIG. 69B is a cross-sectional view showing an example of the configuration of a capacitor, and FIG. 69C is a cross-sectional perspective view showing an example of the configuration of a capacitor. [Figure 70] FIG. 70A is a perspective view showing an example of a semiconductor wafer, FIG. 70B is a perspective view showing an example of a chip, and FIGS. 70C and 70D are perspective views showing an example of an electronic component. [Figure 71] FIG. 71 is a perspective view showing an example of an electronic device. [Figure 72] 72A, 72B, and 72C are perspective views showing examples of electronic devices. DETAILED DESCRIPTION OF THE INVENTION

[0054] In artificial neural networks (hereafter referred to as neural networks), ,The connection strength of the synapses is determined by providing existing information to the neural ,network. In this way, we can feed the neural network with existing information and generate results. The process of determining the combined strength is sometimes called "learning."

[0055] In addition, no action is taken against the neural network that has undergone "learning" (the connection weights have been determined). By providing some information, new information can be output based on the connection strength. In this way, neural networks make decisions based on the given information and connection strengths. The process of generating new information through neural networks is sometimes called "inference" or "cognition."

[0056] Neural network models include, for example, Hopfield and hierarchical types. In particular, neural networks with multi-layer structures are called "deep neural networks." They call machine learning using deep neural networks "DNNs" and call machine learning using deep neural networks " It is sometimes called "deep learning."

[0057] In this specification, the term "metal oxide" refers to a metal in a broad sense. Metal oxides are oxides of the following: oxide insulators, oxide conductors (including transparent oxide conductors), ), oxide semiconductors (also called oxide semiconductors or simply OS), For example, when a metal oxide is used in the active layer of a transistor, the metal oxide In other words, metal oxides have amplifying, rectifying, and and forming a channel forming region of a transistor having at least one of a switching function and a If possible, the metal oxide is referred to as a metal oxide semiconductor. It can be abbreviated as OS, and is also called OS transistor. In this case, the transistor may be referred to as a transistor including a metal oxide or an oxide semiconductor. can be done.

[0058] In this specification and the like, metal oxides containing nitrogen are also referred to as metal oxides (metal ox). Metal oxides containing nitrogen are sometimes collectively called metal oxynitrides (metal oxynitrides). It may also be called tal oxynitride.

[0059] In addition, in this specification and the like, the configurations shown in each embodiment may be interchangeable with the configurations shown in other embodiments. The above-described embodiments can be combined appropriately to form one aspect of the present invention. When multiple configuration examples are shown, the configuration examples can be combined with each other as appropriate.

[0060] It should be noted that the contents (or even a part of the contents) described in one embodiment may be used in the implementation of the embodiment. Another content (or part of the content) described in the embodiment and one or more other embodiments The content described (or a part of the content) is applied to, combined with, or at least one of the contents. or replacement, etc.

[0061] The contents described in the embodiments are explained using various drawings in each embodiment. This refers to the content stated in the specification or the content stated using the text in the specification.

[0062] In addition, a drawing (or a part thereof) described in one embodiment may be replaced with another part of the drawing. In the embodiment, another figure (or a part thereof) and one or more other embodiments may be used. At least one of the drawings (or a part thereof) described in the embodiment is combined with By adding more, more figures can be constructed.

[0063] The embodiments described in this specification are explained with reference to the drawings. The present invention may be embodied in many different forms without departing from the spirit and scope thereof. It will be readily understood by those skilled in the art that various changes in form and details can be made without departing from the spirit and scope of the present invention. Therefore, the present invention should not be construed as being limited to the description of the embodiment. In the configuration of the invention of the embodiment, the same parts or parts having similar functions are designated by the same reference numerals. The same elements are used in different drawings, and repeated explanations may be omitted. In some cases, in order to ensure clarity of the drawings, some components may be omitted. be.

[0064] In this specification and the like, when the same reference numeral is used for a plurality of elements, it is not necessary to distinguish them. When necessary, a distinguishing code such as "_1", "[n]", or "[m,n]" is added to the code. It may be stated in writing.

[0065] Also, in the drawings of this specification, the size, layer thickness, or area may be exaggerated for clarity. Therefore, the drawings are not necessarily limited to the scale. The drawings are merely conceptual examples, and are not limited to the shapes or values shown in the drawings. For example, variations in signal, voltage, or current due to noise, or timing errors This can include variations in signal, voltage, or current.

[0066] In this specification, the expression "In:Ga:Zn=4:2:3 or its vicinity" refers to the atomic ratio of In:Ga:Zn=4:2:3 or its vicinity. For the total number of atoms, when In is 4, Ga is 1 or more and 3 or less (1 ≤ Ga ≤ 3), and Zn is 2 or more and 4.1 or less (2 ≤ Zn ≤ 4.1). Also, In:Ga:Zn = 5:1:6 Or in the vicinity thereof means that when In is 5 with respect to the total number of atoms, Ga is greater than 0.1 and 2 or less (0.1 < Ga ≤ 2), and Zn is 5 or more and 7 or less (5 ≤ Zn ≤ 7). Also , In:Ga:Zn = 1:1:1 or in the vicinity thereof means that when In is 1 with respect to the total number of atoms , Ga is greater than 0.1 and 2 or less (0.1 < Ga ≤ 2), and Zn is greater than 0.1 and 2 or less (0.1 < Zn ≤ 2). Also, In:Ga:Zn = 5:1:3 or in the vicinity thereof means that when In is 5 with respect to the total number of atoms, Ga is 0.5 or more and 1.5 or less ( 0.5 ≤ Ga ≤ 1.5), and Zn is 2 or more and 4.1 or less (2 ≤ Zn ≤ 4.1). Also, In:Ga:Zn = 10:1:3 or in the vicinity thereof means that when In is 10 with respect to the total number of atoms, Ga is 0.5 or more and 1.5 or less (0.5 ≤ Ga ≤ 1.5), and Zn is 2 or more and 4.1 or less (2 ≤ Zn ≤ 4.1). Also, In:Zn = 2:1 or in the near vicinity thereof means that when In is 1 with respect to the total number of atoms, Zn is greater than 0.25 and less than 0.75 (0.25 < Zn ≤ 0.75). Also, In:Zn = 5:1 or in the vicinity thereof means that when In is 1 with respect to the total number of atoms, Zn is greater than 0.12 and 0.25 or less (0 .12 < Zn ≤ 0.25). Also, In:Zn = 10:1 or in the vicinity thereof means that for the total number of atoms, when In is 1, Zn is greater than 0.07 and 0.12 or less (0.0 7 < Zn ≤ 0.12). (Embodiment 1) (Embodiment 1)

[0067] (Embodiment 1) In this embodiment, a semiconductor device according to one embodiment of the present invention is a neural network processor. The arithmetic circuit that performs the calculation will be described.

[0068] <Hierarchical neural network> First, we will explain about hierarchical neural networks. For example, the network has one input layer, one or more intermediate layers (hidden layers), and one output layer. The hierarchical neural network shown in Figure 1A has three or more layers. Neural network 100 is an example of such a network. The layer has R layers (where R can be an integer of 4 or greater). The first layer corresponds to the input layer, the Rth layer corresponds to the output layer, and the other layers correspond to the intermediate layers. In addition, in FIG. 1A, the (k-1)th layer and the kth layer (where k is 3 or more, R-1) are shown as intermediate layers. The following integers are used.) are shown in the figure, and other intermediate layers are omitted from the illustration. .

[0069] Each layer of the neural network 100 has one or more neurons. In this case, the first layer is made up of neurons N1 (1) Neuron N p (1) (where p is 1 or more ) and the (k-1)th layer has neurons N1 (k-1) Neuron N m (k-1) (where m is an integer greater than or equal to 1), and the kth layer has neurons N1 ( k) Neuron N n (k) (where n is an integer equal to or greater than 1), and the Rth layer is Neuron N1 (R) Neuron Nq (R) (where q is an integer greater than or equal to 1.) It has.

[0070] In addition, in Figure 1A, neuron N1 (1) , neuron N p (1) , neuron N1 ( k-1) , neuron N m (k-1) , neuron N1 (k) , neuron N n (k) , Neuron N1 (R) , neuron N q (R) In addition, the (k-1)th layer neuron N i (k-1) (where i is an integer between 1 and m), and the kth layer neuron N j ( k) (where j is an integer between 1 and n) are also shown. The illustration of the .

[0071] Next, the transmission of signals from the neurons in the previous layer to the neurons in the next layer, and the In this explanation, we will explain the signals input and output in the k-th layer of the neural network. N j (k) We are focusing on the following.

[0072] Figure 1B shows the kth layer neuron N j (k) and neuron N j (k) The signal input to and neuron N j (k) 10 shows the signal output from the

[0073] Specifically, the neuron N1 in the (k-1)th layer(k-1) Neuron N m (k-1 ) The output signal z1 (k-1) ~z m (k-1) But neuron N j ( k) The output is directed to neuron N j (k) is z1 (k-1) ~z m (k-1) Depending on z j (k) Generate z j (k) is used as the output signal The output is directed to each neuron in the layer (not shown).

[0074] The signals input from the neurons in the previous layer to the neurons in the next layer are transmitted between those neurons. The strength of the synapse (hereafter referred to as the weighting coefficient) that connects the In the neural network 100, the output from the previous layer neuron is The signal is multiplied by the corresponding weighting coefficient and input to the neuron in the next layer. The (k-1)th layer neuron N i (k-1) and the k-th layer neuron N j (k) The weight coefficient of the synapse between i (k-1) j (k) Then, the k-th layer Newron N j (k) The signal input to can be expressed by equation (1.1).

[0075]

number

[0076] That is, the neuron N1 in the (k-1)th layer (k-1) Neuron N m (k-1) of From each, the k-th layer neuron N j (k) When a signal is transmitted to the (k-1) ~z m (k-1) The weighting coefficients w1 corresponding to each signal are (k-1) j (k) Or even w m (k-1) j (k) Then, the k-th layer neuron N j ( k) has w1 (k-1) j (k) z1 (k-1) Or even w m (k-1) j (k) z m (k-1) is input. At this time, the k-th layer neuron N j (k) of the signal input to Sumwau j (k) is expressed as equation (1.2).

[0077]

number

[0078] Also, the weighting factor w1 (k-1) j (k) Or even w m (k-1) j (k) and neurons signal z1 (k-1) ~z m(k-1) The result of the sum of products of and is biased. When the bias is b, equation (1.2) can be rewritten as .

[0079]

number

[0080] Neuron N j (k) u j (k) Depending on j (k) Generates And neuron N j (k) Output signal z from j (k) is defined as follows:

[0081]

number

[0082] The function f(u j (k) ) is the activation function in a hierarchical neural network , step function, linear ramp function, sigmoid function, etc. The activation function may be the same for all neurons or may be different. Therefore, the activation functions of neurons in each layer may be the same or different.

[0083] By the way, the signal output by the neuron in each layer, the weight coefficient w, or the bias b is The value may be an analog value or a digital value. For example, the digital value may be a binary value. It may be a ternary value, or a value with an even larger number of bits. For analog values, the activation function can be, for example, a linear ramp function or a sigmoid function. In the case of binary digital values, for example, the output can be set to -1 or 1, or 0 or A step function with a value of 1 or less can be used. The signal output by the neurons in each layer is It may be three or more values. For example, an activation function that outputs three values may be three or more values, For example, a step function with outputs of -1, 0, or 1, or 0, 1, or 2. For example, an activation function that outputs five values can be A step function of -2, -1, 0, 1, or 2 may also be used. For at least one of the signals output by the RON, the weighting coefficient w, or the bias b, By using digital values, the circuit scale can be reduced and power consumption can be reduced. Or, the calculation speed can be increased. Also, the neurons in each layer For at least one of the input signal, weighting coefficient w, or bias b, the By using the logarithm, the accuracy of the calculation can be improved.

[0084] The neural network 100 receives an input signal at the first layer (input layer). Therefore, in each layer from the first layer (input layer) to the last layer (output layer), the input from the previous layer is sequentially Based on the input signal, equation (1.1), equation (1.2) (or equation (1.3)), equation (1.4) The output signal is generated using the sigma-based algorithm, and the output signal is output to the next layer. The signal output from the input layer is converted into the result calculated by the neural network 100. Equivalent.

[0085] <Example of arithmetic circuit configuration> Here, in the above-described neural network 100, the equation (1.2) (or the equation (1 .3)) and an example of an arithmetic circuit that can perform the calculation of equation (1.4) will be described. In the arithmetic circuit, as an example, the synaptic circuit of the neural network 100 The weighting coefficient of the path is set as a combination of two values ("-1" and "+1" or "0" and "+1"). ), 3-value (combination of "-1", "0", "1", etc.), or multiple values of 4 or more. Value (for five values, a combination of "-2", "-1", "0", "1", "2", etc.) The activation function of a neuron is a binary combination of "-1" and "+1" or "0" and "+1" " combinations, etc.), 3-value (combinations of "-1", "0", "1", etc.), 4-value or more A function that outputs multiple values (for four values, a combination of "0", "1", "2", "3", etc.) In this specification, the weight coefficients and the number of neurons from the previous layer to the next layer are The value of the signal input to the The first data may be referred to as the first data, and the other as the second data. The weight coefficients and calculation values of the synapse circuits of the network 100 are not limited to digital values. It is also possible to use analog values for at least one of the signals.

[0086] The arithmetic circuit 110 shown in FIG. 2 includes, for example, an array section ALP, a circuit ILD, and a circuit W The semiconductor device includes an LD, a circuit XLD, and a circuit AFP. Neuron N1 in the kth layer in Figure 1A and Figure 1B (k) Neuron N n (k) to Input signal z1 (k-1) ~z m (k-1)and neuron N1 (k) No To Neuron N n (k) The signal z1 output from each (k) ~z n (k) Generate This is a circuit that:

[0087] The entire arithmetic circuit 110 or a part of it may be implemented as a neural network or It may be used for purposes other than AI. For example, it may be used for graphics calculations or scientific calculations. In the case of performing a sum-of-products operation or a matrix operation, the entire operation circuit 110 or a part thereof You can use a part of it to perform processing. In other words, it can be used not only for AI calculations but also for general calculations. For this purpose, the entire arithmetic circuit 110 or a part thereof may be used.

[0088] The circuit ILD includes, for example, wirings IL[1] to IL[n] and wirings ILB[1]. The circuit WLD is electrically connected to the wirings WL[n] to ILB[n]. The circuit XLD is electrically connected to wirings S[1] to WLS[m]. The circuit AFP is electrically connected to the wiring XLS[1] to the wiring XLS[m]. The wiring OL[1] to wiring OL[n], the wiring OLB[1] to wiring OLB[n], is electrically connected to

[0089] <<Array section ALP>> The array unit ALP has, for example, m×n circuits MP. are arranged in a matrix of m rows and n columns in the array section ALP. In Figure 2, the i-th row and j-th column (where i is an integer between 1 and m, and j is an integer between 1 and n) The circuit MP located at i,j is expressed as circuit MP[i,j]. is the circuit MP[1,1], the circuit MP[m,1], the circuit MP[i,j], the circuit MP[1,n ], and only the circuit MP[m,n] is shown, and the other circuits MP are omitted. are.

[0090] For example, the circuit MP[i,j] includes a wiring IL[j], a wiring ILB[j], and a wiring W LS[i], wiring XLS[i], wiring OL[j], and wiring OLB[j] are electrically is connected to.

[0091] The circuit MP[i,j] is, for example, a neuron N i (k-1) and neuron N j (k ) The weighting coefficient between the first data and the second data (sometimes referred to as either the first data or the second data) Specifically, the circuit MP[i,j] has the function of storing the first data. The first data (weighting coefficient) input from the wiring IL[j] and the wiring ILB[j] is It stores information (such as potential, resistance, and current). Also, the circuit MP[i,j] is , neuron N i (k-1) The signal z output from i (k-1) (First data or second data The product of the first data and the second data (sometimes referred to as the other data). As a specific example, the circuit MP[i,j] has a function of outputting the wiring XLS[i ] to the second data z i (k-1) By inputting, the product of the first data and the second data is information (e.g., current, voltage, etc.) according to the first data and the second data, or Information (e.g., current, voltage, etc.) is output to the wiring OL[j] and wiring OLB[j]. Although an example in which the wiring IL[j] and the wiring ILB[j] are arranged has been shown, One aspect of the present invention is not limited to this. Only the above may be arranged.

[0092] <<Circuit ILD>> The circuit ILD includes, for example, wirings IL[1] to IL[n] and wirings ILB[1]. through wiring ILB[n] and the circuits MP[1,1] to MP[m,n]. For each of these, the first data w1 (k-1) 1 (k) Or even w m (k-1) n (k) The device has a function of inputting information (for example, potential, resistance value, current value, etc.) corresponding to the above. As a specific example, the circuit ILD is a first weighting coefficient for the circuit MP[i,j]. Data W i (k-1) j (k) Information corresponding to the potential, resistance, or current ) are supplied by wiring IL[j] and wiring ILB[j].

[0093] <<Circuit XLD>> For example, the circuit XLD is connected to the circuit M via wirings XLS[1] to XLS[n]. For each of P[1,1] to MP[m,n], neuron N1 (k-1) No To Neuron N m (k) The second data z1 corresponds to the calculated value output from (k-1) ~ z m (k-1) Specifically, the circuit XLD has a function of supplying the circuit MP[i,1 ] or circuit MP[i,n], neuron N i (k-1) The second data output from Taz i (k-1) The information corresponding to the wiring XLS[i] (for example, potential, current value, etc.) Although an example in which the wiring XLS[i] is arranged has been shown, For example, in the arithmetic circuit 110 of FIG. [i] may be a plurality of wires. As a specific example, FIG. The wire XLS[i] electrically connected to P[i,j] is the wire X1L, the wire X2L The figure shows the arithmetic circuit 120 in which the wiring XLS[i] is replaced by two. However, one embodiment of the present invention is not limited to this. ], for example, a separate wire that transmits the inverted signal of the signal input to wire XLS[i] It may be arranged.

[0094] <<Circuit WLD>> For example, the circuit WLD receives information (for example, It has the function of selecting the circuit MP to which data (for example, potential, resistance value, current value, etc.) is written. For example, the circuits MP[i,1] to MP[i,n] located in the i-th row of the array unit ALP When writing information (for example, potential, resistance value, current value, etc.) to the circuit WLD, For example, the write switching elements included in the circuits MP[i,1] to MP[i,n] A signal to turn on or off the child is supplied to the wiring WLS[i], and the child is turned on or off in the other rows. A potential that turns off the write switching element included in the circuit MP is supplied to the wiring WLS. Although an example in which the wiring WLS[i] is arranged has been shown, In one embodiment, the present invention is not limited to this. In addition to the wiring WLS[i], for example, A separate wiring may be provided to transmit an inverted signal of the input signal.

[0095] In addition, the arithmetic circuit 110 in FIG. 2 shows a configuration example in which wiring WLS[i] is arranged. However, one embodiment of the present invention is not limited to this. For example, the wiring X1L[i] of the arithmetic circuit 120 in FIG. Also used as a selection signal line for writing information to circuits MP[i,1] to MP[i,n] Specifically, as in the arithmetic circuit 130 shown in FIG. 1L[i] is the wiring WX1L[i], and the wiring WX1L is connected to the circuit WLD and the circuit XLD. , may be electrically connected to the wiring WX1L[i]. to turn on or off the write switching element included in the circuit MP[i,n] When a signal for making the output of the circuit XLD is supplied from the circuit WLD, the circuit XLD is connected to the wiring WX It is preferable that the wiring WX1L[i] has a function of making the wiring WX1L[i] non-conductive. via neuron N1 (k-1) Neuron N m (k) The calculated value output from Corresponding second data z1 (k-1) ~z m (k-1) The signal from the circuit WLD to the circuit MP[ When supplying the power to the circuits MP[i,1] to MP[i,n], the circuit WLD is connected to the wiring WX It is preferable that the electrode has a function of making the electrode and 1L electrically disconnected.

[0096] <<Circuit AFP>> The circuit AFP includes, for example, circuits ACTF[1] to ACTF[n]. The circuit ACTF[j] is, for example, a combination of wiring OL[j] and wiring OLB[j]. The circuit ACTF[j] is electrically connected to the wiring OL[j], for example. and the wiring OLB[j] according to the information (e.g., potential, current value, etc.) input. For example, the signal input from the wiring OL[j] and wiring OLB[j] is generated. Each piece of information (e.g., potential, current value, etc.) is compared, and a signal is generated according to the comparison result. The signal is sent to neuron N j (k) The signal z output from j (k) It is equivalent to That is, the circuits ACTF[1] to ACTF[n] are, for example, the above-mentioned neural However, in one aspect of the present invention, For example, the circuits ACTF[1] to ACTF[n] are The circuit may have the function of converting the log signal into a digital signal. F[1] to ACTF[n] are circuits that amplify and output analog signals. Alternatively, for example, the circuit ACTF[ The circuits ACTF[1] to ACTF[n] may have a function of converting current or charge into voltage. For example, the circuits ACTF[1] to ACTF[n] may be connected to the wiring OL[j] and the wiring O It may have a function to initialize the potential of LB[j].

[0097] The arithmetic circuit 110, the arithmetic circuit 120, and the arithmetic circuit 13 shown in FIGS. 2 to 4, respectively, In the example of FIG. 0, an example in which the circuit ACTF is arranged is shown. For example, the circuit ACTF does not necessarily have to be arranged in the circuit AFP.

[0098] Next, the circuits ACTF[1] to ACTF[n] will be described. 1] to the circuit ACTF[n] can have the circuit configuration shown in FIG. 5A as an example. As an example, FIG. 5A shows the current flowing through the wiring OL[j] and wiring OLB[j]. and signal z j (k) Specifically, FIG. 5A shows a circuit that generates a binary The output signal z j (k) 1 shows an example of an activation function calculation circuit that outputs

[0099] In FIG. 5A, the circuit ACTF[j] includes a resistor RE, a resistor REB, and a comparator CMP. The resistors RE and REB have the function of converting current into voltage. Any element or circuit that has the function of converting voltage is not limited to a resistor. j] is electrically connected to the first terminal of the resistor RE and the first input terminal of the comparator CMP, and The line OLB[j] is electrically connected to the first terminal of the resistor REB and the second input terminal of the comparator CMP. The second terminal of the resistor RE is electrically connected to the wiring VAL, and the second terminal of the resistor R The second terminal of EB is electrically connected to the wiring VAL. The second terminal of the resistor REB may be connected to the same wiring. It may be connected to another wire.

[0100] It is preferable that the resistance values of the resistors RE and REB are equal to each other. For example, The difference in resistance between the resistors RE and REB should be within 10%, more preferably, 5% or less. However, one aspect of the present invention is not limited to this. In some cases, or depending on the situation, the resistance values of the resistors RE and REB may be different from each other. It may be a different value.

[0101] The wiring VAL functions as a wiring that applies a constant voltage, for example. For example, VDD is a high-level potential, VSS is a low-level potential, and GND is a ground potential. ) etc. The constant voltage can be set appropriately depending on the configuration of the circuit MP. It is also preferable that a pulse signal, not a constant voltage, is supplied to the wiring VAL. It may also be used.

[0102] The voltage between the first and second terminals of the resistor RE is proportional to the current flowing from the wire OL[j]. Therefore, the first input terminal of the comparator CMP is determined in accordance with the resistance value of the resistor RE and the voltage Similarly, the voltage between the first and second terminals of the resistor REB is , is determined according to the current flowing from the wiring OLB[j]. A voltage corresponding to the resistance value of the resistor REB and the current is input to the input terminal.

[0103] As an example, the comparator CMP receives the signals input to the first input terminal and the second input terminal. A function that compares voltages and outputs a signal from the output terminal of the comparator CMP according to the comparison result. For example, the comparator CMP has a function of detecting a voltage at the second input terminal that is higher than the voltage input at the first input terminal. When the voltage input to the terminal is high, a high level potential is output from the output terminal of the comparator CMP. When the voltage input to the first input terminal is higher than the voltage input to the second input terminal, the low level The bell potential can be output from the output terminal of the comparator CMP. The potential output from the output terminal can be either high level or low level. Output signal z output by ACTF[j] j (k) can be binary. For example, the comparison The high-level potential and low-level potential output from the output terminal of the CMP are output signals z j (k) It can correspond to "+1" and "-1". The high-level potential and the low-level potential output from the output terminal of the comparator CMP are signal z j (k) may correspond to "+1" and "0".

[0104] In addition, in the circuit ACTF[j] of FIG. 5A, resistors RE and REB are used, but Any element or circuit that has the function of converting voltage into a voltage is not limited to a resistor. The resistors RE and REB in the 5A circuit ACTF[j] can be replaced with other circuit elements. For example, the circuit ACTF[j] shown in FIG. 5B is included in the circuit ACTF[j] of FIG. 5A. The resistors RE and REB in the circuit are replaced with capacitors CE and CEB. The circuit ACTF[j] can perform almost the same operation as the circuit ACTF[j]. It is preferable that the capacitance values of the capacitances of the capacitances CE and B are equal to each other. The difference in capacitance value of each CEB should be within 10%, more preferably within 5%. However, one aspect of the present invention is not limited to this. A circuit for initializing the charge stored in the capacitor E and the capacitor CEB may be provided. A switch may be provided in parallel with the capacitor CE. That is, the second terminal of the switch may be connected to the capacitor CE. The first terminal of the switch is connected to the first terminal of the capacitor CE, the wiring OL[j], and and may be connected to the first input terminal of the comparator CMP. The terminal is connected to a wiring different from the wiring VAL, and the first terminal of the switch is connected to the first terminal of the capacitor CE. The terminal may be connected to the wiring OL[j] and the first input terminal of the comparator CMP. In addition, the circuit ACTF[j] shown in FIG. 5C has a resistor R This is a circuit in which E and resistor REB are replaced with diode elements DE and DEB. , it can perform almost the same operation as the circuit ACTF[j] in FIG. 5A. E, the direction of the diode element DEB (the connection point between the anode and cathode) is It is desirable to change it appropriately depending on the magnitude of the order.

[0105] In addition, the comparator CMP included in the circuit ACTF[j] of FIGS. 5A to 5C is, for example, , can be replaced by an operational amplifier OP. The circuit ACTF[j] shown in Figure 5D can be The circuit diagram shows the circuit ACTF[j] in A, where the comparator CMP is replaced with an operational amplifier OP. do.

[0106] In addition, even if the switch S01a and the switch S01b are provided in the circuit ACTF[j] of FIG. 5B, As a result, the circuit ACTF[j] has the capacitance CE and the capacitance CEB connected to the wiring OL [j], a potential according to the current input from the wiring OLB[j] can be maintained. As an example of a specific circuit, as shown in FIG. 5E, a The line OL[j] is electrically connected to the second terminal of the switch S01a, and the first terminal of the capacitor CE is connected to the second terminal of the switch S01a. The first input terminal of the comparator CMP is electrically connected to the first terminal of the switch S01b. OLB[j] is electrically connected, and the first terminal of the capacitor CEB is connected to the second terminal of the switch S01b. and the second input terminal of the comparator CMP are electrically connected. In ACTF[j], the first and second input terminals of the comparator CMP are wired When inputting the potential of OL[j] and wiring OLB[j], switch S01a and switch S0 1b to the ON state. By turning off the switches S01a and S01b, the comparator CMP The potentials input to the first and second input terminals are held in the capacitors CE and CEB. The switches S01a and S01b may be, for example, analog switches. An electrical switch such as a switch or a transistor can be applied. As the switch S01a and the switch S01b, for example, a mechanical switch may be applied. When transistors are used for the switches S01a and S01b, the transistors The transistor is an OS transistor or a transistor having silicon in the channel formation region ( Hereinafter, this will be referred to as a Si transistor.) Alternatively, the switch S01a , and the period during which the switches S01b and S01b are kept in the ON state is controlled. For example, the voltage value of the capacitors CE and CEB can be controlled. When the current value is large, the switches S01a and S01b are turned on. By shortening the period during which the capacitors are turned off, the voltage values of the capacitors CE and CEB become larger. It can prevent too much.

[0107] The comparator CMP included in the circuit ACTF[j] of FIGS. 5A to 5C and 5E is, for example, For example, a chopper type comparator can be used. The comparator CMP shown in FIG. The comparator CMP is a comparator of the type shown in FIG. The inverter circuit INV3 includes a switch S02, a capacitor CC, and an inverter circuit INV3. a, switch S02b, and switch S03 are the same as the switches S01a and S01 As with b, transistors such as mechanical switches, OS transistors, and Si transistors It can be used as a data.

[0108] The first terminal of the switch S02a is electrically connected to the terminal VinT, and the second terminal of the switch S02b is electrically connected to the terminal VinT. A first terminal of the switch S02a is electrically connected to the terminal VrefT, and a second terminal of the switch S02b is electrically connected to the terminal VrefT. The second terminal of the switch S02b is electrically connected to the first terminal of the capacitor CC. The second terminal of CC is connected to the input terminal of the inverter circuit INV3 and the first terminal of the switch S03. , and the terminal VoutT is electrically connected to the output terminal of the inverter circuit INV3. , and the second terminal of the switch S03.

[0109] The terminal VinT functions as a terminal for inputting the input potential to the comparator CMP, and the terminal V refT functions as a terminal for inputting a reference potential to the comparator CMP, and the terminal Vout T functions as a terminal for outputting the output potential from the comparator CMP. nT corresponds to either the first terminal or the second terminal of the comparator CMP in FIGS. 5A to 5C and 5E. The terminal VrefT corresponds to the first or second terminal of the comparator CMP shown in FIGS. 5A to 5C and 5E. It can correspond to the other child.

[0110] The circuit ACTF[j] of FIGS. 5A to 5E outputs an output signal z j (k) The activation function circuit ACTF[j] outputs the output signal z j (k) of The output may be three or more values or an analog value.

[0111] 6A to 6F show the currents input from the wiring OL[j] and wiring OLB[j]. , signal z j (k) is a circuit that generates an output signal z represented by a ternary value. j (k) Exit 1 shows an example of a calculation circuit for the input activation function.

[0112] The circuit ACTF[j] shown in FIG. 6A includes a resistor RE, a resistor REB, a comparator CMPa, and a comparator The wiring OL[j] is connected to the first terminal of the resistor RE and the first input of the comparator CMPa. The wire OLB[j] is electrically connected to the first terminal of the resistor REB and the comparator C The first input terminal of the comparator MPb is electrically connected to the second input terminal of the comparator CMPa. The input terminal of the comparator CMPb and the second input terminal of the comparator CMPb are electrically connected to the wiring VrefL. Furthermore, the second terminal of the resistor RE is electrically connected to the wiring VAL, and the second terminal of the resistor REB is is electrically connected to the wiring VAL.

[0113] The wiring VrefL is a constant voltage V ref acts as a voltage line that gives V ref For example, , it is preferable that it is above GND and below VDD. ref is G It may be a potential lower than ND or higher than VDD. ref is the comparator CMPa, It is used as a reference potential (potential for comparison) in the comparator CMPb.

[0114] The voltage between the first and second terminals of the resistor RE is proportional to the current flowing from the wire OL[j]. Therefore, the first input terminal of the comparator CMPa is determined in accordance with the resistance value of the resistor RE and the A voltage corresponding to the current is input. Similarly, the voltage between the first and second terminals of the resistor REB is is determined according to the current flowing from the wiring OLB[j]. A voltage according to the resistance value of the resistor REB and the current is input to the first input terminal.

[0115] The comparator CMPa compares the voltages input to the first input terminal and the second input terminal. Then, a signal is output from the output terminal of the comparator CMPa according to the comparison result. The comparator CMPa detects that the voltage input to the second input terminal ( V ref ) is high, a high-level potential is output from the output terminal of the comparator CMPa, and a high-level potential is output from the second input terminal The voltage (V ref ) when the voltage input to the first input terminal is higher than , a low level potential can be output from the output terminal of the comparator CMPa.

[0116] Similar to the comparator CMPa, the comparator CMPb has a first input terminal and a second input terminal. The voltage input to the comparator CMPb is compared with the voltage input to the comparator CMPb, and a signal is output from the output terminal of the comparator CMPb according to the comparison result. For example, the comparator CMPb outputs a signal when the voltage input to the second input terminal is lower than the voltage input to the first input terminal. The voltage (V ref ) is high, the high level potential is output from the comparator CMPb. The voltage input to the second input terminal (V ref ) to the first input terminal. When the input voltage is high, a low level potential is output from the output terminal of the comparator CMPb. can be done.

[0117] At this time, the potentials output from the output terminals of the comparators CMPa and CMPb are Depending on j (k) For example, the output of the comparator CMPa can be expressed as A high-level potential is output from the output terminal of the comparator CMPb, and a low-level potential is output from the output terminal of the comparator CMPb. If the output signal z j (k) is set to "+1", and a low level is output from the output terminal of the comparator CMPa. When a high-level potential is output from the output terminal of comparator CMPb, signal z j (k) is set to "-1", and a low level potential is output from the output terminal of the comparator CMPa. When a low-level potential is output from the output terminal of the comparator CMPb, the output signal z j (k) teeth It can be set to "+0".

[0118] Furthermore, the circuit ACTF[j] is not limited to the circuit configuration shown in FIG. 6A, and may be configured as follows depending on the situation: For example, in the circuit ACTF[j] of FIG. 6A, the comparator CMPa If you want to combine the two output results of the comparator CMPb into one signal, use the circuit ACTF The circuit ACTF[j] in FIG. 6B is the same as the circuit ACTF[j] in FIG. 6A. This is a configuration example in which a conversion circuit TRF is provided in ACTF[j], and the comparators CMPa and CMP b are electrically connected to the input terminals of the conversion circuit TRF. A specific example of the circuit TRF is a digital-to-analog conversion circuit (in this case, a signal z j (k ) is an analog value.)

[0119] Also, for example, in FIG. 6A, the second inputs of the comparators CMPa and CMPb are The wire VrefL electrically connected to the output terminal is referred to as wire Vref1L and wire Vref2. The circuit ACTF[j] in FIG. 6C may be replaced by separate wirings for the circuit AC The second terminal of the comparator CMPa included in TF[j] is connected to the wiring VrefL instead of the wiring Vre f1L, and the second terminal of the comparator CMPb is connected to the wiring Vr instead of the wiring VrefL. It is electrically connected to ef2L. Wiring Vref1L, wiring Vref2L By setting the potentials input to the comparators CMPa and CMP The reference potential at b can be set separately.

[0120] Also, for example, as a configuration different from the circuit ACTF[j] of FIGS. 6A to 6C, an amplifier circuit Alternatively, an impedance conversion circuit or the like may be used. For example, the circuit AC TF[j] can be applied to the circuit AFP of the arithmetic circuit 110 in Figure 2. ACTF[j] has resistor RE, resistor REB, operational amplifier OPa, and operational amplifier OPb. It functions as an amplifier circuit.

[0121] The wiring OL[j] is connected to the first terminal of the resistor RE, the non-inverting input terminal of the operational amplifier OPa, and the The wiring OLB[j] is electrically connected to the first terminal of the resistor REB and the non-terminal of the operational amplifier OPb. The inverting input terminal of the operational amplifier OPa is electrically connected to the inverting input terminal. The inverting input terminal of the operational amplifier OPb is electrically connected to the output terminal of the operational amplifier OPa. The second terminal of the resistor RE is electrically connected to the output terminal of the operational amplifier OPb. The second terminal of the resistor REB is electrically connected to the wiring VAL. It is being done.

[0122] That is, the operational amplifiers OPa and O Pb is configured as a voltage follower. This allows the operational amplifier OPa to The potential output from the output terminal is the same as the potential input to the non-inverting input terminal of the operational amplifier OPa. The voltage output from the output terminal of the operational amplifier OPb is approximately equal to the voltage In this case, the output signal z j (k) teeth , are output from the circuit ACTF[j] as two analog values. The output terminal of the operational amplifier OPb is connected to the input terminal of the comparator CMP. The output from the comparator CMP may be connected to the output signal z j (k) It may also be possible to use the following.

[0123] Also, for example, as a configuration different from the circuit ACTF[j] of FIGS. 6A to 6D, an integrating circuit Alternatively, a current-voltage conversion circuit or the like may be used. As an example, a circuit ACT shown in FIG. 6E may be used. F[j] can be applied to the circuit AFP of the arithmetic circuit 110 in FIG. CTF[j] has an operational amplifier OPa, an operational amplifier OPb, a load LEa, and a load LEb. do.

[0124] The wiring OL[j] is connected to the first input terminal (for example, the inverting input terminal) of the operational amplifier OPa and the negative The first terminal of the load LEa is electrically connected to the line OLB[j] of the operational amplifier OPb. A first input terminal (for example, an inverting input terminal) is electrically connected to a first terminal of the load LEb. The second input terminal (for example, the non-inverting input terminal) of the operational amplifier OPa is connected to the wiring V Electrically connected to ref1L, the second input terminal of the operational amplifier OPb (for example, the non-inverting input The second terminal of the load LEa is electrically connected to the wiring Vref2L. The second terminal of the load LEa is electrically connected to the output terminal of the amplifier OPa. b is electrically connected to the output terminal of

[0125] The wiring Vref1L and the wiring Vref2L may have the same voltage or different voltages. Therefore, the wiring Vref1L and wiring Vref2 L can sometimes be combined into a single wire.

[0126] In the circuit ACTF[j] of FIG. 6E, the loads LEa and LEb are, for example, resistors. In particular, by using capacitance as the load LEa and the load LEb, Therefore, the operational amplifier OPa and the load LEa, and the operational amplifier OPb and the load LEb are the products It functions as a divider circuit. In other words, the amount of current flowing through wiring OL[j] or wiring OLB[j] Depending on the load, charge is stored in each capacitance (load LEa, load LEb). The current flowing from the line OL[j] and the wiring OLB[j] is integrated by the integrator circuit. The quantity is converted to a voltage and the signal z j (k) The output of the operational amplifier OPa is The output terminal of the operational amplifier OPb is connected to the input terminal of the comparator CMP. The output from the comparator CMP may be used as the output signal z j (k) It is also possible to use the following. A circuit for initializing the charge stored in the capacitance of the loads LEa and LEb may be provided. For example, a switch may be provided in parallel with the load LEa (capacitance). The second terminal of the switch is connected to the output terminal of the operational amplifier OPa, and the first terminal of the switch is , wiring OL[j], and the first input terminal (e.g., the inverting input terminal) of the operational amplifier OPa. may be connected to

[0127] In addition, in the circuit ACTF[j] of FIG. 6E, from the wiring OL[j] and wiring OLB[j] When converting the flowing current into a voltage and outputting it, the load LEa and load LEb must be larger than the capacity. A resistor can be used as the external resistor.

[0128] 6F as a configuration different from the circuit ACTF[j] of FIG. 6A to FIG. 6E. The circuit ACTF[j] shown can be applied to the circuit AFP of the arithmetic circuit 110 in FIG. The circuit ACTF[j] in FIG. 4F includes a resistor RE, a resistor REB, an analog-to-digital converter AD Ca and has an analog-to-digital conversion circuit ADCb.

[0129] The wiring OL[j] is connected to the input terminal of the analog-to-digital conversion circuit ADCa and the first terminal of the resistor RE. The wiring OLB[j] is electrically connected to the analog-to-digital conversion circuit ADCb and a first terminal of the resistor REB. The terminal of the resistor REB is electrically connected to the wire VAL, and the second terminal of the resistor REB is electrically connected to the wire VAL. is connected.

[0130] In the circuit ACTF[j] in Figure 6F, the current flowing from the wiring OL[j] and OLB[j] The potentials of the first terminals of the resistors RE and REB are determined according to the following equation. CTF[j] converts the analog voltage into a digital signal. The log-to-digital conversion circuit ADCb converts the signal into two or more values (e.g., 256 values) and convert it into a digital value, and the signal z j (k) It has the function of outputting as

[0131] The resistors RE and REB shown in FIGS. 6A to 6D and 6F are the same as those shown in FIGS. 5B and 5C. Similarly, when the capacitance CE, capacitance CEB, or the diode element DE, diode element DEB is used, In particular, the resistors RE and REB shown in FIGS. 6A to 6D and 6F can be replaced with When the capacitances CE and CEB are replaced, the switches S01a and S01b are also replaced as in FIG. 5E. By providing the switch S01b, the potential input from the wiring OL[j] and wiring OLB[j] can be It can be retained.

[0132] The arithmetic circuit 110, the arithmetic circuit 120, and the arithmetic circuit 13 shown in FIGS. 2 to 4, respectively, In 0, an example was shown in which wiring IL, wiring ILB, wiring OL, and wiring OLB were placed. One embodiment of the present invention is not limited to this. In each of the calculation circuits 130, the wiring IL and the wiring OL are combined into one wiring, and the wiring The ILB and the wiring OLB may be integrated into a single wiring. The arithmetic circuit 140 shown in FIG. It has a circuit TW[n].

[0133] Each of the switching circuits TW[1] to TW[n] has a terminal TSa and a terminal terminals TSaB, TSb, TSbB, TSc, and TScB. do.

[0134] The terminal TSa is electrically connected to the wiring OL[j], and the terminal TSbB is electrically connected to the circuit ILD. and the terminal TSc is electrically connected to the circuit ACTF[i]. is electrically connected to the wiring OLB[j], and the terminal TSbB is electrically connected to the circuit ILD. , the terminal TScB is electrically connected to the circuit ACTF[j].

[0135] The switching circuit TW[j] connects the terminal TSa to either the terminal TSb or the terminal TSc. and put terminal TSa into a conductive state and put terminal TSa into a non-conductive state with the other of terminal TSb and terminal TSc. The switching circuit TW[j] has a function of switching between the terminal TSaB and the terminal TSbB or and one of the terminals TScB, and cB and the other terminal cB.

[0136] That is, the weighting coefficient 1 is added to one of the circuits MP[1,j] to MP[m,j]. 1 data w1 (k-1) 1 (k) Or even w m (k-1) n (k) Information corresponding to (e.g., If you want to input a value such as potential, resistance, or current, in the switching circuit TW[j], The TSa and TSb terminals are connected to each other, and the TSaB and TSbB terminals are connected to each other. By setting it to ON, the first data w is sent from the circuit ILD to the wiring OL[j] and wiring OLB[j]. 1 (k-1) 1 (k) Or even w m (k-1) n (k) Information corresponding to the It is possible to supply voltages (voltages, current values, etc.).

[0137] Also, the circuit ACTF[j] is calculated by the circuits MP[1,j] to MP[m,j]. If you want to obtain the result of the sum of products (equation (1.2)) of the weight coefficients and the neuron signals, In the switching circuit TW[j], the terminals TSa and TSc are brought into a conductive state, and By bringing terminals TSaB and TScB into a conductive state, wiring OL[j] and wiring O Information corresponding to the result of the sum of products (e.g., potential, current value, etc.) is sent from LB[j] to the circuit ACTF[j]. In addition, the circuit ACTF[j] can provide the result of the input sum of products. The activation function is calculated from the results and the signal z is output as the neuron's output signal. j (k) get It is possible.

[0138] Next, regarding the switching circuit TW[j] and the circuit ILD included in the arithmetic circuit 140, FIG. 8A shows a switching circuit TW[j ] and the circuit ILD. In FIG. 8A, the switching circuit TW[j ] and the circuit ILD, the wiring OL[j] and the wiring OLB [j] and the circuit AFP are also shown.

[0139] The switching circuit TW[j] includes, for example, a switch SWI, a switch SWIB, and a switch Switch SWO, switch SWOB, switch SWL, switch SWLB, and switch The switch has a switch SWH and a switch SWHB.

[0140] The circuit ILD includes, for example, a current source circuit ISC. For example, the current source circuit ISC may not be provided, and a voltage source circuit may be provided instead. The current source circuit ISC may be connected to the wiring OL[j] and / or the wiring OLB[j]. In contrast, the circuit MP has a function of passing a current according to a weighting coefficient (first data) input to the circuit MP. The current source circuit ISC is a circuit for the wiring OL[j] and a circuit for the wiring OLB[j]. At least one of each of the circuits may be arranged as separate circuits. Alternatively, as shown in FIG. 8A, a pair of wirings OL[j] and OLB[j] For a line, there may be at least one current source circuit ISC.

[0141] The current source circuit ISC has one or more constant current sources. As a plurality of constant current sources, a constant current source circuit ISC1, a constant current source circuit ISC2, and a constant The current source circuit ISC3 includes, for example, a plurality of constant voltage In order to select the current source, a plurality of switches are provided. In FIG. 8A, The switch SWC1, the switch SWC2, and the switch SWC3 are provided. If the current source circuit ISC has only one constant current source, the constant current source circuit ISC Alternatively, the constant current source circuit ISC1, the constant current source circuit ISC2, and the constant current When the power supply circuit ISC3 and the power supply circuit ISC4 have a function of controlling whether or not to output a current, The switches SWC1, SWC2, and SWC3 may not be provided.

[0142] The currents flowing through the wiring OL[j] and wiring OLB[j] are shown in FIG. 8A. As shown in the figure, it is preferable that the currents are generated by the same current source circuit ISC. When generating the current flowing through each of B[j] using different current source circuits, Since variations in the characteristics of the transistor may occur due to manufacturing processes, There may be differences in performance between different current source circuits. In this case, the same current is supplied to the wiring OL[j] and the wiring OLB[j]. This makes it possible to improve the calculation accuracy.

[0143] The switches SWI, SWIB, SWO, and Switch SWOB, Switch SWL, Switch SWLB, Switch SWH, Switch SWHB, The switches SWC1, SWC2, and SWC3 are, for example, switches S As with switch S01a and switch S01b, analog switches, transistors, and other electrical A switch, a mechanical switch, or the like can be applied.

[0144] In one example of the switching circuit TW[j], the terminal TSa is connected to the first terminal of the switch SWI. , a first terminal of the switch SWO, a first terminal of the switch SWL, and a first terminal of the switch SWH The terminal TSaB is electrically connected to the first terminal of the switch SWIB and the The first terminal of the switch SWOB, the first terminal of the switch SWLB, and the first terminal of the switch SWHB The second terminal of the switch SWI is electrically connected to the terminal TSb1. The second terminal of the switch SWIB is electrically connected to the terminal TSbB1. The second terminal of the switch SWO is electrically connected to the terminal TSc. The second terminal of switch SWOB is electrically connected to terminal TScB. The second terminal of the switch SWLB is electrically connected to the terminal TSb2. The second terminal of the switch SWH is electrically connected to the terminal TSbB2. The second terminal of switch SWHB is electrically connected to terminal TSbB3. It continues.

[0145] The terminals TSb1, TSb2, and TSb3 shown in FIG. 8A are the same as those shown in FIG. Also, the terminals TSbB1 and TSbB2 shown in FIG. 2. Terminal TSbB3 corresponds to terminal TSbB shown in FIG.

[0146] In the current source circuit ISC included in the circuit ILD, the terminal TSb1 is connected to the switch SW A first terminal of switch SWC1, a first terminal of switch SWC2, and a first terminal of switch SWC3 are connected to each other. The terminal TSbB1 is electrically connected to the first terminal of the switch SWC1. The first terminal of the switch SWC2 is electrically connected to the first terminal of the switch SWC3. The second terminal of the switch SWC1 is electrically connected to the output terminal of the constant current source circuit ISC1. The second terminal of the switch SWC2 is electrically connected to the output terminal of the constant current source circuit ISC2. The second terminal of the switch SWC3 is electrically connected to the output terminal of the constant current source circuit ISC3. The input terminal of the constant current source circuit ISC1, the input terminal of the constant current source circuit ISC2, and the constant The input terminals of the current source circuit ISC3 and the input terminals of the current source circuit ISC4 are electrically connected to the wiring VSO. .

[0147] In FIG. 8A, the constant current source circuits ISC1, ISC2, and IS Each of C3 has its output terminal electrically connected to the terminal of the respective switch, and its input terminal However, one embodiment of the present invention is not limited to this. For example, the constant current source circuit ISC1, the constant current source circuit ISC2, the constant current source circuit IS Each of C3 has its input terminal electrically connected to the terminal of the respective switch, and its output terminal The wiring VSO may be electrically connected to the circuit MP. Before inputting, in order to initialize the potential of the wiring OL[j] and wiring OLB[j], 2 may be placed. The wiring VCN2 is connected to the wiring OL[j] via the switch SWH. In addition, the wiring VCN2 is connected to the wiring OLB[j] via the switch SWHB. The wiring VCN2 can supply a potential different from that of the wiring VCN. For example, when VSS or ground potential is supplied to the wiring VCN, VDD and other voltages are supplied to 2. This allows the current output from the circuit MP to The potentials of the wiring OL[j] and the wiring OLB[j] can be changed.

[0148] Specific configurations of the constant current source circuits ISC1, ISC2, and ISC3 Examples are shown in FIGS. 8B and 8C. The constant current source circuit ISC1 (constant current source circuit IS C2, the constant current source circuit ISC3) has a p-channel transistor, A first terminal of the transistor is electrically connected to the wiring VSO, and a second terminal of the transistor is electrically connected to the The switch SWC1 (switch SWC2, switch SWC3) is electrically connected to the second terminal of the switch SWC2. The gate of the transistor is electrically connected to the wiring VB. The current source circuit ISC1 (constant current source circuit ISC2, constant current source circuit ISC3) is an n-channel a transistor, a first terminal of the transistor being electrically connected to a wiring VSO; The second terminal of the transistor is connected to the switch SWC1 (switch SWC2, switch SWC 3) is electrically connected to the second terminal of the transistor, and the gate of the transistor is electrically connected to the wiring VB. The constant current source circuits ISC1 (constant current source circuits) in FIGS. 8B and 8C are connected. In the constant current source circuit ISC2, constant current source circuit ISC3, the wiring VB is It functions as a wiring for inputting bias voltage to the port. This allows determining whether or not to output a current from each constant current source circuit. In this case, the switches SWC1, SWC2, and SWC3 can be controlled. SWC3 may not be provided, or an analog voltage may be supplied to the wiring VB. This allows an analog current to be supplied from the constant current source circuit.

[0149] The wiring VSO is connected to the constant current source circuit ISC1, the constant current source circuit ISC2, and the constant current source circuit ISC3. For example, from the circuit ILD, When current is supplied to the wiring OL or wiring OLB via the switching circuit TW[j], The voltage is preferably a potential higher than the ground potential (for example, VDD, etc.). Furthermore, the constant current source circuit ISC1 (constant current source circuit ISC2, constant current source circuit ISC 3) is preferably used. Also, for example, the switching circuit TW[j] is selected from the circuit ILD. When current is supplied to the wiring OL or OLB via the It is preferable that the potential be higher than the high-level potential and lower than the high-level potential, such as the ground potential. The constant current source circuit ISC1 (constant current source circuit ISC2, constant current source circuit ISC3) shown in 8C is used. In this specification, the switching circuit TW[j] is preferably connected to the circuit ILD. The current flowing through the wiring OL or wiring OLB may be referred to as a positive current. Therefore, the current flows from the wiring OL or wiring OLB to the circuit ILD via the switching circuit TW[j]. The current may be referred to as a negative current.

[0150] By the way, the current flowing from the constant current source circuit ISC1 is I ut As an example, The current source circuit ISC2 flows is 2I ut It is preferable that the constant current source circuit ISC3 The current is 4I ut That is, it is preferable that the number of current source circuits ISC is P (P is 1 or more). (p is an integer between 1 and P) The current flowing from the constant current source is 2 (p-1) ×I ut In this way, it is preferable to The magnitude of the current flowing from the current source circuit ISC can be changed.

[0151] For example, the number of constant current sources in the current source circuit ISC is three (P=3). To I ut If you want to pass a current of After that, switch SWC1 is turned on, and switches SWC2 and SWC 3 should be in the OFF state. Also, connect 5I to the wiring OL[j]. ut If you want to pass a current of Switches SWC1 and SWC3 are turned on, and switch SWC2 is turned off. In other words, the current output from the current source circuit ISC can be set to eight values ("0", "I ut ” , "2I ut ", "3I ut ", "4I ut ", "5I ut ", "6I ut ", "7I u t "). If you want to output a current with a value greater than 8, In this case, the number of constant current sources should be set to four or more. By turning on the switch SWIB, one of the eight values is input to the wiring OLB[j]. In addition, when no current is output from the current source circuit ISC, In this case, the switches SWC1 to SWC3 of the current source circuit ISC are not turned off, but are turned off. The switches SWI and SWIB of the switching circuit TW may be turned off. By arranging multiple constant current sources, DA conversion can be easily achieved. Only one current source circuit is placed and it operates to change the current value output in an analog manner. It may be possible.

[0152] In the circuit ILD, the terminal TSb2 is electrically connected to the wiring VCN, and the terminal T SbB2 is electrically connected to the wiring VCN.

[0153] The wiring VCN supplies a constant voltage to the wiring OL[j] and / or the wiring OLB[j]. For example, the wiring from the circuit ILD through the switching circuit TW[j] When current (positive current) is supplied to OL or wiring OLB, the constant voltage given by wiring VCN is It is preferable to set the potential to a low level (for example, VSS). A current (negative current) flows from L or wiring OLB to circuit ILD via switching circuit TW[j]. When supplying the voltage VCN, it is preferable that the constant potential given by the wiring VCN is a high-level potential. As shown in FIGS. 42 to 45, the capacitance C3 is connected to the transistor M1, etc. If the source terminal is not connected to a power supply line, A positive current is supplied from the line ILD to the wiring OL or wiring OLB via the switching circuit TW[j]. When supplying power, the constant voltage given by the wiring VCN is a high-level potential (for example, VDD). In other words, when a constant voltage is supplied from the wiring VCN, both ends of the capacitor C3 In other words, it is desirable to make the potential difference between the It is desirable to supply a potential to the wiring VCN such that no current is output.

[0154] In the circuit ILD, the terminal TSb3 is electrically connected to the wiring VCN2. TSbB3 is electrically connected to the wiring VCN2.

[0155] The line VCN2 supplies a constant voltage to the line OL[j] and / or the line OLB[j]. For example, the wiring from the circuit ILD through the switching circuit TW[j] When current (positive current) is supplied to line OL or wiring OLB, the constant voltage given by wiring VCN is It is preferable to set the potential to a high level (for example, VDD). A current (negative current) flows from OL or wiring OLB to the circuit ILD via the switching circuit TW[j]. ), the constant potential given by the wiring VCN is preferably a low level potential. stomach.

[0156] The switching circuit TW[j] consists of switches SWI, SWIB, SWO, and Switch SWOB, Switch SWL, Switch SWLB, Switch SWH, Switch SWH By switching each of the wirings OL[j] and B to the on or off state, The circuit that is in a conductive state with the line OLB[j] can be changed.

[0157] Here, the weighting coefficients input to the circuit MP will be explained.

[0158] When a positive weighting coefficient is input to the circuit MP, a current corresponding to the weighting coefficient is input to the wiring OL[j]. For example, a constant potential given by the wiring VCN can be input to the wiring OLB[j]. In this case, the current source circuit ISC and the wiring OL[j] are connected to each other, and the current source circuit ISC and the wiring OL[j] are connected to each other. The circuit AFP and the wiring OL[j] are in a non-conductive state. the circuit AFP and the wiring OLB[j] are in a non-conductive state, and the wiring VCN and the wiring OL [j] is in a non-conductive state, and the wiring VCN and wiring OLB[j] are in a conductive state. The wiring VCN2 and wiring OL[j] are in a non-conductive state, and the wiring VCN2 and wiring OLB[j ] is in a non-conductive state. Switches SWI and SWLB are turned on, and switches SWIB, SWO, and S Switch WOB, switch SWL, switch SWH, and switch SWHB are each set to the off state. This brings the current source circuit ISC and the wiring OL[j] into a conductive state. ,Current can be passed from the current source circuit ISC to the circuit MP via the wiring OL[j]. By the way, when the number of constant current sources in the current source circuit ISC is P, the current is 2 P - The positive weighting coefficient input to the circuit MP is Since it is determined according to the current, the weighting factor is 2 P -1 can be any one of the values In addition, the wiring VCN and wiring OLB[j] are in a conductive state, so that the wiring OLB[j ] receives a constant voltage from the line VCN.

[0159] Also, when you want to input a negative weighting coefficient to the circuit MP, you can input the weighting coefficient to the wiring OLB[j]. A current corresponding to the voltage Vc is input, and the constant potential given by the wiring VCN is input to the wiring OL[j]. For example, the current source circuit ISC and the wiring OL[j] are in a non-conductive state, and the current source circuit I The connection between SC and wiring OLB[j] is made conductive, and the connection between circuit AFP and wiring OL[j] is made non-conductive. The circuit AFP and the wiring OLB[j] are in a non-conductive state, and the wiring VCN and the wiring The line OL[j] is in a conductive state, and the line VCN and the line OLB[j] are in a non-conductive state. , and the line VCN2 and the line OL[j] are in a non-conductive state. B[j] is turned off. , the switches SWIB and SWL are turned on, and the switches SWI and SWO are turned on. , switch SWOB, switch SWLB, switch SWH, switch SWHB This allows the conduction between the current source circuit ISC and the wiring OLB[j] to Since the current source circuit ISC is in a conducting state, a current flows from the current source circuit ISC to the circuit MP via the wiring OLB[j]. By the way, when the number of constant current sources in the current source circuit ISC is P, The current is 2 P The value input to the circuit MP is either -1 or -1 (excluding zero current). The negative weighting factor is determined depending on the current, so the weighting factor is 2 P Any of the -1 values In addition, the wiring VCN and the wiring OL[j] are in a conductive state. A constant voltage is input to the line OL[j] from the line VCN.

[0160] Also, when you want to input a weight coefficient of 0 to the circuit MP, wiring OL[j], wiring OLB[j] A constant potential given by the wiring VCN can be input to each of the current sources I The current source circuit ISC and the wiring OL[j] are in a non-conductive state, and the current source circuit ISC and the wiring OLB[j] are in a non-conductive state. and the circuit AFP and the wiring OL[j] are brought into a non-conductive state, and the circuit AF The connection between P and wiring OLB[j] is made non-conductive, and the connection between wiring VCN and wiring OL[j] is made conductive. and put wiring VCN and wiring OLB[j] into a conductive state, and put wiring VCN2 and wiring OLB[j] into a conductive state. OL[j] and VCN2 are in a non-conductive state, and VCN3 and VCN4 are in a non-conductive state. That is, in the switching circuit TW[j], the switch SWL and the switch Switch SWLB is turned on, and switches SWI, SWIB, SWO, and By doing so, the wiring VCN and wiring OL[ Since there is a state of conduction between wiring VCN and wiring OLB[j], there is a state of conduction between wiring VCN and wiring OLB[j]. A constant voltage is input from the line VCN to the lines OL[j] and OLB[j].

[0161] In other words, by setting the number of constant current sources in the current source circuit ISC to P, The number of weighting factors that can be input (the sum of positive weighting factors, negative weighting factors, and 0 weighting factors) is 2. P+ 1 -1 piece.

[0162] Next, when information (for example, potential, current, etc.) is supplied from the circuit MP to the circuit AFP, and explain.

[0163] Before supplying information (e.g., potential, current, etc.) from the circuit MP to the circuit AFP, the wiring O It is preferable to set the potential of the wiring OLB[j] and the wiring L[j] to a predetermined potential. When a positive current flows from P to the circuit MP via the wiring OL or wiring OLB, a predetermined potential For example, the potential of the wiring OL or the wiring When a positive current flows through the line OLB to the circuit AFP, the predetermined potential is a low-level voltage. Therefore, information (e.g., potential, current, etc.) is sent from the circuit MP to the circuit AFP. ), for example, the current source circuit ISC and the wiring OL[j] are not connected. state, and the current source circuit ISC and the wiring OLB[j] are in a non-conductive state, and the circuit AFP and The circuit AFP and wiring OLB[j] are in a non-conductive state, and the circuit AFP and wiring OLB[j] are in a non-conductive state. state, and the line VCN and the line OL[j] are in a non-conductive state, and the line VCN and the line OL B[j] and VCN2 are in a non-conductive state, and VCN3 and OL[j] are in a conductive state. , the wiring VCN2 and the wiring OLB[j] should be brought into a conductive state. In the circuit TW[j], the switches SWH and SWHB are turned on, and the switch SWI, switch SWIB, switch SWO, switch SWOB, switch SWL, switch By doing so, the wiring OL[j] and the wiring V CN2 is in a conductive state, and the wiring OLB[j] and wiring VCN2 are in a conductive state. Therefore, a constant voltage is input from the line VCN2 to the lines OL and OLB.

[0164] When supplying information (e.g., potential, current, etc.) from circuit MP[i,j] to circuit AFP, For example, the current source circuit ISC is disconnected from the wiring OL[j], and the current source The circuit ISC and the wiring OLB[j] are in a non-conductive state, and the circuit AFP and the wiring OL[j] are in a non-conductive state. and the circuit AFP and the wiring OLB[j] are connected to each other, and the wiring VCN and wiring OL[j] in a non-conductive state, and wiring VCN and wiring OLB[j] in a non-conductive state. and the wiring VCN2 and the wiring OL[j] are in a non-conductive state. In other words, the switching circuit TW[j] should be set to a non-conductive state. In this case, the switches SWO and SWOB are turned on, and the switches SWI and SWIB, switch SWL, switch SWLB, switch SWH, switch SWHB By doing this, the circuit AFP and the circuit MP[i,j] are connected to each other. Since the circuit is in a conductive state, information (e.g., potential, current, etc.) is sent from the circuit MP[i,j] to the circuit AFP. etc.) can be supplied.

[0165] <<Circuit MP>> Next, the calculation circuits 110, 120, 130, and 140 include An example of the configuration of the circuit MP[i,j] will be described.

[0166] FIG. 9A shows an example of the configuration of a circuit MP[i,j] that can be applied to the arithmetic circuit 140. The path MP[i,j] includes, for example, a circuit MC and a circuit MCr. The circuit MCr is a circuit MP that stores weight coefficients, input signals (calculated values) of neurons, and The circuit MC is a circuit that calculates the product of the two. The circuit MC may have the same configuration as the circuit MCr or a different configuration from the circuit MCr. Therefore, the circuit MCr is designated by the symbol MC in order to distinguish it from the circuit MC. The symbols of the circuit elements included in the circuit MCr, which will be described later, are marked with "r". It also has an "r" attached to it.

[0167] For example, the circuit MC has a holding unit HC, and the circuit MCr has a holding unit HCr. The holding unit HC and the holding unit HCr each store information (for example, potential, resistance value, current value, etc.) ) is stored in the circuit MP[i,j]. i (k -1) j (k) is the information (for example, , potential, resistance value, current value, etc.). Each of the first data w i (k-1) j (k) Each piece of information (e.g., potential, Resistance value, current value, etc.) are supplied to the wiring OL[j] and wiring OLB[j]. It is being done.

[0168] In FIG. 9A, the circuit MP[i,j] is connected to the wiring VE[j] and the wiring VEn[j]. Electrically connected. Wiring VE[j] and wiring VEr[j] are wirings that supply constant voltage. In addition, the wiring VE[j] drains the current from the wiring OL through the circuit MC. In addition, the wiring V Er[j] also functions as a wiring for connecting the wiring OLB It also functions as a wiring to drain current from the

[0169] The wiring WL[i] shown in FIG. 9A corresponds to the wiring WL[i] in FIG. 7. [i] is electrically connected to each of the holding portion HC and the holding portion HCr. The first data w is stored in the holding section HC and the holding section HCr included in [i,j]. i (k-1) j (k ) When writing information (for example, potential, resistance, current, etc.) according to the wiring WL[i] By supplying a predetermined potential to the wiring OL[j], the wiring OL[j] and the holding unit HC are brought into a conductive state. The wiring OLB[j] and the holding unit HCr are electrically connected. j], OLB[j] are each assigned the first data w i (k-1) j (k) The potential according to By supplying the voltage, the potential is input to each of the holding unit HC and the holding unit HCr. After that, a predetermined potential is supplied to the wiring WL[i], and the wiring OL[j] and The holding unit HC is brought into a non-conductive state, and the wiring OLB[j] and the holding unit HCr are brought into a non-conductive state. Then, the first data w is stored in each of the holding unit HC and the holding unit HCr. i (k -1) j (k) Each current according to the above is maintained.

[0170] For example, the first data w i (k-1)j (k) is one of the three values "-1", "0" or "1". Consider the case where either of the first data w i (k-1) j (k) If is "1", for example As a result, a current corresponding to "1" flows from wiring OL[j] to wiring VE[j] via circuit MC. A predetermined potential is held in the holding unit HC, and the wiring OLB[j] is connected to the circuit MC The potential V0 is maintained in the holding part HCr so that current does not flow to the wiring VEr[j] via r. In addition, the first data w i (k-1) j (k) is "-1", for example, To prevent current from flowing from the wiring OL[j] to the wiring VE[j] via the circuit MC, the holding part H The potential V0 is maintained at C, and the potential V is supplied from the wiring OLB[j] to the wiring VEr[ A predetermined potential is maintained in the holding unit HCr so that a current corresponding to "-1" flows through the And the first data i (k-1) j (k) is "0", for example, To prevent current from flowing from L[j] to the wiring VE[j] via the circuit MC, the holding part HC is The potential V0 is maintained, and current flows from the wiring OLB[j] to the wiring VEr[j] via the circuit MC. The potential V0 is held in the holding section HCr so that the current does not flow. In the illustrated example, the potential can be the potential applied by the wiring VCN.

[0171] As another example, the first data w i (k-1) j (k) is the analog value, specifically, Consider the case where the analog value is a negative value, a zero value, or a positive value. Data w i (k-1) j (k) is a "positive analog value", for example, wiring OL[ An analog current corresponding to the "positive analog value" flows from the wire VE[j] through the circuit MC to the wire VE[j]. A predetermined potential is held in the holding unit HC, and the wiring OLB[j] is connected to the circuit M The potential V0 is maintained in the holding part HCr so that current does not flow to the wiring VEr[j] via Cr. Also, the first data w i (k-1) j (k) If is a "negative analog value", For example, we can prevent current from flowing from wiring OL[j] to wiring VE[j] via circuit MC. The potential V0 is held in the holding unit HC, and the potential V1 is applied from the wiring OLB[j] through the circuit MCr. The holding part H Cr is held at a predetermined potential. i (k-1) j (k) is "0" For example, if a current flows from the wiring OL[j] to the wiring VE[j] via the circuit MC, To prevent this, the potential V0 is held in the holding unit HC, and the potential V1 is transferred from the wiring OLB[j] to the circuit MC The potential V0 is held in the holding part HCr so that no current flows through the wiring VEr[j]. As in the previous example, the potential V0 is the potential given by the wiring VCN in the explanation of FIG. It can be said that:

[0172] Also, as an example, the circuit MC stores information (for example, potential, resistance value) stored in the storage unit HC. , or current value, etc.) of wiring OL[j] or wiring OLB[j] The circuit MCr has a function of outputting information (for example, potential) stored in the storage unit HCr. , resistance value, or current value) according to the wiring OL[j] or wiring OLB[ j]. For example, when the first potential is held in the holding unit HC, In this case, the circuit MC sends a current having a first current value from the wiring OL[j] or wiring OLB[j] to the wiring VE. When the second potential is held in the holding section HC, the circuit MC is connected to the wiring OL[ A current having a second current value flows from wiring OLB[j] or wiring OLB[j] to wiring VE. When the first potential is held in the holding unit HCr, the circuit MCr is connected to the wiring OL[j] or the wiring A current having a first current value is passed from OLB[j] to the wiring VEr, and a second current value is passed to the holding unit HCr. When the potential is maintained, the circuit MCr is connected to the wiring OL[j] or the wiring OLB[j]. A current having a second current value is passed through the line VE. The size of each is the first data w i (k-1) j (k) It is determined by the value of In some cases, the first current value may be greater than or less than the second current value. As an example, one of the first current value and the second current value may be zero current, i.e., the current value may be 0. Alternatively, the current flow direction is different between a current having a first current value and a current having a second current value. It may be different.

[0173] In particular, for example, the first data w i (k-1) j (k) Three values: "-1", "0", and "1" When either of the first current value or the second current value is zero, the circuit MC , MCr. i (k-1) j (k) is analog If it takes a value, for example, "negative analog value", "0", or "positive analog value" The first current value or the second current value may also be, for example, an analog value. .

[0174] By the way, the current flowing from wiring OL[j] or wiring OLB[j] to wiring VE through circuit MC The current from the wiring OL[j] or wiring OLB[j] to the wiring VEr via the circuit MCr When the current flowing through the transistor is equal to the current flowing through the transistor, the transistor may be affected by the manufacturing process. Since the characteristics of the capacitor may vary, the potential held in the MC circuit and the potential held in the MCr circuit may differ. The potential of the semiconductor device according to one embodiment of the present invention may not be equal to the potential of the transistor. Even if there are variations in the characteristics of the wiring OL[j] or wiring OLB[j], The amount of current flowing through the wiring VE is calculated from the wiring OL[j] or wiring OLB[j] to the circuit MCr The amount of current flowing through the wiring VEr can be made approximately equal to the amount of current flowing through the wiring VEr.

[0175] In this specification and the like, the information held in the holding unit HC and the holding unit HCr (for example, For example, a current or voltage depending on the potential, resistance, or current value is a positive current or may be a voltage, a negative current or voltage, or a zero current or zero It may be a voltage, or may be a mixture of positive, negative and zero. According to the information (for example, potential, resistance value, or current value) stored in the "holding unit HC" The function to output the current or voltage, etc., to either wiring OL[j] or wiring OLB[j]. The circuit MCr stores information (for example, potential, resistance value, or current value, etc.) to the wiring OL[j] or wiring OLB[j]. The phrase "has the function of outputting information stored in the storage unit HC (for example, The current, voltage, etc. according to the value (potential, resistance value, or current value, etc.) are applied to the wiring OL[j] or wiring The circuit MCr has the function of discharging from one side of the OLB[j], and the circuit MCr is Current, voltage, etc. according to information (for example, potential, resistance value, or current value) are transmitted to the wiring O L[j] or the other side of wiring OLB[j]. It is possible.

[0176] The wiring X1L[i] and the wiring X2L[i] shown in FIG. 9A are the wiring XLS in FIG. [i]. The second data z input to the circuit MP[i,j] corresponds to i (k-1) teeth For example, the potential or current of each of the wiring X1L[i] and the wiring X2L[i] Therefore, the circuits MC and MCr are determined by, for example, the wiring X1L[i] and the second data z via the wiring X2L[i]. i (k-1) Each potential is input according to .

[0177] The circuit MC is electrically connected to the wiring OL[j] and the wiring OLB[j]. r is electrically connected to the wiring OL[j] and the wiring OLB[j]. For example, the circuit MCr receives the voltages input to the wiring X1L[i] and the wiring X2L[i]. The first data w is applied to the wiring OL[j] and the wiring OLB[j] according to the potential or current. i ( k-1) j (k) and the second data z i (k-1) Outputs current or potential according to the product of As a specific example, the current output destination from the circuits MC and MCr is the wiring X1L[i]. and the potential of the wiring X2L[i]. For example, the circuit MC and the circuit MCr are , the current output from the circuit MC flows to either the wiring OL[j] or the wiring OLB[j], The current output from the circuit MCr flows to the other of the wiring OL[j] or wiring OLB[j]. In other words, the currents output from the circuits MC and MCr are as follows: The current flows not through the same wiring but through different wirings. There are cases where no current flows from the circuit MCr to either the wiring OL[j] or the wiring OLB[j]. be.

[0178] For example, the second data z i (k-1) can take one of three values: "-1", "0", or "1". For example, the second data z i (k-1) If is "1", the circuit MP The circuit MC and the wiring OL[j] are in a conductive state, and the circuit MCr and the wiring OLB[j] are in a conductive state. For example, the second data z i (k-1) If is "-1", the circuit MP is connected between the circuit MC and the wiring OLB[j], and the circuit MCr and the wiring OL[j] For example, the second data z i (k-1) If is "0", the circuit M The currents output by the wiring OL[j] and the circuit MCr are respectively ], the circuit MP is connected between the circuit MC and the wiring OL[j]. , and the circuit MC and the wiring OLB[j] are in a non-conductive state, and the circuit MCr and the wiring OL[ The state between the circuit MC and the wiring OLB[j] and the state between the circuit MC and the wiring OLB[j] are brought into a non-conductive state.

[0179] An example of the above operations is shown below. i (k-1) j (k) is "1" In this case, the wiring OL[j] or wiring OLB[j] is connected to the wiring VE[j] via the circuit MC. Current may flow through the circuit MCr to the wiring OL[j] or wiring OLB[j]. No current flows from the first data w i (k-1) j (k) is "-1" In this case, the wiring OL[j] or wiring OLB[j] is connected to the wiring VE[j ], and current flows from wiring OL[j] or wiring OLB[j] through circuit MCr. There is a case where a current flows through VEr[j]. Then, the second data z i (k-1) is "1" In this case, between the circuit MC and the wiring OL[j], and between the circuit MCr and the wiring OLB[j], The second data z i (k-1) If is "-1", the circuit MC and the Conduction is established between the line OLB[j] and the circuit MCr and the wiring OL[j]. From the above, the first data i (k-1) j (k) and the second data z i (k-1) The product of If the value is positive, current flows from wiring OL[j] to wiring VE[j] via circuit MCr. Or, current flows from wiring OL[j] to wiring VEr[j] via circuit MCr. On the other hand, the first data w i (k-1) j (k) and the second data z i (k-1) The product of is negative In the case of value, current flows from wiring OL[j] to wiring VEr[j] via circuit MCr. , or current flows from the wiring OLB[j] to the wiring VE[j] via the circuit MC. The first data w i (k-1) j (k) and the second data z i (k-1) The product of these is zero In this case, no current flows from wiring OL[j] or wiring OLB[j] to wiring VE[j]. , no current flows from wiring OL[j] or wiring OLB[j] to wiring VEr[j].

[0180] To take the above example as a specific example, the first data w i (k-1) j (k) is "1" And the second data z i (k-1) is "1", for example, from the circuit MC to the wiring OL A current I1[i, j] with a first current value flows through the wiring OLB[j] from the circuit MCr. A current I2[i, j] having a second current value flows through the first current I2[i, j]. At this time, the magnitude of the second current value is An example is zero. First data w i (k-1) j (k) is "-1" and the second Data z i (k-1) If is "1", for example, the second A current I1[i, j] with a current value flows from the circuit MCr to the wiring OLB[j]. At this time, the magnitude of the second current value is, for example, It is zero. First data w i (k-1) j (k) is "0", and the second data z i (k -1) is "1", a current I1[ i, j] flows from the circuit MCr to the wiring OLB[j], and a current I2[i, j] with a second current value flows from the circuit MCr to the wiring OLB[j]. At this time, the magnitude of the second current value is, for example, zero.

[0181] Also, the first data i (k-1) j (k) is "1", and the second data z i (k-1 ) is "-1", a current I1[ i, j] flows from the circuit MCr to the wiring OL[j], and a current I2[i, j] with a second current value flows At this time, the magnitude of the second current value is, for example, zero. i (k-1) j (k) is "-1", and the second data z i (k-1) is "-1" In this case, a current I1[i, j] with a second current value flows from the circuit MC to the wiring OLB[j], and A current I2[i, j] having a first current value flows from the path MCr to the wiring OL[j]. The magnitude of the second current value is, for example, zero. i (k-1) j(k ) is "0", and the second data z i (k-1) If is "-1", the circuit MC A current I1[i, j] having a second current value flows through the line OLB[j], and a current I2[i, j] flows from the circuit MCr to the wiring OL A current I2[i, j] having a second current value flows through [i, j]. At this time, the magnitude of the second current value is, for example, zero.

[0182] Also, the second data z i (k-1) When is "0", for example, the circuit MC and the wiring OL[j] and between the circuit MC and the wiring OLB[j]. , between the circuit MCr and the wiring OL[j], and between the circuit MCr and the wiring OLB[j] Therefore, the first data w i (k-1) j (k) Whatever the value of No current is output from the circuit MC and the circuit MCr to the wiring OL[j] and the wiring OLB[j]. stomach.

[0183] In this way, as an example, the first data w i (k-1) j (k) and the second data z i (k -1) If the product of is positive, then from either circuit MC or circuit MCr, A current flows through the wiring OL[j]. At this time, the first data w i (k-1) j (k) is a positive value In this case, a current flows from the circuit MC to the wiring OL[j], and the first data w i (k-1) j ( k) When is a negative value, current flows from the circuit MCr to the wiring OL[j]. Data w i (k-1) j (k) and the second data z i (k-1) When the product of In this case, a current flows from either the circuit MC or the circuit MCr to the wiring OLB[j]. At this time, the first data w i (k-1) j (k) If is a positive value, the wire O Current flows through LB[j], and the first data w i (k-1) j (k) If is negative, the circuit Current flows from MCr to wiring OLB[j]. The sum of the currents output from multiple circuits MC or MCr flows through wiring OL[j]. In other words, the current that flows through the wiring OL[j] is the sum of positive values. On the other hand, the output from multiple circuits MC or MCr connected to wiring OLB[j] The sum of the currents flowing through the wiring OLB[j]. In this case, a current with a value equal to the sum of the negative values will flow. The total current value flowing through the wiring OL[j], that is, the sum of the positive values, and the current flowing through the wiring OLB[j] By using the total current value, that is, the sum of negative values, it is possible to perform product-sum calculations. For example, the total current flowing through wiring OL[j] is larger than the total current flowing through wiring OLB[j]. If the value is greater than the current value, it can be determined that the result of the multiplication and accumulation operation will be a positive value. The total current value flowing through the wiring OL[j] is greater than the total current value flowing through the wiring OLB[j]. If σ is also small, it can be determined that the result of the product-sum operation will be a negative value. The total current value flowing through the wire OL[j] and the total current value flowing through the wire OLB[j] are approximately the same value. In some cases, it can be determined that the result of the multiply-and-accumulate operation will be zero.

[0184] In addition, the second data z i (k-1) is one of two values: "-1", "0", or "1" For example, the binary values "-1" and "1" or the binary values "0" and "1" are also the same. Similarly, the first data w i (k-1) j (k) is "-1", In the case of two values, for example, "-1" and "1", Alternatively, the same operation can be performed in the case of two values, "0" and "1".

[0185] In addition, the first data i (k-1) j (k) is an analog value or multi-bit (multi-valued) A specific example is to use "negative analog" instead of "-1". value” and “1” can be replaced by “positive analog value”. In this case, the circuit M The magnitude of the current flowing from C or the circuit MCr is also, for example, the first data w i (k-1 ) j (k) It becomes an analog value according to the absolute value of the value.

[0186] Next, an example of modifying the circuit MP[i,j] in FIG. 9A will be described. Regarding the modified example of [i,j], the difference from the circuit MP[i,j] of FIG. 9A will be mainly explained. , explanation of parts common to the circuit MP[i,j] in FIG. 9A may be omitted.

[0187] The circuit MP[i,j] shown in FIG. 9B has a configuration in which the wiring W1L is replaced with the wiring WX1L. That is, in the circuit MP[i,j] of FIG. 9B, the wiring WX1L and the wiring WL are , the wiring OL[j] and the holding unit HC are switched between a conductive state and a non-conductive state, and the wiring O In order to switch the state between LB[j] and the holding part HCr into a conductive state or a non-conductive state, It functions as a wiring for supplying a predetermined potential. , the wiring X1L and the wiring X2L are connected to the second data z i (k-1 ) It functions as wiring that provides current, voltage, etc. according to the

[0188] The circuit MP[i,j] in FIG. 9B is connected to the wiring WX1L as in the arithmetic circuit 130 shown in FIG. 7, the arithmetic circuit 140 has wirings IL and ILB. Specifically, the circuit MP[i,j] in FIG. 9B can be applied to an arithmetic circuit that does not This can be applied to the circuit MP[i,j] of the arithmetic circuit 150 shown in FIG.

[0189] Next, an example of a modification of the circuit MP[i,j] in FIG. 9A, which is different from that in FIG. 9B, will be described. The circuit MP[i,j] shown in Figure 9C is a modified example of the circuit MP[i,j] in Figure 9A. The circuit MP[i,j] in FIG. 9C is the same as the circuit MP[i,j] in FIG. 9A, but is composed of a circuit MC and a circuit However, the circuit MP[i,j] in FIG. 9C includes a holding unit HC It differs from the circuit MP[i,j] in FIG. 9A in that r is not included.

[0190] Also, since the circuit MCr does not have the holding unit HCr, the circuit MP[i,j] in FIG. The applied arithmetic circuit uses the wiring ILB[j] to supply the potential to be held in the holding unit HCr. In addition, the circuit MCr may not be electrically connected to the wiring WL[i]. Good too.

[0191] In the circuit MP[i,j] of FIG. 9C, the holding unit HC included in the circuit MC is That is, the circuit MP[i,j] in FIG. 9C is electrically connected to the circuit MCr and the circuit MC and the holding unit HC are configured to share each other. The inverted signal of the signal held in C is supplied from the holding unit HC to the circuit MCr. This allows the circuits MC and MCr to operate differently. Alternatively, the internal circuit configurations of the circuits MC and MCr may be different. The voltages output by the circuits MC and MCr for the same signal held by the holding unit HC are It is also possible to make the magnitude of the flow different. i (k-1) j (k) The potential corresponding to the second data z i (k-1) Apply a potential according to By supplying the line X1L[i] and the wiring X2L[i], the circuit MP[i,j] is The first data w i (k-1) j (k) and Day 2 Taz i (k-1)It is possible to output a current according to the product of

[0192] The arithmetic circuit 110 to which the circuit MP of FIG. 9C is applied is the same as the arithmetic circuit 160 shown in FIG. The circuit configuration can be changed. The arithmetic circuit 160 is connected to the arithmetic circuit 110 in FIG. The configuration excludes wiring LB[1] to wiring ILB[m].

[0193] The circuit MP[i,j] shown in FIG. 9D is a modified example of the circuit MP[i,j] in FIG. 9A. Specifically, this is an example of the configuration of the circuit MP[i,j] that can be applied to the arithmetic circuit 160 in FIG. The circuit MP[i,j] of FIG. 9D is composed of a circuit MC and a circuit MCr, where the circuit MP[i,j] in FIG. 9D and the circuit MP[i,j] in FIG. 9A The configuration of the electrically connected wiring is different.

[0194] The wiring W1L[i] and the wiring W2L[i] shown in FIG. 9D correspond to the wiring WL The wiring W1L[i] is electrically connected to the holding unit HC, and the wiring W2L[ i] is electrically connected to the holder HCr.

[0195] The wiring IL[j] is electrically connected to the holding portion HC and the holding portion HCr. .

[0196] In the circuit MP[i,j] of FIG. 9D, different holding units HC and HCr are When storing information (e.g., voltage, resistance, current, etc.), the storage section HC and the storage section HCr It is preferable to perform the information holding operation sequentially rather than simultaneously. For example, in the circuit MP[i,j ]'s first data w i (k-1) j (k)The first information is stored in the storage unit HC, and the second information is stored in the storage unit HCr. First, consider the case where the wiring W1L[i] and A predetermined potential is applied to each of the holding unit HC and the wiring IL[j]. The holding unit HCr and the wiring IL[j] are brought into a conductive state, and the holding unit HCr and the wiring IL[j] are brought into a non-conductive state. By supplying a current, a voltage, or the like according to the first information to the wiring IL[j], the holding unit HC After that, the information of the wiring W1L[i] and the wiring W2L[i] can be A predetermined potential is applied to each of the holding unit HC and the wiring IL[j] to make the state non-conductive, and Then, the holding unit HCr and the wiring IL[j] are brought into a conductive state. By supplying current, voltage, etc. according to the information of 2, the second information is given to the holding unit HCr. As a result, the circuit MP[i,j] receives w as the first data. i (k-1) j (k) can be set.

[0197] The holding section HC and the holding section HCr each contain almost the same information (for example, voltage, resistance value, etc.). , current, etc.) (first data w i (k-1) j (k) is set by storing approximately equal information in the storage section HC and the storage section HCr. When the holding unit HC is connected to the wiring IL[j], the holding unit HC and the wiring IL[j] are electrically connected to each other. The wiring W1L[i] and the wiring W2L[i] are connected to the wiring IL[j] so that they are in a conductive state. A predetermined potential is applied to each of the wiring IL[j] and the holding unit HC and the holding unit HC. The current, voltage, etc. according to the information may be supplied to the unit HCr.

[0198] The circuit MP[i,j] in FIG. 9D stores the first data w in the holding unit HC and the holding unit HCr. i (k -1) j (k) The potential corresponding to the second data z i (k-1) Wire X with a potential according to 1L[i] and wiring X2L[i], the circuit MP[i,j] in FIG. Similarly, the first data w i (k-1) j (k) and the second data z i (k-1) It is possible to output a current according to the product of

[0199] The circuit MP[i,j] shown in FIG. 9E is a modified example of the circuit MP[i,j] in FIG. 9D. The circuit MP[i,j] of FIG. 9E is the same as the circuit MP[i,j] of FIG. 9D, but is composed of a circuit MC and a circuit MCr, where the circuit MP[i,j] in FIG. 9E and the circuit MP[i,j] in FIG. 9D The configuration of the electrically connected wiring is different.

[0200] Specifically, the circuit MP of FIG. 9E is obtained by adding a wiring ILB[j] to the circuit MP of FIG. 9D, and The wiring W1L[i] and the wiring W2L[i] electrically connected to the circuit MP of FIG. 9D are wired. It has been replaced with WL[i].

[0201] In the circuit MP of FIG. 9E, the wiring IL[j] is electrically connected to the holding unit HC, and the wiring I LB[j] is electrically connected to the holding unit HCr. That is, in the circuit MP of FIG. The wiring IL[j] stores information (for example, voltage, resistance) in the holding unit HC and the holding unit HCr. It functions as a wiring that supplies current, voltage, etc. according to the resistance, current, etc. In the circuit MP, the wiring IL[j] supplies the current, voltage, etc. according to the information to the holding unit HC. The wiring ILB[j] functions as a wiring that transmits current, voltage, etc. according to the information to the holding unit HC. It functions as a supply wiring.

[0202] In the circuit MP of FIG. 9E, the holding unit HC and the holding unit HCr are connected to the wiring IL [j] and the wiring ILB[j] are electrically connected, so the holding part HC and the holding part Information (e.g., voltage, resistance, current, etc.) is simultaneously recorded for each HCr. Therefore, the holding unit HC and the wiring IL[j] are in a conductive state. , or non-conductive state, and the conductive state between the holding part HCr and the wiring ILB[j], or In the circuit MP of FIG. 9D, the holding section The connection between HC and the wiring IL[j] is used as a wiring that controls switching between the conductive state and the non-conductive state. The wiring W1L is illustrated, and the holding part HCr and the wiring ILB[j] are in a conductive state or a non-conductive state. The wiring W2L is shown as the wiring that controls the state switching, but in the circuit MP of FIG. illustrates the wiring WL[i] as a wiring that combines the wiring W1L and the wiring W2L.

[0203] The circuit MP in FIG. 9E corresponds to, for example, the arithmetic circuit 110 in FIG. 2 and the arithmetic circuit 120 in FIG. can be applied.

[0204] The circuit MP[i,j] shown in FIG. 9F is a modified example of the circuit MP[i,j] in FIG. 9A. The circuit MP[i,j] of FIG. 9F is composed of a circuit MC and a circuit However, the circuit MP[i,j] in FIG. 9F has a circuit MC connected to wiring OLB[j ], and the circuit MCr is electrically connected to the wiring OL[j]. 9A and that the circuit MP[i,j] does not include a

[0205] The wiring WL[i] shown in FIG. 9F is electrically connected to the holding unit HC and the holding unit HCr. In addition, the wiring XL[i] shown in FIG. 9F is electrically connected to the circuit MC and the circuit MCr. are actively connected.

[0206] As will be described later, the circuit MP[i,j] in FIG. 9F is a circuit in which the circuit MC is electrically connected to the wiring OLB[j]. , and the circuit MCr is not electrically connected to the wiring OL[j]. 9F differs from the circuits MP[i,j] of FIGS. 9A to 9E in that The current output from the circuit MC does not flow to the wiring OLB[j], and the current output from the circuit MCr is configured so that it does not flow into wiring OL[j].

[0207] Therefore, the circuit MP[i,j] of FIG. 9F receives the second data z i (k-1) is "0", or For example, when the second data z i (k-1) When the value is "1", the circuit MP establishes a conductive state between the circuit MC and the wiring OL[j]. In this state, the circuit MCr and the wiring OLB[j] are electrically connected. Data z i (k-1) When is "0", the circuits MC and MCr each output In order to prevent the current from flowing to either wiring OL[j] or wiring OLB[j], MP is a circuit between the circuit MC and the wiring OL[j], and between the circuit MC and the wiring OLB[j]. The circuit MCr and the wiring OL[j] and the circuit MCr and the wiring OLB[ j] to create a non-conductive state.

[0208] The circuit MP[i,j] in FIG. 9F can be applied to the arithmetic circuit 110 to obtain, for example: is the first data w i (k-1) j (k) can take one of three values: "-1", "0", or "1". Take the second data z i (k-1) When the value is "0" or "1", the calculation is performed. It is possible to do this. i (k-1) j (k) is "-1", "0", "1" , ,any two values, for example, "-1", "1", or "0", It can also be operated in the case of a binary value of "1". i (k-1) j ( k) may take analog or multi-bit (multi-valued) digital values. For example, "negative analog value" instead of "-1" and "positive value" instead of "1". In this case, the magnitude of the current flowing from the circuit MC or the circuit MCr is For example, the first data i (k-1) j (k) Analog according to the absolute value of This becomes the value.

[0209] The circuit MP[i,j] shown in FIG. 10 includes the wiring OL[j] and the wiring OLB[i,j] in the same manner as in FIG. 9A. [j], the first data wi (k-1) j (k) and the second data z i (k-1) Depending on the product of The circuit MP[i,j] in FIG. 10 is a circuit that can output a current. For example, it can be applied to the arithmetic circuit 110 in FIG.

[0210] The circuit MP[i,j] in FIG. 10 includes a circuit MC, a circuit MCr, and a transistor Has MZ.

[0211] The first terminal of the transistor MZ is connected to the first terminal of the circuit MC and the first terminal of the circuit MCr. The second terminal of the transistor MZ is electrically connected to the wiring VL. The gate of the transistor MZ is electrically connected to the wiring XL[i].

[0212] For example, the wiring VL functions as a wiring that applies a constant voltage. It is preferable to determine this by the configuration of MP[i,j] and the arithmetic circuit 110. For example, VDD is a high level potential, VSS is a low level potential, and the ground potential. This can be done.

[0213] 10 is the same as the wiring WLS[i] in the arithmetic circuit 110 in FIG. The wiring WL[i] is electrically connected to the holding part HC and the holding part HCr. It is being done.

[0214] The wiring OL[j] is electrically connected to the second terminal of the circuit MC. OLB[j] is electrically connected to the second terminal of the circuit MCr.

[0215] The wiring IL[j] is electrically connected to the holding unit HC, and the wiring ILB[j] is electrically connected to the holding unit HC. It is electrically connected to the HCr part.

[0216] In the circuit MP[i,j] of FIG. 10, the first data is stored in each of the holding unit HC and the holding unit HCr. The operation when maintaining a potential according to the data is as follows: Please refer to the description of the operation of holding the potential according to the first data.

[0217] In the circuit MP[i,j] of FIG. 10, the circuit MC has a first terminal connected to the wiring VL. When a constant voltage is applied, a current corresponding to the potential held in the holding section HC is generated. The circuit MCr has a function of passing current between the first terminal and the second terminal of the circuit MC. When a constant voltage is applied to the first terminal of the The circuit MCr has a function of passing a current corresponding to the potential between the first and second terminals of the circuit MCr. The first data w is stored in the holding unit HC and the holding unit HCr of the circuit MP[i,j]. i (k -1) j (k) By maintaining a potential according to Determine the amount of current flowing between the first and second terminals of the circuit MCr. It should be noted that a constant voltage is applied to the first terminal of the circuit MC (circuit MCr) through the wiring VL. If not supplied, the circuit MC (circuit MCr) may, for example, It is also possible that no current flows between the first terminal and the second terminal.

[0218] For example, if the first data w of "1" is stored in each of the storage units HC and HCr, i (k-1) j (k) When the potential according to is maintained, a constant voltage is applied to the circuit MC from the wiring VL. By this, the circuit MC flows a predetermined current between the first terminal and the second terminal of the circuit MC. Therefore, a current flows between the circuit MC and the wiring OL. does not allow current to flow between the first and second terminals of the circuit MCr. No current flows between MCr and the wiring OLB. The first data w of "-1" for each of r i (k-1) j (k) The potential is maintained according to When the constant voltage given by the wiring VL is applied to the circuit MC, the circuit MCr , a predetermined current flows between the first terminal and the second terminal of the circuit MCr. At this time, the current flows between the first terminal of the circuit MC and the wiring OLB. Therefore, no current flows between the circuit MC and the wiring OL. For example, if the first data of "0" is stored in each of the holding parts HC and HCr, Ta w i (k-1) j (k) When the potential according to the circuit MC and the circuit MCr is maintained, Regardless of whether a constant voltage is applied to the wiring VL, the circuit MC is connected to the first terminal of the circuit MC. No current flows between the first and second terminals of the circuit MCr. In other words, no current flows between the circuit MC and the wiring OL, and no current flows between the circuit MCr and the wiring OL. No current flows between the lines OLB.

[0219] In the circuit MP[i,j] of FIG. 10, the values held in the holding units HC and HCr are , the first data w i (k-1) j (k) For a specific example of the potential according to P[i,j]. In addition, in the circuit MP[i,j] of FIG. C, the holding unit HCr, like the circuit MP[i,j] in FIG. 9A, does not store potential but current and resistance values. The circuit MC and the circuit MCr have the function of storing information such as It may have a function.

[0220] The wiring XL[i] shown in FIG. 10 corresponds to the wiring XLS[i] in the arithmetic circuit 110 in FIG. The second data z input to the circuit MP[i,j] corresponds to i (k-1) is an example The potential and current of the wiring XL[i] are determined. The gate of MZ is connected to the second data z via the wiring XL[i]. i (k-1) Depending on The potential is input.

[0221] For example, the second data z i (k-1) Consider the case where takes either of the two values "0" or "1". For example, the second data z i (k-1) If is "1", the wire XL[i] has a high level. At this time, the transistor MZ is turned on, so The circuit MP brings the wiring VL and the first terminal of the circuit MC into a conductive state, and the wiring VL and the circuit MC r and the first terminal of the second data z i (k-1) is "1" When this occurs, a constant voltage is applied to the circuit MC and the circuit MCr from the wiring VL. For example, the second data zi (k-1) When is "0", the wire XL[i] has a low level potential. In this case, the circuit MP is a non-transitory circuit between the circuit MC and the wiring OLB[j]. The second device is in a conductive state, and the second device is in a non-conductive state. Data z i (k-1) When is "0", the circuit MC and the circuit MCr are connected to the wiring VL. No constant voltage is given by these.

[0222] Here, for example, the first data w i (k-1) j (k) is "1", and the second data z i (k-1) When is "1", current flows between the circuit MC and the wiring OL, and the circuit MC As a result, no current flows between r and the wiring OLB. i ( k-1) j (k) is "-1", and the second data z i (k-1) If is "1", No current flows between circuit MC and wiring OL, and current flows between circuit MCr and wiring OLB. For example, the first data w i (k-1) j (k) is "0" , second data z i (k-1) is "1", the line between the circuit MC and the wiring OL, and the line between the circuit MC and the wiring OL As a result, no current flows between MCr and the wiring OLB. i (k-1) is "0", the first data w i (k-1) j(k) is "-1", "0 " or "1", the circuit MC and the wiring OL, and the circuit MCr and the wiring O As a result, no current flows between LB.

[0223] That is, the circuit MP[i,j] in FIG. 10 is, for example, similar to the circuit MP[i,j] in FIG. 9F. As the first data w i (k-1) j (k) can take one of the three values "-1", "0", or "1" and the second data z i (k-1) When takes two values, "0" and "1", 9F, the circuit MP[i,j] of FIG. i,j] is the first data w i (k-1) j (k) is "-1", "0", or "1", Any two values, for example, "-1" and "1", or "0" and "1" It can also be operated in the case of the first data w i (k-1) j (k) Yes, Anna It may take a logarithmic value or a multi-bit (multi-value) digital value. "Negative analog value" instead of "-1" and "Positive analog value" instead of "1" In this case, the magnitude of the current flowing from the circuit MC or the circuit MCr can be, for example, As for the first data, i (k-1) j (k) It becomes an analog value according to the absolute value of the value.

[0224] <Example of operation of an arithmetic circuit> Next, an example of the operation of the arithmetic circuit 140 in Fig. 7 will be described. In the explanation of this example of operation, As an example, an arithmetic circuit 140 shown in FIG. 13 is used.

[0225] The arithmetic circuit 140 in FIG. 13 is configured by focusing on the circuit located in the j-th column of the arithmetic circuit 140 in FIG. That is, the arithmetic circuit 140 of FIG. 13 is the same as the neural network shown in FIG. 1A. Neuron N in network 100 j (k) neuron N1 (k -1) Neuron N m (k-1) Signal z1 from (k-1) ~z m (k-1) and, Weighting factor w1 (k-1) j (k) Or even w m (k-1) j (k) and the sum of products of It corresponds to the circuit that performs the calculation of the activation function using the result of the sum calculation. The circuit MP included in the array portion ALP of the circuit 110 is the circuit MP of FIG. 9B. It shall be.

[0226] First, in the arithmetic circuit 140, the first Data w1 (k-1) j (k) Or even w m (k-1) j (k) The first data w is set. i (k-1) j (k) As a method of setting, the wiring WLS[1] A predetermined potential is input to the wiring WLS[m] in order, and the circuits MP[1,j] to MP[m , j] in order, and the circuits MC and MC included in the selected circuit MP are selected. For each of the holding units HC and HCr of the r, the circuit ILD is connected to the switching circuit Through TW[j], wiring OL[j], OLB[j], etc., potential, current, etc. according to the first data are generated. After supplying the potential, current, etc., the circuit WLD supplies the circuit MP[1, By deselecting each of the circuits MP[1,j] to MP[m,j], to the circuits MP[m,j], the circuits MC and MCr included in each of the circuits MP[m,j] The first data w1 is stored in the storage section HC and the storage section HCr. (k-1) j (k) Or even w m (k-1) j ( k) As an example, the potential, current, etc. according to the first data w1 ( k-1) j (k) Or even w m (k-1) j (k) For each of the above, if it takes a positive value, In the case of HC, a value corresponding to the positive value is input, and in the case of HCr, a value corresponding to zero is input. On the other hand, the first data w1 (k-1) j (k) Or even w m (k-1) j (k) If each of the values is negative, enter a value equivalent to zero in the holding section HC. A value corresponding to the absolute value of the negative value is input to the holding unit HCr.

[0227] Next, the wirings X1L[1] to X1L[m] and X2L[1 ] to wiring X2L[m], (k-1) ~z m (k-1) of As a specific example, the second data is supplied to the wiring X1L[i] and the wiring X2L[i]. z1 (k-1) The wiring X1L[i] and the wiring X2L[i] are connected as shown in FIG. This corresponds to the wiring XLS[i] of the arithmetic circuit 140 shown in FIG.

[0228] Second data z1 input to each of the circuits MP[1,j] to MP[m,j] ( k-1) ~z m (k-1) According to the circuit MP[1,j] to the circuit MP[m,j], The conduction state between the circuit MC and the circuit MCr and the wiring OL[j] and the wiring OLB[j] As a specific example, the circuit MP[i,j] is determined by the second data z i (k-1) In response As a result, "continuity occurs between the circuit MC and the wiring OL[j], and the circuit MCr and the wiring OLB[j] and "conduction occurs between the circuit MC and wiring OLB[j], and the circuit MCr and wiring OL[j] are electrically connected, and the circuit MC and the circuit MCr are electrically connected. and "they are not electrically connected to the wiring OL[j] and wiring OLB[j], respectively." As an example, the second data z1 (k-1) If the value is positive, X1L[1] is connected to the circuit MC and the wiring OL[j], and the circuit MC Enter a value that allows conduction between r and wiring OLB[j]. X2L[1] has a state where the circuit MC and the wiring OLB[j] are in a non-conductive state, and the circuit Enter a value that allows the connection between MCr and the wiring OL[j] to be non-conductive. Second data z1 (k-1) If the value is negative, the wiring X1L[1] has a The circuit MC and the wiring OLB[j] are in a conductive state, and the circuit MCr and the wiring OL[j] Then, input a value that allows the connection between the The circuit MC and the wiring OL[j] are in a non-conductive state, and the circuit MCr and the wiring OLB[j ] and the second data z1 (k- 1) When the value of 0 is taken, the wiring X1L[1] has the circuit MC and the wiring OLB [j] is in a non-conductive state, and the circuit MCr and the wiring OL[j] are in a non-conductive state. Then, input the value that can be set to the state of the circuit MC and the wiring O into the wiring X2L[1]. L[j] is in a non-conductive state, and the circuit MCr and the wiring OLB[j] are in a non-conductive state. Enter the value that can be used to establish a normal state.

[0229] The second data z input to the circuit MP[i,j] i (k-1) Depending on the circuit MP[i, The circuit MC and the circuit MCr included in [j] and the wiring OL[j] and the wiring OLB[j] are connected to each other. The conduction state or non-conduction state between the circuit MC and the circuit MCr and the wiring is determined by the determination. Current is input / output between OL[j] and wiring OLB[j]. The amount is the first data w set in the circuit MP[i,j]. i (k-1) j (k) and / or 2 Datazi (k-1) It depends on:

[0230] For example, in the circuit MP[i,j], the wiring OL[j] is connected to the circuit MC or the circuit MCr. Let I[i,j] be the current flowing through the wiring OLB[j] to the circuit MC or the circuit MCr. The current flowing through the B Then, the current flows from the circuit ACTF[j] to the wiring OL[j]. The current flowing through the out [j], and the current flowing from wiring OLB[j] to circuit ACTF[j] I Bout If [j], then I out [j] and I Bout [j] can be expressed by the following formula: This can be done.

[0231]

number

[0232] In the circuit MP[i,j], as an example, the first data w i (k-1) j (k) "+ 1", the circuit MC outputs I(+1) and the circuit MCr outputs I(-1). The first data w i (k-1) j (k) When is "-1", the circuit MC is I(-1 ) and the circuit MCr outputs I(+1), and the first data w i (k-1) j (k) When is "0", the circuit MC emits I(-1) and the circuit MCr emits I(-1). shall be discharged.

[0233] Furthermore, the circuit MP[i,j] receives the second data z i(k-1) When is "+1", Conduction occurs between the circuit MC and the wiring OL[j], and conduction occurs between the circuit MCr and the wiring OLB[j]. Conduction occurs, and there is no conduction between the circuit MC and the wiring OLB[j], and there is no conduction between the circuit MCr and the wiring OL [j] is in a non-conductive state, and the second data z i (k-1) is "-1" When this happens, "there is conduction between the circuit MC and the wiring OLB[j], and the circuit MCr and the wiring OL[j ] becomes conductive, and the circuit MC and the wiring OL[j] become non-conductive, and the circuit MCr and The second data z i (k-1) is "0 "When "circuit MC and wiring OL[j], and circuit MC and wiring OLB[ There is no conduction between the circuit MCr and the wiring OL[j], and there is no conduction between the circuit MCr and the wiring OL[j] and between the circuit MCr and the wiring OL[j]. and OLB[j] are in a non-conductive state.

[0234] At this time, in the circuit MP[i,j], the wiring OL[j] is connected to the circuit MC or the circuit MC The current I[i,j] flowing through r and the current I[i,j] flowing from wiring OLB[j] to circuit MC or circuit MCr The current I B [i,j] is as shown in the table below. In some cases, I(- The circuit MP[i,j] may be configured so that the current amount of 1) is 0. i,j] may be a current flowing from the circuit MC or the circuit MCr to the wiring OL[j]. Similarly, the current I B [i,j] flows from the circuit MC or the circuit MCr to the wiring OLB[j]. It may also be an electric current.

[0235] [Table 1]

[0236] Then, I flowing from each of the wiring OL[j] and wiring OLB[j] out [ j] and I Bout [j] is input to the circuit ACTF[j]. , Circuit ACTF[j] is, for example, I out [j] and I Bout [j] comparison The circuit ACTF[j] performs, for example, the following operations depending on the result of the comparison: N j (k) is the signal z sent to the (k+1)th layer neuron. j (k) Output.

[0237] As an example, the arithmetic circuit 140 of FIG. j (k) is entered into , neuron N1 (k-1) Neuron N m (k-1) Signal z1 from (k-1) No Toz m (k-1) and weighting factor w1 (k-1) j (k) Or even w m (k-1) j (k) and, and a calculation of an activation function using the result of the product-sum calculation. Furthermore, in the array part ALP of the arithmetic circuit of FIG. 13, by providing n columns of circuits MP, In other words, the arithmetic circuit 140 of FIG. Neuron N1 (k) Neuron N n (k) The multiplication and accumulation operations in each of the This can be done simultaneously with the calculation of the activation function using the result of the product-sum calculation.

[0238] <<Example of changing circuits included in the arithmetic circuit>> The above-mentioned arithmetic circuit 110, arithmetic circuit 120, arithmetic circuit 130, arithmetic circuit 140, arithmetic circuit The circuit 150 and the calculation circuit 160 each perform the calculation of the formula (1.3) instead of the calculation of the formula (1.2). Equation (1.3) can be modified to a circuit that performs the sum of products in equation (1.2). Therefore, the calculation circuit 110, the calculation circuit 120, and the calculation circuit In each of the arithmetic circuits 130, 140, 150, and 160, the wiring O A circuit for applying a bias value to L and wiring OLB may be provided.

[0239] The arithmetic circuit 170 shown in FIG. 14 includes a circuit BS The circuit configuration includes circuits [1] to BS[n].

[0240] The circuit BS[j] is composed of wiring OL[j], wiring OLB[j], wiring WLBS, and wiring W The XBS is electrically connected to the

[0241] The wiring WLBS corresponds to the wirings WLS[1] to WLS[m] of the arithmetic circuit 110 in FIG. , similar to the wirings WL[1] to WL[m] of the arithmetic circuit 140 of FIG. 1] to BS[n], the write switching elements included in the circuits BS[n] are turned on or off. Therefore, the wiring WLBS functions as a wiring for supplying a signal to By electrically connecting the circuit WLD to the wiring WLBS, The signal can be provided.

[0242] The wiring WXBS corresponds to the wirings XLS[1] to XLS[m] of the arithmetic circuit 110 in FIG. Similarly, neuron N i (k-1) The second data z output from i (k-1) Corresponding to The information (for example, potential, current value, etc.) is supplied to the circuits BS[1] to BS[n]. Therefore, the wiring WXBS is electrically connected to the circuit XLD. This allows the information to be supplied from the circuit XLD to the wiring WXBS.

[0243] The wiring WXBS is connected to the wirings WX1L[1] to WX1L[2] of the arithmetic circuit 140 in FIG. 1L[n], a selection signal for writing information to the circuits BS[1] to BS[n] In the arithmetic circuit 170 of FIG. 14, the wiring WXBS is connected to the circuit WLD In this configuration, the circuit WLD is electrically connected to the wiring The wirings WLBS and WXBS are connected to the wirings BS[1] to BS[n]. A signal can be supplied to turn the write switching element on or off. Cut.

[0244] In the jth column of the array unit ALP of the arithmetic circuit 170, the circuits MP[1,j] to MP[ The amount of current flowing from [m,j] to wiring OL[j] or wiring OLB[j] is given by the formula (1. 5), can be expressed by equation (1.6). Since each of them is electrically connected to the circuit BS[j], the wiring OL The current flowing through [j] is I BIAS [j], flows from circuit BS[j] to wiring OLB[j] Current is I BIASBWhen [j] is used, equations (1.5) and (1.6) are expressed as follows: can be rewritten as:

[0245]

number

[0246] This allows us to calculate the bias in equation (1.3) by using I out [j] and I B out [j] can be generated. Also, I out [j] and I Bout [j] is biased by being input to the circuit ACTF[j] , neuron N j (k) Output signal z from j (k) can be generated.

[0247] In the arithmetic circuit 170 of FIG. 14, the circuits BS[1] to BS[n] are the array unit ALP However, one embodiment of the present invention is not limited to this. The circuits BS[1] to BS[n] may be provided in two or more rows in the array portion ALP.

[0248] The above-mentioned array part ALP, circuit ILD, circuit WLD, circuit XLD, circuit AFP, circuit Some or all of the transistors included in MP, switching circuit TW, etc. For example, the transistor is preferably an OS transistor. In the case of a transistor where it is desirable to have a capacitance element, for example, The transistor having a function of retaining accumulated charge is preferably an OS transistor. In particular, when an OS transistor is used as the transistor, In particular, the OS transistor preferably has the structure described in Embodiment 4. The metal oxide contained in the channel forming region of the transistor is, for example, indium, element M (element M is aluminum, gallium, yttrium, or tin), zinc or It can be made of a number of materials, in particular metals consisting of indium, gallium and zinc. Oxides are semiconductors that have a high bandgap and are intrinsic (also called type I) or substantially intrinsic. A conductor, wherein the carrier concentration of the metal oxide is 1×10 18 cm -3 Is less than or equal to is preferred, and 1×10 17 cm -3 More preferably, it is less than 1×10 16 cm - 3 More preferably, it is less than 1×10 13 cm -3 It is even more preferable that it is less than 1×10 12 cm -3 It is more preferable that the metal oxide is less than 100%. The off-state current of the OS transistor included in the channel formation region is 1 μm per 1 μm of channel width. 0aA(1×10 -17 A) or less, preferably 1 aA (1 × 10 -18 A) or less, and more preferably 10 zA (1 × 10 -20 A) or less, more preferably 1 zA (1 × 10 -21 A) Below, More preferably, 100 yA (1×10 -22 A) The following shall be done: In addition, the OS transistor can be formed by using an OS transistor because the carrier concentration of the metal oxide is low. Even if the temperature of the transistor changes, the off-state current remains low. Even when the temperature of the transistor is 150°C, the off-state current is 100 zA per 1 μm of channel width. It can also be done as follows.

[0249] However, one embodiment of the present invention is not limited to the above, and the array portion ALP, the circuit ILD, the circuit W Transistors included in LD, circuit XLD, circuit AFP, circuit MP, switching circuit TW, etc. The transistor does not have to be an OS transistor. A transistor that contains silicon in the channel formation region (hereafter referred to as a Si transistor). The silicon may be, for example, single crystal silicon or hydrogenated amorphous silicon. Silicon, microcrystalline silicon, polycrystalline silicon, etc. can be used. Transistors other than Si transistors include semiconductors such as Ge. Transistors with silicon as the active layer, ZnSe, CdS, GaAs, InP, GaN, SiG transistors with compound semiconductors such as silicon dioxide as the active layer, and transistors with carbon nanotubes as the active layer A transistor having an organic semiconductor as an active layer, or a transistor having an organic semiconductor as an active layer can be used.

[0250] In the metal oxide semiconductor layer of the OS transistor, a metal oxide containing indium In oxides containing zinc (e.g., In oxide), Although n-type semiconductors have been successfully fabricated, p-type semiconductors are difficult to fabricate due to mobility and reliability issues. Therefore, the calculation circuit 110, the calculation circuit 120, the calculation circuit 130, and the calculation circuit 14 0, the arithmetic circuit 150, the arithmetic circuit 160, and the arithmetic circuit 170 are the array unit ALP, the circuit ILD , n-channel transistors included in circuits WLD, XLD, AFP, and MP. An OS transistor is used as the p-channel transistor, and a Si transistor is used as the p-channel transistor. It may also be configured to apply a .

[0251] Note that this embodiment mode can be appropriately combined with other embodiment modes shown in this specification. do.

[0252] (Embodiment 2) In this embodiment, a specific configuration example of the circuit MP described in the first embodiment will be described. do.

[0253] In the first embodiment, the reference numerals of the circuits MP are denoted by [1,1 ], [i,j], [m,n], etc. are added, but in this embodiment, unless otherwise specified, The notation [1,1], [i,j], [m,n], etc. is omitted for the symbols of the MP.

[0254] <Configuration example 1> First, an example of a circuit configuration that can be applied to the circuit MP of FIG. 9B will be described. The circuit MP shown in FIG. 9B is an example of the configuration of the circuit MP shown in FIG. 15A. The circuit MC includes, for example, transistors M1 to M4, a capacitor C1, For example, the holding unit HC is configured by the transistor M2 and the capacitor C1. It has been done.

[0255] In the circuit MP of FIG. 9B, the circuit MCr has a circuit configuration similar to that of the circuit MC. Therefore, the circuit elements of the circuit MCr are different from the circuit elements of the circuit MC. To distinguish between them, the symbol is prefixed with "r."

[0256] The transistors M1 to M4 shown in FIG. 15A are, for example, The transistor is an n-channel type with a multi-gate structure that has gates above and below the channel. Each of the transistors M1 to M4 has a first gate and a second gate. In particular, as an example, the sizes of the transistors M3 and M4 are However, in this specification and the like, for convenience, as an example, the first gate The first gate is the gate (sometimes referred to as the front gate), and the second gate is the back gate. Although they are written to distinguish between them, the first gate and the second gate can be interchanged. Therefore, in this specification, the term "gate" is replaced with the term "back gate." Similarly, the phrase "back gate" can be written interchangeably with "gate " can be written in place of the phrase "The gate is connected to the first wiring." the back gate is electrically connected to the second wiring. The structure is such that the back gate is electrically connected to the first wiring and the gate is electrically connected to the second wiring. For example, in the case shown in FIG. 15B, The back gate of the transistor M1 is connected to the first terminal of the capacitor C1 and the third terminal of the transistor M2. The configuration may be such that the first terminal is electrically connected to the second terminal.

[0257] Furthermore, the semiconductor device of one embodiment of the present invention can be used without depending on the connection structure of the back gate of the transistor. The transistors M1 to M4 shown in FIG. The back gate is shown in the figure, and the connection configuration of the back gate is not shown. The electrical connection destination of the back gate can be determined at the design stage. For example, In a transistor having a gate and For example, the gate of the transistor M2 may be electrically connected to the back gate. The back gate may be electrically connected to the transistor. In a transistor, to vary the threshold voltage of the transistor or Wiring electrically connected to external circuits to reduce the off-state current of the transistor and a potential may be applied to the back gate of the transistor by the external circuit or the like. This is not only shown in Figure 15A, but also in other parts of the specification. The same is true for the transistors shown in the other drawings.

[0258] In addition, a semiconductor device according to one embodiment of the present invention may include a transistor having a structure For example, the transistors M1 to M4 shown in FIG. As shown in FIG. 15C, a configuration without a back gate, i.e., a single gate In addition, some of the transistors may have a back gate. Another part of the transistors may have no back gate. This is not only explained in the circuit diagram shown in FIG. 15A, but also in other parts of the specification. The same applies to the transistors shown in the drawings or the transistors shown in other drawings. do.

[0259] In this specification and the like, transistors having various structures are used as transistors. Therefore, there is no limitation on the type of transistor to be used. Examples include transistors with single crystal silicon, or transistors with amorphous silicon, polycrystalline silicon, etc. Silicon, microcrystalline (also called microcrystal, nanocrystal, or semi-amorphous) A transistor having a non-single-crystal semiconductor film, such as a silicon nitride film, can be used. Alternatively, thin film transistors (TFTs) made from these semiconductors can be used. There are various advantages to using TFTs. For example, it is Since it can be manufactured at a very low temperature, it is possible to reduce manufacturing costs and increase the size of manufacturing equipment. Since the manufacturing equipment can be made larger, it is possible to manufacture on large substrates. Since a large number of display devices can be manufactured, they can be manufactured at low cost. Therefore, a substrate having low heat resistance can be used. Alternatively, a transistor on a light-transmitting substrate can be used to manufacture a display element. It is possible to control the light transmission. Also, because the film thickness of the transistor is thin, A part of the film that forms the capacitor can transmit light, which improves the aperture ratio. It is possible.

[0260] An example of a transistor is a compound semiconductor (e.g., SiGe, GaAs, etc.). ), or oxide semiconductors (e.g., Zn-O, In-Ga-Zn-O, In-Zn-O, I n-Sn-O(ITO), Sn-O, Ti-O, Al-Zn-Sn-O(AZTO), I A transistor having a material such as n-Sn-Zn-O can be used. These compound semiconductors or thin film transistors made by thinning these oxide semiconductors These can be used to lower the manufacturing temperature, for example, As a result, it is possible to manufacture a resistor on a substrate with low heat resistance, such as a plastic The transistor can be formed directly on a substrate or a film substrate. Compound semiconductors or oxide semiconductors are used not only for the channel portion of transistors but also for For example, these compound semiconductors or oxide semiconductors can be used for other purposes. It can be used as a wiring, a resistor element, a pixel electrode, or a light-transmitting electrode. These can be deposited or formed simultaneously with the transistor, thereby reducing costs.

[0261] An example of a transistor is a transistor formed by an ink-jet method or a printing method. These can be used for manufacturing at room temperature, manufacturing at low vacuum, or can be manufactured on a large substrate. Therefore, it can be manufactured without using a mask (reticle). This allows the transistor layout to be easily changed. Alternatively, it can be manufactured without using resist, which reduces material costs and the number of processes. Or, since it is possible to apply the film only to the necessary parts, after forming the film on the entire surface, This method wastes less material and is less costly than the conventional etching method.

[0262] An example of a transistor is a transistor having an organic semiconductor or a carbon nanotube. This allows transistors to be mounted on a flexible substrate. Transistors using organic semiconductors and carbon nanotubes can be formed. The device using this can be made shock resistant.

[0263] Note that transistors with various other structures can also be used. For example, transistors include MOS transistors, junction transistors, and bipolar transistors. A MOS transistor can be used as the transistor. By using this, the size of the transistor can be reduced. It is possible to mount a bipolar transistor as a transistor. This allows a large current to flow, making it possible to operate the circuit at high speed. It is also possible to combine MOS transistors and bipolar transistors on the same substrate. This makes it possible to achieve low power consumption, miniaturization, high-speed operation, etc. can.

[0264] An example of a transistor is a structure in which gate electrodes are arranged above and below an active layer. The transistor can be applied to a structure in which gate electrodes are arranged above and below the active layer. This results in a circuit configuration in which multiple transistors are connected in parallel. Since the channel forming region increases, the current value can be increased. The structure in which gate electrodes are arranged above and below makes it easier for a depletion layer to form. , the S value can be improved.

[0265] An example of a transistor is a structure in which a gate electrode is disposed on an active layer. A structure in which a gate electrode is placed under an active layer, a normal staggered structure, an inverted staggered structure, a channel A structure in which the region is divided into multiple regions, a structure in which the active layers are connected in parallel, or a structure in which the active layers are connected in series Alternatively, a transistor having a structure such as a pre-transistor may be used. NA type, FIN type, TRI-GATE type, top gate type, bottom gate type, double gate type (gates are placed above and below the channel), etc. A variety of configurations can be used.

[0266] An example of a transistor is a transistor in which a source electrode or a drain electrode is formed in the active layer (or a part thereof). A transistor with an overlapping active layer (or its equivalent) can be used. By using a structure in which the source electrode and drain electrode overlap with part of the active layer, This can prevent the operation from becoming unstable due to accumulation of electric charges.

[0267] As an example of a transistor, a structure provided with an LDD region can be applied. By providing a region, the off-state current can be reduced or the withstand voltage of the transistor can be improved (reliability can be improved). Alternatively, by providing an LDD region, it is possible to , even if the voltage between the drain and source changes, the drain current does not change much, and the slope is A flat voltage-current characteristic can be obtained.

[0268] For example, in this specification and the like, transistors can be formed using various substrates. The type of substrate is not limited to a specific one. Conductor substrates (e.g., single crystal substrates or silicon substrates), SOI substrates, glass substrates, quartz substrates, Plastic substrate, sapphire glass substrate, metal substrate, stainless steel substrate, stainless Substrate with less steel foil, tungsten substrate, tungsten foil Substrates, flexible substrates, laminated films, paper containing fibrous materials, base film, etc. Examples of glass substrates include barium borosilicate glass and aluminoborosilicate glass. Glass or soda lime glass. Flexible substrates, laminating films, base film Examples of films include polyethylene terephthalate. Polyethylene naphthalate (PET), Polyethersulfone (PES) ), and polytetrafluoroethylene (PTFE) are typical plastics. For example, synthetic resin such as acrylic resin is used. Examples include polyethylene, polyester, polyvinyl fluoride, and polyvinyl chloride. Examples of the material include polyamide, polyimide, aramid, epoxy resin, inorganic vapor deposition film, and the like. In particular, transistors are manufactured using semiconductor substrates, single crystal substrates, or SOI substrates. By manufacturing the capacitors, there is little variation in characteristics, size, or shape, and current capacity is This allows for the production of high-power, small-sized transistors. By configuring a circuit using a capacitor, it is possible to reduce the power consumption of the circuit or to increase the integration density of the circuit. Cut.

[0269] In addition, a flexible substrate is used as the substrate, and a transistor is formed directly on the flexible substrate. Alternatively, a separation layer may be provided between the substrate and the transistor. After a semiconductor device is partially or completely completed, it is separated from the substrate and transferred to another substrate. In this case, the transistor can be transferred to a substrate with poor heat resistance or a flexible substrate. The above-mentioned peeling layer may be formed of an inorganic film such as a tungsten film and a silicon oxide film. It uses a laminated film structure or a structure in which an organic resin film such as polyimide is formed on a substrate. It is possible.

[0270] That is, a transistor is formed using one substrate, and then a transistor is formed on another substrate. The transistor may be transposed and placed on another substrate. For example, in addition to the substrate on which the above-mentioned transistors can be formed, a paper substrate, a cellophane substrate, etc. Fan board, aramid film board, polyimide film board, stone board, wood board, cloth Substrate (natural fibers (silk, cotton, linen), synthetic fibers (nylon, polyurethane, polyester) or recycled fibers (including acetate, cupra, rayon, recycled polyester, etc.), There are leather substrates, rubber substrates, etc. By using these substrates, Formation of transistors, formation of low power consumption transistors, manufacturing of durable devices, heat resistance It is possible to provide a lighter, thinner, or more flexible device.

[0271] All circuits required to realize a given function are mounted on the same substrate (e.g., glass It can be formed on a substrate such as a silicon substrate, a plastic substrate, a single crystal substrate, or an SOI substrate. This reduces the cost by reducing the number of components, or reduces the number of connections to circuit components. This can improve reliability.

[0272] It is possible that not all of the circuits required to realize a given function are formed on the same substrate. In other words, part of the circuitry required to achieve a given function can be formed on a certain substrate. Another part of the circuitry required to realize a given function is formed on a different substrate. For example, some of the circuits required to realize a given function can be Another part of the circuitry required to realize a specific function is formed on the single crystal substrate. It can be formed on a substrate (or SOI substrate) and realizes a predetermined function. The single crystal substrate (also called an IC chip) on which another part of the circuitry required for (Chip On Glass) connects to the glass substrate and Alternatively, the IC chip can be mounted on a TAB (Tape Au tomated Bonding), COF(Chip On Film), SMT(S Surface Mount Technology) or a printed circuit board. In this way, part of the circuit is formed on the same substrate as the pixel section. This reduces the number of components, thereby reducing costs, and This reduces the number of circuits, which improves reliability. Also, circuits with high drive frequencies often consume a lot of power. Therefore, such a circuit is formed on a substrate (for example, a single crystal substrate) separate from the pixel section, and By using this IC chip, it is possible to prevent an increase in power consumption. Cut.

[0273] In the circuit MP of FIG. 15A, a first terminal of the transistor M1 is electrically connected to the wiring VE. The second terminal of the transistor M1 is connected to the first terminal of the transistor M3. The gate of transistor M1 is electrically connected to the first terminal of transistor M4. The first terminal of the capacitor C1 is electrically connected to the first terminal of the transistor M2. The second terminal of the transistor C1 is electrically connected to the wiring VE. The gate of the transistor M2 is electrically connected to the wiring WL. The second terminal of the transistor M3 is electrically connected to the wiring OL. The gate of the transistor M3 is electrically connected to the wiring WX1L. The terminal is electrically connected to the wiring OLB, and the gate of the transistor M4 is electrically connected to the wiring X2L. are actively connected.

[0274] The circuit MCr has a different connection configuration from the circuit MC. The second terminal of the transistor M4r is electrically connected to the wiring OLB instead of the wiring OL. The second terminal of the transistor M is electrically connected to the wiring OL, not to the wiring OLB. The first terminal of the capacitor C1r and the first terminal of the capacitor C1r are electrically connected to the wiring VEr. .

[0275] As shown in FIG. 16A, the first terminal of the transistor M1 is connected to a separate Similarly, the first wiring VLm of the transistor M1r may be electrically connected to the first wiring VLm of the transistor M1r. The first terminal may be electrically connected to another wiring VEmr instead of the wiring VEr. In the circuit diagrams of not only FIG. 15A but also other drawings, the first terminal of the transistor M1 is , a configuration in which the wiring VE is electrically connected to another wiring VEm instead of the wiring VE, and / or The first terminal of the transistor M1r is electrically connected to another wiring VEmr, not to the wiring VEr. The configuration may be such that

[0276] In the holding unit HC shown in FIG. 15A, the gate of the transistor M1 and the The electrical connection point between the first terminal and the first terminal of the transistor M2 is referred to as a node n1.

[0277] As described in the first embodiment, the holding unit HC holds, for example, an electric current corresponding to the first data. The potential to the holding unit HC included in the circuit MC of FIG. When the transistors M2 and M3 are turned on, the line OL A potential is input from the capacitor C1, and then the transistor M2 is turned off. This allows the potential of the node n1 to be maintained as a potential corresponding to the first data. At this time, a current is input from the wiring OL, and the Therefore, the current characteristic of the transistor M1 is This can reduce the effects of gender variation.

[0278] In addition, since the transistor M1 holds the potential of the node n1 for a long time, the off-state current is small. It is preferable to use a transistor with a low off-state current. For example, an OS transistor can be used as the transistor M1. A transistor having a gate is applied, and a low level potential is applied to the back gate to reduce the threshold voltage. may be shifted to the positive side to reduce the off-state current.

[0279] In the operation example described later, in order to simply explain the current flowing in and out of the circuit MP, The two ends of the wiring OL shown in 15A are the nodes ina and outa, respectively, and the wiring OLB The two ends of are node inb and node outb, respectively.

[0280] The wiring VE functions as a wiring for supplying a constant voltage, for example. is the transistor M3, the transistor M3r, the transistor M4, or the transistor When M4r is an n-channel transistor and / or when the wiring VSO is given in FIG. If the potential to be applied is a high level potential, for example, VSS, which is a low level potential, or ground potential , or other low level potentials. The wiring VEr and wiring VLmr are voltage lines that supply a constant voltage, just like the wiring VE. The constant voltage includes VSS, which is a low-level potential, a low-level potential other than VSS, The constant voltage may be a high level potential VD In this case, the calculation circuit 110, the calculation circuit 120, the calculation circuit 130, the calculation circuit The circuits ACTF[1] to ACTF[n] of the circuit 140, the arithmetic circuit 150, and the arithmetic circuit 160 5A to 5E, 6A to 6D, or 6F is applied. , a wiring VAL electrically connected to the circuits ACTF[1] to ACTF[n] is given. The constant voltage to be applied is preferably higher than the potential VDD given by the wiring VE and wiring VEr. It's nice.

[0281] In addition, the wiring VE, the wiring VEm, the wiring VEr, and the wiring VEmr each supply The constant voltages may be different from each other, or some or all of them may be the same. If the voltages supplied by these wires are the same, select them and For example, each of the wiring VE, the wiring VEm, the wiring VEr, and the wiring VEmr may be When the constant voltages given by the wiring VEm and the wiring VE are almost equal, as shown in the circuit MP of FIG. 16B, r, and the wiring VEmr can be the same wiring as the wiring VE. When the constant voltages applied to the line VL and the wiring VLr are approximately equal, For example, the wiring VLs and the wiring VL When the constant voltages applied to the wires VLs and VLsr are approximately equal, the wires VLs and VLsr can be connected to a single Similarly, in FIG. 16A, for example, the wiring VL and the wiring VLr is considered to be one and the same wiring, and VLm and VLmr are considered to be one and the same wiring. Alternatively, for example, the wiring VL and the wiring VLmr may be one and the same wiring. VLm and the wiring VLr may be one and the same wiring.

[0282] The configuration of the circuit MP in FIG. 15A can be changed depending on the situation. For example, As shown in FIG. 17A, the transistors M1 and M1r in the circuit MP of FIG. 15A Those of transistor M3, transistor M3r, transistor M4, and transistor M4r These are p-channel transistors M1p, M1pr, and Transistor M3p, transistor M3pr, transistor M4p, transistor M4pr The transistor M3p, the transistor M3pr, and the transistor M4p may be replaced with As an example of the transistor M4pr, SOI (Silicon On In) A p-channel transistor with a sulator structure can be applied. In this case, the constant voltage given by the wiring VE and wiring VEr is set to VDD, which is a high-level potential. In addition to this case, the arithmetic circuit 110, the arithmetic circuit 120, and the arithmetic circuit 130 are preferably , the circuits ACTF[1] to ACTF[2] of the arithmetic circuit 140, the arithmetic circuit 150, and the arithmetic circuit 160. ACTF[n] is applied to any one of FIGS. 5A to 5E, 6A to 6D, and 6F. If the circuit ACTF[1] to the circuit ACTF[n] are electrically connected to the The constant voltage provided by the line VAL is preferably the ground potential or VSS. If the potential of the wire is changed, the direction of the current flow will also be changed.

[0283] Similarly, transistor M2 is replaced with a p-channel transistor. Good too.

[0284] Also, for example, as shown in FIG. 17B, the transistors M4 and M4r in the circuit MP of FIG. 15A are replaced with p-channel transistors M4p and M4pr, respectively. Also, the transistor M3, the transistor M3r, the transistor M4p, the transistor Combine the wires connected to each gate of the register M4pr into one wire, WXL. By this, the circuit MP can hold the first data (for example, weight coefficient) other than 0. This can be done.

[0285] Also, for example, as shown in FIG. 17C, the transistor M3 of the circuit MP of FIG. 15A, The transistor M3r, the transistor M4, and the transistor M4r are connected to analog switch A. S3, Analog switch AS4, Analog switch AS3r, Analog switch AS4r In addition, in FIG. 17C, the analog switch AS3, the analog switch To operate the analog switch AS4, the analog switch AS3r, and the analog switch AS4r, The wiring WX1LB and wiring X2LB are also shown. The wiring WX1LB is connected to the analog switch. The wiring X2LB is electrically connected to the analog switch AS3 and the analog switch AS3r. The wiring WX is electrically connected to the analog switch AS4 and the analog switch AS4r. The inverted signal of the signal input to the wiring WX1L is input to the wiring X1LB, and the inverted signal of the signal input to the wiring X2LB is input to the wiring X2LB. An inverted signal of the signal input to the wiring X2L is input to the wiring WX1L and the wiring X 2L are combined into one wire, and the wires WX1LB and X2LB are combined into one wire. As an example, the analog switch AS3, the analog The analog switch AS4, the analog switch AS3r, and the analog switch AS4r are As a CMOS configuration using n-channel transistors and p-channel transistors, good.

[0286] 15A to 15C and 16A to 16C. The sizes of the transistors M3r, M4, and M4r, e.g., It is preferable that the length and width of the channels are equal to each other. This may allow for a more efficient layout. The currents flowing through M3r, transistor M4, and transistor M4r can be made uniform. Similarly, the transitions shown in FIGS. 15A to 15C and 16A to 16C may be It is preferable that the transistors M1 and M1r have the same size. Similarly, the transistor M2 shown in FIGS. 15A to 15C and 16A to 16C It is preferable that the sizes of the transistors M2r are equal to each other. The sizes of the transistors M1p and M1pr shown in Similarly, the transistor M3p shown in FIG. r, transistor M4p, and transistor M4pr are preferably equal in size. I wish.

[0287] <<Example of operation>> Next, an example of the operation of the circuit MP shown in FIG. 15A will be described. 10 is a timing chart showing an example of the operation of the wiring WL, the wiring WX1L, and the wiring MP. 18 to 19 show the fluctuations in the potentials of the wiring X2L, the node n1, and the node n1r. In FIG. 20, "high" indicates a high level potential, and "low" indicates a low level potential. In this example of operation, the line OL is connected to the node outa (or the node outa The amount of current output from wiring OL is I OL In addition, the wiring OLB to node o The amount of current output to utb (or from node outb to wiring OLB) is I OLB year In the timing charts shown in Figures 18 to 20, I OL , I OLB The change in Illustrated.

[0288] In this operation example, the wiring VE, the wiring VEm, the wiring VEr, and the wiring VEmr give The constant voltage is VSS (low level potential). In this case, in FIG. 8, the wiring VSO is connected to a high level. A bell potential is applied, and the potential is transferred from the wiring VSO through the switching circuit TW and the wiring OL to the wiring VE or Similarly, current flows from the wiring VSO to the switching circuit TW and the wiring V A current flows through the line OLB to the wiring VE or the wiring VEr.

[0289] In this operation example, the potential applied by the wiring VCN is VSS in FIG. By bringing CN into a conductive state and the second terminal of the transistor M1 into a conductive state, the transistor VSS is applied to the second terminal of M1. As will be described later in detail, at this time, the transistor The potential of the gate of M1 also becomes VSS, so that the transistor M1 is turned off. By bringing the line VCN and the second terminal of the transistor M1r into a conductive state, The potential of the second terminal and gate of the transistor M1r is VSS, so the transistor M1r is in the ON state. It becomes a non-operational state.

[0290] In the circuit MP shown in FIG. 15A, the transistor M2 and the transistor M3 are turned on. In this state, the transistor M1 is in a diode-connected configuration. When current flows through the circuit MC, the second terminal of the transistor M1 and the gate of the transistor M1 The potentials of and are approximately equal. It is determined by the flow rate and the potential of the first terminal of the transistor M1 (here, VSS). Here, the potential of the gate of the transistor M1 is held in the capacitor C1, and then the transistor M By turning off transistor M1, the voltage at the gate of transistor M1 is Therefore, the current characteristics of the transistor M1 The influence of variations can be reduced.

[0291] For example, when the transistors M2 and M3 are in an on state, the line OL is connected to the circuit M When the current I1 flows through the wiring VE via C, the gate of the transistor M1 (node n 1) The potential of V1 is set to V2. Therefore, V1 is held by the holding unit HC. The potential VSS of the first terminal of the transistor M1 and the potential V1 of the gate of the transistor M1 correspond to A current I1 can flow between the source and drain of the transistor M1. In the above, such an operation is described as "transistor M1 is a source-drain The amount of current flowing between the transistors is set to I1, and the transistor M1 is This is referred to as "the amount of current flowing between the source and drain is programmed to I1."

[0292] In this operation example, the amount of current flowing from the wiring OL to the circuit MC is set to three levels: 0, I1, and I2. Therefore, the amount of current set to the transistor M1 is 0, I1, and I2. For example, if the potential of the gate of the transistor M1 held in the holding unit HC is VSS, Since the potentials of the first and second terminals of the transistor M1 are also VSS, If the threshold voltage of transistor M1 is higher than 0, transistor M1 is in an off state. Therefore, no current flows between the source and drain of transistor M1. It can be said that the amount of current flowing between the source and drain of 1 is set to 0. For example, if the potential of the gate of the transistor M1 held in the holding unit HC is V1, When the threshold voltage of transistor M1 is lower than V1-VSS, M1 is turned on. At this time, the amount of current flowing through the transistor M1 is I1. Therefore, when the potential of the gate of transistor M1 is V1, the source of transistor M1 is It can be said that the amount of current flowing between the drains is set to I1. When the potential of the gate of the transistor M1 held in the holding unit HC is V2, If the threshold voltage of transistor M1 is lower than V2-VSS, transistor M1 is on. At this time, the amount of current flowing through the transistor M1 is I2. When the gate potential of the transistor M1 is V2, the source-drain It can be said that the amount of current flowing through is set to I2.

[0293] The current amount I1 is greater than 0 and less than I2. The threshold voltage of transistor M1 is set to be higher than VSS and lower than V2. The value voltage is higher than 0 and lower than V1-VSS. In the explanation of Figure 8, I generated by the constant current source circuit ISC1 ut can be replaced with In addition, I2 is, for example, 2I generated by the constant current source circuit ISC2 in the description of FIG. ut can be replaced with

[0294] Before explaining the operation example, the first data (for example, weight The coefficient is defined as follows: VSS is set to node n1 of the holding unit HC, and the holding unit HCr When VSS is held at node n1r, circuit MP uses the first data (weighting coefficient) The node n1 of the holding unit HC holds V1, and the node n2 of the holding unit HCr holds V2. When VSS is held in the node n1r, the circuit MP uses " +1” is stored in node n1 of the storage unit HC. When VSS is held in node n1r, circuit MP uses "+" as the first data (weighting coefficient). 2” is held at node n1 of the holding unit HC and VSS at node n2 of the holding unit HCr. When V1 is held in node n1r, circuit MP sets "-1" as the first data (weighting coefficient). " is held at node n1 of the holding unit HC, VSS is held at node n2 of the holding unit HCr, and When V2 is held in n1r, the circuit MP uses "-2" as the first data (weighting coefficient). It is assumed that the following is held:

[0295] Also, the second data input to the circuit MP (for example, the value of the neuron signal (operation ) is defined as follows as an example: high level potential is applied to the wiring WX1L, When a low-level potential is applied to X2L, the circuit MP receives the second data (neuron A low-level potential is input to the wire WX1L, and a low-level potential is input to the wire X2L. When a high level potential is applied to the circuit MP, the second data (the signal The value "-1" is input. The low level potential is input to the wire WX1L, and the low level potential is input to the wire X2L. When the Bell potential is applied, the circuit MP receives the second data (the value of the neuron's signal) and As an example, the high level potential is VD D, or a potential 10% or more, or 20% or more higher than VDD. .

[0296] In this specification and the like, the transistor M1 and the transistor M1r are not particularly limited. When there is no leakage, the ON state includes the case where the device finally operates in the saturation region. That is, the gate voltage, source voltage, and drain voltage of each of the above-mentioned transistors This includes when the voltage is properly biased to a voltage within the range in which the device operates in the saturated region. However, one embodiment of the present invention is not limited to this. To achieve this, the transistors M1 and M1r may operate in the linear region. In addition, when the first data (weighting coefficient) is an analog value, the first data (weighting coefficient) For example, the transistors M1 and M1r operate in the linear region depending on the magnitude of The case where the output voltage is in the saturated region may be mixed with the case where the output voltage is in the saturated region.

[0297] In this specification and the like, the transistor M2, the transistor M2r, the transistor M3, transistor M3r, transistor M4, and transistor M4r are If there is no such condition, the on-state includes the case where the device ultimately operates in the linear region. That is, the gate voltage, source voltage, and drain voltage of each of the above-mentioned transistors are , including when properly biased to a voltage in the range in which it operates in its linear region. However, one embodiment of the present invention is not limited to this. M2r, transistor M3, transistor M3r, transistor M4, and transistor The transistor M4r may operate in the saturation region when it is on, or may operate in the linear region. The case where the output voltage is in the saturation region and the case where the output voltage is in the saturation region may be mixed.

[0298] In the following, the first data (for example, a weighting coefficient) and the second data (for example, For example, in the following, we will consider the combination of values that each neuron signal (operation value) can take. An example of the operation of the circuit MP will be explained for each combination.

[0299] [Condition 1] First, as an example, the first data (weighting coefficient) is "0" and is input to the circuit MP. Let us consider the case where the second data (the neuron signal value (calculated value)) is “+1.” 8A is a timing chart of the circuit MP in this case.

[0300] Between time T1 and time T2, the holding unit HC and the holding unit HCr have the initial potential In FIG. 18A, for example, the node n1 and the node n1r are held at the initial potential It is assumed that a potential higher than the potential VSS is maintained.

[0301] A low level potential is applied to the wiring WL, wiring WX1L, and wiring X2L. As a result, transistor M2, transistor M2r, transistor M3, and transistor The gates of M3r, M4, and M4r are connected to a low level Since a potential is input, transistors M2, M2r, M3, and The transistor M3r, the transistor M4, and the transistor M4r are each in an off state. become.

[0302] Between time T2 and time T3, a high-level voltage is applied to the wiring WL and the wiring WX1L. This causes the transistors M2, M2r, and M 3. A high-level potential is input to each gate of the transistor M3r. The transistors M2, M2r, M3, and M3r Each of them is in the ON state.

[0303] Although not shown in FIG. 18A, the wiring OL and the wiring OLB each have an initial V as the initial potential ini is applied to the transistor M2, the transistor M2r, and the transistor Since the transistor M3 and the transistor M3r are both in the ON state, the holding section H The potentials of the node n1 of C and the node n1r of the holding unit HCr are V ini This becomes: That is, between time T2 and time T3, node n1 of the holding unit HC and node n2 of the holding unit HC The potentials of the nodes n1r of the node n1 and the node nr of the node n2 are initialized.

[0304] In addition, the initialization potential V ini For example, it is preferable to set the potential to the ground. Initialization potential V ini For example, VSS, a potential higher than ground potential, or Alternatively, the initial potentials applied to the wirings OL and OLB may be low. V ini The potentials of the wirings OL and OLB may be different from each other. Initialize potential V ini It is not necessary to input the time from time T2 to time T3. Alternatively, it is not necessary to provide a period between time T2 and time T3. Therefore, initialization may not be necessary.

[0305] Between time T3 and time T4, the potential VSS is input from the wiring OL to the circuit MC. The potential VSS is input from the wiring OLB to the circuit MCr. Switch SWL and switch SWLB are turned on, and switches SWI and SWIB are turned on. , switch SWO, switch SWOB, switch SWH, and switch SWHB are in the OFF state. This is done by setting the potential of the node n1 of the holding unit HC to VSS As a result, the potential of the node n1r of the holding unit HCr becomes VSS. In this case, the transistor M1 is set to pass 0 current, so the No current flows through the wiring VE via the circuit MC. Since 1r is set to flow 0 as the current amount, from wiring OLB through circuit MCr In other words, no current flows through the wiring VEr between time T3 and time T4. Since the transistor M1 and the transistor M1r are in the off state, is in a non-conductive state, and there is a non-conductive state between the wiring OLB and the wiring VEr.

[0306] Between time T4 and time T5, a low-level voltage is applied to the wiring WL and the wiring WX1L. This causes the transistors M2, M2r, and M 3. A low-level potential is input to each gate of the transistor M3r. Transistor M2, transistor M2r, transistor M3, and transistor M3r, respectively. When the transistors M2 and M2r are turned off, , the potential VSS of the node n1 of the holding unit HC is held, and the potential VSS of the node n1r of the holding unit HCr is held. VSS is maintained. In addition, when the transistor M3 is turned off, the line OL Therefore, no current flows through the circuit MC to the wiring VE. Similarly, when the transistor M3 When r is turned off, a current flows from the wiring OLB to the wiring VEr via the circuit MCr. Between time T4 and time T5, the switch shown in FIG. Switches SWH and SWHB are turned on, and the potential of wiring OL and wiring OLB is initially set to By initializing the potentials of the wiring OL and the wiring OLB, From 5 onwards, the current output from the circuit MP will cause the voltages of the wiring OL and wiring OLB to The position can be changed.

[0307] By the operation from time T1 to time T5, the first data (weighting coefficient) of the circuit MP is After the first data (weighting coefficient) is set in the circuit MP, the In this case, switch SWI, switch SWIB, switch SWO, switch SWOB, The switches SWL and SWLB may be turned off. After the number is set, turn on the switches SWH and SWHB and connect the wiring O The potentials of the wirings OL and OLB may be initialized. After the initialization, the switches SWH and SWHB may be turned off.

[0308] After time T5, the neuron signal (operation value) “+1” is input to the circuit MP. A high-level potential is input to the wiring WX1L, and a low-level potential is input to the wiring X2L. A high-level potential is input to the gates of the transistors M3 and M3r. A low level potential is input to the gates of the transistors M4 and M4r. Therefore, the transistors M3 and M3r are turned on. As a result, the transistors M4 and M4r are both turned off. This operation reduces the power dissipation between the circuit MC and the wiring OL, and between the circuit MCr and the wiring OLB. The connection between the circuit MC and the wiring OLB and the connection between the circuit MCr and the wiring OL are established. becomes non-conductive.

[0309] At this time, in FIG. 8, the switches SWO and SWOB are turned on, and the switch SWI , switch SWIB, switch SWL, switch SWLB, switch SWH, and switch With the switch SWHB in the off state, the lines OL and OLB are connected to the circuit AFP. Since the transistor M1 is in the off state (the amount of current is 0 is set to flow), in the circuit MC, No current flows from the line to the wiring VE. Similarly, the transistor M1r is in the off state. Since the current is set to 0, the wiring No current flows between the line OL and the wiring OLB to the wiring VEr. The current I output from node outa of OL , and output from node outb of wiring OLB The current I OLB does not change before and after time T5. There is a current I between OL does not flow, and the current I OLB teeth It doesn't flow.

[0310] By the way, this condition is that the first data (weighting coefficient) is set to "0" and the first data input to the circuit MP is Since the 2nd data (neuron signal value (calculated value)) is set to "+1", equation (1.1) Using this, the product of the first data (weight coefficient) and the second data (neuron signal value) is 0”. The product of the first data (weight coefficient) and the second data (neuron signal value) is “0 " As a result, in the operation of the circuit MP, the current I OL and current I OL B This corresponds to the case where the first data (weighting coefficient) and the second data do not change. The result of the product of (the value of the neuron's signal) being "0" is that the signal from the circuit AFP is No.z j (k) is output as

[0311] Once the first data (for example, weighting coefficients) is input, the value is not updated. By changing only the second data (such as the neuron signal value or the calculation value), In this case, the first data (weighting coefficient) may not be updated. Therefore, power consumption can be reduced. In order to reduce this, it is necessary to store the first data (weighting coefficient) for a long period of time. For example, when an OS transistor is used, the off-state current is low, and therefore the first data ( It is possible to retain the weighting coefficient for a long period of time.

[0312] [Condition 2] Next, as an example, the first data (weighting coefficient) is "+1" and is input to the circuit MP. Let us consider the case where the second data (the neuron signal value (calculated value)) is “+1.” 8B is a timing chart of the circuit MP in this case.

[0313] Regarding the operation from time T1 to time T3, from time T1 to time T3 under condition 1 Since the operation is the same as that between time T1 and time T3 in Condition 1, please refer to the explanation of the operation between time T1 and time T3 in Condition 1. To pour drinks.

[0314] Between time T3 and time T4, the current I1 flows from the wiring OL to the circuit MC. The potential VSS is input to the circuit MCr from the wiring OLB. , switch SWI, and switch SWLB are turned on, and switch SWIB, switch SWO, switch SWOB, switch SWLB, switch SWH, and switch SWHB This is done by turning off the node n1 of the holding unit HC. becomes V1, and the potential of the node n1r of the holding unit HCr becomes VSS. At C, the transistor M1 is set to pass a current of I1, so the wiring O A current I1 flows from L to the wiring VE via the circuit MC. Therefore, the transistor M1r is set to flow 0 current, so that the current from the wiring OLB No current flows through the circuit MCr to the wiring VEr.

[0315] Between time T4 and time T5, a low-level voltage is applied to the wiring WL and the wiring WX1L. This causes the transistors M2, M2r, and M Since a low-level potential is input to the gates of transistors M3 and M3r, The transistors M2, M2r, M3, and M3r The transistors M2 and M2r are turned off. As a result, the potential V1 of the node n1 of the holding unit HC is held, and the potential V2 of the node n The potential VSS of the transistor M1 is maintained. Then, no current flows from the wiring OL to the wiring VE via the circuit MC. When the resistor M3r is turned off, the line V The current does not flow through Er. Note that, between time T4 and time T5, the Switches SWH and SWHB are turned on, and the voltages of wires OL and OLB are turned on. By initializing the potentials of the wirings OL and OLB, After T5, the current output from the circuit MP causes the wiring OL and wiring OLB The potential can be changed.

[0316] By the operation from time T1 to time T5, the first data (weighting coefficient) of the circuit MP is After the first data (weighting coefficient) is set in the circuit MP, 8, switch SWI, switch SWIB, switch SWO, switch SWOB, The switches SWL and SWLB may be turned off. After the weighting coefficient is set, the switches SWH and SWHB are turned on. The potentials of the wirings OL and OLB may be initialized. After initializing the potential, the switches SWH and SWHB may be turned off. stomach.

[0317] After time T5, the second data (neuron signal value (calculated value)) to the circuit MP As the "+1" input, high level potential is input to wire WX1L and low level potential is input to wire X2L. At this time, a high voltage is applied to the gates of the transistors M3 and M3r. A level potential is input to the gates of the transistors M4 and M4r. Therefore, the low-level potential is input to the transistors M3 and M3r. Each of the transistors M4 and M4r is turned on, and each of the transistors M4 and M4r is turned off. In other words, this operation causes a disconnection between the circuit MC and the wiring OL, and between the circuit MC The state between r and the wiring OLB is conductive, and the state between the circuit MC and the wiring OLB and the circuit MC There is no conduction between r and the wiring OL.

[0318] At this time, in FIG. 8, the switches SWO and SWOB are turned on. Switch SWI, Switch SWIB, Switch SWL, Switch SWLB, Switch SWH , and the switch SWHB is turned off, and the wiring OL and the wiring OLB are connected to the circuit AFP is connected to the circuit MC. In the circuit MC, the transistor M3 is turned on. Since the transistor M1r is in the ON state (current I1 flows), (Because it is set as shown in Fig. 1), current flows from the wiring OL to the wiring VE. In the circuit MC, the transistor M4 is in the off state, so the line V No current flows between E and E. Meanwhile, in the circuit MCr, the transistor M3r is in the ON state. However, since transistor M1 is in the off state (current amount is 0), Therefore, no current flows from the wiring OLB to the wiring VEr. In addition, in the circuit MCr, the transistor M4r is in the off state, so that the wiring OL No current flows from node outa of wiring OL to wiring VEr. Input current I OL After time T5, I1 increases and the current flows from node outb of wiring OLB. The current I OLB does not change before and after time T5. Between the wire OL, a current I of magnitude I1 flows. OL flows, and between the circuit AFP and the wiring OLB is the current I OLB does not flow.

[0319] By the way, this condition is that the first data (weighting coefficient) is set to "+1" and input to the circuit MP. Since the second data (the value of the neuron's signal) is set to "+1", we use equation (1.1) The product of the first data (weight coefficient) and the second data (neuron signal value) is "+1". The product of the first data (weighting coefficient) and the second data (neuron signal value) is "+1". As a result, in the operation of the circuit MP, the current I OL I1 increases, and the current I OLB This corresponds to the case where the first data (weighting coefficient) and the second data (non-weighting coefficient) do not change. The result of the product of the signal from the AFP circuit is "+1". z j (k) is output as

[0320] In addition, during the period from time T3 to time T4 under this condition, for example, By setting the current flowing through C to I2 instead of I1, V2 can be held in the holding section HC. As a result, "+2" is set as the first data (weighting coefficient) of the circuit MP. The first data (weighting coefficient) is set to "+2", and the neuron signal input to the circuit MP is set to "+ 1”, the first data (weighting coefficient) and the second data (numeric The product of the first data (weighting coefficient) and the second data (non-linear signal value) is "+2". The result of the product of the signal values of the two neurons being "+2" is that, in the operation of the circuit MP, after time T5 In the current I OL increases, and the current I OLB This corresponds to the case where the value of In the circuit MCr, VSS is held in the holding unit HCr, and the amount of current I By setting a value other than 1, a positive value other than "+1" can be used as the first data (weighting coefficient) of the circuit MP. The value can be set.

[0321] [Condition 3] Next, as an example, the first data (weighting coefficient) w is "-1" and is input to the circuit MP. Let us consider the case where the second data (the value of the neuron signal (calculated value)) is "+1." 18C is a timing chart of the circuit MP in this case.

[0322] Regarding the operation from time T1 to time T3, from time T1 to time T3 under condition 1 Since the operation is the same as that between time T1 and time T3 in Condition 1, please refer to the explanation of the operation between time T1 and time T3 in Condition 1. To pour drinks.

[0323] Between time T3 and time T4, the potential VSS is input from the wiring OL to the circuit MC. Then, the current I1 is input from the wiring OLB to the circuit MCr. , switch SWIB, and switch SWL are turned on, and switch SWI, switch S WO, switch SWOB, switch SWLB, switch SWH, and switch SWHB This is done by turning it off. As a result, the potential of the node n1 of the holding unit HC becomes VSS, and the potential of the node n1r of the holding unit HCr becomes V1. At r, the transistor M1 is set to pass 0 current, so the wiring OL No current flows from the transistor to the wiring VE via the circuit MC. Since the current flowing through the M1r is set to I1, the line from the OLB to the circuit MCr A current I1 flows through the wiring VEr.

[0324] Between time T4 and time T5, a low-level voltage is applied to the wiring WL and the wiring WX1L. This causes the transistors M2, M2r, and M Since a low-level potential is input to the gates of transistors M3 and M3r, The transistors M2, M2r, M3, and M3r The transistors M2 and M2r are turned off. As a result, the potential VSS of the node n1 of the holding unit HC is held, and the potential VSS of the node n2 of the holding unit HCr is held. The potential V1 of n1r is maintained. Also, when the transistor M3 is turned off, Then, no current flows from the wiring OL to the wiring VE via the circuit MC. When the resistor M3r is turned off, the line V The current does not flow through Er. Note that, between time T4 and time T5, the Turn on the switches SWH and SWHB to turn on the wiring OL and wiring OLB. The potentials of the wirings OL and OLB may be initialized. After time T5, the current output from the circuit MP flows through the wiring OL and The potential of the wiring OLB can be changed.

[0325] By the operation from time T1 to time T5, the first data (weighting coefficient) of the circuit MP is After the first data (weighting coefficient) is set in the circuit MP, 8, switch SWI, switch SWIB, switch SWO, switch SWOB, The switches SWL and SWLB may be turned off. After the data (weighting coefficient) is set, switch SWH and switch SWHB are turned on. In this state, the potentials of the wirings OL and OLB may be initialized. After initializing the potential of LB, the switches SWH and SWHB are set to the off state. Good too.

[0326] After time T5, the second data (neuron signal value (calculated value)) to the circuit MP As the "+1" input, high level potential is input to wire WX1L and low level potential is input to wire X2L. At this time, a high voltage is applied to the gates of the transistors M3 and M3r. A level potential is input to the gates of the transistors M4 and M4r. Therefore, the low-level potential is input to the transistors M3 and M3r. Each of the transistors M4 and M4r is turned on, and each of the transistors M4 and M4r is turned off. In other words, this operation causes a disconnection between the circuit MC and the wiring OL, and between the circuit MC The state between r and the wiring OLB is conductive, and the state between the circuit MC and the wiring OLB and the circuit MC There is no conduction between r and the wiring OL.

[0327] At this time, in FIG. 8, the switches SWO and SWOB are turned on. Switch SWI, Switch SWIB, Switch SWL, Switch SWLB, Switch SWH , and the switch SWHB is turned off, and the wiring OL and the wiring OLB are connected to the circuit AFP is connected to the circuit MC. In the circuit MC, the transistor M3 is turned on. However, since the transistor M1 is in the off state (the current is set to 0), Since the current is set to 0V, no current flows between the wiring OL and the wiring VE. At C, transistor M4 is in the off state, so there is no current from wiring OLB to wiring VE. On the other hand, in the circuit MCr, the transistor M3r is in the ON state. Since the transistor M1r is in the ON state (current I1 is (Because the resistor is set to allow current to flow), current flows from the wiring OLB to the wiring VEr. In addition, in the circuit MCr, the transistor M4r is in the off state, so that the wiring OL No current flows from node outa of wiring OL to wiring VEr. Input current I OL does not change before and after time T5, and the output from node outb of wiring OLB Input current I OLB I1 increases after time T5. Therefore, the circuit AFP and the Between the wire OL, there is a current I OL does not flow, and the current amount I 1 current I OLB is playing.

[0328] By the way, this condition is that the first data (weighting coefficient) is set to "-1" and input to the circuit MP. Since the second data (neuron signal value (calculated value)) is set to "+1", the formula (1.1 ), the product of the first data (weight coefficient) and the second data (neuron signal value) is The product of the first data (weighting coefficient) and the second data (neuron signal value) is The result of "-1" is that in the operation of the circuit MP, the current I OL Changes First, the current I OLB corresponds to the case where I1 increases. Note that the first data (weighting coefficient) and the second The result of the product of the data (neuron signal value) being "-1" is shown in Figure 8 by circuit AF P to signal z j (k) is output as

[0329] In addition, during the period from time T3 to time T4 under this condition, for example, By setting the current flowing through MCr to I2 instead of I1, V2 is held in the holding part HCr. As a result, "-2" is set as the first data (weighting coefficient) of the circuit MP. The first data (weighting coefficient) is set to "-2", and the second data (numeric) input to the circuit MP is By setting the value of the signal of the conductor) to "+1", the first data (weight The product of the first data (coefficient) and the second data (value of the neuron signal) is "-2". The result of the product of the second data (neuron signal value) and the second data (neuron signal value) being "-2" is the circuit MP In this operation, the current I OL does not change, and the current I OLB increases by I2 In this way, in the circuit MC, VSS is held in the holding unit HC, and By setting a current amount other than I1 in MCr, the weighting coefficient of the circuit MP is set to "+ Any positive value other than 1 can be set.

[0330] [Condition 4] In this condition, for example, the first data (weighting coefficient) is set to "0" and the input to the circuit MP is The behavior of the circuit MP when the second data (value of the neuron signal (calculated value)) is set to "-1" Fig. 19A is a timing chart of the circuit MP in this case.

[0331] Regarding the operation from time T1 to time T5, from time T1 to time T5 under condition 1 Since the operation is the same as that between time T1 and time T5 in Condition 1, please refer to the explanation of the operation between time T1 and time T5 in Condition 1. To pour drinks.

[0332] After time T5, the second data (neuron signal value (calculated value)) to the circuit MP As the "-1" input, a low level potential is input to the wire WX1L and a high level potential is input to the wire X2L. At this time, a low voltage is applied to the gates of the transistors M3 and M3r. A level potential is input to the gates of the transistors M4 and M4r. Therefore, the transistors M3 and M3r Each of the transistors M4 and M4r is turned off. In other words, this operation causes a current between the circuit MC and the wiring OL, and between the circuit MC The circuit MC and the wiring OLB are in a non-conductive state, and the circuit MC and the wiring OLB are in a non-conductive state. Conduction is established between Cr and the wiring OL.

[0333] At this time, in FIG. 8, the switches SWO and SWOB are turned on. Switch SWI, switch SWIB, switch SWL, and switch SWLB are in the OFF state. This brings the wiring OL and the wiring OLB into electrical continuity with the circuit AFP. Since the transistor M1 is in the off state (the amount of current is set to 0), In the circuit MC, there is a current between the wiring OL and the wiring OLB to the wiring VE. In other words, the current I output from the node outa of the wiring OL OL , and wiring The current I output from node outb of the OLB OLB does not change before and after time T5. Similarly, since the transistor M1r is in the off state (so that the current is 0), In the circuit MCr, wiring OL and wiring OLB are connected to wiring V In other words, the current I output from node outa of wiring OL O L , and the current I output from node outb of wiring OLB OLB Also, around time T5 Therefore, the current I OL does not flow and the circuit A current I flows between AFP and wiring OLB. OLB does not flow.

[0334] By the way, this condition is that the first data (weighting coefficient) is set to "0" and the first data input to the circuit MP is Since the 2 data (neuron signal value (calculated value)) is set to "-1", equation (1.1) Using this, the product of the first data (weight coefficient) and the second data (neuron signal value) is 0”. The product of the first data (weight coefficient) and the second data (neuron signal value) is “0 " As a result, in the operation of the circuit MP, the current I OL and current I OL B This corresponds to the case where none of the above changes, which is consistent with the circuit operation results for condition 1. The product of the first data (weighting coefficient) and the second data (neuron signal value) is "0". As in condition 1, the result is that in Fig. 8, the signal z j (k) is output as do.

[0335] [Condition 5] In this condition, for example, the first data (weighting coefficient) is set to "+1" and input to the circuit MP. The second data (value of the neuron signal (calculated value)) to be calculated is "-1". Fig. 19B is a timing chart of the circuit MP in this case.

[0336] Regarding the operation from time T1 to time T5, from time T1 to time T5 under condition 2 Therefore, please refer to the explanation of the operation from time T1 to time T5 in Condition 2. To pour drinks.

[0337] After time T5, the second data (neuron signal value (calculated value)) to the circuit MP As the "-1" input, a low level potential is input to the wire WX1L and a high level potential is input to the wire X2L. At this time, a low voltage is applied to the gates of the transistors M3 and M3r. A level potential is input to the gates of the transistors M4 and M4r. Therefore, the transistors M3 and M3r Each of the transistors M4 and M4r is turned off. In other words, this operation causes a current between the circuit MC and the wiring OL, and between the circuit MC The circuit MC and the wiring OLB are in a non-conductive state, and the circuit MC and the wiring OLB are in a non-conductive state. Conduction is established between Cr and the wiring OL.

[0338] At this time, in FIG. 8, the switches SWO and SWOB are turned on. Switch SWI, Switch SWIB, Switch SWL, Switch SWLB, Switch SWH , and the switch SWHB is turned off, and the wiring OL and the wiring OLB are connected to the circuit AFP is connected to the MC circuit. In the MC circuit, the transistor M3 is turned off. Therefore, no current flows between the wiring OL and the wiring VE. , transistor M4 is in the ON state, and transistor M1r is in the ON state. Because the current is set to I1, the wiring is On the other hand, in the circuit MCr, the transistor M3r is in the off state. Since the wiring is in the ON state, no current flows between the wiring OLB and the wiring VEr. In MCr, the transistor M4r is in the on state, and the transistor M1 is in the off state (set to pass 0 current), No current flows from OL to the wiring VEr. The current I OL does not change before and after time T5, and the The current I OLB increases after time T5. Therefore, the AFP circuit Between the wire OL and the wire OL does not flow, and there is no current between the circuit AFP and the wiring OLB. Current I of quantity I1 OLB is playing.

[0339] By the way, this condition is that the first data (weighting coefficient) is set to "+1" and input to the circuit MP. Since the second data (neuron signal value (calculated value)) is set to "-1", the formula (1.1 ), the product of the first data (weight coefficient) and the second data (neuron signal value) is The product of the first data (weighting coefficient) and the second data (neuron signal value) is The result of "-1" is that in the operation of the circuit MP, the current I OL Changes First, the current I OLB corresponds to the case where I1 increases, which is consistent with the circuit operation results for condition 3. Note that the product of the first data (weighting coefficient) and the second data (neuron signal value) is "-1 ” result, as in condition 3, in FIG. 8, the signal z j (k) as is output.

[0340] As described in Condition 2, for example, between time T3 and time T4 under this condition, For example, the current flowing from wiring OL to circuit MC is set to I2 instead of I1, and V is set to the holding part HC. 2. This allows "+2" to be stored as the first data (weighting coefficient) of the circuit MP. The first data (weighting coefficient) is set to "+2", and the neuron input to the circuit MP is By setting the signal to "-1", the first data (weighting coefficient) and the second data are calculated from equation (1.1). The product of the data (value of the neuron signal) is "-2". When the product of two data (neuron signal values) is "-2", the operation of the circuit MP is as follows: After time T5, the current I OL does not change, and the current I OLB corresponds to the case where I2 increases In this way, in the circuit MCr, VSS is held in the holding unit HCr, and in the circuit MC, By setting a current amount other than I1, a positive value other than "+1" can be set as the weighting coefficient of the circuit MP. can be set.

[0341] [Condition 6] In this condition, for example, the first data (weighting coefficient) is set to "-1" and input to the circuit MP. The second data (value of the neuron signal (calculated value)) to be calculated is "-1". Fig. 19C is a timing chart of the circuit MP in this case.

[0342] Regarding the operation from time T1 to time T5, condition 3, from time T1 to time T5 Therefore, please refer to the explanation of the operation from time T1 to time T5 in Condition 3. To pour drinks.

[0343] After time T5, the second data (neuron signal value (calculated value)) to the circuit MP As the "-1" input, a low level potential is input to the wire WX1L and a high level potential is input to the wire X2L. At this time, a low voltage is applied to the gates of the transistors M3 and M3r. A level potential is input to the gates of the transistors M4 and M4r. Therefore, the transistors M3 and M3r Each of the transistors M4 and M4r is turned off. In other words, this operation causes a current between the circuit MC and the wiring OL, and between the circuit MC The circuit MC and the wiring OLB are in a non-conductive state, and the circuit MC and the wiring OLB are in a non-conductive state. Conduction is established between Cr and the wiring OL.

[0344] At this time, in FIG. 8, the switches SWO and SWOB are turned on. Switch SWI, Switch SWIB, Switch SWL, Switch SWLB, Switch SWH , and the switch SWHB is turned off, and the wiring OL and the wiring OLB are connected to the circuit AFP is connected to the MC circuit. In the MC circuit, the transistor M3 is turned off. Therefore, no current flows between the wiring OL and the wiring VE. , transistor M4 is in the ON state, but transistor M1 is in the OFF state. (The current is set to 0.) On the other hand, in the circuit MCr, the transistor M3r is in the off state. Therefore, no current flows between the wiring OLB and the wiring VEr. At r, the transistor M4r is in the on state and the transistor M1 is on. Since the current is set to I1, the wiring is in OL state. From the above, current flows from node outa of wiring OL to the output The current I OL After time T5, I1 increases and the current flows from node outb of wiring OLB to Output current I OLB does not change before and after time T5. Therefore, the circuit AFP and the wiring Between OL and current IOL flows, and between the circuit AFP and the wiring OLB current I OLB does not flow.

[0345] By the way, this condition is that the first data (weighting coefficient) is set to "-1" and input to the circuit MP. Since the second data (neuron signal value (calculated value)) is set to "-1", the formula (1.1 ), the product of the first data (weight coefficient) and the second data (neuron signal value) is The product of the first data (weighting coefficient) and the second data (neuron signal value) is The result of "+1" is that in the operation of the circuit MP, the current I OL changes , current I OLB This corresponds to the case where there is no change, which is consistent with the circuit operation result for condition 2. The product of the first data (weighting coefficient) and the first data (neuron signal value) is "+1". As in condition 2, the result is that the signal z j (k) Output as will be done.

[0346] As described in Condition 3, for example, between time T3 and time T4 under this condition, For example, the current flowing from the wiring OLB to the circuit MCr is set to I2 instead of I1, and the holding section HC V2 may be stored in the circuit MP. The first data (weighting coefficient) is set to "-2", and the second data input to the circuit MP is set to "-2". By setting the first data (neuron signal value) to "-1", the first data is obtained from equation (1.1). The product of the first data (weighting coefficient) and the second data (neuron signal value) is "+2". The result of the product of the data (weight coefficient) and the second data (neuron signal value) being "+2" is In the operation of the circuit MP, after time T5, the current I OL does not change, and the current I OLB I In this way, in the circuit MC, VSS is held in the holding section HC. , and by setting a current amount other than I1 in the circuit MCr, the weight coefficient of the circuit MP is Any positive value other than "+1" can be set.

[0347] [Condition 7] In this condition, for example, the first data (weighting coefficient) is "0" and the input to the circuit MP is Condition 7 is when the second data (the neuron signal value (calculated value)) is "0". Consider the operation of the circuit MP in this case. It is a route.

[0348] Regarding the operation from time T1 to time T5, from time T1 to time T5 under condition 1 Since the operation is the same as that between time T1 and time T5 in Condition 1, please refer to the explanation of the operation between time T1 and time T5 in Condition 1. To pour drinks.

[0349] After time T5, the second data (neuron signal value (calculated value)) to the circuit MP As a "0" input, a low level potential is input to the wire WX1L and a low level potential is input to the wire X2L. At this time, the transistors M3, M3r, M4, and A low level potential is input to each gate of the transistor M4r. The transistors M3, M3r, M4, and M4r are In other words, this operation causes a disconnection between the circuit MC and the wiring OL, and between the circuit MCr and Between the wiring OLB, between the circuit MC and the wiring OLB, and between the circuit MCr and the wiring OL It becomes non-conductive.

[0350] Therefore, in the circuit MC, regardless of the amount of the set current flowing through the transistor M1, Therefore, no current flows from the wiring OL to either the wiring VE or the wiring VEr. In the circuit MCr, regardless of the amount of current that is set to flow through the transistor M1r, No current flows between the line OLB and the other of the wiring VE or wiring VEr. The current I output from node outa of OL OL , and from node outb of wiring OLB The current I OLB Each of these does not change before and after time T5.

[0351] At this time, in FIG. 8, the switches SWO and SWOB are turned on. Switch SWI, switch SWIB, switch SWL, switch SWLB, switch By turning off the switches SWH and SWHB, the wiring OL and wiring OLB Even if the connection between each of these and the circuit AFP is established, as described above, the connection between the circuit AFP and the wiring OL Between them, there is a current I OL does not flow, and the current I OLB The flow do not have.

[0352] By the way, this condition is that the first data (weighting coefficient) is set to "0" and the first data input to the circuit MP is Since the 2 data (neuron signal value (calculated value)) is set to "0", we change equation (1.1) to When using this function, the product of the first data (weight coefficient) and the second data (neuron signal value) is "0 " The product of the first data (weight coefficient) and the second data (neuron signal value) is "0" As a result, in the operation of the circuit MP, the current I OL and current I OLB This corresponds to the case where none of the above changes, which is consistent with the results of the circuit operation under conditions 1 and 4. Note that the product of the first data (weighting coefficient) and the second data (neuron signal value) is "0". As in conditions 1 and 4, the result is that the signal z j (k) is output as

[0353] [Condition 8] In this condition, for example, the first data (weighting coefficient) is "+1" and the input to the circuit MP is Condition 8 is when the second data (neuron signal value (calculated value)) is "0". Then, consider the operation of the circuit MP. FIG. 20B shows the timing chart of the circuit MP in this case. It is a chart.

[0354] Regarding the operation from time T1 to time T5, from time T1 to time T5 under condition 2 Therefore, please refer to the explanation of the operation from time T1 to time T5 in Condition 2. To pour drinks.

[0355] After time T5, the second data (neuron signal value (calculated value)) to the circuit MP As a "0" input, a low level potential is input to the wire WX1L and a low level potential is input to the wire X2L. At this time, the transistors M3, M3r, M4, and A low level potential is input to each gate of the transistor M4r. The transistors M3, M3r, M4, and M4r are In other words, as in condition 7, this operation causes the transistors M1 and Regardless of the amount of current flowing through each of the transistors M1r and M1r, the circuit MC and Between the circuit MCr and the wiring OLB, between the circuit MC and the wiring OLB, and between the circuit Therefore, the line OL is disconnected from the line VE or the line OL. No current flows between the wiring OLB and either the wiring VE or the wiring V Since current also flows to the other side, the current I output from node outa of wiring OL OL , and the current I output from node outb of wiring OLB OLB Each of these is There is no change before or after time T5.

[0356] At this time, in FIG. 8, the switches SWO and SWOB are turned on. and turns off switches SWI, SWIB, SWL, and SWLB. By setting the state, the wiring OL and the wiring OLB are in a conduction state with the circuit AFP. However, as mentioned above, the current I OL does not flow and the circuit A current I flows between AFP and wiring OLB. OLB does not flow.

[0357] By the way, this condition is that the first data (weighting coefficient) is set to "+1" and input to the circuit MP. Since the second data (the neuron signal value (calculated value)) is set to "0", equation (1.1) Using this, the product of the first data (weight coefficient) and the second data (neuron signal value) is 0”. The product of the first data (weight coefficient) and the second data (neuron signal value) is “0 " As a result, in the operation of the circuit MP, the current I OL and current I OL B This corresponds to the case where none of the above changes, and this is the result of the circuit operation under conditions 1, 4, and 7. The results are consistent with the first data (weighting coefficients) and the second data (neuron signal values). The result of the product being "0" is the same as in conditions 1, 4, and 7, as in the case of the circuit AFP in FIG. From signal z j (k) is output as

[0358] [Condition 9] In this condition, for example, the first data (weighting coefficient) is "-1" and the input to the circuit MP Condition 9 is when the second data (the neuron signal value (calculated value)) is "0". Consider the operation of the circuit MP in this case. It is a route.

[0359] Regarding the operation from time T1 to time T5, condition 3, from time T1 to time T5 Therefore, please refer to the explanation of the operation from time T1 to time T5 in Condition 3. To pour drinks.

[0360] After time T5, the second data (neuron signal value (calculated value)) to the circuit MP As a "0" input, a low level potential is input to the wire WX1L and a low level potential is input to the wire X2L. At this time, the transistors M3, M3r, M4, and A low level potential is input to each gate of the transistor M4r. The transistors M3, M3r, M4, and M4r are turned off. In other words, as in condition 7, this operation causes the transistor M1 and the transistor Regardless of the amount of current that flows through each of M1r, between circuit MC and wiring OL , between the circuit MCr and the wiring OLB, between the circuit MC and the wiring OLB, and between the circuit MCr and the wiring OLB. Therefore, the line OL is disconnected from the line VE or one of the lines VEr. No current flows between the wiring OLB and the other of the wiring VE or VEl. Since no current flows through the wiring OL, the current I OL , and The current I output from node outb of wiring OLB OLB Each of these is before and after time T5. does not change.

[0361] At this time, in FIG. 8, the switches SWO and SWOB are turned on. Switch SWI, switch SWIB, switch SWL, switch SWLB, switch By turning off the switches SWH and SWHB, the wiring OL and wiring OLB Even if the connection between each of these and the circuit AFP is established, as described above, the connection between the circuit AFP and the wiring OL Between them, there is a current I OL does not flow, and the current I OLB The flow do not have.

[0362] By the way, this condition is that the first data (weighting coefficient) is set to "-1" and input to the circuit MP. Since the second data (the neuron signal value (calculated value)) is set to "0", equation (1.1) Using this, the product of the first data (weight coefficient) and the second data (neuron signal value) is 0”. The product of the first data (weight coefficient) and the second data (neuron signal value) is “0 " As a result, in the operation of the circuit MP, the current I OL and current I OL B This corresponds to the case where each of the following conditions does not change: The result of the operation is consistent with the first data (weighting coefficient) and the second data (neuron signal The result of the product of (value of) is "0" is the same as in conditions 1, 4, 7, and 8, as shown in Figure 8. Then, the signal z from the circuit AFP j (k) is output as

[0363] The results of the operation example under the above conditions 1 to 9 are summarized in the table below. The high level potential is described as high, and the low level potential is described as low.

[0364] [Table 2]

[0365] Here, one circuit MC and one circuit MCr are connected to the wiring OL and wiring OLB, respectively. This is an example of a case where the As shown in FIG. 6, the wiring OL and the wiring OLB are connected to a plurality of circuits MC and MCr. When the circuits MC and MCr are connected in series, the current output from each circuit is Based on the current law of Friedrich, the sum is calculated as follows: In other words, the multiplication is performed in the circuits MC and MCr, and the multiple circuits M The sum is calculated by adding up the currents from C and MCr. The calculation processing is carried out.

[0366] By the way, in the operation of the circuit MP, the first data (weighting coefficient) is set to "+1" or "-1". The second data (neuron signal value) is limited to two values, "+1" and "-1". By performing the above calculation, the circuit MP operates in the same way as a circuit that performs the NOT of an exclusive OR (match circuit). This can be done.

[0367] In addition, in the operation of the circuit MP, the first data (weighting coefficient) is set to two values of "+1" and "0". The second data (neuron signal value) is calculated as only two values, "+1" and "0". By performing the above, the circuit MP can perform the same operation as a logical AND circuit.

[0368] In this example of operation, the holding units HC and HCr of the circuits MC and MCr of the circuit MP have The potential held is multi-valued, such as VSS, V1, V2, etc., but the holding parts HC, H Cr may hold a potential indicating a binary value or an analog value. For example, the first data (weight In the case of a "positive analog value" as the coefficient, a high level analog signal is output to node n1 of the holding unit HC. A low level potential is held at the node n1r of the log potential holding unit HCr. In the case of a "negative analog value" as a weighting coefficient, for example, a low value is applied to node n1 of the holding unit HC. A high level analog potential is held at the node n1r of the level potential holding unit HCr. And the current I OL and current I OLB The magnitude of the current is determined by the analog potential. In addition, the holding units HC and HCr hold the potentials that indicate analog values, as follows: This is not limited to the operation example of the circuit MP of FIG. 15A, but may also be applied to other circuits MP shown in this specification. It is also possible.

[0369] This configuration example can be appropriately combined with other configuration examples shown in this specification.

[0370] <Configuration example 2> Next, different from the circuit configurations of FIGS. 15A to 15C, 16A, and 16B, An example of a circuit configuration that can be applied to the circuit MP shown in FIG. 9B will be described.

[0371] The circuit MP shown in FIG. 21A shows a configuration example of the circuit MP of FIG. 9B, and is the same as the circuit MP of FIG. 15A. The difference with MP is that the second terminal of transistor M2 is connected to the third terminal of transistor M1 instead of the wiring OL. 2 terminal, the first terminal of the transistor M3, and the first terminal of the transistor M4. The point where the second terminal of the transistor M2r is connected is the transistor M2r, not the wiring OLB. the second terminal of transistor M1r, the first terminal of transistor M3r, and the first terminal of transistor M4r and a point electrically connected to and.

[0372] The circuit MP of FIG. 21A can operate similarly to the circuit MP of FIG. 15A.

[0373] 21A, and can be applied to the circuit MP shown in FIG. 9B. The circuit MP shown in FIG. 21B is a configuration example of the circuit MP shown in FIG. 9B. 15A. The difference from the circuit MP of FIG. 15A is that the circuit MC includes a transistor M1c and The first terminal of transistor M4 is connected to the second terminal of transistor M1 and the second terminal of transistor M3. The circuit MCr is electrically connected to the transistor M1c. 1cr, and the first terminal of the transistor M4r is connected to the second terminal of the transistor M1r. and the second terminal of the transistor M3r is electrically connected to the transistor M1cr, not the second terminal of the transistor M3r. This is the point.

[0374] In this specification and the like, the transistors M1c and M1cr are particularly Unless otherwise specified, the on-state includes the case where the device ultimately operates in the saturated region. That is, the gate voltage, source voltage, and drain voltage of each of the above-mentioned transistors are The input voltage includes the case where the device is properly biased to a voltage that operates in the linear region. However, one embodiment of the present invention is not limited to this. To reduce the load, the transistors M1c and M1cr operate in the linear region. It should be noted that the first data (for example, a weighting coefficient in this case) may be an analog value. In this case, depending on the magnitude of the first data (weighting coefficient), for example, the transistor M1c and The transistor M1cr operates in both the linear region and the saturation region. It may exist.

[0375] In the circuit MP of FIG. 21B, the first terminal of the transistor M1c is electrically connected to the wiring VE. The gate of the transistor M1c is connected to the gate of the transistor M1. The first terminal of the transistor M2 is electrically connected to the first terminal of the capacitor C1. In addition, the second terminal of the transistor M1c is electrically connected to the first terminal of the transistor M4. It is being done.

[0376] In the circuit MP of FIG. 21B, the circuit MCr has a circuit configuration similar to that of the circuit MC. Therefore, the circuit elements of the circuit MCr are To distinguish it from children, the symbol is prefixed with "r."

[0377] Also, the circuit MP in FIG. 21B and the circuit MP in FIG. 15A have the same connection configuration. The explanation of this will be omitted.

[0378] In the circuit MP of FIG. 21B, the current flowing through the transistor M3 and the transistor M4 are determined by the potentials of the gates of the transistors M1 and M1c, respectively. As an example, the size of the transistor M1 and the transistor M1c, e.g. For example, it is preferable that the channel length and the channel width are equal to each other. By doing so, it may be possible to achieve an efficient layout. It may be possible to make the current flowing through transistor M4 uniform.

[0379] The circuit MP of FIG. 21B can operate similarly to the circuit MP of FIG. 15A.

[0380] This configuration example can be appropriately combined with other configuration examples shown in this specification.

[0381] <Configuration example 3> Next, an example of a circuit configuration that can be applied to the circuit MP shown in FIG. 9E will be described.

[0382] The circuit MP shown in FIG. 22A shows a configuration example of the circuit MP of FIG. 9E, and is the same as the circuit MP of FIG. 15A. The difference with MP is that the circuit MC includes transistor M5, and the circuit MCr includes transistor The circuit MP is electrically connected to the wiring IL and the wiring ILB. This is the point.

[0383] In this specification and the like, the transistor M5 and the transistor M5r are not particularly limited. When there is no change, the on-state includes the case where the device ultimately operates in the linear region. That is, the gate voltage, source voltage, and drain voltage of each of the above-mentioned transistors This includes when the voltage is properly biased to a voltage within the range in which the device operates in the linear region. do.

[0384] In the circuit MP of FIG. 22A, the first terminal of transistor M5 is connected to the first terminal of transistor M2. The second terminal of the transistor M5 is electrically connected to the wiring IL. The second terminal of the transistor M1, the first terminal of the transistor M3, and the first terminal of the transistor M4 The gate of the transistor M5 is electrically connected to the wiring WL. is connected.

[0385] In the circuit MP of FIG. 22A, the circuit MCr has almost the same circuit configuration as the circuit MC. Therefore, the circuit elements of the circuit MCr are To distinguish it from children, the symbol is prefixed with "r."

[0386] Also, the circuit MP in FIG. 22A and the circuit MP in FIG. 15A have the same connection configuration. The explanation of this will be omitted.

[0387] In the circuit MP of FIG. 22A, similarly to the configuration examples 1 and 2, the transistor M1, the The sizes of the transistors M2, M3, and M4, e.g., the channel lengths and channel widths of the transistors M1r, M2r, and M It is preferable that the sizes of the transistors M3r and M4r are equal to each other. In addition, the layout of transistor M5 may be more efficient. The size is preferably equal to that of transistor M5r.

[0388] When setting the current in the circuits MC and MCr, a high-level potential is applied to the wiring WL. The transistor M2, the transistor M2r, the transistor M5, and the transistor M5r are turned on. After setting the currents in the circuits MC and MCr, In order to maintain the potential set in the holding section HC and the holding section HCr, a low-level voltage is applied to the wiring WL. By giving a voltage, the transistor M2, the transistor M2r, the transistor M5, and the transistor Just turn off StaM5r.

[0389] In the circuit MP described in the configuration examples 1 and 2, the second data (for example, The wiring for transmitting the first data (for example, the weight coefficient and Wiring for supplying or holding information (for example, voltage, current, etc.) corresponding to the By configuring the circuit MP in Figure 22, the second data The wire that transmits the data (the signal value of the neuron) is wire X1L, and the first data is sent to the circuit MP. Wiring for supplying or holding information (e.g., voltage, current, etc.) according to (weighting coefficient) In other words, the circuit MP in FIG. 22 is the same as the circuits in the configuration examples 1 and 2. It can be said that the wiring WX1L of the circuit MP is divided by function.

[0390] FIG. 22B shows a circuit configuration different from the circuit MP of FIG. 22A.

[0391] The circuit MP shown in FIG. 22B is a circuit similar to the circuit MP shown in FIG. 22A except for transistor M5 and transistor The electrical connection of each first terminal of the M5r is changed. In the circuit MP of FIG. 22B, the first terminal of the transistor M5 is connected to the first terminal of the transistor M2. a first terminal electrically connected to the gate of the transistor M1 and the first terminal of the capacitor C1; There are.

[0392] By configuring the circuit MP shown in FIG. 22B, the circuit MP of FIG. 22B can be realized by It operates almost identically to the circuit MP.

[0393] In the circuits MP shown in FIGS. 22A and 22B, the wiring IL is connected to the wiring OL. For example, in FIG. 22A, In the circuit MP shown in FIG. 1, the wiring IL is combined into the wiring OL, and the wiring ILB is combined into the wiring OLB. By fixing the circuit, the circuit MP shown in FIG. 23A can be configured. In the circuit MP shown in FIG. 22B, the wiring IL is integrated into the wiring OL, and the wiring ILB is arranged By combining them into a line OLB, the configuration of the circuit MP shown in FIG. 23B can be achieved. The circuits MP in FIGS. 23A and 23B are adapted to the circuit MP shown in FIG. 9A. The operation of each circuit MP in FIG. 23A and FIG. 23B is the same as that in FIG. Please refer to the explanation of the operation of circuit MP in 5A.

[0394] This configuration example can be appropriately combined with other configuration examples shown in this specification.

[0395] <Configuration Example 4> The circuit MP shown in FIG. 24 differs from the circuit MP shown in FIG. 15A in that it includes a holding unit HC and a holding unit HC This is an example of a circuit that has not only a holding unit HCs but also a holding unit HCsr.

[0396] The circuit MC included in the circuit MP of FIG. 24 has the same circuit elements as the circuit MP of FIG. 21A. In addition, transistor M1s, transistor M2s, transistor M6, transistor M6 s and a capacitance C1s. The circuit MCr included in the circuit MP of FIG. Since the circuit MC has the same circuit elements as the transistors M1s and M 2s, transistor M6, transistor M6s, and capacitor C1s, Transistor M1sr, transistor M2sr, transistor M6r, transistor M6 The transistor M2s and the capacitance C1sr are protected The holding unit HCs includes a transistor M2sr and a capacitor C1sr. It is being eaten.

[0397] In this specification, the transistors M2s, M6, and Unless otherwise specified, M6s, transistor M6r, and transistor M6sr are in the on state. The case of the state includes the case where it finally operates in the linear region. The gate voltage, source voltage, and drain voltage of each transistor are set to operate in the linear region. This includes when the device is properly biased to a voltage in the range specified.

[0398] Next, the configuration of the circuit MP in Fig. 24 will be described. In the circuit MP in Fig. 24, Portions having the same configuration as the circuit MP in FIG. 21A are omitted.

[0399] In the circuit MP of FIG. 24, the second terminal of transistor M1 is connected to the second terminal of transistor M2. The terminal is electrically connected to the first terminal of the transistor M6. The second terminal of the transistor M1 is electrically connected to the first terminal of the transistor M3 and the second terminal of the transistor M4. The gate of the transistor M6 is electrically connected to the wiring S1L. A first terminal of the transistor M1s is electrically connected to the wiring VE. The second terminal of the transistor M1s is electrically connected to the first terminal of the transistor M6s. The gate of the transistor M1s is connected to the first terminal of the capacitor C1s and the first terminal of the transistor M2s. The second terminal of the capacitor C1s is electrically connected ...

Claims

1. A memory cell; a first circuit having a constant current source circuit; a second circuit; the memory cell is electrically connected to the first circuit via a wiring; the memory cell is electrically connected to the second circuit via the wiring; the first circuit has a function of supplying a current according to a weighting coefficient to the memory cell using the constant current source circuit; the memory cell has a function of holding a current according to the weighting coefficient; The second circuit is a semiconductor device having a function of performing an arithmetic operation.

2. In claim 1, The second circuit is a semiconductor device having a function of calculating an activation function of a neural network.

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