Photonic crystal surface-emitting laser element and photonic crystal surface-emitting laser device

Abstract

To provide a photonic crystal surface-emitting laser element in which the effects of stress when the photonic crystal surface-emitting laser element is mounted on an element board can be avoided, and an increase in an oscillation threshold current and drive current can be suppressed, and which has a stable oscillation mode and excellent beam quality, and a photonic crystal surface-emitting laser device including the same.SOLUTION: A photonic crystal surface-emitting laser element includes: an element board; a first semiconductor layer provided on the element board; a first electrode electrically connected to the first semiconductor layer; an active layer provided on the first semiconductor layer; a second semiconductor layer with a conductivity type that is opposite to that of the first semiconductor layer, the second semiconductor layer being provided on the active layer; a hole layer included in the first semiconductor layer or the second semiconductor layer, the hole layer being a photonic crystal layer including holes disposed with two-dimensional periodicity in a plane parallel to the active layer; a light reflection layer provided between the element board and the first semiconductor layer; and a second electrode provided in electrical connection with the second semiconductor layer on the second semiconductor layer, the second electrode having a light emission part.SELECTED DRAWING: Figure 1

Description

[Technical Field]

[0001] The present invention relates to a photonic crystal surface-emitting laser element and a photonic crystal surface-emitting laser device. [Background technology]

[0002] In recent years, development of photonic-crystal surface-emitting lasers using photonic crystals (PC) has been progressing.

[0003] For example, Patent Document 1 discloses a photonic crystal surface emitting laser with high beam quality that suppresses higher-order mode oscillation, maintains the fundamental mode, and is stable even when a high current is injected.

[0004] However, when a photonic crystal surface-emitting laser element is mounted junction-down on a circuit board or a heat sink, stress generated in the photonic crystal layer increases the oscillation threshold current, reducing the light-emitting efficiency and making the oscillation mode unstable.

[0005] In particular, when oscillation in a mode called a flat band mode appears, the oscillation threshold current increases and the beam quality deteriorates significantly, which is undesirable even in applications where high light-gathering ability is required. [Prior art documents] [Patent documents]

[0006] [Patent Document 1] Japanese Patent Publication No. 2022-018026 Summary of the Invention [Problem to be solved by the invention]

[0007] The present invention has been made in consideration of the above points, and aims to provide a photonic crystal surface-emitting laser element and a photonic crystal surface-emitting laser device that avoid the influence of stress when mounted on an element substrate or the like, suppress increases in oscillation threshold current and drive current, have a stable oscillation mode, and have excellent beam quality. [Means for solving the problem]

[0008] A photonic crystal surface-emitting laser element according to one embodiment of the present invention comprises: an element substrate; a first semiconductor layer provided on the element substrate; a first electrode electrically connected to the first semiconductor layer; an active layer provided on the first semiconductor layer; a second semiconductor layer provided on the active layer and having an opposite conductivity type to that of the first semiconductor layer; a hole layer that is a photonic crystal layer included in the first semiconductor layer or the second semiconductor layer and has holes that are arranged with two-dimensional periodicity in a plane parallel to the active layer; a light reflecting layer provided between the element substrate and the first semiconductor layer; The light emitting device further includes a second electrode provided on the second semiconductor layer and electrically connected to the second semiconductor layer, the second electrode having a light emitting portion.

[0009] A photonic crystal surface-emitting laser element according to another embodiment of the present invention comprises: a light-transmitting element substrate; a first semiconductor layer provided on the element substrate; a first electrode electrically connected to the first semiconductor layer; an active layer provided on the first semiconductor layer; a second semiconductor layer provided on the active layer and having an opposite conductivity type to that of the first semiconductor layer; a hole layer that is a photonic crystal layer included in the first semiconductor layer or the second semiconductor layer and has holes that are arranged with two-dimensional periodicity in a plane parallel to the active layer; a light reflecting layer provided on the rear surface of the element substrate; The light emitting device further includes a second electrode provided on the second semiconductor layer and electrically connected to the second semiconductor layer, the second electrode having a light emitting portion.

[0010] A photonic crystal surface emitting laser device according to still another embodiment of the present invention comprises: the photonic crystal surface-emitting laser element; and a mounting substrate to which the photonic crystal surface-emitting laser element is bonded with a junction up by an element bonding member. [Brief explanation of the drawings]

[0011] [Figure 1] 1 is a cross-sectional view showing a cross section of a surface-emitting laser device according to a first embodiment. [Figure 2A] 1 is a cross-sectional view schematically illustrating an example of the structure of a photonic crystal surface-emitting laser device (PCSEL device). [Figure 2B] 2B is an enlarged cross-sectional view schematically showing photonic crystal layer 14P of FIG. 2A and holes arranged in photonic crystal layer 14P. FIG. [Figure 3A] FIG. 1 is a plan view schematically showing the upper surface of a PCSEL element. [Figure 3B] FIG. 2 is a cross-sectional view schematically showing a cross section of the photonic crystal layer in a plane parallel to the n-side guide layer. [Figure 3C] FIG. 2 is a plan view schematically showing the bottom surface of a PCSEL element. [Figure 3D] FIG. 10 is a plan view schematically showing holes formed by filling a hole formation region having a circular shape in a top view. [Figure 4] FIG. 2 is a diagram schematically showing a cross section of a photonic crystal layer perpendicular to the photonic crystal layer. [Figure 5] FIG. 10 is a diagram schematically showing a simulation result of stress calculated by the finite element method. [Figure 6A] FIG. 1 is a diagram showing the photonic bands of a PCSEL device. [Figure 6B]FIG. 10 is a diagram showing photonic bands at band edges A and B of a PCSEL device when εcenter<εedge. [Figure 6C] FIG. 10 is a diagram showing the photonic bands at band edges A and B of a PCSEL device when εcenter>εedge. [Figure 7] FIG. 10 is a cross-sectional view showing a cross section of a photonic crystal surface-emitting laser device having a PCSEL element according to a second embodiment. [Figure 8] FIG. 10 is a cross-sectional view showing a cross section of a photonic crystal surface-emitting laser device having a PCSEL element according to a third embodiment. DETAILED DESCRIPTION OF THE INVENTION

[0012] In the following, preferred embodiments of the present invention will be described, but these may be modified and combined as appropriate. In the following description and accompanying drawings, substantially the same or equivalent parts are designated by the same reference numerals.

[0013] [First embodiment] 1. Structure of photonic crystal surface-emitting laser device 1 is a cross-sectional view showing a photonic crystal surface-emitting laser device 5 of this embodiment. The surface-emitting laser device 5 has a photonic-crystal surface-emitting laser (PCSEL) element 10, an element bonding member 31, a mounting substrate 32, a substrate bonding member 34, a heat sink 35, and a housing 38.

[0014] Photonic crystal surface-emitting laser device (hereinafter also referred to as PCSEL device) 10 has a photonic crystal layer 14P inside. PCSEL device 10 also has a first electrode (n-electrode) 27 and a second electrode (p-electrode) 24.

[0015] The PCSEL device 10 is mounted on a mounting substrate 32 by being bonded to the mounting substrate 32 by a device bonding member 31. The PCSEL device 10 is bonded to the mounting substrate 32 in a so-called junction-up position, with the pn junction (i.e., the active layer) facing the light-emitting surface.

[0016] More specifically, the n-electrode 27 provided on the back surface of the element substrate 11 is joined by an element joining member 31 to a wiring electrode 33, which is a conductive layer on a mounting substrate 32, and is electrically connected.

[0017] The mounting board 32 is joined to the heat sink 35 by a board joining member 34. Furthermore, the wiring electrode 33 of the mounting board 32 is electrically connected by a bonding wire W2 to a first terminal 37B (cathode terminal) provided on the housing 38. Note that the connection is not limited to this, and the heat sink 35 may be a conductor and function as the first terminal (cathode terminal).

[0018] Furthermore, a bonding pad 24B provided on the p-electrode 24 of the PCSEL device 10 is electrically connected by a bonding wire W1 to a second terminal 37A (anode terminal) provided on the housing 38. Therefore, when a voltage is applied between the second terminal 37A and the first terminal 37B, the PCSEL device 10 emits light.

[0019] The above-mentioned components are housed in a housing 38 to form the surface-emitting laser device 5. (Mounting board) A diamond substrate with a thickness of 500 μm, which has excellent heat dissipation properties, was used as the base material 32A of the mounting substrate 32 (submount). Other materials that may be used as the base material 32A of the mounting substrate 32 include aluminum nitride (AlN), silicon carbide (SiC), alumina (Al2O3), copper-aluminum nitride-copper (Cu-AlN-Cu), copper-tungsten (CuW), GaN, and graphite.

[0020] In this embodiment, a metal film coating layer made of nickel / palladium / gold (Ni / Pd / Au) is used as the wiring electrode 33 of the mounting substrate 32. If the base material 32A of the mounting substrate 32 is a conductor, the wiring electrode 33 may not be provided. (Element joining material) The element bonding member 31 used was a paste material (MAX102 manufactured by Nippon Handa) in which silver particles (silver nanoparticles) were mixed in an organic solvent, or a paste material (AuRoFUSE manufactured by Tanaka Kikinzoku Kogyo) in which gold particles (gold nanoparticles) were mixed. This paste material can be sintered at 200°C, which is significantly lower than the 320°C sintering temperature of gold-tin alloy (AuSn), which has traditionally been used as a bonding material, and can bond the PCSEL element 10 to the mounting substrate 32. In other words, the PCSEL element 10 can be bonded while suppressing thermal distortion.

[0021] Specifically, after applying the adhesive to the mounting substrate 32, the PCSEL element 10 is pressed against the mounting substrate 32 at a pressure of approximately 1.5 kgf / cm. 2 The mounting substrate 32 on which the PCSEL device 10 was mounted under load was placed in a sintering oven, heated to 200° C. in an N 2 atmosphere, and sintered for 1 hour.

[0022] The sintering temperature may be in the range of 80 to 320°C. If the temperature is too low, the metal particles will not be sintered, and if the temperature is too high, the element characteristics will deteriorate. For example, the IV characteristics will be impaired. Furthermore, the sintering time should be long enough to vaporize the organic solvent contained in the element bonding member 31 during sintering, and may be, for example, 2 minutes to 8 hours.

[0023] In this embodiment, a paste material mixed with nanoparticles is used, but a bonding material such as AuSn, SnAgCu, etc. can also be used.

[0024] Although a paste material containing silver nanoparticles or gold nanoparticles is used in this embodiment, any paste material containing at least one type of metal fine particles (nanoparticles) such as gold (Au), silver (Ag), copper (Cu), etc. The use of nanometer-order metal fine particles in the element bonding member 31 is preferable because it allows for a lower bonding temperature between the PCSEL element 10 and the mounting substrate 32.

[0025] As described above, fine particles other than the metal nanoparticles described above can be used as long as they bond (neck) at the contact points between particles by sintering at low temperatures and have high conductivity and heat dissipation properties.

[0026] Furthermore, it is preferable that the element bonding member 31 has a Young's modulus smaller than that of the mounting substrate 32. The Young's modulus of the element bonding member 31 is more preferably 100 GPa or less, and even more preferably 70 GPa or less.

[0027] Alternatively, a room-temperature bonding process may be used to mount the PCSEL device 10 on the mounting substrate 32. For example, the bonding surfaces of the n-electrode 27 and wiring electrode 33 of the PCSEL device 10 are activated with Ar and H2 plasma, and then the n-electrode 27 and wiring electrode 33 are pressurized at room temperature. This allows the PCSEL device 10 and mounting substrate 32 to be bonded together.

[0028] (Bonding material for circuit boards) An indium alloy (content ratio: In0.52-Sn0.48) was used for the substrate bonding member 34. Specifically, after the substrate bonding material was applied to the heat sink 35, the heat sink 35 was heated to 120°C to soften the bonding material, and pressure was applied to the mounting substrate 32 on which the PCSEL device 10 was mounted, thereby bonding the heat sink 35 and the mounting substrate 32 together.

[0029] (heat sink) The heat sink 35 is made of copper (Cu), which has excellent electrical and thermal conductivity. A Peltier cooling device (not shown) is disposed on the back surface of the heat sink 35 (the surface opposite to the surface bonded to the mounting substrate 32), and the back surface is kept at a predetermined constant temperature.

[0030] (filled gas) The surface-emitting laser device 5 is sealed in a housing 38, and dry nitrogen is used as the gas filled inside. Other gases that can be used as the gas filled include nitrogen-oxygen mixed gas and dry air. When the wavelength of the light emitted from the PCSEL device 10 is shorter than 420 nm, the generation of carbides derived from residual organic matter can be suppressed by mixing a few percent of oxygen.

[0031] 2. Structure of photonic crystal surface-emitting laser element (1) Device structure A photonic crystal surface-emitting laser (PCSEL) has a resonator layer parallel to the semiconductor light-emitting structure layers (n-side guide layer, light-emitting layer, p-side guide layer) that make up the light-emitting element, and emits coherent light in a direction perpendicular to the resonator layer.

[0032] In other words, in a PCSEL device, light waves propagating in a plane parallel to the photonic crystal layer are diffracted by the diffraction effect of the photonic crystal to form a two-dimensional resonance mode, and are also diffracted in a direction perpendicular to the parallel plane. That is, in a PCSEL device, the light extraction direction is perpendicular to the resonance direction (in the plane parallel to the photonic crystal layer).

[0033] Fig. 2A is a cross-sectional view schematically illustrating an example of the structure of a photonic crystal surface-emitting laser device (PCSEL device) 10 according to an embodiment of the present invention. Fig. 2B is an enlarged cross-sectional view schematically illustrating a photonic crystal layer 14P (air hole layer) and air holes 14K arranged in the photonic crystal layer 14P in Fig. 2A.

[0034] 2A, a semiconductor structure layer 10A is formed on a light-transmitting device substrate 11. The semiconductor layers are stacked perpendicular to the central axis CZ of the semiconductor structure layer 10A.

[0035] The semiconductor structure layer 10A is made of a hexagonal nitride semiconductor. In this embodiment, the semiconductor structure layer 10A is made of, for example, a GaN-based semiconductor.

[0036] More specifically, a semiconductor structure layer 10A made up of a plurality of semiconductor layers is provided on an element substrate 11, which is a growth substrate. That is, the semiconductor structure layer 10A is configured by forming, in this order, a semiconductor multilayer reflective film 12, an n-clad layer (first clad layer of a first conductivity type) 13, an n-side guide layer (first guide layer) 14 which is a guide layer provided on the n-side, an active layer (ACT) 15, a p-side guide layer (second guide layer) 16 which is a guide layer provided on the p-side, an electron barrier layer (EBL: Electron Blocking Layer) 17, a p-clad layer (second clad layer of a second conductivity type) 18, and a p-contact layer 19.

[0037] Although the case where the first conductivity type is n-type and the second conductivity type opposite to the first conductivity type is p-type will be described, the first conductivity type and the second conductivity type may be p-type and n-type, respectively.

[0038] The device substrate 11 is a hexagonal GaN single crystal substrate with high transmittance for light emitted from the active layer 15. More specifically, the device substrate 11 is a hexagonal GaN single crystal substrate whose main surface (crystal growth surface) is the +c plane, which is the {0001} plane with Ga atoms arranged on the outermost surface. The back surface (light emission surface) is the -c plane, which is the (000-1) plane with N atoms arranged on the outermost surface. The -c plane is suitable as a light emission surface because it is resistant to oxidation and the like.

[0039] Although the element substrate 11 is not limited to this, a so-called just substrate or, for example, a substrate whose main surface is offset by about 1° in the m-axis direction is preferable. For example, a substrate offset by about 0.3 to 0.7° in the m-axis direction can achieve mirror-finish growth under a wide range of growth conditions.

[0040] The composition, thickness, and other configuration of each layer of the semiconductor structure layer 10A will be described below, but these are merely examples and can be modified as appropriate.

[0041] A semiconductor multilayer reflective film 12 is formed on the element substrate 11. The semiconductor multilayer reflective film 12 has a structure in which nitride semiconductor layers with different refractive indices are alternately stacked. For example, the semiconductor multilayer reflective film 12 is composed of a 1 μm-thick GaN underlayer formed on the upper surface of the element substrate 11, and 41 pairs of n-type AlInN layers (layer thickness 50 nm) and GaN layers (layer thickness 45 nm) formed on the GaN underlayer. The thickness, composition, and number of pairs of each layer can be appropriately selected depending on the desired reflectance and reflection wavelength.

[0042] The n-clad layer 13 formed on the semiconductor multilayer reflective film 12 is, for example, silicon (Si) doped n-Al having an Al composition of 4%. 0.04 Ga 0.96 The N layer has a thickness of 2 μm. The aluminum (Al) composition ratio is set so that the refractive index is smaller than that of the layer adjacent to the active layer 15 (that is, the n-side guide layer 14).

[0043] The n-side guide layer 14 is composed of a lower guide layer 14A, a photonic crystal layer (PC layer) 14P which is an air-hole layer, and a buried layer 14B. As shown in FIG. 2B, the photonic crystal layer 14P has a thickness d PC The buried layer 14B has a thickness d EMB For example, the thickness d PC is 40 to 180 nm.

[0044] In a plane parallel to photonic crystal layer 14P, holes 14K are arranged at lattice point positions (for example, square lattice point positions). That is, holes 14K are arranged with two-dimensional periodicity in a plane parallel to active layer 15.

[0045] In this specification, photonic crystal layer 14P refers to the layer portion of n-side guide layer 14 extending from the upper end to the lower end of the holes (see FIG. 2B). PC is equal to the height of the hole.

[0046] Lower guide layer 14A is, for example, n-GaN with a layer thickness of 100 to 400 nm. Photonic crystal layer 14P is n-GaN with a layer thickness (or depth of holes 14K) of 40 to 180 nm.

[0047] The buried layer 14B is made of n-GaN, n-InGaN, undoped GaN, or undoped InGaN. Alternatively, it may be a layer in which these semiconductor layers are stacked. The thickness d of the buried layer 14B is EMB The thickness is, for example, 50 to 150 nm. The buried layer 14B is made up of a first buried layer 14B1 and a second buried layer 14B2.

[0048] The n-side semiconductor layer including the n-cladding layer 13 and the n-side guide layer 14 is also referred to as a first semiconductor layer 13A (FIG. 1).

[0049] The active layer 15, which is a light-emitting layer, is, for example, a multiple quantum well (MQW) layer having a plurality of quantum well layers. The barrier layers and quantum well layers of the MQW are, for example, GaN (layer thickness 3.0 nm) and In, respectively. x Ga 1-x The active layer 15 has a thickness of 3.0 nm and a central emission wavelength of 440 nm.

[0050] Active layer 15 is preferably located within 180 nm of photonic crystal layer 14P (ie, within period PK of holes 14K). In this case, a high resonance effect is obtained by photonic crystal layer 14P.

[0051] The p-side guide layer 16 is made of an undoped GaN layer or an undoped InGaN layer, and has a layer thickness of, for example, 250 nm. 0.02 Ga 0.98N layer (70 nm thick) and undoped In 0.02 Ga 0.98 It consists of an undoped GaN layer (180 nm thick) formed on the N layer.

[0052] The p-side guide layer 16 is an undoped layer in consideration of light absorption by dopants (Mg: magnesium, etc.), but may be doped to obtain good electrical conductivity. In addition, the In composition and layer thickness of the InGaN layer of the p-side guide layer 16 can be appropriately selected to adjust the electric field distribution in the oscillation operation mode.

[0053] The electron barrier layer (EBL) 17 is a magnesium (Mg) doped p-type Al 0.2 Ga 0.8 The N layer has a thickness of, for example, 15 nm.

[0054] The p-cladding layer 18 is made of Mg-doped p-Al 0.06 Ga 0.94 The Al composition of the p-cladding layer 18 is preferably selected so that the refractive index is smaller than that of the p-side guide layer 16.

[0055] The p-contact layer 19 is an Mg-doped p-GaN layer having a thickness of, for example, 20 nm. The carrier density of the p-contact layer 19 is set to a concentration that allows for ohmic contact with the transparent electrode 29, which is a transparent conductive layer provided on the surface of the p-contact layer 19. Instead of p-type GaN, p-type or undoped InGaN may be used. Alternatively, a layer in which a GaN layer and an InGaN layer are stacked may be used.

[0056] The layer consisting of the p-side guide layer 16 , the electron barrier layer 17 , the p-cladding layer 18 and the p-contact layer 19 is also referred to as a second semiconductor layer 20 .

[0057] In this specification, "n-side" and "p-side" do not necessarily mean n-type and p-type. For example, an n-side guide layer means a guide layer provided on the n-side of the active layer, and may be an undoped layer (or i-layer).

[0058] The n-cladding layer 13 may be composed of multiple layers, not just a single layer. In this case, all layers do not need to be n-layers (n-doped layers), and may include undoped layers (i-layers). The same applies to the guide layer 16 and the p-cladding layer 18.

[0059] Furthermore, it is not necessary to provide all of the semiconductor layers described above, and it is sufficient to have a configuration having a first semiconductor layer of a first conductivity type, a second semiconductor layer of a second conductivity type, and an active layer (light-emitting layer) sandwiched between these layers.

[0060] Furthermore, in this embodiment, the case where the photonic crystal layer 14P (hole layer) is provided in the first semiconductor layer (n-type semiconductor layer) has been described, but the photonic crystal layer may also be provided in the second semiconductor layer (p-type semiconductor layer).

[0061] An insulating film 21 is provided on the p-contact layer 19. The insulating film 21 is made of, for example, SiO2 with a layer thickness of 100 nm. The insulating film 21 has a diameter D about a central axis CZ perpendicular to the semiconductor structure layer 10A. inj A circular opening is formed in the p-contact layer 19. The p-contact layer 19 is exposed from the opening. Specifically, the opening has a shape of, for example, D inj = 300 μm diameter.

[0062] A transparent electrode 23 (p-contact electrode) is provided on the insulating film 21 and the p-contact layer 19 exposed from the opening. That is, the transparent electrode 23 is formed by filling the opening, and forms a current injection region INJ connected to the p-contact layer 19 in the opening by ohmic contact. That is, the insulating film 21 functions as a current confinement layer. Note that the transparent electrode 23 is preferably formed by filling the opening to form a flat surface. For example, it is preferable that the region of the upper surface of the transparent electrode 23 corresponding to the opening be formed flat. The translucent electrode 23 is formed of a translucent conductor, for example, indium tin oxide (ITO), and has a layer thickness of 300 nm in the opening and a layer thickness of 200 nm on the insulating film 21. Note that the translucent electrode 23 is not limited to ITO, and a translucent conductor that is a metal oxide such as zinc tin oxide (ZTO), GZO (ZnO:Ga), or AZO (ZnO:Al) can be used.

[0063] The thickness of the transparent electrode 23 is preferably selected to be within the range of 20 nm to 300 nm.

[0064] A p-electrode 24 (anode) is provided on the transparent electrode 23. The p-electrode 24 is coaxial with the opening of the insulating film 21, that is, has a diameter D about the central axis CZ. AR The light exit area AR has a circular opening with a diameter D AR is the diameter D of the opening of the insulating film 21 which is the current injection region INJ (see FIG. 3A). inj (D inj ≦D AR That is, the light emitting region AR encompasses the opening in the insulating film 21 when viewed from above, and functions as a light emitting portion of the PCSEL device 10.

[0065] The p-electrode 24 is made of, for example, a Ni / Au layer formed by depositing nickel (Ni) and gold (Au) in this order. The p-electrode 24 may be made of a Ni / Pd (palladium) / Au layer, a Pt (platinum) / Au layer, a Ti / Pt (platinum) / Au layer, or the like.

[0066] The surface 23S of the translucent electrode 23 exposed from the opening of the p-electrode 24 is a light emitting region, and the surface 23S of the translucent electrode 23 is coated with an anti-reflection film (AR film) 25.

[0067] An n-electrode (cathode) 27 made of a Ti / Pt / Au layer is formed on the back surface of the element substrate 11 and is in ohmic contact with the element substrate 11. The n-electrode 27 is not limited to this, and other materials such as Ti / Al, Ti / Rh (rhodium), Ti / Al / Pt / Au, Ti / Au, V (vanadium) / Al, V / Rh, V / Al / Pt / Au, and V / Pt / Au can also be selected.

[0068] The side surfaces of the semiconductor structure layer 10A and the side surfaces of the insulating film 21, the translucent electrode 23, and the p-electrode 24 are covered with an insulating film 29 such as SiO2. The insulating film 29 is formed so as to extend over the p-electrode 24 and cover the edge of the upper surface of the p-electrode 24.

[0069] The insulating film 29 also functions as a protective film, protecting the aluminum (Al)-containing crystal layers that make up the PCSEL device 10 from corrosive gases and other contaminants. It also prevents short circuits caused by deposits or solder creeping up during mounting, contributing to improved reliability and yield. The material for the insulating film 29 is not limited to SiO2, but can also be ZrO2, HfO2, TiO2, Al2O3, SiNx, SiOx, Si, or a combination of these.

[0070] In the PCSEL device 10, light emitted from the active layer 15 is diffracted by the photonic crystal layer (PC layer) 14P. Light diffracted by the photonic crystal layer 14P and directly emitted from the photonic crystal layer 14P (direct diffracted light Ld: first diffracted light) and light diffracted by the photonic crystal layer 14P and reflected by the semiconductor multilayer reflective film 12 (reflected diffracted light Lr: second diffracted light) are emitted from the surface 23S of the light-transmitting electrode 23, i.e., from the p-electrode 24 side (emitted light LE). The distance between the diffracting plane where the diffracted light of the photonic crystal layer 14P is generated and the semiconductor multilayer reflective mirror 12 is preferably set so that the direct diffracted light Ld and the reflected diffracted light Lr interfere with each other and reinforce each other.

[0071] Fig. 3A is a plan view schematically showing the upper surface of the PCSEL device 10. Fig. 3B is a cross-sectional view schematically showing a cross section of the photonic crystal layer 14P in a plane parallel to the n-side guide layer 14, and Fig. 3C is a plan view schematically showing the lower surface of the PCSEL device 10.

[0072] FIG. 3A schematically shows the positional relationship between the current injection region INJ, the light emission region AR, and the hole formation region 14R when viewed from above (that is, when viewed along the central axis CZ).

[0073] As shown in FIG. 3A, a bonding pad 24B such as an Au wire or a bonding region 24B (denoted by the same reference numeral) may be provided on the p-electrode 24. In this case, the bonding pad or bonding region 24B is preferably provided outside the hole-forming region 14R in a top view. This can reduce the stress applied to the holes 14K in the photonic crystal layer 14P by bonding, thereby preventing deterioration of beam quality. It is sufficient that at least one bonding pad or bonding region 24B is provided in a top view. Furthermore, when two or more bonding pads or bonding regions 24B are provided, it is more preferable that they are arranged at equal intervals. This makes it possible to make the current density distribution uniform within the device surface. As shown in FIG. 3B, in photonic crystal layer 14P, holes 14K are provided, for example, in a rectangular hole formation region 14R, and are periodically arranged.

[0074] 3C, an n-electrode 27 is provided on the back surface of the element substrate 11. The n-electrode 27 does not have to be provided on the entire back surface, but may be provided by patterning. Furthermore, the n-electrode 27 does not have to be provided on the back surface of the element substrate 11, but may be provided on the upper surface of the element substrate 11.

[0075] 3D, the air hole formation region 14R preferably has a circular shape coaxial with the current injection region INJ in top view, and the air holes 14K are preferably arranged to fill this circular region. The stress and strain acting on the photonic crystal layer 14P due to the temperature rise caused by bonding the PCSEL device 10 to a circuit board or the like and operating the PCSEL device 10 becomes isotropic, thereby preventing degradation of beam quality.

[0076] (2) Photonic crystal layer structure 4 is a diagram schematically showing a cross section perpendicular to the central axis CZ of photonic crystal layer 14P. Photonic crystal layer 14P of this embodiment is a single-lattice photonic crystal layer in which air holes 14K are arranged at each of the square lattice points.

[0077] More specifically, the holes 14K have a long hexagonal shape, and their centers of gravity CD are arranged in a square lattice pattern at a period PK in two mutually perpendicular directions (x direction and y direction). The long axes of the holes 14K are parallel to the <11-20> direction of the crystal orientation, and the short axes of the holes 14K are parallel to the <1-100> direction.

[0078] Photonic crystal layer 14P is not limited to being a single-lattice photonic crystal layer, but may also be a multiple-lattice photonic crystal layer.

[0079] (3) Element manufacturing process (Step S1) Crystal growth Using an MOVPE growth apparatus, an n-type AlGaN layer doped with Si was grown as n-clad layer 13 on device substrate 11, which was an n-type GaN single crystal wafer. Next, an n-GaN layer was grown on n-clad layer 13 as a preparatory layer for photonic crystal layer 14P (vacancy layer). (Step S2) Formation of holes for vacancies Next, the wafer was removed from the MOVPE growth reactor, and fine holes were formed in the n-GaN layer to create vacancies (14K). Resist patterning was performed using an electron lithography system, and the holes were formed by dry etching using an ICP-RIE (Inductive Coupled Plasma - Reactive Ion Etching) system. (Step S3) Regrowth Next, the wafer with the holes formed therein was returned to the growth furnace, and buried growth was carried out to form n-side guide layer 14 consisting of lower guide layer 14A, photonic crystal layer 14P, and buried layer 14B. Subsequently, an n-side guide layer 14, an active layer 15, a p-side guide layer 16, an electron barrier layer 17, a p-cladding layer 18 and a p-contact layer 19 were grown in this order. (Step S4) Formation of insulating film and electrodes Next, an insulating film 21, a light-transmitting electrode 23, a p-electrode 24, an anti-reflection film 25, and an insulating film 29 were formed, and the back surface of the device substrate 11 was ground to a thickness of 170 μm and mirror-finished using a CMP (Chemical Mechanical Polishing) device. Next, an n-electrode 27 was formed on the back surface of the device substrate 11, thereby forming a wafer on which a plurality of PCSEL devices 50 were arranged. Note that these processes involved a patterning process and an etching process using photolithography, as well as a vapor deposition process. (Step S5) Singulation The wafer formed as described above was divided into individual pieces by laser scribing, to obtain the PCSEL devices 10.

[0080] (4) Junction-up junction We investigated the bonding of the PCSEL device 10 mounted on a circuit board or the like, and the stresses that are applied to the PCSEL device 10 due to the bonding. Figure 5 shows a schematic diagram of the results of a simulation of stress calculated using the finite element method.

[0081] For simplicity of calculation, we assumed that the mounting substrate 32 (submount) was diamond, and the PCSEL device 10 was a single layer of GaN. We also assumed that the device bonding member 31 was made of a paste material mixed with silver particles (silver nanoparticles), which was soldered (sintered) at 200°C, and then returned to room temperature of 25°C.

[0082] As shown in Figure 5, the stress generated when the temperature was returned to room temperature was very large at the solder joint surface, and the stress gradually decreased toward the element surface.

[0083] When the p-electrode side (i.e., the pn junction side) is used as the junction surface (junction down), the distance from the junction surface to the photonic crystal layer is approximately 1 μm, so it can be seen that a very large stress is applied to the photonic crystal layer.

[0084] On the other hand, in this embodiment, the n-electrode side (substrate side) is the junction surface (junction up), and the photonic crystal layer 14P (PC) is positioned at the position shown by the dashed line in the figure, i.e., away from the junction surface, so that the effect of stress on the photonic crystal layer 14P due to the junction can be significantly reduced.

[0085] 6A shows the photonic band of a PCSEL device. A PCSEL device oscillates by taking advantage of the zero group velocity effect (i.e., the resonance effect) at the Γ point of the photonic band.

[0086] For example, in the case of a square lattice photonic crystal, there are four oscillation modes (A, B, C, and D from the low frequency side) at the Γ point, and laser oscillation occurs in one of these modes. Each mode can be evaluated by measuring the spectrum at the Γ point before oscillation, that is, the emission spectrum in the direction perpendicular to the surface (normal direction) of the substrate.

[0087] When the stress on the hole formation region 14R (i.e., the region where the holes are formed) of the photonic crystal layer (hole layer) is large and the amount of distortion in the hole formation region 14R is large, the two-dimensional optical resonance effect in the photonic crystal layer weakens, and the flat band mode, which is a one-dimensional oscillation mode, is more likely to appear. Oscillation in the flat band mode is not desirable because it significantly deteriorates beam quality.

[0088] That is, when a PCSEL element is bonded junction-down, the distance between the photonic crystal layer and the bonding portion of the mounting substrate is short, which may cause stress and distortion in the photonic crystal layer, resulting in an unstable oscillation mode.

[0089] As described above, the degradation and instability of the emission mode due to the occurrence of stress or strain in the photonic crystal layer 14P is a problem specific to PCSEL devices that use a photonic crystal layer, and is not a problem in conventional semiconductor lasers.

[0090] 6B is a diagram showing the photonic bands at band edges A and B of the PCSEL device. More specifically, regarding the in-plane strain ε in the pore formation region 14R of the photonic crystal layer 14P, the strain ε at the edge of the pore formation region 14R is edge is the strain at the center, ε center If it is greater than (ε center <ε edge ) is shown.

[0091] In this case, the edges are subjected to stronger tensile strain than the center. That is, in the hole-formation region 14R, the hole spacing PK increases slightly from the center to the edges. Here, the resonant wavelength λ of a PCSEL element is expressed as "λ = n × PK" (n is the refractive index), so the resonant wavelength λ increases from the center to the edges.

[0092] For example, in the case of a PCSEL device with a square lattice photonic crystal, the resonance effect at band edges A and B, which have a mode frequency lower than the photonic band gap at the Γ point, is utilized. If the resonant wavelength λ has the distribution described above within the device, the spatial distribution of the resonant frequencies at band edges A and B will be as shown in Figure 6B. That is, in this case, at the edge of the current injection region INJ, light is localized in the center of the current injection region INJ due to the effect of reflection from the surrounding photonic band gap (white arrow in the figure). Therefore, ε center <ε edge In this case, the effective resonator size becomes smaller and the oscillation threshold current increases.

[0093] 6C is a diagram showing the photonic bands of the PCSEL element at band edges A and B. More specifically, the strain ε center is the strain at the edge ε edge If it is greater than (ε center >ε edge ) is shown.

[0094] In this case, the edges are subjected to stronger tensile strain than the center. That is, in the hole formation region 14R, the hole spacing PK decreases slightly from the center to the edges. Therefore, the resonant wavelength λ becomes shorter from the center to the edges.

[0095] For example, in the case of a PCSEL device having a square lattice photonic crystal, if the resonant wavelength λ has the distribution described above within the device, the spatial distribution of the resonant frequencies at the band edges A and B will be as shown in Figure 6C. center <ε edge In contrast to the case of , the photons spread over the entire surface.

[0096] In other words, the effective resonator area is approximately equal to the current injection area INJ, and the oscillation threshold does not increase. center ≧ε edge In this case, the increase in the threshold current can be suppressed.

[0097] However, even in this case, excessive strain ε distribution can cause degradation of the emission mode. Furthermore, the strain ε distribution is generally difficult to control because it depends on various conditions, such as the bonding material used to bond the PCSEL device, the bonding material thickness, bonding conditions (e.g., bonding temperature), the metal to which the PCSEL device is bonded, and the thickness of that metal.

[0098] That is, when a PCSEL element is bonded junction-down, the distance between the photonic crystal layer and the mounting substrate is short, and stress is applied to the photonic crystal layer, causing distortion and distortion distribution, which may result in an unstable oscillation mode.

[0099] As described above, the degradation and instability of the emission mode caused by the application of stress to the photonic crystal layer 14P and the occurrence of strain and strain distribution is a problem specific to PCSEL devices that use a photonic crystal layer.

[0100] As described above, according to this embodiment, it is possible to provide a PCSEL element suitable for junction-up junction.

[0101] Furthermore, the junction-up bonding can significantly reduce the stress applied to the photonic crystal layer, thereby suppressing increases in the oscillation threshold current and drive current of the photonic crystal surface-emitting laser element, and providing a photonic crystal surface-emitting laser device with a stable oscillation mode and excellent beam quality.

[0102] [Second embodiment] FIG. 7 is a cross-sectional view showing a cross section of a photonic crystal surface-emitting laser device 55 of the second embodiment. (1) Structure of light-emitting laser element and device The photonic crystal surface-emitting laser device 55 includes a PCSEL element 50. The PCSEL element 50 includes a dielectric multilayer reflective film (dielectric DBR) 52 formed on an element substrate 11, and a semiconductor burying layer 53 formed by burying the dielectric multilayer reflective film 52.

[0103] The PCSEL device 10 is the same as the PCSEL device 10 of the first embodiment in that an n-clad layer 13, an n-side guide layer 14, an active layer 15, a p-side guide layer 16, an electron barrier layer 17, a p-clad layer 18, and a p-contact layer 19 are formed in this order on the semiconductor buried layer 53.

[0104] Also, the insulating film 21, the transparent electrode 23, the p-electrode 24, and the anti-reflection film 25 are provided on the p-contact layer 19, which is the same as the PCSEL device 10 of the first embodiment.

[0105] The dielectric multilayer reflective film 52 has a structure in which dielectric layers having different refractive indices are alternately stacked. For example, the dielectric multilayer reflective film 52 is made of a layer of SiO2 and SiN x The dielectric multilayer reflective film 52 is entirely buried in the semiconductor burying layer 53.

[0106] An n-electrode 27 is provided on the back surface of the element substrate 11, and is joined onto a mounting substrate 32 by an element joining member 31. That is, the PCSEL element 50 is joined to the mounting substrate 32 with the junction facing up.

[0107] (2) Element formation process (Step S0-1) Formation of a multilayer reflective film Fourteen pairs of SiN / SiO2 multilayer reflective films (dielectric DBR) were formed by ECR (Electron Cyclotron Resonance) plasma deposition on an n-GaN single crystal wafer device substrate 11. The thicknesses of the SiN and SiO2 films should be set to λ / 4, where λ is the oscillation wavelength. The dielectric multilayer reflective film 52 has a diameter D HR The current injection area INJ has a circular shape and a diameter D inj (D inj ≦D HR ) For example, the diameter D of the current injection area INJ inj is 300 μm, and the diameter D HRis 350 μm.

[0108] The outer peripheral edge of the dielectric multilayer reflective film 52 is preferably tapered with respect to the element substrate 11, i.e., has a shape in which the diameter decreases with increasing distance from the element substrate 11, from the viewpoint of ease of embedding during burying growth. The tapered shape can be formed by a lift-off method, a dry etching method, or the like. Furthermore, the distance between the diffracting plane where diffracted light of the photonic crystal layer 14P is generated and the dielectric multilayer reflective film 52 is preferably set to a condition in which the direct diffracted light Ld and the reflected diffracted light Lr interfere with each other and reinforce each other.

[0109] (Step S0-2) Buried growth By MOVPE (metal organic vapor phase epitaxy), n-GaN was grown laterally on the device substrate 11 to bury the entire dielectric multilayer reflective film 52. 0.04 Ga 0.96 N was grown to 2 μm, and then n-GaN was grown to 500 nm, and the dielectric multilayer reflective film 52 was buried flat. (Step S1A) Crystal Growth Following the burying growth, an n-cladding layer 13 and an n-GaN layer (a preparatory layer for the vacancy layer) were grown in this order on the n-GaN growth layer having a flat surface. (Steps S2 to S5) The PCSEL device 50 was obtained by carrying out the same steps S2 to S5 as in the first embodiment described above.

[0110] In the PCSEL device 50 of this embodiment, light diffracted by the photonic crystal layer 14P and directly emitted from the photonic crystal layer 14P (direct diffracted light Ld) and light diffracted by the photonic crystal layer 14P and reflected by the dielectric multilayer reflective film 52 (reflected diffracted light Lr) are emitted to the outside from the surface 23S of the light-transmitting electrode 23, i.e., from the p-electrode 24 side (emitted light LE). Therefore, a PCSEL device suitable for junction-up junctions can be provided.

[0111] Furthermore, in the photonic crystal surface-emitting laser device 55 of this embodiment, the PCSEL element 50 is bonded to the mounting substrate 32 with the junction up by the element bonding member 31, and the stress acting on the photonic crystal layer 14P is significantly suppressed. Therefore, it is possible to provide a photonic crystal surface-emitting laser device in which increases in the oscillation threshold current and drive current of the photonic crystal surface-emitting laser element are suppressed, and which has a stable oscillation mode and excellent beam quality.

[0112] [Third embodiment] FIG. 8 is a cross-sectional view showing a photonic crystal surface-emitting laser device 65 having a PCSEL device 60 according to the third embodiment. (1) Structure of light-emitting laser element The PCSEL device 60 of this embodiment differs from the PCSEL device 10 of the first embodiment in that a light-reflecting film (DBR) is provided on the element substrate 11 in that a light-reflecting film 62 is provided on the back surface (element bonding surface) of the light-transmitting element substrate 11, but the other configurations are the same as those of the PCSEL device 10.

[0113] More specifically, the light reflecting film 62 has a diameter D about the central axis CZ. MR The current injection area INJ has a circular shape and a diameter D inj It has a size of more than (D inj ≦D MR ) For example, the diameter D of the current injection area INJ inj is 300 μm, and the diameter D HR is, for example, 350 μm.

[0114] An Ag alloy was used for the light reflecting film 62. Note that other materials such as Ag and Al may also be used for the light reflecting film 62, or a dielectric multilayer reflective film (dielectric DBR) may also be used.

[0115] The light reflecting film 62 was formed by grinding the wafer to a thickness of 170 μm, mirror finishing it by CMP, and then patterning and depositing an Ag alloy.

[0116] After the light reflecting film 62 was formed, an n-electrode 63 covering the light reflecting film 62 was formed by depositing Ti / Pt / Au (layer thickness: 10 nm / 100 nm / 700 nm) on the entire back surface of the element substrate 11 .

[0117] The wafer thus formed was then divided into individual pieces by laser scribing to obtain the PCSEL devices 60, similar to the PCSEL devices 10 and 51 of the first and second embodiments.

[0118] (2) Structure of photonic crystal surface-emitting laser device As shown in FIG. 8, the PCSEL element 60 is joined to a mounting substrate 32 by an element joining member 31 in a junction-up position.

[0119] In the PCSEL device 60, the direct diffracted light Ld from the photonic crystal layer 14P and the reflected diffracted light Lr emitted by the diffraction of the photonic crystal layer 14P and reflected by the light reflecting film 62 are emitted to the outside (emitted light LE) from the surface 23S of the light-transmitting electrode 23, i.e., from the opening (light emitting portion) of the p-electrode 24. Therefore, a PCSEL device suitable for junction-up bonding can be provided.

[0120] Therefore, in the photonic crystal surface-emitting laser device 65 of this embodiment, stress acting on the photonic crystal layer 14P of the PCSEL element 60 is significantly reduced, and therefore it is possible to provide a photonic crystal surface-emitting laser device that suppresses increases in the oscillation threshold current and drive current of the photonic crystal surface-emitting laser element, has a stable oscillation mode, and is excellent in beam quality.

[0121] As described above in detail, the present invention can provide a photonic crystal surface-emitting laser device that suppresses increases in the oscillation threshold current and drive current of the mounted PCSEL element, has a stable oscillation mode, and has excellent beam quality.

[0122] The numerical values in the above-described embodiment are merely examples and can be appropriately modified and applied.

[0123] Although a single-lattice photonic crystal layer in which air holes 14K are arranged at each square lattice point has been illustrated, the present invention can also be applied to PCSEL elements with triangular lattice structures, polygonal lattice structures, etc. Furthermore, although a PCSEL element with a single lattice structure has been illustrated, the present invention can also be applied to PCSEL elements with a multi-lattice structure.

[0124] Furthermore, although the present invention has been exemplified with respect to a photonic crystal layer in which the holes have a hexagonal columnar shape, the present invention can also be applied to cases in which the holes in the photonic crystal layer have an irregular columnar shape such as a cylindrical, rectangular, polygonal columnar, or teardrop shape. [Explanation of symbols]

[0125] 5, 55, 65: Surface-emitting laser device 10, 50, 60: PCSEL element 11: Element substrate 12: Semiconductor multilayer reflective film 13: First cladding layer 13A: First semiconductor layer 14: n-side guide layer (first guide layer) 14P: Photonic crystal layer 15: Active layer (ACT) 16: p-side guide layer (second guide layer) 17: Electron barrier layer 18: p-cladding layer (second cladding layer) 19: p-contact layer 20: Second semiconductor layer 21: insulating film 23: Translucent electrode 24:p electrode 27:n electrode 31: Element bonding material 32: Mounting board 32A: Base material 52: Multilayer reflective film 62:Light reflective film

Claims

1. an element substrate; a first semiconductor layer provided on the element substrate; a first electrode electrically connected to the first semiconductor layer; an active layer provided on the first semiconductor layer; a second semiconductor layer provided on the active layer and having an opposite conductivity type to that of the first semiconductor layer; a hole layer that is a photonic crystal layer included in the first semiconductor layer or the second semiconductor layer and has holes that are arranged with two-dimensional periodicity in a plane parallel to the active layer; a light reflecting layer provided between the element substrate and the first semiconductor layer; a second electrode provided on the second semiconductor layer and electrically connected to the second semiconductor layer, the second electrode having a light emitting portion;

2. The second electrode is an insulating film provided on the second semiconductor layer and having an opening; a transparent electrode that covers the insulating film and the opening and is in ohmic contact with the second semiconductor layer exposed from the opening; a metal electrode provided on the translucent electrode and having a light emission region that is an opening region that includes the opening of the insulating film in a top view; The photonic crystal surface-emitting laser element according to claim 1 , comprising:

3. 2. The photonic crystal surface-emitting laser element according to claim 1, wherein the light reflecting layer is a semiconductor multilayer reflecting film.

4. 2. The photonic crystal surface-emitting laser element according to claim 1, wherein the light reflecting layer is a dielectric multilayer reflective film, and the dielectric multilayer reflective film is entirely buried in the first semiconductor layer.

5. 2. The photonic crystal surface-emitting laser element according to claim 1, wherein the conductivity types of the first semiconductor layer and the second semiconductor layer are n-type and p-type, respectively.

6. a light-transmitting element substrate; a first semiconductor layer provided on the element substrate; a first electrode electrically connected to the first semiconductor layer; an active layer provided on the first semiconductor layer; a second semiconductor layer provided on the active layer and having an opposite conductivity type to that of the first semiconductor layer; a hole layer that is a photonic crystal layer included in the first semiconductor layer or the second semiconductor layer and has holes that are arranged with two-dimensional periodicity in a plane parallel to the active layer; a light reflecting layer provided on the rear surface of the element substrate; a second electrode provided on the second semiconductor layer and electrically connected to the second semiconductor layer, the second electrode having a light emitting portion;

7. 7. The photonic crystal surface-emitting laser element according to claim 6, wherein the light reflecting layer is a dielectric multilayer reflecting film.

8. 7. The photonic crystal surface-emitting laser element according to claim 6, wherein the conductivity types of the first semiconductor layer and the second semiconductor layer are n-type and p-type, respectively.

9. The photonic crystal surface-emitting laser element according to claim 1 , a mounting substrate to which the photonic crystal surface-emitting laser element is joined with the junction up by an element joining member.

10. 10. The photonic crystal surface emitting laser device according to claim 9, wherein the first electrode is provided on a rear surface of the element substrate and is joined to the mounting substrate by the element joining member.

11. The photonic crystal surface-emitting laser element according to any one of claims 6 to 8, a mounting substrate to which the surface-emitting laser element is joined with the junction up by an element joining member,

12. The photonic crystal surface emitting laser device according to claim 11 , wherein the light reflecting layer provided on the back surface of the element substrate is bonded to the mounting substrate by the element bonding member.

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