Light-emitting device, display device including the same, and electronic apparatus

Abstract

To provide a display device in which the leakage current of a light-emitting element is reduced.SOLUTION: A light-emitting device includes: a light-emitting element; a first transistor and a second transistor provided on a first surface of a silicon substrate; an insulating layer disposed between the light-emitting element and the first surface; and a third transistor provided in a peripheral circuit that supplies image signals. A source of the first transistor is connected to a gate electrode of the second transistor. A drain of the second transistor is connected to the light-emitting element. At least one of source, drain, or gate electrode of the third transistor includes a silicide layer. A region in which no silicide layer is provided exists between the source, drain, and gate of the first transistor or the second transistor and the insulating layer.SELECTED DRAWING: Figure 4

Description

[Technical Field]

[0001] The present invention relates to a light-emitting device, for example, a light-emitting device having a light-emitting element, a display device having the same, and an electronic device. [Background technology]

[0002] In recent years, display devices have become known that have arrays of light-emitting elements that emit light at a brightness that corresponds to the current flowing through the elements, and organic EL elements are used as the light-emitting elements. The applications of these display devices have expanded significantly, and higher definition and functionality are required depending on the application.

[0003] Patent Document 1 describes a display device having a semiconductor compound layer (silicide layer) of a high melting point metal at the source and drain of a drive transistor in a drive circuit for an organic light emitting element. [Prior art documents] [Patent documents]

[0004] [Patent Document 1] Japanese Patent Publication No. 2020-71323 Summary of the Invention [Problem to be solved by the invention]

[0005] The transistor described in Patent Document 1 has a silicide layer disposed in the source and drain. This silicide layer can reduce the resistance of the transistor. However, providing a silicide layer can also degrade the characteristics of the light-emitting device.

[0006] SUMMARY OF THE INVENTION It is therefore an object of the present invention to provide a light emitting device in which the degradation of characteristics caused by the provision of a silicide layer is reduced. [Means for solving the problem]

[0007] The present invention provides a light-emitting device having a light-emitting element, a first transistor and a second transistor provided on a first surface of a silicon substrate, an insulating layer disposed between the light-emitting element and the first surface, and a third transistor provided in a peripheral circuit that supplies an image signal to the first transistor, The present invention provides a light-emitting device, characterized in that either the source or drain of the first transistor is connected to the gate electrode of the second transistor, either the source or drain of the second transistor is connected to the light-emitting element, at least one of the source, drain, and gate electrode of the third transistor has a silicide layer, the silicide layer is in contact with the insulating layer, and there is a region where no silicide layer is provided between at least one of the source, drain, and gate electrode of the first transistor or the second transistor and the insulating layer. [Effects of the Invention]

[0008] According to the present invention, it is possible to provide a light emitting device in which the deterioration of characteristics caused by providing a silicide layer is reduced. [Brief explanation of the drawings]

[0009] [Figure 1] 1 is a schematic diagram illustrating an example of a light emitting device according to a first embodiment. [Figure 2] 1 is a circuit diagram illustrating an example of a pixel circuit of the light emitting device according to Embodiment 1. FIG. [Figure 3] 1(a) is a plan view showing an example of a circuit of the light emitting device according to the first embodiment, and FIG. 1(b) is a plan view showing an example of a transistor in a peripheral circuit of the light emitting device according to the first embodiment. [Figure 4] 1(a) is a cross-sectional view showing an example of a light emitting device according to Embodiment 1, and FIG. 1(b) is a cross-sectional view showing an example of a transistor in a peripheral circuit of the light emitting device according to Embodiment 1. FIG. [Figure 5] 10(a) is a cross-sectional view showing an example of a light emitting device according to Embodiment 2, and FIG. 10(b) is a cross-sectional view showing a modified example of the light emitting device according to Embodiment 2. FIG. [Figure 6]1A to 1D are schematic diagrams illustrating an example of a manufacturing process for a light emitting device according to one embodiment of the present invention. [Figure 7] 1(a) is a cross-sectional view showing an example of a light emitting device according to a third embodiment, and FIG. 1(b) is a cross-sectional view showing an example of a light emitting device according to a fourth embodiment. [Figure 8] 10(a) is a cross-sectional view showing an example of a light emitting device according to a fifth embodiment, and FIG. 10(b) is a cross-sectional view showing an example of a light emitting device according to the fifth embodiment. [Figure 9] FIG. 10 is a schematic diagram illustrating a light emitting device according to a sixth embodiment. [Figure 10] FIG. 13 is a circuit diagram illustrating an example of a pixel circuit according to a sixth embodiment. [Figure 11] FIG. 13 is a plan view illustrating an example of a pixel circuit according to a sixth embodiment. [Figure 12] FIG. 10 is a cross-sectional view illustrating an example of a light emitting device according to a sixth embodiment. [Figure 13] FIG. 10 is a schematic diagram illustrating an example of a light emitting device according to a seventh embodiment. [Figure 14] FIG. 11 is a circuit diagram illustrating an example of a pixel circuit of a light emitting device according to a seventh embodiment. [Figure 15] FIG. 13 is a plan view illustrating an example of a pixel circuit according to a seventh embodiment. [Figure 16] FIG. 11 is a cross-sectional view illustrating an example of a light emitting device according to a seventh embodiment. [Figure 17] 13 is an example of an inverter circuit in a vertical scanning circuit according to the eighth embodiment. [Figure 18] FIG. 13 is a plan view illustrating an example of a circuit according to an eighth embodiment. [Figure 19] FIG. 13 is a cross-sectional view illustrating an example of a light emitting device according to an eighth embodiment. [Figure 20] 1 is a schematic diagram illustrating an example of a display device according to an embodiment of the present invention. [Figure 21] 1A is a schematic diagram illustrating an example of an imaging device according to an embodiment of the present invention, and FIG. 1B is a schematic diagram illustrating an example of an electronic device according to an embodiment of the present invention. [Figure 22] 1(a) and 1(b) are schematic diagrams illustrating an example of a display device according to an embodiment of the present invention. [Figure 23] FIG. 1 is a schematic diagram illustrating an example of a wearable device according to an embodiment of the present invention. DETAILED DESCRIPTION OF THE INVENTION

[0010] A light emitting device according to one embodiment of the present invention is a light emitting device including: a light emitting element; a first transistor and a second transistor provided on a first surface of a silicon substrate; an insulating layer disposed between the light emitting element and the first surface; and a third transistor provided in a peripheral circuit that supplies an image signal to the first transistor, one of a source and a drain of the first transistor is connected to a gate electrode of the second transistor, and one of a source and a drain of the second transistor is connected to the light-emitting element; The light-emitting device is characterized in that at least one of the source, drain, and gate electrode of the third transistor has a silicide layer, the silicide layer is in contact with the insulating layer, and there is a region where no silicide layer is provided between at least one of the source, drain, and gate electrode of the first transistor or the second transistor and the insulating layer.

[0011] By providing a region where no silicide layer is provided between the insulating layer and at least one of the source, drain, and gate electrode of the first transistor or the second transistor, the leakage current in this region can be reduced.

[0012] Furthermore, a light emitting device according to another embodiment of the present invention is a light emitting device including a light emitting element, a first transistor and a second transistor provided on a first surface of a silicon substrate, and a third transistor provided in a peripheral circuit that supplies an image signal to the first transistor, The light-emitting device is characterized in that either the source or drain of the first transistor is connected to the gate electrode of the second transistor, either the source or drain of the second transistor is connected to the light-emitting element, at least one of the source, drain and gate electrode of the third transistor has a salicide structure, and at least one of the source, drain and gate electrode of the first transistor or the second transistor does not have a salicide structure.

[0013] By not providing a salicide structure in at least one of the source, drain, and gate electrode of the first transistor or the second transistor, it is possible to reduce the leakage current in this region.

[0014] Hereinafter, embodiments will be described in detail with reference to the accompanying drawings. Note that the following embodiments do not limit the scope of the invention claimed. Although multiple features are described in the embodiments, not all of these multiple features are necessarily essential to the invention, and multiple features may be combined arbitrarily. Furthermore, in the accompanying drawings, the same reference numerals are used to designate the same or similar components, and redundant explanations will be omitted.

[0015] In the following embodiments, a driving transistor is connected to the anode of the organic light-emitting element, and all the transistors are P-type transistors. However, the light-emitting device of the present invention is not limited to this. The polarity and conductivity type may all be reversed. The transistors may be either P-type or N-type transistors. To change the type, the supplied potential or connection may be changed appropriately according to the conductivity type and polarity.

[0016] In the following embodiments, the peripheral circuits may be provided on the same silicon substrate as the pixel transistors, or may be provided on a second silicon substrate different from the first silicon substrate on which the pixel transistors are provided.

[0017] In this specification, the light-emitting element may be an organic light-emitting element in which the light-emitting portion is a light-emitting layer containing an organic compound, or an inorganic light-emitting element in which the light-emitting portion is made of an inorganic compound.

[0018] An organic light-emitting element has an organic layer including a light-emitting layer between an anode and a cathode. In addition to the light-emitting layer, the organic layer may appropriately have one or more of a hole injection layer, a hole transport layer, an electron injection layer, and an electron transport layer. A display device having an organic light-emitting element is an example of a light-emitting device and is also called an organic light-emitting device.

[0019] In the following embodiments, examples using organic light-emitting elements will be described.

[0020] [Embodiment 1] 1 is a schematic diagram of an example of a light-emitting device according to this embodiment. The light-emitting device 101 has a pixel array section 103 and a peripheral circuit section arranged around the pixel array section 103. The pixel array section 103 has a plurality of pixels 102 arranged two-dimensionally in a matrix, and each pixel 102 has an organic light-emitting element 201 (shown in FIG. 2).

[0021] The light emitting device 101 has a peripheral circuit section that drives each pixel 102. The peripheral circuit section has, for example, a vertical scanning circuit 104 and a signal output circuit 105. In the pixel array section 103, a first scanning line 106 is arranged for each row of pixels along the row direction. In addition, a signal line 107 is arranged for each column of pixels along the column direction.

[0022] The first scanning line 106 is connected to an output terminal of the corresponding row of the vertical scanning circuit 104. Furthermore, the signal line 107 is connected to an output terminal of the corresponding column of the signal output circuit 105. The vertical scanning circuit 104 supplies the first scanning line 106 with a write control signal that controls the timing of writing a video signal to each pixel 102 in the pixel array section 103. The signal output circuit 105 outputs a luminance signal having a voltage corresponding to luminance information.

[0023] 2 is a circuit diagram showing an example of a pixel circuit included in the light-emitting device 101 of FIG. 1. The pixel 102 includes a light-emitting element 201, a driving transistor 202 (DRV), a writing transistor 203 (SEL), and a first capacitor 204. One of the source and drain of the driving transistor 202 is connected to a first electrode of the light-emitting element 201, and the other of the source and drain of the driving transistor 202 is connected to a first power supply terminal 205 (hereinafter referred to as Vdd). A second electrode of the light-emitting element 201 is connected to a second power supply terminal 206 (hereinafter referred to as Vss).

[0024] One of the source and drain of the write transistor 203 is connected to the gate electrode of the drive transistor 202, and the other of the source and drain of the write transistor 203 is connected to the signal line 107. The gate electrode of the write transistor 203 is connected to the first scan line 106.

[0025] The first capacitance element 204 is connected between the gate of the driving transistor 202 and one of the source and drain (here, the source), and holds the respective luminance signals in each pixel 102. The first capacitance element 204 may be any of a parasitic capacitance, a capacitance between the gate and channel of a MOS, an MIM (Metal-Insulator-Metal) structure, and an MOM (Metal-Oxide-Metal) structure.

[0026] In this embodiment, the drain of the driving transistor 202 is connected to the anode of the light emitting element 201, and the source of the driving transistor 202 is connected to a first power supply terminal 205 (Vdd).

[0027] The first capacitance element 204 is connected between the gate electrode of the driving transistor 202 and the source of the driving transistor 202, and holds the respective luminance signals in each pixel 102. The first capacitance element 204 according to this embodiment has an MIM structure.

[0028] Fig. 3(a) is a plan view of an example of the circuit shown in Fig. 2. The driving transistor 202 is composed of a gate electrode 301, a source 302, and a drain 303.

[0029] The write transistor 203 is composed of a gate electrode 304, a source 305, and a drain 306. Reference numeral 307 denotes a contact wiring, which is connected to wiring in other layers.

[0030] 3(b) is a plan view of an example of a transistor in the peripheral circuit. A transistor 308 in the peripheral circuit is composed of a gate electrode 309, a source 310, and a drain 311. The peripheral circuit supplies an image signal to the writing transistor. Here, the image signal is a signal that controls the timing at which the writing transistor turns on or a signal that represents a luminance signal.

[0031] 4(a) is a cross-sectional view taken along line AA' in the plan view shown in FIG. 3(a). All of the transistors according to this embodiment are provided on an N-type well layer 407 provided on a first surface of a P-type silicon substrate 408. Specifically, a drive transistor 202 and a write transistor 203 are provided, and these transistors are separated by an insulator isolation portion 409. The source and drain of the drive transistor 202 and the write transistor 203 are formed by P-type diffusion layers 401 and 402, respectively. The insulator isolation portion 409 may be any of STI (Shallow Trench Isolation) isolation, LOCOS (Local Oxidation Of Silicon) isolation, and N-type diffusion layer isolation.

[0032] The silicide layer 405 can reduce the contact resistance between the source or drain of the transistor and the contact wiring 307. The silicide layer 405 may be a silicide layer formed using a salicide (self aligned silicide) process.

[0033] The salicide process involves the following steps: (a) forming a film of metal elements on a semiconductor layer, (b) silicidation, and (c) removing the metal elements. First, a film containing metal elements is formed on the surface of the semiconductor layer using a method such as PVD. Next, when the semiconductor layer is heated, the metal elements on the semiconductor layer react to form silicide. Areas that are not semiconductor layers, such as metal layers on insulating layers such as silicon oxide layers, are not silicidated and remain as metal layers.

[0034] Next, the metal layer on top of the insulating layer is selectively removed using a chemical treatment. This process leaves silicide on the gate, source, and drain of the transistor if no insulating layer is provided. This process is called the salicide process because silicide is formed in a self-aligned manner.

[0035] When a semiconductor region that will become a source or drain region is heated while in contact with a metal such as a contact electrode, the contact portion between the semiconductor region and the metal may be silicided. In this case, silicide is formed on the source or drain region. However, even in this case, silicide is not provided in at least a portion of the region where the source or drain region contacts the insulating layer. In this specification, silicide formed during the formation of such contact electrodes is not included in the salicide structure or silicide layer.

[0036] The metal element constituting the silicide layer is, for example, at least one selected from the group consisting of titanium, nickel, cobalt, tungsten, molybdenum, tantalum, chromium, palladium, and platinum, or an alloy containing one of the metal elements as a main component. For example, the silicide layer provided in the source or drain region 211 of the transistor in the second semiconductor layer 200 is cobalt silicide, and the metal element constituting the silicide layer is cobalt.

[0037] The insulating layer 406 is an insulating layer provided between the light-emitting element 201 and the first surface of the silicon substrate. The insulating layer 406 is also called an interlayer insulating layer and constitutes part of the wiring layer of the light-emitting device. As shown in the figure, the insulating layer 406 is the interlayer insulating layer closest to the silicon substrate. The contact electrodes 307 contact the source, drain, and gate electrodes of the drive transistor 202 and the write transistor 203 through openings provided in the insulating layer 406.

[0038] The source, drain, and gate electrode of the write transistor 203 are provided with silicide layers. On the other hand, the source, drain, and gate electrode of the drive transistor 202 are not provided with silicide layers. The provision of a silicide layer in the write transistor 203 reduces the resistance between the write transistor 203 and the contact electrode. Considering only the reduction in resistance, it is conceivable to provide a silicide layer in the drive transistor 202 as well. However, heat applied during the manufacturing process can cause metal atoms constituting the silicide layer to diffuse into the depletion layer of the transistor, which can generate dark electrons. This can result in a source of leakage current flowing between the source and drain of the drive transistor 202. The occurrence of leakage current changes the amount of current flowing through the light-emitting element 201, potentially resulting in variations in the brightness of the light-emitting element. Therefore, in this embodiment, the absence of a silicide layer in the drive transistor 202 reduces leakage current and enables high-quality black display.

[0039] 4(b) is a cross-sectional view taken along line BB' in the plan view shown in FIG. 3(b). As shown in FIG. 4(b), the source and drain of the peripheral circuit transistor 308 are formed by P-type diffusion layers 410 and 411, respectively. A silicide layer is provided in at least one of the source, drain, and gate electrode of the peripheral circuit transistor. In the peripheral circuit transistor according to this embodiment, performance is improved by lowering the resistance of the transistor rather than reducing the leakage current.

[0040] That is, the light emitting device according to this embodiment has a configuration in which there are regions in which no silicide layer is provided between the source, drain and gate electrodes of the driving transistor and the insulating layer.

[0041] According to the configuration of this embodiment, no silicide layer is provided on the source and drain of the driving transistor 202, thereby making it possible to reduce the diffusion of metal atoms in the silicide layer into the depletion layer around the source and drain of the driving transistor 202. This reduces the leakage current flowing from the driving transistor 202 to the light-emitting element 201, enabling high-quality black display.

[0042] In this embodiment, an example has been shown in which a silicide layer is not disposed on any of the source, drain, and gate electrode of the driving transistor 202, but even if the driving transistor 202 does not have a silicide layer on at least a part of the source, drain, and gate electrode, but has a silicide layer on one of the regions, the effect of reducing leakage current compared to the conventional configuration can be achieved. In other words, this effect is achieved by having a region without a silicide layer in a part of the source, a part of the drain, or a part of the gate electrode of the driving transistor 202, and is not limited to the description of this embodiment.

[0043] [Embodiment 2] 5(a) is a cross-sectional view of a light-emitting device according to this embodiment. This embodiment differs from embodiment 1 in that a silicide layer is provided between the insulating layer 406 and the source, drain, and gate electrodes of the driving transistor. This embodiment also differs from embodiment 1 in that a silicide layer is not provided between the insulating layer 406 and the source, drain, and gate electrodes of the writing transistor. In embodiment 1, a pixel circuit configuration for reducing the occurrence of leakage current in the driving transistor was described. In contrast, this embodiment describes a pixel circuit configuration for reducing leakage current in the writing transistor.

[0044] 5(a), a silicide layer 405 is provided on the source, drain, and gate electrode of the drive transistor 202, and the silicide layer 405 is in contact with an insulating layer 406. On the other hand, no silicide layer is provided between the source, drain, and gate electrode of the write transistor 203 and the insulating layer 406, and the source, drain, and gate electrode of the write transistor 203 are in contact with the insulating layer 406. The other transistors of the peripheral circuit are the same as those shown in FIG. 4(b).

[0045] That is, the light emitting device according to this embodiment has a configuration in which there are regions where the silicide layer 405 is not provided between the source, drain, and gate electrode of the write transistor 203 and the insulating layer 406 .

[0046] The above configuration reduces the resistance between the drive transistor 202 and the contact electrode. On the other hand, the write transistor 203 does not have a silicide layer, and the leakage current between the source and drain of the write transistor 203 is reduced.

[0047] The source or drain of the writing transistor 203 is connected to one electrode of the first capacitor 204. When the leakage current of the writing transistor is reduced, the charge flowing out from one electrode of the first capacitor 204 can be reduced. As a result, the fluctuation in the potential of the gate electrode of the driving transistor 202 connected to one electrode of the first capacitor can be reduced. The potential of one electrode of the first capacitor 204 is the potential of the gate electrode of the driving transistor 202, which is a potential that affects the light emission luminance of the light emitting element 201. Therefore, if the fluctuation in the potential of one electrode of the first capacitor 204 is reduced, the fluctuation in light emission luminance can be reduced. By reducing the fluctuation in light emission luminance, a display device with high display quality can be provided.

[0048] 5B shows a modified example of the light emitting device according to this embodiment, in which neither the drive transistor 202 nor the write transistor 203 has a silicide layer.

[0049] That is, in a cross section perpendicular to the first surface of the silicon substrate, the light-emitting device has an area in which no silicide layer is provided between any of the source, drain, and gate electrodes of the drive transistor 202 and the write transistor 203 and the insulating layer.

[0050] With this structure, the resistance of the transistors in the peripheral circuits can be reduced, and leakage currents in both the driving transistor 202 and the writing transistor 203 can be reduced.

[0051] 6(a) to 6(d) are schematic diagrams showing an example of a manufacturing process for the light emitting device according to the above embodiment.

[0052] 6(a) shows a configuration in which an insulating layer 410 is formed so as to cover the drive transistor 202 and the write transistor 203. The insulating layer 413 may be formed by a sputtering method, an atomic deposition method, a vapor deposition method such as CVD, or the like.

[0053] Next, the insulating layer 413 is partially removed. Specifically, the insulating layer 413 is removed so that at least one of the driving transistor 202 and the writing transistor 203 is exposed.

[0054] 6(b) is a cross-sectional view showing a configuration in which the insulating layer 413 has been removed to expose the write transistor 203. A known technique such as etching can be used to expose the write transistor. In this embodiment, the process is described as exposing the write transistor 203 after forming the insulating layer 413 on the entire surface, but the process may also be a process in which the insulating layer 413 is selectively disposed on the drive transistor 202.

[0055] 6(c) is a cross-sectional view showing a configuration in which a metal layer 414 is disposed on the insulating layer 413 and the write transistor 203. After the metal layer 414 is formed so as to cover the drive transistor 202 and the write transistor 203, heating or the like is performed to form a silicide layer 405. Because the drive transistor 202 is covered with the insulating layer 413, the silicon substrate of the drive transistor section and the metal layer 414 are not in contact with each other. As a result, the silicide layer 405 is not formed on the drive transistor 202. This process in which the silicide layer 405 is disposed in areas other than where the insulating layer 413 is formed is the salicide process described above, and the silicide layer formed by the salicide process is the salicide structure in this specification.

[0056] FIG. 6(d) is a cross-sectional view of an example of a light-emitting device after forming the silicide layer 405. After forming the silicide layer 405, the metal layer 414 is selectively removed. Here, the metal layer 414 is removed, but the silicide layer 405 formed on the write transistor 203 is not removed. Then, an insulating layer 406 is formed. In this embodiment, the insulating layer 406 is made of the same material as the insulating layer 413, so the boundary between the insulating layer 413 and the insulating layer 406 is not shown. After forming the insulating layer 406, openings for forming the contact electrodes 307 are formed, and connections are made between the source, drain, and gate electrodes and the contact electrodes 307. The openings are sometimes called vias. Here, the first opening for the contact electrodes in contact with the write transistor 203 overlaps the silicide layer or salicide structure in a planar view of the silicon substrate. The second opening for the contact electrodes in contact with the drive transistor does not overlap the silicide layer or salicide structure in a planar view of the silicon substrate. The first and second openings may have opposite configurations depending on the embodiment.

[0057] By the above process, an example of a light-emitting device according to this embodiment can be manufactured. A silicide layer is formed in the transistor 308 of the peripheral circuit by the above-described salicide process. The light-emitting device according to this embodiment configured in this manner has a salicide structure in at least one of the source, drain, and gate electrode of the transistor 308 of the peripheral circuit, and does not have a salicide structure in at least one of the source, drain, and gate electrode of the drive transistor.

[0058] In this embodiment, a configuration has been described in which a silicide layer is provided on the source, drain, and gate electrode of the write transistor 203, and no silicide is provided on the source, drain, and gate electrode of the drive transistor 202. However, a configuration in which a silicide layer is not provided on the source, drain, and gate electrode of the write transistor 203 may also be used, or a silicide layer may not be provided on either the drive transistor 202 or the write transistor 203.

[0059] [Embodiment 3] Fig. 7(a) is a cross-sectional view of the light emitting device according to this embodiment taken along line AA' in Fig. 3(a). The light emitting device according to this embodiment is the same as that of embodiment 1 except that the source and drain of the driving transistor are low-concentration P-type diffusion layers. The following description will focus on the configuration that differs from other embodiments.

[0060] The source and drain of the driving transistor 202 of the light-emitting device according to this embodiment are formed by low-concentration P-type diffusion layers 701 and 702, respectively, and have a concentration distribution with a concentration peak in the direction from the source to the drain. These peak concentrations are lower than the peak concentrations of the P-type diffusion layers 410 and 411 of the transistor 308 in the peripheral circuit. Here, the peak concentration refers to the concentration at the concentration peak.

[0061] That is, the impurity concentration in the source diffusion region of the driving transistor 202 and the impurity concentration in the drain diffusion region have a concentration distribution with a peak concentration in a first direction from the source to the drain, and the impurity concentration in the source diffusion region of the peripheral transistor 308 and the impurity concentration in the drain diffusion region have a concentration distribution with a peak concentration in a second direction from the source to the drain.

[0062] The peak concentration of impurities in the diffusion region of the source or drain of the driving transistor 202 is configured to be lower than the peak concentration of impurities in the diffusion region of the source or drain of the peripheral transistor.

[0063] This configuration reduces the electric field strength between the source and drain of the driving transistor 202 and the N-type well layer 407, thereby reducing the leakage current flowing from the well to the source and drain. This also reduces the leakage current flowing from the driving transistor 202 to the organic light-emitting element 201, enabling high-quality black display.

[0064] In this embodiment, the peak concentration of impurities in the driving transistor 202 is smaller than the peak concentration of impurities in the transistors of the peripheral circuit. However, the present invention is not limited to this, and the peak concentration of impurities in other transistors may be smaller than the peak concentration of impurities in the transistors of the peripheral circuit.

[0065] [Embodiment 4] 7(b) is a cross-sectional view of the light emitting device according to this embodiment taken along line AA' in FIG. 3(a). In this embodiment, the source and drain of the write transistor 203 are low-concentration P-type diffusion layers, and no semiconductor compound layer is disposed. The following description will focus on the configuration that differs from other embodiments.

[0066] The source and drain of the write transistor 203 are formed by low-concentration P-type diffusion layers 703 and 704, respectively, which have a concentration distribution with a peak concentration in the direction from the source to the drain, which is lower than the peak concentration of the P-type diffusion layers 410 and 411 of the transistor 308 in the peripheral circuit.

[0067] That is, the impurity concentrations in the source diffusion region and the drain diffusion region of the write transistor 203 have concentration distributions with concentration peaks in a third direction from the source to the drain, the impurity concentrations in the source diffusion region and the drain diffusion region of the transistor 308 in the peripheral circuit have concentration distributions with concentration peaks in a second direction from the source to the drain, and the peak impurity concentration in the source or drain diffusion region of the write transistor 203 is smaller than the peak impurity concentration in the source or drain diffusion region of the transistor 308 in the peripheral circuit. Here, the peak concentration refers to the concentration at the concentration peak.

[0068] With this configuration, it is possible to reduce the electric field strength between the source and drain of the write transistor 203 and the N-type well layer 407, and to reduce the leakage current flowing from the well to the source and drain. This also reduces the leakage current flowing into the first capacitance element 204, making it possible to reduce fluctuations in the luminance signal held by the first capacitance element 204. Therefore, the organic light emitting element 201 can emit light stably at a predetermined luminance.

[0069] [Embodiment 5] 8(a) is a cross-sectional view of the light-emitting device according to this embodiment taken along line AA' in FIG. 3(a). In this embodiment, the write transistor 203 and the peripheral circuit transistor have a halo structure. The following description will focus on the configuration that differs from other embodiments.

[0070] In the write transistor 203, high-concentration N-type diffusion layers 801 and 802, which are halo injection layers, are adjacent to low-concentration P-type diffusion layers 703 and 704, respectively, and a lower-concentration N-type well layer 407 is disposed between the high-concentration N-type diffusion layers 801 and 802.

[0071] The driving transistor 202 according to this embodiment has a structure in which a halo injection layer is not disposed. The driving transistor 202 supplies a subthreshold current to the organic light-emitting element. Therefore, if a halo injection layer were disposed, the subthreshold current would vary greatly from pixel to pixel, even if the concentration variation in the halo injection layer was small. By not disposing a halo injection layer, it is possible to reduce variation in the amount of current supplied by the driving transistor 202 to the organic light-emitting element 201.

[0072] 8(b) is a cross-sectional view of the light-emitting device according to this embodiment taken along line BB' in FIG. 3(b). As shown in FIG. 8(b), in the peripheral circuit transistor 308, N-type diffusion layers 803 and 804, which are halo-implanted layers, are adjacent to the P-type diffusion layers 410 and 411, respectively, and a lower-concentration N-type well layer 407 is disposed between the N-type diffusion layers 803 and 804. In this embodiment, the peak concentrations of the high-concentration N-type diffusion layers 701 and 702 constituting the write transistor 203 are higher than the peak concentrations of the N-type diffusion layers 703 and 704 constituting the peripheral circuit transistor 308. However, this is not limiting and the concentrations of the halo-implanted layers may be adjusted appropriately depending on the amount of leakage current, and the magnitude relationship may be reversed.

[0073] In the light-emitting device according to this embodiment, the write transistor 203 has a halo injection layer in the source and drain diffusion regions, and the halo injection layer has the opposite polarity to that of the diffusion regions, i.e., the halo injection layer has the same polarity as the channel formed when the transistor is turned on.

[0074] The peripheral transistor 308 has halo implants in the source and drain diffusion regions, which are of opposite polarity to the diffusion regions.

[0075] The peak impurity concentration in the halo implantation layer of the write transistor 203 is higher than the peak impurity concentration in the halo implantation layer of the peripheral circuit transistor 308. In this embodiment, the relationship of the peak concentrations is configured as described above, but it is sufficient that the peak impurity concentration in the halo implantation layer of the write transistor 203 is different from the peak impurity concentration in the halo implantation layer of the peripheral circuit transistor 308. The peak impurity concentration can be adjusted by adjusting the control of the leakage current.

[0076] With this configuration, it is possible to reduce the leakage current flowing from the source to the drain of the writing transistor 202 and the first capacitor 204, and to suppress fluctuations in the luminance signal held by the first capacitor 204. Therefore, the organic light emitting element 201 can emit light stably at a predetermined luminance. In addition, it is possible to suppress the leakage current flowing from the source to the drain of the peripheral circuit transistor 308, and to reduce current consumption in the peripheral circuit section.

[0077] [Embodiment 6] This embodiment has a light-emitting control transistor arranged between a power supply that supplies current to the light-emitting element and a drive transistor. More specifically, it has a configuration that has a light-emitting control transistor 1001 that controls the current supply from Vdd 205 to the drive transistor 202. The following will mainly explain the configuration that differs from other embodiments. The light-emitting control transistor is also called the fourth transistor, following the drive transistor, write transistor, and transistors of the peripheral circuit.

[0078] 9 is a schematic diagram illustrating an example of a light-emitting device according to this embodiment. In the pixel array section 103, a second scanning line 901 is arranged for each pixel row along the row direction. The second scanning line 901 is connected to the output terminal of the corresponding row in the vertical scanning circuit 104, and supplies a light-emitting control signal to each pixel 102.

[0079] 10 is a circuit diagram showing an example of a pixel circuit included in the light-emitting device of FIG. 9. One of the source and drain (here, the drain) of the light-emitting control transistor 1001 is connected to one of the source and drain (here, the source) of the driving transistor 202. The other (here, the source) of the light-emitting control transistor 1001 is connected to Vdd 205. In addition, the gate of the light-emitting control transistor 1001 is connected to a second scanning line 901.

[0080] The second capacitance element 1002 is connected between the drain of the light-emitting control transistor 1001 and Vdd 205. The second capacitance element 1002 may be any of a parasitic capacitance, a capacitance between the gate and channel of a MOS, an MIM (Metal-Insulator-Metal) structure, and an MOM (Metal-Oxide-Metal) structure.

[0081] The emission control transistor 1001 responds to an emission control signal applied to its gate from the vertical scanning circuit 104 via the second scanning line 901 and turns on, thereby allowing current to be supplied from Vdd 205 to the drive transistor 202. This enables the drive transistor 202 to emit light from the organic light emitting element 201. In other words, the emission control transistor 1001 functions as a transistor that controls whether the organic light emitting element 201 emits light. In this way, the switching operation of the emission control transistor 1001 enables so-called duty control, which controls the ratio between the emission period and the non-emission period of the organic light emitting element 201. This duty control reduces afterimage blurring caused by the emission of light by the pixel 102 over one frame period, thereby improving image quality, particularly in moving images.

[0082] Furthermore, due to variations during manufacturing, the threshold value of the drive transistor 202 may differ from pixel to pixel. When the same signal voltage is written to multiple pixels that emit the same light color, the amount of current flowing through the drive transistor 202 differs for each pixel, resulting in variations in the amount of light emitted. Therefore, before writing the signal voltage, a so-called threshold correction operation is performed to maintain a threshold between the gate and source of the drive transistor 202. This threshold correction operation can reduce variations in the amount of current through the drive transistor 202 in each pixel, achieving more uniform light emission.

[0083] In the threshold correction operation, a current is passed through the organic light emitting element 201 via the light emitting control transistor 1001 and the drive transistor 202, and then the light emitting control transistor 1001 is turned off. As a result, a current flows through the organic light emitting element 201 until the voltage between the gate and source of the drive transistor 202 becomes statically stable, and the threshold correction is performed.

[0084] Fig. 11 is a plan view of an example of the circuit shown in Fig. 10. The light-emitting control transistor 1001 is composed of a gate electrode 1101, a source section 1102, and a drain section 302.

[0085] Fig. 12 is a cross-sectional view taken along line CC' in the plan view shown in Fig. 11. The source and drain of the light-emission control transistor 1001 are formed of low-concentration P-type diffusion layers 1201 and 1202, respectively, and their peak concentrations are lower than the peak concentrations of the P-type diffusion layers 410 and 411 of the peripheral circuit transistor 308. Furthermore, high-concentration N-type diffusion layers 1203 and 1204, which are halo-implanted layers, are adjacent to the low-concentration P-type diffusion layers 1201 and 1202, respectively, and a lower-concentration N-type well layer 407 is disposed between the high-concentration N-type diffusion layers 1203 and 1204. In this embodiment, the peak concentration of the high-concentration N-type diffusion layers 1203 and 1204 that constitute the light-emission control transistor 1001 is higher than the peak concentration of the N-type diffusion layers 803 and 804 that constitute the peripheral circuit transistor 308. However, this is not limiting, and the concentration of the halo injection layer may be adjusted appropriately depending on the amount of leakage current, and the magnitude relationship may be reversed. The concentration of the halo injection layer of the light-emission control transistor 1001 may be the same as that of the write transistor 203. Here, the term "same" in this specification includes "substantially the same" taking into account manufacturing errors.

[0086] In this embodiment, a configuration is shown in which the light-emitting control transistor 1001 is arranged between the power source 205 that supplies current to the light-emitting element and the driving transistor 202, and a configuration in which a halo injection layer is provided. However, the present invention is not limited to this, and the light-emitting control transistor 1001 may have a region in which no silicide layer is provided between at least one of the source, drain, and gate electrode and the insulating layer, or at least one of the source, drain, and gate electrode of the light-emitting control transistor 1001 may not have a salicide structure.

[0087] Furthermore, the impurity concentration in the source diffusion region of the light-emitting control transistor 1001 and the impurity concentration in the drain diffusion region may have a concentration distribution with a concentration peak in a fourth direction from the source to the drain, and the impurity concentration in the source diffusion region of the transistor 308 of the peripheral circuit may have a concentration distribution with a concentration peak in a second direction from the source to the drain, and the peak impurity concentration in the source or drain diffusion region of the light-emitting control transistor 1001 may be smaller than the peak impurity concentration in the source or drain diffusion region of the transistor 308 of the peripheral circuit.

[0088] With this configuration, during threshold correction, the leakage current flowing from the source to the drain of the light-emitting control transistor 1001 and into the first capacitance element 204 can be reduced, and fluctuations in the threshold voltage held by the first capacitance element 204 can be reduced.

[0089] [Embodiment 7] The light-emitting device according to this embodiment includes a reset transistor disposed between the drain or source terminal of the driving transistor 202 connected to the light-emitting element 201 and a terminal at a lower potential than the power supply that supplies current to the light-emitting element 201. More specifically, the light-emitting device includes a reset transistor that connects the anode of the light-emitting element 201 to a third power supply terminal 1302 (hereinafter referred to as Vres) to reset the light-emitting element 201. The reset transistor is also referred to as a fifth transistor following the light-emitting control transistor 1001. The third power supply terminal 1302 may be a power supply at a lower potential than the power supply that supplies current to the light-emitting element 201. The third power supply terminal 1302 according to this embodiment may have a potential that allows the reset transistor to reset the light-emitting element, and is not limited to this embodiment. The following description will focus on configurations that differ from the other embodiments.

[0090] 13 is a schematic diagram showing an example of a light-emitting device according to this embodiment. In the pixel array section 103, a third scanning line 1301 is arranged for each pixel row along the row direction. The third scanning line 1301 is connected to the output terminal of the corresponding row in the vertical scanning circuit 104, and supplies a reset signal to each pixel 102.

[0091] FIG. 14 is a circuit diagram showing an example of a pixel circuit included in the light-emitting device of FIG. 13. One of the source and drain (here, the source) of a reset transistor 1401 is connected to one of the source and drain (here, the drain) of a drive transistor 202. The other of the reset transistor 1401 is connected to Vres 1402. The gate of the reset transistor 1401 is connected to a third scan line 1301. By turning on the reset transistor 1401, the anode of the organic light-emitting element 201 is connected to Vres 1402, and the luminance of the organic light-emitting element 201 can be set to the black level. This makes it possible to realize a high-contrast light-emitting device. Furthermore, during the light-emitting period, the reset transistor 1401 is in the off state.

[0092] Fig. 15 is a plan view of an example of the circuit shown in Fig. 14. The reset transistor 1401 is composed of a gate electrode 1501, a source 303, and a drain 1502.

[0093] 16 is a cross-sectional view taken along the line DD′ in the plan view of FIG. 15 . The source and drain of the reset transistor 1401 are formed of low-concentration P-type diffusion layers 1601 and 1602, respectively, and their peak concentrations are lower than the peak concentrations of the P-type diffusion layers 410 and 411 of the peripheral circuit transistor 308. Furthermore, high-concentration N-type diffusion layers 1603 and 1604, which are halo-implanted layers, are adjacent to the low-concentration P-type diffusion layers 1601 and 1602, respectively, and a lower-concentration N-type well layer 407 is disposed between the high-concentration N-type diffusion layers 1603 and 1604. In this embodiment, the peak concentrations of the high-concentration N-type diffusion layers 1603 and 1604 constituting the reset transistor 1401 are higher than the peak concentrations of the N-type diffusion layers 703 and 704 constituting the peripheral circuit transistor 308. However, this is not limiting, and the concentrations of the halo-implanted layers may be adjusted appropriately depending on the amount of leakage current, or the magnitude relationship may be reversed. The concentration of the halo implant layer of the reset transistor 1401 may be the same as that of the halo implant layer of the write transistor 203 .

[0094] The light-emitting device of this embodiment has a reset transistor 1401 arranged between the drain or source terminal of the driving transistor 202 that is connected to the light-emitting element and a terminal at a lower potential than the power supply that supplies current to the light-emitting element 201.

[0095] The reset transistor according to this embodiment may have a configuration in which a silicide layer is not provided between at least one of the source, drain, and gate electrode of the reset transistor and the insulating layer, as in the configurations of the other embodiments. Also, at least one of the source, drain, and gate electrode of the reset transistor may not have a salicide structure.

[0096] In the reset transistor according to this embodiment, the impurity concentrations in the source diffusion region and the drain diffusion region of the reset transistor have concentration distributions with a concentration peak in a fifth direction from the source to the drain, and the impurity concentrations in the source diffusion region and the drain diffusion region of the transistor in the peripheral circuit have concentration distributions with a concentration peak in a second direction from the source to the drain. The peak impurity concentration in the source or drain diffusion region of the reset transistor may be smaller than the peak impurity concentration in the source or drain diffusion region of the transistor in the peripheral circuit. Here, the peak concentration refers to the concentration at the concentration peak.

[0097] This configuration makes it possible to reduce the leakage current that flows from the source to the drain of the reset transistor 1301. As a result, during the light emission period, it is possible to reduce the leakage current that flows from the drive transistor 202 to Vres 1402 via the reset transistor 1401, and it is possible to reduce the current consumption of the pixel 102.

[0098] [Embodiment 8] In the light emitting device according to this embodiment, the transistors constituting the inverter circuit 1701 in the vertical scanning circuit 104 have a halo structure. The following description will focus on the configuration that differs from other embodiments.

[0099] Fig. 17 is a circuit diagram of an example of an inverter circuit 1701 in the vertical scanning circuit 104 of the light emitting device of Fig. 13. The drain, source, and gate of a P-type transistor 1702 are connected to the drain of an N-type transistor 1703, a fourth power supply terminal 1704 (hereinafter, Vddd), and the gate of the N-type transistor 1703, respectively.

[0100] The source of the N-type transistor 1703 is connected to a fifth power supply terminal 1705 (hereinafter referred to as Vssd).

[0101] The inverter circuit 1701 has an input terminal 1706 and an output terminal 1707. The input terminal 1706 is connected to the gates of a P-type transistor 1702 and an N-type transistor 1703. The output terminal 1707 is connected to the drain of the P-type transistor 1702 and the drain of the N-type transistor 1703, and further to any one of the first scanning line 106, the second scanning line 901, and the third scanning line 1301.

[0102] Fig. 18 is a plan view of an example of the circuit shown in Fig. 17. The P-type transistor 1702 is composed of a gate electrode 1801, a source 1802, and a drain 1803.

[0103] The N-type transistor 1703 is composed of a gate electrode 1804 , a source 1805 , and a drain 1806 .

[0104] Fig. 19 is a cross-sectional view taken along the line E-E' in the plan view shown in Fig. 18. The source and drain of P-type transistor 1702 are formed by P-type diffusion layers 1901 and 1902, respectively. N-type diffusion layers 1903 and 1904, which are halo-implanted layers, are adjacent to P-type diffusion layers 1901 and 1902, respectively, and a lightly doped N-type well layer 407 is disposed between N-type diffusion layers 1903 and 1904.

[0105] The drain and source of the N-type peripheral circuit transistor 1703 are respectively formed by N-type diffusion layers 1905 and 1906. P-type diffusion layers 1907 and 1908, which are halo-implanted layers, are adjacent to the N-type diffusion layers 1905 and 1906, respectively, and a lightly doped P-type well layer 1809 is disposed between the P-type diffusion layers 1907 and 1908.

[0106] With this configuration, it is possible to reduce the leakage current flowing from Vddd 1604 to Vssd 1705 via the P-type peripheral circuit transistor 1702 and the N-type peripheral circuit transistor 1703, thereby reducing the current consumption in the vertical scanning circuit 104.

[0107] [Other embodiments] 20 is a schematic diagram showing an example of a display device according to this embodiment. The display device 2000 may have a touch panel 2003, a display panel 2005, a frame 2006, a circuit board 2007, and a battery 2008 between an upper cover 2001 and a lower cover 2009. The touch panel 2003 and the display panel 2005 are connected by flexible printed circuits FPCs 2002 and 2004. Transistors are printed on the circuit board 2007. The battery 2008 may not be provided if the display device is not a portable device, and may be provided in a different position even if the display device is a portable device.

[0108] The display device according to this embodiment may have color filters having red, green, and blue colors, which may be arranged in a delta arrangement.

[0109] The display device according to the present embodiment may be used as a display unit of a mobile terminal. In this case, the display device may have both a display function and an operation function. Examples of the mobile terminal include a mobile phone such as a smartphone, a tablet, and a head-mounted display.

[0110] The display device according to this embodiment may be used as a display unit of an imaging device having an optical unit with a plurality of lenses and an imaging element that receives light that has passed through the optical unit. The imaging device may have a display unit that displays information acquired by the imaging element. The display unit may be a display unit exposed to the outside of the imaging device or a display unit disposed within a viewfinder. The imaging device may be a digital camera or a digital video camera.

[0111] 21(a) is a schematic diagram showing an example of an imaging device according to this embodiment. The imaging device 2100 may have a viewfinder 2101, a rear display 2102, an operation unit 2103, and a housing 2104. The viewfinder 2101 may have a display device according to this embodiment. In this case, the display device may display not only an image to be captured, but also environmental information, imaging instructions, and the like. The environmental information may include the intensity of external light, the direction of external light, the speed at which the subject is moving, the possibility that the subject will be blocked by an obstruction, and the like.

[0112] Since the optimum timing for capturing an image is very short, it is better to display information as soon as possible. Therefore, it is preferable to use a display device using the organic light-emitting element of the present invention. This is because the organic light-emitting element has a fast response speed. A display device using an organic light-emitting element can be used more preferably than a liquid crystal display device, which requires a high display speed.

[0113] The imaging device 2100 has an optical section (not shown). The optical section has multiple lenses, which form an image on an imaging element housed in a housing 2104. The focus of the multiple lenses can be adjusted by adjusting their relative positions. This operation can also be performed automatically. The imaging device may also be called a photoelectric conversion device. Rather than sequentially capturing images, the photoelectric conversion device can include an imaging method that detects the difference from the previous image, or a method of cutting out an image from a constantly recorded image, etc.

[0114] FIG. 21(b) is a schematic diagram illustrating an example of an electronic device according to this embodiment. The electronic device 2200 has a display unit 2201, an operation unit 2202, and a housing 2203. The housing 2203 may include a circuit, a printed circuit board having the circuit, a battery, and a communication unit. The operation unit 2202 may be a button or a touch panel type reaction unit. The operation unit may be a biometric recognition unit that recognizes a fingerprint to unlock the device, etc. The communication unit is a communication unit that communicates with the outside world and may be wired or wireless. An electronic device having a communication unit may also be called a communication device. The electronic device may further have a camera function by including a lens and an image sensor. An image captured by the camera function is displayed on the display unit. Examples of the electronic device include a smartphone, a laptop computer, etc.

[0115] Fig. 22 is a schematic diagram showing an example of a display device according to this embodiment. Fig. 22(a) shows a display device such as a television monitor or a PC monitor. A display device 2300 has a frame 2301 and a display unit 2302. The light-emitting device according to this embodiment may be used in the display unit 2302.

[0116] It has a frame 2301 and a base 2303 that supports a display unit 2302. The base 2303 is not limited to the form shown in Fig. 22(a). The bottom side of the frame 1301 may also serve as the base.

[0117] The frame 2301 and the display unit 2302 may be curved. The radius of curvature may be 5000 mm or more and 6000 mm or less.

[0118] FIG. 22(b) is a schematic diagram illustrating another example of a display device according to this embodiment. The display device 2310 in FIG. 22(b) is configured to be bendable, and is a so-called foldable display device. The display device 2310 has a first display unit 2311, a second display unit 2312, a housing 2313, and a bending point 2314. The first display unit 2311 and the second display unit 2312 may include a light-emitting device according to this embodiment. The first display unit 2311 and the second display unit 2312 may be a single, seamless display unit. The first display unit 2311 and the second display unit 2312 can be separated by the bending point. The first display unit 2311 and the second display unit 2312 may each display different images, or the first and second display units may display a single image.

[0119] 23 is a schematic diagram showing an example of a wearable device according to this embodiment. The wearable device can be applied to systems that can be worn as a wearable device, such as smart glasses, HMDs, and smart contact lenses. An image capturing and displaying device used in such an application example includes an image capturing device capable of photoelectrically converting visible light and a displaying device capable of emitting visible light.

[0120] 23(a) shows glasses 1600 (smart glasses) according to one application example. An imaging device 2602 such as a CMOS sensor or SPAD is provided on the front side of a lens 2601 of the glasses 2600. In addition, a display device according to any of the above-described embodiments is provided on the back side of the lens 2601.

[0121] The glasses 2600 further include a control device 2603. The control device 2603 functions as a power source that supplies power to the image capture device 2602 and the display device according to each embodiment. The control device 2603 also controls the operations of the image capture device 2602 and the display device. The lens 2601 is formed with an optical system for focusing light onto the image capture device 2602.

[0122] FIG. 23(b) shows glasses 2610 (smart glasses) according to one application example. The glasses 2610 include a control device 2612. The control device 2612 is equipped with an imaging device corresponding to the imaging device 2602 and a display device. A lens 2611 is formed with an optical system for projecting light emitted by the display device in the control device 2612, and an image is projected onto the lens 2611. The control device 2612 functions as a power source for supplying power to the imaging device and the display device, and also controls the operation of the imaging device and the display device. The control device includes an image control unit, which transmits an image control signal to a peripheral circuit of the light-emitting device. The control device may also include a gaze detection unit that detects the gaze of the wearer. Infrared light may be used to detect the gaze. The infrared light emitter emits infrared light toward the eyeball of a user gazing at a displayed image. An imaging unit having a light-receiving element detects the emitted infrared light reflected from the eyeball, thereby obtaining an image of the eyeball. By providing a reduction means for reducing the amount of light from the infrared light emitting section to the display section in a plan view, degradation of image quality is reduced.

[0123] The gaze of the user relative to the displayed image is detected from an image of the eyeball obtained by capturing infrared light. Any known method can be used for gaze detection using an image of the eyeball. One example is a gaze detection method based on the Purkinje image formed by reflection of irradiated light on the cornea.

[0124] More specifically, gaze detection processing is performed based on the pupil-corneal reflex method, which calculates a gaze vector representing the direction (rotation angle) of the eyeball based on the pupil image and Purkinje image included in the captured image of the eyeball, thereby detecting the user's gaze.

[0125] A display device according to an embodiment of the present invention may have an imaging device having a light receiving element, and may control the image displayed on the display device based on information about the user's line of sight from the imaging device.

[0126] Specifically, the display device determines a first display area on which the user gazes and a second display area other than the first display area based on the line-of-sight information. The first display area and the second display area may be determined by a control device of the display device, or may be determined by an external control device and received. In the display area of the display device, the display resolution of the first display area may be controlled to be higher than the display resolution of the second display area. In other words, the resolution of the second display area may be lower than the resolution of the first display area.

[0127] Furthermore, the first display area and the second display area of the display area may be determined based on gaze information. Note that AI may be used to determine the first display area and areas with high priority. The AI may be a model configured to estimate the gaze angle and the distance to an object in the gaze from an image of the eyeball, using an image of the eyeball and the actual gaze direction of the eyeball in the image as training data. The AI program may be included in the display device, the imaging device, or an external device. If included in an external device, it is transmitted to the display device via communication.

[0128] When display control is performed based on visual recognition detection, the smart glasses can be preferably applied to smart glasses that further include an imaging device for capturing images of the outside world. The smart glasses can display captured external information in real time.

[0129] As described above, according to the present invention, it is possible to provide a light emitting device in which the leakage current of the light emitting element is reduced.

[0130] As described using the above embodiments, the present invention includes the following configurations.

[0131] [Configuration 1] A light-emitting element; a first transistor and a second transistor disposed on a first surface of a silicon substrate; an insulating layer disposed between the light emitting element and the first surface; a third transistor provided in a peripheral circuit that supplies an image signal to the first transistor, one of the source and drain of the first transistor is connected to the gate electrode of the second transistor; one of a source and a drain of the second transistor is connected to the light emitting element; a silicide layer is provided in at least one of a source, a drain, and a gate electrode of the third transistor, and the silicide layer is in contact with the insulating layer; a light-emitting device having a region where no silicide layer is provided between at least one of the source, drain and gate electrode of the first transistor or the second transistor and the insulating layer;

[0132] [Configuration 2] A light-emitting element; a first transistor and a second transistor disposed on a first surface of a silicon substrate; a third transistor provided in a peripheral circuit that supplies an image signal to the first transistor, one of the source and drain of the first transistor is connected to the gate electrode of the second transistor; one of a source and a drain of the second transistor is connected to the light emitting element; At least one of a source, a drain, and a gate electrode of the third transistor has a salicide structure, A light emitting device, wherein at least one of the source, drain and gate electrode of the first transistor or the second transistor does not have a salicide structure.

[0133] [Configuration 3] The light-emitting device according to configuration 1, characterized in that in a cross section perpendicular to the first surface, there is a region between at least one of the source, drain, and gate electrode of the second transistor and the insulating layer where no silicide layer is provided.

[0134] [Configuration 4] The light-emitting device according to structure 3, characterized in that in a cross section perpendicular to the first surface, there is a region in which no silicide layer is provided between at least one of the source, drain, and gate electrode of the first transistor and the insulating layer.

[0135] [Configuration 5] 3. The light emitting device according to configuration 2, wherein at least one of the source, drain, and gate electrode of the second transistor does not have a salicide structure.

[0136] [Configuration 6] 6. The light-emitting device according to configuration 5, wherein at least one of the source, drain, and gate electrode of the first transistor does not have a salicide structure.

[0137] [Configuration 7] a fourth transistor disposed between a power source that supplies a current to the light emitting element and the second transistor; The light-emitting device according to configuration 1, characterized in that in a cross section perpendicular to the first surface, there is a region where no silicide layer is provided between at least one of the source, drain, and gate electrode of the fourth transistor and the insulating layer.

[0138] [Configuration 8] a fourth transistor disposed between a power source that supplies a current to the light emitting element and the second transistor; 3. The light emitting device according to configuration 2, wherein at least one of the source, drain, and gate electrode of the fourth transistor does not have a salicide structure.

[0139] [Configuration 9] a fifth transistor disposed between a terminal of the drain or the source of the second transistor that is connected to the light emitting element and a terminal that has a lower potential than a power supply that supplies a current to the light emitting element; The light-emitting device according to configuration 1, characterized in that in a cross section perpendicular to the first surface, there is a region where no silicide layer is provided between at least one of the source, drain, and gate electrode of the fifth transistor and the insulating layer.

[0140] [Configuration 10] a fifth transistor disposed between a terminal of the drain or the source of the second transistor that is connected to the light emitting element and a terminal that has a lower potential than a power supply that supplies a current to the light emitting element; 3. The light emitting device according to configuration 2, wherein at least one of the source, drain, and gate electrode of the fifth transistor does not have a salicide structure.

[0141] [Configuration 11] an impurity concentration in the diffusion region of the source of the second transistor and an impurity concentration in the diffusion region of the drain of the second transistor have a concentration distribution having a peak concentration in a first direction from the source to the drain; an impurity concentration in the diffusion region of the source of the third transistor and an impurity concentration in the diffusion region of the drain of the third transistor have a concentration distribution having a peak concentration in a second direction from the source to the drain; 11. The light-emitting device according to any one of structures 1 to 10, wherein a peak concentration of impurities in the diffusion region of the source or the drain of the second transistor is lower than a peak concentration of impurities in the diffusion region of the source or the drain of the third transistor.

[0142] [Configuration 12] an impurity concentration in the diffusion region of the source of the first transistor and an impurity concentration in the diffusion region of the drain of the first transistor have a concentration distribution having a peak concentration in a third direction from the source to the drain; an impurity concentration in the diffusion region of the source of the third transistor and an impurity concentration in the diffusion region of the drain of the third transistor have a concentration distribution having a peak concentration in a second direction from the source to the drain; 12. The light-emitting device according to any one of structures 1 to 11, wherein a peak impurity concentration in the diffusion region of the source or the drain of the first transistor is lower than a peak impurity concentration in the diffusion region of the source or the drain of the third transistor.

[0143] [Configuration 13] a fourth transistor disposed between a power source that supplies a current to the light emitting element and the second transistor; the fourth transistor has a source, a drain, and a gate electrode; an impurity concentration in the diffusion region of the source of the fourth transistor and an impurity concentration in the diffusion region of the drain of the fourth transistor have a concentration distribution having a peak concentration in a fourth direction from the source to the drain; an impurity concentration in the diffusion region of the source of the third transistor and an impurity concentration in the diffusion region of the drain of the third transistor have a concentration distribution having a peak concentration in a second direction from the source to the drain; 13. The light-emitting device according to any one of structures 1 to 12, wherein a peak impurity concentration in the diffusion region of the source or the drain of the fourth transistor is lower than a peak impurity concentration in the diffusion region of the source or the drain of the third transistor.

[0144] [Configuration 14] a fifth transistor disposed between a terminal of the drain or the source of the second transistor that is connected to the light emitting element and a terminal that has a lower potential than a power supply that supplies a current to the light emitting element; an impurity concentration in the diffusion region of the source of the fifth transistor and an impurity concentration in the diffusion region of the drain of the fifth transistor have a concentration distribution having a peak concentration in a fifth direction from the source to the drain; an impurity concentration in the diffusion region of the source of the third transistor and an impurity concentration in the diffusion region of the drain of the third transistor have a concentration distribution having a peak concentration in a second direction from the source to the drain; 14. The light-emitting device according to any one of structures 1 to 13, wherein a peak impurity concentration in the diffusion region of the source or the drain of the fifth transistor is lower than a peak impurity concentration in the diffusion region of the source or the drain of the third transistor.

[0145] [Configuration 15] 15. The light-emitting device according to any one of claims 1 to 14, wherein the first transistor has a halo injection layer in the diffusion region of the source and the drain, and the halo injection layer has a polarity opposite to that of the diffusion region.

[0146] [Configuration 16] the third transistor has a halo implantation layer in the source and drain diffusion regions, the halo implantation layer having a polarity opposite to that of the diffusion regions; 16. The light emitting device according to configuration 15, wherein the peak impurity concentration in the halo injection layer of the first transistor is different from the peak impurity concentration in the halo injection layer of the third transistor.

[0147] [Configuration 17] a fourth transistor disposed between a power source that supplies a current to the light emitting element and the second transistor; the fourth transistor has a halo implantation layer in a source and drain diffusion region, the halo implantation layer having a polarity opposite to that of the diffusion region; 17. The light-emitting device according to any one of configurations 1 to 16, wherein the peak concentration of the impurity concentration in the halo injection layer of the third transistor is different from the peak concentration of the impurity concentration in the halo injection layer of the fourth transistor.

[0148] [Configuration 18] a fifth transistor disposed between a terminal of the drain or the source of the second transistor that is connected to the light emitting element and a terminal that has a lower potential than a power supply that supplies a current to the light emitting element; the fifth transistor has a halo implantation layer in the source and drain diffusion regions, the halo implantation layer having a polarity opposite to that of the diffusion regions; 18. The light-emitting device according to any one of configurations 1 to 17, wherein the peak concentration of the impurity concentration in the halo injection layer of the third transistor is different from the peak concentration of the impurity concentration in the halo injection layer of the fifth transistor.

[0149] [Configuration 19] 19. The light emitting device according to any one of configurations 1 to 18, wherein the peripheral circuit is provided on the first surface of the silicon substrate.

[0150] [Configuration 20] 20. The light emitting device according to any one of configurations 1 to 19, wherein the peripheral circuit is disposed on a second silicon substrate different from the silicon substrate.

[0151] [Configuration 21] 21. The display device according to any one of configurations 1 to 20, further comprising an image control unit that transmits an image control signal to the peripheral circuit, and the light-emitting element emits light in response to the image control signal.

[0152] [Configuration 22] an optical unit having a plurality of lenses, an image pickup element that receives light that has passed through the optical unit, and a display unit that displays an image picked up by the image pickup element; 22. A photoelectric conversion device, wherein the display unit is the display device according to configuration 21.

[0153] [Configuration 23] 22. An electronic device comprising: a display device according to claim 21; a housing in which the display device is provided; and a communication unit provided in the housing for communicating with an external device.

[0154] [Configuration 24] A light-emitting element; a first transistor and a second transistor disposed on a first surface of a silicon substrate; a third transistor provided in a peripheral circuit that supplies an image signal to the first transistor; one of the source and drain of the first transistor is connected to the gate electrode of the second transistor; A method for manufacturing a light emitting element, wherein one of a source and a drain of the second transistor is connected to the light emitting element, providing an insulating layer over the source, drain, and gate electrode of the second transistor, the insulating layer having openings corresponding to at least one of the source, drain, and gate electrode of the third transistor; a step of forming a metal layer covering the second transistor and the third transistor after the step of providing an insulating layer, and a step of forming a silicide layer on at least one of the source, the drain, and the gate electrode of the third transistor.

[0155] [Configuration 25] 25. A method for manufacturing a light-emitting device according to claim 24, further comprising the steps of: after forming the silicide layer, providing an insulating layer on the silicide layer; forming a first opening in the insulating layer; and forming a contact wiring in the first opening.

[0156] [Configuration 26] 26. The method for manufacturing a light-emitting device according to claim 25, wherein, in a plan view relative to the first surface, the first opening overlaps with a region in which the silicide layer is formed in the third transistor.

[0157] [Configuration 27] 27. A method for manufacturing a light-emitting device according to any one of structures 24 to 26, comprising the steps of providing an insulating layer covering the first transistor or the second transistor while no silicide layer is formed on any of the source, drain, and gate electrode of the first transistor or the second transistor, forming a second opening in the insulating layer, and forming a contact wiring in the second opening.

[0158] [Configuration 28] 28. The method for manufacturing a light-emitting device according to claim 27, wherein, in a plan view relative to the first surface, the second opening overlaps with a region in which the silicide layer is formed in the first transistor or the second transistor. [Explanation of symbols]

[0159] 201 Light-emitting element 202 Drive transistor 203 Write transistor 204 first capacitance element 205 First power supply terminal Vdd 206 Second power supply terminal Vss 301 Gate electrode of drive transistor 302 Source part of drive transistor 303 Drain part of drive transistor 304 Gate electrode of write transistor 305 Source part of write transistor 306 Drain part of write transistor 307 Contact electrode 308 Peripheral Circuit Transistor 309 Gate electrodes of peripheral circuit transistors 310 Source part of peripheral circuit transistor 311 Drain part of peripheral circuit transistor 401, 402, 403, 404 P-type diffusion layer 405 Semiconductor Compound Layer 406 Insulating film 407 N-type well layer 408 P type board 409 Insulator Separator 410, 411 P-type diffusion layer

Claims

1. A light-emitting element; a first transistor and a second transistor disposed on a first surface of a silicon substrate; an insulating layer disposed between the light emitting element and the first surface; a third transistor provided in a peripheral circuit that supplies an image signal to the first transistor, one of the source and drain of the first transistor is connected to the gate electrode of the second transistor; one of a source and a drain of the second transistor is connected to the light emitting element; a silicide layer is provided in at least one of a source, a drain, and a gate electrode of the third transistor, and the silicide layer is in contact with the insulating layer; a region where no silicide layer is provided between at least one of the source, drain and gate electrode of the first transistor or the second transistor and the insulating layer;

2. A light-emitting element; a first transistor and a second transistor disposed on a first surface of a silicon substrate; a third transistor provided in a peripheral circuit that supplies an image signal to the first transistor, one of the source and drain of the first transistor is connected to the gate electrode of the second transistor; one of a source and a drain of the second transistor is connected to the light emitting element; At least one of a source, a drain, and a gate electrode of the third transistor has a salicide structure, A light emitting device, wherein at least one of the source, drain and gate electrode of the first transistor or the second transistor does not have a salicide structure.

3. 2. The light-emitting device according to claim 1, wherein in a cross section perpendicular to the first surface, there is a region where no silicide layer is provided between at least one of the source, drain, and gate electrode of the second transistor and the insulating layer.

4. 4. The light-emitting device according to claim 3, wherein in a cross section perpendicular to the first surface, there is a region in which no silicide layer is provided between at least one of the source, drain, and gate electrode of the first transistor and the insulating layer.

5. 3. The light emitting device according to claim 2, wherein at least one of the source, drain and gate electrode of the second transistor does not have a salicide structure.

6. 6. The light emitting device according to claim 5, wherein at least one of the source, drain and gate electrode of the first transistor does not have a salicide structure.

7. a fourth transistor disposed between a power source that supplies a current to the light emitting element and the second transistor; 2. The light-emitting device according to claim 1, wherein in a cross section perpendicular to the first surface, there is a region where no silicide layer is provided between at least one of the source, drain, and gate electrode of the fourth transistor and the insulating layer.

8. a fourth transistor disposed between a power source that supplies a current to the light emitting element and the second transistor; 3. The light emitting device according to claim 2, wherein at least one of the source, drain and gate electrode of the fourth transistor does not have a salicide structure.

9. a fifth transistor disposed between a terminal of the drain or the source of the second transistor that is connected to the light emitting element and a terminal that has a lower potential than a power supply that supplies a current to the light emitting element; 2. The light-emitting device according to claim 1, wherein in a cross section perpendicular to the first surface, there is a region where no silicide layer is provided between at least one of the source, drain, and gate electrode of the fifth transistor and the insulating layer.

10. a fifth transistor disposed between a terminal of the drain or the source of the second transistor that is connected to the light emitting element and a terminal that has a lower potential than a power supply that supplies a current to the light emitting element; 3. The light emitting device according to claim 2, wherein at least one of the source, drain and gate electrode of the fifth transistor does not have a salicide structure.

11. an impurity concentration in the diffusion region of the source of the second transistor and an impurity concentration in the diffusion region of the drain of the second transistor have a concentration distribution having a peak concentration in a first direction from the source to the drain; an impurity concentration in the diffusion region of the source of the third transistor and an impurity concentration in the diffusion region of the drain of the third transistor have a concentration distribution having a peak concentration in a second direction from the source to the drain; 11. The light-emitting device according to claim 1, wherein a peak concentration of impurities in the diffusion region of the source or the drain of the second transistor is lower than a peak concentration of impurities in the diffusion region of the source or the drain of the third transistor.

12. an impurity concentration in the diffusion region of the source of the first transistor and an impurity concentration in the diffusion region of the drain of the first transistor have a concentration distribution having a peak concentration in a third direction from the source to the drain; an impurity concentration in the diffusion region of the source of the third transistor and an impurity concentration in the diffusion region of the drain of the third transistor have a concentration distribution having a peak concentration in a second direction from the source to the drain; 11. The light-emitting device according to claim 1, wherein a peak impurity concentration in the diffusion region of the source or the drain of the first transistor is lower than a peak impurity concentration in the diffusion region of the source or the drain of the third transistor.

13. a fourth transistor disposed between a power source that supplies a current to the light emitting element and the second transistor; the fourth transistor has a source, a drain, and a gate electrode; an impurity concentration in the diffusion region of the source of the fourth transistor and an impurity concentration in the diffusion region of the drain of the fourth transistor have a concentration distribution having a peak concentration in a fourth direction from the source to the drain; an impurity concentration in the diffusion region of the source of the third transistor and an impurity concentration in the diffusion region of the drain of the third transistor have a concentration distribution having a peak concentration in a second direction from the source to the drain; 11. The light-emitting device according to claim 1, wherein a peak impurity concentration in the diffusion region of the source or the drain of the fourth transistor is lower than a peak impurity concentration in the diffusion region of the source or the drain of the third transistor.

14. a fifth transistor disposed between a terminal of the drain or the source of the second transistor that is connected to the light emitting element and a terminal that has a lower potential than a power supply that supplies a current to the light emitting element; an impurity concentration in the diffusion region of the source of the fifth transistor and an impurity concentration in the diffusion region of the drain of the fifth transistor have a concentration distribution having a peak concentration in a fifth direction from the source to the drain; an impurity concentration in the diffusion region of the source of the third transistor and an impurity concentration in the diffusion region of the drain of the third transistor have a concentration distribution having a peak concentration in a second direction from the source to the drain; 11. The light-emitting device according to claim 1, wherein a peak impurity concentration in the diffusion region of the source or the drain of the fifth transistor is lower than a peak impurity concentration in the diffusion region of the source or the drain of the third transistor.

15. 11. The light-emitting device according to claim 1, wherein the first transistor has a halo injection layer in the source and drain diffusion regions, the halo injection layer having a polarity opposite to that of the diffusion regions.

16. the third transistor has a halo implantation layer in the source and drain diffusion regions, the halo implantation layer having a polarity opposite to that of the diffusion regions; 16. The light emitting device according to claim 15, wherein a peak concentration of the impurity concentration in the halo injection layer of the first transistor is different from a peak concentration of the impurity concentration in the halo injection layer of the third transistor.

17. a fourth transistor disposed between a power source that supplies a current to the light emitting element and the second transistor; the fourth transistor has a halo implant layer in a source and drain diffusion region, the halo implant layer having a polarity opposite to that of the diffusion region; 11. The light emitting device according to claim 1, wherein a peak concentration of impurity concentration in the halo injection layer of the third transistor is different from a peak concentration of impurity concentration in the halo injection layer of the fourth transistor.

18. a fifth transistor disposed between a terminal of the drain or the source of the second transistor that is connected to the light emitting element and a terminal that has a lower potential than a power supply that supplies a current to the light emitting element; the fifth transistor has a halo implantation layer in the source and drain diffusion regions, the halo implantation layer having a polarity opposite to that of the diffusion regions; 11. The light emitting device according to claim 1, wherein a peak concentration of impurity concentration in the halo injection layer of the third transistor is different from a peak concentration of impurity concentration in the halo injection layer of the fifth transistor.

19. 11. The light emitting device according to claim 1, wherein the peripheral circuit is provided on the first surface of the silicon substrate.

20. 11. The light emitting device according to claim 1, wherein the peripheral circuit is disposed on a second silicon substrate different from the silicon substrate.

21. 11. The display device according to claim 1, further comprising an image control unit that transmits an image control signal to the peripheral circuit, and the light-emitting element emits light in response to the image control signal.

22. an optical unit having a plurality of lenses, an image pickup element that receives light that has passed through the optical unit, and a display unit that displays an image picked up by the image pickup element; 22. A photoelectric conversion device, wherein the display unit is the display device according to claim 21.

23. 22. An electronic device comprising: the display device according to claim 21; a housing in which the display device is provided; and a communication section provided in the housing for communicating with an external device.

24. A light-emitting element; a first transistor and a second transistor disposed on a first surface of a silicon substrate; a third transistor provided in a peripheral circuit that supplies an image signal to the first transistor; one of the source and drain of the first transistor is connected to the gate electrode of the second transistor; A method for manufacturing a light emitting element, wherein one of a source and a drain of the second transistor is connected to the light emitting element, providing an insulating layer over the source, drain, and gate electrode of the second transistor, the insulating layer having openings corresponding to at least one of the source, drain, and gate electrode of the third transistor; a step of forming a metal layer covering the second transistor and the third transistor after the step of providing an insulating layer, and a step of forming a silicide layer on at least one of the source, the drain, and the gate electrode of the third transistor.

25. 25. The method for manufacturing a light-emitting device according to claim 24, further comprising the steps of: after forming the silicide layer, providing an insulating layer on the silicide layer; forming a first opening in the insulating layer; and forming a contact wiring in the first opening.

26. 26. The method for manufacturing a light-emitting device according to claim 25, wherein, in a plan view relative to the first surface, the first opening overlaps with a region in which the silicide layer is formed in the third transistor.

27. 25. The method for manufacturing a light-emitting device according to claim 24, further comprising the steps of: providing an insulating layer covering the first transistor or the second transistor in a state in which no silicide layer is formed on any of the source, drain, and gate electrode of the first transistor or the second transistor; forming a second opening in the insulating layer; and forming a contact wiring in the second opening.

28. 28. The method for manufacturing a light-emitting device according to claim 27, wherein, in a plan view relative to the first surface, the second opening overlaps with a region in which the silicide layer is formed in the first transistor or the second transistor.

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