Light-emitting device

Abstract

To provide a light-emitting device in which a leakage current of pixels is reduced.SOLUTION: A light-emitting device includes: a light-emitting element; a first transistor and a second transistor provided on a first surface of a silicon substrate; and a third transistor provided in a peripheral circuit that supplies an image signal to the first transistor. Either a source or a drain of the first transistor is connected to a gate electrode of the second transistor. Either a source or a drain of the second transistor is connected to the light-emitting element. The first transistor has Halo implantation layers in diffusion regions of the source and the drain. The Halo implantation layers have a polarity opposite to that of the diffusion regions.SELECTED DRAWING: Figure 4

Description

[Technical Field]

[0001] The present invention relates to a light-emitting device, for example, a light-emitting device having a light-emitting element, a display device having the same, and an electronic device. [Background technology]

[0002] In recent years, display devices have become known that have arrays of light-emitting elements that emit light at a brightness that corresponds to the current flowing through the elements, and organic EL elements are used as the light-emitting elements. The applications of these display devices have expanded significantly, and higher definition and functionality are required depending on the application.

[0003] Patent Document 1 describes a display device having a silicide layer in order to reduce electrical resistance in the source and drain of a drive transistor in a drive circuit for an organic light-emitting element. [Prior art documents] [Patent documents]

[0004] [Patent Document 1] Japanese Patent Publication No. 2020-71323 Summary of the Invention [Problem to be solved by the invention]

[0005] The transistor described in Patent Document 1 has a silicide layer disposed in the source and drain. This silicide layer can reduce the resistance of the transistor. However, providing a silicide layer can also cause leakage current and other degradation in the characteristics of the light-emitting element.

[0006] SUMMARY OF THE INVENTION It is therefore an object of the present invention to provide a light emitting device with reduced leakage current. [Means for solving the problem]

[0007] The present invention provides a light-emitting device comprising: a light-emitting element; a first transistor and a second transistor provided on a first surface of a silicon substrate; and a third transistor provided in a peripheral circuit that supplies an image signal to the first transistor, wherein either a source or a drain of the first transistor is connected to a gate electrode of the second transistor, and either a source or a drain of the second transistor is connected to the light-emitting element; The first transistor has a halo injection layer in the diffusion region of the source and the drain, and the halo injection layer has a polarity opposite to that of the diffusion region. [Effects of the Invention]

[0008] According to the present invention, it is possible to provide a light emitting element with reduced leakage current. [Brief explanation of the drawings]

[0009] [Figure 1] 1 is a schematic diagram of an example of a light emitting device according to an embodiment of the present invention. [Figure 2] 1 is a circuit diagram illustrating an example of a pixel circuit of the light emitting device according to Embodiment 1. FIG. [Figure 3] 1 is a plan view illustrating an example of a circuit of the light emitting device according to the first embodiment. [Figure 4] 1 is a cross-sectional view illustrating an example of a light emitting device according to a first embodiment. [Figure 5] FIG. 10 is a plan view illustrating an example of a peripheral circuit transistor of the light emitting device according to the second embodiment. [Figure 6] FIG. 10 is a cross-sectional view illustrating an example of a peripheral circuit transistor of the light emitting device according to the second embodiment. [Figure 7] FIG. 10 is a schematic diagram illustrating an example of a light emitting device according to a third embodiment. [Figure 8] FIG. 10 is a circuit diagram illustrating an example of a pixel circuit of a light emitting device according to a third embodiment. [Figure 9] FIG. 10 is a plan view illustrating an example of a circuit of a light emitting device according to a third embodiment. [Figure 10]FIG. 10 is a cross-sectional view illustrating an example of a light emitting device according to a third embodiment. [Figure 11] FIG. 10 is a schematic diagram illustrating an example of a light emitting device according to a fourth embodiment. [Figure 12] FIG. 10 is a circuit diagram illustrating an example of a pixel circuit of a light emitting device according to a fourth embodiment. [Figure 13] FIG. 10 is a plan view illustrating an example of a circuit of a light emitting device according to a fourth embodiment. [Figure 14] FIG. 10 is a cross-sectional view illustrating an example of a light emitting device according to a fourth embodiment. [Figure 15] FIG. 10 is a circuit diagram illustrating an example of an inverter circuit of a light emitting device according to a fifth embodiment. [Figure 16] FIG. 10 is a plan view illustrating an example of an inverter circuit of a light emitting device according to a fifth embodiment. [Figure 17] FIG. 10 is a cross-sectional view illustrating an example of an inverter circuit of a light emitting device according to a fifth embodiment. [Figure 18] 1 is a schematic diagram illustrating an example of a display device according to an embodiment of the present invention. [Figure 19] 1A is a schematic diagram illustrating an example of an imaging device according to an embodiment of the present invention, and FIG. 1B is a schematic diagram illustrating an example of an electronic device according to an embodiment of the present invention. [Figure 20] 1(a) and 1(b) are schematic diagrams illustrating an example of a display device according to an embodiment of the present invention. [Figure 21] FIG. 1 is a schematic diagram illustrating an example of a wearable device according to an embodiment of the present invention. DETAILED DESCRIPTION OF THE INVENTION

[0010] A light emitting device according to one embodiment of the present invention includes a light emitting element, a first transistor and a second transistor provided on a first surface of a silicon substrate, and a third transistor provided in a peripheral circuit that supplies an image signal to the first transistor, wherein either a source or a drain of the first transistor is connected to a gate electrode of the second transistor, and either a source or a drain of the second transistor is connected to the light emitting element; The light emitting device is characterized in that the first transistor has a halo injection layer in the diffusion region of the source and the drain, and the halo injection layer has a polarity opposite to that of the diffusion region.

[0011] By providing the halo injection layer in the first transistor, the leakage current of the light emitting device can be reduced.

[0012] Hereinafter, embodiments will be described in detail with reference to the accompanying drawings. Note that the following embodiments do not limit the scope of the invention claimed. Although multiple features are described in the embodiments, not all of these multiple features are necessarily essential to the invention, and multiple features may be combined arbitrarily. Furthermore, in the accompanying drawings, the same reference numerals are used to designate the same or similar components, and redundant explanations will be omitted.

[0013] In the following embodiments, a driving transistor is connected to the anode of the organic light-emitting element, and all the transistors are P-type transistors. However, the light-emitting device of the present invention is not limited to this. The polarity and conductivity type may all be reversed. The transistors may be either P-type or N-type transistors. To change the type, the supplied potential or connection may be changed appropriately according to the conductivity type and polarity.

[0014] In the following embodiments, the peripheral circuits may be provided on the same silicon substrate as the transistors such as the drive transistors, or may be provided on a second silicon substrate different from the silicon substrate.

[0015] In this specification, the light-emitting element may be an organic light-emitting element in which the light-emitting portion is a light-emitting layer containing an organic compound, or an inorganic light-emitting element in which the light-emitting portion is made of an inorganic compound.

[0016] An organic light-emitting element has an organic layer including an emitting layer between an anode and a cathode. In addition to the emitting layer, the organic layer may appropriately have one or more of a hole injection layer, a hole transport layer, an electron injection layer, and an electron transport layer. A display device having an organic light-emitting element is an example of a light-emitting device and is also called an organic light-emitting device. In the following embodiments, examples using an organic light-emitting element will be described.

[0017] [Embodiment 1] 1 is a schematic diagram of an example of a light-emitting device according to this embodiment. The light-emitting device 101 has a pixel array section 103 and a peripheral circuit section arranged around the pixel array section 103. The pixel array section 103 has a plurality of pixels 102 arranged two-dimensionally in a matrix, and each pixel 102 has an organic light-emitting element 201 (shown in FIG. 2).

[0018] The light emitting device 101 has a peripheral circuit section that drives each pixel 102. The peripheral circuit section has, for example, a vertical scanning circuit 104 and a signal output circuit 105. In the pixel array section 103, a first scanning line 106 is arranged for each row of pixels along the row direction. In addition, a signal line 107 is arranged for each column of pixels along the column direction.

[0019] The first scanning line 106 is connected to an output terminal of the corresponding row of the vertical scanning circuit 104. Furthermore, the signal line 107 is connected to an output terminal of the corresponding column of the signal output circuit 105. The vertical scanning circuit 104 supplies the first scanning line 106 with a write control signal that controls the timing of writing a video signal to each pixel 102 in the pixel array section 103. The signal output circuit 105 outputs a luminance signal having a voltage corresponding to luminance information.

[0020] 2 is a circuit diagram showing an example of a pixel circuit included in the light-emitting device 101 of FIG. 1. The pixel 102 includes a light-emitting element 201, a driving transistor 202 (DRV), a writing transistor 203 (SEL), and a first capacitor 204. One of the source and drain of the driving transistor 202 is connected to a first electrode of the light-emitting element 201, and the other of the source and drain of the driving transistor 202 is connected to a first power supply terminal 205 (hereinafter referred to as Vdd). A second electrode of the light-emitting element 201 is connected to a second power supply terminal 206 (hereinafter referred to as Vss).

[0021] One of the source and drain of the write transistor 203 is connected to the gate electrode of the drive transistor 202, and the other of the source and drain of the write transistor 203 is connected to the signal line 107. The gate electrode of the write transistor 203 is connected to the first scan line 106.

[0022] The first capacitance element 204 is connected between the gate of the driving transistor 202 and one of the source and drain (here, the source), and holds the respective luminance signals in each pixel 102. The first capacitance element 204 may be any of a parasitic capacitance, a capacitance between the gate and channel of a MOS, an MIM (Metal-Insulator-Metal) structure, and an MOM (Metal-Oxide-Metal) structure.

[0023] In this embodiment, the drain of the driving transistor 202 is connected to the anode of the light emitting element 201, and the source of the driving transistor 202 is connected to a first power supply terminal 205 (Vdd).

[0024] The first capacitance element 204 is connected between the gate electrode of the driving transistor 202 and the source of the driving transistor 202, and holds the respective luminance signals in each pixel 102. The first capacitance element 204 according to this embodiment has an MIM structure.

[0025] Fig. 3 is a plan view showing an example of the circuit shown in Fig. 2. The driving transistor 202 is composed of a gate electrode 301, a source 302, and a drain 303.

[0026] The write transistor 203 is composed of a gate electrode 304, a source 305, and a drain 306. Reference numeral 307 denotes a contact electrode, which is connected to wiring in other layers.

[0027] Fig. 4 is a cross-sectional view taken along line AA' in the plan view shown in Fig. 3. The source and drain of the driving transistor 202 are formed by P-type diffusion layers 401 and 402, respectively.

[0028] The source and drain of the write transistor 203 are respectively formed by P-type diffusion layers 403 and 404. High-concentration N-type diffusion layers 405 and 406, which are halo-implanted layers, are adjacent to the P-type diffusion layers 403 and 404, and a lower-concentration N-type well layer 407 is disposed between the high-concentration N-type diffusion layers 405 and 406.

[0029] On the other hand, the driving transistor 202 has a structure in which a halo injection layer is not disposed. Because the driving transistor 202 supplies a subthreshold current to the light-emitting element, if a halo injection layer were disposed, even slight variations in its concentration could result in large variations in the subthreshold current for each pixel. By not disposing a halo injection layer, it is possible to reduce variations in the amount of current supplied by the driving transistor 202 to the organic light-emitting element 201.

[0030] Each of the transistors according to this embodiment is provided on an N-type well layer 407 and a P-type substrate 408, and is isolated by an insulator isolation portion 409. The insulator isolation portion 409 may be any of STI (Shallow Trench Isolation) isolation, LOCOS (Local Oxidation Of Silicon) isolation, and N-type diffusion layer isolation.

[0031] The insulating layer 410 is an insulating layer provided between the light-emitting element 201 and the first surface of the silicon substrate. The insulating layer 410 is also called an interlayer insulating layer and constitutes the wiring layer of the light-emitting device. The contact electrodes 307 pass through openings provided in the insulating layer 410 and are in contact with the source, drain, and gate electrodes of the drive transistor 202 and the write transistor 203.

[0032] In this embodiment, the write transistor has a halo implantation layer in the source and drain diffusion regions, and the halo implantation layer has a polarity opposite to that of the diffusion regions.

[0033] This configuration can reduce leakage current flowing from the source to the drain of the writing transistor 202 and into the first capacitor 204, thereby reducing fluctuations in the luminance signal held by the first capacitor 204. Therefore, the light-emitting element 201 can emit light stably at a predetermined luminance.

[0034] Furthermore, this embodiment describes that the driving transistor can reduce variations in the amount of current supplied from the driving transistor 202 to the organic light-emitting element 201 by configuring the driving transistor so that the source and drain diffusion regions do not have a halo injection layer having a polarity opposite to that of the diffusion regions.

[0035] [Embodiment 2] In this embodiment, a peripheral circuit transistor 501 (shown in FIG. 5) has a halo structure. The following mainly describes the configuration that differs from other embodiments.

[0036] 5 is a plan view of an example of a transistor in the peripheral circuit section. A peripheral circuit transistor 501 is composed of a gate electrode 502, a source 503, and a drain 504.

[0037] 6 is a cross-sectional view taken along line BB' in the plan view of FIG. 5. The source and drain of the peripheral circuit transistor 501 are formed by P-type diffusion layers 601 and 602, respectively. N-type diffusion layers 603 and 604, which are halo-implanted layers, are adjacent to the P-type diffusion layers 601 and 602, respectively, and a lower-concentration N-type well layer 407 is disposed between the N-type diffusion layers 603 and 604. In this embodiment, the peak concentrations of the high-concentration N-type diffusion layers 405 and 406 constituting the write transistor 203 are higher than the peak concentrations of the N-type diffusion layers 603 and 604 constituting the peripheral circuit transistor 501. However, the present invention is not limited to this configuration. The concentrations of the halo-implanted layers may be adjusted appropriately depending on the amount of leakage current, and the magnitude relationship may be reversed.

[0038] In this embodiment, the transistors of the peripheral circuit have halo implantation layers in the diffusion regions of the source and drain, and the halo implantation layers have a polarity opposite to that of the diffusion regions. Also, it has been described that the peak concentration of the impurity concentration in the halo implantation layer of the write transistor is different from the peak concentration of the impurity concentration in the halo implantation layer of the transistors of the peripheral circuit, and in particular, that the peak concentration of the halo implantation layer of the write transistor is higher than the peak concentration of the halo implantation layer of the transistors of the peripheral circuit.

[0039] With this configuration, it is possible to suppress the leakage current flowing from the source to the drain of the peripheral circuit transistor 501, thereby reducing the current consumption in the peripheral circuit section.

[0040] [Embodiment 3] This embodiment has a light-emitting control transistor arranged between a power supply that supplies current to the light-emitting element and a drive transistor. More specifically, this configuration has a light-emitting control transistor that controls the current supply from Vdd 205 to the drive transistor 202. The following will mainly describe the configuration that differs from other embodiments. The light-emitting control transistor is also called a fourth transistor, following the drive transistor, write transistor, and peripheral circuit transistors. It may also be called a light-emitting period control transistor because it controls the light-emitting period. The following will mainly describe the configuration that differs from other embodiments.

[0041] 7 is a schematic diagram illustrating an example of a light-emitting device according to this embodiment. In the pixel array section 103, a second scanning line 701 is arranged for each pixel row along the row direction. The second scanning line 701 is connected to the output terminal of the corresponding row in the vertical scanning circuit 104, and supplies a light-emitting control signal to each pixel 102.

[0042] Fig. 8 is a circuit diagram showing an example of a pixel included in the light-emitting device of Fig. 7. One of the source and drain (here, the drain) of the light-emitting control transistor 801 is connected to one of the source and drain (here, the source) of the driving transistor 202. The other (here, the source) of the light-emitting control transistor 801 is connected to Vdd 205. In addition, the gate of the light-emitting control transistor 801 is connected to the second scanning line 701.

[0043] The second capacitance element 802 is connected between the drain of the light-emitting control transistor 801 and Vdd 205. The second capacitance element 802 may be any of a parasitic capacitance, a capacitance between the gate and channel of a MOS, an MIM (Metal-Insulator-Metal) structure, and an MOM (Metal-Oxide-Metal) structure.

[0044] The emission control transistor 801 responds to an emission control signal applied to its gate from the vertical scanning circuit 104 via the second scanning line 701 and turns on, thereby allowing current to be supplied from Vdd 205 to the drive transistor 202. This enables the drive transistor 202 to emit light from the organic light emitting element 201. In other words, the emission control transistor 801 functions as a transistor that controls whether the organic light emitting element 201 emits light. In this way, the switching operation of the emission control transistor 801 enables so-called duty control, which controls the ratio between the emission period and the non-emission period of the organic light emitting element 201. This duty control reduces afterimage blurring caused by the emission of light by the pixel 102 over one frame period, thereby improving image quality, particularly in moving images.

[0045] Furthermore, due to variations during manufacturing, the threshold value of the drive transistor 202 may differ from pixel to pixel. When the same signal voltage is written to multiple pixels that emit the same light color, the amount of current flowing through the drive transistor 202 differs for each pixel, resulting in variations in the amount of light emitted. Therefore, before writing the signal voltage, a so-called threshold correction operation is performed to maintain a threshold between the gate and source of the drive transistor 202. This threshold correction operation can reduce variations in the amount of current through the drive transistor 202 in each pixel, achieving more uniform light emission.

[0046] In the threshold correction operation, a current is passed through the organic light emitting element 201 via the light emitting control transistor 801 and the drive transistor 202, and then the light emitting control transistor 801 is turned off. As a result, a current flows through the organic light emitting element 201 until the voltage between the gate and source of the drive transistor 202 becomes statically stable, and the threshold correction is performed.

[0047] Fig. 9 is a plan view of an example of the circuit shown in Fig. 8. The light-emitting control transistor 801 is composed of a gate electrode 901, a source section 902, and a drain section 302.

[0048] 10 is a cross-sectional view taken along line CC' in the plan view of FIG. 9. The source and drain of the light-emission control transistor 801 are formed of P-type diffusion layers 1001 and 1002, respectively. High-concentration N-type diffusion layers 1003 and 1004, which are halo-implanted layers, are adjacent to the P-type diffusion layers 1001 and 1002, respectively, and a lower-concentration N-type well layer 407 is disposed between the high-concentration N-type diffusion layers 1003 and 1004. In this embodiment, the peak concentrations of the high-concentration N-type diffusion layers 1003 and 1004 constituting the light-emission control transistor 801 are higher than the peak concentrations of the N-type diffusion layers 603 and 604 constituting the peripheral circuit transistor 501. However, the present invention is not limited to this configuration. The concentrations of the halo-implanted layers may be adjusted appropriately depending on the amount of leakage current, and the magnitude relationship may be reversed.

[0049] In this embodiment, the peak impurity concentration in the halo implantation layer of the light-emission control transistor is higher than the peak impurity concentration in the halo implantation layer of the transistor of the peripheral circuit.

[0050] Furthermore, the peak concentration of the impurity concentration in the halo injection layer of the light-emission control transistor may be the same as the peak concentration of the impurity concentration in the halo injection layer of the write transistor.

[0051] With this configuration, during threshold correction, the leakage current flowing from the source to the drain of the light-emitting control transistor 801 and into the first capacitance element 204 can be reduced, and fluctuations in the threshold voltage held by the first capacitance element 204 can be suppressed.

[0052] [Embodiment 4] This embodiment has a reset transistor disposed between the drain or source terminal of the drive transistor connected to the light-emitting element and a terminal at a lower potential than the power supply that supplies current to the light-emitting element. More specifically, this configuration has a reset transistor that connects the anode of the light-emitting element 201 to a third power supply terminal 1202 (hereinafter referred to as Vres) to reset the light-emitting element 201. The reset transistor is also called a fifth transistor following the light-emitting control transistor. The third power supply terminal 1202 may be a power supply with a lower potential than the power supply that supplies current to the light-emitting element. The third power supply terminal 1202 according to this embodiment is not limited to this embodiment as long as it has a potential that allows the reset transistor to reset the light-emitting element. The following description will focus on configurations that differ from other embodiments.

[0053] 11 is a schematic diagram illustrating an example of a light-emitting device according to this embodiment. In the pixel array section 103, a third scanning line 1101 is arranged for each pixel row along the row direction. The third scanning line 1101 is connected to the output terminal of the corresponding row in the vertical scanning circuit 104, and supplies a reset signal to each pixel 102.

[0054] FIG. 12 is a circuit diagram showing an example of a pixel circuit included in the light-emitting device of FIG. 11. One of the source and drain (here, the source) of a reset transistor 1201 is connected to one of the source and drain (here, the drain) of a drive transistor 202. The other terminal of the reset transistor 1201 is connected to a third power supply terminal 1202 (hereinafter, Vres). The gate of the reset transistor 1201 is connected to a third scanning line 1101. By turning on the reset transistor 1201, the anode of the organic light-emitting element 201 is connected to Vres 1202, and the luminance of the organic light-emitting element 201 can be set to the black level. This makes it possible to realize a high-contrast light-emitting device. Furthermore, during the light-emitting period, the reset transistor is in an off state.

[0055] Fig. 13 is a plan view of an example of the circuit shown in Fig. 12. The reset transistor 1201 is composed of a gate electrode 1301, a source 303, and a drain 1302.

[0056] 14 is a cross-sectional view taken along the line DD′ in the plan view shown in FIG. 13. The source and drain of the reset transistor 1201 are formed by P-type diffusion layers 1401 and 1402, respectively. High-concentration N-type diffusion layers 1403 and 1404, which are halo-implanted layers, are adjacent to the P-type diffusion layers 1401 and 1402, respectively, and a lower-concentration N-type well layer 407 is disposed between the high-concentration N-type diffusion layers 1403 and 1404. In this embodiment, the peak concentrations of the high-concentration N-type diffusion layers 1403 and 1404 constituting the reset transistor 1201 are higher than the peak concentrations of the N-type diffusion layers 603 and 604 constituting the peripheral circuit transistor 501. However, the present invention is not limited to this configuration. The concentrations of the halo-implanted layers may be adjusted appropriately depending on the amount of leakage current, and the magnitude relationship may be reversed.

[0057] In this embodiment, the configuration has been described in which the peak concentration of the impurity concentration in the halo implantation layer of the transistor of the peripheral circuit is different from the peak concentration of the impurity concentration in the halo implantation layer of the reset transistor.

[0058] The peak impurity concentration in the halo implantation layer of the reset transistor may be higher than the peak impurity concentration in the halo implantation layer of the transistor of the peripheral circuit.

[0059] Furthermore, the peak concentration of the impurity concentration in the halo implantation layer of the reset transistor may be the same as the peak concentration of the impurity concentration in the halo implantation layer of the write transistor.

[0060] This configuration makes it possible to suppress the leakage current that flows from the source to the drain of the reset transistor 1201. As a result, during the light emission period, it is possible to suppress the leakage current that flows from the drive transistor 202 to Vres 1202 via the reset transistor 1201, and it is possible to reduce the current consumption of the pixel 102.

[0061] [Embodiment 5] In this embodiment, the transistors constituting the inverter circuit 1501 in the vertical scanning circuit 104 have a halo structure. The following mainly describes the configuration that differs from other embodiments.

[0062] Fig. 15 is a circuit diagram of an example of an inverter circuit 1501 in the vertical scanning circuit 104 of the light emitting device of Fig. 11. As shown in Fig. 15, the drain, source, and gate electrode of a P-type transistor 1502 are connected to the drain of an N-type transistor 1503, a fourth power supply terminal 1504 (hereinafter, Vddd), and the gate electrode of the N-type transistor 1503, respectively.

[0063] The source of the N-type transistor 1503 is connected to a fifth power supply terminal 1505 (hereinafter referred to as Vssd).

[0064] The inverter circuit 1501 has an input terminal 1506 and an output terminal 1507. The input terminal 1506 is connected to the gates of a P-type transistor 1502 and an N-type transistor 1503. The output terminal 1507 is connected to the drain of the P-type transistor 1502 and the drain of the N-type transistor 1503, and further to any one of the first scan line 106, the second scan line 701, and the third scan line 1101.

[0065] Fig. 16 is a plan view of an example of the circuit shown in Fig. 15. The P-type transistor 1502 is composed of a gate electrode 1601, a source section 1602, and a drain section 1603.

[0066] The N-type transistor 1503 is composed of a gate electrode 1604 , a source 1605 , and a drain 1606 .

[0067] Fig. 17 is a cross-sectional view taken along the line E-E' in the plan view shown in Fig. 16. The source and drain of P-type transistor 1502 are formed by P-type diffusion layers 1701 and 1702, respectively. N-type diffusion layers 1703 and 1704, which are halo-implanted layers, are adjacent to P-type diffusion layers 1701 and 1702, respectively, and a lightly doped N-type well layer 407 is disposed between N-type diffusion layers 1703 and 1704.

[0068] The drain and source of N-type peripheral circuit transistor 1503 are respectively formed by N-type diffusion layers 1705 and 1706. P-type diffusion layers 1707 and 1708, which are halo-implanted layers, are adjacent to N-type diffusion layers 1705 and 1706, respectively, and a lightly doped P-type well layer 1709 is disposed between P-type diffusion layers 1707 and 1708.

[0069] With this configuration, it is possible to reduce the leakage current flowing from Vddd 1504 to Vssd 1505 via the P-type peripheral circuit transistor 1502 and the N-type peripheral circuit transistor 1503, thereby reducing the current consumption in the vertical scanning circuit 104.

[0070] [Other embodiments] 18 is a schematic diagram showing an example of a display device according to this embodiment. A display device 2000 may have a touch panel 2003, a display panel 2005, a frame 2006, a circuit board 2007, and a battery 2008 between an upper cover 2001 and a lower cover 2009. The touch panel 2003 and the display panel 2005 are connected by flexible printed circuits FPCs 2002 and 2004. Transistors are printed on the circuit board 2007. The battery 2008 may not be provided if the display device is not a portable device, and may be provided in a different position even if the display device is a portable device.

[0071] The display device according to this embodiment may have color filters having red, green, and blue colors, which may be arranged in a delta arrangement.

[0072] The display device according to the present embodiment may be used as a display unit of a mobile terminal. In this case, the display device may have both a display function and an operation function. Examples of the mobile terminal include a mobile phone such as a smartphone, a tablet, and a head-mounted display.

[0073] The display device according to this embodiment may be used as a display unit of an imaging device having an optical unit with a plurality of lenses and an imaging element that receives light that has passed through the optical unit. The imaging device may have a display unit that displays information acquired by the imaging element. The display unit may be a display unit exposed to the outside of the imaging device or a display unit disposed within a viewfinder. The imaging device may be a digital camera or a digital video camera.

[0074] 19(a) is a schematic diagram showing an example of an imaging device according to this embodiment. The imaging device 2100 may have a viewfinder 2101, a rear display 2102, an operation unit 2103, and a housing 2104. The viewfinder 2101 may have a display device according to this embodiment. In this case, the display device may display not only an image to be captured, but also environmental information, imaging instructions, and the like. The environmental information may include the intensity of external light, the direction of external light, the speed at which the subject is moving, the possibility that the subject will be blocked by an obstruction, and the like.

[0075] Since the optimum timing for capturing an image is very short, it is better to display information as soon as possible. Therefore, it is preferable to use a display device using the organic light-emitting element of the present invention. This is because the organic light-emitting element has a fast response speed. A display device using an organic light-emitting element can be used more preferably than a liquid crystal display device, which requires a high display speed.

[0076] The imaging device 2100 has an optical section (not shown). The optical section has multiple lenses, which form an image on an imaging element housed in a housing 2104. The focus of the multiple lenses can be adjusted by adjusting their relative positions. This operation can also be performed automatically. The imaging device may also be called a photoelectric conversion device. Rather than sequentially capturing images, the photoelectric conversion device can include an imaging method that detects the difference from the previous image, or a method of cutting out an image from a constantly recorded image, etc.

[0077] FIG. 19(b) is a schematic diagram illustrating an example of an electronic device according to this embodiment. The electronic device 2200 has a display unit 2201, an operation unit 2202, and a housing 2203. The housing 2203 may include a circuit, a printed circuit board having the circuit, a battery, and a communication unit. The operation unit 2202 may be a button or a touch panel type reaction unit. The operation unit may be a biometric recognition unit that recognizes a fingerprint to unlock the device, etc. The communication unit is a communication unit that communicates with the outside world and may be wired or wireless. An electronic device having a communication unit may also be called a communication device. The electronic device may further have a camera function by including a lens and an image sensor. An image captured by the camera function is displayed on the display unit. Examples of the electronic device include a smartphone, a laptop computer, etc.

[0078] 20A and 20B are schematic diagrams illustrating an example of a display device according to this embodiment. Fig. 20A shows a display device such as a television monitor or a PC monitor. A display device 2300 has a frame 2301 and a display unit 2302. The light-emitting device according to this embodiment may be used in the display unit 2302.

[0079] It has a frame 2301 and a base 2303 that supports a display unit 2302. The base 2303 is not limited to the form shown in Fig. 22(a). The bottom side of the frame 1301 may also serve as the base.

[0080] The frame 2301 and the display unit 2302 may be curved. The radius of curvature may be 5000 mm or more and 6000 mm or less.

[0081] FIG. 20(b) is a schematic diagram illustrating another example of a display device according to this embodiment. The display device 2310 in FIG. 20(b) is configured to be bendable, and is a so-called foldable display device. The display device 2310 has a first display unit 2311, a second display unit 2312, a housing 2313, and a bending point 2314. The first display unit 2311 and the second display unit 2312 may include a light-emitting device according to this embodiment. The first display unit 2311 and the second display unit 2312 may be a single, seamless display unit. The first display unit 2311 and the second display unit 2312 can be separated by the bending point. The first display unit 2311 and the second display unit 2312 may each display different images, or the first and second display units may display a single image.

[0082] 21 is a schematic diagram showing an example of a wearable device according to this embodiment. The wearable device can be applied to systems that can be worn as a wearable device, such as smart glasses, HMDs, and smart contact lenses. An image capturing and displaying device used in such an application example includes an image capturing device capable of photoelectrically converting visible light and a displaying device capable of emitting visible light.

[0083] 21(a) shows glasses 1600 (smart glasses) according to one application example. An imaging device 2602 such as a CMOS sensor or SPAD is provided on the front side of a lens 2601 of the glasses 2600. In addition, a display device according to any of the above-described embodiments is provided on the back side of the lens 2601.

[0084] The glasses 2600 further include a control device 2603. The control device 2603 functions as a power source that supplies power to the image capture device 2602 and the display device according to each embodiment. The control device 2603 also controls the operations of the image capture device 2602 and the display device. The lens 2601 is formed with an optical system for focusing light onto the image capture device 2602.

[0085] FIG. 21(b) shows glasses 2610 (smart glasses) according to one application example. The glasses 2610 include a control device 2612. The control device 2612 is equipped with an imaging device corresponding to the imaging device 2602 and a display device. A lens 2611 is formed with an optical system for projecting light emitted by the display device in the control device 2612, and an image is projected onto the lens 2611. The control device 2612 functions as a power source for supplying power to the imaging device and the display device, and also controls the operation of the imaging device and the display device. The control device includes an image control unit, which transmits an image control signal to a peripheral circuit of the light-emitting device. The control device may also include a gaze detection unit that detects the gaze of the wearer. Infrared light may be used to detect the gaze. The infrared light emitter emits infrared light toward the eyeball of a user gazing at a displayed image. An imaging unit having a light-receiving element detects the emitted infrared light reflected from the eyeball, thereby obtaining an image of the eyeball. By providing a reduction means for reducing the amount of light from the infrared light emitting section to the display section in a plan view, degradation of image quality is reduced.

[0086] The gaze of the user relative to the displayed image is detected from an image of the eyeball obtained by capturing infrared light. Any known method can be used for gaze detection using an image of the eyeball. One example is a gaze detection method based on the Purkinje image formed by reflection of irradiated light on the cornea.

[0087] More specifically, gaze detection processing is performed based on the pupil-corneal reflex method, which calculates a gaze vector representing the direction (rotation angle) of the eyeball based on the pupil image and Purkinje image included in the captured image of the eyeball, thereby detecting the user's gaze.

[0088] A display device according to an embodiment of the present invention may have an imaging device having a light receiving element, and may control the image displayed on the display device based on information about the user's line of sight from the imaging device.

[0089] Specifically, the display device determines a first display area on which the user gazes and a second display area other than the first display area based on the line-of-sight information. The first display area and the second display area may be determined by a control device of the display device, or may be determined by an external control device and received. In the display area of the display device, the display resolution of the first display area may be controlled to be higher than the display resolution of the second display area. In other words, the resolution of the second display area may be lower than the resolution of the first display area.

[0090] Furthermore, the first display area and the second display area of the display area may be determined based on gaze information. Note that AI may be used to determine the first display area and areas with high priority. The AI may be a model configured to estimate the gaze angle and the distance to an object in the gaze from an image of the eyeball, using an image of the eyeball and the actual gaze direction of the eyeball in the image as training data. The AI program may be included in the display device, the imaging device, or an external device. If included in an external device, it is transmitted to the display device via communication.

[0091] When display control is performed based on visual recognition detection, the smart glasses can be preferably applied to smart glasses that further include an imaging device for capturing images of the outside world. The smart glasses can display captured external information in real time.

[0092] As described above, according to the present invention, it is possible to provide a light emitting device in which the leakage current of the light emitting element is reduced.

[0093] As described in the above embodiments, the present invention includes the following configurations.

[0094] [Configuration 1] A light-emitting element; a first transistor and a second transistor disposed on a first surface of a silicon substrate; a third transistor provided in a peripheral circuit that supplies an image signal to the first transistor; one of the source and drain of the first transistor is connected to the gate electrode of the second transistor; a light-emitting device in which either a source or a drain of the second transistor is connected to the light-emitting element, The light emitting device, wherein the first transistor has a halo injection layer in the diffusion region of the source and the drain, and the halo injection layer has a polarity opposite to that of the diffusion region.

[0095] [Configuration 2] 2. The light emitting device according to claim 1, wherein the second transistor does not have a halo injection layer having a polarity opposite to that of the diffusion region in the source and drain diffusion regions.

[0096] [Configuration 3] The light-emitting device according to configuration 2, wherein the third transistor has a halo injection layer in the diffusion region of the source and the drain, and the halo injection layer has a polarity opposite to that of the diffusion region.

[0097] [Configuration 4] The light emitting device according to configuration 3, wherein the peak impurity concentration in the halo injection layer of the first transistor is different from the peak impurity concentration in the halo injection layer of the third transistor.

[0098] [Configuration 5] 5. The light emitting device according to configuration 4, wherein the peak impurity concentration in the halo injection layer of the first transistor is higher than the peak impurity concentration in the halo injection layer of the third transistor.

[0099] [Configuration 6] a fourth transistor disposed between a power source that supplies a current to the light emitting element and the second transistor; the fourth transistor has a halo implantation layer in a source and drain diffusion region, the halo implantation layer having a polarity opposite to that of the diffusion region; The light emitting device according to configuration 3, wherein the peak impurity concentration in the halo injection layer of the third transistor is different from the peak impurity concentration in the halo injection layer of the fourth transistor.

[0100] [Configuration 7] 7. The light emitting device according to configuration 6, wherein the peak impurity concentration in the halo injection layer of the fourth transistor is higher than the peak impurity concentration in the halo injection layer of the third transistor.

[0101] [Configuration 8] 8. The light emitting device according to configuration 6 or 7, wherein the peak impurity concentration in the halo injection layer of the first transistor is the same as the peak impurity concentration in the halo injection layer of the fourth transistor.

[0102] [Configuration 9] a fifth transistor disposed between a terminal of the drain or the source of the second transistor that is connected to the light emitting element and a terminal that has a lower potential than a power supply that supplies a current to the light emitting element; the fifth transistor has a halo implantation layer in the source and drain diffusion regions, the halo implantation layer having a polarity opposite to that of the diffusion regions; The light emitting device according to configuration 3, wherein the peak impurity concentration in the halo injection layer of the third transistor is different from the peak impurity concentration in the halo injection layer of the fifth transistor.

[0103] [Configuration 10] 10. The light emitting device according to configuration 9, wherein the peak impurity concentration in the halo injection layer of the fifth transistor is higher than the peak impurity concentration in the halo injection layer of the third transistor.

[0104] [Configuration 11] 11. The light emitting device according to configuration 9 or 10, wherein the peak impurity concentration in the halo injection layer of the first transistor is the same as the peak impurity concentration in the halo injection layer of the fifth transistor.

[0105] [Configuration 12] 12. The light emitting device according to any one of configurations 1 to 11, wherein the peripheral circuit is provided on the first surface of the silicon substrate.

[0106] [Configuration 13] 13. The light emitting device according to any one of configurations 1 to 12, wherein the peripheral circuit is disposed on a second silicon substrate different from the silicon substrate.

[0107] [Configuration 14] 14. The display device according to any one of configurations 1 to 13, further comprising an image control unit that transmits an image control signal to the peripheral circuit, and the light-emitting element emits light in response to the image control signal.

[0108] [Configuration 15] an optical unit having a plurality of lenses, an image pickup element that receives light that has passed through the optical unit, and a display unit that displays an image picked up by the image pickup element; 15. A photoelectric conversion device, wherein the display unit is the display device according to configuration 14.

[0109] [Configuration 16] 15. An electronic device comprising: the display device according to configuration 14; a housing in which the display device is provided; and a communication unit provided in the housing for communicating with an external device. [Explanation of symbols]

[0110] 201 Light-emitting element 202 Drive transistor 203 Write transistor 204 first capacitance element 205 First power supply terminal Vdd 206 Second power supply terminal Vss 301 Gate electrode of drive transistor 302 Source part of drive transistor 303 Drain part of drive transistor 304 Gate electrode of write transistor 305 Source part of write transistor 306 Drain part of write transistor 307 Contact electrode 401, 402, 403, 404 P-type diffusion layer 405, 406 Highly doped N-type diffusion layer 407 N-type well layer 408 P type board 409 Insulator Separator

Claims

1. A light-emitting element; a first transistor and a second transistor disposed on a first surface of a silicon substrate; a third transistor provided in a peripheral circuit that supplies an image signal to the first transistor; one of the source and the drain of the first transistor is connected to the gate electrode of the second transistor; a light-emitting device in which either a source or a drain of the second transistor is connected to the light-emitting element, The light emitting device according to claim 1, wherein the first transistor has a halo injection layer in the diffusion region of the source and the drain, and the halo injection layer has a polarity opposite to that of the diffusion region.

2. The light emitting device according to claim 1 , wherein the second transistor does not have a halo injection layer having a polarity opposite to that of the diffusion region in the source and drain diffusion regions.

3. 3. The light emitting device according to claim 2, wherein the third transistor has a halo injection layer in the source and drain diffusion regions, the halo injection layer having a polarity opposite to that of the diffusion regions.

4. 4. The light emitting device according to claim 3, wherein a peak concentration of the impurity concentration in the halo injection layer of the first transistor is different from a peak concentration of the impurity concentration in the halo injection layer of the third transistor.

5. 5. The light emitting device according to claim 4, wherein a peak impurity concentration in the halo injection layer of the first transistor is higher than a peak impurity concentration in the halo injection layer of the third transistor.

6. a fourth transistor disposed between a power source that supplies a current to the light emitting element and the second transistor; the fourth transistor has a halo implant layer in a source and drain diffusion region, the halo implant layer having a polarity opposite to that of the diffusion region; 4. The light emitting device according to claim 3, wherein a peak concentration of the impurity concentration in the halo injection layer of the third transistor is different from a peak concentration of the impurity concentration in the halo injection layer of the fourth transistor.

7. 7. The light emitting device according to claim 6, wherein a peak impurity concentration in the halo injection layer of the fourth transistor is higher than a peak impurity concentration in the halo injection layer of the third transistor.

8. 7. The light emitting device according to claim 6, wherein a peak concentration of the impurity concentration in the halo injection layer of the first transistor is the same as a peak concentration of the impurity concentration in the halo injection layer of the fourth transistor.

9. a fifth transistor disposed between a terminal of the drain or the source of the second transistor that is connected to the light emitting element and a terminal that has a lower potential than a power supply that supplies a current to the light emitting element; the fifth transistor has a halo implantation layer in the source and drain diffusion regions, the halo implantation layer having a polarity opposite to that of the diffusion regions; 4. The light emitting device according to claim 3, wherein a peak concentration of the impurity concentration in the halo injection layer of the third transistor is different from a peak concentration of the impurity concentration in the halo injection layer of the fifth transistor.

10. 10. The light emitting device according to claim 9, wherein a peak concentration of the impurity concentration in the halo injection layer of the fifth transistor is higher than a peak concentration of the impurity concentration in the halo injection layer of the third transistor.

11. 10. The light emitting device according to claim 9, wherein a peak concentration of the impurity concentration in the halo injection layer of the first transistor is the same as a peak concentration of the impurity concentration in the halo injection layer of the fifth transistor.

12. 2. The light emitting device according to claim 1, wherein the peripheral circuit is provided on the first surface of the silicon substrate.

13. 2. The light emitting device according to claim 1, wherein the peripheral circuit is disposed on a second silicon substrate different from the silicon substrate.

14. 14. The display device according to claim 1, further comprising an image control unit that transmits an image control signal to the peripheral circuit, and the light-emitting element emits light in response to the image control signal.

15. an optical unit having a plurality of lenses, an image pickup element that receives light that has passed through the optical unit, and a display unit that displays an image picked up by the image pickup element; A photoelectric conversion device, wherein the display unit is the display device according to claim 14.

16. 15. An electronic device comprising: the display device according to claim 14; a housing in which the display device is provided; and a communication section provided in the housing for communicating with an external device.

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