Tuning voltage setpoint in pulsed RF signal for tunable edge sheath system

Abstract

To provide a method for tuning a voltage setpoint for a multi-state pulsed RF signal in a plasma processing system.SOLUTION: The method includes: applying RF power from a first generator to an electrostatic chuck (ESC), where the RF power from the first generator defines a first multi-state pulsed RF signal; applying RF power from a second generator to an edge electrode that surrounds the ESC and is disposed below an edge ring that surrounds the ESC, where the RF power from the second generator defines a second multi-state pulsed RF signal having a first state and a second state, where, for each state of the second multi-state pulsed RF signal, the second generator automatically introduces a phase adjustment to substantially match phase with a corresponding state of the first multi-state pulsed RF signal; and adjusting a voltage setpoint for the second state of the second multi-state pulsed RF signal to tune the phase adjustment to a target phase adjustment setting.SELECTED DRAWING: Figure 1

Description

[Technical Field]

[0001] The present disclosure relates to the fabrication of semiconductor devices. [Background technology]

[0002] Plasma etching processes are often used in the fabrication of semiconductor devices on semiconductor wafers. In plasma etching processes, semiconductor wafers containing semiconductor devices under fabrication are exposed to plasma generated within a plasma processing volume. The plasma interacts with materials on the semiconductor wafer, thereby removing and / or modifying materials so that they can subsequently be removed from the semiconductor wafer. Plasma can be generated using specific reactive gases that cause components of the plasma to interact with materials to be removed / modified from the semiconductor wafer without significantly interacting with other materials on the wafer that should not be removed / modified. Plasma is generated using radio frequency signals that energize the specific reactive gases. These radio frequency signals are transmitted through a plasma processing volume containing the reactive gases while the semiconductor wafer is exposed to the plasma processing volume. The transmission path of the radio frequency signal through the plasma processing volume can affect the manner in which the plasma is generated within the plasma processing volume. For example, in regions of the plasma processing volume where more radio frequency signal power is transmitted, more energy may be imparted to the reactive gas, causing spatial non-uniformity of the plasma characteristics throughout the plasma processing volume. The spatial non-uniformity of the plasma characteristics may manifest as spatial non-uniformity of ion density, ion energy, and / or reactive component density, among other plasma characteristics. The spatial non-uniformity of the plasma characteristics may correspondingly cause spatial non-uniformity of the plasma processing results on the semiconductor wafer. Therefore, the manner in which the radio frequency signal is transmitted through the plasma processing volume may affect the uniformity of the plasma processing results on the semiconductor wafer. It is in this context that the present disclosure arises. Summary of the Invention

[0003] Broadly speaking, embodiments of the present disclosure provide a method and system for adjusting the voltage set point of a secondary state of a pulsed RF signal in an adjustable edge sheath (TES) system, where the edge electrode is powered separately and independently from the main electrode of an electrostatic chuck (ESC).

[0004] In some implementations, a method for adjusting a voltage set point for a multi-state pulsed RF signal in a plasma processing system is provided, the method including: applying RF power from a first generator to an ESC, wherein the RF power from the first generator defines a first multi-state pulsed RF signal; applying RF power from a second generator to an edge electrode surrounding the ESC and disposed below an edge ring surrounding the ESC, wherein the RF power from the second generator defines a second multi-state pulsed RF signal having a first state and a second state, wherein for each state of the second multi-state pulsed RF signal, the second generator automatically introduces a phase adjustment to substantially match a phase to a corresponding state of the first multi-state pulsed RF signal; and adjusting the voltage set point for the second state of the second multi-state pulsed RF signal to adjust the phase adjustment to a target phase adjustment setting.

[0005] In some implementations, the target phase adjustment settings are captured via a user interface.

[0006] In some implementations, the target phase adjustment setting is calculated based on a model.

[0007] In some implementations, the target phase adjust setting defines a predetermined phase adjust amount by which the phase of the RF power from the secondary generator is adjusted.

[0008] In some implementations, adjusting the voltage set point to regulate the phase adjustment includes making incremental adjustments to the voltage set point until the phase adjustment reaches a target phase adjustment setting.

[0009] In some implementations, the stepwise adjustment is based on a particular voltage set point associated with a first state of the second multi-state pulsed RF signal.

[0010] In some implementations, the phase adjustment is adjusted to the target phase adjustment setting when the phase adjustment reaches the target phase adjustment setting or when the phase adjustment is within a predetermined range of the target phase adjustment setting.

[0011] In some implementations, adjusting the voltage set point to adjust the phase adjustment to a target phase adjustment setting places the voltage set point in the middle portion of the voltage set point's allowable range.

[0012] In some implementations, the target phase adjustment setting that facilitates the voltage set point being located in the middle portion of the voltage set point tolerance range remains substantially the same with changes in the capacitance of the matching circuit through which RF power from the second generator passes as it is applied to the edge electrode.

[0013] In some implementations, the change in capacitance of the matching circuit is responsive to a change in the voltage set point of the first state of the second multi-state pulsed RF signal.

[0014] In some implementations, the change in the voltage set point of the first state occurs based on the usage of the edge ring.

[0015] In some implementations, edge ring usage is defined as the amount of time the edge ring is exposed to RF.

[0016] In some implementations, a method for adjusting a voltage set point for a multi-state pulsed RF signal in a plasma processing system is provided, the method including applying RF power to an ESC from a first generator, wherein the RF power from the first generator defines a first pulsed RF signal having a first state and a second state; and applying RF power from a second generator to an edge electrode surrounding the ESC and disposed below an edge ring surrounding the ESC, wherein the RF power from the second generator defines a second pulsed RF signal having a first state and a second state. automatically introducing a first phase adjustment that substantially aligns the phase of a first state of the second pulsed RF signal with the first state of the first pulsed RF signal, the second generator automatically introducing a second phase adjustment that substantially aligns the phase of a second state of the second pulsed RF signal with the second state of the first pulsed RF signal, the second phase adjustment being adjusted to a target phase adjustment setting; and in response to detecting a change in the second phase adjustment away from the target phase adjustment setting, adjusting a voltage set point for the second state of the second pulsed RF signal to return the second phase adjustment to the target phase adjustment setting.

[0017] In some implementations, the target phase adjustment settings are captured via a user interface.

[0018] In some implementations, the target phase adjustment setting is calculated based on a model.

[0019] In some implementations, the target phase adjust setting defines a predetermined phase adjust amount by which the phase of the second state of the second pulsed RF signal is adjusted.

[0020] In some implementations, adjusting the voltage set point to return the second phase adjustment includes making incremental adjustments to the voltage set point until the second phase adjustment reaches the target phase adjustment setting.

[0021] In some implementations, the incremental adjustment is based on a particular voltage set point associated with the first state.

[0022] In some implementations, when the second phase adjustment reaches the target phase adjustment setting or is within a predetermined range of the target phase adjustment setting, the second phase adjustment is returned to the target phase adjustment setting.

[0023] In some implementations, adjusting the voltage set point to return the second phase adjustment to the target phase adjustment setting positions the voltage set point in the middle portion of the acceptable range of the voltage set point.

[0024] In some implementations, the target phase adjustment setting that facilitates the voltage set point being located in the middle portion of the voltage set point tolerance range remains substantially the same with changes in the capacitance of the matching circuit through which RF power from the second generator passes as it is applied to the edge electrode.

[0025] In some implementations, the change in capacitance of the matching circuit is responsive to a change in the voltage set point of the first state of the second pulsed RF signal.

[0026] In some implementations, the change in the voltage set point of the first state of the second pulsed RF signal occurs based on the usage of the edge ring.

[0027] In some implementations, edge ring usage is defined as the amount of time the edge ring is exposed to RF. [Brief explanation of the drawings]

[0028] [Figure 1] FIG. 1 shows a vertical cross-sectional view of a portion of a plasma processing system 100 for use in semiconductor chip manufacturing, according to some embodiments.

[0029] [Figure 2] FIG. 2 shows a vertical cross-sectional view of a plasma processing system for use in semiconductor chip manufacturing, according to some embodiments.

[0030] [Figure 3]FIG. 3 illustrates an exemplary circuit schematic of a TES impedance matching system, according to some embodiments.

[0031] [Figure 4] FIG. 4 conceptually illustrates components of a TES radio frequency signal generator 403 according to an implementation of the present disclosure.

[0032] [Figure 5] FIG. 5 shows voltage set points versus time for the TES multi-state pulsed RF signal generated by the TES RF signal generator 403, according to an implementation of the present disclosure.

[0033] [Figure 6] FIG. 6 is a graph conceptually illustrating the acceptable range of voltage set points for states S0 or S2, according to an implementation of the present disclosure.

[0034] [Figure 7] FIG. 7 is a graph conceptually illustrating the relationship between phase adjustment for state S0 / S2 and voltage set point for state S0 / S2, according to an implementation of the present disclosure.

[0035] [Figure 8] FIG. 8 conceptually illustrates a method for maintaining a voltage set point within a general mid-range of voltage set points allowed for the conditions of a pulsed RF signal, according to an implementation of the present disclosure.

[0036] [Figure 9] FIG. 9 is a graph conceptually illustrating the change in voltage set point for various states of a pulsed RF signal, according to an implementation of the present disclosure.

[0037] [Figure 10] FIG. 10 shows an example schematic diagram of the control system of FIG. 2, according to some embodiments. DETAILED DESCRIPTION OF THE INVENTION

[0038] In the following description, numerous specific details are set forth in order to provide an understanding of embodiments of the present disclosure. However, it will be apparent to one skilled in the art that the present disclosure may be practiced without some or all of these specific details. In other instances, well-known process operations have not been described in detail in order to avoid unnecessarily obscuring the present disclosure.

[0039] In plasma etching systems for semiconductor wafer fabrication, spatial variations in etching results across a semiconductor wafer can be characterized by radial etch uniformity and azimuthal etch uniformity. Radial etch uniformity can be characterized by the variation in etch rate at a given azimuthal position on the semiconductor wafer as a function of radial position on the semiconductor wafer, extending outward from the center of the semiconductor wafer to the edge of the semiconductor wafer. And, azimuthal etch uniformity can be characterized by the variation in etch rate at a given radial position on the semiconductor wafer, around the center of the semiconductor wafer, as a function of azimuthal position on the semiconductor wafer. In some plasma processing systems, such as those described herein, a semiconductor wafer is placed on an electrode, and a radio frequency signal is emitted from the electrode to generate a plasma in a plasma generating region above the semiconductor wafer, the plasma having controlled characteristics to produce a specified etching process on the semiconductor wafer.

[0040] Advances in two-state RF pulsing have enabled high aspect ratio etching by improving the relationship between process margins and etch selectivity, profile bow, critical dimension (CD), and etch rate uniformity. In the current two-state RF pulse nomenclature, "State 1" (or "S1") represents a high bias and source power, e.g., 1 kW, operating at pressures below 30 mTorr with ion energies above 3 keV to obtain a narrow IADF. The other state in the pulse, designated "State 0" (or "S0"), represents the deposition step with low bias and source power, e.g., less than 1 kW, and ion energies below 100 eV. State 0 primarily provides passivation due to different mechanisms, such as direct ion deposition and ion-activated neutral deposition. Typical pulse repetition rates for operating this two-state RF pulse regime are approximately 100 Hz to 2 kHz.

[0041] Currently, current state-of-the-art dielectric etch processes rely on the implementation of one or two RF regimes supported by on / off RF pulsing or level-level RF pulsing to combine the benefits of high vertical etch rates and sufficient sidewall passivation.

[0042] However, according to implementations of the present disclosure, additional regimes can independently restore or add more margin to the process. Such regime-based implementations can incorporate suitable intermediate states based on the implementation of a multi-state RF pulsing scheme, which overcomes fundamental process development limitations and barriers in existing etching technologies. The intermediate states are based on selective trimming of mask neck polymer at low ion energy states to facilitate a more aggressive high-energy state (on / high state) and a more polymer-prone passivation state (off / low state). Introducing such low ion energy states through source power only serves to control the neck / mask shape. Combining this approach with on-off pulsing instead of level-level pulsing causes more polymer deposition on the top of the mask, passivating the top of the mask and controlling the mask etch rate. This approach fundamentally breaks the trade-off between mask neck / process margin and selectivity.

[0043] The pulsed RF cycle can be characterized as a three-level pulsed RF using three different states of RF. In some implementations, S1 is configured to provide high source power and high bias power. This results in high aspect ratio (HAR) etching, but also results in sputtering of the mask, forming necks. S0 is configured as a low / off state, with low / absent source or bias power applied. S0 protects the mask by creating more neutral deposition on top. In some implementations, S0 is configured to provide direct ion deposition and ion-assisted neutral deposition.

[0044] In some implementations, the intermediate state S2 (State 2) is configured as a (substantially) source power only state (e.g., 60 MHz, high frequency) using low source power and very low or zero (or substantially zero) bias power. S2 induces dissociation to help etch open any necks that may have formed. Therefore, State S2 is configured to open the neck.

[0045] In summary, according to implementations of the present disclosure, S1 uses high-energy ions that create a neck, while S2 opens the neck and S0 provides passivation. The resulting feature has an open neck and also has more mask due to the increased passivation. This poses a trade-off challenge between neck and selectivity.

[0046] In contrast, in a level-level RF pulsing regime where only S1 and S0 are activated, not only is there a significant passivation, but there may also be a neck, which tends to cause clogging. However, three-level RF pulsing using S1, S0, and S2 provides an open neck and passivation, thereby breaking the trade-off between selectivity and cap margin. Roughly speaking, state S0 provides selectivity, while state S2 improves cap margin.

[0047] Generally speaking, in some implementations, the frequency of the bias power is less than about 10 MHz, and in some implementations, the frequency of the bias power is about 400 kHz.

[0048] In some implementations, the frequency of the source power is greater than about 10 MHz, in some implementations, the frequency of the source power is greater than about 20 MHz, and in some implementations, the frequency of the source power is about 60 MHz.

[0049] Although states S1, S0, and S2 above are discussed with respect to RF power applied to the main electrode of the ESC, in plasma processing systems implementing a tunable edge sheath (TES) system, bias RF power is independently supplied to the edge electrode surrounding the ESC, thereby enabling control of the plasma sheath and plasma characteristics at the edge region of the wafer. The RF power applied to the edge electrode is synchronized with the main electrode and therefore also includes corresponding states S1, S0, and S2, but the attributes of these states in the TES RF signal are controlled independently of the main bias RF signal.

[0050] 1 illustrates a vertical cross-sectional view of a portion of a plasma processing system 100 for use in semiconductor chip manufacturing, according to some embodiments. The plasma processing system 100 includes an electrode 109, which in some embodiments is formed of aluminum. A ceramic layer 110 is formed on an upper surface of the electrode 109. The ceramic layer 110 is configured to receive and support a wafer W while plasma processing operations are performed on the wafer W. In some implementations, the ceramic layer 110, the electrode 109, and associated components define an electrostatic chuck (ESC).

[0051] A first high frequency signal generator 147 (e.g., about 60 MHz) and a second high frequency signal generator 149 (e.g., about 400 kHz) supply high frequency power to the electrode 109 through an impedance matching system 143. By applying the high frequency power to gas species introduced into the process space above the wafer, a plasma 180 is generated for wafer processing, e.g., etching.

[0052] An edge ring 167 surrounds the ceramic layer 110 and is configured to facilitate extension of the plasma sheath radially outward beyond the outer peripheral edge of the wafer W to improve process results near the periphery of the wafer W.

[0053] An adjustable edge sheath (TES) system is implemented to include a TES electrode 415 disposed (embedded) within the coupling ring 161. A TES RF signal generator 403 supplies RF power to the TES electrode 415 via a TES impedance match system 401. The TES system can control properties of the plasma 180 near the outer peripheral edge of the wafer W, such as controlling the plasma sheath, plasma density, and ion attraction or repulsion characteristics. In general, by applying RF power to the TES electrode 415, the TES system enables adjustment of the plasma at the edge of the wafer to improve radial uniformity.

[0054] For a given process recipe, process recipe parameters are set, including parameters of the TES system that provide radial uniformity. For example, in the illustrated implementation, RF power is supplied by the TES RF signal generator 403 to the edge ring 167 having an initial thickness J1, for a state S1 at a first voltage V1, which is configured to adjust a plasma sheath, designated S1, above the top surface of the wafer W at the edge or peripheral region of the wafer W to have a height H1.

[0055] However, during plasma processing, the edge ring 167 is partially consumed or worn away, and thus, as RF time and process cycles accumulate, the thickness of the edge ring 167 gradually decreases. Thus, for example, over the course of several hours of RF time, the thickness of the edge ring 167 may decrease from a thickness J1 to a thickness J2. As the thickness of the edge ring 167 decreases with the application of voltage V1 to state S1 during processing, the level of the plasma sheath also decreases. For example, if the thickness of the edge ring 167 wears down to a thickness J2, the plasma sheath will decrease to a level indicated by S2, thereby decreasing the height H2 above the top surface of the wafer W at the wafer edge.

[0056] This reduction in edge ring thickness and the resulting change in plasma sheath level at the wafer edge can lead to radial non-uniformities at the edge, such as differences in etch rate between the edge and center of the wafer (non-uniform etch rate and etch depth) and a tilted feature profile at the edge (non-uniform etch direction).

[0057] Therefore, to offset the effects of edge ring wear / consumption and maintain the plasma sheath level despite the loss of edge ring thickness, the voltage applied to the TES electrode 415 for state S1 can be increased to a second voltage V2. In the illustrated implementation, when voltage V2 (greater than voltage V1) is applied by the TES RF signal generator 403 for state S1 and the edge sheath thickness is reduced to thickness J2, the plasma sheath is restored to that shown at reference S1. That is, even though the thickness of the edge ring 167 has decreased, the plasma sheath level is maintained in the TES system by applying an increased voltage for state S1.

[0058] However, increasing the voltage applied to the TES electrode 415 in state S1 changes the impedance of the system, causing an increase in the reflection of RF power in state S1. To minimize the reflected RF power in state S1, the capacitance setting in the TES impedance match system 401 can be adjusted, as discussed in more detail below.

[0059] Note that the TES RF signal generator 403 is configured to automatically adjust the phase of the state S1 of the RF signal generated by the RF signal generator 149 to match the phase of the state S1 (e.g., at 400 kHz) of the RF signal. Thus, as the state S1 voltage applied to the TES electrode 415 increases, the TES RF signal generator 401 automatically adjusts to maintain phase alignment with the state S1 of the RF signal from the RF signal generator 149. It has been discovered that adjusting the capacitance setting in the TES impedance matching system to minimize RF power reflections results in the (automatically occurring) phase adjustment by the TES RF signal generator 403 essentially returning to its original phase adjustment amount for the original voltage (the first voltage of state S1 before it was increased to compensate for edge ring wear). Thus, the phase adjustment amount for state S1 can be used to optimize the capacitance setting in the TES impedance matching system.

[0060] 2 shows a vertical cross-sectional view of a plasma processing system 100 for use in semiconductor chip manufacturing, according to some embodiments. The system 100 includes a chamber 101 formed by walls 101A, a top member 101B, and a bottom member 101C. The walls 101A, top member 101B, and bottom member 101C collectively form an interior region 103 within the chamber 101. The bottom member 101C includes an exhaust port 105 through which exhaust gases from a plasma processing operation are directed. In some embodiments, during operation, a suction force is applied at the exhaust port 105, such as by a turbo pump or other vacuum device, to draw process exhaust gases from the interior region 103 of the chamber 101. In some embodiments, the chamber 101 is formed of aluminum. However, in various embodiments, chamber 101 can be formed from essentially any material that provides sufficient mechanical strength and acceptable thermal performance, and that is chemically compatible with other materials it interfaces with and to which it is exposed during plasma processing operations within chamber 101, such as stainless steel, among others. At least one wall 101A of chamber 101 includes a door 107 through which semiconductor wafers W are transferred into and out of chamber 101. In some embodiments, door 107 is configured as a slit valve door.

[0061] In some embodiments, a semiconductor wafer W is a semiconductor wafer undergoing a fabrication process. For ease of discussion, a semiconductor wafer W is hereinafter referred to as a wafer W. However, it should be understood that in various embodiments, a wafer W can be essentially any type of substrate undergoing a plasma-based fabrication process. For example, in some embodiments, a wafer W referred to herein can be a substrate formed of silicon, sapphire, GaN, GaAs, or SiC, or other substrate materials, and can include a glass panel / substrate, a metal foil, a metal sheet, a polymeric material, etc. Also, in various embodiments, a wafer W referred to herein can vary in shape, shape, and / or size. For example, in some embodiments, a wafer W referred to herein can correspond to a circular semiconductor wafer on which integrated circuit devices are fabricated. In various embodiments, a circular wafer W can have a diameter of 200 mm (millimeters), 300 mm, 450 mm, or another size. Also, in some embodiments, a wafer W referred to herein can correspond to a non-circular substrate, such as a rectangular substrate for a flat panel display, among other shapes.

[0062] The plasma processing system 100 includes an electrode 109 disposed on a facility plate 111. In some embodiments, the electrode 109 and facility plate 111 are formed of aluminum. However, in other embodiments, the electrode 109 and facility plate 111 can be formed of another electrically conductive material that has sufficient mechanical strength and compatible thermal and chemical performance characteristics. A ceramic layer 110 is formed on the upper surface of the electrode 109. In some embodiments, the ceramic layer has a vertical thickness, measured perpendicular to the upper surface of the electrode 109, of approximately 1.25 millimeters (mm). However, in other embodiments, the ceramic layer 110 can have a vertical thickness greater or less than 1.25 mm. The ceramic layer 110 is configured to receive and support a wafer W during plasma processing operations on the wafer W. In some embodiments, the upper surface of the electrode 109 and the outer peripheral side of the electrode 109, which are located radially outward of the ceramic layer 110, are coated with a ceramic spray coat.

[0063] The ceramic layer 110 includes an arrangement of one or more clamping electrodes 112 for generating an electrostatic force to hold the wafer W against the upper surface of the ceramic layer 110. In some embodiments, the ceramic layer 110 includes an arrangement of two clamping electrodes 112 that operate in a bipolar configuration to provide a clamping force to the wafer W. The clamping electrodes 112 are connected to a direct current (DC) supply 117, which generates a controlled clamping voltage to hold the wafer W against the upper surface of the ceramic layer 110. Electrical wires 119A, 119B are connected between the DC supply 117 and the equipment plate 111. Electrical wires / conductors are routed through the equipment plate 111 and the electrodes 109 to electrically connect the electrical wires 119A, 119B to the clamping electrodes 112. The DC supply 117 is connected to a control system 120 through one or more signal conductors 121.

[0064] The electrode 109 also includes a configuration of temperature control fluid channels 123 through which a temperature control fluid flows to control the temperature of the electrode 109, and thereby the temperature of the wafer W. The temperature control fluid channels 123 are plumbed (fluidically connected) to ports on the fixture plate 111. Temperature control fluid supply and return lines connect to these ports on the fixture plate 111, as indicated by arrows 126, and to a temperature control fluid circulation system 125. The temperature control fluid circulation system 125 includes a temperature control fluid supply, a temperature control fluid pump, and a heat exchanger, among other devices, to provide a controlled flow of temperature control fluid through the electrode 109 to achieve and maintain a specified wafer W temperature. The temperature control fluid circulation system 125 is connected to the control system 120 through one or more signal conductors 127. In various embodiments, various types of temperature control fluids, such as water or cooling liquids / gases, can be used. Additionally, in some embodiments, the temperature control fluid channel 123 is configured to allow spatially varying control of the temperature of the wafer W, for example, control in two dimensions (x and y) across the wafer W.

[0065] Ceramic layer 110 also includes an arrangement of backside gas supply ports (not shown) that are fluidly connected to corresponding backside gas supply channels in electrode 109. The backside gas supply channels in electrode 109 are routed through electrode 109 to the interface between electrode 109 and facility plate 111. One or more backside gas supply lines connect to ports on facility plate 111, as indicated by arrow 130, and to a backside gas supply system 129. Facility plate 111 is configured to supply backside gas from the one or more backside gas supply lines to the backside gas supply channels in electrode 109. Backside gas supply system 129 includes, among other devices, a backside gas supply, a mass flow controller, and a flow control valve to provide a controlled flow of backside gas through the arrangement of backside gas supply ports in ceramic layer 110. In some embodiments, backside gas supply system 129 also includes one or more components for controlling the temperature of the backside gas. In some embodiments, the backside gas is helium. Additionally, in some embodiments, a backside gas supply system 129 may be used to supply clean dry air (CDA) to an arrangement of backside gas supply ports in the ceramic layer 110. The backside gas supply system 129 is connected to the control system 120 through one or more signal conductors 131.

[0066] Three lift pins 132 extend through the facility plate 111, the electrode 109, and the ceramic layer 110 to provide vertical movement of the wafer W relative to the upper surface of the ceramic layer 110. In some embodiments, the vertical movement of the lift pins 132 is controlled by corresponding electromechanical and / or pneumatic lifting devices 133 connected to the facility plate 111. The three lifting devices 133 are connected to the control system 120 through one or more signal conductors 134. In some embodiments, the three lift pins 132 are positioned with substantially equal azimuthal spacing about a vertical centerline of the electrode 109 / ceramic layer 110, which extends perpendicular to the upper surface of the ceramic layer 110. It should be understood that the lift pins 132 are raised to load the wafer W into the chamber 101 and to remove the wafer W from the chamber 101. The lift pins 132 are also lowered to allow the wafer W to rest on the upper surface of the ceramic layer 110 during processing of the wafer W.

[0067] Also, in various embodiments, one or more of the electrode 109, facility plate 111, ceramic layer 110, clamp electrode 112, lift pins 132, or essentially any other components associated therewith, can be equipped to include one or more sensors, such as sensors for temperature, voltage, and current measurements, among others. Any sensors located within the electrode 109, facility plate 111, ceramic layer 110, clamp electrode 112, lift pins 132, or essentially any other components associated therewith, connect to the control system 120 via electrical wires, optical fibers, or through a wireless connection.

[0068] The facility plate 111 is disposed within an opening in and supported by the ceramic support 113. The ceramic support 113 is disposed on a support surface 114 of a cantilever arm assembly 115. In some embodiments, the ceramic support 113 has a substantially annular shape, such that the ceramic support 113 substantially surrounds the radial periphery of the facility plate 111 while also providing a support surface 116 upon which a bottom peripheral surface of the facility plate 111 rests. The cantilever arm assembly 115 extends through a wall 101A of the chamber 101. In some embodiments, a sealing mechanism 135 is disposed within the wall 101A of the chamber 101 in which the cantilever arm assembly 115 is located to provide sealing of the interior region 103 of the chamber 101 while also allowing the cantilever arm assembly 115 to move upward and downward in a controlled manner in the z-direction.

[0069] The cantilever arm assembly 115 has an open area 118 through which various devices, wires, cables, and tubing are routed to support the operation of the system 100. The open area 118 in the cantilever arm assembly is exposed to ambient atmospheric conditions outside the chamber 101, such as air composition, temperature, pressure, and relative humidity. Also disposed within the cantilever arm assembly 115 is a radio frequency signal supply rod 137. More specifically, the radio frequency signal supply rod 137 is disposed within a conductive tube 139 such that the radio frequency signal supply rod 137 is spaced from the inner wall of the tube 139. The sizes of the radio frequency signal supply rod 137 and the tube 139 may vary. The area within the tube 139 between the inner wall of the tube 139 and the radio frequency signal supply rod 137 is occupied by air along the entire length of the tube 139. In some embodiments, the outer diameter (D rod ) and the inner diameter of the pipe 139 (D tube ) is related to the relation ln(D tube / D rod )≧e 1 is set to satisfy

[0070] In some embodiments, the radio frequency signal feed rod 137 is substantially centered within the tube 139, such that a substantially uniform radial thickness of air exists between the radio frequency signal feed rod 137 and the inner wall of the tube 139 along the length of the tube 139. However, in some embodiments, the radio frequency signal feed rod 137 is not centered within the tube 139, but rather an air gap exists within the tube 139 between the radio frequency signal feed rod 137 and the inner wall of the tube 139 everywhere along the length of the tube 139. The delivery end of the radio frequency signal feed rod 137 is electrically and physically connected to the lower end of the radio frequency signal feed shaft 141. In some embodiments, the delivery end of the radio frequency signal feed rod 137 is bolted to the lower end of the radio frequency signal feed shaft 141. The upper end of the radio frequency signal feed shaft 141 is electrically and physically connected to the bottom of the equipment plate 111. In some embodiments, the upper end of the radio frequency signal feed shaft 141 is bolted to the bottom of the equipment plate 111. In some embodiments, both the radio frequency signal feed rod 137 and the radio frequency signal feed shaft 141 are made of copper. In some embodiments, the radio frequency signal feed rod 137 is made of copper, aluminum, or anodized aluminum. In some embodiments, the radio frequency signal feed shaft 141 is made of copper, aluminum, or anodized aluminum. In other embodiments, the radio frequency signal feed rod 137 and / or the radio frequency signal feed shaft 141 are made of another conductive material that transmits high frequency electrical signals. In some embodiments, the radio frequency signal feed rod 137 and / or the radio frequency signal feed shaft 141 are coated with a conductive material that transmits high frequency electrical signals (e.g., silver or another conductive material). Also, in some embodiments, the radio frequency signal feed rod 137 is a solid rod. However, in other embodiments, the radio frequency signal feed rod 137 is a tube. It should also be understood that the region 140 surrounding the connection between the radio frequency signal feed rod 137 and the radio frequency signal feed shaft 141 is occupied by air.

[0071] The feed end of the radio frequency signal feed rod 137 is electrically and physically connected to an impedance matching system 143. The impedance matching system 143 is connected to a first radio frequency signal generator 147 and a second radio frequency signal generator 149. The impedance matching system 143 is also connected to the control system 120 through one or more signal conductors 144. The first radio frequency signal generator 147 is also connected to the control system 120 through one or more signal conductors 148. The second radio frequency signal generator 149 is also connected to the control system 120 through one or more signal conductors 150. The impedance matching system 143 includes an arrangement of inductors and capacitors sized and connected to provide an impedance match such that radio frequency power can be transmitted along the radio frequency signal feed rod 137, along the radio frequency signal feed shaft 141, through the equipment plate 111, through the electrode 109, and into the plasma processing region 182 above the ceramic layer 110. In some embodiments, the first high-frequency signal generator 147 is a high-frequency signal generator, and the second high-frequency signal generator 149 is a low-frequency signal generator. In some embodiments, the first high-frequency signal generator 147 generates a high-frequency signal in a range of about 50 megahertz (MHz) to about 70 MHz, or in a range of about 54 MHz to about 63 MHz, or about 60 MHz. In some embodiments, the first high-frequency signal generator 147 provides a high-frequency power in a range of about 5 kilowatts (kW) to about 25 kW, or in a range of about 10 kW to about 20 kW, or in a range of about 15 kW to about 20 kW, or about 10 kW, or about 16 kW. In some embodiments, the second high-frequency signal generator 149 generates a high-frequency signal in a range of about 50 kilowatts (kHz) to about 500 kHz, or in a range of about 330 kHz to 440 kHz, or about 400 kHz. In some embodiments, the second radio frequency signal generator 149 provides radio frequency power in the range of about 15 kW to about 100 kW, or in the range of about 30 kW to about 50 kW, or about 34 kW, or about 50 kW.In an exemplary embodiment, the first high frequency signal generator 147 is configured to generate a high frequency signal having a frequency of approximately 60 MHz, and the second high frequency signal generator 149 is configured to generate a high frequency signal having a frequency of approximately 400 kHz.

[0072] A coupling ring 161 is configured and arranged to extend around the radial outer periphery of the electrode 109. In some embodiments, the coupling ring 161 is formed of a ceramic material. A quartz ring 163 is configured and arranged to extend around the radial outer periphery of both the coupling ring 161 and the ceramic support 113. In some embodiments, when the quartz ring 163 is arranged around both the coupling ring 161 and the ceramic support 113, the coupling ring 161 and the quartz ring 163 are configured to have substantially aligned upper surfaces. In some embodiments, the substantially aligned upper surfaces of the coupling ring 161 and the quartz ring 163 are substantially aligned with the upper surface of the electrode 109, and the upper surface is outside the radial periphery of the ceramic layer 110. In some embodiments, a cover ring 165 is configured and arranged to extend around the radial outer periphery of the upper surface of the quartz ring 163. In some embodiments, the cover ring 165 is formed of quartz. In some embodiments, the cover ring 165 is configured to extend vertically above the upper surface of the quartz ring 163. Thus, the cover ring 165 provides a peripheral boundary within which the edge ring 167 is disposed.

[0073] The edge ring 167 is configured to facilitate extension of the plasma sheath radially outward beyond the outer peripheral edge of the wafer W to improve process results near the periphery of the wafer W. In various embodiments, the edge ring 167 is formed of a conductive material, such as crystalline silicon, polycrystalline silicon (polysilicon), boron-doped single crystal silicon, aluminum oxide, quartz, aluminum nitride, silicon nitride, a silicon carbide or silicon carbide layer on an aluminum oxide layer, or a silicon alloy, or a combination thereof, among other materials. It should be understood that the edge ring 167 is formed as an annular-shaped structure, e.g., a ring-shaped structure. The edge ring 167 can perform many functions, including shielding components below the edge ring 167 from damage by ions of the plasma 180 formed in the plasma processing region 182. The edge ring 167 also improves the uniformity of the plasma 180 at and along the outer peripheral region of the wafer W.

[0074] A fixed outer support flange 169 is attached to the cantilever arm assembly 115. The fixed outer support flange 169 is configured to extend around the outer vertical side of the ceramic support 113, around the outer vertical side of the quartz ring 163, and around the lower outer vertical side of the cover ring 165. The fixed outer support flange 169 has an annular shape that surrounds the assembly of the ceramic support 113, the quartz ring 163, and the cover ring 165. The fixed outer support flange 169 has an L-shaped vertical cross section including a vertical portion and a horizontal portion. The vertical portion of the L-shaped cross section of the fixed outer support flange 169 has an inner vertical surface that is positioned in contact with the outer vertical side of the ceramic support 113, the outer vertical side of the quartz ring 163, and the lower outer vertical side of the cover ring 165. In some embodiments, the vertical portion of the L-shaped cross section of the fixed outer support flange 169 extends over the entire outer vertical side surface of the ceramic support 113, the entire outer vertical side surface of the quartz ring 163, and the lower outer vertical side surface of the cover ring 165. In some embodiments, the cover ring 165 extends radially outward over the upper surface of the vertical portion of the L-shaped cross section of the fixed outer support flange 169. In some embodiments, the upper outer vertical side surface of the cover ring 165 (located above the upper surface of the vertical portion of the L-shaped cross section of the fixed outer support flange 169) is aligned substantially vertically with the outer vertical surface of the vertical portion of the L-shaped cross section of the fixed outer support flange 169. The horizontal portion of the L-shaped cross section of the fixed outer support flange 169 rests on and is fixed to the support surface 114 of the cantilever arm assembly 115. The fixed outer support flange 169 is formed of an electrically conductive material. In some embodiments, the fixed outer support flange 169 is formed of aluminum or anodized aluminum. However, in other embodiments, the fixed outer support flange 169 can be formed from another conductive material, such as copper or stainless steel. In some embodiments, the horizontal portion of the L-shaped cross section of the fixed outer support flange 169 is bolted to the support surface 114 of the cantilever arm assembly 115.

[0075] The articulating outer support flange 171 is constructed and arranged to extend around the outer vertical surface 169D of the vertical portion of the L-shaped cross section of the fixed outer support flange 169 and around the upper outer vertical side surface of the cover ring 165. The articulating outer support flange 171 has an annular shape that surrounds both the vertical portion of the L-shaped vertical cross section of the fixed outer support flange 169 and the upper outer vertical side surface of the cover ring 165. The articulating outer support flange 171 has an L-shaped vertical cross section that includes a vertical portion and a horizontal portion. The vertical portion of the L-shaped cross section of the articulating outer support flange 171 has an inner vertical surface that is adjacent to and spaced apart from both the outer vertical side surface of the vertical portion of the L-shaped cross section of the fixed outer support flange 169 and the upper outer vertical side surface of the cover ring 165. In this manner, the articulating outer support flange 171 is movable vertically (in the z-direction) along both the vertical portion of the L-shaped vertical cross section of the fixed outer support flange 169 and the upper outer vertical side surface of the cover ring 165. The articulating outer support flange 171 is formed of an electrically conductive material. In some embodiments, the articulating outer support flange 171 is formed of aluminum or anodized aluminum. However, in other embodiments, the articulating outer support flange 171 can be formed of another electrically conductive material, such as copper or stainless steel.

[0076] A plurality of conductive straps 173 are connected between the articulating outer support flange 171 and the fixed outer support flange 169 around the radial circumference of both the articulating outer support flange 171 and the fixed outer support flange 169. In the exemplary embodiment, the conductive straps 173 are shown as having an "outward" configuration in that the conductive straps 173 bend outward, away from the fixed outer support flange 169. In some embodiments, the conductive straps 173 are formed from stainless steel. However, in other embodiments, the conductive straps 173 can be formed from another conductive material, such as aluminum or copper, among others.

[0077] In some embodiments, 48 conductive straps 173 are substantially equally spaced around the radial circumference of the articulating outer support flange 171 and the fixed outer support flange 169. However, it should be understood that the number of conductive straps 173 can vary in different embodiments. In some embodiments, the number of conductive straps 173 is in the range of about 24 to about 80, or in the range of about 36 to about 60, or in the range of about 40 to about 56. In some embodiments, the number of conductive straps 173 is less than 24. In some embodiments, the number of conductive straps 173 is greater than 80. The number of conductive straps 173 can affect the uniformity of process results across the wafer W because it affects the ground return path of the high frequency signal around the periphery of the plasma processing region 182. Additionally, the size of the conductive straps 173 can vary in different embodiments.

[0078] In some embodiments, the conductive straps 173 are connected to the fixed outer support flange 169 by a clamping force applied by fastening the clamp ring 175 to the top surface of the horizontal portion of the L-shaped cross section of the fixed outer support flange 169. In some embodiments, the clamp ring 175 is bolted to the fixed outer support flange 169. In some embodiments, the bolts securing the clamp ring 175 to the fixed outer support flange 169 are located between the conductive straps 173. However, in some embodiments, one or more bolts securing the clamp ring 175 to the fixed outer support flange 169 can be located to extend through the conductive straps 173. In some embodiments, the clamp ring 175 is formed from the same material as the fixed outer support flange 169. However, in other embodiments, the clamp ring 175 and the fixed outer support flange 169 can be formed from different materials.

[0079] In some embodiments, the conductive straps 173 are connected to the articulating outer support flange 171 by a clamping force applied by fastening a clamp ring 177 to the bottom surface of the horizontal portion of the L-shaped cross section of the articulating outer support flange 171. Alternatively, in some embodiments, a first end portion of each of the plurality of conductive straps 173 is connected to the top surface of the horizontal portion of the articulating outer support flange 171 by a clamp ring 177. In some embodiments, the clamp ring 177 is bolted to the articulating outer support flange 171. In some embodiments, the bolts securing the clamp ring 177 to the articulating outer support flange 171 are located at locations between the conductive straps 173. However, in some embodiments, one or more bolts securing the clamp ring 177 to the articulating outer support flange 171 can be positioned to extend through the conductive straps 173. In some embodiments, the clamp ring 177 is formed of the same material as the articulating outer support flange 171. However, in other embodiments, the clamp ring 177 and the articulating outer support flange 171 may be formed from different materials.

[0080] A set of support rods 201 are disposed around the cantilever arm assembly 115 and extend vertically through the horizontal portion 169B of the L-shaped cross section of the fixed outer support flange 169. The upper ends of the support rods 201 are configured to engage the bottom surface of the horizontal portion of the L-shaped cross section of the articulating outer support flange 171. In some embodiments, the lower end of each support rod 201 is engaged with a resistance mechanism 203. The resistance mechanism 203 is configured to provide an upward force to the corresponding support rod 201 that resists downward movement of the support rod 201, while still allowing some downward movement of the support rod 201. In some embodiments, the resistance mechanism 203 includes a spring to provide the upward force to the corresponding support rod 201. In some embodiments, the resistance mechanism 203 includes a material having a sufficient spring constant, such as a spring and / or rubber, to provide the upward force to the corresponding support rod 201. It should be appreciated that as the articulating outer support flange 171 moves downward to engage the set of support rods 201, the set of support rods 201 and corresponding resistance mechanisms 203 provide an upward force on the articulating outer support flange 171. In some embodiments, the set of support rods 201 includes three support rods 201 and corresponding resistance mechanisms 203. In some embodiments, the support rods 201 are arranged at substantially equal azimuthal spacing relative to the vertical centerline of the electrodes 109. However, in some embodiments, the support rods 201 are arranged at unequal azimuthal spacing relative to the vertical centerline of the electrodes 109. Also, in some embodiments, more than two support rods 201 and corresponding resistance mechanisms 203 are provided to support the articulating outer support flange 171.

[0081] Referring again to FIG. 2 , the plasma processing system 100 further includes a C-shroud member 185 disposed above the electrode 109. The C-shroud member 185 is configured to interface with the articulating outer support flange 171. Specifically, a seal 179 is disposed on an upper surface of the horizontal portion of the L-shaped cross section of the articulating outer support flange 171, such that the C-shroud member 185 engages with the seal 179 when the articulating outer support flange 171 moves upward toward the C-shroud member 185. In some embodiments, the seal 179 is conductive to help establish electrical conductivity between the C-shroud member 185 and the articulating outer support flange 171. In some embodiments, the C-shroud member 185 is formed of polysilicon. However, in other embodiments, the C-shroud member 185 is formed of another type of conductive material that is chemically compatible with processes performed in the plasma processing region 182 and has sufficient mechanical strength.

[0082] The C-shroud extends around the plasma processing region 182 and is configured to provide a radial extension of the plasma processing region 182 volume into the region defined within the C-shroud member 185. The C-shroud member 185 includes a lower wall 185A, an outer vertical wall 185B, and an upper wall 185C. In some embodiments, the outer vertical wall 185B and the upper wall 185C of the C-shroud member 185 are solid, non-perforated members, and the lower wall 185A of the C-shroud member 185 includes a plurality of vent holes 186 through which process gas flows from within and out of the plasma processing region 182. In some embodiments, a throttle member 196 is disposed below the vent holes 186 in the C-shroud member 185 to control the flow of process gas through the vent holes 186. More specifically, in some embodiments, the throttle member 196 is configured to move up and down perpendicular to the z-direction relative to the C-shroud member 185 to control the flow of process gas through the vent opening 186. In some embodiments, the throttle member 196 is configured to engage and / or enter the vent opening 186.

[0083] The upper wall 185C of the C shroud member 185 is configured to support the upper electrodes 187A / 187B. In some embodiments, the upper electrodes 187A / 187B include an inner upper electrode 187A and an outer upper electrode 187B. Alternatively, in some embodiments, the inner upper electrode 187A is present and the outer upper electrode 187B is absent, with the inner upper electrode 187A extending radially to cover the location that would be occupied by the outer upper electrode 187B. In some embodiments, the inner upper electrode 187A is formed of single crystal silicon and the outer upper electrode 187B is formed of polysilicon. However, in other embodiments, the inner upper electrode 187A and the outer upper electrode 187B can be formed of other materials that are structurally, chemically, electrically, and mechanically compatible with the processes performed in the plasma processing region 182. The inner upper electrode 187A includes a plurality of through ports 197, defined as holes extending through the entire vertical thickness of the inner upper electrode 187A. Through ports 197 are distributed throughout the inner upper electrode 187A relative to the xy plane to provide process gas flow from the plenum region 188 above the upper electrodes 187A / 187B to the plasma processing region 182 below the upper electrodes 187A / 187B.

[0084] It should be understood that the distribution of the through ports 197 throughout the inner upper electrode 187A can be configured differently in different embodiments. For example, the total number of through ports 197 in the inner upper electrode 187A and / or the spatial distribution of the through ports 197 in the inner upper electrode 187A can vary between different embodiments. Also, the diameter of the through ports 197 can vary between different embodiments. Generally, it is of interest to reduce the diameter of the through ports 197 to a size small enough to prevent the plasma 180 from penetrating into the through ports 197 from the plasma processing region 182. In some embodiments, as the diameter of the through ports 197 is reduced, the total number of through ports 197 in the inner upper electrode 187A is increased to maintain a specified overall flow rate of process gas from the process gas plenum region 188 through the inner upper electrode 187A and into the plasma processing region 182. Also, in some embodiments, the upper electrodes 187A / 187B are electrically connected to a reference ground potential. However, in other embodiments, the inner upper electrode 187A and / or the outer upper electrode 187B are electrically connected to a corresponding direct current (DC) power supply or a corresponding radio frequency power supply via a corresponding impedance matching circuit.

[0085] A plenum region 188 is defined by a top element 189. One or more gas supply ports 192 are formed through the chamber 101 and the top element 189 so as to be in fluid communication with the plenum region 188. The one or more gas supply ports 192 are fluidly connected (plumbed) to a process gas supply system 191. The process gas supply system 191 includes, among other devices, one or more process gas supplies, one or more mass flow controllers, and one or more flow control valves to provide a controlled flow of one or more process gases through the one or more gas supply ports 192 to the plenum region 188, as indicated by arrows 193. In some embodiments, the process gas supply system 191 also includes one or more components for controlling the temperature of the process gas. The process gas supply system 191 is connected to the control system 120 through one or more signal conductors 194.

[0086] The process gap (g1) is defined as the vertical (z-direction) distance measured between the top surface of the ceramic layer 110 and the bottom surface of the inner upper electrode 187A. The size of the process gap (g1) can be adjusted by moving the cantilever arm assembly 115 vertically (z-direction). As the cantilever arm assembly 115 moves upward, the articulating outer support flange 171 eventually engages the bottom wall 185A of the C-shroud member 185, at which point, as the cantilever arm assembly 115 continues to move upward, the articulating outer support flange 171 moves along the fixed outer support flange 169 until a set of support rods 201 engages the articulating outer support flange 171 and the specified process gap (g1) size is achieved. To then reverse this movement to remove the wafer W from the chamber, the cantilever arm assembly 115 is moved downward until the articulating outer support flange 171 moves away from the lower wall 185A of the C-shroud member 185. In various embodiments, the size of the processing gap (g1) during plasma processing of the wafer W is controlled in a range of up to about 10 centimeters, or up to about 8 centimeters, or up to about 5 centimeters. It should be understood that Figure 2 shows the system 100 in a closed configuration, with the wafer W on the ceramic layer 110 in position for plasma processing.

[0087] During plasma processing operations in the plasma processing system 100, one or more process gases are supplied to the plasma processing region 182 via the process gas supply system 191, the plenum region 188, and the through-ports 197 in the inner upper electrode 187A. A radio frequency signal is also transmitted to the plasma processing region 182 via the first and second radio frequency signal generators 147, 149, the impedance matching system 143, the radio frequency signal supply rod 137, the radio frequency signal supply shaft 141, the fixture plate 111, the electrode 109, and through the ceramic layer 110. The radio frequency signal converts the process gases in the plasma processing region 182 into a plasma 180. Ions and / or reactive components of the plasma interact with one or more materials on the wafer W, changing the composition and / or shape of certain materials on the wafer W. Exhaust gases from the plasma processing region 182, under the influence of the suction force applied at the exhaust port 105, flow through the vent 186 in the C-shroud member 185, through the inner region 103 in the chamber 101, and to the exhaust port 105, as shown by arrows 195.

[0088] In various embodiments, the electrode 109 can be configured to have different diameters. However, in some embodiments, the diameter of the electrode 109 is extended to increase the surface of the electrode 109 upon which the edge ring 167 rests. In some embodiments, a conductive gel 226 is disposed between the bottom of the edge ring 167 and the top of the electrode 109, and / or between the bottom of the edge ring 167 and the top of the coupling ring 161. In these embodiments, the increased diameter of the electrode 109 increases the surface area upon which the conductive gel is disposed between the edge ring 167 and the electrode 109.

[0089] It should be understood that the combination of the articulating outer support flange 171, the conductive straps 173, and the fixed outer support flange 169 are electrically at a reference ground potential and collectively form a ground return path for radio frequency signals transmitted from the electrode 109 through the ceramic layer 110 and into the plasma processing region 182. The azimuthal uniformity of this ground return path around the periphery of the electrode 109 can affect the uniformity of process results on the wafer W. For example, in some embodiments, the uniformity of the etch rate across the wafer W can be affected by the azimuthal uniformity of the ground return path around the periphery of the electrode 109. To this end, it should be understood that the number, configuration, and placement of the conductive straps 173 around the periphery of the electrode 109 can affect the uniformity of process results across the wafer W.

[0090] Referring again to FIG. 2 , an adjustable edge sheath (TES) system is implemented to include a TES electrode 415 disposed (embedded) within the coupling ring 161. The TES system also includes multiple TES radio frequency signal supply pins 413 that are physically and electrically connected to the TES electrode 415. Each TES radio frequency signal supply pin 413 extends through a corresponding insulator feedthrough member 421 configured to electrically isolate the TES radio frequency signal supply pin 413 from surrounding structures, such as the ceramic support 113 and cantilever arm assembly 115 structures. In some embodiments, O-rings 417 and 419 are positioned to ensure that the area within the insulator feedthrough member 421 is not exposed to any materials / gases present within the plasma processing region 182. In some embodiments, the TES radio frequency signal supply pins 413 are formed of copper, aluminum, or anodized aluminum, among others.

[0091] The TES radio frequency signal supply pins 413 extend into the open region 118 within the cantilever arm assembly 115, and each of the TES radio frequency signal supply pins 413 is electrically connected to the TES radio frequency signal supply conductor 409 through a corresponding TES radio frequency signal filter 411. In some embodiments, three TES radio frequency signal supply pins 413 are positioned to physically and electrically connect to the TES electrodes 415 at substantially equally spaced azimuthal locations around the centerline of the electrode 109. However, it should be understood that other embodiments may have more than two TES radio frequency signal supply pins 413 physically and electrically connect to the TES electrodes 415. Also, some embodiments may have either one or two TES radio frequency signal supply pins 413 physically and electrically connect to the TES electrodes 415. Each TES radio frequency signal supply pin 413 is electrically connected to a corresponding TES radio frequency signal filter 411, and each TES radio frequency signal filter 411 is electrically connected to the TES radio frequency signal supply conductor 409. In some embodiments, each TES radio frequency signal filter 411 is configured as an inductor. For example, in some embodiments, each TES radio frequency signal filter 411 is configured as a coiled conductor, such as a metal coil wound around a dielectric core structure. In various embodiments, the metal coil can be formed from a solid copper rod, copper tubing, aluminum rod, or aluminum tubing, among others. Also, in some embodiments, each TES radio frequency signal filter 411 can be configured as a combination of inductive and capacitive structures. To improve uniformity of plasma processing results across the wafer W, each of the TES radio frequency signal filters 411 has substantially the same configuration.

[0092] In some embodiments, the TES high frequency signal feed conductor 409 is formed as a ring-shaped structure that extends around the interior open area 118 of the cantilever arm assembly 115, allowing for physical and electrical connection between the azimuthally distributed TES high frequency signal filter 411 and the TES high frequency signal feed conductor 409. In some embodiments, the TES high frequency signal feed conductor 409 is formed as a solid (non-tubular) structure. Alternatively, in some embodiments, the TES high frequency signal feed conductor 409 is formed as a tubular structure. In some embodiments, the TES high frequency signal feed conductor 409 is formed of copper, aluminum, or anodized aluminum, among others.

[0093] The TES high frequency signal feed conductor 409 is electrically connected to the TES high frequency feed cable 407. Additionally, the capacitor 408 is connected between the TES high frequency signal feed conductor 409 and a reference ground potential, such as the structure of the cantilever arm assembly 115. More specifically, the capacitor 408 has a first end electrically connected to both the TES high frequency feed cable 407 and the TES high frequency signal feed conductor 409, and the capacitor 408 has a second end electrically connected to the reference ground potential. In some embodiments, the capacitor 408 is a variable capacitor. In some embodiments, the capacitor 408 is a fixed capacitor. In some embodiments, the capacitor 408 is configured to have a capacitance within a range ranging from approximately 10 picofarads to approximately 100 picofarads. The TES high frequency feed cable 407 is connected to the TES impedance matching system 401. The TES impedance matching system 401 is connected to the TES high frequency signal generator 403. The radio frequency signal generated by the TES radio frequency signal generator 403 is transmitted through the TES impedance matching system 401 to the TES radio frequency feed cable 407, then to the TES radio frequency signal feed conductor 409, then through the TES radio frequency signal filter 411 to the corresponding TES radio frequency signal feed pin 413, and then to the TES electrode 415 in the coupling ring 161. In some embodiments, the TES radio frequency signal generator 403 is configured and operated to generate a radio frequency signal within a frequency range extending from about 50 kilohertz to about 27 MHz. In some embodiments, the TES radio frequency signal generator 403 provides radio frequency power within a range extending from about 50 watts to about 10 kilowatts. The TES radio frequency signal generator 403 is also connected to the control system 120 through one or more signal conductors 405.

[0094] The TES impedance matching system 401 includes an arrangement of inductors and capacitors sized and connected to provide impedance matching so that radio frequency power can be transmitted from the TES radio frequency signal generator 403, along the TES radio frequency supply cable 407, along the TES radio frequency signal supply conductor 409, through the TES radio frequency signal filter 411, through the corresponding TES radio frequency signal supply pin 413, to the TES electrode 415 in the coupling ring 161, and into the plasma processing region 182 above the edge ring 167. FIG. 3 shows an exemplary circuit schematic of the TES impedance matching system 401, according to some embodiments. The TES impedance matching system 401 includes an input line 321 electrically connected to the TES radio frequency signal generator 403. The TES input line 321 is electrically connected to an input terminal of a first inductor 322. The output terminal of the first inductor 322 is electrically connected to an internal node 328. A second inductor 324 has an input terminal electrically connected to the internal node 328. The output terminal of the second inductor 324 is electrically connected to the second internal node 329. The first capacitor 326 has an input terminal electrically connected to the second internal node 329. The output terminal of the first capacitor 326 is electrically connected to the input terminal of the third inductor 327. The output terminal of the third inductor 327 is electrically connected to the TES high-frequency supply cable 407. The second capacitor 323 has an input terminal electrically connected to the first internal node 328. The second capacitor 323 has an output terminal electrically connected to the reference ground potential. In some embodiments, the second capacitor 323 is a variable capacitor. The third capacitor 325 has an input terminal electrically connected to the second internal node 329. The third capacitor 325 has an output terminal electrically connected to the reference ground potential. It should be understood that the electrical configuration of the TES impedance matching system 401 shown in FIG. 3 is provided by way of example. In other embodiments, the TES impedance matching system 401 may have different configurations of inductors and / or capacitors than the example shown in FIG.The TES impedance matching system 401 also connects to the control system 120 through one or more signal conductors 404 .

[0095] By transmitting a radio frequency signal / power through the TES electrode 415 disposed (embedded) in the coupling ring 161, the TES system can control the characteristics of the plasma 180 near the peripheral edge of the wafer W. For example, in some embodiments, the TES system is operated to control the characteristics of the plasma 180 sheath near the edge ring 167 by controlling the shape and / or size (either by increasing the sheath thickness or decreasing the sheath thickness) of the plasma 180 sheath. Also, in some embodiments, controlling the shape of the plasma 180 sheath near the edge ring 167 can control various characteristics of the bulk plasma 180 above the wafer W. Also, in some embodiments, the TES system is operated to control the density of the plasma 180 near the edge ring 167. For example, in some embodiments, the TES system is operated to increase or decrease the density of the plasma 180 near the edge ring 167. Additionally, in some embodiments, the TES system is operated to control a bias voltage present on the edge ring 167, which in turn controls / influences the movement of ions and other charged components in the plasma 180 near the edge ring 167. For example, in some embodiments, the TES system is operated to control a bias voltage present on the edge ring 167 to attract more ions from the plasma 180 toward the edge of the wafer W. And, in some embodiments, the TES system is operated to control a bias voltage present on the edge ring 167 to repel ions from the plasma 180 away from the edge of the wafer W. It should be understood that the TES system can be operated to perform a variety of different functions, particularly those described above, either separately or in combination.

[0096] In some embodiments, the coupling ring 161 is formed of a dielectric material, such as quartz, or a ceramic, or alumina (Al 2 O 3 ), or a polymer, among others.

[0097] The bottom surface of the edge ring 167 has a portion bonded to the top surface of the coupling ring 161 via a layer of thermally and electrically conductive gel, making the edge ring 167 a heat sink for the coupling ring 161. The bottom surface of the edge ring 167 also has another portion bonded to the top surface of the electrode 109 via a layer of thermally and electrically conductive gel. Examples of thermally and electrically conductive gels include polyimide, polyketone, polyetherketone, polyethersulfone, polyethylene terephthalate, fluoroethylene propylene copolymer, cellulose, triacetate, and silicone, among others. In some embodiments, the thermally and electrically conductive gel is formed as a double-sided tape. In some embodiments, the edge ring 167 has an inner diameter sized to closely match the outer diameter of the ceramic layer 110.

[0098] In various embodiments, the TES electrode 415 is formed of a conductive material, such as platinum, steel, aluminum, or copper, among others. In operation, capacitive coupling occurs between the TES electrode 415 and the edge ring 167, such that the edge ring 167 is powered and affects processing of the wafer W near the periphery of the wafer W.

[0099] FIG. 4 conceptually illustrates components of a TES radio frequency signal generator 403 according to an implementation of the present disclosure. FIG. 5 is a graph illustrating various states of a (multi-state / pulse) TES radio frequency signal generated by the TES radio frequency signal generator 403 and applied to a TES electrode according to an implementation of the present disclosure. With reference to both FIG. 4 and FIG. 5, the various states of the (multi-state / pulse) TES radio frequency (RF) signal and the corresponding operation of the TES radio frequency signal generator 403 to achieve the various states are now described.

[0100] 5 illustrates voltage set points versus time for the TES RF signal generated by the TES RF signal generator 403 in accordance with an implementation of the present disclosure. As shown, the TES RF signal is defined to have a three-state pulse RF cycle, with states S1, S0, and S2 periodically repeating in sequence. In the implementation shown, state S0 precedes state S2, but in other implementations, these orders are reversed, e.g., state S2 precedes state S0. As shown, each state has a voltage set point that defines the target voltage achieved by the TES RF signal generator 403 for that state.

[0101] For state S1 of the TES RF signal, the voltage set point is Vs1, which in some implementations is configured to provide a high aspect ratio etch. For state S0 of the TES RF signal, the voltage set point is Vs0, which in some implementations is configured to induce passivation. For state S2 of the TES RF signal, the voltage set point is Vs2, which in some implementations is configured to promote dissociation and neck opening in the feature.

[0102] As can be seen, the voltage set points for states S0 and S2 are lower than the voltage set point for state S1. Therefore, to efficiently realize a three-state pulsed TES RF signal, TES RF signal generator 403 uses a single power amplifier 431 to control the RF output power to achieve the voltage set point for state S1 (Vs1) and utilizes drive actuators 433 and 435 to selectively attenuate the RF output to achieve the voltage set points for states S0 and S2 (Vs0 and Vs2). The output level of power amplifier 431 is adjusted to generate an RF signal according to the voltage set point for S1, which is Vs1. In some implementations, the RF signal from power amplifier 431 further includes additional voltage states that are lower than Vs1 but not too low to achieve the desired voltage set points Vs0 and Vs2. To fully generate state S0 for the TES RF signal, drive actuator 433 is configured to selectively attenuate the relevant portion of the power amplifier's signal by an attenuation amount D1 to achieve the voltage set point Vs0 for S0. Similarly, to fully generate state S2, drive actuator 435 is configured to selectively attenuate relevant portions of the power amplifier signal by an attenuation amount D2 to achieve voltage setpoint Vs2 for S2. Thus, according to implementations of the present disclosure, the voltage levels of states S0 and S2 are achieved by attenuating the power amplifier output as necessary to achieve voltage setpoints Vs0 and Vs2.

[0103] While the voltages of each state are related as described above, the phase of each state can be independently controlled according to implementations of the present disclosure. Broadly speaking, it is optimal to match the phase of each state of the pulsed TES RF signal to the phase of the corresponding state of the pulsed RF signal applied to electrode 109 by RF signal generator 149. That is, the phase of state S1 of the TES RF signal (generated by RF signal generator 403) is adjusted to match the phase of state S1 of the bias RF signal (generated by RF signal generator 149), the phase of state S0 of the TES RF signal (generated by RF signal generator 403) is adjusted to match the phase of state S0 of the bias RF signal (generated by RF signal generator 149), and the phase of state S2 of the TES RF signal (generated by RF signal generator 403) is adjusted to match the phase of state S2 of the bias RF signal (generated by RF signal generator 149).

[0104] According to an implementation of the present disclosure, the TES RF signal generator 403 is configured to automatically and independently adjust the phase of various states of its generated TES RF signal to align with the phase of corresponding states of the RF signal generated by the RF signal generator 149. To achieve this, the TES RF signal generator 403 includes a phase actuator 437 for state S1, a phase actuator 439 for state S0, and a phase actuator 441 for state S2. The phase actuator 437 applies a phase adjustment PA1 to automatically adjust the phase of state S1 in the TES RF signal to align with the corresponding state S1 in the RF signal generated by the RF signal generator 149 for the electrode 109. The phase actuator 439 applies a phase adjustment PA2 to automatically adjust the phase of state S0 in the TES RF signal to align with the corresponding state S0 in the RF signal generated by the RF signal generator 149 for the electrode 109. The phase actuator 441 applies a phase adjustment PA3 to automatically adjust the phase of the state S2 in the TES RF signal to match the corresponding state S2 in the RF signal generated by the radio frequency signal generator 149 to the electrode 109.

[0105] In some implementations, the voltage set point for state S1 applied to the TES electrode 415 is increased to compensate for wear on the edge ring 167 over accumulated RF time. The TES radio frequency signal generator 403 is then automatically adjusted accordingly to maintain phase alignment with state S1 of the radio frequency signal from the radio frequency signal generator 149. As noted, it has been discovered that adjusting the capacitance setting in the TES impedance matching system 401 to minimize reflections of radio frequency power in state S1 results in the (automatically occurring) phase adjustment by the TES radio frequency signal generator 403 essentially returning to its original phase adjustment amount for the original voltage (the first voltage for state S1 before being increased to compensate for edge ring wear). Therefore, the phase adjustment amount for state S1 can be used to optimize the capacitance setting of the variable capacitor 323 in the TES impedance matching system 401.

[0106] However, in accordance with implementations of the present disclosure, the capacitance setting in the TES impedance matching system 401 sets the capacitance C1 that is applied to all of the states S1, S0, and S2 of the pulsed TES RF signal. As discussed further below, such changes in the capacitance setting of the TES impedance matching system also affect the relationship between the voltage set points for states S0 and S2 and the tolerance ranges of the voltage set points for these states. Accordingly, it may be desirable to optimize the voltage set points for states S0 and S2 in response to changes in the capacitance setting.

[0107] FIG. 6 is a graph conceptually illustrating the allowable voltage set point range for states S0 or S2 according to an implementation of the present disclosure. More specifically, the allowable voltage set point range is shown by the vertical bars as a function of the capacitor tap position of the variable capacitor 323 in the TES impedance matching system 401. Roughly speaking, as the voltage set point for state S1 changes, the capacitor tap position is changed accordingly, for example, to minimize reflected power from state S1. However, as noted above, states S0 and S2 depend on the voltage for state S1 in that the voltages for states S0 and S2 are achieved by the drive actuator attenuating the power amplifier output. This is set by the TES RF signal generator when controlling the voltage set point for state S1. The expected voltage set point range for states S0 and S2 is determined by the voltage for state S1 and the ability of the drive actuator to attenuate the power amplifier output. The maximum or upper limit of the voltage set point for states S0 / S2 is determined by the voltage set point for state S1. This is because the power amplifier output used to control state S1 to its fully unattenuated amount is the maximum output power expected for states S0 / S2. The minimum or lower limit of the voltage setpoint for S0 / S2 is determined by the amount of attenuation possible by the drive actuator of TES RF signal generator 403. Thus, the range of allowable voltage setpoints is bounded by the output power required to control state S1 and the amount the drive actuator can attenuate the power amplifier output.

[0108] As previously mentioned, if the voltage set point for state S1 is increased, for example to compensate for edge ring wear, the capacitor tap position of variable capacitor 323 of TES impedance matching system 401 is adjusted to minimize reflected power. Accordingly, as the voltage set point for state S1 changes with edge ring wear, the tolerance range of the voltage set points for states S0 / S2 changes with the change in capacitor tap position, as shown in FIG.

[0109] However, such a shift in the acceptable range of voltage set points presents a challenge in how to adjust the voltage set points for states S0 and S2. For example, if the voltage set point for state S1 changes and the capacitor tap position also changes, the change in the acceptable range of the voltage set point for state S0 may result in the existing voltage set point for state S0 no longer being within the acceptable range, and as a result, the system would not be able to achieve the existing voltage set point for state S0. A similar change in the acceptable range of the voltage set point for state S2 may also result in the existing voltage set point for state S2 no longer being within the acceptable range, and as a result, the system would not be able to achieve the existing voltage set point for state S2. Additionally, even if the existing voltage set point for either state S0 or S2 is still within the acceptable range, it may be at the edge of the range of acceptable values, thereby limiting the freedom to adjust the voltage set point as needed to optimize a given recipe.

[0110] For example, still referring to Figure 6, the existing voltage set point for S0 / S2 is V1. When the capacitor tap position is at P5, the voltage set point V1 is approximately in the middle of the tolerance range 600 of acceptable voltage set points. This provides latitude to adjust the voltage set point up or down if needed for recipe optimization.

[0111] However, if the voltage set point for state S1 is increased, resulting in a change in capacitor tap position to P4, the acceptable range of the voltage set point for states S0 / S2 changes to acceptable range 602, which is roughly an increase from the previous acceptable range 600. At this stage, the existing voltage set point V1 for S0 / S2 is still within acceptable range 602. However, V1 is now near the bottom of the current acceptable range 602, and as a result, there is very limited freedom to further reduce the voltage set point, if necessary. This can be problematic for recipe development, because a user may attempt to adjust the voltage set point in this manner and find that they are unable to do so.

[0112] If the voltage set point for state S1 is further increased, so that the capacitor tap position then changes to P3, the acceptable range of voltage set points for states S0 / S2 changes to acceptable range 604, which is roughly an increase from the previous acceptable range 602. This presents an unsatisfactory scenario in that the existing S0 / S2 voltage set point V1 is now no longer within the current acceptable range 604 of voltage set points. In other words, when the capacitor tap position is at P3, the system cannot achieve the existing set point V1. In such a scenario, by way of non-limiting example, the system may generate an error indicating that the voltage set point is outside the acceptable range.

[0113] Therefore, as the voltage set point for state S1 changes and the capacitor tap position changes, it may be desirable to adjust the voltage set points for states S0 / S2. For example, if the capacitor tap position changes to P4, it may be desirable to change the S0 / S2 voltage set point to V2 to maintain the S0 / S2 voltage set point at or near the middle of tolerance range 602. Similarly, if the capacitor tap position changes to P3, it may be desirable to change the S0 / S2 voltage set point to V3 to maintain the S0 / S2 voltage set point at or near the middle or intermediate portion of tolerance range 604.

[0114] It has been unexpectedly discovered that a voltage setpoint for states S0 / S2 that is approximately midway through the tolerance range for any given capacitor tap setting across the entire range of capacitor tap settings results in a substantially constant or identical phase adjustment (automatically set by TES RF signal generator 403 for states S0 / S2) across the entire range of capacitor tap settings. In other words, if the capacitor tap setting is changed in response to a change in the voltage setpoint for state S1, and the resulting phase adjustment is approximately the same phase adjustment that existed before the capacitor tap setting was changed, then the voltage setpoint for states S0 / S2 will be approximately midway through the (new) tolerance range. Thus, when the capacitor tap setting is changed, a target phase adjustment can be defined and utilized to determine the appropriate voltage setpoint for states S0 / S2. It should be understood that states S0 and S2 are referred to alternatively herein, and thus the target phase adjustment for state S0 can be the same as or different from the target phase adjustment for state S2.

[0115] 7 is a graph conceptually illustrating the relationship between the phase adjustment for states S0 / S2 and the voltage set point for states S0 / S2, according to an implementation of the present disclosure. In the implementation shown, curve 700 illustrates the phase adjustment for a given capacitor tap position as described above as a function of the voltage set point for states S0 / S2. The voltage set point tolerance range 602 is indicated by the width of curve 700 along the horizontal axis, which represents the voltage set value.

[0116] Point 706 along curve 700 represents the maximum voltage set point Vmax as defined by the voltage in state S1, as previously described. Point 702 along curve 700 represents the minimum voltage set point Vmin, which may be based on the amount of power attenuation allowed by the drive actuator of TES RF signal generator 403. The allowed voltage set point range 602 also corresponds to a phase adjustment range 710. As shown, when the voltage set point is adjusted to Vc, which is approximately in the middle or midpoint of the allowed voltage set point range 602 and corresponds to point 704 along curve 700, the amount of phase adjustment is PA TAn unexpected result is that when the voltage set point is adjusted to approximately the middle of the voltage set point tolerance range, this phase adjustment amount PA T was found to be approximately the same for all capacitor tap settings.

[0117] Therefore, P.A. T defines a target phase adjustment that can be used to automatically adjust the voltage set point for states S0 / S2 so that it remains approximately in the middle of an acceptable range of voltage set points. In response to changes in the voltage set point for state S1, and the resulting changes in the capacitor tap settings, the phase adjustment for states S0 / S2 may reach the target phase adjustment or may fall within a predetermined range of the target phase adjustment (e.g., PA T The voltage set points for states S0 / S2 are adjusted until the target phase adjustment is within x degrees of the tolerance range. As noted, states S0 and S2 may have the same or different target phase adjustment amounts, each configured to allow the corresponding voltage set point to remain approximately in the middle of the tolerance range.

[0118] In some implementations, a target phase adjustment range 708 is defined, and the voltage set points for states S0 / S2 are adjusted until the phase adjustment amount for states S0 / S2 falls within the target phase adjustment range. It will be appreciated that the target phase adjustment range is configured such that the corresponding voltage set point range (the phase adjustment that results in falling within the target phase adjustment range) is approximately in the middle of the allowable voltage set point range. It will be appreciated that states S0 and S2 may have the same or different target phase adjustment ranges.

[0119] FIG. 8 conceptually illustrates a method for maintaining a voltage set point within a general mid-range of acceptable voltage set points for a state of a pulsed RF signal, according to an implementation of the present disclosure. In method operation 801, a target phase adjustment range (or amount) is defined for a given state of the pulsed RF signal. The target phase adjustment range is configured to be the range of phase adjustment amounts obtained when the voltage set point for the given state is within the mid / center range of acceptable voltage set points. As previously described, phase adjustment is automatically performed by the TES RF signal generator to minimize the phase difference / delta with the (main) RF signal applied to the electrode 109 for the given state. Thus, as the voltage set point changes, the phase adjustment also automatically changes to minimize the phase difference. Thus, the range of acceptable voltage set points corresponds to the range of phase adjustment, and it has been unexpectedly discovered that the target phase adjustment range / amount resulting from a voltage set point in the middle of that acceptable range is approximately constant or the same for different capacitance settings in the TES impedance matching system 401.

[0120] At method operation 803, the phase adjustment amount automatically determined by the TES RF signal generator is monitored for a given state, e.g., state S0 or state S2. At method operation 805, it is determined whether the phase adjustment amount is within a target phase adjustment range. If yes, the method returns to method operation 803 for continued monitoring of the phase adjustment amount.

[0121] If no, then the voltage set point for the given state, e.g., state S0 or state S2, is adjusted in method operation 807. The method then returns to method operations 803 and 805 to continue monitoring the phase adjustment amount and again determine whether the phase adjustment amount is within the target phase adjustment range. It will be appreciated that if the phase adjustment amount is within the target phase adjustment range, then the voltage set point will be approximately in the middle / center range of acceptable voltage set points for the current situation.

[0122] 9 is a graph conceptually illustrating the change in voltage set point for various states of a pulsed RF signal, in accordance with an implementation of the present disclosure. Voltage set points for states S1, S0, and S2 are shown as a function of accumulated RF time of the edge ring. Curve 901 shows the voltage set point for state S1. As can be seen, as RF time accumulates, the voltage set point for state S1 is periodically increased to compensate for edge ring wear and maintain plasma sheath height and characteristics in the edge region.

[0123] In accordance with the method of the present disclosure, the voltage set points for state S2 (represented by curve 903) and state S0 (represented by curve 905) are also increased in steps in coordination with the step change in the voltage set point for state S1. As discussed, the voltage set points for states S0 and S2 are adjusted to maintain a target phase adjustment amount or range for each state.

[0124] In some implementations, the target phase adjustment amount or range can be specified via a user interface. For example, there can be a default target phase adjustment amount or range (e.g., 160-180 degrees in some implementations) that can be adjusted by the user in predetermined increments (e.g., 1-10 degree increments in some implementations) and within a predetermined range (e.g., 120-220 degrees in some implementations).

[0125] For a given recipe, there may be a target phase adjustment for each recipe step for each state of the pulsed RF signal. Furthermore, the target phase adjustment may be editable via the user interface, for example, via a recipe editor in the user interface. There may be a default value for the target phase adjustment that is provided when a new recipe step is built. For example, there may be a model (based on empirical data) that predicts what the target phase adjustment should be for each recipe step. When building each recipe step, the user may have the option to choose to use this model, or the user may enter their own value.

[0126] It will be appreciated that any of the methods described in this disclosure can be implemented to operate automatically by control system 120. In some embodiments, as discussed, capacitor tap locations can be automatically optimized to minimize reflected power in the TES system.

[0127] 10 shows an exemplary schematic diagram of the control system 120 of FIG. 2 , according to some embodiments. In some embodiments, the control system 120 is configured as a process controller for controlling a semiconductor manufacturing process performed in the plasma processing system 100. In various embodiments, the control system 120 includes a processor 1401, a storage hardware unit (HU) 1403 (e.g., memory), an input HU 1405, an output HU 1407, an input / output (I / O) interface 1409, an I / O interface 1411, a network interface controller (NIC) 1413, and a data communication bus 1415. The processor 1401, the storage HU 1403, the input HU 1405, the output HU 1407, the I / O interface 1409, the I / O interface 1411, and the NIC 1413 are in data communication with each other via the data communication bus 1415. The input HU 1405 is configured to receive data communications from multiple external devices. Examples of input HUs 1405 include data acquisition systems, data acquisition cards, etc. Output HUs 1407 are configured to transmit data to multiple external devices. One example of output HUs 1407 is a device controller. Examples of NICs 1413 include network interface cards, network adapters, etc. Each of I / O interfaces 1409 and 1411 is defined to provide compatibility between various hardware units coupled to the I / O interface. For example, I / O interface 1409 can be defined to convert signals received from input HUs 1405 to a shape, amplitude, and / or speed compatible with data communication bus 1415. I / O interface 1407 can also be defined to convert signals received from data communication bus 1415 to a shape, amplitude, and / or speed compatible with output HUs 1407.Although various operations herein are described as being performed by processor 1401 of control system 120, it should be understood that in some embodiments, various operations may be performed by multiple processors of control system 120 and / or multiple processors of multiple computing systems in data communication with control system 120.

[0128] In some embodiments, control system 120 is used to control devices in various wafer fabrication systems based in part on the sensed values. For example, control system 120 may control one or more of valves 1417, filter heaters 1419, wafer support structure heaters 1421, pumps 1423, and other devices 1425 based on the sensed values and other control parameters. Valves 1417 may include valves associated with controlling backside gas supply system 129, process gas supply system 191, and temperature control fluid circulation system 125. Control system 120 receives sensed values, for example, from pressure manometers 1427, flow meters 1429, temperature sensors 1431, and / or other sensors 1433, such as voltage sensors, current sensors, etc. Control system 120 may also be used to control process conditions within plasma processing system 100 during performance of plasma processing operations on wafers W. For example, the control system 120 can control the type and amount of process gas supplied from the process gas supply system 191 to the plasma processing region 182. The control system 120 can also control the operation of the first RF signal generator 147, the second RF signal generator 149, the impedance matching system 143, the TES RF signal generator 403, and the TES impedance matching system 401. The control system 120 can also control the operation of the DC supply 117 for the clamping electrode 112. The control system 120 can also control the operation of the lifting device 133 for the lift pins 132 and the operation of the door 107. The control system 120 also controls the operation of the backside gas supply system 129 and the temperature control fluid circulation system 125. The control system 120 also controls the vertical movement of the cantilever arm assembly 115. The control system 120 also controls the operation of the throttle member 196 and a pump that controls suction at the exhaust port 105. Control system 120 also controls the operation of hold-down control mechanism 913 of hold-down rod 911 of TES system 1000. Control system 120 also receives input from temperature probes of TES system 1000.It should be understood that the control system 120 is equipped to programmatically and / or manually control any function within the plasma processing system 100 .

[0129] In some embodiments, the control system 120 is configured to execute a computer program including a set of instructions for controlling process timing, process gas delivery system temperature and pressure differentials, valve positions, process gas mixture, process gas flow rates, backside cooling gas flow rates, chamber pressure, chamber temperature, wafer support structure temperature (wafer temperature), RF power levels, RF frequency, RF pulsing, impedance match system 143 settings, cantilever arm assembly position, bias power, and other parameters of a particular process. In some embodiments, other computer programs stored on a memory device associated with the control system 120 may be used. In some embodiments, there is a user interface associated with the control system 120. The user interface includes a display 1435 (e.g., a display screen and / or graphical software display of equipment and / or process conditions) and a user input device 1437, such as a pointing device, keyboard, touch screen, microphone, etc.

[0130] Software for directing the operation of control system 120 may be designed or configured in many different ways. Computer programs for directing the operation of control system 120 to perform various wafer fabrication processes in a process sequence can be written in any conventional computer-readable programming language, such as assembly language, C, C++, Pascal, Fortran, etc. Compiled object code or scripts are executed by processor 1401 to perform the tasks identified in the program. Control system 120 can be programmed to control various process control parameters related to process conditions, such as filter pressure differential, process gas composition and flow rate, backside cooling gas composition and flow rate, plasma conditions such as temperature, pressure, RF power level and RF frequency, bias voltage, cooling gas / fluid pressure, and chamber wall temperature, among others. Examples of sensors that may be monitored during the wafer fabrication process include, but are not limited to, mass flow control modules, pressure sensors such as pressure manometer 1427, and temperature sensor 1431. Appropriately programmed feedback and control algorithms may be used in conjunction with data from these sensors to control / adjust one or more process control parameters to maintain desired process conditions.

[0131] In some implementations, control system 120 is part of a broader manufacturing control system. Such manufacturing control systems may include semiconductor processing equipment, including processing tools, chambers, and / or wafer processing platforms, and / or specific processing components, such as wafer pedestals and gas flow systems. These manufacturing control systems may incorporate electronics for controlling operations before, during, and after wafer processing. Control system 120 may control various components or subcomponents of the manufacturing control system. Depending on wafer processing requirements, control system 120 may be programmed to control any of the processes disclosed herein, including supply of process gases, supply of backside cooling gases, temperature settings (e.g., heating and / or cooling), pressure settings, vacuum settings, power settings, radio frequency (RF) generator settings, RF matching circuit settings, frequency settings, flow rate settings, fluid supply settings, position and operation settings, and wafer transfer to and from tools and other transfer tools and / or load locks connected or interfaced with the particular system.

[0132] Broadly speaking, control system 120 may be defined as electronic equipment having various integrated circuits, logic, memory, and / or software that receive instructions, issue instructions, control operations, enable wafer processing operations, enable endpoint measurements, etc. Integrated circuits may include chips in the form of firmware that store program instructions, digital signal processors (DSPs), chips defined as application-specific integrated circuits (ASICs), and / or one or more microprocessors or microcontrollers that execute program instructions (e.g., software). Program instructions may be instructions communicated to control system 120 in the form of various personalizations (or program files) that define operational parameters for performing particular processes on wafers in system 100. In some embodiments, the operational parameters may be part of a recipe defined by a process engineer to accomplish one or more processing steps during the fabrication of one or more layers, materials, metals, oxides, silicon, silicon dioxide, surfaces, circuits, and / or wafer dies.

[0133] In some implementations, control system 120 may be part of or coupled to a computer that is embedded in or coupled to plasma processing system 100, or otherwise networked to system 100, or a combination thereof. For example, control system 120 may reside in the "cloud" of all or part of a fab host computer system, thereby enabling remote access to wafer processing. The computer may enable remote access to system 100 to monitor the current progress of a manufacturing operation, examine the history of past manufacturing operations, examine trends or performance indicators from multiple manufacturing operations, modify current process parameters, and configure processing steps to continue current processing or start new processes. In some embodiments, a remote computer (e.g., a server) may provide process recipes to system 100 over a network, which may include a local network or the Internet.

[0134] The remote computer may include a user interface that allows for entry or programming of parameters and / or settings, which are then communicated from the remote computer to the system 100. In some embodiments, the control system 120 receives instructions in the form of data specifying parameters for each processing step performed during one or more operations. It should be understood that the parameters may be specific to the type of process being performed in the plasma processing system 100. Thus, as described above, the control system 120 may be distributed, for example, by comprising one or more individual controllers networked together and directed toward a common purpose, such as the processes and controls described herein. One example of a distributed controller for such a purpose may be one or more integrated circuits on the plasma processing system 100 in communication with one or more remotely located integrated circuits (e.g., at the platform level or as part of a remote computer) that, in combination, control the processes being performed in the plasma processing system 100.

[0135] Exemplary systems with which control system 120 may interface may include, but are not limited to, a plasma etch chamber or module, a deposition chamber or module, a spin rinse chamber or module, a metal plating chamber or module, a cleaning chamber or module, a bevel edge etch chamber or module, a physical vapor deposition (PVD) chamber or module, a chemical vapor deposition (CVD) chamber or module, an atomic layer deposition (ALD) chamber or module, an atomic layer etch (ALE) chamber or module, an ion implantation chamber or module, a track chamber or module, and any other semiconductor processing system that may be associated with or used in the fabrication and / or manufacturing of semiconductor wafers. As mentioned above, depending on the process steps performed by the tool, control system 120 may communicate with one or more of other tool circuits or modules, other tool components, cluster tools, other tool interfaces, adjacent tools, neighboring tools, tools located throughout the factory, a main computer, another controller, or tools used in material transport to and from tool locations and / or load ports within a semiconductor fabrication factory.

[0136] The embodiments described herein may also be implemented in conjunction with various computer system configurations, including handheld hardware units, microprocessor systems, microprocessor-based or programmable consumer electronics, minicomputers, mainframe computers, and the like. The embodiments described herein may also be implemented in conjunction with distributed computing environments in which tasks are performed by remote processing hardware units linked through a network. It should be understood that the embodiments described herein, particularly those associated with control system 120, may employ various computer-implemented operations involving data stored in computer systems. These operations are operations requiring physical manipulation of physical quantities. Any operations described herein that form part of the embodiments are useful machine operations. The embodiments also relate to hardware units or apparatus for performing these operations. An apparatus may be specially constructed for a special-purpose computer. When defined as a special-purpose computer, the computer may also be capable of operating for its dedicated purpose while also performing other processes, program execution, or routines that are not part of its dedicated purpose. In some embodiments, operations may be processed by a general-purpose computer selectively activated or configured by one or more computer programs stored in the computer's memory, cache, or retrieved over a network. If the data is obtained over a network, the data may be processed by other computers on the network, for example, a cloud of computing resources.

[0137] Various embodiments described herein can be implemented via process control instructions instantiated as computer-readable code on a non-transitory computer-readable medium. A non-transitory computer-readable medium is any data storage hardware unit that can store data that can be subsequently read by a computer system. Examples of non-transitory computer-readable media include hard drives, network-attached storage (NAS), ROM, RAM, compact disc-ROMs (CD-ROMs), CD-recordables (CD-Rs), CD-rewritables (CD-RWs), magnetic tapes, and other optical and non-optical data storage hardware units. A non-transitory computer-readable medium can include tangible computer-readable media distributed across network-coupled computer systems such that the computer-readable code is stored and executed in a distributed fashion.

[0138] Although the foregoing disclosure includes some details for clarity of understanding, it will be apparent that certain changes and modifications can be practiced within the scope of the appended claims. For example, it should be understood that one or more features from any embodiment disclosed herein may be combined with one or more features of any embodiment disclosed herein. Therefore, the present embodiments should be considered illustrative rather than restrictive, and the claims should not be limited to the details set forth herein, but may be modified within the scope and equivalents of the described embodiments.

Claims

1. 1. A method for adjusting a voltage set point for a multi-state pulsed RF signal in a plasma processing system, the method comprising: applying RF power from a first generator to an ESC, the RF power from the first generator defining a first multi-state pulsed RF signal; applying RF power from a second generator to an edge electrode surrounding the ESC and disposed below an edge ring surrounding the ESC, the RF power from the second generator defining a second multi-state pulsed RF signal having a first state and a second state, and for each state of the second multi-state pulsed RF signal, the second generator automatically introduces a phase adjustment to substantially phase-match a corresponding state of the first multi-state pulsed RF signal; adjusting a voltage set point for the second state of the second multi-state pulsed RF signal to adjust the phase adjustment to a target phase adjustment setting.

2. The method of claim 1 , wherein the target phase adjustment setting is captured via a user interface.

3. The method of claim 1 , wherein the target phase adjustment setting is calculated based on a model.

4. 2. The method of claim 1, wherein the target phase adjust setting defines a predetermined phase adjust amount by which the phase of the RF power from the second generator is adjusted.

5. 2. The method of claim 1, wherein adjusting the voltage set point to adjust the phase adjustment comprises making incremental adjustments to the voltage set point until the phase adjustment reaches the target phase adjustment setting.

6. 6. The method of claim 5, wherein the incremental adjustment is based on a particular voltage set point associated with the first state of the second multi-state pulsed RF signal.

7. 2. The method of claim 1, wherein the phase adjustment is adjusted to the target phase adjustment setting when the phase adjustment reaches the target phase adjustment setting or when the phase adjustment is within a predetermined range from the target phase adjustment setting.

8. 2. The method of claim 1, wherein adjusting the voltage set point to adjust the phase adjustment to the target phase adjustment setting places the voltage set point in a middle portion of an acceptable range of the voltage set point.

9. 7. The method of claim 6, wherein the target phase adjustment setting that facilitates the voltage set point being located in the intermediate portion of the tolerance range of the voltage set point remains substantially the same with changes in capacitance of a matching circuit through which the RF power from the second generator is applied to the edge electrode.

10. 10. The method of claim 9, wherein the change in the capacitance of the matching circuit is responsive to a change in a voltage set point of the first state of the second multi-state pulsed RF signal.

11. 11. The method of claim 10, wherein the change in the voltage set point of the first state occurs based on usage of the edge ring.

12. 12. The method of claim 11, wherein the usage of the edge ring is defined as an amount of time of RF exposure of the edge ring.

13. 1. A method for adjusting a voltage set point for a multi-state pulsed RF signal in a plasma processing system, the method comprising: applying RF power from a first generator to an ESC, the RF power from the first generator defining a first pulsed RF signal having a first state and a second state; applying RF power from a second generator to an edge electrode surrounding the ESC and disposed below an edge ring surrounding the ESC, the RF power from the second generator defining a second pulsed RF signal having a first state and a second state, the second generator automatically introducing a first phase adjustment that substantially aligns a phase of the first state of the second pulsed RF signal to the first state of the first pulsed RF signal, the second generator automatically introducing a second phase adjustment that substantially aligns a phase of the second state of the second pulsed RF signal to the second state of the first pulsed RF signal, the second phase adjustment being adjusted to a target phase adjustment setting; and in response to detecting a change in the second phase adjustment away from the target phase adjustment setting, adjusting a voltage set point for the second state of the second pulsed RF signal to return the second phase adjustment to the target phase adjustment setting.

14. 14. The method of claim 13, wherein the target phase adjustment setting is captured via a user interface.

15. 14. The method of claim 13, wherein the target phase adjustment setting is calculated based on a model.

16. 14. The method of claim 13, wherein the target phase adjust setting defines a predetermined phase adjust amount by which the phase of the second state of the second pulsed RF signal is adjusted.

17. 14. The method of claim 13, wherein adjusting the voltage set point to return the second phase adjustment includes making incremental adjustments to the voltage set point until the second phase adjustment reaches the target phase adjustment setting.

18. 20. The method of claim 17, wherein the incremental adjustment is based on a particular voltage set point associated with the first state.

19. 14. The method of claim 13, wherein the second phase adjustment is returned to the target phase adjustment setting when the second phase adjustment reaches the target phase adjustment setting or when the second phase adjustment is within a predetermined range of the target phase adjustment setting.

20. 14. The method of claim 13, wherein adjusting the voltage set point to return the second phase adjustment to the target phase adjustment setting positions the voltage set point in a middle portion of an acceptable range of the voltage set point.

21. 21. The method of claim 20, wherein the target phase adjustment setting that facilitates the voltage set point being located in the intermediate portion of the tolerance range of the voltage set point remains substantially the same with changes in capacitance of a matching circuit through which the RF power from the second generator is applied to the edge electrode.

22. 22. The method of claim 21, wherein the change in the capacitance of the matching circuit is responsive to a change in a voltage set point of the first state of the second pulsed RF signal.

23. 23. The method of claim 22, wherein the change in the voltage set point of the first state of the second pulsed RF signal occurs based on usage of the edge ring.

24. 24. The method of claim 23, wherein the usage of the edge ring is defined as an amount of time of RF exposure of the edge ring.

Images