Method for manufacturing wiring board

Abstract

To provide a wiring board including a through conductor with suppressed recesses.SOLUTION: A method for manufacturing a wiring board according to an embodiment includes: preparing an insulating layer 100 having a first surface 100A and a second surface 100B; forming a through hole 100th penetrating from the first surface 100A to the second surface 100B; forming a through conductor 113 and a first conductor layer FCL; and exposing the first surface 100A by removing the first conductor layer FCL. The removing of the first conductor layer FCL includes: forming a first resist layer FRL on the first conductor layer FCL so as to cover a region overlapping the through conductor 113 in a plan view; removing an exposed portion of the first conductor layer FCL by etching; and removing a part of the first conductor layer FCL covered with the first resist layer FRL by polishing.SELECTED DRAWING: Figure 2D

Description

[Technical Field]

[0001] The present invention relates to a method for manufacturing a wiring board. [Background technology]

[0002] Patent Document 1 discloses a method for manufacturing a wiring board. A through hole is formed in an insulating substrate that constitutes a core substrate of the wiring board, and a through-hole conductor that fills the through hole and a conductor layer that covers the insulating substrate are integrally formed. The conductor layer is removed by etching, exposing the entire surface of the insulating substrate perpendicular to the thickness direction and the surface of the through-hole conductor. A via conductor is formed on the exposed surface of the through-hole conductor. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] Japanese Patent Application Publication No. 2024-6642 Summary of the Invention [Problem to be solved by the invention]

[0004] In the method for manufacturing a wiring board disclosed in Patent Document 1, it is believed that etching can cause relatively large depressions (dishing) on ​​the exposed surfaces of the through-hole conductors, which can lead to poor connections between the through-hole conductors and the via conductors. [Means for solving the problem]

[0005] A method for manufacturing a wiring board of the present invention includes: preparing an insulating layer having a first surface and a second surface opposite to the first surface; forming a through hole penetrating from the first surface to the second surface; filling the through hole with a conductor to form a through conductor and forming a first conductor layer by covering the first surface with the conductor; and removing the first conductor layer to expose the first surface. Removing the first conductor layer includes forming a first resist layer on the first conductor layer to cover an area that overlaps the through conductor in a plan view; removing the exposed portion of the first conductor layer by etching; and removing the portion of the first conductor layer covered by the first resist layer by polishing.

[0006] According to the embodiment of the present invention, a wiring board having through conductors with reduced dishing on the surface can be provided in a relatively short time. [Brief explanation of the drawings]

[0007] [Figure 1] 1 is a cross-sectional view showing an example of a wiring board according to an embodiment of the present invention. [Figure 2A] 2A to 2C are diagrams illustrating an example of a method for manufacturing the wiring board shown in FIG. [Figure 2B] 2A to 2C are diagrams illustrating an example of a method for manufacturing the wiring board shown in FIG. [Figure 2C] 2A to 2C are diagrams illustrating an example of a method for manufacturing the wiring board shown in FIG. [Figure 2D] 2A to 2C are diagrams illustrating an example of a method for manufacturing the wiring board shown in FIG. [Figure 2E] 2A to 2C are diagrams illustrating an example of a method for manufacturing the wiring board shown in FIG. [Figure 2F] 2A to 2C are diagrams illustrating an example of a method for manufacturing the wiring board shown in FIG. [Figure 2G] 2A to 2C are diagrams illustrating an example of a method for manufacturing the wiring board shown in FIG. [Figure 2H] 2A to 2C are diagrams illustrating an example of a method for manufacturing the wiring board shown in FIG. DETAILED DESCRIPTION OF THE INVENTION

[0008] The method for manufacturing a wiring board of the present invention will be described with reference to the drawings. Note that the drawings referred to below are not intended to show the exact proportions of the components, but are drawn to make the features of the present invention easier to understand. Figure 1 shows a cross section of a wiring board 1, which is an example of a wiring board manufactured by the manufacturing method of the embodiment.

[0009] As shown in FIG. 1, the wiring board 1 includes a laminate 10. The laminate 10 has an insulating layer 100 having a first surface 100A and a second surface 100B opposite to the first surface 100A. The insulating layer 100 is made of, for example, a glass substrate. The first surface 100A of the insulating layer 100 is covered with an insulating layer 101. The second surface 100B of the insulating layer 100 is covered with an insulating layer 102. A conductor layer 111 is formed on the insulating layer 101, and a conductor layer 112 is formed on the insulating layer 102. One surface 10A of the laminate 10 is formed by the surface of the conductor layer 111 and the upper surface of the insulating layer 101 exposed from the pattern of the conductor layer 111. The other surface 10B of the laminate 10 is formed by the surface of the conductor layer 112 and the upper surface of the insulating layer 102 exposed from the pattern of the conductor layer 112.

[0010] In the illustrated example, the wiring board 1 has a first buildup section 11 formed on one surface 10A of the laminate 10 and a second buildup section 12 formed on the other surface 10B. That is, the laminate 10 has the form of a core substrate in the wiring board 1. Therefore, in the description of this embodiment, the laminate 10 is also referred to as a core substrate 10. The insulating layer 100 is also referred to as a core insulating layer 100. The insulating layers 101 and 102 are also referred to as coating insulating layers 101 and 102. The conductor layers 111 and 112 are also referred to as core conductor layers 111 and 112.

[0011] In the description of the wiring board of this embodiment, the side farther from the core insulating layer 100 is also referred to as the "top," "upper side," "outside," or "outside," and the side closer to the core insulating layer 100 is also referred to as the "bottom," "lower side," "inside," or "inside." Furthermore, in each insulating layer and conductor layer, the surface facing away from the core insulating layer 100 is also referred to as the "top surface," and the surface facing the core insulating layer 100 is also referred to as the "bottom surface." Therefore, for example, in the description of each element constituting the core substrate 10, the first buildup section 11, and the second buildup section 12, the side farther from the core insulating layer 100 is also referred to as the "top side," "upper," "upper layer side," "outside," or simply "top" or "outside," and the side closer to the core insulating layer 100 is also referred to as the "bottom side," "lower," "lower layer side," "inside," or simply "bottom" or "inside." In the description of the embodiment, the thickness direction of the wiring board is also simply referred to as the "Z direction."

[0012] The core conductor layers 111 and 112 constituting the core substrate 10 are connected by a through conductor 113 that penetrates the core insulating layer 100 in the thickness direction, a via conductor 121 that penetrates the insulating layer 101, and a via conductor 122 that penetrates the insulating layer 102. The through conductor 113 is composed of a conductor that fills a through hole 100th that penetrates the core insulating layer 100 in the thickness direction.

[0013] The diameters of the through conductor 113 on the two surfaces (first surface 100A and second surface 100B) perpendicular to the thickness direction of the core insulating layer 100 are formed to be approximately the same, for example, 40 μm or more and 200 μm or less. Although the term "diameter" is used here, the planar shape of the through conductor 113 is not necessarily limited to a circle. It means the distance between the longest two points on the periphery of the through conductor 113 in a planar view. Note that "planar view" means viewing an object with a line of sight parallel to the thickness direction of the wiring board 1.

[0014] The first buildup section 11 is composed of insulating layers 110 and conductor layers 120 alternately stacked on one surface 10A of the core substrate 10. The second buildup section 12 is composed of insulating layers 210 and conductor layers 220 alternately stacked on the other surface 10B of the core substrate 10. The insulating layers 110 constituting the first buildup section 11 and the insulating layers 210 constituting the second buildup section 12 each include via conductors 13, 23 that connect conductor layers formed on opposite sides in the thickness direction.

[0015] A solder resist layer SR1 is formed on the first buildup section 11. A solder resist layer SR2 is formed on the second buildup section 12. An opening SR1o is formed in the solder resist layer SR1, and a conductor pad 120p of the outermost conductor layer 120 in the first buildup section 11 is exposed from the opening SR1o. An opening SR2o is formed in the solder resist layer SR2, and a conductor pad 220p of the outermost conductor layer 220 in the second buildup section 12 is exposed from the opening SR2o.

[0016] The conductor pad 120p may be, for example, a connection pad used for mounting an external electronic component (not shown), etc. On the other hand, the conductor pad 220p may be, for example, a connection pad used for connecting to an external motherboard (not shown), etc. A surface protection film (not shown) made of Au, Ni / Au, Ni / Pd / Au, solder, heat-resistant preflux, etc. may be formed on the exposed surfaces of the conductor pads 120p and 220p.

[0017] When the core insulating layer 100 constituting the core substrate 10 includes glass, which is an amorphous solid, the core insulating layer 100 may include, for example, soda-lime glass, borosilicate glass, fluoroglass, chalcogenide glass, alkali-free glass, or quartz glass. Alternatively, the core insulating layer 100 may include organic glass such as acrylic glass. These glasses may include elements such as magnesium, calcium, manganese, aluminum, lead, iron, chromium, potassium, sulfur, antimony, and boron as additives.

[0018] The covering insulating layers 101 and 102 constituting the core substrate 10, the insulating layer 110 constituting the first buildup section 11, and the insulating layer 210 constituting the second buildup section 12 may each be formed using an insulating resin such as epoxy resin, bismaleimide triazine resin (BT resin), or phenolic resin. Each of the insulating layers 101, 102, 110, and 210 may contain a reinforcing material (core material) such as glass fiber and / or an inorganic filler such as silica or alumina. The core insulating layer 100 may also be formed using a prepreg in which a reinforcing material (core material) such as glass fiber is impregnated with an insulating resin. The solder resist layers SR1 and SR2 are formed using, for example, a photosensitive epoxy resin or a polyimide resin.

[0019] The conductor layers 111, 112, 120, 220, the via conductors 121, 122, 13, 23, and the through-hole conductor 113 may be formed using any metal, such as copper or nickel. For example, the conductor layers 111, 112, 120, 220 may be formed using a metal foil, such as copper foil, and / or a metal film formed by plating, sputtering, or the like. The conductor layers 111, 112, 120, 220, the via conductors 121, 122, 13, 23, and the through-hole conductor 113 may have a multilayer structure of two or more layers, as shown in the figure. The conductor layers 111, 112, 120, 220, the via conductors 121, 122, 13, 23, and the through-hole conductor 113 may have a two-layer structure, for example, including a metal film layer (electroless plated film layer or sputtered film layer) and an electrolytic plated film layer.

[0020] The outward facing surfaces of the through conductors 113 that penetrate the core insulating layer 100 are formed by polishing, as will be described in detail later. Therefore, dishing of the outward facing surfaces of the through conductors 113 relative to the surfaces (first surface 100A and second surface 100B) of the core insulating layer 100 is suppressed. Preferably, the outward facing surfaces of the through conductors 113 and the surface of the core insulating layer 100 are formed to be approximately flush with each other. Therefore, in the wiring board 1 manufactured by the manufacturing method of the embodiment, good connections can be achieved in which the occurrence of connection defects is suppressed in the connections between the through conductors 113 and the via conductors 121, 122.

[0021] Next, an example of a method for manufacturing a wiring board according to an embodiment will be described with reference to FIGS. 2A to 2H, taking the case where wiring board 1 of FIG. 1 is manufactured as an example.

[0022] First, as shown in Fig. 2A, a core insulating layer 100 is prepared. A glass substrate made of, for example, soda-lime glass, alkali-free glass, quartz glass, or borosilicate glass is prepared as the core insulating layer 100. When the core insulating layer 100 is a glass substrate, the core insulating layer 100 can be prepared by a general plate glass manufacturing method such as the float glass method.

[0023] A through hole 100th is formed in the core insulating layer 100. The through hole 100th can be formed, for example, by drilling the core insulating layer 100, sandblasting, or laser processing in which laser light such as a carbon dioxide laser is irradiated onto the core insulating layer 100. Fig. 2A shows an example in which the through hole 100th is formed by irradiating the first surface 100A and the second surface 100B of the core insulating layer 100 with laser light from the outside, and the through hole 100th is formed so that its diameter decreases toward the center in the thickness direction of the insulating layer 100. The through hole 100th can be formed to have approximately the same diameter on two surfaces (the first surface 100A and the second surface 100B) of the core insulating layer 100 that are perpendicular to the thickness direction.

[0024] 2B, the through hole 100th is filled with a conductor to form the through conductor 113. Along with the formation of the through conductor 113, a first conductor layer FCL is formed on the first surface 100A of the core insulating layer 100. A second conductor layer SCL is formed on the second surface 100B of the core insulating layer 100. The formation of the through conductor 113, the first conductor layer FCL, and the second conductor layer SCL may include, for example, the formation of a metal film layer CRa that covers the inner surface of the through hole 100th, the first surface 100A, and the second surface 100B, and a plating film layer CRb that covers the metal film layer CRa.

[0025] In forming the through conductors 113, the first conductor layer FCL, and the second conductor layer SCL, for example, first, a metal film layer CRa that covers the inner surface of the through hole 100th and the entire area of ​​both surfaces (first surface 100A and second surface 100B) of the core insulating layer 100 is formed by sputtering, electroless plating, or the like. Next, a plating film layer CRb is formed on the metal film layer CRa by electrolytic plating using the metal film layer CRa as a power supply layer, and the through conductors 113 having a two-layer structure of the metal film layer CRa and the plating film layer CRb are formed in the through holes 100th. Together with the formation of the through conductors 113, a first conductor layer FCL having a two-layer structure of the metal film layer CRa and the plating film layer CRb is formed on the first surface 100A of the core insulating layer 100, and a second conductor layer SCL having a two-layer structure of the metal film layer CRa and the plating film layer CRb is formed on the second surface 100B.

[0026] 2C, a first resist layer FRL is formed on the first conductor layer FCL, and a second resist layer SRL is formed on the second conductor layer SCL. The first resist layer FRL and the second resist layer SRL are formed so as to cover the area directly above the through conductor 113 and its peripheral area (i.e., an area wider than the area directly above the through conductor 113). That is, the first resist layer FRL and the second resist layer SRL are formed by photolithography so as to have a resist pattern that covers the area that overlaps with the through conductor 113 in a plan view.

[0027] 2D, the portion of the first conductor layer FCL exposed from the resist pattern of the first resist layer FRL is removed by etching using, for example, a cupric chloride solution. By removing the first conductor layer FCL by etching, the first surface 100A of the core insulating layer 100 is partially exposed. The second conductor layer SCL exposed from the resist pattern of the second resist layer SRL of the second conductor layer SCL is similarly removed by etching, exposing the second surface 100B of the core insulating layer 100.

[0028] Next, the first resist layer FRL and the second resist layer SRL are removed. By removing the first resist layer FRL, the first conductor layer FCL formed at a position overlapping the through conductor 113 in a plan view is exposed, as shown in Fig. 2E. By removing the second resist layer SRL, the second conductor layer SCL formed at a position overlapping the through conductor 113 in a plan view is exposed.

[0029] Next, the exposed portion of the first conductor layer FCL is removed by polishing, thereby completely removing the first conductor layer FCL, and as shown in FIG. 2F, the entire first surface 100A of the core insulating layer 100 and one surface 113a of the through conductor 113 are exposed. One surface 113a of the through conductor 113 exposed by the removal of the first conductor layer FCL can be formed to be approximately flush with the first surface 100A of the core insulating layer 100. In addition, the exposed portion of the second conductor layer SCL is removed by polishing, thereby completely removing the second conductor layer SCL, and the entire second surface 100B of the core insulating layer 100 and the other surface 113b of the through conductor 113 are exposed. The other surface 113b of the through conductor 113 exposed by the removal of the second conductor layer SCL can be formed to be approximately flush with the second surface 100B of the core insulating layer 100. The first conductor layer FCL and the second conductor layer SCL can be removed by polishing, for example, chemical mechanical polishing (CMP).

[0030] In the method for manufacturing a wiring board of this embodiment, as described above, one surface 113a of the through conductor 113 penetrating the core insulating layer 100 is exposed by polishing away the conductor layer FCL formed integrally with the through conductor 113 on the first surface 100A of the core insulating layer 100. When the conductor layer FCL located directly above the through conductor 113 is removed by polishing, it is relatively unlikely that one surface 113a of the through conductor 113 will be dished relative to the first surface 100A, compared to when the removal is performed by etching using a chemical solution. The depression that may be formed on one surface 113a of the through conductor 113 relative to the first surface 100A can be suppressed to 1 μm or less. The first surface 100A of the core insulating layer 100 and one surface 113a of the through conductor 113 may be formed to be approximately flush with each other.

[0031] Furthermore, in the method for manufacturing a wiring board of this embodiment, before removing the conductor layer FCL by polishing, the conductor layer FCL is removed by etching except for the portions located directly above the through conductors 113. Therefore, the portions of the conductor layer FCL that need to be removed in the polishing step are limited to the vicinity of directly above the through conductors 113. Even if polishing is performed at a relatively slow polishing rate that is unlikely to cause dishing on one surface 113a of the through conductors 113, polishing can be completed in a relatively short time.

[0032] Next, as shown in FIG. 2G, a covering insulating layer 101 is formed on the first surface 100A of the core insulating layer 100. A covering insulating layer 102 is formed on the second surface 100B of the core insulating layer 100. Specifically, semi-cured sheet-like resin is laminated on the first surface 100A and the second surface 100B of the core insulating layer 100. The sheet-like resin is cured by applying pressure and heat, forming the covering insulating layers 101 and 102. Next, a through hole 101a that penetrates the covering insulating layer 101 and a through hole 102a that penetrates the covering insulating layer 102 are formed. The through holes 101a and 102a can be formed, for example, by laser processing using laser light such as a carbon dioxide laser.

[0033] Next, via conductor 121 in through hole 101a is formed integrally with conductor layer 111 on insulating layer 101. Also, via conductor 122 in through hole 102a is formed integrally with conductor layer 112 on insulating layer 102. In forming via conductor 121 and conductor layer 111, first, metal film layer 111a covering the entire inner surface of through hole 101a and the upper surface of covering insulating layer 101 is formed by sputtering, electroless plating, or the like. Next, plating film layer 111b is formed on metal film layer 111a by electrolytic plating using metal film layer 111a as a power supply layer using a plating resist with appropriate openings, thereby forming via conductor 121 with a two-layer structure of metal film layer 111a and plating film layer 111b in through hole 101a. Next, metal film layer 111a exposed by removing the plating resist is removed by etching using a chemical solution, thereby forming conductor layer 111 having a desired conductor pattern. On the second surface 100B side of the core insulating layer 100, via conductors 122 and conductor layers 112 can be formed by the same steps as those for the above-described via conductors 121 and conductor layers 111. The formation of the core substrate 10 is then completed.

[0034] For example, if the diameter of the through hole 101a is formed to decrease from the outside to the inside of the insulating layer 101, if one surface 113a is recessed relative to the first surface 100A, the surface area of ​​the through conductor 113 exposed at the bottom of the through hole 101a may be reduced. Therefore, the contact area between the via conductor 121 formed in the through hole 101a and the through conductor 113 may not be sufficiently secured, which may result in a connection failure. In contrast, in the method for manufacturing a wiring board according to the embodiment, as described above, one surface 113a of the through conductor 113 may be formed so that the recess relative to the first surface 100A is suppressed to a depth of at least 1 μm or less. Therefore, a desired connection area is secured in the connection between the through conductor 113 and the via conductor 121, and a highly reliable connection with little risk of connection failure may be realized.

[0035] 2H, a first buildup section 11 is formed on one surface 10A of the core substrate 10. A second buildup section 12 is formed on the other surface 10B of the core substrate 10.

[0036] In forming the first buildup section 11, first, the conductor layer 111 constituting one surface 10A of the core substrate 10 and the insulating layer 110 covering the surface of the insulating layer 101 exposed from the pattern of the conductor layer 111 are laminated. Next, the via conductors 13 penetrating the insulating layer 110 and the conductor layer 120 on the insulating layer 110 are formed by the same process as the via conductors 121 and the conductor layer 111 described above, that is, for example, by a semi-additive process (SAP) method. The process of forming the insulating layer 110, the via conductors 13, and the conductor layer 120 is repeated to form the first buildup section 11 including the desired number of insulating layers 110 and conductor layers 120. In the example shown, two insulating layers 110 and two conductor layers 120 are alternately laminated.

[0037] On the other surface 10B of the core substrate 10, the second buildup section 12 is formed by repeatedly forming an insulating layer 210, via conductors 23, and a conductor layer 220 using steps similar to those used to form the insulating layer 110, via conductors 13, and conductor layer 120. The outermost conductor layer 120 of the first buildup section 11 is formed in a pattern including conductor pads 120p. The outermost conductor layer 220 of the second buildup section 12 is formed in a pattern including conductor pads 220p. Next, a solder resist layer SR1 is formed on the first buildup section 11, and a solder resist layer SR2 is formed on the second buildup section 12. The solder resist layers SR1 and SR2 are formed of a resin layer containing, for example, a photosensitive epoxy resin or a polyimide resin.

[0038] Next, by exposure and development using a mask with an appropriate opening pattern, the solder resist layers SR1, SR2 are formed to have openings SR1o, SR2o that expose the conductor pads 120p, 220p, thereby completing the wiring board 1 of Fig. 1. A surface protection film (not shown) made of Au, Ni / Au, Ni / Pd / Au, solder, heat-resistant preflux, or the like may be formed on the exposed surfaces of the conductor pads 120p, 220p by electroless plating, a solder leveler, spray coating, or the like.

[0039] The method for manufacturing a wiring board according to the embodiment is not limited to the method described with reference to FIGS. 2A to 2H, and the conditions and order of the steps may be arbitrarily changed. Furthermore, certain steps may be omitted, or other steps may be added. The method for manufacturing a wiring board according to the embodiment may include at least forming an insulating layer having through holes, forming through conductors and forming a first conductor layer, forming a first resist layer on the first conductor layer to cover an area overlapping the through conductor in a planar view, and removing the exposed portion of the first conductor layer by etching, and removing the portion of the first conductor layer covered by the first resist layer by polishing to expose the surface of the core insulating layer. For example, a copper-clad laminate may be used for the core insulating layer. The first resist layer and the portion of the first conductor layer covered by the first resist layer may be removed together by polishing. [Explanation of symbols]

[0040] 1. Wiring board 10 Core Board 11 First build-up section 12 Second build-up section 100 Core insulation layer 100A Page 1 100B 2nd side 113 Through conductor 113a One surface 113b Other surface 121, 122 via conductor FCL conductor layer (first conductor layer) SCL conductor layer (second conductor layer) FRL resist layer (first resist layer) SRL Resist layer (second resist layer)

Claims

1. providing an insulating layer having a first surface and a second surface opposite the first surface; forming a through hole penetrating from the first surface to the second surface; filling the through holes with a conductor to form through conductors, and covering the first surface with the conductor to form a first conductor layer; removing the first conductor layer to expose the first surface; A method for manufacturing a wiring substrate, comprising: Removing the first conductor layer includes: forming a first resist layer on the first conductor layer to cover an area overlapping the through conductor in a plan view; etching away the exposed portion of the first conductor layer; removing a portion of the first conductor layer covered with the first resist layer by polishing; Contains:

2. 2. The method for manufacturing a wiring board according to claim 1, forming the through conductor and covering the second surface with the conductor to form a second conductor layer; removing the second conductor layer to expose the second surface; further comprising Removing the second conductor layer includes: forming a second resist layer on the second conductor layer to cover an area overlapping the through conductor in a plan view; etching away the exposed portion of the second conductor layer; removing a portion of the second conductor layer covered with the second resist layer by polishing; Contains:

3. 3. A method for manufacturing a wiring board according to claim 2, wherein removing the first conductor layer to expose the first surface and removing the second conductor layer to expose the second surface are carried out simultaneously.

4. 2. The method for manufacturing a wiring board according to claim 1, further comprising polishing the surface of the through conductor so that the depth of the recess with respect to the first surface is 1 [mu]m or less.

5. 2. The method for manufacturing a wiring board according to claim 1, further comprising removing the first resist layer from the first conductor layer after the etching and before the polishing.

6. 2. The method for manufacturing a wiring board according to claim 1, wherein the insulating layer is made of glass.

7. 2. The method for manufacturing a wiring board according to claim 1, wherein the polishing includes CMP polishing.

8. 2. The method for manufacturing a wiring board according to claim 1, wherein forming the through hole includes forming the through hole so that the diameter of the through hole on the first surface and the diameter of the through hole on the second surface are substantially equal.

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