Semiconductor device

Abstract

To provide a semiconductor device capable of improving IFSM tolerance by suppressing current concentration to a source ring part.SOLUTION: A semiconductor device includes an active region 40 where main current flows on semiconductor substrates 1 and 2 of a first conductivity type, a terminal region 42 that surrounds the active region 40, and a transition region 41 between the active region 40 and the terminal region 42. The semiconductor device includes a front surface electrode 12 connected to first semiconductor regions 6 and 8 of a second conductivity type on a front surface side of the semiconductor substrates 1 and 2 in the active region 40, and a source ring 25 electrically connected to a front surface electrode 14 and connected to a second semiconductor region 7 of the first conductivity type for extracting current in the transition region 41. On the semiconductor substrates 1 and 2 side of the source ring 25, the second semiconductor region 7 is provided.SELECTED DRAWING: Figure 2

Description

[Technical Field]

[0001] This disclosure relates to semiconductor devices. [Background technology]

[0002] Conventionally, in order to mitigate adverse effects on the surface electrodes of a semiconductor device, a semiconductor device has been known which includes a first well region formed in the surface layer of the upper surface of a drift layer, a gate electrode, a second well region surrounding the first well region in a planar view, and a gate portion covering an interlayer insulating film and the gate electrode exposed from the interlayer insulating film, wherein the outer end of the gate electrode is farther from the first well region than the outer end of the gate portion and closer to the first well region than the outer end of the second well region (see, for example, Patent Document 1 below). [Prior art documents] [Patent documents]

[0003] [Patent Document 1] International Publication No. 2021 / 005821 Summary of the Invention [Problem to be solved by the invention]

[0004] Conventional semiconductor devices have a problem in that current concentrates in the source ring during an IFSM (rated forward surge current) test, reducing IFSM resistance. An object of this disclosure is to provide a semiconductor device that can suppress current concentration in the source ring and improve IFSM resistance. [Means for solving the problem]

[0005] In order to solve the above-mentioned problems and achieve the object of the present disclosure, a semiconductor device according to this disclosure has the following features: The semiconductor device includes, on a semiconductor substrate of a first conductivity type, an active region through which a main current flows, a termination region surrounding the active region, and a transition region between the active region and the termination region. A front surface electrode connected to a first semiconductor region of a second conductivity type is provided on the front surface side of the semiconductor substrate of the active region, and a source ring electrically connected to the front surface electrode in the transition region and connected to a second semiconductor region of the first conductivity type for extracting current, the second semiconductor region being provided on the semiconductor substrate side of the source ring.

[0006] According to the above disclosure, by providing the second semiconductor region of the first conductivity type below the source ring, it is possible to allow current to flow from the first semiconductor region of the second conductivity type to the source ring and prevent current from flowing from the source ring to the first semiconductor region. Therefore, even if resistance increases due to a rise in temperature during IFSM testing, current can be prevented from flowing from the source ring to the first semiconductor region, preventing current concentration at the source ring connection portion and improving IFSM tolerance. [Effects of the Invention]

[0007] The semiconductor device according to the present disclosure has the effect of suppressing current concentration in the source ring portion and improving the IFSM resistance. [Brief explanation of the drawings]

[0008] [Figure 1] 1 is a plan view showing a top surface structure of a silicon carbide semiconductor device in accordance with a first embodiment. [Figure 2] 2 is a cross-sectional view taken along the line YY′ of FIG. 1 showing the structure of the silicon carbide semiconductor device according to the first embodiment. [Figure 3] 2 is a cross-sectional view taken along the line XX' of FIG. 1 showing the structure of the silicon carbide semiconductor device according to the first embodiment. [Figure 4] FIG. 10 is a plan view showing a top surface structure of a silicon carbide semiconductor device according to a second embodiment. [Figure 5] 5 is a cross-sectional view taken along the line YY′ of FIG. 4, showing the structure of a silicon carbide semiconductor device according to a second embodiment. FIG. [Figure 6] FIG. 10 is a plan view showing a top surface structure of a silicon carbide semiconductor device according to a third embodiment. [Figure 7] 7 is a cross-sectional view taken along the line YY′ of FIG. 6 showing the structure of a silicon carbide semiconductor device according to a third embodiment. FIG. [Figure 8] 7 is a cross-sectional view taken along the line YY′ of FIG. 6 showing the structure of a silicon carbide semiconductor device according to a fourth embodiment. FIG. [Figure 9] FIG. 10 is a cross-sectional view showing current distribution in a conventional silicon carbide semiconductor device. [Figure 10] 2 is a cross-sectional view showing a current distribution in the silicon carbide semiconductor device according to the first embodiment. FIG. [Figure 11] FIG. 1 is a cross-sectional view showing the structure of a conventional silicon carbide semiconductor device (part 1). [Figure 12] FIG. 2 is a cross-sectional view showing the structure of a conventional silicon carbide semiconductor device (part 2). [Figure 13] FIG. 1 is a plan view showing a top surface structure of a conventional silicon carbide semiconductor device. [Figure 14] FIG. 1 is a plan view showing an upper surface electrode structure of a conventional silicon carbide semiconductor device. DETAILED DESCRIPTION OF THE INVENTION

[0009] <Summary of Embodiments of the Present Disclosure> In order to solve the above-mentioned problems and achieve the object of the present disclosure, a semiconductor device according to this disclosure has the following features: The semiconductor device includes, on a semiconductor substrate of a first conductivity type, an active region through which a main current flows, a termination region surrounding the active region, and a transition region between the active region and the termination region. A front surface electrode connected to a first semiconductor region of a second conductivity type is provided on the front surface side of the semiconductor substrate of the active region, and a source ring electrically connected to the front surface electrode in the transition region and connected to a second semiconductor region of the first conductivity type for extracting current, the second semiconductor region being provided on the semiconductor substrate side of the source ring.

[0010] According to the above disclosure, by providing the second semiconductor region of the first conductivity type below the source ring, it is possible to pass a current from the first semiconductor region of the second conductivity type to the source ring and to prevent a current from flowing from the source ring to the first semiconductor region. Therefore, even if the resistance increases due to a rise in temperature during an IFSM test, it is possible to prevent a current from flowing from the source ring to the first semiconductor region, prevent current from concentrating at the source ring connection portion, and improve the IFSM tolerance.

[0011] Furthermore, the semiconductor device according to the present disclosure is characterized in that, in the above disclosure, the second semiconductor region is provided in the active region, the termination region, and the transition region, and in the transition region, it is provided over the entire front surface side of the semiconductor substrate.

[0012] Furthermore, the semiconductor device according to the present disclosure is characterized in that, in the above disclosure, the first semiconductor region is provided in the active region and the transition region, and the second semiconductor region is provided in the termination region and the transition region, in contact with the first semiconductor region, and in the transition region, is provided on the semiconductor substrate side of the source ring.

[0013] Furthermore, the semiconductor device according to the present disclosure is characterized in that, in the above disclosure, the first semiconductor region is provided in the active region, the termination region, and the transition region, and the second semiconductor region is provided in the transition region in contact with the first semiconductor region, and in the transition region, is provided on the semiconductor substrate side of the source ring.

[0014] According to the above disclosure, by narrowing the width of the second semiconductor region of the first conductivity type, it is possible to reduce Vf (forward voltage).

[0015] Furthermore, the semiconductor device according to the present disclosure is characterized in that, in the above disclosure, it comprises a third semiconductor region of a second conductivity type on the semiconductor substrate side of the first semiconductor region, the third semiconductor region having a higher impurity concentration than the first semiconductor region, and the second semiconductor region is deeper than the first semiconductor region and reaches the third semiconductor region.

[0016] According to the above disclosure, by forming the second semiconductor region of the first conductivity type deeply, the concentration difference between the n-type and p-type can be reduced, and avalanche between the n-type and p-type can be suppressed when a reverse bias is applied.

[0017] Moreover, in the semiconductor device according to the present disclosure, the impurity concentration of the first semiconductor region is higher than the impurity concentration of the second semiconductor region.

[0018] <Findings underlying this disclosure> First, we will explain the problems with conventional semiconductor devices. From the perspective of power semiconductor devices, semiconductor materials to replace silicon are being considered, and silicon carbide (SiC) is attracting attention as a semiconductor material that can be used to fabricate (manufacture) next-generation power semiconductor devices with low on-state voltage, high-speed characteristics, and excellent high-temperature characteristics.

[0019] Figures 11 and 12 are cross-sectional views showing the structure of a conventional silicon carbide semiconductor device. Figure 11 is a Y-Y' cross-sectional view of Figure 13 shown below, and Figure 12 is an X-X' cross-sectional view of Figure 13. Figures 11 and 12 show a trench MOSFET 150 as a conventional silicon carbide semiconductor device.

[0020] 11 and 12, the trench MOSFET 150 includes a MOS gate with a general trench gate structure on the front surface (the surface on the p-type base layer 106 side, which will be described later) of a semiconductor substrate (hereinafter referred to as the silicon carbide substrate) made of silicon carbide in the active region 140. The silicon carbide substrate (semiconductor chip) includes an n-type + Mold support substrate (hereinafter referred to as n + n-type silicon carbide substrate) on 101 -The n-type drift layer 102 and the p-type base layer 106 are formed by epitaxially growing silicon carbide layers in this order. + The silicon carbide substrate 101 and the n - The p-type drift layer 102 and the p-type base layer 106 together form a silicon carbide semiconductor substrate.

[0021] n + The front surface (n - On the surface of the n-type drift layer 102, a p-type base layer 106 and an n-type ++ The MOS gate structure is formed of a source region 107, a trench 116, a gate insulating film 109, and a gate electrode 110. Reference numerals 108, 111, and 112 denote p + The n-type contact region, the interlayer insulating film, and the source electrode. + A back surface electrode 113 serving as a drain electrode is provided on the back surface of the silicon carbide substrate 101 .

[0022] n - The first p + Mold region 104a and second p + The second p consisting of the mold region 104b + A type base region 104 is selectively provided. - The first p-type drift layer 102 is formed so as to cover the entire bottom surface of the trench 116. + A mold base region 103 is optionally provided.

[0023] 11 and 12, the trench MOSFET 150 includes an active region 140 in which an element structure is formed and through which current flows when the trench MOSFET is on, a termination structure region 142 that surrounds the active region 140 and maintains a breakdown voltage, and a transition region 141 between the active region 140 and the termination structure region 142.

[0024] The termination structure region 142 includes a p-type base layer 106, a p + type contact region 108 and the second p + The p-type base region 104 is partially provided, and the p-type base layer 106, p +type contact region 108 and the second p + In the region where the base region 104 is not provided, n - The n-type drift layer 102 is exposed. - A breakdown voltage structure such as a guard ring structure 121 or a JTE (Junction Termination Extension) structure is provided on the type drift layer 102 .

[0025] The guard ring structure 121 is + The silicon carbide substrate 101 is then heated to a temperature of 1000 K. + A plurality of p-type regions with different impurity concentrations are arranged in a substantially rectangular planar shape surrounding the periphery of the active region 140 so that the p-type regions with lower impurity concentrations are arranged as they move away from the active region 140 (toward the end of the silicon carbide substrate 101). Furthermore, an n-type region serving as a channel stopper is arranged outside the breakdown voltage structure. ++ The n-type region 123 is disposed. ++ An initial oxide film 117 and an interlayer insulating film 111 are provided on the surface of the mold region 123, and a protective film (not shown) made of polyimide or the like is provided on the surface of the trench MOSFET 150.

[0026] In SiC, the deep energy level of p-type impurities increases the resistance of the p-type region, especially at low temperatures such as -40°C or -55°C. Therefore, when dV / dt is applied to the device, a large lateral voltage drop occurs due to the hole current flowing through the p-type region. This results in a large voltage being applied between the p-type region and the electrode placed above it via an insulating film, resulting in the breakdown of the insulating film. This phenomenon is likely to occur around the active region, where current from inactive regions such as the breakdown voltage structure is concentrated. To solve this problem, a source ring 125 has been provided to extract hole current from the periphery of the active region 140 and direct it to the source electrode 112.

[0027] As shown in FIGS. 11 and 12, the transition region 141 includes p ++An initial oxide film 117 and an interlayer insulating film 111 are provided on the front surface of the contact region 108, a source ring 125 is buried in an opening of the initial oxide film 117 and the interlayer insulating film 111, and a silicide layer 134 of the source ring 125 is formed as a p ++ The source ring 125 is in ohmic contact with the type contact region 108. The source ring 125 is electrically connected to the source electrode 112. This configuration allows hole current in the periphery of the active region to be extracted to the source ring 125 and flow to the source electrode 112.

[0028] 12, the transition region 141 is provided with a gate ring 124 for connecting the gate electrode 110 to a gate electrode pad 127 (see FIG. 14). + An initial oxide film 117 is provided to insulate the contact region 108, and polysilicon 118 connected to the gate electrode 110 is provided on the initial oxide film 117. The gate ring 124 is connected to the polysilicon 118 through an opening provided in the interlayer insulating film 111.

[0029] FIG. 13 shows a gate ring 124, a source ring 125 and a p + 13 is a plan view showing the top structure of only the gate contact region 108. As shown in FIG. 13, below the gate ring 124 and the source ring 125, p + A mold contact region 108 is provided.

[0030] Fig. 14 is a plan view showing the upper surface electrode structure of a conventional silicon carbide semiconductor device. As shown in Fig. 14, a source electrode pad 126 connected to source electrode 112 (see Figs. 11 and 12) and a gate electrode pad 127 connected to gate electrode 110 (see Figs. 11 and 12) via gate ring 124 are provided on the upper surface of trench MOSFET 150. Gate ring 124 is formed in a substantially rectangular shape surrounding source electrode pad 126. Source ring 125 is connected to source electrode 112 by source ring connection portion 128. There may be multiple source ring connection portions 128.

[0031] In the silicon carbide semiconductor device provided with the source ring 125, when the resistance increases due to a rise in temperature during the IFSM test, the p ++ A current 145 flows through the contact region 108, and this current 145 is concentrated in the source ring connection part 128 as shown in FIG. 14, which causes a problem of a decrease in the IFSM resistance.

[0032] Preferred embodiments of a semiconductor device according to the present disclosure that solve the problems of conventional semiconductor devices described above will be described in detail below with reference to the accompanying drawings. In this specification and the accompanying drawings, layers and regions prefixed with n or p indicate that electrons or holes are the majority carriers, respectively. The + and - prefixed with n or p indicate that the impurity concentration is higher or lower than that of layers or regions not prefixed with that prefix, respectively. In the following description of the embodiments and the accompanying drawings, similar components are designated by the same reference numerals, and redundant explanations will be omitted. Furthermore, descriptions of "same" or "equivalent" should preferably include variations within 5% in consideration of variations in manufacturing.

[0033] (Embodiment 1) The semiconductor device according to the present disclosure is configured using a wide bandgap semiconductor. In the first embodiment, a silicon carbide semiconductor device fabricated (manufactured) using, for example, silicon carbide (SiC) as a wide bandgap semiconductor will be described using a trench MOSFET 50 as an example. FIG. 1 shows a gate ring 24, a source ring 25, a p + type contact region 8 and n ++ Fig. 2 is a plan view showing an upper surface structure of only type source region 7. Fig. 2 is a Y-Y' cross-sectional view of Fig. 1 showing the structure of the silicon carbide semiconductor device according to the first embodiment. Fig. 3 is an X-X' cross-sectional view of Fig. 1 showing the structure of the silicon carbide semiconductor device according to the first embodiment.

[0034] 1 to 3, the trench MOSFET 50 according to the first embodiment includes an active region 40 in which an element structure is formed and through which a current flows when the device is in an on-state, a termination structure region 42 that surrounds the active region 40 and maintains a breakdown voltage, and a transition region 41 between the active region 40 and the termination structure region 42. The trench MOSFET 50 also includes an n + A first main surface (front surface) of a silicon carbide substrate (semiconductor substrate of a first conductivity type) 1, for example, a (0001) surface (Si surface), is provided with an n - A mold drift layer 2 is deposited.

[0035] n + The silicon carbide substrate 1 is a silicon carbide single crystal substrate. - The n-type drift layer 2 + The impurity concentration is lower than that of the silicon carbide substrate 1, and is, for example, a low-concentration n-type drift layer. - n-type drift layer (first conductivity type semiconductor substrate) 2 + An n-type heavily doped region (not shown) may be provided on the surface opposite to the silicon carbide substrate 1 side. + The impurity concentration is lower than that of the n-type silicon carbide substrate 1. - It is a high-concentration n-type layer having a higher impurity concentration than the n-type drift layer 2.

[0036] n - n-type drift layer 2 (or n-type high concentration region if provided) + On the surface side opposite to the silicon carbide substrate 1 side, a p-type base layer (first semiconductor region of a second conductivity type) 6 is provided. + A silicon carbide substrate 1 and an n - The n-type drift layer 2 and the p-type base layer 6 together constitute a silicon carbide semiconductor substrate. ++ type source region (second semiconductor region of the first conductivity type) 7 and p ++ A contact region (first semiconductor region of the second conductivity type) 8 is selectively provided on each of the first and second semiconductor regions.

[0037] n +A drain electrode serving as a back surface electrode 13 is provided on the second main surface (back surface, ie, the back surface of the silicon carbide semiconductor base) of the silicon carbide substrate 1.

[0038] A trench structure is formed on the first main surface side (p-type base layer 6 side) of the silicon carbide semiconductor substrate. Specifically, the trench 16 is formed between the n-type + The n-type silicon carbide semiconductor substrate 1 is connected to the surface opposite to the n-type silicon carbide substrate 1 (the first main surface of the silicon carbide semiconductor substrate) through the p-type base layer 6. - The trenches 16 are formed in a stripe pattern. A gate insulating film 9 is formed on the bottom and side walls of the trenches 16 along the inner walls of the trenches 16, and a gate electrode 10 is formed on the front surface of the gate insulating film 9 in the trenches 16. The gate electrode 10 is formed by the gate insulating film 9. - The gate electrode 10 is insulated from the p-type drift layer 2 and the p-type base layer 6. A part of the gate electrode 10 may protrude from above the trench 16 (the side where the source electrode 12, which will be described later, is provided) toward the source electrode 12.

[0039] n - n-type drift layer 2 + On the opposite side to the silicon carbide substrate 1 side (the first main surface side of the silicon carbide semiconductor base), + A second p-type base region (third semiconductor region of the second conductivity type) 4 is selectively provided. + The base region 4 has at least n - n-type drift layer 2 + The second p-type silicon carbide substrate 1 is provided on the surface layer opposite to the second p-type silicon carbide substrate 1. + The base region 4 is separated from the trench 16 and extends to a position deeper than the bottom of the trench 16 on the drain side. + The mold base region 4 is a first p + The first p + Mold area 4a and 1st p + The second p provided on the surface of the mold region 4a + It is composed of a mold region 4b.

[0040] The first p + A mold base region 3 is provided. + The width of the mold base region 3 is equal to or wider than the width of the trench 16. The bottom of the trench 16 is the first p + The p-type base layer 6 and the first p-type base region 3 may be connected to each other. + n type base region 3 sandwiched - The first p + Type base region 3 and second p + The base region 4 is doped with, for example, aluminum (Al).

[0041] 1st p. + The first base region 3 + A part of the base region 3 is extended to the trench side to form a second p + The second p + The first p-type base region 4 on the drain side from the bottom of the trench 16 + A part of the mold region 4a is extended to form the first p + The second p + The second p of the base region 4 on the source side from the bottom of the trench 16 + 2 and 3, the first p + Type base region 3 and second p + The p-type base layer 6 is separated from the second p-type base region 4 in the active region 40 and the transition region 41. + Type regions 4b and n - It is provided so as to cover the mold drift layer 2 .

[0042] In addition, in the trench 16 closest to the transition region 41 in the active region 40, the sidewall of the trench 16 on the transition region 41 side is p ++ Type contact region 8, first p + Mold region 4a and 2p + The second p + The mold region 4b is the first p +The trench 16 is in contact with the n-type base region 3. Therefore, the sidewall of the trench 16 on the transition region 41 side is - It is not in contact with the mold drift layer.

[0043] An interlayer insulating film 11 is provided on the entire front surface side of the silicon carbide substrate so as to cover the gate electrode 10 embedded in the trench 16. A source electrode (front surface electrode) 12 is connected to the n-type semiconductor layer 11 through a contact hole opened in the interlayer insulating film 11. ++ Type source region 7 and p ++ The source electrode 12 is in ohmic contact with the gate electrode region 8. The source electrode 12 is electrically insulated from the gate electrode 10 by an interlayer insulating film 11. A source electrode pad (not shown) is provided on the source electrode 12. The source electrode 12 and the source electrode pad may be a single layer, or may be made of different materials stacked together.

[0044] Although three trench MOS structures are shown in the active region 40 of FIGS. 2 and 3, many more trench MOS (metal-oxide-semiconductor insulated gate) structures may be arranged in parallel.

[0045] In the transition region 41, a gate ring 24 for connecting the gate electrode 10 to the gate electrode pad 27 is formed in a substantially rectangular shape surrounding the periphery of the active region 40. In the transition region 41, p ++ In order to insulate the p-type contact region 8, ++ An initial oxide film 17, which functions as a field oxide film, is provided on the mold contact region 8. A gate insulating film 9 is provided on the initial oxide film 17, and polysilicon 18, which is connected to the gate electrode 10, is provided on the gate insulating film 9. A gate ring 24 is connected to the polysilicon 18 through an opening provided in the interlayer insulating film 11.

[0046] In the transition region 41, a source ring 25 for extracting electric charges is formed in a substantially rectangular shape surrounding the periphery of the gate ring 24. The source ring 25 is connected to the source electrode 12 by a source ring connection part 28. There may be a plurality of source ring connection parts 28. The source ring 25 is connected to the n-type electrode 12 by an opening provided in the interlayer insulating film 11, the gate insulating film 9, and the initial oxide film 17. ++ The source ring 25 is connected to the source region 7. This allows the source ring 25 to extract the current generated in the transition region 41 to the source electrode 10.

[0047] Furthermore, the termination structure region 42 does not include the p-type base layer 6 and the n-type high concentration region. - The n-type drift layer 2 is exposed. - On the type drift layer 2, a breakdown voltage structure such as a guard ring structure 21 or a JTE (Junction Termination Extension) structure is provided.

[0048] The guard ring structure 21 is formed from the inside (transition region 41 side) to the outside (n + A plurality of dispersed p-type regions, the impurity concentration of which decreases with increasing distance from the n-type silicon carbide substrate 1 (the end side of the n-type silicon carbide substrate 1), are arranged in a substantially rectangular planar shape surrounding the periphery of the active region 40 and the transition region 41. Alternatively, instead of changing the impurity concentration, the spacing between the p-type regions may be increased from the inside to the outside, or the width of the p-type regions may be decreased. In the case of a JTE structure, the impurity concentration increases from the inside (the transition region 41 side) to the outside (the n-type silicon carbide substrate 1). + A plurality of adjacent p-type regions, the impurity concentration of which decreases with increasing distance from the substrate (toward the end of the silicon carbide substrate 1), are arranged in a substantially rectangular planar shape surrounding the active region 40 and the transition region 41. Outside these breakdown voltage structures, n-type regions serving as channel stoppers are formed. ++ The n-type region 23 is disposed. ++ An interlayer insulating film 11, a gate insulating film 9, and an initial oxide film 17 are provided on the surface of the mold region 23, and a protective film (not shown) made of polyimide or the like is provided on the outermost surface of the trench MOSFET 50.

[0049] Here, the boundary between the active region 40 and the transition region 41 is n++ The boundary between the transition region 41 and the termination structure region 42 is the bottom of the step of the initial oxide film 17 .

[0050] Also, n ++ the p-type source region 7, the p-type base layer 6 and the second p + The base region 4 extends to the termination structure region 42, and the breakdown voltage structure is provided outside these regions. ++ The second p-type source region 7 is shorter than the p-type base layer 6, and a part of the p-type base layer 6 is exposed on the surface of the silicon carbide substrate. + The first base region 4 + Mold area 4a is the 2nd p + Shorter than the mold region 4b, the second p + The p-type region 4 b has the same length as the p-type base layer 6 .

[0051] As shown in FIG. 1, in the first embodiment, p ++ The n-type contact region 8 is provided only inside the gate ring 24. ++ The source region 7 is p ++ The gate ring 24 and the source ring 25 are provided outside the contact region 8. + The silicon carbide substrate 1) has an n ++ A type source region 7 is provided.

[0052] In addition, as shown in FIGS. 2 and 3, in the first embodiment, p ++ The contact region 8 is not provided in the transition region 41 or the termination structure region 42, but is provided in the portion of the active region 40 that is closest to the transition region 41 and in contact with the sidewall of the trench 16. ++ The source region 7 is p ++ In contact with the contact region 8, ++ The source ring 25 is formed in the n-type contact region 8 through the opening of the interlayer insulating film 11. ++ The p ++ It is not in contact with the mold contact region 8.

[0053] Thus, the underside of the source ring 25 is ++ A diode is formed from the p-type source region 7 and the p-type base layer 6. This allows current to flow from the p-type base layer 6 to the source ring 25, and prevents current from flowing from the source ring 25 to the p-type base layer 6. Therefore, even if the resistance increases due to a temperature rise during the IFSM test, the current from the source ring 25 to the p-type base layer 6 is prevented from flowing. ++ This can prevent current 45 from flowing in type contact region 8, and can prevent current 45 from concentrating in source ring connection portion 28, thereby improving the IFSM resistance.

[0054] (Method for Manufacturing Silicon Carbide Semiconductor Device According to First Embodiment) The silicon carbide semiconductor device according to the first embodiment can be fabricated by the following method. Here, a case where a MOSFET with a breakdown voltage of 1200 V is fabricated will be described as an example. First, for example, 2.0×10 19 / cm 3 The n-type impurity concentration of silicon carbide single crystal is determined by doping with n-type impurities (dopants) such as nitrogen (N). + A silicon carbide substrate (semiconductor wafer) 1 is prepared. + The front surface of the silicon carbide substrate 1 may be a (0001) plane having an off-angle of about 4 degrees in the <11-20> direction. + The front surface of the silicon carbide substrate 1 is coated with, for example, 1.0×10 16 / cm 3 n-type impurities such as nitrogen are doped to achieve an impurity concentration of - The drift layer 2 is epitaxially grown to a thickness of, for example, 10 μm.

[0055] Next, photolithography and ion implantation are used to create n - In this ion implantation, for example, 1×10 17 / cm 3 Alternatively, an n-type impurity (dopant) such as nitrogen may be implanted to a concentration of 0.1 to 1.0.

[0056] Next, photolithography and ion implantation are used to create n - The first p + The base region 3 and the first p + The n-type region 4a is selectively formed. - The second p + In this ion implantation, a p-type impurity (dopant) such as aluminum (Al) is implanted into the first p + Mold base region 3, first p + Mold region 4a and 2p + The impurity concentration of the mold region 4b is 5.0×10 18 / cm 3 The mixture may be injected so that

[0057] Next, n - On the surface of the drift layer 2, for example, 2.0 × 10 17 / cm 3 The p-type base layer 6 is doped with p-type impurities such as aluminum so as to have an impurity concentration of 1.3 μm, and is then epitaxially grown to a thickness of, for example, 1.3 μm.

[0058] In the process up to this point, n + On the front surface of the silicon carbide substrate 1, - A silicon carbide substrate is fabricated by sequentially stacking a silicon carbide drift layer 2 and a p-type base layer 6. Next, a set of steps including forming an ion implantation mask by photolithography and etching, ion implantation using this ion implantation mask, and removal of the ion implantation mask is repeatedly performed under different ion implantation conditions to implant n ions into the surface layer of the p-type base layer 6. ++ Type source region 7 and p ++ The p-type contact region 8 is formed. ++ The impurity concentration of the contact region 8 is 1.0×10 20 / cm 3 It is desirable to make it so that it is more than this.

[0059] In the transition region 41 and the termination structure region 42, n ++ The source region 7 is p ++The p-type contact region 8 is not formed, and n-type impurities are implanted into the region below the source ring 25. ++ The impurity concentration of the contact region 8 is the same as that of the n-type contact region 41 and the termination structure region 42. ++ The impurity concentration of the source region 7 is higher than that of the source region 7 .

[0060] Next, in the termination structure region 42, the guard ring structure 21 is selectively formed by photolithography and ion implantation. Next, in the termination structure region 42, the n ++ A mold region 23 is selectively formed.

[0061] Next, heat treatment (annealing) is performed to form, for example, p + Type base region 3, n ++ Type source region 7, p ++ type contact region 8, guard ring structure 21, n ++ The mold region 23 is activated. The temperature of the heat treatment may be, for example, about 1700°C. The time of the heat treatment may be, for example, about 2 minutes. As described above, the ion implantation regions may be activated all at once by a single heat treatment, or the heat treatment may be performed each time an ion implantation is performed.

[0062] Next, the surface of the p-type base layer 6 (i.e., n ++ Type source region 7 and p ++ An oxide film is formed on the surface of the contact region 8. The oxide film may be, for example, a thermally oxidized film or a deposited film. The thickness of the oxide film in the active region 40 is thinner than the thicker portion of the oxide film formed on the outer periphery of the termination structure region 42.

[0063] Next, a resist mask (not shown) with predetermined openings is formed on the surface of the oxide film by photolithography. Next, openings are formed in the oxide film by dry etching using the resist mask. Next, the resist mask is removed, and anisotropic dry etching is performed using the oxide film as a mask to remove n ++through the p-type source region 7 and the p-type base layer 6; - A trench 16 is formed so as to reach the first p-type drift layer 2. The bottom of the trench 16 is + The mold base region 3 is reached.

[0064] Next, isotropic etching and sacrificial oxidation are performed on the oxide film. This process removes damage to trench 16 and rounds the bottom of trench 16. The order of isotropic etching and sacrificial oxidation is not critical. Alternatively, only one of isotropic etching and sacrificial oxidation may be performed. After that, the thin oxide film used as a mask for forming trench 16 is removed. At this time, the thin oxide film and the sacrificial oxide film may be removed simultaneously. Because the oxide film has thin portions and thick portions in termination structure region 42, a full-surface etching is performed to remove the thin portions of the oxide film, leaving the oxide film in the thick portions of termination structure region 42. The sacrificial oxide film (not shown) may be removed along with the thin portions of the oxide film. Alternatively, the oxide film may be removed using photolithography and etching, leaving the oxide film in termination structure region 42. The oxide film remaining in termination structure region 42 (thick portions of the oxide film) becomes initial oxide film 17.

[0065] Next, the initial oxide film 17, n ++ Type source region 7 and p ++ A gate insulating film 9 is formed along the surface of the contact region 8 and the bottom and sidewalls of the trench 16. This gate insulating film 9 may be formed by thermal oxidation at a temperature of about 1000°C in an oxygen atmosphere. Alternatively, this gate insulating film 9 may be formed by a deposition method using a chemical reaction such as high temperature oxidation (HTO).

[0066] Next, a polycrystalline silicon layer doped with, for example, phosphorus atoms (P) is formed on the gate insulating film 9. This polycrystalline silicon layer is formed so as to fill the trench 16. This polycrystalline silicon layer is patterned and left inside the trench 16 to form the gate electrode 10. A portion of the gate electrode 10 may protrude above the trench 16 toward the source electrode 12.

[0067] Next, for example, phosphorus sulphide (PSG) is deposited to a thickness of about 1 μm to form an interlayer insulating film 11 so as to cover the gate insulating film 9 and the gate electrode 10. The interlayer insulating film 11 and the gate insulating film 9 are patterned and selectively removed to form contact holes, and n ++ Type source region 7 and p ++ The mold contact region 8 is exposed. After that, the interlayer insulating film 11 is planarized by performing a heat treatment (reflow).

[0068] Next, a conductive film that will become the source electrode 12 is formed in the contact hole and on the interlayer insulating film 11. This conductive film is selectively removed, for example, to leave the source electrode 12 only in the contact hole. The source electrode 12 is p ++ The p-type contact region 8 and the p-type base layer 6 are formed to form ohmic contacts.

[0069] Next, for example, an aluminum film is formed by sputtering to a thickness of about 5 μm, covering the source electrode 12 and the interlayer insulating film 11. The aluminum film is then selectively removed, leaving a film covering the active region 40 and transition region 41 of the entire device, thereby forming the gate ring 24, source ring 25, source electrode pad 26, and gate electrode pad 27. After this, polyimide is applied as a surface passivation film by, for example, spin coating, patterned using photolithography, and heat-treated (cured) to form a protective film (not shown). The source electrode pad 26 may be formed at the portion where the source electrode 12 is exposed from the polyimide, or by depositing a film of another metal, such as nickel, at the portion where the source electrode 12 is exposed from the polyimide.

[0070] Next, the back surface (n + A back electrode 13 made of, for example, a nickel (Ni) film is formed on the back surface of the silicon carbide substrate 1. Then, a heat treatment is performed at a temperature of, for example, about 970° C. to form an n-type silicon carbide substrate. + The silicon carbide substrate 1 and the back surface electrode 13 are ohmic-contacted.

[0071] The back electrode 13 may be a laminated film in which titanium (Ti), nickel (Ni), and gold (Au) are laminated in this order, or a laminated film of nickel (Ni), titanium (Ti), molybdenum (Mo), and gold (Au). In this manner, the semiconductor device shown in FIGS. 1 to 3 is completed.

[0072] Thus, according to the first embodiment, the lower side of the source ring is ++ By using a p-type source region, it is possible to pass current from the p-type base layer to the source ring, and to prevent current from flowing from the source ring to the p-type base layer. Therefore, even if the resistance increases due to a temperature rise during the IFSM test, the current from the source ring to the p-type base layer is prevented. ++ This can prevent current from flowing in the mold contact region, prevent current from concentrating in the source ring connection portion, and improve the IFSM tolerance.

[0073] (Embodiment 2) Next, a second embodiment will be described. FIG. 4 shows a gate ring 24, a source ring 25, and a p + type contact region 8 and n ++ 5 is a plan view showing the upper surface structure of only the n-type source region 7 seen from above. FIG. 5 is a cross-sectional view taken along the line YY′ in FIG. 4 showing the structure of the silicon carbide semiconductor device according to the second embodiment. - The structure on the n-type drift layer 2 is the same as that shown in FIG. - The structure inside the drift layer 2 is the same as that shown in FIG. 5, and therefore the cross section taken along line XX' in FIG. 4 is omitted.

[0074] In the second embodiment, n ++ The width of the p-type source region 7 is narrower than that of the first embodiment. ++ The width of the contact region 8 is increased. ++ The contact region 8 is provided only inside the source ring 25, and the n ++ The source region 7 is p ++ The n-type contact region 8 is provided outside the n-type contact region 8 and below the source ring 25. ++ A type source region 7 is provided.

[0075] Also, as shown in FIG. 5, in the second embodiment, p ++ The n-type contact region 8 is provided in the surface layer of the p-type base layer 6 from the sidewall of the trench 16 in the active region 40 closest to the transition region 41 to partway through the transition region 41. ++ The source region 7 is p ++ In contact with the contact region 8, ++ The source ring 25 is formed in the n-type contact region 8 through the opening of the interlayer insulating film 11. ++ The source ring 25 is in contact with the p-type source region 7. ++ It is not in contact with the mold contact region 8.

[0076] In addition, the n ++ The source region 7 is p ++ The p-type contact region 8 is not formed, and n-type impurities are implanted into the region below the source ring 25. ++ The impurity concentration of the contact region 8 is the same as that of the n-type contact region 41 and the termination structure region 42. ++ The impurity concentration of the source region 7 is higher than that of the source region 7 .

[0077] In the second embodiment, as in the first embodiment, the lower side of the source ring 25 is ++ A diode is formed consisting of the n-type source region 7 and the p-type base layer 6. This provides the same effects as in the first embodiment.++ By narrowing the width of the source region 7, Vf (forward voltage) can be reduced.

[0078] Thus, according to the second embodiment, the lower side of the source ring is ++ By using the n-type source region, the same effect as in the first embodiment can be obtained. ++ By narrowing the width of the source region, Vf can be reduced.

[0079] (Embodiment 3) Next, a third embodiment will be described. FIG. 6 shows a gate ring 24, a source ring 25, and a p + type contact region 8 and n ++ 7 is a plan view showing the upper surface structure of only the n-type source region 7 seen from above. FIG. 7 is a cross-sectional view taken along the line YY′ in FIG. 6 showing the structure of the silicon carbide semiconductor device according to the third embodiment. - The structure on the n-type drift layer 2 is the same as that shown in FIG. - The structure inside the drift layer 2 is the same as that shown in FIG. 7, and therefore the cross section taken along line XX' in FIG. 6 is omitted.

[0080] In the third embodiment, n ++ The width of the p-type source region 7 is narrower than that of the second embodiment. ++ The width of the contact region 8 is increased. ++ The contact region 8 is provided inside the source ring 25 and outside the source ring 25, and n ++ The source region 7 is p ++ The source ring 25 is provided between the contact regions 8 and has an n ++ A type source region 7 is provided.

[0081] In addition, as shown in FIG. 7, in the third embodiment, p ++ The n-type contact region 8 extends from the sidewall of the trench 16 closest to the transition region 41 in the active region 40 to the middle of the transition region 41. ++The n-type source region 7 is formed in the surface layer of the p-type base layer 6. ++ The source region 7 is p ++ In contact with the contact region 8, ++ The source ring 25 is provided between the n-type contact regions 8. ++ The source ring 25 is in contact with the p-type source region 7. ++ It is not in contact with the mold contact region 8.

[0082] In the third embodiment, as in the first embodiment, the lower side of the source ring 25 is ++ A diode is formed by the n-type source region 7 and the p-type base layer 6. This provides the same effects as in the first embodiment. ++ By narrowing the width of the source region 7, the forward voltage (Vf) can be further reduced.

[0083] Also, n of the transition region 41 ++ The source region 7 is p ++ The p-type contact region 8 is not formed, and n-type impurities are implanted into the region below the source ring 25. ++ The impurity concentration of the contact region 8 is ++ The impurity concentration of the source region 7 is higher than that of the source region 7 .

[0084] Thus, according to the third embodiment, the lower side of the source ring is ++ By using the n-type source region, the same effect as in the first embodiment can be obtained. ++ By narrowing the width of the source region, Vf can be further reduced.

[0085] (Fourth embodiment) Next, a fourth embodiment will be described. Fig. 8 is a cross-sectional view taken along the line YY' in Fig. 6, showing the structure of a silicon carbide semiconductor device according to the fourth embodiment. The plan view of the fourth embodiment is the same as Fig. 6 of the third embodiment, and therefore will not be described again.- The structure on the n-type drift layer 2 is the same as that shown in FIG. - The structure inside the type drift layer 2 is the same as that in FIG. 8, and therefore the cross section taken along line XX' in FIG. 6 is omitted.

[0086] In the fourth embodiment, p ++ The width and n ++ The width of the n-type source region 7 is the same as that of the third embodiment, and the n-type source region 7 is formed below the source ring 25. ++ In the fourth embodiment, the n-type source region 7 is deeper than that in the third embodiment. ++ The source region 7 is p ++ For example, the n-type contact region 8 is located below the source ring 25. ++ The p-type source region 7 is connected to the p-type base layer 6 and the second p + The first p + The depth of the n-type region 4a is so deep that it reaches the surface of the n-type region 4a. ++ The source region 7 is p ++ the p-type contact region 8, the p-type base layer 6 and the second p + It can be formed by implanting n-type impurities into the region below the source ring 25 without forming the type region 4b.

[0087] In the fourth embodiment, as in the first embodiment, the lower side of the source ring 25 is ++ type source region 7 and the first p + A diode is formed from the n-type region 4a. This provides the same effects as in the first embodiment. In the fourth embodiment, the n-type region 4a is formed from the n-type region 4a. ++ By forming the n-type source region 7 deeply, ++ The first p-type source region 7 + Therefore, the difference in concentration between the n-type and p-type regions (n ++ Impurity concentration of the first p-type source region 7 + The impurity concentration of the n-type region 4a is the difference between the n-type and p-type impurity concentrations in the first to third embodiments ( ++The impurity concentration of the n-type source region 7 minus the impurity concentration of the p-type base layer 6 is smaller than the impurity concentration of the p-type source region 7, and avalanche between the n-type and p-type regions when a reverse bias is applied can be suppressed.

[0088] Thus, according to the fourth embodiment, the lower side of the source ring is ++ By using the n-type source region, the same effect as in the first embodiment can be obtained. ++ By forming the source region deep, the difference in concentration between the n-type and p-type can be reduced, and avalanche between the n-type and p-type when a reverse bias is applied can be suppressed.

[0089] The effects of the present disclosure are demonstrated below by simulation. FIG. 9 is a cross-sectional view showing current distribution in a conventional silicon carbide semiconductor device. FIG. 10 is a cross-sectional view showing current distribution in a silicon carbide semiconductor device according to the first embodiment. FIGS. 9 and 10 show the results of simulating current distribution under the conditions of Vgs=−3 V and Is=500 A, with the darker hatched areas indicating larger current values. Although not explicitly shown in FIGS. 9 and 10, source rings 25, 125 are electrically connected to source electrodes 12, 112.

[0090] As shown in FIG. 9 , in the conventional silicon carbide semiconductor device, current concentrates below source ring 125, resulting in a large current value below source ring 125. On the other hand, as shown in FIG. 10 , in the silicon carbide semiconductor device according to the first embodiment, current concentration below source ring 25 is suppressed, resulting in a small current value. Note that in the silicon carbide semiconductor device according to the first embodiment, current concentrates below source electrode 12, resulting in a large current value below source electrode 12. This is because the simulation was performed using a single opening in source electrode 12 in active region 30, resulting in current concentration in one source electrode 12. In an actual semiconductor device, source electrode 12 has a large area and multiple openings, so current does not concentrate in one opening and such a situation does not occur.

[0091] In the above, the present disclosure has been described using an example in which a MOS gate structure is configured on the first main surface of a silicon carbide substrate, but the present disclosure is not limited to this and various changes can be made to the surface orientation of the substrate main surface, etc. Furthermore, in the embodiments of the present disclosure, a trench MOSFET has been described as an example, but the present disclosure is not limited to this and can be applied to semiconductor devices with various configurations, such as MOS semiconductor devices such as trench IGBTs. Furthermore, in each embodiment of the present disclosure, the first conductivity type is n-type and the second conductivity type is p-type, but the present disclosure is equally valid even if the first conductivity type is p-type and the second conductivity type is n-type. [Industrial Applicability]

[0092] As described above, the semiconductor device according to the present disclosure is useful as a high-voltage semiconductor device used in power conversion devices and power supply devices for various industrial machines. [Explanation of symbols]

[0093] 1, 101 n + Silicon carbide substrate 2, 102 n - Mold drift layer 3, 103 1st p. + Type-based domain 4, 104 2nd p. + Type-based domain 4a, 104a 1st p. + type area 4b, 104b 2nd p. + type area 6, 106 p-type base layer 7, 107 n ++ Type Source Area 8, 108 p. ++ Mold contact area 9, 109 Gate insulating film 10, 110 Gate electrode 11, 111 Interlayer insulating film 12, 112 Source electrode 13, 113 Back electrode 16, 116 trenches 17, 117 Initial oxide film 18, 118 Polysilicon 21, 121 Guard ring structure 23, 123 n ++ type area 24, 124 Gate Ring 25, 125 Source Ring 26, 126 Source electrode pad 27, 127 Gate electrode pad 28, 128 Source Ring Connection 40, 140 active area 41, 141 transition region 42, 142 Termination structure area 45, 145 current 50 Trench MOSFET

Claims

1. a first conductivity type semiconductor substrate, the first conductivity type semiconductor substrate including an active region through which a main current flows, a termination region surrounding the active region, and a transition region between the active region and the termination region; a front surface electrode connected to a first semiconductor region of a second conductivity type on a front surface side of the semiconductor substrate in the active region; a source ring electrically connected to the front surface electrode in the transition region and connected to a second semiconductor region of the first conductivity type for drawing out current; The semiconductor device is characterized in that the second semiconductor region is provided on the semiconductor substrate side of the source ring.

2. 2. The semiconductor device according to claim 1, wherein the second semiconductor region is provided in the active region, the termination region, and the transition region, and in the transition region, the second semiconductor region is provided over the entire front surface side of the semiconductor substrate.

3. the first semiconductor region is provided in the active region and the transition region; 2. The semiconductor device according to claim 1, wherein the second semiconductor region is provided in the termination region and the transition region in contact with the first semiconductor region, and in the transition region, is provided on the semiconductor substrate side of the source ring.

4. the first semiconductor region is provided in the active region, the termination region, and the transition region; 2. The semiconductor device according to claim 1, wherein the second semiconductor region is provided in the transition region in contact with the first semiconductor region, and is provided in the transition region on the semiconductor substrate side of the source ring.

5. a third semiconductor region of a second conductivity type having an impurity concentration higher than that of the first semiconductor region, on the semiconductor substrate side of the first semiconductor region; 5. The semiconductor device according to claim 4, wherein the second semiconductor region is deeper than the first semiconductor region and reaches the third semiconductor region.

6. 6. The semiconductor device according to claim 1, wherein the impurity concentration of the first semiconductor region is higher than the impurity concentration of the second semiconductor region.

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