Semiconductor device

Abstract

To provide a semiconductor device having a memory device capable of achieving both high speed and stable operation.SOLUTION: A semiconductor device includes: a resistance-change type memory cell array 1100_1; a sense amplifier SA electrically connected to the resistance-change type memory cell array 1100_1; and a clamp voltage generation circuit CLPG electrically connected to the sense amplifier SA. The sense amplifier SA includes: an amplifying unit SAP that amplifies a voltage in a sense node; a first clamp circuit having NMOS transistors N1 and N2 each of whose gate terminals is electrically connected; a second clamp circuit having NMOS transistors N3 and N4 each of whose gate terminals is electrically connected; a NMOS transistor N5 electrically connected to the resistance-change type memory cell array 1100_1; a reference resistor Rref; and a NMOS transistor N6 electrically connected to the reference resistor Rref.SELECTED DRAWING: Figure 1

Description

[Technical Field]

[0001] The present invention relates to a semiconductor device, and more particularly to a semiconductor device including a memory device having, for example, a resistance change type memory cell. [Background technology]

[0002] A resistance change memory cell is a memory element whose resistance value changes depending on the information stored therein, and an example of a memory device having such a resistance change memory cell (hereinafter also referred to simply as a memory cell) is a magnetoresistive random access memory (hereinafter also referred to as an MRAM). Technology related to MRAM is disclosed in, for example, Non-Patent Document 1. [Prior art documents] [Non-patent literature]

[0003] [Non-Patent Document 1] “A Reflow-capable,Embedded 8Mb STT-MRAM Macro with 9nS Read Access Time in 16nm FinFET Logic CMOS Process”, TSMC, IEDM 2020 Summary of the Invention [Problem to be solved by the invention]

[0004] The present inventors have studied the technology relating to MRAM shown in Non-Patent Document 1. The study by the present inventors will be explained later in a comparative example and will not be discussed here, but it has been found that the technology shown in Non-Patent Document 1 has a problem in that it is difficult to achieve both high-speed operation and stable operation at high temperatures. [Means for solving the problem]

[0005] A brief summary of representative embodiments disclosed in the present application is as follows: In the following description, a field effect transistor is referred to as a MOS transistor, an N-channel MOS transistor is referred to as an NMOS transistor, and a P-channel MOS transistor is referred to as a PMOS transistor.

[0006] A semiconductor device according to one embodiment includes a resistance change type memory cell array, a sense amplifier electrically connected to the resistance change type memory cell array, and a clamp voltage generating circuit electrically connected to the sense amplifier.

[0007] In the semiconductor device, the sense amplifier includes an amplifier unit that amplifies a voltage at a sense node, a first clamp circuit having a first NMOS transistor and a second NMOS transistor whose gate terminals are electrically connected to each other, a second clamp circuit having a third NMOS transistor and a fourth NMOS transistor whose gate terminals are electrically connected to each other, a fifth NMOS transistor electrically connected to the resistance change type memory cell array, a reference resistor, and a sixth NMOS transistor electrically connected to the reference resistor.

[0008] Here, the drain terminal of the third NMOS transistor is electrically connected to the amplifier section via a first node constituting a sense node, the drain terminal of the fourth NMOS transistor is electrically connected to the amplifier section via a second node constituting a sense node, the source terminal of the third NMOS transistor is electrically connected to the drain terminal of the first NMOS transistor via the third node, the source terminal of the fourth NMOS transistor is electrically connected to the drain terminal of the second NMOS transistor via the fourth node, the source terminal of the first NMOS transistor is electrically connected to the drain terminal of the fifth NMOS transistor via a fifth node, and the source terminal of the second NMOS transistor is electrically connected to the drain terminal of the fifth NMOS transistor via the fifth node. the terminal is electrically connected to the drain terminal of the sixth NMOS transistor via a sixth node, the source terminal of the fifth NMOS transistor is electrically connected to the resistance change type memory cell array, and the source terminal of the sixth NMOS transistor is electrically connected to the reference resistor; the clamp voltage generation circuit supplies a first clamp voltage to the gate terminals of the first NMOS transistor and the second NMOS transistor, and supplies a second clamp voltage to the gate terminals of the third NMOS transistor and the fourth NMOS transistor, and a mutual conductance of the third NMOS transistor and the fourth NMOS transistor is lower than a mutual conductance of the first NMOS transistor and the second NMOS transistor.

[0009] Other objects and novel features will become apparent from the description of this specification and the accompanying drawings. [Effects of the Invention]

[0010] According to one embodiment, it is possible to provide a semiconductor device including a memory device that can achieve both high-speed operation and stable operation. [Brief explanation of the drawings]

[0011] [Figure 1] 1A and 1B are diagrams for explaining a sense amplifier according to the first embodiment. [Figure 2]FIG. 2 is a circuit diagram showing the configuration of the clamp circuit and the clamp voltage generating circuit according to the first embodiment. [Figure 3] FIG. 3 is a circuit diagram showing the configuration of the clamp circuit and the clamp voltage generating circuit according to the first embodiment. [Figure 4] FIG. 4 is a circuit diagram showing the configuration of the current correction circuit according to the first embodiment. [Figure 5] FIG. 5 is a diagram for explaining the current correction circuit according to the first embodiment. [Figure 6] FIG. 6 is a diagram for explaining the current correction circuit according to the first embodiment. [Figure 7] FIG. 7 is a diagram for explaining the initialization circuit according to the first embodiment. [Figure 8] 8(A) and 8(B) are waveform diagrams for explaining the initialization circuit according to the first embodiment. [Figure 9] FIG. 9 is a circuit diagram illustrating an example of the initialization circuit according to the first embodiment. [Figure 10] FIG. 10 is a circuit diagram showing a configuration of a reference resistor according to the second embodiment. [Figure 11] FIG. 11 is a circuit diagram showing a configuration of a reference resistor according to a modification of the second embodiment. [Figure 12] 12(A) and 12(B) are diagrams for explaining a semiconductor device according to the second embodiment. [Figure 13] FIG. 13 is a block diagram showing the configuration of a nonvolatile memory device built into the semiconductor device according to the first embodiment. [Figure 14] FIG. 14 is a block diagram showing a configuration of the semiconductor device according to the first embodiment. [Figure 15] 15(A) and 15(B) are diagrams for explaining a comparative example investigated by the present inventors. [Figure 16] FIG. 16 is a diagram showing mathematical expressions for explaining the comparative example. [Figure 17] FIG. 17 is a circuit diagram showing the configuration of a reference resistor as a comparative example investigated by the present inventors. DETAILED DESCRIPTION OF THE INVENTION

[0012] Hereinafter, various embodiments of the present invention will be described with reference to the drawings. Note that the disclosure is merely an example, and any appropriate modifications that can be easily conceived by a person skilled in the art while maintaining the gist of the invention are naturally included within the scope of the present invention.

[0013] Furthermore, in this specification and each drawing, elements similar to those previously described with respect to the previous drawings are given the same reference numerals, and detailed descriptions thereof may be omitted as appropriate.

[0014] <Comparative Example> Several embodiments will be described below. However, to facilitate understanding, before describing the embodiments, the technology shown in Non-Patent Document 1 and the problems discovered by the inventors will be described using comparative examples.

[0015] <<Configuration and operation of the comparative example>> FIG. 15 is a diagram for explaining a comparative example studied by the present inventors. FIG. 15 is similar to FIG. 6 of Non-Patent Document 1. The main difference is that, for ease of explanation, the present inventors have added symbols (for example, Vthn, etc.) to FIG. 6 of Non-Patent Document 1 in FIG. 15. In FIG. 15, FIG. 15(A) shows a circuit diagram of the comparative example, and FIG. 15(B) is a waveform diagram showing the operation of FIG. 15(A).

[0016] Here, the circuit diagram of FIG. 15(A) shows a portion related to a sense amplifier used when reading information stored in a memory cell.

[0017] The sense amplifier is connected to a pair of sense nodes Q and QB, and includes a latch unit Latch that amplifies the small potential difference between the sense nodes Q and QB when activated by an activation signal LATCH and outputs DOUT, and a precharge circuit configured with PMOS transistors PP1 to PP3.

[0018] The potentials of the pair of sense nodes Q and QB are determined by the memory cell and the reference resistor. In FIG. 15A, the memory cell is equivalently represented by a current source Icell, and the reference resistor is equivalently represented by a current source Iref. The resistance value (cell resistance) of the memory cell is in a low resistance Rp or high resistance Rap state (low resistance Rp<high ​​resistance Rap) depending on the stored information. Therefore, the value of the current source Icell, which equivalently represents the memory cell, changes depending on the stored information. The value of the current source Iref, which equivalently represents the reference resistor, is a value (e.g., an intermediate value) between the value of the current source Icell corresponding to high resistance and the value of the current source Icell corresponding to low resistance.

[0019] Clamp elements are connected between the pair of sense nodes Q and QB and the memory cell (current source Icell) and reference resistor (current source Iref). The clamp elements are composed of NMOS transistors NN1 and NN2, whose gate terminals are supplied with a clamp voltage Vclamp. In FIG. 15(A), Vthn denotes the threshold voltage of the NMOS transistors NN1 and NN2, and Vbl denotes the voltage applied to the memory cell and reference resistor. The value of the memory cell voltage Vbl varies depending on the value of the cell resistance, but by appropriately setting the clamp voltage Vclamp and threshold voltage Vthn, it can be limited (clamped) to, for example, about 0.1 V.

[0020] 15B, even during the precharge period indicated by the symbol PTH (the period when the PMOS transistors PP1 to PP3 are on), the voltage Vbl applied to the memory cells and the reference resistors is clamped to about 0.1 V. Thereafter, during the discharge period indicated by the symbol DTH (the period when the PMOS transistors PP1 to PP3 are off), a potential difference determined by the memory cells and the reference resistors is generated between the sense nodes Q and QB, and during the sense period indicated by the symbol STH, the potential difference between the sense nodes Q and QB is amplified by the latch unit Latch.

[0021] 15A, NMOS transistors NN1A-NN1X, NN2A-NN2X and switches S1A-S1X, S2A-S2X are used to correct variations. That is, when there is a relative variation between the clamp element (NMOS transistor NN1) corresponding to the memory cell and the clamp element (NMOS transistor NN2) corresponding to the reference resistor, and / or when an offset occurs between the inputs of the latch unit Latch due to variations in the latch unit Latch, one of the switches S1A-S1X, S2A-S2X, for example (S2A), is turned on. This connects NMOS transistor NN2A in parallel with the clamp element (NMOS transistor NN2) corresponding to the reference resistor, for example, thereby enabling the variation to be reduced.

[0022] If variation correction is not required, the clamp element can be configured with two NMOS transistors NN1 and NN2, and even if a memory device is provided with multiple sense amplifiers, it is possible to suppress an increase in the area occupied by the clamp element. Furthermore, a common clamp voltage Vclamp can be used for the clamp elements provided in each of the multiple sense amplifiers, which also suppresses an increase in the area occupied.

[0023] <<Investigations by the Inventors>> In general, as the ambient temperature rises, the resistance ratio of the resistance value corresponding to the stored information in the memory cells of MRAM deteriorates. That is, depending on the stored information, the cell resistance becomes either a high resistance Rap or a low resistance Rp, and as the ambient temperature rises, the TMR ratio, which is the resistance ratio between the high resistance Rap and the low resistance Rp, deteriorates. The value of the current source Iref based on the reference resistance is set between the value of the current source Icell corresponding to the high resistance Rap and the value of the current source Icell corresponding to the low resistance Rp. However, as the temperature rises, the resistance ratio deteriorates, so the current difference between the current source Iref and the current source Icell decreases, and the read margin at high temperatures decreases.

[0024] In the configuration of the comparative example shown in FIG. 15, the read margin at high temperatures can be improved by the following two measures.

[0025] <<<First Method>>> The first method is to improve the transconductance (Gm) of the NMOS transistors NN1 and NN2 that make up the clamp element. For example, by improving (raising) the transconductance of the NMOS transistor NN1, it is possible to improve the conversion efficiency when converting cell resistance to cell current (corresponding to the current source Icell). Therefore, even if the TMR ratio deteriorates due to high temperatures, it is possible to ensure a sufficient read margin.

[0026] The first means will be explained in detail as follows using the formula shown in Fig. 16. In formula (1) in Fig. 16, symbol λ represents the channel length modulation coefficient of the NMOS transistors NN1 to NN1X, and symbol Vds represents the drain-source voltage of the NMOS transistors NN1 to NN1X.

[0027] For ease of explanation, let us assume that the channel length modulation coefficient λ is 0 and the multiplier 2 is 1. The current Ip (current source Icell) of the memory cell when the cell resistance is a low resistance Rp is expressed by equation (2), and the current Iap (current source Icell) of the memory cell when the cell resistance is a high resistance Rap is expressed by equation (3). In equations (2) and (3), the symbols Vbl(p) and Vbl(ap) represent the voltage of the memory cell generated when the cell resistance is a low resistance Rp and the voltage of the memory cell generated when the cell resistance is a high resistance Rap, as shown in equations (4) and (5). By substituting equations (4) and (5) into equations (2) and (3), equations (6) and (7) can be obtained.

[0028] As can be seen from equations (6) and (7), as the transconductance Gm increases, the ratio of the cell resistance to the memory cell current Ip, Iap increases. In other words, when the cell resistance changes from low resistance Rp to high resistance Rap (or from Rap to Rp), it becomes possible to increase the change in the cell current flowing through the memory cell, thereby ensuring a read margin.

[0029] <<<Second Method>>> The second means is to correct the variations using NMOS transistors NN1A to NN1X, NN2A to NN2X and switches S1A to S1X, S2A to S2X, as explained in Fig. 15(A). By performing the correction, for example, by reducing the offset between the inputs of the latch unit Latch, it is possible to improve the read margin.

[0030] <<<Issues arising from the first and second measures>>> The transconductance Gm is determined by the ratio (W / L) of the channel width W to the channel length L of an NMOS transistor. A first method is to improve the transconductance Gm by, for example, widening the channel width W of the NMOS transistor NN1. In this case, the overlap between the drain diffusion regions and gate terminals of the NMOS transistors NN1 and NN2 connected to the sense nodes Q and QB increases, and the drain capacitance (capacitance formed by the overlap between the drain diffusion regions and gate terminals) of the NMOS transistors NN1 and NN2 connected to the sense nodes Q and QB increases.

[0031] When the second method is adopted, the drain diffusion regions of the correction NMOS transistors NN1A-NN1X and NN2A-NN2X are connected to the drain diffusion regions of the NMOS transistors NN1 and NN2 by, for example, wiring. That is, the wiring connecting the correction NMOS transistors and the drain diffusion regions of the correction NMOS transistors are connected to the sense nodes Q and QB. Therefore, even when the second method is adopted, the parasitic capacitance (wiring capacitance, drain capacitance of the correction NMOS transistors, etc.) connected to the sense nodes Q and QB increases.

[0032] When the parasitic capacitance (including drain capacitance) connected to the sense nodes Q and QB increases, it takes time for the potentials of the sense nodes Q and QB to decrease according to the memory cell and reference resistance. Referring to Figure 15(B), the discharge period DTH shown in Figure 15(B) becomes longer, making it difficult to speed up the read operation.

[0033] In other words, if the read margin is secured or improved at high temperatures to ensure stable operation of MRAM, it becomes difficult to increase speed, and it has become clear that there is a problem in that it is difficult to achieve both stable operation at high temperatures and high speed at the same time.

[0034] (Embodiment 1) <Configuration of semiconductor device> Fig. 14 is a block diagram showing the configuration of a semiconductor device according to the first embodiment. In Fig. 14, 1000 indicates a semiconductor device. The semiconductor device 1000 includes an internal bus 1001 and a plurality of circuit blocks connected to the internal bus 1001. Fig. 14 shows, as examples of the plurality of circuit blocks, a processor 1002, a volatile memory device (RAM) 1003, a non-volatile memory device 1004, a timer 1005, an analog-to-digital conversion circuit (ADC) 1006, a digital-to-analog conversion circuit (DAC) 1007, a communication interface circuit (communication IF) 1008, and a peripheral circuit 1009. Note that the circuit blocks shown in Fig. 14 are merely an example and are not limited to these.

[0035] For example, the processor 1002 operates in accordance with a program, thereby realizing a predetermined function in the semiconductor device 1000. In order to realize the predetermined function, circuit blocks (e.g., the nonvolatile memory device 1004, the peripheral circuit 1009, etc.) connected to the internal bus 1001 are accessed by the processor 1002 via the internal bus 1001 when the processor 1002 operates.

[0036] <<Configuration of nonvolatile storage device>> 13 is a block diagram showing the configuration of a nonvolatile memory device (hereinafter also simply referred to as a memory device) built into a semiconductor device according to the first embodiment. The nonvolatile memory device 1004 according to the first embodiment is an MRAM. The nonvolatile memory device 1004 according to the first embodiment includes a memory cell array (resistance variable memory cell array) 1100 in which a plurality of memory cells MC11 to MCnm constituting the MRAM are arranged in an array, an address decoder 1101, a word line driver 1102, a plurality of input / output circuits 1103_1 to 1103_k, and a control circuit 1104.

[0037] The memory cell array 1100 includes unit memory cell arrays 1100_1 to 1100_k corresponding to the input / output circuits 1103_1 to 1103_k. The unit memory cell arrays 1100_1 to 1100_k have the same configuration as each other, and therefore, in Fig. 13, memory cells MC11 to MCnm arranged in an array are clearly shown only for the unit memory cell array 1100_1 corresponding to the input / output circuit 1103_1, and memory cells etc. are omitted for the other unit memory cell arrays. In the unit memory cell array 1100_1 as well, a plurality of memory cells are arranged in an array, and therefore the unit memory cell array can also be considered as a memory cell array.

[0038] In the memory cell array 1100, common word lines WL1 to WLn are arranged in each row, and memory cells arranged in the same row are connected to each other. Also, bit lines BL1 to BLm are arranged in each column of the unit memory cell array 1100_1, and memory cells arranged in the same column are connected to each other. Although omitted in FIG. 13, source lines SL for writing (high resistance state) are provided in the columns corresponding to the bit lines BL1 to BLm.

[0039] 14, the address decoder 1101 decodes the row address signal and the column address signal (not shown), and supplies the decoded result Swl to the word line driver 1102. The address decoder 1101 also decodes the column address signal and supplies the decoded result Sbl to the input / output circuits 1103_1 to 1103_k.

[0040] The word line driver 1102 supplies a selection voltage (for example, a high level) to the word line specified by the decoded result Swl, i.e., the word line selected by the row address signal, and supplies a non-selection voltage (for example, a low level) to the other word lines. As a result, multiple memory cells connected to the word line supplied with the selection voltage are selected and electrically connected to the bit lines.

[0041] The input / output circuit 1103_1 includes a column selector CSEL, write circuits IBF&WTD, and read circuits SA&OBF. The column selector CSEL is connected to bit lines BL1 to BLm arranged in the corresponding unit memory cell array 1100_1, selects a bit line indicated by the decoded result Sbl, i.e., a bit line selected by the column address signal, and connects the selected bit line as a common bit line GBL to the write circuits IBF&WTD and the read circuits SA&OBF.

[0042] The write system circuits IBF&WTD, the read system circuits SA&OBF, and the control circuit 1104 are connected to the internal bus 1001 shown in Fig. 14. When a write operation to the memory device 1004 is instructed via the internal bus 1001, for example, from the processor 1002, the control circuit 1104 operates the write system circuits IBF&WTD. As a result, information from the internal bus 1001 is supplied to a bit line selected by a column address signal via the write system circuits IBF&WTD and the common bit line GBL, and is written into a memory cell connected to this bit line.

[0043] Furthermore, when a read operation to the storage device 1004 is instructed, for example, from the processor 1002 via the internal bus 1001, the control circuit 1104 operates the read circuits SA&OBF. The read circuits SA&OBF are composed of a sense amplifier SA and an output buffer circuit OBF. Information on the common bit line GBL is amplified by the sense amplifier SA and output to the internal bus 1001 via the output buffer circuit OBF.

[0044] <<Sense amplifier>> 1A and 1B are diagrams illustrating a sense amplifier according to the first embodiment, in which Fig. 1A is a circuit diagram showing the configuration of the sense amplifier, and Fig. 1B is a waveform diagram showing the operation of the sense amplifier.

[0045] In addition to the sense amplifier SA, FIG. 1A also shows a main part of the control circuit 1104 shown in FIG. 13. Also, FIG. 1A shows an example in which the column selector CSEL is arranged in the sense amplifier SA, but the present invention is not limited to this. That is, as described in FIG. 13, the column selector CSEL may be arranged between the unit memory cell array 1100_1 and the sense amplifier SA. Furthermore, as shown in FIG. 13, the unit memory cell array 1100_1 has a plurality of memory cells MC11 to MCnm arranged in an array, but FIG. 1A depicts one memory cell MC11 among the plurality of memory cells as a representative.

[0046] <<<Memory cell configuration>>> As can be seen from the configuration of memory cell MC11 shown in FIG. 1A, a memory cell is composed of an NMOS transistor NM and a resistive element (MRAM resistive element) RM connected in series between a bit line BL and a wiring SL supplied with a ground voltage Vss. The resistance value of resistive element RM becomes high or low depending on the information to be stored. The gate terminal of NMOS transistor NM is connected to word line WL. When a high level indicating selection is supplied to word line WL, memory cell MC11 is selected, and a resistive element with a resistance value corresponding to the stored information is connected via NMOS transistor NM between the bit line BL and wiring SL supplied with a ground voltage Vss.

[0047] <<<Sense amplifier configuration>>> The sense amplifier SA includes PMOS transistors P1 and P2, NMOS transistors N1 to N8, a noise cancellation circuit NCC, an amplifier SAP, a reference resistor Rref, a current correction circuit TCP, a correction information storage circuit TCP_O, and a column selector CSEL. The sense amplifier SA further includes a cell-side sense line SAC, a reference-side sense line SAR, a cell-side bit line BLC, a reference-side bit line BLR, a first clamp voltage line VL1, a second clamp voltage line VL2, a correction current line TLC, a correction current line TLR, and an initial voltage line VLI.

[0048] The source terminal of PMOS transistor P1 is connected to power supply voltage Vdd, and its drain terminal is connected to cell-side sense line SAC. The source terminal of PMOS transistor P2 is connected to power supply voltage Vdd, and its drain terminal is connected to reference-side sense line SAR. A precharge signal / PC is supplied to the gate terminals of PMOS transistors P1 and P2, and the PMOS transistors P1 and P2 form a precharge circuit PCK. That is, while the precharge signal / PC is low, PMOS transistors P1 and P2 are on, precharging the cell-side sense line SAC and reference-side sense line SAR with power supply voltage Vdd.

[0049] The amplifier SAP has a pair of sense nodes NI1 and NI2, and when the activation signal SAE goes high, it amplifies the potential difference between the pair of sense nodes NI1 and NI2 and outputs it as an output Dout to an output buffer circuit OBF (not shown). Of the pair of sense nodes of the amplifier SAP, one sense node NI1 is connected to the cell-side sense line SAC, and the other sense node NI2 is connected to the reference-side sense line SAR.

[0050] Each of the NMOS transistors N1 to N4 functions as a clamp element, and the NMOS transistors N1 to N4 constitute a clamp circuit CLP. That is, the clamp circuit CLP includes an NMOS transistor N3 having a drain terminal connected to the cell-side sense line SAC and a source terminal connected to the connection node CLC, and an NMOS transistor N4 having a drain terminal connected to the reference-side sense line SAR and a source terminal connected to the connection node CLR. Furthermore, the clamp circuit CLP includes an NMOS transistor N1 having a drain terminal connected to the connection node CLC and a source terminal connected to the cell-side bit line BLC, and an NMOS transistor N2 having a drain terminal connected to the connection node CLR and a source terminal connected to the reference-side bit line.

[0051] In other words, the clamp circuit CLP can be considered to include NMOS transistors N3 and N1 whose source-drain paths are connected in series between the cell-side sense line SAC and the cell-side bit line BLC, and NMOS transistors N4 and N2 whose source-drain paths are connected in series between the reference-side sense line SAR and the reference-side bit line BLR.

[0052] In the clamp circuit CLP, the gate terminals of the NMOS transistors N1 and N2 are commonly connected to a first clamp voltage line VL1, and the gate terminals of the NMOS transistors N3 and N4 are commonly connected to a second clamp voltage line VL2. Therefore, the clamp circuit CLP can be considered to be composed of a first clamp circuit including the NMOS transistors N1 and N2, and a second clamp circuit including the NMOS transistors N3 and N4.

[0053] In the first embodiment, the transconductance Gm of the NMOS transistors N3 and N4 constituting the second clamp circuit is set to be smaller than the transconductance Gm of the NMOS transistors N1 and N2 constituting the first clamp circuit. In order to set the transconductance Gm in this manner, for example, if the channel lengths L of the NMOS transistors N1 to N4 are the same, the channel width W of the NMOS transistors N1 and N2 is set to be longer (larger) than the channel width W of the NMOS transistors N3 and N4. Also, if the channel width W of the NMOS transistors N1 to N4 is the same, the channel length L of the NMOS transistors N1 and N2 is set to be shorter (smaller) than the channel length L of the NMOS transistors N3 and N4. If the ratio (W / L) of the channel width W to the channel length L of the NMOS transistor is defined as the size of the NMOS transistor, the size of the NMOS transistors N3 and N4 is set to be smaller than that of the NMOS transistors N1 and N2.

[0054] The NMOS transistors N5 to N8 configure a selector switch for initializing the cell-side bit line BLC and the reference-side bit line BLR. The drain terminals of the NMOS transistors N5 and N7 are connected to the cell-side bit line BLC, the source terminal of the NMOS transistor N5 is connected to the column selector CSEL, and the source terminal of the NMOS transistor N7 is connected to the initial voltage line VLI. The drain terminals of the NMOS transistors N6 and N8 are connected to the reference-side bit line BLR, the source terminal of the NMOS transistor N6 is connected to the ground voltage Vss via the reference resistor Rref, and the source terminal of the NMOS transistor N8 is connected to the initial voltage line VLI.

[0055] The gate terminal of NMOS transistor N5 and the gate terminal of NMOS transistor N6 are connected in common and a read signal READ is supplied to them. The gate terminal of NMOS transistor N7 and the gate terminal of NMOS transistor N8 are connected in common and a read signal / READ is supplied to them. Since the read signal / READ is an inverted signal (inverted read signal) of the read signal READ, NMOS transistors N5 and N7 are complementarily turned on (off), and NMOS transistors N6 and N8 are also complementarily turned on (off).

[0056] The correction information storage circuit TCP_O pre-stores correction information for correcting, for example, an offset at the input of the amplifier SAP. The correction information stored in the correction information storage circuit TCP_O is supplied to the current correction circuit TCP. While the read signal READ is at a high level, the current correction circuit TCP generates a correction current using the supplied correction information and a bias signal (correction current bias signal) VTRM, and supplies the correction current to the connection nodes CLC and / or CLR via the correction current lines TLC and TLR.

[0057] <<<<Noise cancellation circuit>>>> The noise cancel circuit NCC includes NMOS transistors N11 to N15, a noise cancel side (hereinafter also referred to as the NC side) sense line SANC, and an NC side bit line BLNC.

[0058] The drain terminal of the NMOS transistor N15 is connected to the power supply voltage Vdd, the source terminal is connected to the NC-side sense line SANC, and the gate terminal is supplied with a read signal READ. The drain terminal of the NMOS transistor N12 is connected to the NC-side sense line SANC, and the source terminal is connected to the connection node CLNC. The drain terminal of the NMOS transistor N11 is connected to the connection node CLNC, and the source terminal is connected to the NC-side bit line BLNC. The gate terminal of the NMOS transistor N11, whose source-drain paths are connected in series, is connected to the first clamp voltage line VL1, and the gate terminal of the NMOS transistor N12 is connected to the second clamp voltage line VL2.

[0059] The NMOS transistors N13 and N14, like the NMOS transistors N5 to N8, function as switches when initializing the NC bit line BLNC. The drain terminals of the NMOS transistors N13 and N14 are connected to the NC bit line BLNC, the source terminal of the NMOS transistor N13 is connected to the ground voltage Vss, and the source terminal of the NMOS transistor N14 is connected to the initial voltage line VLI. The gate terminals of the NMOS transistors N13 and N14 are supplied with an inverted read signal / READ and a read signal READ. This causes the NMOS transistors N13 and N14 to be complementarily turned on (off).

[0060] <<Control circuit>> The control circuit 1104 includes multiple circuit blocks, but only the circuit blocks necessary for explanation are shown in Fig. 1A. That is, the control circuit 1104 includes a timing control circuit TCNT, a clamp voltage generation circuit CLPG, and an initialization circuit VBLG.

[0061] The timing control circuit TCNT outputs a precharge signal / PC, an activation signal SAE, a read signal READ, and an inverted read signal / READ in accordance with instructions supplied via the internal bus 1001 (FIG. 14).

[0062] The clamp voltage generation circuit CLPG generates a first clamp voltage VCL1 of a predetermined voltage value and a second clamp voltage VCL2 of a predetermined voltage value and supplies them to the first clamp voltage line VL1 and the second clamp voltage line VL2. When performing correction, the clamp voltage generation circuit CLPG also supplies a bias signal VTRM of a predetermined voltage value to the current correction circuit TCP. As will be explained in detail later, the voltage values ​​of the first clamp voltage VCL1 and the second clamp voltage VCL2 are lower than the power supply voltage Vdd, and further, the voltage value of the first clamp voltage VCL1 is lower than the second clamp voltage VCL2.

[0063] Furthermore, during the standby period, the initialization circuit VBLG generates an initialization voltage VINI of a predetermined voltage value and supplies it to the initialization voltage line VLI. As will be explained in detail later, the voltage value of the initialization voltage VINI is lower than the power supply voltage Vdd.

[0064] In the following description, the PMOS transistors P1 and P2 may be referred to as the first and second PMOS transistors. Similarly, the NMOS transistors N1 to N8 and N11 to N15 may be referred to as the first to eighth NMOS transistors and the eleventh to fifteenth NMOS transistors.

[0065] <<Outline of operation of nonvolatile memory devices>> The read operation of the nonvolatile memory device including the sense amplifier SA shown in FIG. 1 will be outlined below using the waveform diagram shown in FIG.

[0066] During the standby period SBH before the time t0 at which the read operation starts, the read signal READ is at a low level. This turns off the NMOS transistors N5 and N6, turns on the NMOS transistors N7 and N8, and supplies the initialization voltage VINI, which is lower than the power supply voltage Vdd, to the cell-side bit line BLC and the reference-side bit line BLR. As a result, during the standby period SBH, the cell-side bit line BLC, the reference-side bit line BLR, and the connection nodes CLC and CLR are at a voltage lower than the power supply voltage Vdd.

[0067] During the standby period SBH and the precharge period PTH from time t0 to time t1, the precharge signal / PC goes low, turning on the PMOS transistors P1 and P2 of the precharge circuit PCK, and the cell-side sense line SAC, the reference-side sense line SAR, and the pair of sense nodes NI1 and NI2 of the amplifier unit SAP are precharged to the power supply voltage Vdd.

[0068] During the precharge period PTH, the read signal READ changes to a high level, turning on the NMOS transistors N5 and N6. As a result, the memory cell is connected to the cell-side bit line BLC via the column selector CSEL, and the reference-side bit line BLR is connected to the reference resistor Rref. During the precharge period PTH, the voltages of the cell-side bit line BLC, the reference-side bit line BLR, and the connection nodes CLC and CLR are clamped by the first clamp voltage VCL1 and the second clamp voltage VCL2, and are lower than the power supply voltage Vdd, as shown in Figure 1(B).

[0069] At time t1, the precharge signal / PC goes high, turning off the PMOS transistors P1 and P2. This ends the precharge of the cell-side sense line SAC and the reference-side sense line SAR, and the discharge period DTH begins. During the discharge period DTH from time t1 to time t2, the voltage of the cell-side sense line SAC decreases in accordance with the cell current flowing through the selected memory cell, and the voltage of the reference-side sense line SAR decreases in accordance with the reference current flowing through the reference resistor. This generates a potential difference between the pair of sense nodes NI1 and NI2 in the amplifier unit SAP.

[0070] At time t2, the activation signal SAE goes high, causing the amplifier SAP to amplify the potential difference between the pair of sense nodes NI1 and NI2 and output it as the output Dout.

[0071] In the noise cancellation circuit NCC, the NMOS transistor N13 is turned on during the standby period SBH, and when the circuit transitions to the precharge period PTH, the NMOS transistor N14 is turned on. As a result, when the circuit transitions from the standby period SBH to the precharge period PTH, the voltages of the NC bit line BLNC and the connection node CLNC rise from the ground voltage Vss to a voltage determined by the first clamp voltage VCL1 and the second clamp voltage VCL2, as shown in FIG. 1B. That is, when the circuit transitions from the standby period SBH to the precharge period PTH, as shown in FIG. 1B, the direction of change in the voltages of the NC bit line BLNC and the connection node CLNC is opposite to the direction of change in the voltages of the cell-side bit line BLC, the reference-side bit line BLR, and the connection nodes CLC and CLR. This allows voltage changes of opposite phases to be applied to the first clamp voltage line VL1 and the second clamp voltage line VL2 via the gate capacitances of the NMOS transistors N11 and N12, for example, thereby canceling noise.

[0072] Next, the characteristic parts of the configuration according to the first embodiment shown in FIG. 1(A) will be described in more detail with reference to the drawings.

[0073] <<Clamp circuit and clamp voltage generation circuit>> Fig. 2 is a circuit diagram showing the configuration of a clamp circuit and a clamp voltage generating circuit according to embodiment 1. Fig. 2 is similar to Fig. 1(A). The main difference is that Fig. 2 shows only the parts related to the clamp circuit CLP in the circuit diagram shown in Fig. 1(A).

[0074] In Figure 1(A), it has been described that the clamp voltage generation circuit CLPG generates voltages lower than the power supply voltage Vdd as the first clamp voltage VL1 and the second clamp voltage VL2. However, as a more specific example, Figure 2 describes a case where the first clamp voltage VL1 and the second clamp voltage VL2 having the following voltage values ​​are generated.

[0075] That is, the clamp voltage generation circuit CLPG generates, as the first clamp voltage VCL1, a voltage obtained by adding the threshold voltage Vthn of the NMOS transistors N1 and N2, which serve as clamp elements, to the voltages set for the cell-side bit line BLC and the reference-side bit line BLR. Here, the voltages set for the cell-side bit line BLC and the reference-side bit line BLR are the voltage Vbl (e.g., approximately 0.1 V) applied to the selected memory cell (e.g., MC11). As a result, the clamp voltage generation circuit CLPG generates the first clamp voltage VCL1, which has a voltage value (=Vbl+Vthn) obtained by adding the threshold voltage Vthn to the voltage Vbl. Furthermore, the clamp voltage generation circuit CLPG generates, as the second clamp voltage VCL2, a voltage value (=Vcnd+Vth) obtained by adding the threshold voltage Vthn of the NMOS transistors N3 and N4, which serve as clamp elements, to the voltage Vcnd set for the connection nodes CLC and CLR. The voltage Vcnd is higher than the voltage Vbl by the DC saturation margin of the NMOS transistors N1 and N2, and is, for example, about 0.3V.

[0076] 1B, that is, when the cell-side bit line BLC and the reference-side bit line BLR are connected to the memory cell MC11 and the reference resistor Rref via the NMOS transistors N5 and N6, the voltages of the cell-side bit line BLC and the reference-side bit line BLR are limited (clamped) to a voltage Vbl (approximately 0.1 V), and the voltages of the connection nodes CLC and CLR are limited (clamped) to a voltage Vcnd (approximately 0.3 V). For ease of explanation, the case where the threshold voltages of the NMOS transistors N1 and N2 and the NMOS transistors N3 and N4 are the same threshold voltage Vthn is taken as an example, but the present invention is not limited to this.

[0077] The clamp circuit CLP is configured with two pairs of cascode-connected NMOS transistors (N1 and N3, and N2 and N4). As described in FIG. 1A, the NMOS transistors N3 and N4 have a smaller channel width W than the NMOS transistors N1 and N2, and their mutual conductance Gm is set smaller than that of the NMOS transistors N1 and N2.

[0078] Since the mutual conductance Gm of the NMOS transistors N1 and N2 is set large, it is possible to improve the clamping accuracy when controlling the voltages of the cell-side bit line BLC and the reference-side bit line BLR, to which the source terminals of the NMOS transistors N1 and N2 are connected, to the voltage Vbl. Furthermore, by increasing the mutual conductance Gm, it is possible to improve the read margin, as will be understood from the explanation of FIG.

[0079] On the other hand, the NMOS transistors N3 and N4 connected to the pair of sense nodes via the cell-side sense line SAC and the reference-side sense line SAR have a channel width W shorter than that of the NMOS transistors N1 and N2 (for example, 1 / 4 of the channel width W of the NMOS transistors N1 and N2). Therefore, it is possible to reduce the parasitic capacitance connected to the pair of sense nodes (for example, the drain capacitance of the NMOS transistors N3 and N4) to, for example, 1 / 4. This makes it possible to shorten the discharge period DTH and the sense period STH shown in FIG. 1B, thereby enabling faster read operations.

[0080] Note that because the mutual conductance Gm of the NMOS transistors N3 and N4 is reduced, the clamping accuracy when limiting the connection nodes CLC and CLR to the voltage Vcnd is reduced. However, the voltage fluctuations at the connection nodes CLC and CLR due to the reduced clamping accuracy occur when the NMOS transistors N1 and N2 are operating in the saturation region, so this does not result in a deterioration in the read margin. Rather, the cascode connection improves the channel length modulation coefficient λ, making it possible to reduce current fluctuations when the voltages of the cell-side sense line SAC and the reference-side sense line SAR fluctuate.

[0081] Furthermore, since two NMOS transistors N1 and N3 are connected to the connection node CLC and two NMOS transistors N2 and N4 are connected to the connection node CLR, the parasitic capacitances connected to the connection nodes CLC and CLR increase. However, since the voltages of the connection nodes CLC and CLR are limited to the voltage Vcnd by the NMOS transistors N3 and N4, the discharge time related to the connection nodes CLC and CLR does not increase.

[0082] <<<Example of a clamp voltage generation circuit>>> 3 is a circuit diagram showing the configuration of a clamp circuit and a clamp voltage generation circuit according to the first embodiment. FIG. 3 is similar to FIG. 2. The main difference is that FIG. 3 shows a detailed example of the configuration of the clamp voltage generation circuit CLPG. In FIG. 3, the configuration of the sense amplifier SA is the same as in FIG. 2, so a description of the sense amplifier SA will be omitted.

[0083] The clamp voltage generating circuit CLPG includes PMOS transistors P3 and P4, NMOS transistors N16 to N18, a reference resistor Rref_CL, a resistive element Rclamp2, a current source Iclamp2, and a reference current source Iref_CL.

[0084] The source terminals of the PMOS transistors P3 and P4 are connected to the power supply voltage Vdd, and the drain terminal of the PMOS transistor P3 is connected to the gate terminals of the PMOS transistors P3 and P4. The drain terminal of the PMOS transistor P3 is also connected to the ground voltage Vss via the reference current source Iref_CL. This allows the PMOS transistors P3 and P4 to form a current mirror circuit, and a reference current corresponding to the reference current Iref_CL is output from the drain terminal of the PMOS transistor P4.

[0085] The drain terminal of the PMOS transistor P4 is connected to the drain terminal of the NMOS transistor N18, and the source terminal of the NMOS transistor N18 is connected to the drain terminal of the NMOS transistor N16, whose source terminal is connected to the ground voltage Vss via a reference resistor Ref_CL. The gate terminal of the NMOS transistor N16 is connected to the drain terminal of the PMOS transistor P4. The NMOS transistor N16 is a replica element that simulates the NMOS transistors N1 and N2, which are clamp elements. The NMOS transistor N18 is a replica element that simulates the NMOS transistors N3 and N4, which are clamp elements. Therefore, the NMOS transistor N16 is set to have characteristics similar to, for example, the NMOS transistor N1, and the NMOS transistor N18 is set to have characteristics similar to, for example, the NMOS transistor N3.

[0086] Furthermore, the reference resistor Ref_CL is a replica element that simulates the reference resistor Rref, and is therefore set to have the same characteristics as the reference resistor Rref.

[0087] The reference current output from the drain terminal of the PMOS transistor P4 is supplied to a series circuit formed by the NMOS transistors N18 and N16 and the reference resistor Rref_CL. As a result, a voltage equivalent to the voltage Vbl (approximately 0.1 V) applied to the memory cell is generated at the source terminal of the NMOS transistor N16. Since the first clamp voltage line VL1 is connected to the gate terminal of the NMOS transistor N16, the value of the first clamp voltage VCL1 supplied from the clamp voltage generating circuit CLPG to the first clamp voltage line VL1 is a voltage (=Vbl+Vthn) obtained by adding the voltage Vbl (approximately 0.1 V) at the source terminal of the NMOS transistor N16 to the threshold voltage Vthn of the NMOS transistor.

[0088] The gate terminal of NMOS transistor N17 is connected to the drain terminal of NMOS transistor N17 and the gate terminal of NMOS transistor N18, and the drain terminal of NMOS transistor N17 is connected to power supply voltage Vdd via current source Iclamp2. The source terminal of NMOS transistor N17 is connected to ground voltage Vss via resistor Rclamp2. NMOS transistor N17 is a replica element that simulates NMOS transistors N3 and N4, which are clamp elements. Therefore, NMOS transistor N17 is set to have characteristics similar to those of NMOS transistor N3, for example.

[0089] The current source Iclamp2 and the resistor Rclam2 are set so that the voltage generated in the resistor Rclamp2 by the current supplied to the resistor Rclamp2 from the current source Iclamp2 via the NMOS transistor N17 is equal to the voltage Vcnd at the connection nodes CLC and CLR. As a result, the voltage at the source terminal of the NMOS transistor N17 becomes equal to the voltage Vcnd (approximately 0.3 V). Because the second clamp voltage line VL2 is connected to the gate terminal of the NMOS transistor N17, the second clamp voltage VCL2 becomes a value obtained by adding the threshold voltage Vthn of the NMOS transistor N17 to a voltage value equal to the voltage Vcnd (approximately 0.3 V) (= Vcnd + Vthn).

[0090] As explained in FIG. 1A, the parasitic capacitance connected to the cell-side sense line SAC and the reference-side sense line SAR can be reduced, making it possible to achieve both stable operation and high speed.

[0091] 2 generates the first clamp voltage VCL1 and the second clamp voltage VCL2 using replica elements of the NMOS transistors N1 to N4, which are clamp elements, and a replica element of the reference resistor Rref. Therefore, even if the characteristics of the NMOS transistors N1 to N4 and the reference resistor Rref vary, for example, during manufacturing, the clamp voltage generation circuit CLPG can generate the first clamp voltage VCL1 and the second clamp voltage VCL2 in accordance with this variation, thereby further improving operational stability.

[0092] <<Current compensation circuit>> Fig. 4 is a circuit diagram showing the configuration of the current correction circuit according to the first embodiment. Fig. 4 is similar to Fig. 2. The main difference is that Fig. 4 adds a portion related to the current correction circuit to Fig. 2.

[0093] An input offset may occur in the amplifier section SAP due to variations in characteristics between the clamp elements that make up the clamp circuit CLP, for example, variations in characteristics between the NMOS transistors N1 and N2, and / or variations in characteristics between the elements (for example, MOS transistors) that make up the amplifier section SAP.

[0094] For example, if an input offset occurs due to a characteristic variation between the NMOS transistors N1 and N2, a potential difference occurs between the pair of sense nodes N11 and N12 even if the cell resistance and the reference resistance are the same value. Also, if an input offset occurs due to an element constituting the amplifier unit SAP, even if there is no potential difference between the pair of sense nodes NI1 and NI2, the amplifier unit SAP will output an undesired output Dout, thereby reducing the read margin during read operations of memory cells with high resistance and / or low resistance.

[0095] In the first embodiment, a current correction circuit TCP is provided in the sense amplifier SA. Although not particularly limited, the sense amplifier SA is further provided with a correction information storage circuit TCP_O. Correction information is stored in advance in the correction information storage circuit TCP_O. The correction information is supplied from the correction information storage circuit TCP_O to the current correction circuit TCP. The current correction circuit TCP generates a minute correction current based on the supplied correction information and a bias signal VTRM supplied from the clamp voltage generation circuit CLPG, and supplies the generated correction current to the connection node CLC and / or the connection node CLR via the correction current lines TLC and TLR.

[0096] By supplying a correction current to the connection node CLC and / or the connection node CLR, the cell current flowing through the cell side sense line SAC and / or the reference current flowing through the reference side sense line SAR is corrected during a read operation, making it possible to reduce the input offset and improve the read margin.

[0097] Connecting the correction current lines TLC and TLR to the connection nodes CLC and CLR increases the parasitic capacitance connected to the connection nodes CLC and CLR. However, the voltages of the connection nodes CLC and CLR are clamped to the voltage Vcnd (approximately 0.3 V) by the NMOS transistors N3 and N4, which act as clamp elements, so the discharge time required to discharge the connection nodes CLC and CLR does not increase.

[0098] The input offset can also be reduced by connecting the correction current lines TLC and TLR to, for example, the cell-side sense line SAC and the reference-side sense line SAR and supplying a correction current to the sense lines SAC and SAR. However, in this case, the parasitic capacitance generated by the correction current lines TLC and TLR is connected to the sense lines SAC and SAR, and the parasitic capacitance connected to the pair of sense nodes increases, which increases the discharge time of the sense lines SAC and SAR and limits the speed of the read operation.

[0099] In addition, the input offset can also be reduced by connecting the correction current lines TLC and TLR to, for example, the cell-side bit line BLC and the reference-side bit line BLR and supplying a correction current to the bit lines BLC and BLR. However, in this case, the current correction circuit TCP is required to generate a correction current at the very low voltage Vbl (approximately 0.1 V) applied to the memory cell, which makes it difficult to configure the current correction circuit TCP.

[0100] Therefore, as shown in FIG. 4, it is desirable that the correction current lines TLC and TLR to which the correction current is supplied are connected to the connection nodes CLC and CLR.

[0101] <<<Example of a current compensation circuit>>> 5 and 6 are diagrams for explaining the current correction circuit according to the first embodiment. Here, Fig. 5 shows the configuration of a clamp voltage generation circuit that generates a bias signal to be supplied to the current correction circuit. Also, Fig. 6 is a circuit diagram showing one configuration of the current correction circuit shown in Fig. 5.

[0102] FIG. 5 is similar to FIG. 4. The main difference is that FIG. 5 shows a detailed configuration of the clamp voltage generation circuit CLPG. The clamp voltage generation circuit CLPG shown in FIG. 5 is similar to the clamp voltage generation circuit shown in FIG. 3. The main difference is that FIG. 5 shows a configuration for generating a bias signal supplied to the current correction circuit.

[0103] In order to generate the bias signal VTRM supplied to the current correction circuit TCP, the clamp voltage generation circuit CLPG shown in FIG. 5 additionally includes a PMOS transistor P5 and NMOS transistors N19 and N20 in comparison with the clamp voltage generation circuit CLPG shown in FIG. 3.

[0104] The source terminal of the PMOS transistor P5 is connected to the power supply voltage Vdd, and the gate terminal is connected to the gate terminal of the PMOS transistor P3. The drain terminal of the PMOS transistor P5 is connected to the drain terminal of the NMOS transistor N20, and the source terminal of the NMOS transistor N20 is connected to the drain terminal of the NMOS transistor N19, and the source terminal of the NMOS transistor N19 is connected to the ground voltage Vss. The gate terminal of the NMOS transistor N19 is connected to the drain terminal of the PMOS transistor P5, and the gate terminal of the NMOS transistor N20 is connected to the gate terminal of the NMOS transistor N17. The bias signal VTRM is taken out from the gate terminal of the NMOS transistor N19 (the drain terminal of the PMOS transistor P5).

[0105] The NMOS transistor N20, like the NMOS transistors N17 and N18, is a replica element that simulates the NMOS transistors N3 and N4, which are clamp elements.

[0106] A current mirror circuit is formed by the PMOS transistors P3 to P5, and a current mirror current corresponding to the reference current Iref_CL is supplied from the PMOS transistor P5 to the series-connected NMOS transistors N20 and N19, causing the bias signal VTRM to be output from the gate terminal of the NMOS transistor N19.

[0107] The current correction circuit TCP shown in FIG. 6 includes NMOS transistors N21 to N25 and N31 to N37.

[0108] The source terminals of the NMOS transistors N21 to N25 are connected to the ground voltage Vss, and the gate terminals are connected to the gate terminal of the NMOS transistor N19 shown in Fig. 5 so as to receive the bias signal VTRM. As a result, a current mirror circuit is formed by the NMOS transistors N19 and N21 to N25, and the NMOS transistors N21 to N25 function as a current source.

[0109] In the first embodiment, the size of the NMOS transistor N21 is set as a reference (x1), and the sizes of the NMOS transistors N22 to N25 are set to be twice (x2), four times (x4), eight times (x8), and sixteen times (x16) the reference (x1) size. Also, the size of the NMOS transistor N19 shown in FIG. 5 is set to be N times (xN) the reference (x1).

[0110] The drain terminals of the NMOS transistors N21 to N25 are connected to the source terminals of the NMOS transistors N31 to N35, and the drain terminals of the NMOS transistors N31 to N35 are connected to the source terminals of the NMOS transistors N36 and N37. The drain terminal of the NMOS transistor N36 is connected to the connection node CLC via the correction current line TLC, and the drain terminal of the NMOS transistor N37 is connected to the connection node CLR via the correction current line TLR.

[0111] The gate terminals of the NMOS transistors N31 to N35 and the gate terminals of the NMOS transistors N36 and N37 are connected to the correction information storage circuit TCP_O. The correction information stored in the correction information storage circuit TCP_O is supplied to the gate terminals of the NMOS transistors N31 to N35 and N36 and N37 as switching signals CHS1 to CHS5 and selection signals SLS1 and SLS2. The NMOS transistors N31 to N35 and N36 and N37 have the same size, and the NMOS transistors N31 to N35 function as switches that are turned on when the switching signals CHS1 to CHS5 are set to high level, and the NMOS transistors N36 and N37 function as switches that are turned on when the selection signals SLS1 and SLS2 are set to high level.

[0112] By combining the high levels of the switching signals CHS1 to CHS5, 32 different settings can be made, making it possible to adjust the size from 0 to 31 times. For example, if the size N of the NMOS transistor N19 is 256 (N=256), by combining the high levels of the switching signals CHS1 to CHS5, it is possible to generate minute correction currents of 0, 1 / 256 × reference current Iref_CL (FIG. 5) to 31 / 256 × reference current Iref_CL. The generated correction current can be supplied to, for example, the connection node CLC or CLR by the selection signals SLS1 and SLS2, for correction.

[0113] If the input offset reduces the read margin when the memory cell has a low resistance, the select signal SLS1 is set to high level, causing a small correction current to be applied to the connection node CLC. This makes it possible to increase the cell current Icell during a read operation. On the other hand, if the input offset reduces the read margin when the memory cell has a high resistance, the select signal SLS2 is set to high level, causing a small correction current to be applied to the connection node CLR. This makes it possible to increase the reference current Iref generated in the reference resistor Rref (Figure 5) during a read operation. By supplying a small correction current to the connection node, the read margin when the memory cell has a high resistance and the read margin when the memory cell has a low resistance are equalized, making it possible to improve the read margin.

[0114] In the clamp voltage generation circuit CLPG shown in FIG. 5 and the current correction circuit TCP shown in FIG. 6, a current mirror is formed by the NMOS transistors N19, N20 and N21 to N25, N3, and N4. Even if the characteristics of the NMOS transistors fluctuate during manufacturing, for example, it is possible to generate a correction current that matches the fluctuations, thereby improving the stability of operation.

[0115] <<Initialization circuit>> 7 is a diagram illustrating an initialization circuit according to the first embodiment. FIG. 7 is similar to FIG. 4. The difference is that FIG. 7 adds a portion related to the initialization circuit to FIG. 4. That is, FIG. 7 illustrates, as the portion related to the initialization circuit, an initialization circuit VBLG, an initial voltage line VLI to which an initialization voltage VINI generated by the initialization circuit VBLG is supplied, and NMOS transistors N7 and N8.

[0116] 8 is a waveform diagram for explaining the initialization circuit according to the first embodiment. FIG. 8 is similar to FIG. 1(B). The difference is that the waveforms of the NC side sense line and the NC side bit line are omitted in FIG. 8. Here, FIG. 8(A) shows the operation of the circuit shown in FIG. 4, for example, and FIG. 8(B) shows the operation of the circuit shown in FIG. 7.

[0117] The initialization circuit VBLG generates an initialization voltage VINI and supplies it to an initialization voltage line VLI. The initialization voltage VINI is lower than the power supply voltage Vdd, and is, for example, about a voltage Vbl (about 0.1V)+0.2V.

[0118] As shown in FIG. 7, the NMOS transistor N7 is connected between the initial voltage line VLI and the cell-side bit line BLC, and the NMOS transistor N8 is connected between the initial voltage line VLI and the reference-side bit line BLR. An inverted read signal / READ is supplied to the gate terminals of the NMOS transistors N7 and N8. Therefore, during the standby period SBH (FIGS. 8A and 8B) when the read signal READ is at a low level, the NMOS transistors N7 and N8 are turned on. As a result, during the standby period SBH, the voltages of the cell-side bit line BLC and the reference-side bit line BLR are set to a voltage value determined by the initialization voltage VINI.

[0119] During the standby period SBH, the read signal READ is at a low level, turning off the NMOS transistors N5 and N6. Therefore, if the initialization voltage VINI is not supplied via the NMOS transistors N7 and N8, the cell-side bit line BLC and the reference-side bit line BLR are in a floating state and rise toward, for example, the power supply voltage Vdd, as shown in FIG. 8A. Thereafter, at time t0 when the read operation starts, the voltages of the cell-side bit line BLC and the reference-side bit line BLR change from the power supply voltage Vdd to a voltage Vbl determined by the first clamp voltage VCL1. That is, when the standby period is switched to the read operation, the voltage change in the cell-side bit line BLC and the reference-side bit line BLR increases. This change in the voltage in the bit line is transmitted to the first clamp voltage line VL1 via, for example, the gate capacitance (capacitance between the source terminal and gate terminal) of the NMOS transistors N1 and N2, resulting in, for example, noise.

[0120] 7, in contrast, an initialization voltage VINI (voltage Vbl (approximately 0.1 V) + 0.2 V) lower than the power supply voltage Vdd is supplied to the cell-side bit line BLC and the reference-side bit line BLR during the standby period SBH, so that, as shown in FIG. 8(B), when the standby period is shifted to the read operation, it is possible to reduce the amount of change in voltage on the cell-side bit line BLC and the reference-side bit line BLR (to approximately 0.2 V). As a result, it is possible to reduce noise transmitted to the first clamp voltage line VL1 via the gate capacitance.

[0121] In the configuration of FIG. 7, in which an initialization voltage VINI (voltage Vbl (approximately 0.1 V) + 0.2 V) lower than the power supply voltage Vdd is supplied to the cell-side bit line BLC and the reference-side bit line BLR during the standby period SBH, the voltages of the connection nodes CLC and CLR transition from approximately 0.5 V (standby period SBH) to approximately 0.3 V (period of read operation), as shown in FIG. 8(B). In other words, the amount of voltage change at the connection nodes CLC and CLR can also be reduced, enabling noise reduction.

[0122] By reducing noise, it is possible to shorten the time required to wait for noise to converge, and therefore, for example, it is possible to shorten the precharge period PTH from time t0 to t1 to achieve faster speeds.Alternatively, it is possible to reduce fluctuations in the first clamp voltage VCL1 and the second clamp voltage VCL2 due to noise, and therefore it is possible to suppress fluctuations in the cell current after time t1 and improve the read margin.

[0123] <<<Configuration example of initialization circuit>>> Fig. 9 is a circuit diagram showing an example of an initialization circuit according to embodiment 1. Fig. 9 is similar to Fig. 7. The difference is that Fig. 9 explicitly shows the configuration of the initialization circuit VBLG.

[0124] The initialization circuit VBLG includes a current source I_VB and NMOS transistors N41 and N42. The source terminal of the NMOS transistor N42 is connected to the ground voltage Vss, and the drain terminal is connected to the power supply voltage Vdd via the current source I_VB. The source terminal of the NMOS transistor N41 is connected to the ground voltage Vss, and the drain terminal is connected to the initial voltage line VLI. Furthermore, the gate terminals of the NMOS transistors N41 and N42 are connected to the drain terminal of the NMOS transistor N42. As a result, the NMOS transistors N41 and N42 form a current mirror circuit.

[0125] In the first embodiment, the initialization circuit VBLG is shared by a plurality of sense amplifiers. In the example shown in Fig. 13, one initialization circuit VBLG is provided for k input / output circuits 1103_1 to 1103_k.

[0126] When the NMOS transistors N7 and N8 are turned on, a current flows from the power supply voltage Vdd to the initial voltage line VLI via the PMOS transistors P1 and P2, the NMOS transistors N3 and N4, the NMOS transistors N1 and N2, and the NMOS transistors N7 and N8, and further the current flows to the ground voltage Vss via the NMOS transistor N41.

[0127] The NMOS transistor N41 functions as a current source that supplies, for example, 4 μA of current. Therefore, assuming that one initialization circuit VBLG is shared by 256 sense amplifiers, a current of 7 nA is allocated to each NMOS transistor that functions as a clamp element. The first clamp voltage VCL1 is applied to the NMOS transistors N1 and N2 even during the standby period SBH before time t0. By passing a current of 7 nA, an initialization voltage VINI of approximately 0.3 V is automatically generated on the initialization voltage line VLI to which the source terminals of the NMOS transistors N1 and N2 are connected.

[0128] In this way, the initialization circuit VBLG can be realized by adding a current source and an NMOS transistor without adding any complex circuitry, and can be shared by multiple sense amplifiers, thereby suppressing increases in the occupied area and power consumption.

[0129] <<Noise cancellation circuit>> Next, the noise cancellation circuit NCC shown in FIG. 1 will be described with reference to FIGS. 7 and 8. As shown in FIG. 1A, the noise cancellation circuit NCC includes NMOS transistors N11 to N15. Here, the NMOS transistors N11 and N12 are replica elements that simulate the NMOS transistors N1, N2, N3, and N4, which are clamp elements. Therefore, the NMOS transistors N11 and N12 are set to have similar characteristics to, for example, the NMOS transistors N1 and N3.

[0130] As explained in FIGS. 7 and 8, at time t0 when the standby period SBH transitions to the read operation, the voltages of the cell-side bit line BLC and the reference-side bit line BLR transition from approximately 0.3 V (= voltage Vbl (approximately 0.1 V) + approximately 0.2 V) to approximately 0.1 V (= voltage Vbl). Also, at time t0, the voltages of the connection nodes CLC and CLR transition from approximately 0.5 V to approximately 0.3 V. The voltage transitions at the cell-side bit line BLC and the reference-side bit line BLR propagate to the first clamp voltage line VL1 via the gate capacitances of the NMOS transistors N1 and N2, and the voltage transitions at the connection nodes CLC and CLR propagate to the second clamp voltage line VL2 via the NMOS transistors N3 and N4.

[0131] Since the voltage transition at time t0 is a negative change from a high voltage value to a low voltage value, as shown in FIG. 8, the voltage transition acts as an application of negative noise to the first clamp voltage VCL1 and the second clamp voltage VCL2.

[0132] On the other hand, in the noise cancellation circuit NCC, at time t0 when the standby period SBH transitions to the read operation, the NMOS transistor N13 switches to the OFF state, and the NMOS transistors N14 and N15 switch to the ON state. As a result, the voltages of the NC bit line BLNC and the connection node CLNC rise from the ground voltage Vss to a voltage determined by the initialization voltage VINI. That is, the voltage of the connection node CLNC transitions from the ground voltage Vss to approximately 0.5 V, and the voltage of the NC bit line BLNC transitions from the ground voltage Vss to approximately 0.3 V.

[0133] The voltage transition at the non-conductive bit line BLNC is transmitted to the first clamp voltage line VL1 via the gate capacitance of the NMOS transistor N11, and the voltage transition at the connection node CLNC is transmitted to the second clamp voltage line VL1 via the gate capacitance of the NMOS transistor N12. Since the transition at time t0 is a positive change from a low voltage value to a high voltage value as shown in FIG. 8, the voltage transition acts as the application of positive noise to the first clamp voltage VCL1 and the second clamp voltage VCL2.

[0134] Since both negative noise and positive noise are applied to the first clamp voltage line VL1 and the second clamp voltage line VL2, the noises can be canceled out.

[0135] Since the noise is reduced by cancellation, it is possible to shorten the time to wait for the noise to converge, and therefore it is possible to increase the speed by shortening the precharge period PTH from time t0 to t1, for example.Alternatively, it is possible to reduce fluctuations in the first clamp voltage VCL1 and the second clamp voltage VCL2 due to noise, which makes it possible to suppress fluctuations in the cell current after time t1 and improve the read margin.

[0136] Furthermore, since the NMOS transistors N11 and N12 are replica elements of the NMOS transistors N1 to N4, if the gate capacitance of the NMOS transistors N1 to N4 changes due to manufacturing variations, for example, the gate capacitance of the NMOS transistors N11 and N12 also changes similarly, making it possible to prevent the amount of noise to be cancelled from decreasing due to manufacturing variations.

[0137] The NMOS transistors N5 to N8 and N13 and N14 can be considered to constitute a selection circuit, which changes what is connected to the cell-side bit line BLC, reference-side bit line BLR, and NC-side bit line BLNC during standby and read operations.

[0138] According to the first embodiment, it is possible to provide a semiconductor device including an MRAM that can achieve both high-speed operation and stable operation at high temperatures. This makes it possible to broaden the range of application of the semiconductor device and increase its commercial value. For example, endpoint devices in network communications with the cloud often require high-speed data processing in harsh surrounding environments. The semiconductor device including the MRAM according to the first embodiment can be used for such endpoint devices as well.

[0139] (Embodiment 2) In the second embodiment, a preferred example of a reference resistor Rref used in a sense amplifier SA (e.g., FIG. 1A) is shown. The reference resistor Rref is set to have an intermediate resistance value between the resistance value when a memory cell (e.g., MC11) has a high resistance and the resistance value when a memory cell (e.g., MC11) has a low resistance. To enable such a setting, the reference resistor Rref has an adjustment function unit that adjusts the resistance value.

[0140] The present inventors have studied a reference resistor having such an adjustment function unit. First, the study by the present inventors will be described using a comparative example.

[0141] <Reference resistor comparison example> Fig. 17 is a circuit diagram showing a comparative example of a reference resistor studied by the present inventors. As shown in Fig. 17, the reference resistor Rref of the comparative example is composed of a resistance fixing unit Rref_fx and five resistance adjusting units Rref_ad1 to Ref_ad5 connected in series between terminal nodes RT1 and RT2 of the reference resistor Rref. The five resistance adjusting units implement an adjusting function unit.

[0142] The resistance value fixing unit Rref_fx and the resistance value adjusting units Rref_ad1 to Ref_ad5 are basically configured with polysilicon resistors (hereinafter also referred to as polysilicon resistors) having substantially the same characteristics as the resistive element RM (FIG. 1(A)) that configures the memory cell (MC11). The sheet resistance of the polysilicon resistor is relatively large, at approximately 1 kΩ. Each of the resistance value adjusting units Rref_ad1 to Ref_ad5 is configured with a resistor configured using a basic resistor R and a short-circuit switch. In the following, a case will be described in which the basic resistor R is configured with a 1 kΩ polysilicon resistor.

[0143] In the resistance value adjustment unit Rref_ad1, the resistor R11 is composed of eight basic resistors R connected in parallel. This results in the resistor R11 having a resistance value of approximately 125 Ω. To achieve the adjustment function with a resolution of 125 Ω, the resistor R11 and an NMOS transistor N51 are connected in parallel. The NMOS transistor N51 forms a short-circuit switch, and the short-circuit switch is turned on / off by a switching signal 11 supplied to the gate terminal of the NMOS transistor N51. As a result, the switching signal 11 determines whether to add or not add a resistance value with a resolution of 125 Ω to the reference resistor Rref.

[0144] Similarly, in the resistance value adjustment unit Rref_ad2, a resistor R12 is formed by four basic resistors R connected in parallel, and an NMOS transistor N52 constituting a short-circuit switch is connected in parallel to the resistor R12. Similarly, in the resistance value adjustment unit Rref_ad3, a resistor R13 is formed by two basic resistors R connected in parallel, and the resistor R13 and an NMOS transistor N53 constituting a short-circuit switch are connected in parallel. Furthermore, in the resistance value adjustment unit Rref_ad4, a resistor R14 is formed by one basic resistor R, and the resistor R14 and an NMOS transistor N54 constituting a short-circuit switch are connected in parallel. Furthermore, in the resistance value adjustment unit Rref_ad5, a resistor R15 is formed by two basic resistors R connected in series, and the resistor R15 and an NMOS transistor N55 constituting a short-circuit switch are connected in parallel.

[0145] By connecting these resistance adjusting units Rref_ad1 to Rref_ad5 in series with a resistance fixing unit Rref_fx having a resistor R16 with a base resistance value, a reference resistor Rref with a resistance resolution of 125 Ω can be realized. In this case, by combining high and low levels in the switching signals 11 to 15, a reference resistor Rref with an adjustable resistance value in the range of +0 Ω to +3.875 kΩ relative to the base resistance value can be realized.

[0146] When the NMOS transistors N51 to N55 are in the on state, an on-resistance occurs. This on-resistance causes an error in the resistance value of the reference resistor Rref. If an attempt is made to suppress the error in the reference resistor Rref caused by the error in the NMOS transistors N51 to N55 to, for example, 10%, the on-resistances of the NMOS transistors N51 to N55 must be set to 12.5Ω, 25Ω, 50Ω, 100Ω, and 200Ω, which are 10% of the resistance value of the resistors R11 to R15.

[0147] For example, to achieve an on-resistance of less than 100 Ω, it is necessary to increase the size of the NMOS transistors N51 to N53, and in particular, to achieve an on-resistance of 12.5 Ω, the size of the NMOS transistor N51 must be increased. In other words, there is a problem that the area occupied by the NMOS transistors that configure the short-circuit switch increases.

[0148] <Reference resistor configuration> FIG. 10 is a circuit diagram showing the configuration of a reference resistor according to the second embodiment. In FIG. 10, Rref represents a reference resistor. Similar to the configuration of the comparative example shown in FIG. 17, the reference resistor Rref is configured by a resistance fixing unit Rref_fx and five resistance adjusting units Rref_ad1 to Ref_ad5 connected in series between terminal nodes RT1 and RT2. The resistance fixing unit Rref_fx includes a resistor R17 having a base resistance, and the resistance values ​​of the resistance adjusting units Rref_ad1 to Rref_ad5 controlled by switching signals 11 to 15 are added to this base resistance to determine the resistance value of the reference resistor Rref. In this case, the resolution of the resistance value to be added to the base resistance value becomes coarser in the order of the resistance adjusting units Rref_ad1 to Rref_ad5.

[0149] Here, the resistors constituting the resistance value adjustment units Rref_ad1 to Rref_ad5 are configured by combining basic resistors R each having a resistance value of 1 kΩ as explained in Fig. 17, but the present invention is not limited to this. Also, the present invention is described with reference to a case where the reference resistor Rref includes five resistance value adjustment units, but the present invention is not limited to five.

[0150] The resistance value adjustment unit Rref_ad1 includes resistors R21 and R22 and an NMOS transistor N51 that configures a short-circuit switch. The resistor R22 and the NMOS transistor N51 are connected in series, and the resistor R21 is connected in parallel to the series-connected resistor R22 and NMOS transistor N51. Here, the resistor R22 has two resistor sets (3×R) in which three basic resistors R are connected in series. The resistor R22 is realized by connecting two resistor sets (3×R) in parallel (3×R / 2). The resistor R21 is realized by connecting two basic resistors R in parallel (R / 2).

[0151] As described in the comparative example, the basic resistor R is 1 kΩ, so the resistance value of resistor R22 is 1.5 kΩ and the resistance value of resistor R21 is 0.5 kΩ. Therefore, when the NMOS transistor N51 is turned on by the switching signal 11, the resistance value of the resistance value adjustment unit Rref_ad1 is 0.375 kΩ, and when the NMOS transistor N51 is turned off, the resistance value of the resistance value adjustment unit Rref_ad1 is 0.5 kΩ. Therefore, the difference in the resistance value of the resistance value adjustment unit Rref_ad1 caused by the on / off of the short-circuit switch is set to 125 Ω, as in the comparative example. In addition, the number of elements constituting the resistance value adjustment unit Rref_ad1 (the number of NMOS transistors and the number of basic resistors) is the same as that of the resistance value adjustment unit of the comparative example (the number of NMOS transistors is 1 and the number of basic resistors is 8).

[0152] The resistance value adjustment unit Rref_ad2 includes resistors R23 and R24 and an NMOS transistor N52 that configures a short-circuit switch. In the resistance value adjustment unit Rref_ad2, the resistor R24 ​​and the NMOS transistor N52 are connected in series, and the resistor R23 is connected in parallel to the series-connected resistor R24 ​​and NMOS transistor N52. Here, the resistor R24 ​​is configured from three basic resistors R connected in series, and the resistor R23 is configured from one basic resistor R.

[0153] As a result, when the NMOS transistor N52 is turned on by the switching signal 12, the resistor R23 with a resistance of 1 kΩ and the resistor R24 ​​with a resistance of 3 kΩ are connected in parallel, and the resistance of the resistance adjustment unit Rref_ad2 becomes 0.75 kΩ. When the NMOS transistor N52 is turned off, the resistance of the resistance adjustment unit Rref_ad2 becomes 1 kΩ. Therefore, the difference in the resistance of the resistance adjustment unit Rref_ad2 caused by the on / off of the short-circuit switch is set to 250 Ω, as in the comparative example. In addition, the number of elements constituting the resistance adjustment unit Rref_ad2 (the number of NMOS transistors and the number of basic resistors) is the same as the resistance adjustment unit of the comparative example (the number of NMOS transistors is one and the number of basic resistors is four).

[0154] The resistance value adjusters Rref_ad3 to Rref_ad5 are similar to the resistance value adjusters Rref_ad3 to Rref_ad5 shown in FIG. 17, and therefore a description thereof will be omitted.

[0155] The resistance of resistor R17 constituting the resistance fixed unit Rref_fx is set to a value approximately 1 kΩ lower than the resistance of resistor R16 shown in the comparative example. This is because, in the comparative example, when NMOS transistors N51 and N52 are turned on by switching signals 11 and 12, the resistance of resistance adjusters Rref_ad1 and Rref_ad2 becomes 0Ω, whereas in the second embodiment, the resistance of resistance adjusters Rref_ad1 and Rref_ad2 becomes 0.375 kΩ and 0.75 kΩ.

[0156] The resistance value of the reference resistor Rref according to the second embodiment can be adjusted with approximately the same resolution (125Ω) and range as in the comparative example by controlling the short-circuit switches (NMOS transistors N51 to N55) using the switching signals 11 to 15. As in the comparative example, if the error caused by the on-resistance of the NMOS transistors constituting the short-circuit switches is to be suppressed to 10%, the resistance values ​​of the resistors R22 and R24 connected in series with the NMOS transistors N51 and N52 will be as large as 1.5 kΩ and 3 kΩ, respectively. Therefore, the on-resistance values ​​allowable for the NMOS transistors N51 and N52 can be increased to 150Ω (=1.5 kΩ×10%) and 300Ω (=3 kΩ×10%). As a result, the size of the NMOS transistors N51 and N52 can be reduced. Furthermore, since the resistance value of the resistor R17 is reduced, the resistor R17 itself can also be reduced in size. In other words, an increase in the occupied area can be suppressed.

[0157] In order to suppress the error to 10%, the on-resistance values ​​allowed for the NMOS transistors N53 to N55 are 50Ω, 100Ω, and 200Ω, similar to the comparative example.

[0158] <Modification> 10 shows a reference resistor Rref having a resistance value adjustment unit (for example, Rref_ad1) having a resistor in which four or more basic resistors R are connected in parallel in the comparative example shown in Fig. 17, in which the basic resistors R constituting the resistor (R11) are divided into 1:3 (1 to 3), the basic resistor R with a ratio of 3 is changed from a parallel connection to a series connection, and further, a short-circuit switch is connected in series to this series-connected basic resistor, and the basic resistor R with a ratio of 1 is connected in parallel. In Fig. 17, the resistance value adjustment units having a configuration in which four or more basic resistors R are connected in parallel are Rref_ad1 and Rref_ad2. Regarding the resistance value adjustment unit Rref_ad2 shown in FIG. 17, the resistor R12 formed by four basic resistors R connected in parallel in FIG. 17 is divided into a resistor R24 ​​formed by three basic resistors R connected in series and a resistor R23 formed by one basic resistor R in FIG. 10, the resistor R24 ​​is connected in series with an NMOS transistor N52 constituting a short-circuit switch, and the resistor R23 is connected in parallel to the series-connected NMOS transistor N52 and resistor R24.

[0159] In contrast to this, in a modified example, in the comparative example shown in Figure 17, a resistor formed by connecting two or more basic resistors R in parallel, is divided into 1:N-1 (1 to N-1), and the basic resistor R on the N-1 side is changed from parallel connection to series connection to form a reference resistor.

[0160] 11 is a circuit diagram showing the configuration of a reference resistor according to a modification of the second embodiment. Similar to FIGS. 10 and 17, the reference resistor Rref is composed of a resistance fixing unit Rref_fx and five resistance adjusting units Rref_ad1 to Rref_ad5 connected in series between terminal nodes RT1 and RT2. The resistance fixing unit Rref_fx has a resistor R18 with a base resistance, and the resistance values ​​of the resistance adjusting units Rref_ad1 to Rref_ad5 controlled by switching signals 11 to 15 are added to this base resistance to determine the resistance value of the reference resistor Rref.

[0161] In the comparative example of FIG. 17, the resistance value adjustment unit Rref_ad1 includes a resistor R11 configured with 8(N) basic resistors R connected in parallel. In the modified example shown in FIG. 11, the resistor R11 is divided into a resistor R25 configured with one basic resistor R and a resistor R26 configured with 7(N-1) basic resistors R connected in series. In the resistance value adjustment unit Rref_ad1, an NMOS transistor N51 is connected in series to the resistor R26, and a resistor R25 is connected in parallel to the series circuit configured with the resistor R26 and the NMOS transistor N51. The resistance value adjustment unit Rref_ad1 according to the modified example is configured with eight basic resistors R and one NMOS transistor, and therefore has the same number of elements as the resistance value adjustment unit Rref_ad1 shown in FIG. 17.

[0162] When the NMOS transistor N51 is turned on by the switching signal 11, the seven series-connected basic resistors R and one basic resistor R are connected in parallel, so the resistance value of the resistance value adjustment unit Rref_ad1 is 0.875 kΩ. In contrast, when the NMOS transistor N51 is turned off, the resistance value of the resistance value adjustment unit Rref_ad1 is 1 kΩ. The difference in the resistance value of the resistance value adjustment unit Rref_ad1 depending on whether the NMOS transistor N51 is on or off is 125 Ω, as in FIG. 10 and the comparative example.

[0163] 11, the resistance value adjustment units Rref_ad2, Rref_ad4, and Rref_ad5 are the same as those in FIG. 10. In the case of the resistance value adjustment unit Rref_ad2, the number of basic resistors R connected in parallel in FIG. 17 is four, and dividing it at a ratio of 1:3 in FIG. 10 and dividing it at a ratio of 1:N-1 in FIG. 11 will result in the same outcome. Also, in the case of the resistance value adjustment units Rref_ad4 and Rref_ad5, the basic resistors R are not connected in parallel in FIG. 17. Next, a description will be given of the resistance value adjustment unit Rref_ad3 in FIG. 17, in which the basic resistors R are connected in parallel and which can be divided at a ratio of 1:N-1.

[0164] In the comparative example of FIG. 17, the resistance value adjustment unit Rref_ad3 includes a resistor R13 configured with 2(N) basic resistors R connected in parallel. In the modified example shown in FIG. 11, the resistor R13 is divided into a resistor R27 configured with one basic resistor R and a resistor R28 configured with 1(N-1) basic resistors R. In the resistance value adjustment unit Rref_ad3, an NMOS transistor N53 is connected in series to the resistor R28, and a resistor R27 is connected in parallel to the series circuit configured with the resistor R28 and the NMOS transistor N53. Because the resistance value adjustment unit Rref_ad3 according to the modified example is configured with two basic resistors R and one NMOS transistor, the number of elements is the same as that of the resistance value adjustment unit Rref_ad3 shown in FIG. 17.

[0165] When the NMOS transistor N53 is turned on by the switching signal 13, two basic resistors R are connected in parallel, and the resistance value of the resistance value adjustment unit Rref_ad3 is 0.500 kΩ. In contrast, when the NMOS transistor N53 is turned off, the resistance value of the resistance value adjustment unit Rref_ad1 is 1 kΩ. Depending on whether the NMOS transistor N53 is turned on or off, the difference in the resistance value of the resistance value adjustment unit Rref_ad2 is 500 Ω, as in FIG. 10 and the comparative example.

[0166] When the NMOS transistors N51 to N53 are turned on, the resistance value added to the resistance value fixed section Rref_fx by the resistance value adjustment section increases to 0.875 kΩ, 0.750 kΩ, and 0.500 kΩ, so the resistance value of the resistor R18 that constitutes the resistance value fixed section Rref_fx is set to be approximately 2 kΩ smaller than the resistor R16 shown in the comparative example.

[0167] The resistance value of the reference resistor Rref according to the modification can be adjusted with approximately the same resolution (125Ω) and range as in the comparative example by controlling the short-circuit switches (NMOS transistors N51 to N55) with switching signals 11 to 15. As in the comparative example, when the error caused by the on-resistance of the NMOS transistors constituting the short-circuit switches is suppressed to 10%, the resistance values ​​of the resistors R26, R24, and R28 connected in series to the NMOS transistors N51, N52, and N53 become large, to 7 kΩ, 3 kΩ, and 1 kΩ, respectively, and therefore the on-resistance values ​​allowed for the NMOS transistors N51, N52, and N53 can be increased to 700Ω (=7 kΩ×10%), 300Ω (=3 kΩ×10%), and 100Ω (=1 kΩ×10%). As a result, it is possible to reduce the size of the NMOS transistors N51, N52, and N53 (to about 1 / 50, 1 / 10, or 1 / 2 times that of the comparative example), and since the resistance value of the resistor R18 is reduced, it is also possible to reduce the size of the resistor R18. In other words, it is possible to suppress an increase in the occupied area.

[0168] In order to suppress the error to 10%, the on-resistance values ​​allowed for the NMOS transistors N54 and N55 are 100Ω and 200Ω, respectively, similar to the comparative example.

[0169] <Configuration of semiconductor device> 12A and 12B are diagrams for explaining a semiconductor device according to embodiment 2. Here, Fig. 12A is a circuit diagram showing the configuration of the semiconductor device according to embodiment 2, and Fig. 12B is a circuit diagram showing the configuration of a reference resistor.

[0170] FIG. 12(A) is similar to FIG. 1(A). The main difference is that FIG. 12(A) shows a resistance value information storage circuit REF_O that sets the resistance value of the reference resistor Rref. Switching signals 11 to 15 for setting the resistance value of the reference resistor to an appropriate value are stored in advance in the resistance value information storage circuit REF_O. In the second embodiment, a reference resistor Rref is provided in each of the clamp voltage generation circuit and the multiple sense amplifiers SA, and the output of the resistance value information storage circuit REF_O is supplied to the reference resistors Rref in the clamp voltage generation circuit and the multiple sense amplifiers SA. This makes it possible to set the resistance value of each reference resistor Rref to an appropriate value while suppressing an increase in the area occupied by the resistance value information storage circuit REF_O.

[0171] A connection node RT1 of the reference resistor Rref is connected to the source terminal of the NMOS transistor N6 shown in Fig. 12(A), and a connection node RT2 is connected to the ground voltage Vss. Switching signals 11 to 15 are supplied to the resistance value adjusting units Rref_ad1 to Rref_ad5 from the resistance value information storage circuit REF_0. As described with reference to Figs. 10 and 11, the resistance value of the reference resistor Rref is adjusted to an appropriate value by the switching signals 11 to 15.

[0172] If the resistance value adjustment units Rref_ad1 to Rref_ad5 are considered to constitute an adjustment function unit that adjusts the resistance value, the adjustment function unit can be considered to be composed of a resistance value coarse adjustment unit (first adjustment unit) that roughly adjusts the resistance value, and a resistance value fine adjustment unit (second adjustment unit) that finely adjusts the resistance value in order to adjust a certain resistance value range with high resolution.

[0173] 12(B) corresponds to the reference resistor Rref shown in FIG. 10, and in FIG. 12(B), resistance value adjustment units Rref_ad1 to Rref_ad2 correspond to the fine resistance adjustment unit, and resistance value adjustment units Rref_ad3 to Rref_ad5 correspond to the coarse resistance adjustment unit. As shown in FIG. 12(B), the coarse resistance adjustment unit (first adjustment unit) is composed of a resistance element (first resistance element: 2×R) composed of a basic resistance R and a MOS transistor (N55) functioning as a short-circuit switch connected in parallel with the first resistance element, and the fine resistance adjustment unit (second adjustment unit) is composed of an adjustment unit composed of a resistance element (second resistance element: 3×R) and a short-circuit switch (N52) connected in series with the second resistance element, and a resistance element (third resistance element: R) connected in parallel with the adjustment unit.

[0174] In the first and second embodiments, the nonvolatile memory device is described taking the MRAM as an example, but is not limited to this, and may be a resistance change memory such as a ReRAM (Resistive Random Access Memory).

[0175] The invention made by the inventor has been specifically described above based on an embodiment, but it goes without saying that the present invention is not limited to the above embodiment and can be modified in various ways without departing from the gist of the invention. [Explanation of symbols]

[0176] 1000 Semiconductor device 1002 processor 1004 Non-volatile storage device 1100 Memory cell array (resistive memory cell array) 1103_1~1103_k Input / output circuit 1104 Control circuit CLPG Clamp voltage generation circuit MC11~MCnm memory cells N1 to N8, N11 to N25, N31 to N37, N41 to N42, N51 to N55 NMOS transistors NCC Noise Cancellation Circuit P1~P5 PMOS transistors Rref Reference resistor Rref_fx Resistance value fixed part Rref_ad1~Rref_ad5 Resistance value adjustment section SA Sense Amplifier TCP current compensation circuit VBLG initialization circuit

Claims

1. a resistance change memory cell array; a sense amplifier electrically connected to the resistance change type memory cell array; a clamp voltage generating circuit electrically connected to the sense amplifier; Equipped with The sense amplifier an amplifier for amplifying a voltage at the sense node; a first clamp circuit having a first NMOS transistor and a second NMOS transistor whose gate terminals are electrically connected to each other; a second clamp circuit having a third NMOS transistor and a fourth NMOS transistor whose gate terminals are electrically connected to each other; a fifth NMOS transistor electrically connected to the resistance change type memory cell array; a reference resistor, a sixth NMOS transistor electrically connected to the reference resistor; Equipped with a drain terminal of the third NMOS transistor is electrically connected to the amplifier unit via a first node constituting the sense node; a drain terminal of the fourth NMOS transistor is electrically connected to the amplifier unit via a second node constituting the sense node; a source terminal of the third NMOS transistor is electrically connected to a drain terminal of the first NMOS transistor via a third node; a source terminal of the fourth NMOS transistor is electrically connected to a drain terminal of the second NMOS transistor via a fourth node; a source terminal of the first NMOS transistor is electrically connected to a drain terminal of the fifth NMOS transistor via a fifth node; a source terminal of the second NMOS transistor is electrically connected to a drain terminal of the sixth NMOS transistor via a sixth node; a source terminal of the fifth NMOS transistor is electrically connected to the resistance change type memory cell array; a source terminal of the sixth NMOS transistor is electrically connected to the reference resistor; the clamp voltage generation circuit supplies a first clamp voltage to gate terminals of the first NMOS transistor and the second NMOS transistor, and supplies a second clamp voltage to gate terminals of the third NMOS transistor and the fourth NMOS transistor; a transconductance of the third NMOS transistor and the fourth NMOS transistor is lower than a transconductance of the first NMOS transistor and the second NMOS transistor; Semiconductor device.

2. 2. The semiconductor device according to claim 1, a channel length of the first NMOS transistor and the second NMOS transistor is shorter than a channel length of the third NMOS transistor and the fourth NMOS transistor, and / or a channel width of the first NMOS transistor and the second NMOS transistor is longer than a channel width of the third NMOS transistor and the fourth NMOS transistor; Semiconductor device.

3. 3. The semiconductor device according to claim 2, the sense amplifier includes a current correction circuit electrically connected to the third node and the fourth node; the current correction circuit applies a correction current based on a correction current bias signal input from the clamp voltage generation circuit to the third node and / or the fourth node; Semiconductor device.

4. 2. The semiconductor device according to claim 1, The semiconductor device includes: a VBL initialization circuit that generates an initialization potential to be supplied to the fifth node and the sixth node; The sense amplifier a seventh NMOS transistor having a drain terminal electrically connected to the fifth node and a source terminal electrically connected to the VBL initialization circuit; an eighth NMOS transistor having a drain terminal electrically connected to the sixth node and a source terminal electrically connected to the VBL initialization circuit; Furthermore, During standby, the seventh NMOS transistor and the eighth NMOS transistor are turned on, and the fifth NMOS transistor and the sixth NMOS transistor are turned off. Semiconductor device.

5. 5. The semiconductor device according to claim 4, The sense amplifier a first PMOS transistor; a second PMOS transistor; A noise cancellation circuit, Furthermore, The noise cancellation circuit an eleventh NMOS transistor; a twelfth NMOS transistor; and a thirteenth NMOS transistor; and a fourteenth NMOS transistor; and a fifteenth NMOS transistor; and Equipped with a gate terminal of the eleventh NMOS transistor is electrically connected to the clamp voltage generating circuit, and thereby the first clamp voltage is supplied thereto; a gate terminal of the twelfth NMOS transistor is electrically connected to the clamp voltage generating circuit, and thereby the second clamp voltage is supplied thereto; The drain terminal of the 11th NMOS transistor is electrically connected to the source terminal of the 12th NMOS transistor; a source terminal of the 11th NMOS transistor is electrically connected to a drain terminal of the 13th NMOS transistor and a drain terminal of the 14th NMOS transistor; a source terminal of the fourteenth NMOS transistor is electrically connected to the VBL initialization circuit; the first PMOS transistor is electrically connected to the first node; The second PMOS transistor is electrically connected to the second node. the fifteenth NMOS transistor is electrically connected to the drain terminal of the twelfth NMOS transistor; During the standby state, the thirteenth NMOS transistor and the fifteenth NMOS transistor are turned on, and the fourteenth NMOS transistor is turned off. Semiconductor device.

6. 2. The semiconductor device according to claim 1, The reference resistor is A first adjustment unit; a second adjustment unit connected in series with the first adjustment unit; Equipped with the first adjustment unit includes a first resistor element and a first transistor that functions as a short-circuit switch, connected in parallel; the second adjustment unit has an adjustment unit in which a second resistor element and a second transistor functioning as a short-circuit switch are connected in series, and the adjustment unit is connected in parallel to a third resistor element; Semiconductor device.

7. 2. The semiconductor device according to claim 1, the resistance change memory cell array is a magnetoresistive memory cell array; Semiconductor device.

8. a memory cell array in which a plurality of resistance change type memory cells are arranged; a sense amplifier connected to the memory cell array; a clamp voltage generating circuit that generates a clamp voltage for clamping a voltage applied to a resistance change memory cell selected from the plurality of resistance change memory cells during a read operation; Equipped with The sense amplifier an amplifier that amplifies a potential difference between a pair of sense nodes; a precharge circuit that supplies a predetermined voltage to the pair of sense nodes during standby before the read operation; a reference resistor, a first MOS transistor and a second MOS transistor, the source-drain paths of which are connected in series between one of the pair of sense nodes and the selected resistance change memory cell; a third MOS transistor and a fourth MOS transistor, the source-drain paths of which are connected in series between the other of the pair of sense nodes and the reference resistor; Equipped with the clamp voltage is applied to gate terminals of the first MOS transistor, the second MOS transistor, the third MOS transistor, and the fourth MOS transistor; a size of the first MOS transistor connected to the one sense node of the first MOS transistor and the second MOS transistor is smaller than a size of the second MOS transistor; the size of the third MOS transistor connected to the other sense node out of the third MOS transistor and the fourth MOS transistor is smaller than the size of the fourth MOS transistor; Semiconductor device.

9. 9. The semiconductor device according to claim 8, the sense amplifier includes a current correction circuit that supplies a correction current to a node connecting the first MOS transistor and the second MOS transistor and a node connecting the third MOS transistor and the fourth MOS transistor; Semiconductor device.

10. 10. The semiconductor device according to claim 9, the clamp voltage generation circuit generates, as the clamp voltage, a first clamp voltage and a second clamp voltage different from the first clamp voltage; a gate terminal of the first MOS transistor and a gate terminal of the third MOS transistor are connected to a first wiring to which the first clamp voltage is applied; a gate terminal of the second MOS transistor and a gate terminal of the fourth MOS transistor are connected to a second wiring to which the second clamp voltage is applied; the semiconductor device includes an initialization circuit that generates an initialization voltage that is lower than the predetermined voltage supplied by the precharge circuit; the sense amplifier includes a selection circuit that supplies the initialization voltage generated by the initialization circuit to the third MOS transistor and the fourth MOS transistor during the standby state. Semiconductor device.

11. 11. The semiconductor device according to claim 10, the sense amplifier includes a noise cancellation circuit having a fifth MOS transistor and a sixth MOS transistor whose source-drain paths are connected in series; a gate terminal of the fifth MOS transistor is connected to the first wiring, and a gate terminal of the sixth MOS transistor is connected to the second wiring; the sixth MOS transistor is supplied with the initialization voltage by the selection circuit during the standby state; Semiconductor device.

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