Semiconductor device

Abstract

To provide a semiconductor device excellent in product reliability.SOLUTION: A semiconductor device comprises a glass substrate, a base layer on the glass substrate, and a thin film transistor on the base layer. The base layer has a structure in which a first insulating layer made of silicon oxide, a second insulating layer made of silicon nitride, a conductive layer, and a third insulating layer made of silicon oxide are stacked in this order from the glass substrate side. The base layer may include a fourth insulating layer made of silicon oxide between the second insulating layer and the conductive layer.SELECTED DRAWING: Figure 1

Description

[Technical Field]

[0001] The present invention relates to a semiconductor device in which thin film transistors are provided on a glass substrate. [Background technology]

[0002] A semiconductor device is known that includes a thin film transistor formed on a glass substrate using a semiconductor layer such as polysilicon. In such a semiconductor device, as described in Patent Document 1, for example, a base layer is formed on the glass substrate.

[0003] The semiconductor device disclosed in Patent Document 1 has a structure in which an insulating layer such as silicon oxide, silicon nitride, or silicon oxynitride and a light-shielding layer made of titanium are stacked in a portion corresponding to the base layer of a thin-film transistor. [Prior art documents] [Patent documents]

[0004] [Patent Document 1] Japanese Patent Application Laid-Open No. 2005-252188 Summary of the Invention [Problem to be solved by the invention]

[0005] Silicon nitride has excellent properties as a barrier film, but it is known that charge traps are formed in the film and at the interface. Charge traps in the underlayer can affect the characteristics of thin-film transistors, which is a problem. The semiconductor device disclosed in Patent Document 1 has a structure in which an insulating layer and a metal layer are stacked as described above, but the effect of charge traps is not taken into consideration, which is a problem.

[0006] The present invention has been made with a focus on the layer structure of the underlayer, and has an object to provide a semiconductor device with excellent product reliability. [Means for solving the problem]

[0007] A semiconductor device according to one embodiment of the present invention comprises a glass substrate, a base layer on the glass substrate, and a thin-film transistor on the base layer, wherein the base layer has a structure in which, from the glass substrate side, a first insulating layer made of silicon oxide, a second insulating layer made of silicon nitride, a conductive layer, and a third insulating layer made of silicon oxide are stacked in this order. [Brief explanation of the drawings]

[0008] [Figure 1] 1 is a cross-sectional view showing an outline of a semiconductor device according to a first embodiment of the present invention. [Figure 2] FIG. 10 is a cross-sectional view showing an outline of a semiconductor device according to another embodiment of the present invention. [Figure 3] FIG. 4 is a cross-sectional view showing an outline of a semiconductor device according to a second embodiment of the present invention. [Figure 4] 1 is a graph showing the Vg-Id characteristics of the semiconductor device of Example 1. [Figure 5] 10 is a graph showing the Vg-Id characteristics of the semiconductor device of Reference Example 1. [Figure 6] 10 is a graph showing the Vg-Id characteristics of the semiconductor device of Example 2. [Figure 7] 10 is a graph showing the Vg-Id characteristics of the semiconductor device of Reference Example 2. DETAILED DESCRIPTION OF THE INVENTION

[0009] Hereinafter, embodiments of the present invention will be described with reference to the drawings. To clarify the description, the drawings may show the width, thickness, shape, etc. of each part more schematically than the actual embodiment, but these are merely examples and are not intended to limit the interpretation of the present invention. In this specification and each drawing, elements similar to those previously described with reference to the previous drawings are designated by the same reference numerals, and detailed descriptions may be omitted as appropriate.

[0010] First Embodiment A semiconductor device 1 according to a first embodiment of the present invention will be described. Fig. 1 is a cross-sectional view showing an outline of the semiconductor device 1. As shown in Fig. 1, the semiconductor device 1 includes a glass substrate 10, a base layer 20, and a thin film transistor 30, in that order.

[0011] From the viewpoint of strength of the semiconductor device 1, a glass substrate 10 is used as the substrate.

[0012] The base layer 20 is formed on the glass substrate 10. The base layer 20 has a structure in which a first insulating layer 210, a second insulating layer 220, a conductive layer 250, and a third insulating layer 230 are stacked from the glass substrate 10 side. The second insulating layer 220 is formed on the first insulating layer 210 and is in contact with the first insulating layer 210. The conductive layer 250 is formed on the second insulating layer 220 and is in contact with the second insulating layer 220. The third insulating layer 230 is formed on the conductive layer 250 and is in contact with the conductive layer 250. The layer configuration of the base layer 20 is not limited to this. For example, from the viewpoint of insulation properties of the semiconductor device 1, the base layer 20 may have a fourth insulating layer 240 between the second insulating layer 220 and the conductive layer 250, as shown in FIG. 2 .

[0013] The first insulating layer 210 and the third insulating layer 230 are made of silicon oxide (SiO2). The second insulating layer 220 is made of silicon nitride (SiN x ). The first insulating layer 210, the second insulating layer 220, and the third insulating layer 130 are formed, for example, by using a plasma CVD (chemical vapor deposition) method. Silicon oxide has excellent affinity with the semiconductor layer 310. Silicon nitride has excellent ion blocking properties. When the base layer 20 further includes an insulating layer, such as the fourth insulating layer 240, the insulating layer is made of silicon oxide, silicon nitride, silicon oxynitride, or the like, and is formed by using a plasma CVD method.

[0014] The conductive layer 250 is made of, for example, a metal such as titanium, aluminum, tantalum, molybdenum, or tungsten, or an alloy thereof. The conductive layer 250 is formed, for example, by using a sputtering method. The conductive layer 250 is made of, for example, a metal such as molybdenum or tungsten, or an alloy thereof. The conductive layer 250 can block light incident on the thin-film transistor 30 from the glass substrate 10 side, and therefore can also be called a light-shielding layer.

[0015] The thin film transistor 30 has a structure in which a semiconductor layer 310, a gate insulating layer 320, and a gate electrode layer 330 are stacked in this order from the base layer 20 side. The semiconductor layer 310 is formed on the base layer 20 and is in contact with the base layer 20. The gate insulating layer 320 is formed on the semiconductor layer 310 and is in contact with the semiconductor layer 310. The gate electrode layer 330 is formed on the gate insulating layer 320 and is in contact with the gate insulating layer 320.

[0016] The semiconductor layer 310 is made of, for example, amorphous silicon, polysilicon, or an oxide semiconductor made of an oxide of indium, gallium, zinc, or the like. The semiconductor layer 310 is formed, for example, by using a sputtering method or a plasma CVD method. When the semiconductor layer 310 is made of polysilicon, it may be formed by subjecting amorphous silicon formed on the base layer 20 to heat treatment using laser irradiation or the like.

[0017] A channel region 310c is formed in the semiconductor layer 310 in a region overlapping with the gate electrode layer 330. The semiconductor layer 310 has a region extending outward from the region overlapping with the gate electrode layer 330. A source region 310s and a drain region 310d doped with n-type impurities or p-type impurities are formed on both sides of the channel region 310c of the semiconductor layer 310. Thus, the semiconductor layer 310 includes the source region 310s, the channel region 310c, and the drain region 310d within the layer. When doped with n-type impurities, the thin film transistor 30 becomes an n-channel thin film transistor 30n. When doped with p-type impurities, the thin film transistor 30 becomes a p-channel thin film transistor 30p.

[0018] The gate insulating layer 320 is made of, for example, silicon oxide and is formed by, for example, plasma CVD.

[0019] The gate electrode layer 330 is made of, for example, a metal such as aluminum, tantalum, molybdenum, or an alloy of these metals, and is formed by, for example, sputtering.

[0020] In conventional semiconductor devices, the base layer may consist of three layers: a first insulating layer made of silicon oxide, a second insulating layer made of silicon nitride, and a third insulating layer made of silicon oxide. In this case, positive fixed charges due to charge traps may exist in the second insulating layer made of silicon nitride, at the interface between the first and second insulating layers in the second insulating layer, and at the interface between the second and third insulating layers in the second insulating layer. The semiconductor layer is affected by these fixed charges, causing the threshold voltage (Vth) of the semiconductor device to shift negatively. This results in an n-channel transistor entering a normally-on state (a state in which drain current flows between the source and drain even when no voltage is applied to the gate electrode). To prevent n-channel transistors from becoming normally-on, a technique is used in which the semiconductor layer is doped with p-type impurities (acceptor impurities). Specifically, in the case of n-channel thin-film transistors, the semiconductor layer is doped with p-type impurities to mitigate the effects of these fixed charges. The doping of p-type impurities is performed using ion implantation. Ion implantation is a method in which p-type impurity ions are accelerated by an electric field and implanted into a semiconductor layer. Therefore, if the dose of p-type impurities is large, ion implantation damage will occur, resulting in a decrease in field-effect mobility.

[0021] In contrast, in the semiconductor device 1 according to the first embodiment of the present invention, the conductive layer 250 is disposed between the second insulating layer 220, which has a positive fixed charge, and the semiconductor layer 310, which is affected by the positive fixed charge. This prevents the influence of the positive fixed charge by the conductive layer 250. Therefore, the threshold voltage (Vth) of the thin-film transistor 30 is optimized. That is, even if fixed charges accumulate in the second insulating layer 220 made of silicon nitride that forms the underlayer 20 and at the interfaces with the upper and lower layers, the presence of the conductive layer 250 between the second insulating layer 220 and the semiconductor layer 310 shields the electric field caused by the fixed charges, thereby preventing a negative shift in the threshold voltage (Vth) of the thin-film transistor 30. As a result, the dose of p-type impurities doped into the semiconductor layer 310 can be reduced, thereby preventing a decrease in field-effect mobility.

[0022] Second Embodiment A semiconductor device 2 according to a second embodiment of the present invention will be described. Fig. 3 is a cross-sectional view showing an outline of the semiconductor device 2. As shown in Fig. 3, the semiconductor device 2 includes a glass substrate 10, an underlayer 20, and an n-channel thin film transistor 30n and a p-channel thin film transistor 30p on the underlayer 20. The glass substrate 10, the underlayer 20, the n-channel thin film transistor 30n, and the p-channel thin film transistor 30p are configured in the same manner as in the first embodiment, and can be formed in the same manner.

[0023] The base layer 20 has a structure in which a first insulating layer 210 made of silicon oxide, a second insulating layer 220 made of silicon nitride, and a third insulating layer 230 made of silicon oxide are stacked in this order from the glass substrate 10 side. The layer configuration of the base layer 20 is not limited to this. For example, from the viewpoint of the insulating properties of the semiconductor device 2, a fourth insulating layer 240 may be further included.

[0024] In a cross-sectional view, the base layer 20 has a first light-shielding layer 251 overlapping the n-channel thin-film transistor 30n between the second insulating layer 220 and the third insulating layer 230. While the first light-shielding layer 251 is conductive, in a cross-sectional view, the base layer 20 overlapping the p-channel thin-film transistor 30p does not have a conductive layer between the second insulating layer 220 and the semiconductor layer 310, and has a second light-shielding layer 252 overlapping the p-channel thin-film transistor 30p between the glass substrate 10 and the first insulating layer 210. Note that the base layer 20 overlapping the p-channel transistor 30p may not have the second light-shielding layer 252.

[0025] According to the semiconductor device 2 of the second embodiment of the present invention, in a cross-sectional view, the base layer 20 on which the n-channel thin-film transistor 30n overlaps has a conductive first light-shielding layer 251 between the second insulating layer 220 and the third insulating layer 230, and therefore the first light-shielding layer 251 can block the influence of positive fixed charges present in the second insulating layer 220. On the other hand, in a cross-sectional view, the base layer 20 on which the p-channel thin-film transistor 30p overlaps does not have a conductive layer between the second insulating layer 220 and the semiconductor layer 310, and therefore is influenced by positive fixed charges present in the second insulating layer 220. With this configuration, even if the n-channel thin-film transistor 30n and the p-channel thin-film transistor 30n have the same impurity doping amount, the Vth of the n-channel thin-film transistor 30n and the p-channel thin-film transistor 30n are approximately the same, and the Vth of the semiconductor device 2 can be optimized. [Example]

[0026] The present invention will be specifically explained below with reference to examples, but the present invention is not limited thereto.

[0027] Example 1 The semiconductor device of Example 1 comprises a glass substrate, base layers (first insulating layer, second insulating layer, fourth insulating layer, conductive layer, third insulating layer), and an n-channel thin-film transistor (semiconductor layer, gate insulating layer, gate electrode layer). A 500-nm-thick first insulating layer made of silicon oxide, a 50-nm-thick second insulating layer made of silicon nitride, and a 50-nm-thick fourth insulating layer made of silicon oxide were sequentially formed on a 0.5-mm-thick glass substrate. A 50-nm-thick conductive layer made of a molybdenum-tungsten alloy was formed on the fourth insulating layer. A 200-nm-thick third insulating layer made of silicon oxide was formed on the conductive layer. A polysilicon semiconductor layer was formed on the third insulating layer and doped with n-type impurities. A 100-nm-thick gate insulating layer made of silicon oxide and a 250-nm-thick gate electrode layer made of MoW were sequentially formed on the semiconductor layer.

[0028] (Reference example 1) The semiconductor device of Reference Example 1 is composed of a glass substrate, base layers (first insulating layer, second insulating layer, fourth insulating layer, third insulating layer), and an n-channel thin film transistor (semiconductor layer, gate insulating layer, gate electrode layer). The semiconductor device of Reference Example 1 was fabricated in the same manner as the semiconductor device of Example 1, except that no conductive layer was formed.

[0029] Example 2 The semiconductor device of Example 2 is composed of a glass substrate, base layers (first insulating layer, second insulating layer, fourth insulating layer, conductive layer, third insulating layer), and a p-channel thin film transistor (semiconductor layer, gate insulating layer, gate electrode layer). The semiconductor device of Example 2 was fabricated in the same manner as the semiconductor device of Example 1, except that the same amount of p-type impurities were doped instead of n-type impurities.

[0030] (Reference example 2) The semiconductor device of Comparative Example 2 is composed of a glass substrate, base layers (first insulating layer, second insulating layer, fourth insulating layer, third insulating layer), and a p-channel thin film transistor (semiconductor layer, gate insulating layer, gate electrode layer). The semiconductor device of Reference Example 2 was fabricated in the same manner as the semiconductor device of Example 2, except that no conductive layer was formed.

[0031] The Vg-Id characteristics of the semiconductor devices of Example 1, Reference Example 1, Example 2, and Reference Example 2 were measured when the drain-source voltage (Vd) was set to 0.1 V. Graphs of the Vg-Id characteristics of the semiconductor devices of Example 1, Reference Example 1, Example 2, and Reference Example 2 are shown in FIGS.

[0032] As shown in Figures 4 and 5, in a semiconductor device consisting of an n-channel thin film transistor, providing a conductive layer between the second insulating layer and the semiconductor layer prevents the influence of positive fixed charges present in the second insulating layer, shifting the Vth of the semiconductor device to the positive side by about 2 V, and optimizing the Vth. Also, as shown in Figures 6 and 7, in a semiconductor device consisting of a p-channel thin film transistor, providing a conductive layer between the second insulating layer and the semiconductor layer prevents the influence of positive fixed charges present in the second insulating layer, shifting the Vth of the semiconductor device to the positive side by about 1 V, and optimizing the Vth.

[0033] Furthermore, as shown in Figures 4 and 7, in a semiconductor device consisting of n-channel thin film transistors, a conductive layer is provided between the second insulating layer and the semiconductor layer, and in a semiconductor device consisting of p-channel thin film transistors, a conductive layer is not provided between the second insulating layer and the semiconductor layer.By doing so, even if the impurity doping amounts of the n-channel thin film transistor and the p-channel thin film transistor are the same, the Vth of the n-channel thin film transistor and the p-channel thin film transistor become approximately the same, and it is possible to optimize the Vth of the semiconductor device.

[0034] Other effects and advantages brought about by the aspects described in this embodiment that are clear from the description in this specification or that can be appropriately thought of by a person skilled in the art are naturally understood to be brought about by the present invention. [Explanation of symbols]

[0035] 1, 2 Semiconductor device 10 Glass substrate 20 Base layer 210 First insulating layer 220 Second insulating layer 230 Third insulating layer 240 Fourth insulating layer 250 conductive layer 251 1st light shielding layer 252 2nd light shielding layer 30 Thin-film transistor 30n n-channel thin film transistor 30p p-channel thin film transistor 310 Semiconductor layer 310s Source Region 310c channel region 310d drain region 320 Gate insulating layer 330 gate electrode layer

Claims

1. A glass substrate; an underlayer on the glass substrate; a thin film transistor on the underlayer, the base layer has a structure in which, from the glass substrate side, a first insulating layer made of silicon oxide, a second insulating layer made of silicon nitride, a conductive layer, and a third insulating layer made of silicon oxide are stacked in this order.

2. 2. The semiconductor device according to claim 1, wherein said conductive layer is made of a metal.

3. 3. The semiconductor device according to claim 2, wherein said base layer has a fourth insulating layer made of silicon oxide between said second insulating layer and said conductive layer.

4. A glass substrate; an underlayer on the glass substrate; an n-channel thin film transistor and a p-channel thin film transistor on the underlayer, the underlayer has a structure in which a first insulating layer made of silicon oxide, a second insulating layer made of silicon nitride, and a third insulating layer made of silicon oxide are stacked in this order from the glass substrate side; the underlayer has a first light-shielding layer overlapping the n-channel thin film transistor, The semiconductor device, wherein the first light-shielding layer is conductive and is disposed between the second insulating layer and the third insulating layer.

5. the underlayer has a second light-shielding layer overlapping the p-channel thin film transistor, The semiconductor device according to claim 4 , wherein the second light-shielding layer is disposed between the substrate and the first insulating layer.

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