Semiconductor device

Abstract

To enable increase in warpage of a semiconductor chip to be suppressed while reducing on-resistance.SOLUTION: In a region where a pad arrangement region Re and an active region Rb overlap each other, pads 12a to 12e are arranged on a source electrode 113 functioning as a surface electrode via a separation insulating film, and as a result, a semiconductor device has two-layer wiring electrode structure in which two layers of wiring electrode material are stacked. In a region which does not overlap the pad arrangement region Re, of the active region Rb, the semiconductor device has one-layer wiring electrode structure in which the source electrode 113 functioning as the surface electrode is constituted of a one layer of the wiring electrode material.SELECTED DRAWING: Figure 2B

Description

[Technical Field]

[0001] The present invention relates to a semiconductor device having pads on the surface of a chip. [Background technology]

[0002] Conventionally, there have been semiconductor devices in which semiconductor elements such as switching elements are built into a semiconductor chip (see, for example, Patent Document 1). In such semiconductor devices, an active area that operates as a semiconductor element is arranged over a wide area including the center of the semiconductor chip. An area of ​​the semiconductor chip different from the active area, specifically an area adjacent to the active area along one side of the semiconductor chip, is used as a pad arrangement area, and pads are arranged in this pad arrangement area. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] Japanese Patent Application Publication No. 2017-204570 Summary of the Invention [Problem to be solved by the invention]

[0004] However, in the semiconductor device described above, the active area and the pad arrangement area are separate areas, and the pad arrangement area is an area where the semiconductor element cannot operate. Therefore, the proportion of the active area to the total area of ​​the semiconductor chip is reduced by the amount of the pad arrangement area, and the on-resistance of the semiconductor element cannot be reduced significantly.

[0005] Therefore, the inventors discovered a structure in which the active area is expanded to include the area below the pads in the pad arrangement area, which increases the ratio of the active area to the total area of ​​the semiconductor chip and makes it possible to reduce the on-resistance of the semiconductor element.

[0006] In a semiconductor device having such a structure, a semiconductor element is formed below the pad arrangement region, and therefore, the wiring electrode material constituting the pad is disposed on top of the wiring electrode material constituting the electrode connected to the semiconductor element. In other words, the second-layer upper wiring electrode is laminated on top of the first-layer lower wiring electrode connected to the semiconductor element. In the pad arrangement region, the lower-layer wiring electrode and the upper-layer wiring electrode must be insulated from each other, so an insulating film can be disposed between them, and the lower-layer wiring electrode and the upper-layer wiring electrode can be connected in the region of the active region that does not overlap with the pad arrangement region.

[0007] However, as a result of intensive research by the present inventors, it was found that the wiring electrode material becomes too thick when it is stacked, and this increases the warpage that occurs in the semiconductor chip at high temperatures.

[0008] In view of the above, an object of the present invention is to provide a semiconductor device that can reduce the on-resistance while suppressing an increase in warpage of the semiconductor chip. [Means for solving the problem]

[0009] In order to achieve the above object, the invention described in claim 1 is a semiconductor device constituted by a semiconductor chip (10), which has an active region (Ra) in which a semiconductor element is formed and in which surface electrodes (113) made of wiring electrode material are arranged, connected to the semiconductor element on one surface side of the semiconductor chip, and a pad arrangement region (Re) which is provided so as to overlap with the active region in a normal direction to the one surface of the semiconductor chip and in which pads (12a-12e) made of wiring electrode material are arranged. In the region where the pad arrangement region and the active region overlap, pads are arranged on the surface electrodes via an isolation insulating film (116), thereby forming a two-layer wiring electrode structure in which two layers of wiring electrode material are stacked, and outside the two-layer wiring electrode structure, a wiring layer (130) is provided which is electrically connected to a contact region (108) included in the semiconductor element, and the wiring layer is a single-layer electrode structure formed of one layer of the wiring electrode material.

[0010] In this way, by making the wiring layer arranged on the outside of the two-layer wiring structure a single-layer electrode structure, the wiring layer can also be made thin, making it possible to suppress an increase in warping at high temperatures.

[0011] In the invention described in claim 2, a wiring layer (130) electrically connected to a contact region (108) included in the semiconductor element is provided outside the active region, and the wiring layer has a single-layer electrode structure made of a single layer of wiring electrode material.

[0012] In this way, by making the wiring layer arranged outside the active region a single-layer electrode structure, the wiring layer can also be configured to be thin, making it possible to suppress an increase in warping at high temperatures.

[0013] The reference symbols in parentheses attached to each component indicate an example of the correspondence between the component and the specific components described in the embodiments described below. [Brief explanation of the drawings]

[0014] [Figure 1] FIG. 1 is a cross-sectional view of a power module according to a first embodiment. [Figure 2A] FIG. 2 is a top view layout diagram of a semiconductor chip provided in the power module shown in FIG. [Figure 2B] FIG. 1 is a diagram showing hatched areas in a semiconductor chip that have a two-layer wiring electrode structure. [Figure 3] 3 is a cross-sectional view taken along line III-III in FIG. 2A when a vertical MOSFET is formed on a semiconductor chip. [Figure 4] 4 is a cross-sectional view taken along line IV-IV in FIG. 2A when a vertical MOSFET is formed on a semiconductor chip. [Figure 5] FIG. 3 is a cross-sectional view of a semiconductor chip used as a comparative example, which corresponds to the cross section taken along line III-III in FIG. 2A. [Figure 6]FIG. 4 is a cross-sectional view of a semiconductor chip used as a comparative example, which corresponds to the cross section taken along line IV-IV in FIG. 2A. [Figure 7] FIG. 10 is a diagram showing the results of a simulation of the on-resistance of the semiconductor chip of the first embodiment and a comparative example. [Figure 8] 1 is a flowchart showing a method for manufacturing a semiconductor device. [Figure 9] FIG. 10 is a diagram showing, by hatching, an area having a two-layer wiring electrode structure in a semiconductor chip according to a second embodiment. [Figure 10] 3 is a cross-sectional view of the semiconductor chip according to the second embodiment, which corresponds to the cross section taken along line III-III in FIG. 2A. [Figure 11] FIG. 10 is a top surface layout diagram of a semiconductor chip according to a fourth embodiment. [Figure 12] FIG. 10 is a top view layout diagram of a semiconductor chip according to a fifth embodiment. DETAILED DESCRIPTION OF THE INVENTION

[0015] Hereinafter, embodiments of the present invention will be described with reference to the accompanying drawings. In the following embodiments, parts that are identical or equivalent to each other will be denoted by the same reference numerals.

[0016] (First embodiment) First, a first embodiment will be described with reference to Fig. 1, taking as an example a case where a semiconductor device according to this embodiment is applied to a power module.

[0017] The power module shown in Fig. 1 incorporates a semiconductor chip 10 corresponding to the semiconductor device of this embodiment, and is used, for example, as a switching device for driving a motor. Specifically, the power module includes the semiconductor chip 10, a heat sink 20, a heat sink 30, etc. The semiconductor chip 10, the heat sink 20, and the heat sink 30 are bonded together by a bonding material 50 including first to third bonding materials 50a to 50c. These are then sealed with a mold resin 60.

[0018] Specifically, the lower surface of the semiconductor chip 10 is defined as the lower surface, and the upper surface of the semiconductor chip 10 is defined as the upper surface. The lower surface of the semiconductor chip 10 is bonded to the upper surface of the heat sink 20 by a first bonding material 50a. The heat sink 20 is formed of a laminate in which a metal layer 21, an insulating layer 22, and a metal layer 23 are stacked in this order. The metal layer 23 side is bonded to the lower surface of the semiconductor chip 10 via the first bonding material 50a. The upper surface of the semiconductor chip 10 is bonded to the heat sink 30 by a second bonding material 50b and a third bonding material 50c. The heat sink 30 is formed of a laminate in which a metal layer 31, an insulating layer 32, and a metal layer 33 are stacked in this order. The metal layer 33 is divided into multiple connection portions 33a and 33b. The divided connection portions 33a and 33b are bonded to the upper surface of the semiconductor chip 10 via the second bonding material 50b and the third bonding material 50c.

[0019] As will be described later, the connection portion 33a is connected to a source electrode 113 corresponding to a surface electrode of the active region Rb of the semiconductor chip 10 shown in FIG. 2A, and the connection portion 33b is connected to each of the pads 12a to 12e in the pad arrangement region Re of the semiconductor chip 10. Although only one connection portion 33b is shown in FIG. 1, there are provided as many as the pads 12a to 12e. The connection portion 33a also has a lead portion (not shown) that is led out from the mold resin 60 to enable electrical connection to the outside. Each connection portion 33b also has a lead portion (not shown) that is led out from the mold resin 60 to enable electrical connection to the outside. The metal layer 23 also has a lead portion (not shown) that is led out from the mold resin 60 to enable electrical connection to the outside.

[0020] In this embodiment, the bonding material 50 including the first to third bonding materials 50a to 50c is made of a bonding metal such as a lead-free solder, which is a conductive material, or a conductive adhesive. The bonding material 50 physically and electrically connects the semiconductor chip 10, the heat sink 20, and the heat sink 30 to each other.

[0021] With this configuration, the upper surface of the semiconductor chip 10 is electrically connected to the outside and dissipates heat via the second bonding material 50b, the third bonding material 50c, and the heat sink 30. Also, the lower surface of the semiconductor chip 10 is electrically connected to the outside and dissipates heat via the first bonding material 50a and the heat sink 20.

[0022] The semiconductor chip 10 is a semiconductor device in which semiconductor elements are formed on a semiconductor substrate such as silicon carbide (SiC), and is, for example, in the form of a rectangular thin plate. The semiconductor chip 10 may be made of a material other than SiC. However, in the case of SiC, since high-voltage semiconductor elements are used, the semiconductor chip 10 may become hotter than when made of other materials, and the effects of warping may be greater. For this reason, it is preferable to apply the present disclosure when the semiconductor chip 10 is made of SiC.

[0023] Examples of semiconductor elements formed on the semiconductor chip 10 include vertical MOSFETs and vertical IGBTs (insulated gate bipolar transistors). In the present embodiment, a detailed structure will be described later, but a vertical MOSFET is formed on the semiconductor chip 10.

[0024] A connection portion 33a is bonded to a portion of the top surface of the semiconductor chip 10, and a plurality of connection portions 33b are connected to portions of the semiconductor chip 10 outside the portion connected to the connection portion 33a. A surface electrode provided in the active region Rb of the semiconductor chip 10, i.e., a source electrode 113 in a vertical MOSFET, is connected to the connection portion 33a. Furthermore, each of the pads 12a to 12e provided in the pad arrangement region Re of the semiconductor chip 10 is connected to the connection portion 33b. Although only one connection portion 33b is shown in FIG. 1, there are actually as many connection portions 33b as there are pads 12a to 12e. Meanwhile, a back electrode, i.e., a drain electrode 114 in the case of a vertical MOSFET, is formed on the back surface of the semiconductor chip 10, and the entire surface of the back surface electrode is connected to the metal layer 23 of the heat sink 20.

[0025] Heat sink 20 has high heat dissipation properties by insulating metal layer 21 and metal layer 23, which are arranged on both sides of insulating layer 22, with metal layer 21 and metal layer 23 being made of a metal with high thermal conductivity, such as copper. Because metal layer 21 and metal layer 23 are insulated from each other, metal layer 23 is insulated from the outside while the metal layer 21 side is exposed from mold resin 60 to serve as a heat dissipation surface that facilitates heat dissipation.

[0026] The heat sink 30 achieves high heat dissipation by insulating the metal layers 31 and 33, which are disposed on both sides of the insulating layer 32, with the metal layers 31 and 33 being made of a metal with high thermal conductivity, such as copper. Because the metal layers 31 and 33 are insulated from each other, the metal layer 31 is exposed from the molded resin 60 to provide a heat dissipation surface that facilitates heat dissipation, while the metal layer 33 is insulated from the outside. The metal layer 33 is also divided into multiple sections to form connection portions 33a and 33b. While the connection portion 33b would conventionally be formed using a bonding wire, this section is also formed using a portion of the metal layer 33 included in the heat sink 30, thereby achieving high heat dissipation.

[0027] The mold resin 60 seals the semiconductor chip 10, the heat sink 20, the heat sink 30, etc. One surface of the heat sink 20 and the heat sink 30, and one end of the lead portion of the metal layer 23 and the metal layer 33 (not shown) are exposed from the mold resin 60. The exposed end of each lead portion can be electrically connected to the outside.

[0028] Next, the detailed structure of the semiconductor chip 10 in the semiconductor device configured as above will be described.

[0029] 2A and 2B, the semiconductor chip 10 has a rectangular plate-like top surface. The semiconductor chip 10 is provided with an internal region Ra, an active region Rb, a connecting region Rc, a peripheral region Rd, and a pad arrangement region Re.

[0030] The inner region Ra is a region including the central portion of the semiconductor chip 10, and is a portion where a source electrode 113 corresponding to a surface electrode, which will be described later, is exposed. This portion serves as a source pad 11.

[0031] The active region Rb is a region of the semiconductor chip 10 where a semiconductor element is operated. In this embodiment, a vertical MOSFET is formed as the semiconductor element in the active region Rb. The active region Rb surrounds the inner region Ra and is formed to a position a predetermined distance inward from the outer edge of the semiconductor chip 10, and in this embodiment, is a rectangular region.

[0032] The connecting region Rc is a region provided between the active region Rb and the peripheral region Rd, and is shaped like a rectangular frame, for example, and includes a gate wiring layer 120 that constitutes a gate liner, which will be described later.

[0033] The peripheral region Rd is arranged around the entire outer edge of the semiconductor chip 10, surrounding the active region Rb and the connecting region Rc, and is a region in which a peripheral breakdown voltage structure, etc. is provided, and in this embodiment, it has a rectangular frame shape.

[0034] The pad arrangement region Re is a region where the various pads 12a to 12e are arranged. The pad arrangement region Re is a part of the active region Rb, in this case, a region along one side of the rectangular active region Rb, that is, along the side on the lower side of the paper in FIG. 2A. The pad arrangement region Re is formed so as to overlap with the active region Rb in a top view of the semiconductor chip 10 seen from the normal direction.

[0035] In this embodiment, the area enclosed by the two-dot chain line in the drawing is the connection area Rc, the area inside the connection area Rc is the active area Rb, and the area outside the connection area Rc is the peripheral area Rd. Also, the area enclosed by the one-dot chain line in the drawing is the pad arrangement area Re.

[0036] Furthermore, a temperature sensor area 13 in which a temperature sensor is formed is provided within the pad arrangement area Re that overlaps with the active area Rb of the semiconductor chip 10, so that the temperature rise caused by the semiconductor element can be grasped based on the temperature detection by the temperature sensor.

[0037] The pad arrangement region Re is provided with a plurality of pads 12a to 12e. In this embodiment, the pad arrangement region Re is provided with, from the left side of the drawing, a cathode pad 12a, an anode pad 12b, a gate pad 12c, a first sense pad 12d, and a second sense pad 12e. These are electrically connected to the respective parts of the vertical MOSFET provided in the active region Rb and the respective parts of the temperature sensor provided in the temperature sensor region 13. These pads 12a to 12e are connected to the connection portion 33b, thereby enabling electrical connection to the outside via the lead-out portion provided in the connection portion 33b.

[0038] The semiconductor chip 10 has a cross-sectional configuration shown in FIGS. 3 and 4, and a vertical MOSFET is formed in the active region Rb.

[0039] The semiconductor chip 10 has n-type semiconductor layers made of semiconductor materials such as Si or SiC. + A type substrate 101 is used, and n +On the main surface of the substrate 101, n + The n-type substrate 101 has a lower impurity concentration than the n-type substrate 101. - A low concentration layer 102 is epitaxially grown.

[0040] [Configuration of active region Rb] As shown in Figures 3 and 4, in the active region Rb, n - The low concentration layer 102 contains n + At a position away from the mold substrate 101, JFET sections 102a are formed in a stripe pattern with one direction as the longitudinal direction. - The low concentration layer 102 may have the same impurity concentration. - By making the impurity concentration of the low concentration type layer 102 higher than that of other portions, a lower on-resistance can be achieved.

[0041] P-type first deep layers 103 are formed between the JFET sections 102a, and the first deep layers 103 are also arranged in stripes with one direction as the longitudinal direction. The JFET sections 102a and the first deep layers 103 have the same thickness.

[0042] Moreover, on the JFET section 102a and the first deep layer 103, a current spreading layer 104 formed to be wide with its longitudinal direction intersecting the longitudinal direction of these layers, and a second deep layer 105 formed to be narrower than the current spreading layer 104 are alternately and repeatedly arranged. The second deep layer 105 is connected to the first deep layer 103. Furthermore, a p-type base region 106 is formed on the current spreading layer 104 and the second deep layer 105, and an n-type base region 106 is formed on the p-type base region 106. + type source region 107 and p + A contact region 108 is formed. + The p-type source region 107 is formed on a portion of the p-type base region 106 that corresponds to the current diffusion layer 104. + The p-type contact region 108 is formed on a portion of the p-type base region 106 that corresponds to the second deep layer 105.

[0043] p-type base region 106 and n + A gate trench 109 is formed through the p-type source region 107 and reaches the current spreading layer 104. The p-type base region 106 and the n-type base region 107 are in contact with the side surfaces of the gate trench 109. + 3 is a cross-sectional view of a gate trench 109. The gate trench 109 is formed in a linear layout with the width direction being the left-right direction of the paper surface of FIG. 3, the length direction being the direction normal to the paper surface, and the depth direction being the up-down direction of the paper surface. Although only two gate trenches 109 are shown in FIG. 3, multiple gate trenches 109 are arranged at equal intervals in the left-right direction of the paper surface, and are arranged so as to be sandwiched between second deep layers 105, forming a stripe pattern.

[0044] Furthermore, the portion of the p-type base region 106 located on the side of the gate trench 109 becomes n-type when the vertical MOSFET is in operation. + The gate trench 109 has a channel region connecting the source region 107 and the current spreading layer 104. A gate insulating film 110 is formed on the inner wall surface of the gate trench 109, including the channel region. A gate electrode 111 made of doped poly-Si is formed on the surface of the gate insulating film 110, and the gate insulating film 110 and the gate electrode 111 are buried in the gate trench 109. This forms a trench gate structure.

[0045] 4, the trench gate structure extends in the left-right direction of the paper surface of FIG. 2, and as shown in FIG. 3, a plurality of trench gate structures are arranged in the up-down direction of the paper surface of FIG. 2. Although not shown, the trench gate structure is formed so as to extend outward beyond the active region Rb in the left-right direction of the paper surface of FIG. 2. Also, n + The n-type source region 107 is formed. +The type source region 107 is formed in the active region Rb and not outside of it, so that a channel region is formed only within the active region Rb.

[0046] n + Type source region 107 and p + An interlayer insulating film 112 is formed on the surface of the contact region 108 and the trench gate structure. In the active region Rb, a source electrode 113 corresponding to a surface electrode is formed on the interlayer insulating film 112. The source electrode 113 is formed by patterning a lower-layer wiring electrode made of a first-layer wiring electrode material, and the upper-layer wiring electrode made of a second-layer wiring electrode material is removed, resulting in a single-layer wiring structure.

[0047] In the interlayer insulating film 112, n + Type source region 107 and p + A contact hole 112a is formed at a position corresponding to the type contact region 108. As a result, as shown in FIG. 3, the source electrode 113 is connected to the n-type contact region 108 through the contact hole 112a. + Type source region 107 and p + It is in electrical contact with the mold contact region 108 .

[0048] Also, n + The back side of the substrate 101, that is, the surface opposite to the side on which the source electrode 113 is formed, is provided with an n-type + A drain electrode 114 corresponding to a backside electrode electrically connected to the mold substrate 101 is formed. With this structure, an n-channel type inversion trench gate vertical MOSFET is formed, and an active region Rb is formed by arranging multiple vertical MOSFET cells. As shown in FIG. 3, the surface of the semiconductor chip 10 is covered with a passivation film 115, and a portion of the passivation film 115 corresponding to the source electrode 113 is removed to form an opening. The portion of the passivation film 115 corresponding to the source electrode 113 where the opening is made is the internal region Ra, and the exposed portion of the source electrode 113 becomes the source pad 11.

[0049] Furthermore, as shown in FIG. 4, the portion of the active region Rb overlapping with the pad placement region Re has a configuration generally similar to that of the portion of the active region Rb not overlapping with the pad placement region Re. However, in the portion of the active region Rb overlapping with the pad placement region Re, an isolation insulating film 116 is disposed on the surface of the source electrode 113, and the pads 12a to 12e are formed on this isolation insulating film 116. While FIG. 4 shows a cross section of the portion where the gate pad 12c is disposed, the other pads 12a, 12b, 12d, and 12e are also formed on the source electrode 113 via the isolation insulating film 116. The pads 12a to 12e are formed by patterning upper-layer wiring electrodes, which are second-layer wiring electrodes. Therefore, as shown in FIG. 2B, the portion of the active region Rb overlapping with the pad placement region Re has a two-layer wiring electrode structure in which the source electrode 113 and the pads 12a to 12e are stacked.

[0050] Furthermore, portions of the passivation film 115 corresponding to the pads 12a to 12e provided in the pad arrangement region Re are also removed to form openings, allowing the connection portions 33b to be connected to the pads 12a to 12e.

[0051] In addition, in the temperature sensor region 13 arranged over the active region Rb, for example, a temperature sensor diode is formed as a temperature sensor. The temperature sensor diode is configured, for example, by forming multiple stages of PN diodes by ion-implanting p-type impurities or n-type impurities into polysilicon. The cathode of the temperature sensor diode is connected to the cathode pad 12a, and the anode is connected to the anode pad 12b, so that an electrical signal corresponding to the temperature of the semiconductor chip 10 is output.

[0052] The other pads 12c to 12e provided in the pad arrangement region Re are electrically connected to the respective components of the vertical MOSFET. The gate pad 12c is electrically connected to the gate electrode 111 via a gate wiring layer 120 (described later) that constitutes a gate liner. This allows a gate voltage to be applied to the gate electrode 111 through the gate pad 12c. The gate wiring layer 120 is formed, for example, in the connecting region Rc, i.e., near the outer edge of the semiconductor chip 10, in a rectangular frame shape that surrounds the active region Rb, and is routed to the vicinity of the gate pad 12c. The first sense pad 12d and the second sense pad 12e are connected to the source electrode 113 of the vertical MOSFET. Specifically, most of the vertical MOSFETs formed as multiple cells in the active region Rb are main cells that supply current to a load such as a motor through their source and drain, but some are sense cells that measure the current flowing through the main cells. The first sense pad 12d is connected to the source electrode 113 on the sense cell side and outputs the current flowing between the source and drain of the vertical MOSFET on the sense cell side to the outside, thereby enabling measurement of the current flowing through the main cell. The second sense pad 12e is connected to the source electrode 113 on the main cell side and outputs the source potential to the outside through the second sense pad 12e.

[0053] [Configuration of the connecting region Rc] As shown in FIG. 3, even in the connecting region Rc, up to a position near the outer peripheral region Rd, n - The JFET section 102a and the first deep layer 103 are formed on the low-concentration layer 102. However, the current diffusion layer 104 is not formed on these, and only the second deep layer 105 is formed. In addition, a trench gate structure is not formed, and the p-type base region 106 and the p-type + Only the mold contact region 108 is formed.

[0054] In addition, the p-type base region 106 and the p +A gate lead-out portion 111a made of doped polysilicon and led out from the gate electrode 111 is formed on a gate insulating film 110 formed on the contact region 108. An interlayer insulating film 112 is formed to cover the gate lead-out portion 111a, and a gate wiring layer 120 is further formed on the interlayer insulating film 112. This gate wiring layer 120 constitutes a gate liner and is routed in a rectangular frame shape so as to surround the active region Rb, for example, and is connected to a gate pad 12c. A contact hole 112b is formed in the interlayer insulating film 112 at a position corresponding to the gate wiring layer 120, and the gate wiring layer 120 and the gate lead-out portion 111a are electrically connected through the contact hole 112b.

[0055] Furthermore, a hole extracting layer 130 is formed on the interlayer insulating film 112, closer to the outer periphery region Rd than the gate wiring layer 120. A contact hole 112c is formed in the interlayer insulating film 112 at a position corresponding to the hole extracting layer 130, and the hole extracting layer 130 is connected to p + It is electrically connected to the mold contact region 108 .

[0056] The gate wiring layer 120 and the hole extraction layer 130 formed in the connecting region Rc are also configured by patterning a lower-layer wiring electrode, which is the first-layer wiring electrode, and an upper-layer wiring electrode, which is the second-layer wiring electrode, as shown in Figures 2B and 3. In this embodiment, the gate wiring layer 120 and the hole extraction layer 130 have a two-layer wiring electrode structure consisting of a lower-layer wiring electrode and an upper-layer wiring electrode.

[0057] In order to electrically isolate the pads 12a to 12e from the source electrode 113, the isolation insulating film 116 is formed between the lower-layer wiring electrode and the upper-layer wiring electrode. Therefore, with respect to the gate wiring layer 120 and the hole extracting layer 130, the isolation insulating film 116 formed between the lower-layer wiring electrode and the upper-layer wiring electrode is removed so that the lower-layer wiring electrode and the upper-layer wiring electrode are electrically connected. In this way, by forming the gate wiring layer 120 and the hole extracting layer 130 into a two-layer wiring electrode structure, it is possible to reduce wiring resistance.

[0058] In a cross section different from that of FIG. 3 or FIG. 4, the gate wiring layer 120 is connected to the gate pad 12c, and the hole extracting layer 130 is connected to a portion at ground potential, such as the second sense pad 12e.

[0059] [Configuration of outer peripheral region Rd] In the peripheral region Rd, the p-type base region 106 and the second deep layer 105 are removed to form a recess 140. A plurality of p-type guard rings 150 are arranged at the bottom of this recess 140 so as to surround the active region Rb. By providing the p-type guard rings 150, the equipotential lines are extended and terminated further outside the active region Rb, thereby mitigating electric field concentration and ensuring a sufficient breakdown voltage in the peripheral region Rd.

[0060] The entire peripheral region Rd is covered with a passivation film 115 to protect the surface. In this manner, a power module including the semiconductor chip 10 corresponding to the semiconductor device of this embodiment is configured.

[0061] This power module operates, for example, by applying a voltage of about 10 V to the drain electrode 114 via the metal layer 23, grounding the source electrode 113 via the connection portion 33a, and applying a predetermined voltage to the gate electrode 111 via the connection portion 33b. That is, when a gate voltage is applied to the gate electrode 111, a channel region is formed in the portion of the p-type base region 106 that contacts the trench gate structure. This turns on the vertical MOSFET, causing a current to flow between the source and drain.

[0062] Even when a high voltage is applied to the drain electrode 114, the first deep layer 103 is fixed to the source potential through the second deep layer 105 and the p-type base region 106, preventing the equipotential lines from rising up to the trench gate structure. Furthermore, in the peripheral region Rd, a peripheral breakdown voltage structure such as the p-type guard ring 150 is provided, which guides the equipotential lines further outward, thereby mitigating electric field concentration. This makes it possible to realize a vertical MOSFET with a high breakdown voltage.

[0063] When the vertical MOSFET is operated as described above, the semiconductor chip 10 becomes hot, and if the thickness of each portion of the semiconductor chip 10 formed by the wiring electrodes is large, warpage will increase at high temperatures. However, in this embodiment, the thickness of the source pad 11, which is the pad formed by opening the passivation film 115 with the largest area, i.e., the source electrode 113, is made thin. This makes it possible to suppress the increase in warpage at high temperatures.

[0064] Specifically, the source electrode 113, gate wiring layer 120, hole extraction layer 130, and pads 12a-12e are configured by patterning a lower-layer wiring electrode, which is the first-layer wiring electrode, and an upper-layer wiring electrode, which is the second-layer wiring electrode. In this embodiment, the gate wiring layer 120 and hole extraction layer 130 have a two-layer wiring electrode structure consisting of a lower-layer wiring electrode and an upper-layer wiring electrode, while the source electrode 113 has a single-layer wiring electrode structure in which the upper-layer wiring electrode is removed and the lower-layer wiring electrode remains. Furthermore, the pads 12a-12e have a single-layer wiring electrode structure consisting of an upper-layer wiring electrode.

[0065] In this way, the source electrode 113, which has the largest area among the portions made of wiring electrode material on the front surface side of the semiconductor chip 10, has a single-layer wiring structure. That is, even though a two-layer wiring electrode structure in which the pads 12a to 12e are stacked on the source electrode 113 is used at the positions where the pads 12a to 12e are arranged, a single-layer wiring electrode structure is used at the position where only the source electrode 113 is arranged, rather than a stacked structure. This makes it possible to suppress an increase in warpage of the semiconductor chip 10 at high temperatures.

[0066] Therefore, by forming a semiconductor element below the pad arrangement region Re, a wide area of ​​the semiconductor chip 10 can be made into the active region Rb, thereby reducing the on-resistance and suppressing an increase in warpage of the semiconductor chip 10. By suppressing an increase in warpage of the semiconductor chip 10, it is possible to suppress deterioration of the semiconductor element characteristics due to warpage and further reduce the on-resistance. Furthermore, because heat can also be dissipated through the connection portions 33b, even if the active region Rb is laid out so as to overlap the pad arrangement region Re, heat generated in that area can also be dissipated through the connection portions 33b.

[0067] The structure of this embodiment was actually fabricated, and changes in on-resistance were examined for the structure of this embodiment and a comparative example in which the source electrode 113 also has a two-layer wiring electrode structure. The structure fabricated in this embodiment is the structure shown in FIGS. 3 and 4. The comparative example has the structure shown in FIGS. 5 and 6. That is, as shown in FIGS. 5 and 6, not only the pads 12a to 12e but also the source electrode 113, gate wiring layer 120, and hole extraction layer 130 all have a two-layer wiring electrode structure.

[0068] FIG. 7 shows the evaluation results of the on-resistance. Specifically, while applying 10 V to the drain electrode 114, the source electrode 113 was grounded, and the gate voltage was adjusted so that a predetermined current value flowed between the source and drain. The on-resistance was measured for each case. Here, vertical MOSFETs with four different characteristics were fabricated for each case. As a result, regardless of the characteristics of the vertical MOSFET, the on-resistance was reduced by approximately 5% when the structure of this embodiment was used compared to when the source electrode 113 also had a two-layer wiring electrode structure. This evaluation result also shows that the structure of this embodiment achieves a further reduction in on-resistance. This is presumably due to the following reason. That is, when a two-layer wiring electrode structure is used, an oxide layer is formed on the surface of the lower-layer wiring electrode, which increases the contact resistance between the lower-layer wiring electrode and the upper-layer wiring electrode, thereby increasing the on-resistance. In contrast, with the structure of this embodiment, even if an oxide layer is formed on the source electrode 113 when the isolation insulating film 116 is formed, as described below, the oxide layer can be removed when the upper-layer wiring electrode formed thereon is removed. It is believed that this reduces the contact resistance of the source electrode 113, thereby reducing the on-resistance.

[0069] Next, a method for manufacturing the semiconductor chip 10 configured as described above, i.e., a semiconductor device, will be described. However, in the method for manufacturing a semiconductor device, the steps of forming the semiconductor elements, the interlayer insulating film 112, and the contact holes 112a-112c may be performed by any known method. Therefore, only the steps subsequent to the step of forming the contact holes 112a-112c will be described.

[0070] 8, after forming a semiconductor element, the steps of forming an interlayer insulating film 112 and forming contact holes 112a to 112c in the interlayer insulating film 112 are performed. Then, by performing the steps shown thereafter, the steps of forming a source electrode 113, a gate wiring layer 120, a gate lead-out portion 111a, and pads 12a to 12e are performed.

[0071] Specifically, lower-layer wiring electrodes are formed on the interlayer insulating film 112, including inside the contact holes 112a to 112e. For example, a wiring electrode material, primarily AlSi, is formed by sputtering as the lower-layer wiring electrodes. In this case, rather than forming the wiring electrode material directly on the semiconductor layer, it is preferable to form a barrier metal layer as an underlayer by sputtering a Ti / TiN laminated structure, for example, before forming the lower-layer wiring electrodes. Next, a resist is applied to the lower-layer wiring electrodes, followed by exposure and development processes to form a resist mask. Then, the lower-layer wiring electrodes are wet-etched using the resist mask, and if an underlayer is formed, the underlayer is dry-etched. After that, the resist mask is peeled off and washed, followed by sintering. This completes the patterning of the lower-layer wiring electrodes, forming the source electrode 113, and also forming the gate wiring layer 120 and the portion of the hole extraction layer 130 that is composed of the lower-layer wiring electrodes.

[0072] Next, the isolation insulating film 116 is formed. For example, a silicon oxide film or silicon nitride film such as USG (Undoped Silicate Glass) is deposited as an insulating material for the isolation insulating film 116. The use of a silicon oxide film or silicon nitride film allows for accurate insulation between the lower-layer wiring electrodes and the upper-layer wiring electrodes. The use of a silicon nitride film also has the effect of suppressing oxidation of the portions of the lower-layer wiring electrodes covered with the silicon nitride film. A resist is applied to the isolation insulating film 116, and then an exposure and development process is performed to form a resist mask. The isolation insulating film 116 is then patterned by dry etching using the resist mask. At this time, the isolation insulating film 116 is left in the regions where the pads 12a to 12e are to be formed, but is not left on the surfaces of the source electrodes 113 or the surfaces of the portions of the gate wiring layer 120 and the hole extraction layer 130 that are formed by the lower-layer wiring electrodes. The resist mask is then removed and washed to form the isolation insulating film 116 with a desired pattern.

[0073] Furthermore, an upper-layer wiring electrode is formed so as to cover portions of the lower-layer wiring electrode, such as the source electrode 113, including the isolation insulating film 116. For example, a wiring electrode material such as AlSi is formed by sputtering as the upper-layer wiring electrode. In this case, rather than directly forming the wiring electrode material, it is preferable to form a barrier metal layer as an underlayer by sputtering a layered structure such as Ti / TiN, and then form the upper-layer wiring electrode. Next, a resist is applied to the upper-layer wiring electrode, and then an exposure and development process is performed to form a resist mask. Then, the upper-layer wiring electrode is wet-etched using the resist mask, and if an underlayer is formed, the underlayer is dry-etched. After that, the resist mask is peeled off and washed, followed by sintering. This completes the patterning of the upper-layer wiring electrode, forming the gate wiring layer 120 and the portions of the hole extraction layer 130 formed by the upper-layer wiring electrode, and forming the pads 12a to 12e.

[0074] Regarding the patterning of the upper-layer wiring electrode, removal of the lower-layer wiring electrode can be prevented by controlling the etching time when removing the upper-layer wiring electrode, but if a barrier metal layer is formed as an underlying layer, it can be used as an etching stopper. Also, an oxide layer may be formed on the surface of the source electrode 113 when the isolation insulating film 116 is formed, but this oxide layer can be removed at the same time when the upper-layer wiring electrode is removed. This reduces the contact resistance of the source electrode 113 and makes it possible to reduce the on-resistance.

[0075] After this, the semiconductor chip 10 can be manufactured through a process of forming a passivation film 115 made of, for example, PIQ (Polyimideisoindoloquinazolinedione), a process of forming a drain electrode 114 as a back surface electrode, and a process of dividing into chips by dicing.

[0076] (Second embodiment) The second embodiment will be described. This embodiment is different from the first embodiment in that the region where the two-layer wiring electrode structure is used is changed, and the rest is the same as the first embodiment, so only the parts that are different from the first embodiment will be described.

[0077] In this embodiment, the two-layer wiring electrode structure is used only at the positions of the pads 12a to 12e in the pad arrangement region Re, and the single-layer wiring electrode structure is used in all other regions, as shown in Fig. 9. Specifically, in this embodiment, the single-layer wiring electrode structure is used not only for the source electrode 113 in the active region Rb at a position that does not overlap with the pad arrangement region Re, but also for the gate wiring layer 120 and the hole extraction layer 130, as shown in Fig. 10.

[0078] With this structure, the gate wiring layer 120 and the hole extraction layer 130 can also be configured to be thin, making it possible to further suppress warpage at high temperatures. Furthermore, when the gate wiring layer 120 and the hole extraction layer 130 have a two-layer wiring electrode structure, as in the first embodiment, it is necessary to remove the isolation insulating film 116 formed between the lower-layer wiring electrode and the upper-layer wiring electrode. However, when the gate wiring layer 120 and the hole extraction layer 130 are configured using only the lower-layer wiring electrode, it is not necessary to remove the isolation insulating film 116 except for the portion of the gate wiring layer 120 connected to the gate pad 12c and the portion of the hole extraction layer 130 connected to the second sense pad 12e. Therefore, when the isolation insulating film 116 is configured using a silicon nitride film, oxidation of the gate wiring layer 120 and the hole extraction layer 130 can be further suppressed.

[0079] (Third embodiment) The third embodiment will be described. This embodiment is different from the first and second embodiments in that the ratio of the area having a two-layer wiring electrode structure is set, but other aspects are the same as the first and second embodiments, so only the differences from the first and second embodiments will be described.

[0080] As described above, in the first embodiment, the region where the pads 12a to 12e are arranged, the gate wiring layer 120, and the hole extraction layer 130 form a two-layer wiring electrode structure. In the second embodiment, the region where the pads 12a to 12e are arranged also forms a two-layer wiring electrode structure. The area of ​​the region with this two-layer wiring electrode structure is preferably 30% or less of the area of ​​the active region Rb. Specifically, the larger the region with the two-layer wiring electrode structure, the greater the warpage of the semiconductor chip 10 at high temperatures. Furthermore, the area of ​​the active region Rb is the area of ​​the heat-generating portion. There is a correlation between the area of ​​the active region Rb and the area of ​​the region with the two-layer wiring electrode structure. When the ratio of the area of ​​the region with the two-layer wiring electrode structure to the area of ​​the active region Rb is 30% or less, the increase in warpage of the semiconductor chip 10 is kept within a more preferable range.

[0081] Therefore, by setting the layout of each area so that the ratio of the area of ​​the area with the two-layer wiring electrode structure to the area of ​​the active area Rb is 30% or less, it is possible to further suppress an increase in warpage of the semiconductor chip 10.

[0082] (Fourth embodiment) The fourth embodiment will be described. This embodiment defines the pad layout in the semiconductor chip 10 in comparison with the first to third embodiments, and is otherwise similar to the first to third embodiments, so only the differences from the first to third embodiments will be described.

[0083] 11, in this embodiment, the layout of the pads 12a to 12e formed on the semiconductor chip 10 and the internal region Ra constituting the source pad 11 are arranged to be line-symmetrical about a straight line L. The straight line L is one of the center lines of the semiconductor chip 10 that passes through the center of the internal region Ra constituting the rectangular source pad 11. With this straight line L as the center, the source pad 11 itself is line-symmetrical, and the pads 12a to 12e are also line-symmetrical.

[0084] With this configuration, the warp of the semiconductor chip 10 becomes uniform around the straight line L. This makes it easier to predict the warp, facilitating design that takes the warp into consideration.

[0085] (Fifth embodiment) The fifth embodiment will be described. This embodiment is different from the first to fourth embodiments in that it defines the number of pads on the semiconductor chip 10, and is otherwise similar to the first to fourth embodiments, so only the differences from the first to fourth embodiments will be described.

[0086] As shown in FIG. 12, in this embodiment, in addition to the internal region Ra that constitutes the source pad 11, a gate pad 12c is provided, but other pads 12a, 12b, 12d, and 12e are not provided, and the number of pads in the two-layer wiring electrode structure is only one.

[0087] The warpage of the semiconductor chip 10 increases in proportion to the area of ​​the region having the two-layer wiring electrode structure. For this reason, it is preferable to reduce the number of pads in the two-layer wiring electrode structure, preferably to five or less. Furthermore, although the number of pads in the two-layer wiring electrode structure is five in the first to fourth embodiments, it is more preferable to reduce the number of pads. For this reason, by reducing the number of pads to less than five, particularly to the minimum of one, as in this embodiment, it is possible to further suppress the increase in warpage of the semiconductor chip 10.

[0088] In this embodiment, gate pad 12c is arranged along the center of one side of the rectangular semiconductor chip 10, and an internal region Ra constituting source pad 11 surrounding it is configured as a concave shape that opens downward in the plane of the drawing. As in the fourth embodiment, source pad 11 itself is line-symmetrical, and pads 12a to 12e are line-symmetrical with respect to line L. However, this is merely an example of the layout of semiconductor chip 10 when the number of pads in the two-layer wiring electrode structure is five or less, and other layouts may be used as long as the number of pads satisfies the condition.

[0089] (Other embodiments) Although the present disclosure has been described based on the above-described embodiment, it is not limited to the embodiment and encompasses various modifications and modifications within the equivalent range. In addition, various combinations and forms, as well as other combinations and forms including only one element, more than one element, or less than one element, are also within the scope and spirit of the present disclosure.

[0090] For example, in each of the above embodiments, a vertical MOSFET is given as an example of a semiconductor element provided in the active region Rb, but other elements such as a vertical IGBT or a diode may also be used, or a combination of multiple types of elements may also be provided.

[0091] Although an example of the semiconductor chip 10 constituting the semiconductor device has been given, the semiconductor device may have a structure different from that shown in Fig. 3A. That is, in addition to surface electrodes such as the source electrode 113 provided in the active region Rb, the semiconductor device may have pads 12a to 12e arranged in the pad arrangement region Re, and the pads 12a to 12e may have a two-layer wiring electrode structure while the surface electrodes have a single-layer wiring electrode structure.

[0092] Furthermore, in each of the above embodiments, the case where the entire pad placement area Re overlaps with the active area Rb has been described, but the structure may also be such that at least a portion of the pad placement area Re overlaps with the active area Rb, rather than the entire area.

[0093] In the above embodiments, the one-layer wiring electrode structure and the two-layer wiring electrode structure refer to the number of layers of wiring electrode material such as AlSi, and do not include metal layers that are not wiring electrode materials, such as barrier metal layers. [Explanation of symbols]

[0094] 10...semiconductor chip, 11...source pad, 12a to 12e...pad, 112...interlayer insulating film, 113...source electrode, 116...isolation insulating film, 120...gate wiring layer, Ra...internal region, Rb...active region, Rc...connection region, Rd...peripheral region, Re...pad arrangement region

Claims

1. A semiconductor device composed of a semiconductor chip (10), an active region (Ra) in which a semiconductor element is formed and in which a surface electrode (113) made of a wiring electrode material is arranged and connected to the semiconductor element on one surface side of the semiconductor chip; a pad arrangement region (Re) provided so as to overlap the active region in a normal direction to one surface of the semiconductor chip, and in which pads (12a to 12e) made of the wiring electrode material are arranged; In the region where the pad arrangement region and the active region overlap, the pad is arranged on the surface electrode via an isolation insulating film (116), thereby forming a two-layer wiring electrode structure in which two layers of the wiring electrode material are stacked, A wiring layer (130) electrically connected to a contact region (108) included in the semiconductor element is provided on the outside of the two-layer wiring electrode structure, The semiconductor device, wherein the wiring layer has a single-layer electrode structure made of one layer of the wiring electrode material.

2. A semiconductor device composed of a semiconductor chip (10), an active region (Ra) in which a semiconductor element is formed and in which a surface electrode (113) made of a wiring electrode material is arranged and connected to the semiconductor element on one surface side of the semiconductor chip; a pad arrangement region (Re) provided so as to overlap the active region in a normal direction to one surface of the semiconductor chip, and in which pads (12a to 12e) made of the wiring electrode material are arranged; In the region where the pad arrangement region and the active region overlap, the pad is arranged on the surface electrode via an isolation insulating film (116), thereby forming a two-layer wiring electrode structure in which two layers of the wiring electrode material are stacked, A wiring layer (130) is provided outside the active region and electrically connected to a contact region (108) included in the semiconductor element; The semiconductor device, wherein the wiring layer has a single-layer electrode structure made of one layer of the wiring electrode material.

3. 3. The semiconductor device according to claim 1, wherein the area of ​​the region having the two-layer wiring electrode structure is 30% or less of the area of ​​the active region.

4. 4. The semiconductor device according to claim 1, wherein the surface electrodes and the pads are laid out symmetrically with respect to a straight line (L) that is a center line of the semiconductor chip and passes through the center of the surface electrodes.

5. 5. The semiconductor device according to claim 1, wherein the number of said pads is five or less.

6. 6. The semiconductor device according to claim 1, wherein said isolation insulating film is made of a silicon oxide film.

7. 6. The semiconductor device according to claim 1, wherein said isolation insulating film is made of a silicon nitride film.

8. 8. The semiconductor device according to claim 1, wherein said wiring electrode material is made of AlSi.

9. 9. The semiconductor device according to claim 1, wherein the semiconductor chip is formed by forming the semiconductor element on a semiconductor substrate made of silicon carbide.

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