Semiconductor device

Abstract

To provide a sense amplifier, a semiconductor device, and an operating method thereof that are less susceptible to an influence of variations in transistor characteristics.SOLUTION: An amplifier circuit 62 included in a sense amplifier SA1 has a first circuit and a second circuit. The first circuit and the second circuit each have an inverter, a first transistor, a second transistor, and a capacitor. A first terminal of the capacitor is connected to a first bit line, and a second terminal thereof is connected to an input terminal of the inverter. The first transistor functions as a switch that connects or disconnects an input terminal and an output terminal of the inverter, and the second transistor functions as a switch that connects or disconnects the output terminal of the inverter and the second bit line. The first circuit and the second circuit are in a relation in which the first bit line and the second bit line are connected inversely. The first circuit and the second circuit are initialized by a potential obtained when the input terminal and the output terminal of the inverter are brought into a conductive state.SELECTED DRAWING: Figure 4

Description

[Technical Field]

[0001] One embodiment of the present invention relates to a sense amplifier or a semiconductor device. This relates to the sense amplifier used when reading data from a memory cell.

[0002] In this specification and the like, a semiconductor device is a device that can function by utilizing semiconductor characteristics. This refers to a general term for memory devices, display devices, light-emitting devices, electro-optical devices, power storage devices, semiconductor circuits, and The electronic devices may include semiconductor devices.

[0003] It should be noted that one embodiment of the present invention is not limited to the above technical fields. The technical field relates to products, methods, or manufacturing methods. is a process, machine, manufacture, or composition of matter. This concerns the [Background technology]

[0004] DRAM (Dynamic Random Access Memory) is a typical DRAM is widely used as a memory. In principle, DRAM can be written to unlimitedly. The write and read speeds are high, and the small number of cell elements makes it easy to achieve high integration. These features make it suitable for use as a large-capacity memory in many electronic devices.

[0005] Generally, a memory cell in a DRAM (hereinafter referred to as a DRAM cell) consists of one transistor. It consists of a transistor (1T) and one capacitance element (1C), and is electrically connected to the bit line and word line. The gate of the transistor is electrically connected to the word line, and the has a function as a switch that connects or disconnects the bit line and the capacitance element. DRAM is a memory that stores data by holding an electric charge in a capacitance element. Data stored in the cells is written and read via bit lines and transistors. The procedure will be carried out.

[0006] When reading data stored in a DRAM cell, the transistor connects the bit line and the capacitor However, due to the capacitance of the bit line, The potential of the bit line changes slightly due to the charge. The sense amplifier electrically connects the bit line connected to the DRAM cell, amplifying the slightly changing potential of the bit line and storing it in the DRAM cell. The data can be read.

[0007] On the other hand, transistors that have metal oxide in the channel formation region ("oxide semiconductor transistors") A DRAM that uses a silicon-doped silicon transistor (also called an "OS transistor") in a DRAM cell has been proposed. (For example, Patent Documents 1 and 2, and Non-Patent Document 1) OS transistors have Leak current (off current) is extremely small, resulting in a long refresh period and low power consumption. In this specification, the OS transistor is applied to a DRAM cell. The DRAM used in this technology is referred to as "oxide semiconductor DRAM" or "DOSRAM (registered trademark)." Dynamic Oxide Semiconductor RAM (DOSRAM) We will do so.

[0008] In recent years, with the trend toward smaller and lighter electronic devices, transistors and capacitors have become increasingly difficult to manufacture. There is an increasing demand for highly integrated semiconductor devices, using methods such as multi-layering and forming different layers. do. [Prior art documents] [Patent documents]

[0009] [Patent Document 1] Japanese Patent Application Laid-Open No. 2012-256820 [Patent Document 2] International Publication No. 2015 / 155635 [Non-patent literature]

[0010] [Non-Patent Document 1] T. Onuki et al.,”DRAM with Storage Capacitance of 3.9fF Using CAAC-OS Transistor with L of 60nm and Having More Than 1-h Retention Characteristics,”Ext.Abstr.SSDM,2014,pp.430-431. Summary of the Invention [Problem to be solved by the invention]

[0011] In memory devices such as DRAM and DOSRAM, the data stored in the memory cells is read. The sense amplifier used to read the data is the charge stored in the capacitor of the memory cell. The sense amplifier has the function of amplifying the potential of the bit line, which changes slightly depending on the Variations in transistor characteristics affect the accuracy of the sense amplifier, and if the variations in characteristics are large, This poses a problem in that minute changes in the bit line potential cannot be detected.

[0012] One aspect of the present invention provides a sense amplifier that is less susceptible to variations in transistor characteristics. Another object of one embodiment of the present invention is to reduce variations in characteristics of transistors. Another object of the present invention is to provide a semiconductor device that is less susceptible to such influences. provides a sense amplifier operation method that is less susceptible to variations in transistor characteristics Another object of one embodiment of the present invention is to reduce the influence of variations in characteristics of transistors. Another object of the present invention is to provide a method for operating a semiconductor device that is less susceptible to noise. One aspect is directed to providing a novel semiconductor device or a method of operating a novel semiconductor device. This is one of the topics.

[0013] It should be noted that one embodiment of the present invention does not necessarily have to solve all of the above problems, but at least It is enough if it can solve one problem. Also, the description of the problem above may not be sufficient if other problems exist. Other issues than these are not covered by the description, claims, drawings, etc. This becomes clear from the description, claims, drawings, etc. It is possible to extract issues other than these. [Means for solving the problem]

[0014] One aspect of the present invention is a semiconductor device including an inverter, a first transistor, a second transistor, and a capacitor. The semiconductor device has an element, an input section, and an output section. The semiconductor device has a first control line and , and the second control line, and the first terminal of the capacitive element is electrically connected to the input section. The second terminal of the capacitance element is electrically connected to the input terminal of the inverter. The resistor acts as a switch that connects the input and output terminals of the inverter to conduction or non-conduction. The second transistor serves to connect the output terminal of the inverter to the output section. The gate of the first transistor functions as a switch that turns off the first transistor. The gate of the second transistor is electrically connected to the control line, and the gate of the second transistor is electrically connected to the second control line. It is characterized by being continued.

[0015] Furthermore, one aspect of the present invention is a transistor including an inverter, a first transistor, a second transistor, and The semiconductor device has a first control line, an input section, and an output section. and the control line of the inverter is electrically connected to the input terminal of the inverter. The first transistor connects the input terminal and the output terminal of the inverter to each other in a conductive or non-conductive state. The second transistor has a function as a switch that connects the output terminal of the inverter to the output section. The gate of the first transistor has a function as a switch that turns on or off the gate of the second transistor. The gate of the second transistor is electrically connected to a first control line, and the gate of the second transistor is electrically connected to a second control line. It is characterized by being electrically connected to a wire.

[0016] In the above-described embodiment, the semiconductor device has a function of performing an initialization operation. The first transistor is used to establish a conductive state between the input terminal and the output terminal of the inverter. The present invention is characterized by including the steps of:

[0017] In the above embodiment, the first transistor includes a metal oxide in a channel formation region. .

[0018] Another embodiment of the present invention is a sense amplifier including an amplifier circuit and a precharge circuit. The sense amplifier is electrically connected to the first wiring and the second wiring, and includes a precharge circuit. has a function of setting the first wiring and the second wiring to a first potential. The first circuit includes a first inverter and a second inverter. the second circuit has a second inductor, a second transistor, and a first capacitor; The second capacitor includes a first transistor, a second capacitor, a third transistor, a fourth transistor, and a second capacitor. The first terminal of the first capacitance element is electrically connected to the first wiring, and the second terminal of the first capacitance element is The first transistor is electrically connected to the input terminal of the first inverter. Functions as a switch that connects or disconnects the input and output terminals of the inverter. the second transistor is electrically connected between the output terminal of the first inverter and the second wiring; The first terminal of the second capacitor element has a function as a switch that turns on or off the second capacitor element. The second terminal of the second capacitance element is electrically connected to the wiring, and is connected to the input terminal of the second inverter. The third transistor is electrically connected to the input terminal and the output terminal of the second inverter. The fourth transistor has a function as a switch that turns on or off the second transistor. The inverter has a function as a switch that connects the output terminal of the inverter and the first wiring to or from a conductive state. It is characterized by its ability to

[0019] Another embodiment of the present invention is a sense amplifier including an amplifier circuit and a precharge circuit. The sense amplifier is electrically connected to the first wiring and the second wiring, and includes a precharge circuit. has a function of setting the first wiring and the second wiring to a first potential. The first circuit includes a first inverter and a second inverter. a first transistor, a first capacitance element, and a first conductor; The circuit includes a second inverter, a third transistor, a fourth transistor, and a second capacitor. The first terminal of the first capacitor element is electrically connected to the first wiring. the first inverter has a fifth transistor and a sixth transistor; The second terminal of the first capacitance element is connected to the fifth transistor and the sixth transistor via the first conductor. The first conductor is electrically connected to one or both gates of the transistors. has a function as an electrode of the first capacitor element, and the first transistor has a function as a first inverter. The input terminal and the output terminal of the inverter are connected or disconnected. The second transistor connects the output terminal of the first inverter and the second wiring in a conductive or non-conductive state. The first terminal of the second capacitor is electrically connected to the second wiring. The second inverter has a seventh transistor and an eighth transistor. The second terminal of the second capacitance element is connected to the seventh transistor and the third transistor through the second conductor. The second conductor is electrically connected to the gate of one or both of the eighth transistors. The capacitor functions as an electrode of the second capacitor, and the third transistor functions as an electrode of the second insulator. It has the function of a switch that connects or disconnects the input and output terminals of the inverter. The fourth transistor connects the output terminal of the second inverter and the first wiring in a conductive or non-conductive state. It is characterized by having a function as a switch that makes the device conductive.

[0020] Another aspect of the present invention is a sense amplifier having a first circuit and a second circuit. The sense amplifier is electrically connected to the first wiring and the second wiring, and the first circuit is The second circuit includes an inverter, a first transistor, and a second transistor. The first inverter has a second transistor, a third transistor, and a fourth transistor. The input terminal of the inverter is electrically connected to the first wiring, and the first transistor is It has the function of a switch that connects the input terminal and output terminal of the inverter to conduction or non-conduction. The second transistor connects the output terminal of the first inverter and the second wiring to each other. The input terminal of the second inverter is connected to the second wiring. The third transistor is electrically connected to the line and the input terminal and the output terminal of the second inverter. The fourth transistor has a function as a switch that turns on or off the first transistor. A switch that connects the output terminal of the second inverter and the first wiring to conduction or non-conduction. It is characterized by having a function.

[0021] In the above embodiment, the sense amplifier has a function of performing an initialization operation. uses a first transistor to conduct between the input terminal and the output terminal of the first inverter. and using a third transistor, and bringing the output terminal into a conductive state.

[0022] In the above embodiment, the sense amplifier performs initialization operations including the first to fourth operations. The first operation is to operate a first inverter using a first transistor. The second operation is to bring the input terminal and the output terminal of the transistor into a conductive state by using a third transistor. a third operation of bringing the input terminal and the output terminal of the second inverter into a conductive state, A second transistor is used to establish a conductive state between the output terminal of the first inverter and the second wiring. The fourth operation is to connect the output terminal of the second inverter to the output terminal of the third inverter using a fourth transistor. The second wiring is electrically connected to the first wiring.

[0023] Another aspect of the present invention is a sense amplifier having a first circuit and a second circuit. The sense amplifier is electrically connected to the first wiring and the second wiring, and the first circuit is An inverter, a first transistor, a second transistor, and a first capacitance element. , the second circuit includes a second inverter, a third transistor, a fourth transistor, A first terminal of the first capacitor is electrically connected to the first wiring. The second terminal of the first capacitance element is electrically connected to the input terminal of the first inverter. The first transistor connects the input terminal and the output terminal of the first inverter in a conductive or non-conductive state. The second transistor has a function as a switch for connecting the output terminal of the first inverter to the output terminal of the second inverter. The second capacitor has a function as a switch that connects the capacitor to the second wiring and disconnects the capacitor from the second wiring. A first terminal of the second capacitance element is electrically connected to the second wiring, and a second terminal of the second capacitance element is electrically connected to the first wiring. The third transistor is electrically connected to the input terminal of the second inverter. The input terminal and the output terminal of the inverter are electrically connected or disconnected. The fourth transistor connects the output terminal of the second inverter and the first wiring in a conductive or non-conductive state. The sense amplifier has a function as a switch that allows the first to fourth operations to be performed. The first operation includes performing an initialization operation using a first transistor. The second operation is to bring the input terminal and the output terminal of the first inverter into a conductive state. a transistor is used to establish a conductive state between the input terminal and the output terminal of the second inverter; The third operation is to connect the output terminal of the first inverter and the second wiring using the second transistor. The fourth operation is to use a fourth transistor to turn on the second inverter. and bringing the output terminal of the capacitor and the first wiring into a conductive state.

[0024] In the above embodiment, the first transistor and the third transistor are channel-type The composition region contains a metal oxide.

[0025] In the above embodiment, the first transistor, the third transistor, and the fifth transistor either the seventh transistor or the sixth transistor, Any one of the eight transistors includes a metal oxide in a channel formation region. [Effects of the Invention]

[0026] According to one aspect of the present invention, a sense amplifier that is less susceptible to the influence of variations in transistor characteristics is provided. Furthermore, according to one embodiment of the present invention, it is possible to reduce the influence of variations in characteristics of transistors. Furthermore, according to one embodiment of the present invention, a semiconductor device that is less susceptible to the influence of a transistor can be provided. It is possible to provide a sense amplifier operation method that is less susceptible to variations in transistor characteristics. Furthermore, according to one embodiment of the present invention, a semiconductor device that is less susceptible to variations in transistor characteristics can be obtained. A method of operating a conductor device can be provided.

[0027] The effects of one embodiment of the present invention are not limited to the effects listed above. An effect does not preclude the existence of other effects. Other effects may be affected by this section, as described below. The effects not mentioned in this section are effects that a person skilled in the art would understand by understanding the specification. Or it can be derived from the description in the drawings, etc., and can be extracted appropriately from these descriptions. It should be noted that one embodiment of the present invention has at least the above-listed effects and other effects. Therefore, one aspect of the present invention is to provide the above-listed However, there are cases where the effect is not significant. [Brief explanation of the drawings]

[0028] [Figure 1] 1A and 1B are a block diagram and a circuit diagram illustrating a configuration example of a semiconductor device. [Figure 2] FIG. 1 is a block diagram illustrating a configuration example of a semiconductor device. [Figure 3] FIG. 1 is a block diagram illustrating a configuration example of a semiconductor device. [Figure 4] FIG. 1 is a circuit diagram showing an example of the configuration of a memory cell and a sense amplifier. [Figure 5] FIG. 1 is a circuit diagram showing an example of the configuration of a memory cell and a sense amplifier. [Figure 6] FIG. 1 is a circuit diagram showing an example of the configuration of a memory cell and a sense amplifier. [Figure 7] FIG. 1 is a circuit diagram showing an example of the configuration of a memory cell and a sense amplifier. [Figure 8] FIG. 1 is a circuit diagram showing an example of the configuration of a memory cell and a sense amplifier. [Figure 9] FIG. 1 is a circuit diagram showing an example of the configuration of a memory cell and a sense amplifier. [Figure 10] FIG. 1 is a circuit diagram showing an example of the configuration of a memory cell and a sense amplifier. [Figure 11] FIG. 1 is a circuit diagram showing an example of the configuration of a memory cell and a sense amplifier. [Figure 12] FIG. 2 is a circuit diagram showing a configuration example of a sense amplifier and an amplifier circuit. [Figure 13] Timing chart. [Figure 14] Timing chart. [Figure 15] FIG. 1 is a circuit diagram showing an example of the configuration of a memory cell and a sense amplifier. [Figure 16] FIG. 1 is a circuit diagram showing an example of the configuration of a memory cell and a sense amplifier. [Figure 17] FIG. 1 is a circuit diagram showing an example of the configuration of a memory cell and a sense amplifier. [Figure 18] FIG. 1 is a circuit diagram showing an example of the configuration of a memory cell and a sense amplifier. [Figure 19] FIG. 2 is a circuit diagram showing a configuration example of a sense amplifier and an amplifier circuit. [Figure 20] Timing chart. [Figure 21] 1A and 1B are a top view and a cross-sectional view illustrating a semiconductor device. [Figure 22] 1 is a cross-sectional view illustrating a semiconductor device. [Figure 23] 1 is a cross-sectional view illustrating a semiconductor device. [Figure 24] 1 is a cross-sectional view illustrating a semiconductor device. [Figure 25] Schematic diagrams showing examples of electronic components. [Figure 26] 1A and 1B are schematic diagrams showing examples of electronic devices. [Figure 27] 1A and 1B are schematic diagrams showing examples of electronic devices. DETAILED DESCRIPTION OF THE INVENTION

[0029] Hereinafter, embodiments will be described with reference to the drawings. The present invention may be implemented in any form without departing from the spirit and scope of the present invention. It will be readily apparent to those skilled in the art that various modifications may be made to the design and details of the present invention. However, the present invention should not be construed as being limited to the description of the following embodiments.

[0030] In addition, the following embodiments can be combined as appropriate. When a plurality of configuration examples are shown in one embodiment, the configuration examples may be combined with each other as appropriate. It is possible to do this.

[0031] In the drawings attached to this specification, the components are classified by function and are shown as independent blocks. Although the block diagram is shown as a block, the actual components are not completely separated by function. It is difficult to achieve this, and one component may be involved in multiple functions.

[0032] In addition, in the drawings, etc., the size, thickness of layers, areas, etc. may be exaggerated for clarity. Therefore, the scale is not necessarily limited to the above. The drawings are only a schematic representation of ideal examples. The present invention is not limited to the shapes or values ​​shown in the drawings.

[0033] In addition, in drawings, etc., the same elements or elements having similar functions, elements made of the same material, Alternatively, elements formed at the same time may be given the same reference numerals, and the repeated explanations thereof may be omitted. may be omitted.

[0034] In addition, in this specification and the like, the terms "film" and "layer" are interchangeable. For example, the term "conductive layer" can be changed to the term "conductive film." Alternatively, for example, the term "insulating film" may be changed to "insulating layer." It may be possible to change the term to

[0035] In addition, in this specification, terms indicating placement such as "above" and "below" refer to the positional relationship of components. The relationship is not limited to being "directly above" or "directly below." For example, In the case of the expression "gate electrode on an insulating layer," it is understood that there is no other component between the gate insulating layer and the gate electrode. Do not exclude anything that includes.

[0036] In addition, in this specification, "parallel" means that two straight lines are at an angle of -10° or more and 10° or less. Therefore, it includes the case where the angle is between -5° and 5°. "Perpendicular" means that two straight lines are arranged at an angle of 80° or more and 100° or less. Therefore, this also includes cases where the angle is between 85° and 95°.

[0037] In addition, in this specification, ordinal numbers such as "first," "second," and "third" indicate the order of constituent elements. This is added to avoid confusion and is not intended to limit the number.

[0038] In addition, in this specification, "electrically connected" means "something that has some kind of electrical effect." This includes cases where the device is connected via a " is not subject to any particular restrictions as long as it enables the transmission and reception of electrical signals between connected objects. For example, "things that have some kind of electrical action" include electrodes, wiring, and transistors. These include switching elements, resistor elements, inductors, capacitor elements, and various other functions. This includes elements, etc.

[0039] In this specification, the term "voltage" refers to the difference between a certain potential and a reference potential (for example, ground potential). Therefore, voltage and potential difference can be interchanged. can.

[0040] In this specification, a transistor includes a gate, a drain, and a source. , an element having at least three terminals. drain region, or drain electrode) and source (source terminal, source region, or source electrode) A channel forming region is formed between the source and drain. In this specification and the like, a channel formation region is a region where a current can flow. The region refers to the region through which the current mainly flows.

[0041] The source and drain functions may differ depending on the type of transistor used, or the circuit operation. This may be reversed if the direction of the current changes during operation. In the text, the terms source and drain may be used interchangeably.

[0042] Unless otherwise specified, in this specification and the like, the off-state current refers to the current that flows when a transistor is in an off-state. The drain current when the device is in the on state (also known as the non-conducting state or cut-off state). , unless otherwise specified, for n-channel transistors, the gate to source voltage V When gs is lower than the threshold voltage Vth, in a p-channel transistor, This refers to the state in which the gate voltage Vgs is higher than the threshold voltage Vth. The off-state current of a gate-type transistor is the voltage Vgs of the gate to the source when the threshold voltage V This is sometimes called the drain current when it is lower than th.

[0043] In the above description of the off-state current, the drain may be read as the source. The off-state current is the source current when the transistor is in the off state. In this specification and the like, the off-state current is , which refers to the current that flows between the source and drain when the transistor is in the off state. There is.

[0044] In this specification, the term "metal oxide" is used in a broad sense. Metal oxides are oxide insulators and oxide conductors (transparent oxide conductors). Oxide Semiconductor (also known as OS) For example, when a metal oxide is used in the active layer of a transistor, Metal oxides are sometimes called oxide semiconductors. In other words, metal oxides have the functions of amplification and rectification. and switching action, the metal oxide is Metal oxide semiconductor, abbreviated as OS In addition, when referring to an OS transistor or an OS FET, In other words, a transistor including a metal oxide or an oxide semiconductor.

[0045] (Embodiment 1) In this embodiment, a semiconductor device according to one embodiment of the present invention will be described. The semiconductor device according to the present invention has memory cells formed using OS transistors.

[0046] <Configuration example of semiconductor device> FIG. 1A is a block diagram showing an example of the configuration of a semiconductor device 10 according to one embodiment of the present invention. .

[0047] The semiconductor device 10 includes a plurality of memory cells MC and a sensor electrically connected to the memory cells MC. It has a scan amplifier SA (see FIG. 1(A)).

[0048] The memory cell MC includes a transistor OS1 and a capacitance element C0 (see FIG. 1B). The memory cell MC is a volatile memory that can store data by holding a charge in the capacitance element C0. It is a sexual memory.

[0049] The wiring WL supplies a signal that controls the on / off state of the transistor OS1. The line WL functions as a word line for the memory cell MC. The wiring BL supplies the charge to be written to the capacitance element C0 via S1. The memory cell MC functions as a bit line for the capacitor C0. After the charge is written into the capacitor C0, the charge written into the capacitor C0 is released by turning off the transistor OS1. It can be retained.

[0050] The memory cells MC are electrically connected to the sense amplifiers SA via wiring BL. The amplifier SA has a function of amplifying and outputting the potential of the data stored in the memory cell MC. Even if the potential read from the memory cell MC is weak, the read potential is sensed. Since the signal is amplified by the amplifier SA, the semiconductor device 10 can read the data reliably. This can be done.

[0051] In FIG. 1A, the memory cells MC are formed in a layer different from that of the sense amplifiers SA. In FIG. 1A, the memory cell MC is formed in the upper layer of the sense amplifier SA. At least one memory cell MC has an area overlapping with the sense amplifier SA. This allows the memory cells MC and sense amplifiers SA to be formed on the same layer. In comparison with the case where the semiconductor device 10 is fabricated, the area of ​​the semiconductor device 10 can be reduced.

[0052] FIG. 1A shows an example in which a memory cell MC is formed above a sense amplifier SA. However, this is not the only option, and the memory cells MC and the sense amplifiers SA may be formed in the same layer. FIG. 2 shows a semiconductor memory device in which memory cells MC and sense amplifiers SA are formed in the same layer. 1 is a block diagram showing an example of the configuration of a device 10. FIG.

[0053] The semiconductor device 10 includes a cell array 70 and a sense amplifier circuit 60. The cell array 70 includes Each memory cell MC is electrically connected to a wiring WL and a wiring BL. The memory cell MC is selected by the potential supplied to the wiring WL. A potential corresponding to data to be written in the memory cell MC (hereinafter also referred to as a write potential) is allocated. When a voltage is supplied to the line BL, data is written into the memory cell MC.

[0054] The number of memory cells MC included in the cell array 70 can be freely set. For example, The number of cells can be set to 128 or more and 512 or less. Here, the cell array 70 has the i-th row and j-th column ( The case where i and j are integers of 2 or more) are included in the memory cells MC will be described. The array 70 is provided with i wires WL and j wires BL.

[0055] In the cell array 70 shown in FIG. 1A, a memory cell electrically connected to a certain wiring BL The memory cell MC is electrically connected to the wiring BL adjacent to the wiring BL. Therefore, the cell array 70 is configured such that the wiring WL is not electrically connected to the wiring WL. , i×j / 2 memory cells MC.

[0056] In one embodiment of the present invention, the layout method of the cell array 70 may be a folded type or an open type. When the folded type is applied, the potential change of the wiring WL causes This makes it possible to reduce noise that occurs in the read potential output to the wiring BL. When the open type is applied, the density of the memory cells MC can be increased compared to the folded type. It is possible to reduce the area of ​​the cell array 70. FIG. 1(A) shows the case where the folded type is applied. 1 shows an example of the configuration of the cell array 70 in this case.

[0057] The sense amplifier circuit 60 is electrically connected to a plurality of wirings BL and wirings GBL. The sense amplifier circuit 60 has the function of amplifying the input signal and controlling the output of the amplified signal. Specifically, the wiring BL corresponding to the data stored in the memory cell MC The potential (hereinafter also referred to as read potential) is amplified and output to the wiring GBL at a predetermined timing. The sense amplifier circuit 60 amplifies the read potential, Even if the potential read from the memory cell MC is weak, data can be read reliably. In addition, by controlling the output of the amplified signal to the wiring GBL, The sense amplifier circuit 60 has a plurality of sense amplifiers SA. do.

[0058] The sense amplifier SA detects a potential difference between a reference potential and a read potential supplied to the line BL. The amplified potential difference is then amplified and held. In this example, the sense amplifier SA has the function of controlling the output to two wires BL and 2 An example of electrical connection to the wiring GBL is shown.

[0059] FIG. 1B shows an example of the configuration of the memory cell MC. The memory cell MC includes a transistor OS1 The gate of the transistor OS1 is electrically connected to the wiring WL. One of the source and drain is electrically connected to one electrode of the capacitance element C0. The other of the drains is electrically connected to the wiring BL. The electrodes are connected to wiring or terminals to which a predetermined potential (such as a ground potential) is supplied. Here, the voltage at either the source or drain of the transistor OS1 and the voltage at either the capacitance element C0 are The node connected to the pole is called node N.

[0060] The transistor OS1 is in a non-conductive state, and thus the charge stored in the node N is retained. Therefore, the off-state current of the transistor OS1 is preferably small. When the off-state current of the transistor OS1 is small, leakage of the charge held at the node N is reduced. Therefore, the data stored in the memory cell MC can be retained for a long time. This can be done.

[0061] Here, a semiconductor with a wider band gap and lower intrinsic carrier density than silicon is called a chalcogenide. The transistor having the gate electrode in the channel formation region can have a small off-state current. Such a semiconductor material is suitable for use as a transistor OS1. Examples include oxide semiconductors with a band gap more than twice that of semiconductors. A transistor including an oxide semiconductor in a gate formation region (also called an OS transistor) is The off-state current is extremely low compared to transistors made of materials other than oxide semiconductors, such as silicon dioxide. Therefore, by using an OS transistor for the transistor OS1, the memory cell M Data written to C can be retained for a long time, and Specifically, the interval between refresh operations can be set to one hour or more. This can be done.

[0062] The transistor OS1 may also be a transistor having a back gate. The transistor OS2 shown in C) has a back gate. The output terminal is electrically connected to the wiring BGL. The wiring BGL supplies the voltage Vbg_w1. By setting the voltage Vbg_w1 to a negative voltage, the threshold voltage of the transistor OS2 is set to a value closer to the positive potential. , and the retention time of the memory cell MC can be extended.

[0063] By using an OS transistor as the transistor OS1 of the memory cell MC, The semiconductor device 10 can be used as a storage device capable of storing data for a long period of time. Therefore, the semiconductor device 10 stops the power supply when data is not being written or read. You can increase the interval between refresh operations, write or read data, By stopping the power supply when no power is being supplied, the semiconductor device 10 reduces power consumption. can be reduced.

[0064] A more specific example of the configuration of the semiconductor device 10 will be described with reference to FIG.

[0065] The semiconductor device 10 shown in FIG. 3 is the same as the semiconductor device 10 shown in FIG. 1(A) except that a driving circuit 80, a main The circuit is formed by adding a power amplifier 81 and an input / output circuit 82.

[0066] The main amplifier 81 is connected to the sense amplifier circuit 60 and the input / output circuit 82. The input amplifier 81 has a function of amplifying an input signal. It has the function of amplifying the potential and outputting it to the input / output circuit 82. Note that the main amplifier 81 is omitted. You can also do this.

[0067] In FIG. 3, the memory cell MC includes a sense amplifier SA, a drive circuit 80, a main amplifier 3 shows an example in which the memory cell 81 and the input / output circuit 82 are formed on different layers. The memory cell MC is formed on the upper layer of the sense amplifier SA, and at least one memory cell M C is arranged to have an area overlapping with the sense amplifier SA. The area of ​​the device 10 can be reduced.

[0068] In FIG. 3, an example in which the memory cells MC are formed above the sense amplifiers SA is shown. However, the memory cells MC and the sense amplifiers SA may be formed in the same layer. Also, the memory cell MC includes a sense amplifier SA, a drive circuit 80, a main amplifier 81, and The input / output circuit 82 may be formed in the same layer as the input / output circuit 82.

[0069] The input / output circuit 82 reads the potential of the wiring GBL or the potential output from the main amplifier 81. It has the function of outputting the data externally as read data.

[0070] The drive circuit 80 is connected to the memory cells MC via wiring WL. A signal for selecting a memory cell MC to which data is to be written (hereinafter referred to as The driver circuit 80 has a function of supplying a signal (also called a write word signal). It can be configured as follows.

[0071] The sense amplifier SA is connected to the memory cell MC via the wiring BL. The two adjacent wires BL (wires BL_1 and BL_2) are connected to the same sense amplifier SA. The sense amplifier SA includes an amplifier circuit 62 and a switch It has a circuit 63.

[0072] The amplifier circuit 62 has a function of amplifying the potential of the wiring BL. The potential difference between the wiring BL and the reference potential is amplified, and the amplified potential difference is held. For example, when amplifying the potential of the wiring BL_1, the potential of the wiring BL_2 is used as the reference potential, The potential difference between the wiring BL_1 and the wiring BL_2 is amplified. Also, the potential of the wiring BL_2 is amplified. In this case, the potential difference between wire BL_1 and wire BL_2 is Amplify.

[0073] The switch circuit 63 selects whether or not to output the amplified potential of the wiring BL to the wiring GBL. Here, the switch circuit 63 has a function of switching two wirings GBL (wirings GBL_1 and GBL_2). The switch circuit 63 is connected to the wiring BL_ 1 and wiring GBL_1, and the conduction state between wiring BL_2 and wiring GBL_2. It has the function of controlling.

[0074] The switch circuit 63 is connected to one of the plurality of wirings CSEL, and the drive circuit 8 The operation of the switch circuit 63 is controlled based on the signal supplied from the line CSEL to the The semiconductor device 10 uses the switch circuit 63 and the wiring CSEL to select a signal to be output to the outside. Therefore, the input / output circuit 82 is configured to select a signal using a multiplexer or the like. The signal selection function is no longer necessary, and the circuit configuration can be simplified.

[0075] Here, a configuration example in which the wiring WL and the wiring CSEL are connected to the drive circuit 80 is shown. However, the wiring WL and the wiring CSEL may be connected to different drive circuits. The potentials of the wiring WL and the wiring CSEL are controlled by separate drive circuits.

[0076] The number of wirings GBL is not particularly limited, and the number of wirings BL in the cell array 70 (j For example, the number of wires connected to one wire GBL can be any number smaller than When the number of wirings BL is k (k is an integer of 2 or more), the number of wirings GBL is j / k.

[0077] <Sense amplifier SA1> Next, a sense amplifier that can be applied to the sense amplifier SA included in the semiconductor device 10 will be described. An example of the configuration of the amplifier SA1 will be described.

[0078] FIG. 4 shows a memory cell MC and a sense amplifier SA1 electrically connected to the memory cell MC. A circuit configuration example is shown. The memory cell MC is connected to a sense amplifier SA1 via a wiring BL. Here, the memory cell MC_1 is connected to the sense amplifier SA1 via the wiring BL_1. The memory cell MC_2 is connected to the sense amplifier SA1 via the wiring BL_2. An example configuration is shown below.

[0079] FIG. 4 shows an example of a configuration in which one memory cell MC is connected to one wiring BL. However, a plurality of memory cells MC may be connected to the wiring BL.

[0080] The sense amplifier SA1 includes an amplifier circuit 62, a switch circuit 63, and a precharge circuit 64. do.

[0081] The amplifier circuit 62 includes p-channel transistors 21 and 22 and an n-channel The transistors 23 and 24 are of the same type as the transistors 31 to 34. The circuit includes a resistor 34, a capacitance element C11, and a capacitance element C12.

[0082] Here, the n-channel transistors 31 to 34 are p-channel transistors. In FIG. 5, transistors 31 to 34 are p-channel transistors. 1 shows an example of the circuit configuration of the sense amplifier SA1 in which the transistors 35 to 38 are used. In this case, the gates of the transistors 35 to 38 are inverted. To operate the inverter, connect the wiring PL2 or PL3 via inverter INV2 or inverter INV3. The wiring PL2 and the wiring PL3 are connected to one side of the wiring PL3. The wiring PL2 and the wiring PL3 will be described later.

[0083] Alternatively, the n-channel transistors 31 to 34 may be analog switches. In FIG. 6, the transistors 31 to 34 are analog Circuit configuration of sense amplifier SA1 using switches ASW1 to ASW4 Here is an example.

[0084] Alternatively, the n-channel transistors 31 to 34 may be replaced with some kind of switch. In FIG. 7, transistors 31 to 34 are shown. 10 shows an example of the circuit configuration of the sense amplifier SA1, in which the switches SW1 to SW4 are used. vinegar.

[0085] The p-channel transistor 21 and the transistor 22 are n-channel transistors. For example, the p-channel transistors 21 and 22 may be replaced with n-channel transistors. The transistors 41 and 42 are of the same type. The resistors 42 are connected to the gate and either the source or the drain. 8 shows the transistor 21 and the transistor 22 shown in FIG. , and n-channel transistors 41 and 42 are used as the sense amplifiers. 1 shows an example of the circuit configuration of amplifier SA1.

[0086] Alternatively, the p-channel transistors 21 and 22 may be used as resistor elements. 9 shows the transistor 21 and the transistor 22 shown in FIG. An example of the circuit configuration of the sense amplifier SA1 is shown in FIG. The transistor 21 and the transistor 22 are n-channel transistors or resistor elements. By doing so, the amplifier circuit 62 can be configured using unipolar transistors. In this case, the transistors included in the amplifier circuit 62 can be manufactured in the same process. The manufacturing process can be shortened.

[0087] Alternatively, the p-channel transistors 21 and 22 may be depletion-type transistors. The transistor may be an n-channel transistor of a normally-on type (also called a normally-on type). 4. The transistor 21 and the transistor 22 shown in FIG. The circuit configuration of the sense amplifier SA1 is that the transistors 43 and 44 are of the same type. Here is an example.

[0088] Alternatively, the p-channel transistor 21 and the transistor 22 are n-channel transistors, As a transistor having a back gate similar to the transistor OS2 shown in FIG. For example, the p-channel transistors 21 and 22 may be The source or the drain of the n-channel transistor is Alternatively, one of the drains can be connected to the gate to form a diode connection. Applying a positive voltage to the back gate makes the threshold voltage of the n-channel transistor negative. The n-channel transistor is shifted to the depletion mode transistor. It may also be used.

[0089] More specifically, FIG. 11 shows the transistor 21 and the transistor 22 shown in FIG. The sense amplifiers are transistors 45 and 46, each having a back gate. 1 shows an example of the circuit configuration of amplifier SA1. The outputs are connected to the wiring BGL, and by supplying a positive voltage via the wiring BGL, The transistors 45 and 46 are depletion-mode transistors. By using the transistors 21 and 22 as n-channel transistors, The width circuit 62 can be constructed with unipolar transistors.

[0090] One of the source and drain of the transistor 21 is connected to the wiring Vd. The other of the drains is connected to one of the source or drain of transistor 23 and the other of the drain of transistor 31. One of the source or drain of the transistor 33 and one of the source or drain of the transistor 34. The other of the source and drain of the transistor 23 is connected to the wiring V s, and the other of the source and drain of the transistor 33 is connected to the wiring BL_1. The other of the source and drain of the transistor 31 is connected to the gate of the transistor 21. The gate of the transistor 23 and one electrode of the capacitance element C11 are connected to the The other electrode of the transistor C11 is connected to the wiring BL_2. The gate of the transistor 33 is connected to the wiring PL2, and the gate of the transistor 34 is connected to the wiring PL3. Here, the other of the source or drain of the transistor 31, the gate of the transistor 21, A node connected to the gate of the transistor 23 and one electrode of the capacitance element C11 is connected to Let's call this node N11.

[0091] One of the source and drain of the transistor 22 is connected to the wiring Vd. The other of the drains is connected to one of the source or drain of transistor 24 and the other of the drains of transistor 32. One of the source or drain of transistor 34 and one of the source or drain of transistor 35. The other of the source and drain of the transistor 24 is connected to the wiring Vs. The other of the source and the drain of the transistor 34 is connected to the wiring BL_2. The other of the source and drain of transistor 32 is connected to the gate of transistor 22, The gate of the capacitor C12 is connected to the gate of the capacitor C24 and one electrode of the capacitor C12. The gate of the transistor 32 is connected to the wiring PL The gate of the transistor 34 is connected to the wiring PL3. The other of the source or drain of the transistor 32, the gate of the transistor 22, the transistor A node connected to the gate of the capacitor C12 and one electrode of the capacitor C12 is referred to as a node N12. Let's say.

[0092] Here, the wiring Vd is a wiring that supplies a high potential power supply VH_SP, and the wiring Vs is a wiring that supplies a low potential power supply VH_SP. This is the wiring that supplies the power supply VL_SN. L_SN may be supplied intermittently. That is, high voltage is supplied via the wiring Vd and the wiring Vs. The period when the potential power supply VH_SP and the low potential power supply VL_SN are supplied and the period when they are not supplied are May be present.

[0093] Furthermore, the transistors 31 and 32 are in a non-conductive state. The transistor N11 and the transistor N12 have the function of holding the charge accumulated in them. It is preferable that the off-state current of the transistor 31 and the transistor 32 be small. The transistor 31 and the transistor 32 may be OS transistors.

[0094] The amplifier circuit 62 has a function of amplifying the potential of the wiring BL_1 and a function of amplifying the potential of the wiring BL_2. The sense amplifier SA1 having the amplifier circuit 62 shown in FIG. It functions as a switch-type sense amplifier.

[0095] The amplifier circuit 62 may have two amplifier circuits 65. An example of the circuit configuration of the sense amplifier SA1 when it has two width circuits 65 is shown in FIG. An example of the circuit configuration of the amplifier circuit 65 is shown in FIG.

[0096] As shown in FIG. 12A, the amplifier circuit 62 has two amplifier circuits 65. One amplifier circuit 65 has an input terminal IN1 and an output terminal OUT1. The other amplifier circuit has an output terminal OUT1 connected to the line BL_1 and an output terminal OUT2 connected to the line BL_2. 65, the input terminal IN1 is connected to the wiring BL_2, and the output terminal OUT1 is connected to the wiring BL_1. Connected.

[0097] The amplifier circuit 65 includes a p-channel transistor 21 and an n-channel transistor 23. , transistor 31, transistor 33, and a capacitance element C11.

[0098] One of the source and drain of the transistor 21 is connected to the wiring Vd. The other of the drains is connected to one of the source or drain of transistor 23 and the other of the drain of transistor 31. One of the source or drain of the transistor 33 and one of the source or drain of the transistor 34. The other of the source and drain of the transistor 23 is connected to the wiring Vs. The other of the source and drain of the transistor 33 is connected to the output terminal OUT1. The other of the source and drain of the transistor 31 is connected to the gate of the transistor 21. The gate of the transistor 23 and one electrode of the capacitance element C11 are connected to each other. The other electrode of the transistor 31 is connected to the input terminal IN1. The gate of the transistor 33 is connected to the line PL3.

[0099] The switch circuit 63 includes an n-channel transistor 25 and a transistor 26. The transistors 25 and 26 may be p-channel transistors. One of the source and drain of the transistor 25 is connected to the wiring BL_1. The other end of the gate is connected to the wiring GBL_1. One of the source and drain is connected to the wiring BL_2, and the other of the source and drain is connected to the wiring GBL_2. It has been done.

[0100] The gates of the transistors 25 and 26 are connected to the wiring CSEL. The switch circuit 63 switches between the wiring B and the The conduction state between L_1 and wiring GBL_1, and the conduction state between wiring BL_2 and wiring GBL_2 It has the function of controlling.

[0101] The precharge circuit 64 includes an n-channel transistor 27, a transistor 28, and The transistors 27 to 29 are p-channel transistors. One of the source and the drain of the transistor 27 is connected to the wiring BL_1. The other of the source and drain is connected to the wiring Pre and the source or drain of the transistor 28. The other of the source or drain of transistor 28 is connected to a It is connected to line BL_2.

[0102] One of the source and the drain of the transistor 29 is connected to the wiring BL_1. The other drain of the transistor 27 is connected to the wiring BL_2. The gate of the transistor 28 and the gate of the transistor 29 are connected to the wiring PL1. The precharge circuit 64 initializes the potentials of the wirings BL_1 and BL_2. It has a function.

[0103] <Operation example 1 of sense amplifier SA1> Next, regarding the memory cell MC and the sense amplifier SA1 shown in FIG. 4, An example of the operation will be described with reference to the timing chart shown in FIG.

[0104] During the period T1, the transistors 27 to 29 of the precharge circuit 64 are The potentials of the wirings BL_1 and BL_2 are initialized by turning on the wirings P A high-level potential VH_PL is applied to L1, and a transistor 27 to 29 are turned on. This causes the wiring BL_1 and the wiring BL_2 The potential Vpre of the wiring Pre is applied to the wiring Pre. VL_SN) / 2.

[0105] During the period T1, the transistors 31 and 32 of the amplifier circuit 62 are The potentials of the nodes N11 and N12 are initialized by turning on the wiring P A high-level potential VH_PL is applied to L2, and the transistors 31 and and transistor 32 is turned on.

[0106] Here, since the transistors 21 and 23 form an inverter, By turning on the transistor 31 and establishing a conductive state between the input and output of the inverter, The potential of the node N11 is an intermediate potential depending on the characteristics of the transistors 21 and 23. This potential is designated as Vn11. The intermediate potential Vn11 is The potential is determined by reflecting the influence of the characteristic variations of the transistor 23. 1 and transistor 23, the input potential of the inverter is the intermediate potential Vn1 It can react sensitively when it fluctuates from 1.

[0107] Similarly, transistors 22 and 24 form an inverter. By turning on the transistor 32 and establishing a conductive state between the input and output of the inverter, The potential of the node N12 is an intermediate potential depending on the characteristics of the transistors 22 and 24. This potential is designated as Vn12. The intermediate potential Vn12 is The potential is determined by reflecting the influence of the characteristic variations of the transistor 24 and the transistor 25. 2 and transistor 24, the input potential is the intermediate potential Vn1 If it fluctuates from 2, it can react sensitively.

[0108] Note that during the period T1, a low-level potential VL_CSEL is applied to the wiring CSEL. In the switch circuit 63, the transistors 25 and 26 are in the off state. In addition, a low-level potential VL_WL is applied to the wiring WL_1, and the memory cell In the case of the capacitor MC_1, the transistor OS1 is in an off state. However, a low-level potential VL_WL is applied to the wiring WL_2, and the memory cell In the channel MC_2, the transistor OS1 is in an off state.

[0109] Next, a low-level potential VL_PL is applied to the wiring PL1, and the precharge circuit 64 Similarly, a low-level signal is applied to the wiring PL2. The potential VL_PL of the amplifier 62 is applied to the transistor 31 and the transistor Turn off 32.

[0110] At the timing when the low-level potential VL_PL is applied to the wiring PL2, the high-level potential VH_SP The supply of the high potential power supply VH_SP and the low potential power supply VL_SN may be stopped. By stopping the supply of the voltage source VL_SN, the transistors 21 and 23 are turned on. The through current flows through transistor 22 and transistor 24. This can prevent through current from flowing through the high potential power supply VH_SP and When the supply of the low potential power supply VL_SN is stopped, the wiring PL At the timing when a high level potential VH_PL is applied to the high potential power supply VH_SP and the low potential power supply VH_PL The supply of the potential power supply VL_SN is restored.

[0111] In addition, during a part of the period T1, the wirings Vd and Vs supply the potential Vpre. During the period when the wiring Vd and the wiring Vs supply the potential Vpre, The inverter formed by the transistor 21 and the transistor 23, and the inverter formed by the transistor 22 and the transistor The inverter formed by the transistor 24 outputs the potential Vpre. Transistor 31 and transistor 32 are turned off, and transistor 33 and transistor 3 By turning on 4, a potential Vpre can be applied to the wiring BL_1 and the wiring BL_2. That is, the function of the precharge circuit 64 can be performed by using the amplifier circuit 62. can.

[0112] In the period T2, the wiring WL_1 is selected. Specifically, a high-level potential is applied to the wiring WL_1. VH_WL is applied to turn on the transistor OS1 in the memory cell MC_1. By this operation, the wiring BL_1 and the capacitance element C0 are brought into a conductive state via the transistor OS1. When the wiring BL_1 and the capacitor C0 are brought into a conductive state, the voltage held in the capacitor C0 The potential of the wiring BL_1 varies according to the amount of charge.

[0113] In the timing chart shown in FIG. 13, when the amount of charge held in the capacitance element C0 is large, When the amount of charge held in the capacitance element C0 is large, When the charge is released to BL_1, the potential of the wiring BL_1 decreases by ΔV1 from the potential Vpre. Conversely, when the amount of charge held in the capacitance element C0 is small, the When a charge flows into the capacitance element C0, the potential of the wiring BL_1 drops by ΔV2 (not shown). To descend.

[0114] When the potential of the wiring BL_1 rises by ΔV1 from the potential Vpre, Therefore, the potential of the node N12 also rises by ΔV3 from the intermediate potential Vn12. However, the voltage Vn12 is changed from the intermediate voltage Vn12 to ΔV 3, the inverter formed by transistor 22 and transistor 24 outputs the low potential power supply VL_SN.

[0115] Note that during the period T2, a low-level potential VL_CSEL is applied to the wiring CSEL. In the switch circuit 63, the transistors 25 and 26 are turned off. The status is maintained.

[0116] Next, in a period T3, the transistors 33 and 34 of the amplifier circuit 62 is turned on, and the amplifier circuit 62 outputs to the wiring BL_1 and the wiring BL_2. , a high-level potential VH_PL is applied to the wiring PL3, and the transistor 33 and transistor 34 are turned on.

[0117] In the case of FIG. 13 (when the amount of charge held in the capacitance element C0 is large), in the amplifier circuit 62 When the transistors 33 and 34 are turned on, the amplifier circuit 62 is connected to the wiring BL_ 2, the low potential power supply VL_SN is output. The potential of the wiring BL_2 is Vpre to the low potential power supply V As the potential at node N11 approaches L_SN, the potential at node N11 drops via capacitance element C11, and the transistor The inverter formed by the transistor 21 and the transistor 23 is connected to the high potential power supply VH_SP. Then, the amplifier circuit 62 outputs the high potential power supply VH_SP to the wiring BL_1, The potential of BL_1 approaches the high potential power supply VH_SP from Vpre+ΔV1. The potential of the capacitor C12 also rises via the capacitor C12.

[0118] At the beginning of the period T3, the amount of charge held in the capacitance element C0 is small, and the wiring BL_ When the potential of transistor 33 is equal to the potential Vpre-ΔV2, the potential of transistor 34 is equal to the potential Vpre-ΔV2. When this is turned on, the potential of the wiring BL_2 approaches the high potential power supply VH_SP from Vpre. As the potential of the wiring BL_1 approaches the low potential power supply VL_SN from the potential Vpre-ΔV2, It goes on.

[0119] During the period T3, the low-level potential VL_PL is still applied to the wiring PL1. In the precharge circuit 64, the transistors 27 to 29 are in the off state. Similarly, a low-level potential VL_CSEL is applied to the line CSEL. In the switch circuit 63, the transistors 25 and 26 are turned on. The line WL_1 is applied with a high-level potential VH_WL. In the memory cell MC_1, the transistor OS1 remains on. Therefore, in the memory cell MC_1, a charge according to the potential VH_SP of the wiring BL_1 is generated. It is stored in the capacitance element C0.

[0120] In the period T4, the potential applied to the wiring CSEL is controlled to turn on the switch circuit 63. Specifically, a high-level potential VH_CSEL is applied to the wiring CSEL, and the switch circuit Path 63 turns on transistors 25 and 26. This turns on the The potential of the line BL_1 is supplied to the wiring GBL_1, and the potential of the wiring BL_2 is supplied to the wiring GBL_2. Supplied.

[0121] Note that during the period T4, the low-level potential VL_PL remains applied to the wiring PL1. In the precharge circuit 64, the transistors 27 to 29 are in the off state. The wiring WL_1 is maintained at a high level potential VH_WL. In the memory cell MC_1, the transistor OS1 remains on. Therefore, in the memory cell MC_1, a charge according to the potential VH_SP of the wiring BL_1 is transferred to the capacitor It remains stored in C0.

[0122] When the period T4 ends, the potential applied to the wiring CSEL is controlled to turn on the switch circuit 63. Specifically, a low-level potential VL_CSEL is applied to the line CSEL, and the switch In the switch circuit 63, the transistor 25 and the transistor 26 are turned off. A low-level potential VL_PL is applied to the wiring PL3, and the transistor 3 3 and transistor 34 are turned off.

[0123] When the period T4 ends, the selection of the wiring WL_1 ends. A low-level potential VL_WL is applied to the memory cell MC_1 to turn on the transistor OS1. By the above operation, a charge according to the potential VH_SP of the wiring BL_1 is transferred to the capacitance element C Even after the data is read, the data is still stored in the memory cell MC_1. It is held in place.

[0124] In the period T1, the operation of initializing the potentials of the node N11 and the node N12 is as follows: It is not necessary to do this every time. Once, wire BL_1, wire BL_2, node N11, and node When the potential of N12 is initialized, the potentials of the wiring BL_1 and wiring BL_2 change. Even if the potentials of the node N11 and the node N12 change, the wiring BL_1 and the wiring BL_2 When the potentials of the nodes N11 and N12 are initialized, the potentials of the nodes N11 and N12 are also initialized to Vn11 and Vn12, respectively. In this case, the transistors 31 and 32 It is preferable that the off-state current is small. For example, , an OS transistor can be used.

[0125] By the operations during the above-described periods T1 to T4, data is read from the memory cell MC_1. Data can be read from memory cell MC_2 in the same manner. do.

[0126] Data can also be written to the memory cells MC using the same principle as above. Specifically, as in the case of reading data, first, the transistors of the precharge circuit 64 are The transistors 27 to 29 are turned on to turn on the wirings BL_1 and BL_2. The potential is initialized, and the transistors 31 and 32 of the amplifier circuit 62 are turned on. This initializes the potentials of the nodes N11 and N12.

[0127] Next, the wiring WL_1 connected to the memory cell MC_1 to which data is to be written, selects the wiring WL_2 connected to the memory cell MC_2, and In memory cell MC_2, transistor OS1 is turned on. L_1 or the wiring BL_2 and the capacitance element C0 are in a conductive state via the transistor OS1. becomes.

[0128] Next, the potential applied to the wiring CSEL is controlled to turn on the switch circuit 63. Wiring BL_1 and wiring GBL_1 are in a conductive state, and wiring BL_2 and wiring GBL_2 are in a conductive state. This is the state.

[0129] Then, by applying a write potential to each of the wiring GBL_1 and the wiring GBL_2, A write potential is applied to the wiring BL_1 and the wiring BL_2 via the switch circuit 63. By the above operation, charges are stored in the capacitor C0 according to the potential of the wiring BL_1 or the wiring BL_2. The data is written to the memory cell MC_1 or the memory cell MC_2.

[0130] The potential of the wiring GBL_1 is applied to the wiring BL_1, and the potential of the wiring GBL_2 is applied to the wiring BL_2. After the potential is applied, the transistors 25 and 26 in the switch circuit 63 Even if the power supply 26 is turned off, the relationship between the potential of the wiring BL_1 and the potential of the wiring BL_2 is amplified. It is maintained by circuit 62.

[0131] <Operation example 2 of sense amplifier SA1> Regarding the memory cell MC and the sense amplifier SA1 shown in FIG. 4, the timing chart shown in FIG. An example of operation different from the chart will be described with reference to the timing chart shown in FIG.

[0132] During the period T1, the transistors 31 and 32 of the amplifier circuit 62 are turned on. Specifically, the potentials of the nodes N11 and N12 are initialized. A high-level potential VH_PL is applied to the amplifier circuit 62, and the transistors 31 and 32 are connected to the amplifier circuit 62. Transistor 32 is turned on.

[0133] During the period T1, the transistors 33 and 34 of the amplifier circuit 62 are turned on. The potentials of the wirings BL_1 and BL_2 are initialized by turning on the wirings P A high-level potential VH_PL is applied to L3, and the transistors 33 and and transistor 34 is turned on.

[0134] Here, since the transistors 21 and 23 form an inverter, By turning on the transistor 31 and establishing a conductive state between the input and output of the inverter, The potential of the node N11 is an intermediate potential depending on the characteristics of the transistors 21 and 23. This potential is designated as Vn11. The intermediate potential Vn11 is The potential is determined by reflecting the influence of the characteristic variations of the transistor 23. The inverter formed by transistors 1 and 23 receives the input voltage Vn11 and changes it from Vn11. If it moves, it can react sensitively.

[0135] Also, transistor 33 is turned on, and transistors 21 and 23 By connecting the output of the inverter formed by the inverter to the wiring BL_1, The potential of BL_1 also becomes Vn11. Since the potential is an intermediate potential according to the characteristics of transistor 23, transistors 21 and 2 When the input of the inverter formed by 3 varies from Vn11, the output of the inverter The potential of the wiring BL_1 is also changed from Vn11. ,When the inverter input fluctuates from Vn11, the output change is quickly transmitted to wiring BL_1. It can be communicated.

[0136] Similarly, transistors 22 and 24 form an inverter. By turning on the transistor 32 and establishing a conductive state between the input and output of the inverter, The potential of the node N12 is an intermediate potential depending on the characteristics of the transistors 22 and 24. This potential is designated as Vn12. The intermediate potential Vn12 is The potential is determined by reflecting the influence of the characteristic variations of the transistor 24 and the transistor 25. The inverter formed by transistors 2 and 24 receives the input voltage from Vn12. If it moves, it can react sensitively.

[0137] Similarly, transistor 34 is turned on to allow transistors 22 and 24 to By bringing the output of the inverter formed by this into a conductive state with the wiring BL_2, The potential of the line BL_2 also becomes Vn12. Since the potential is an intermediate potential according to the characteristics of the transistor 24, the potential of the transistor 22 and the transistor When the input of the inverter formed by Vn12 changes from Vn12, the output of the inverter The potential of the wiring BL_2 is initialized to Vn12. Then, when the inverter input changes from Vn12, the output change is quickly transmitted to wiring BL_2. It can be easily conveyed.

[0138] The transistors 33 and 34 of the amplifier circuit 62 are turned on. When initializing the potentials of the line BL_1 and the wiring BL_2, the precharge circuit 64 is 14, the wiring PL1 is supplied with a low-level potential VL_ PL is given.

[0139] In the period T1, a low-level potential VL_CSEL is applied to the wiring CSEL. In the switch circuit 63, the transistors 25 and 26 are in the off state. A low-level potential VL_WL is applied to the wiring WL_1, and the memory cell MC In the state of _1, the transistor OS1 is in an off state. However, a low-level potential VL_WL is applied to the line WL_2, and the memory cell MC In _2, the transistor OS1 is in an off state.

[0140] Next, a low-level potential VL_PL is applied to the wiring PL2 and the wiring PL3, and the amplifier circuit 6 In 2, transistors 31 to 34 are turned off.

[0141] At the timing when a low-level potential VL_PL is applied to the wiring PL2 and the wiring PL3, a high-level potential VL_PL is applied to the wiring PL3. The supply of the high potential power supply VH_SP and the low potential power supply VL_SN may be stopped. By stopping the supply of V_SP and the low potential power supply VL_SN, the transistors 21 and The through current flowing through the transistor 23 and the transistor 22 and the transistor 24, the through current can be prevented, and power consumption can be reduced. When the supply of the power supply VH_SP and the low potential power supply VL_SN is stopped, during a period T3 described later, At the timing when a high-level potential VH_PL is applied to the wiring PL3, The supply of H_SP and the low potential power supply VL_SN is restored.

[0142] In the period T2, the wiring WL_1 is selected. Specifically, a high-level potential is applied to the wiring WL_1. VH_WL is applied to turn on the transistor OS1 in the memory cell MC_1. By this operation, the wiring BL_1 and the capacitance element C0 are brought into a conductive state via the transistor OS1. When the wiring BL_1 and the capacitor C0 are brought into a conductive state, the voltage held in the capacitor C0 The potential of the wiring BL_1 varies according to the amount of charge.

[0143] In the timing chart shown in FIG. 14, when the amount of charge held in the capacitance element C0 is large, When the amount of charge held in the capacitance element C0 is large, When the charge is released to BL_1, the potential of the wiring BL_1 decreases by ΔV4 from the potential Vn11. Conversely, when the amount of charge held in the capacitance element C0 is small, the When a charge flows into the capacitance element C0, the potential of the wiring BL_1 drops by ΔV5 (not shown). To descend.

[0144] When the potential of the wiring BL_1 rises by ΔV4 from the potential Vn11, Therefore, the potential of the node N12 also rises by ΔV6. and the potential rises by ΔV6 from the intermediate potential Vn12 according to the characteristics of the transistor 24. , the inverter formed by the transistor 22 and the transistor 24 is connected to the low potential power supply VL_ Output SN.

[0145] Note that during the period T2, a low-level potential VL_CSEL is applied to the wiring CSEL. In the switch circuit 63, the transistors 25 and 26 are turned off. The status is maintained.

[0146] Next, in a period T3, the transistors 33 and 34 of the amplifier circuit 62 is turned on, and the amplifier circuit 62 outputs to the wiring BL_1 and the wiring BL_2. , a high-level potential VH_PL is applied to the wiring PL3, and the transistor 33 and transistor 34 are turned on.

[0147] In the case of FIG. 14 (when the amount of charge held in the capacitance element C0 is large), in the amplifier circuit 62 When the transistors 33 and 34 are turned on, the amplifier circuit 62 is connected to the wiring BL_ 2, the low potential power supply VL_SN is output. The potential of the wiring BL_2 is Vn12 to the low potential power supply V As the potential at node N11 approaches L_SN, the potential at node N11 drops via capacitance element C11, and the transistor The inverter formed by the transistor 21 and the transistor 23 is connected to the high potential power supply VH_SP. Then, the amplifier circuit 62 outputs the high potential power supply VH_SP to the wiring BL_1, The potential of BL_1 approaches the high potential power supply VH_SP from Vn11+ΔV4. The potential of the capacitor C12 also rises via the capacitor C12.

[0148] At the beginning of the period T3, the amount of charge held in the capacitance element C0 is small, and the wiring BL_ When the potential of transistor 1 is Vn11-ΔV5, transistor 33 and transistor 34 When this is turned on, the potential of the wiring BL_2 approaches the high potential power supply VH_SP from Vn12. As the potential of the wiring BL_1 increases, it approaches the low potential power supply VL_SN from the potential Vn11-ΔV5. It goes on.

[0149] In addition, during the period T3, a low-level potential VL_CSEL is applied to the wiring CSEL. In the switch circuit 63, the transistors 25 and 26 are turned off. The high-level potential VH_WL is applied to the wiring WL_1. In the memory cell MC_1, the transistor OS1 remains on. Therefore, in the memory cell MC_1, a charge according to the potential VH_SP of the wiring BL_1 is stored in the capacitor. It is stored in element C0.

[0150] In the period T4, the potential applied to the wiring CSEL is controlled to turn on the switch circuit 63. Specifically, a high-level potential VH_CSEL is applied to the wiring CSEL, and the switch circuit Path 63 turns on transistors 25 and 26. This turns on the The potential of the line BL_1 is supplied to the wiring GBL_1, and the potential of the wiring BL_2 is supplied to the wiring GBL_2. Supplied.

[0151] During the period T4, the high-level potential VH_WL is still applied to the wiring WL_1. In the memory cell MC_1, the transistor OS1 is maintained in the on state. In the memory cell MC_1, a charge corresponding to the potential VH_SP of the wiring BL_1 is transferred to the capacitor C0 It remains accumulated in

[0152] When the period T4 ends, the potential applied to the wiring CSEL is controlled to turn on the switch circuit 63. Specifically, a low-level potential VL_CSEL is applied to the line CSEL, and the switch In the switch circuit 63, the transistor 25 and the transistor 26 are turned off. A low-level potential VL_PL is applied to the wiring PL3, and the transistor 3 3 and transistor 34 are turned off.

[0153] When the period T4 ends, the selection of the wiring WL_1 ends. A low-level potential VL_WL is applied to the memory cell MC_1 to turn on the transistor OS1. By the above operation, a charge according to the potential VH_SP of the wiring BL_1 is transferred to the capacitance element C Even after the data is read, the data is still stored in the memory cell MC_1. It is stored in the

[0154] By the operations during the above-described periods T1 to T4, data is read from the memory cell MC_1. Data can be read from memory cell MC_2 in the same manner. do.

[0155] Data can also be written to the memory cells MC using the same principle as above. Specifically, as in the case of reading data, first, the transistor of the amplifier circuit 62 By turning on the transistor 31 and the transistor 32, the potentials of the nodes N11 and N12 are The amplifier circuit 62 is initialized and the transistors 33 and 34 are turned on. , the potentials of the wirings BL_1 and BL_2 are initialized.

[0156] Next, the wiring WL_1 connected to the memory cell MC_1 to which data is to be written, selects the wiring WL_2 connected to the memory cell MC_2, and In memory cell MC_2, transistor OS1 is turned on. L_1 or the wiring BL_2 and the capacitance element C0 are in a conductive state via the transistor OS1. becomes.

[0157] Next, the potential applied to the wiring CSEL is controlled to turn on the switch circuit 63. Wiring BL_1 and wiring GBL_1 are in a conductive state, and wiring BL_2 and wiring GBL_2 are in a conductive state. This is the state.

[0158] Then, by applying a write potential to each of the wiring GBL_1 and the wiring GBL_2, A write potential is applied to the wiring BL_1 and the wiring BL_2 via the switch circuit 63. By the above operation, charges are stored in the capacitor C0 according to the potential of the wiring BL_1 or the wiring BL_2. The data is written to the memory cell MC_1 or the memory cell MC_2.

[0159] The potential of the wiring GBL_1 is applied to the wiring BL_1, and the potential of the wiring GBL_2 is applied to the wiring BL_2. After the potential is applied, the transistors 25 and 26 in the switch circuit 63 Even if the power supply 26 is turned off, the relationship between the potential of the wiring BL_1 and the potential of the wiring BL_2 is amplified. It is maintained by circuit 62.

[0160] <Sense amplifier SA2> Next, regarding an example of the configuration of a sense amplifier different from the sense amplifier SA1 shown in FIG. 4, 5 will be used to explain.

[0161] The sense amplifier SA2 shown in FIG. 15 does not have a precharge circuit 64 and The circuit 62 does not have the capacitance elements C11 and C12, and therefore the sense amplifier S A1. An example of the configuration of the sense amplifier SA2 will be explained below. The same components as those of A1 will be described with reference to the description of the sense amplifier SA1.

[0162] FIG. 15 shows a memory cell MC and a sense amplifier SA2 electrically connected to the memory cell MC. The memory cell MC is connected to the sense amplifier SA2 via the wiring BL. Here, the memory cell MC_1 is connected to the sense amplifier SA2 via the wiring BL_1. The memory cell MC_2 is connected to the sense amplifier SA2 via the wiring BL_2. An example of the configuration is shown below.

[0163] The sense amplifier SA2 includes an amplifier circuit 62 and a switch circuit 63.

[0164] The amplifier circuit 62 includes p-channel transistors 21 and 22 and an n-channel The transistors 23 and 24 are of the same type as the transistors 31 to 34. and register 34.

[0165] Here, the n-channel transistors 31 to 34 are p-channel transistors. In FIG. 16, transistors 31 to 34 are p-channel The circuit configuration of the sense amplifier SA2 is shown in FIG. In this case, the gates of transistors 35 to 38 are connected to the logic To reverse the voltage, connect the inverter INV2 or inverter INV3 to the wiring PL2 or is connected to one end of the wiring PL3.

[0166] Alternatively, the n-channel transistors 31 to 34 may be analog switches. In FIG. 17, the transistors 31 to 34 are respectively The circuit configuration of the sense amplifier SA2 is as follows: An example is shown below.

[0167] Alternatively, the n-channel transistors 31 to 34 may be replaced with some kind of switch. 18 shows transistors 31 to 34. The circuit configuration example of the sense amplifier SA2 is shown in FIG. show.

[0168] The transistors 21 and 22 are explained in the same manner as in the sense amplifier SA1. .

[0169] One of the source and drain of the transistor 21 is connected to the wiring Vd. The other of the drains is connected to one of the source or drain of transistor 23 and the other of the drain of transistor 31. One of the source or drain of the transistor 33 and one of the source or drain of the transistor 34. The other of the source and drain of the transistor 23 is connected to a wiring (see FIG. 15). The other of the source and drain of the transistor 33 is connected to the wiring BL_1. The other of the source and drain of the transistor 31 is connected to the gate of the transistor 21. The gate of the transistor 23 and the wiring BL_2 are connected to the The gate of the transistor 31 is connected to the wiring PL2, and the gate of the transistor 33 is connected to the wiring PL3. is connected.

[0170] One of the source and drain of the transistor 22 is connected to the wiring Vd. The other of the drains is connected to one of the source or drain of transistor 24 and the other of the drains of transistor 32. One of the source or drain of transistor 34 and one of the source or drain of transistor 35. The other of the source and drain of the transistor 24 is connected to the wiring Vs. The other of the source and the drain of the transistor 34 is connected to the wiring BL_2. The other of the source and drain of transistor 32 is connected to the gate of transistor 22, The gate of the transistor 32 is connected to the wiring BL_1. The gate of transistor 34 is connected to wiring PL2, and the gate of transistor 35 is connected to wiring PL3. .

[0171] The wiring Vd is a wiring that supplies a high potential power supply VH_SP, and the wiring Vs is a wiring that supplies a low potential power supply VL_S The high potential power supply VH_SP and the low potential power supply VL_SN are That is, the high potential power supply VH There may be periods when V_SP and the low potential power supply VL_SN are supplied and periods when they are not. stomach.

[0172] The amplifier circuit 62 has a function of amplifying the potential of the wiring BL_1 and a function of amplifying the potential of the wiring BL_2. The sense amplifier SA2 having the amplifier circuit 62 shown in FIG. It functions as a sense amplifier of the same type.

[0173] The amplifier circuit 62 may have two amplifier circuits 66. An example of the circuit configuration of the sense amplifier SA2 when it has two width circuits 66 is shown in FIG. An example of the circuit configuration of the amplifier circuit 66 is shown in FIG.

[0174] As shown in FIG. 19A, the amplifier circuit 62 has two amplifier circuits 66. One amplifier circuit 66 has an input terminal IN2 and an output terminal OUT2. The other amplifier circuit is connected to the line BL_1, and the output terminal OUT2 is connected to the line BL_2. 66, the input terminal IN2 is connected to the wiring BL_2, and the output terminal OUT2 is connected to the wiring BL_1. Connected.

[0175] The amplifier circuit 66 includes a p-channel transistor 21 and an n-channel transistor 23. , transistor 31, and transistor 33.

[0176] One of the source and drain of the transistor 21 is connected to the wiring Vd. The other of the drains is connected to one of the source or drain of transistor 23 and the other of the drain of transistor 31. One of the source or drain of the transistor 33 and one of the source or drain of the transistor 34. The other of the source and drain of the transistor 23 is connected to the wiring Vs. The other of the source and drain of the transistor 33 is connected to the output terminal OUT2. The other of the source and drain of the transistor 31 is connected to the gate of the transistor 21. The gate of the transistor 23 is connected to the input terminal IN2. The gate of transistor 1 is connected to wiring PL2, and the gate of transistor 33 is connected to wiring PL3. are.

[0177] For the switch circuit 63, the description of the sense amplifier SA1 is cited.

[0178] <Operation example 1 of sense amplifier SA2> Next, regarding the memory cell MC and the sense amplifier SA2 shown in FIG. 15, An example of the operation will be described with reference to the timing chart shown in FIG.

[0179] During the period T1, the transistors 31 and 32 of the amplifier circuit 62 are turned on. Specifically, the potentials of the wirings PL_1 and BL_2 are initialized. A high-level potential VH_PL is applied to the amplifier circuit 62, and the transistors 31 and 32 are connected to the amplifier circuit 62. Transistor 32 is turned on.

[0180] The transistors 21 and 23 form an inverter. By turning on the inverter 31 and establishing a conductive state between the input and output of the inverter, The potential of L_2 is an intermediate potential according to the characteristics of the transistors 21 and 23. This potential is designated as Vbl2. The intermediate potential Vbl2 is applied to the transistor 21 and the transistor 22. The potential is determined by reflecting the influence of the characteristic variations of the transistors 21 and 23. The inverter formed by the transistor 23 operates in the following manner when the input potential changes from Vbl2. In this case, it can react sensitively.

[0181] Similarly, transistors 22 and 24 form an inverter. By turning on the transistor 32 and establishing a conductive state between the input and output of the inverter, The potential of the wiring BL_1 is an intermediate potential depending on the characteristics of the transistors 22 and 24. This potential is designated as Vbl1. The intermediate potential Vbl1 is The potential is determined by reflecting the influence of the characteristic variations of the transistor 24 and the transistor 25. The inverter formed by transistors 2 and 24 operates when the input potential changes from Vbl1. If it moves, it can react sensitively.

[0182] Note that during the period T1, a low-level potential VL_CSEL is applied to the wiring CSEL. In the switch circuit 63, the transistors 25 and 26 are in the off state. In addition, a low-level potential VL_WL is applied to the wiring WL_1, and the memory cell In the case of the cell MC_1, the transistor OS1 is in an off state. However, a low-level potential VL_WL is applied to the wiring WL_2, and the memory cell In the channel MC_2, the transistor OS1 is in an off state.

[0183] Next, a low-level potential VL_PL is applied to the wiring PL2, and the amplifier circuit 62 The transistor 31 and the transistor 32 are turned off.

[0184] At the timing when the low-level potential VL_PL is applied to the wiring PL2, the high-level potential VH_SP The supply of the high potential power supply VH_SP and the low potential power supply VL_SN may be stopped. By stopping the supply of the voltage source VL_SN, the transistors 21 and 23 are turned on. The through current flows through transistor 22 and transistor 24. This can prevent through current from flowing through the high potential power supply VH_SP and When the supply of the low potential power supply VL_SN is stopped, the wiring PL At the timing when a high level potential VH_PL is applied to the high potential power supply VH_SP and the low potential power supply VH_PL The supply of the potential power supply VL_SN is restored.

[0185] In the period T2, the wiring WL_1 is selected. Specifically, a high-level potential is applied to the wiring WL_1. VH_WL is applied to turn on the transistor OS1 in the memory cell MC_1. By this operation, the wiring BL_1 and the capacitance element C0 are brought into a conductive state via the transistor OS1. When the wiring BL_1 and the capacitor C0 are brought into a conductive state, the voltage held in the capacitor C0 The potential of the wiring BL_1 varies according to the amount of charge.

[0186] In the timing chart shown in FIG. 20, when the amount of charge held in the capacitance element C0 is large, When the amount of charge held in the capacitance element C0 is large, By discharging the charge to BL_1, the potential of the wiring BL_1 is reduced by ΔV7 from the potential Vbl1. Conversely, when the amount of charge held in the capacitance element C0 is small, the When a charge flows into the capacitance element C0, the potential of the wiring BL_1 drops by ΔV8 (not shown). To descend.

[0187] The potential of the wiring BL_1 is an intermediate potential according to the characteristics of the transistors 22 and 24. When the voltage rises by ΔV7 from the potential Vbl1, the transistors 22 and 24 are formed. The inverter outputs the low potential power supply VL_SN.

[0188] Note that during the period T2, a low-level potential VL_CSEL is applied to the wiring CSEL. In the switch circuit 63, the transistors 25 and 26 are turned off. The status is maintained.

[0189] Next, in a period T3, the transistors 33 and 34 of the amplifier circuit 62 is turned on, and the amplifier circuit 62 outputs to the wiring BL_1 and the wiring BL_2. , a high-level potential VH_PL is applied to the wiring PL3, and the transistor 33 and transistor 34 are turned on.

[0190] In the case of FIG. 20 (when the amount of charge held in the capacitance element C0 is large), in the amplifier circuit 62 When the transistors 33 and 34 are turned on, the amplifier circuit 62 is connected to the wiring BL_ 2, the low potential power supply VL_SN is output. The potential of the wiring BL_2 is Vbl2 to the low potential power supply V As we approach L_SN, the inverter formed by transistors 21 and 23 The amplifier 62 outputs a high voltage power supply VH_SP to the wiring BL_1. The potential of the wiring BL_1 is Vbl1+ΔV7, which is the high potential power supply VH Approaching the SP.

[0191] At the beginning of the period T3, the amount of charge held in the capacitance element C0 is small, and the wiring BL_ When the potential of transistor 33 is Vbl1-ΔV8, the potential of transistor 34 is Vbl1-ΔV8. When this is turned on, the potential of the wiring BL_2 approaches the high potential power supply VH_SP from Vbl2. As the potential of the wiring BL_1 increases, it approaches the low potential power supply VL_SN from the potential Vbl1-ΔV8. It goes on.

[0192] In addition, during the period T3, a low-level potential VL_CSEL is applied to the wiring CSEL. In the switch circuit 63, the transistors 25 and 26 are turned off. The high-level potential VH_WL is still applied to the wiring WL_1. In the memory cell MC_1, the transistor OS1 is maintained in the on state. In the memory cell MC_1, a charge corresponding to the potential VH_SP of the wiring BL_1 is transferred to the capacitor C0 is accumulated in

[0193] In the period T4, the potential applied to the wiring CSEL is controlled to turn on the switch circuit 63. Specifically, a high-level potential VH_CSEL is applied to the wiring CSEL, and the switch circuit Path 63 turns on transistors 25 and 26. This turns on the The potential of the line BL_1 is supplied to the wiring GBL_1, and the potential of the wiring BL_2 is supplied to the wiring GBL_2. Supplied.

[0194] During the period T4, the high-level potential VH_WL is still applied to the wiring WL_1. In the memory cell MC_1, the transistor OS1 is maintained in the on state. In the memory cell MC_1, a charge corresponding to the potential VH_SP of the wiring BL_1 is transferred to the capacitor C0 It remains accumulated in

[0195] When the period T4 ends, the potential applied to the wiring CSEL is controlled to turn on the switch circuit 63. Specifically, a low-level potential VL_CSEL is applied to the line CSEL, and the switch In the switch circuit 63, the transistor 25 and the transistor 26 are turned off. A low-level potential VL_PL is applied to the wiring PL3, and the transistor 3 3 and transistor 34 are turned off.

[0196] When the period T4 ends, the selection of the wiring WL_1 ends. A low-level potential VL_WL is applied to the memory cell MC_1 to turn on the transistor OS1. By the above operation, a charge according to the potential VH_SP of the wiring BL_1 is transferred to the capacitance element C Even after the data is read, the data is still stored in the memory cell MC_1. It is held in place.

[0197] By the operations during the above-described periods T1 to T4, data is read from the memory cell MC_1. Data can be read from memory cell MC_2 in the same manner. do.

[0198] Data can also be written to the memory cells MC using the same principle as above. Specifically, as in the case of reading data, first, the transistor of the amplifier circuit 62 By turning on the transistor 31 and the transistor 32, the potential of the wiring BL_1 and the wiring BL_2 is Initialize.

[0199] Next, the wiring WL_1 connected to the memory cell MC_1 to which data is to be written, selects the wiring WL_2 connected to the memory cell MC_2, and In memory cell MC_2, transistor OS1 is turned on. L_1 or the wiring BL_2 and the capacitance element C0 are in a conductive state via the transistor OS1. becomes.

[0200] Next, the potential applied to the wiring CSEL is controlled to turn on the switch circuit 63. Wiring BL_1 and wiring GBL_1 are in a conductive state, and wiring BL_2 and wiring GBL_2 are in a conductive state. This is the state.

[0201] Then, by applying a write potential to each of the wiring GBL_1 and the wiring GBL_2, A write potential is applied to the wiring BL_1 and the wiring BL_2 via the switch circuit 63. By the above operation, charges are stored in the capacitor C0 according to the potential of the wiring BL_1 or the wiring BL_2. The data is written to the memory cell MC_1 or the memory cell MC_2.

[0202] The potential of the wiring GBL_1 is applied to the wiring BL_1, and the potential of the wiring GBL_2 is applied to the wiring BL_2. After the potential is applied, the transistors 25 and 26 in the switch circuit 63 Even if the power supply 26 is turned off, the relationship between the potential of the wiring BL_1 and the potential of the wiring BL_2 is amplified. It is maintained by circuit 62.

[0203] <Operation example 2 of sense amplifier SA2> Regarding the memory cell MC and the sense amplifier SA2 shown in FIG. As in the second example of operation, in the period T1, the transistors 31 and 32 of the amplifier circuit 62 In addition to transistor 32, transistors 33 and 34 are also turned on. This can be done.

[0204] In this case, the capacitance elements C11 and C12 included in the sense amplifier SA1 are replaced with capacitance elements C11 and C12 included in the sense amplifier SA2. Since the amplifier SA2 is not provided, the wiring BL_1 and the wiring BL_2 are connected to the potential In other words, both the potential Vbl1 and the potential Vbl2 are output. The inverter formed by transistor 23 couples potential Vbl2 to transistor 22 and transistor 23. The inverter formed by the transistor 24 supplies the potential Vbl1 to the wiring BL_1 and the wiring Output to each of BL_2.

[0205] As a result, the potential of the wiring BL_1 and the wiring BL_2 is between the potential Vbl1 and the potential Vbl2. Both the potential Vbl1 and the potential Vbl2 are applied to the wiring BL_1 and the wiring BL_2. By outputting to each of the transistors BL_1 and BL_2, the potentials of the wirings BL_1 and BL_2 are The potentials can be set to intermediate potentials depending on the characteristics of the transistors 21 to 24.

[0206] As described above, according to one embodiment of the present invention, the characteristics of the transistors constituting the sense amplifier are not varied. By initializing the wiring and nodes to a potential that corresponds to the transistor characteristics, This allows the construction of a sense amplifier that is less susceptible to variations in transistor characteristics. Even if the influence of characteristic variations on power supply voltage increases due to miniaturization of capacitors and capacitive elements, A highly accurate sense amplifier can be configured. The methods can be combined as appropriate.

[0207] This embodiment may be implemented in appropriate combination with other embodiments described in this specification. It is possible.

[0208] (Embodiment 2) In this embodiment mode, an example of the semiconductor device illustrated in the above embodiment mode will be described with reference to FIGS. 24 will be used for the description. In the following, we will focus on metal oxides and Cloud-Aligned Carbon (CAC). This section explains the details of the composite.

[0209] <Configuration example of semiconductor device> 21(A), 21(B), 22(A), 22(B), and 23 show the configuration of the present invention. A transistor 200 according to one embodiment, a transistor 500, and a capacitor 100 6A and 6B are a top view and a cross-sectional view of a semiconductor device 600. The transistor 500 is a transistor having a back gate.

[0210] The semiconductor device 600 corresponds to a part of the amplifier circuit 62 in the sense amplifier SA1, Transistor 200 is connected to transistor 31, transistor 500 is connected to transistor 23, The capacitance element 100 corresponds to the capacitance element C11. transistor 32, transistor 500 is transistor 24, and capacitance element 100 is capacitance element C12. corresponds to:

[0211] In the amplifier circuit 62 of the sense amplifier SA1, the transistor 21 and the transistor When the transistor 22 is an n-channel transistor, the transistor 500 is a It may correspond to transistor 21 or transistor 22.

[0212] 21(A) is a top view of the semiconductor device 600. Also, FIGS. 21(B) and 22(A) 22(B) and 23 are cross-sectional views of the semiconductor device 600. FIG.

[0213] Here, FIG. 21(B) is a cross-sectional view of the portion indicated by the dashed line A1-A2 in FIG. 21(A). The channel length direction of the transistor 200 and the channel width direction of the transistor 500 are FIG. 22(A) shows a cross section of the portion indicated by the dashed line A3-A4 in FIG. 21(A). 22(B) is a cross-sectional view of the transistor 200 taken along the channel width direction. 21(A) is a cross-sectional view of the portion indicated by the dashed line A5-A6 in FIG. 21(A), and 21(A) shows a cross section of the channel length direction of 00. 1 is a cross-sectional view of the portion indicated by the dashed line, showing the source region or drain region of the transistor 200. In the top view shown in FIG. 21(A), some elements are omitted for clarity. The illustration omits elements.

[0214] The semiconductor device 600 includes a transistor 200, a transistor 500, a capacitor element 100, and , an insulator 210 serving as an interlayer film, an insulator 212, an insulator 273, an insulator 274, an insulator The insulating film 280 is electrically connected to the transistor 200 and functions as a wiring. The conductor 203 and the conductor 240 (conductor 240a, conductor 24 0b) and a conductive layer electrically connected to the transistor 500 and functioning as a wiring. The capacitor element 1 has a conductor 503 and a conductor 540a that functions as a plug. 00 and a conductor 540b that functions as a plug. In this case, the conductor 540a and the conductor 540b may be collectively referred to as the conductor 540. Here, the conductor 503 is formed in the same layer as the conductor 203, and the conductor 540 is formed in the same layer as the conductor 240. Therefore, the conductor 503 is the same as the conductor 203, and the conductor 540 is the same as the conductor 203. The description of the electric device 240 can be taken into consideration.

[0215] The conductor 203 is formed so that the first conductor is in contact with the inner wall of the opening of the insulator 212. The second conductor is formed further inside. Here, the height of the upper surface of the conductor 203 and the insulating In this embodiment, the height of the upper surface of the first conductor 203 can be set to be approximately the same. The present invention is not limited to the above embodiment, but may be modified in various ways. For example, the conductor 203 may be a single layer or a stack of three or more layers. In addition, when the structure has a laminated structure, the layers may be arranged in the order of formation. In addition, the conductor 503 has the same structure as the conductor 203. do.

[0216] The insulator 273 covers the transistor 200, the transistor 500, and the capacitor 100. Insulator 274 is disposed on insulator 273. Insulator 280 is disposed on insulator 27 4 is placed on top.

[0217] The conductor 240 is also formed on the inner walls of the openings of the insulators 273, 274, and 280. Here, the height of the upper surface of the conductor 240 and the height of the upper surface of the insulator 280 are In this embodiment, the conductor 240 has a two-layer laminated structure. However, the present invention is not limited to this configuration. The conductor 540 may have a single layer structure or a laminated structure of three or more layers. It has a similar configuration.

[0218] As shown in FIGS. 21 and 22A, the transistor 200 is disposed on a substrate (not shown). The insulators 214 and 216 are placed on the insulating material 214 and the insulators 216 are embedded in the insulating material 214 and the insulators 216. The conductor 205 is disposed so as to be embedded in the insulator 216 and the conductor 205. An insulator 220, an insulator 222 disposed on the insulator 220, and a and an oxide 230 (oxide 230a) disposed on the insulator 224. , oxide 230b, and oxide 230c), and an insulator 2 disposed on the oxide 230. 50, a metal oxide 252 disposed on the insulator 250, and a The conductor 260 (conductor 260a and conductor 260b) is connected to the an insulator 270 disposed on the insulating layer 271; and at least an acid The oxide 230c, the insulator 250, the metal oxide 252, and the conductor 260 are arranged in contact with each other. The insulating layer 275 is disposed on the insulating layer 275, and the layer 242 is formed on the oxide 230. A conductor 240a is disposed in contact with one side of 242.

[0219] In transistor 200, one of layers 242 functions as either the source or the drain. The other layer 242 functions as the other of the source and drain, and the conductor 260 is a fluororesin. The conductor 205 functions as a front gate and the conductor 24 functions as a back gate. 0b is electrically connected to a conductor corresponding to the wiring BL_1 or the wiring BL_2. The conductor 260 is electrically connected to a conductor corresponding to the wiring PL2.

[0220] As shown in FIGS. 21 and 22B, the transistor 500 has a substrate (not shown) The insulators 214 and 216 are disposed on the insulators 214 and 216. A conductor 505 is disposed so as to be embedded, and an insulator 216 is disposed on the conductor 505. an insulator 220 disposed on the insulator 220; an insulator 222 disposed on the insulator 220; An insulator 524 is disposed on the insulating layer 522, and an oxide 530 (oxide 530) is disposed on the insulating layer 522. 30a, oxide 530b, and oxide 530c) and an insulating layer disposed on oxide 530. An insulator 550, a metal oxide 552 disposed on the insulator 550, and a metal oxide 552 Conductors 560 (conductors 560a and 560b) arranged in the an insulator 570 disposed on the insulating layer 571; and The oxide 530c is in contact with the side surfaces of the insulator 550, the metal oxide 552, and the conductor 560. The insulating layer 575 is disposed over the oxide layer 530, and the insulating layer 575 is disposed over the oxide layer 530. A conductor 540a is disposed in contact with one side of the layer 542, and a conductor 540b is disposed in contact with the other side of the layer 542. 40b is placed.

[0221] In transistor 500, one of layers 542 functions as either the source or the drain. The other of the layers 542 functions as the other of the source and drain, and the conductor 560 is a fluororesin. The conductor 505 functions as a front gate and the conductor 56 functions as a back gate. 0 is electrically connected to the conductor 110 corresponding to the node N11 or the node N12.

[0222] Here, the transistor 500 is formed in the same layer as the transistor 200 and has the same configuration. Therefore, the oxide 530 has the same structure as the oxide 230, and the oxide 530 has the same structure as the oxide 230. The conductor 505 has the same structure as the conductor 205. The insulator 524 has the same structure as the insulator 224. The description of the insulator 224 can be taken into consideration. The insulator 550 is similar to the insulator 250. The description of the insulator 250 can be referred to. The oxide 252 has the same structure as the metal oxide 252, and the description of the metal oxide 252 can be referred to. The conductor 560 has the same configuration as the conductor 260, and the description of the conductor 260 can be taken into consideration. The insulator 570 has the same configuration as the insulator 270, and the description of the insulator 270 can be referred to. The insulator 571 has the same structure as the insulator 271. The insulator 575 has the same structure as the insulator 275. The description of the body 275 can be taken into consideration. In the following, unless otherwise specified, As such, the configuration of the transistor 500 can be understood by taking into consideration the description of the configuration of the transistor 200. can.

[0223] In the transistor 200, the oxide 230a, the oxide 230b, and the oxide 230 Although the configuration in which three layers of c are stacked is shown, the present invention is not limited to this. For example, a single layer of oxide 230b, a two-layer structure of oxide 230b and oxide 230a, Alternatively, a two-layer structure of the oxide 230b and the oxide 230c may be provided, or a laminated structure of four or more layers may be provided. The same is true for the oxide 530 of the transistor 500. In the example shown in FIG. 200, a conductor 260a and a conductor 260b are stacked. However, the present invention is not limited to this. The same applies to

[0224] The capacitance element 100 includes a conductor 110, an insulator 130 on the conductor 110, and a The conductor 120 is at least partially conductive via an insulator 130. It is preferable that the conductive member 110 is disposed so as to overlap the conductive member 110. The conductor 110 is the source or drain of the transistor 200. The openings in the insulators 570 and 571 are in contact with the layer 242 which serves as one of the insulators. It contacts with the conductor 560 via.

[0225] In the capacitor 100, the conductor 110 functions as one of the electrodes, and the conductor 120 functions as one of the electrodes. The insulator 130 functions as the dielectric of the capacitor element 100. The conductor 240b is electrically connected to the conductor corresponding to the wiring BL_1 or the wiring BL_2. Here, the conductor 110 is connected to either the source or the drain of the transistor 200, and the gate of the transistor 500, and is connected to the node N11 or the node N12. It functions as such.

[0226] As shown in FIG. 21A, a part of the capacitance element 100 is connected to the transistor 200 and the transistor The transistor 200 is formed so as to overlap with the transistor 500. The total projected area of ​​the capacitor 500 and the capacitor element 100 is reduced, and the occupation area of ​​the semiconductor device 600 is reduced. The area required can be reduced, and therefore the semiconductor device can be easily miniaturized and highly integrated. In addition, the transistor 200, the transistor 500, and the capacitor element 100 are Since the film can be formed in one step, the process can be shortened and productivity can be improved.

[0227] In the semiconductor device 600, the channel length direction of the transistor 200 and the The transistor 200, the transistor 500, and the transistor 500 are arranged so that the channel length directions of the transistors are perpendicular to each other. However, the semiconductor device shown in this embodiment is not limited to this. It's not that.

[0228] Next, a detailed description of the oxide 230 used in the transistor 200 will be given. Unless otherwise specified, the oxide 530 of the transistor 500 is also the oxide 23 The transistor 200 has a region where a channel is formed (a region where a gate electrode is formed). The oxide 230 (oxide 230a, oxide 230b, and and oxide 230c), a metal oxide (also called an oxide semiconductor) that functions as an oxide semiconductor. ) is preferably used.

[0229] The transistor 200 using an oxide semiconductor for a channel formation region has an extremely low Since the leakage current is extremely small, a semiconductor device with low power consumption can be provided. Since the body can be formed into a film by a sputtering method or the like, it can be used to form a highly integrated semiconductor device. It can be used for the transistor 200.

[0230] For example, the oxide 230 may be an In-M-Zn oxide (wherein the element M is aluminum, gallium, or the like). Aluminum, yttrium, copper, vanadium, beryllium, boron, titanium, iron, nickel, gel Al, zirconium, molybdenum, lanthanum, cerium, neodymium, hafnium, one or more selected from the group consisting of tantalum, tungsten, and magnesium, etc. It is preferable to use a metal oxide. In addition, the oxide 230 may be an In-Ga oxide or an In-Zn oxide. An oxide may also be used.

[0231] Here, the oxide semiconductor contains aluminum, ruthenium, and the like in addition to the elements constituting the oxide semiconductor. By adding metal elements such as aluminum, titanium, tantalum, chromium, and tungsten, Preferably, aluminum, titanium, or tantalum is used to form a metal compound and reduce the resistance. , tungsten, etc. are preferably used.

[0232] To add a metal element to an oxide semiconductor, for example, the metal element is deposited on the oxide semiconductor. It is preferable to provide a metal film containing a metal element, a nitride film containing a metal element, or an oxide film containing a metal element. In addition, by providing the film, a metal oxide film positioned at the interface between the film and the oxide semiconductor or in the vicinity of the interface can be formed. A part of oxygen in the oxide semiconductor placed in the film is absorbed by the film, etc., to form oxygen vacancies, and the boundary The resistance near the surface may become low.

[0233] Further, a metal film, a nitride film containing a metal element, or an oxide film containing a metal element may be formed on an oxide semiconductor. After the oxide film is formed, it is preferable to perform a heat treatment in an atmosphere containing nitrogen. By heat treatment, a metal film, a nitride film containing a metal element, or an oxide film containing a metal element is converted into The metal element that is a component of the film is converted into an oxide semiconductor, or the metal element that is a component of the oxide semiconductor is converted into an oxide semiconductor. The element diffuses into the film, and the oxide semiconductor and the film form a metal compound, resulting in a low resistance. The metal element added to the oxide semiconductor can be a metal element of the oxide semiconductor and a metal By forming a compound, the state becomes relatively stable, providing highly reliable semiconductor devices. It is possible.

[0234] In addition, a metal film, a nitride film containing a metal element, or an oxide film containing a metal element and an oxide semiconductor A compound layer (hereinafter also referred to as a hetero layer) may be formed at the interface with the body. The layer (different layer) is a metal film, a nitride film containing a metal element, or an oxide film containing a metal element. For example, the compound layer may be a layer having a metal compound containing a component of an oxide semiconductor and a component of an oxide semiconductor. Thus, a layer in which the metal element of the oxide semiconductor and the added metal element are alloyed is formed. The alloyed layer is in a relatively stable state, and provides a highly reliable semiconductor device. It can be provided.

[0235] In addition, hydrogen present in the oxide semiconductor diffuses into the low-resistance region of the oxide semiconductor, When the oxygen enters the oxygen vacancies in the oxidized region, it becomes relatively stable. The hydrogen in the oxygen vacancies in the semiconductor is released from the oxygen vacancies by heat treatment at 250°C or higher. The oxide semiconductor is then released from the oxide semiconductor, diffuses into the low-resistance region, and reacts with the oxide present in the low-resistance region. It is known that the lattice structure is in a relatively stable state after heat treatment. Therefore, the region where the resistance of the oxide semiconductor is reduced or the region where the metal compound is formed has a lower resistance. Oxide semiconductors that have not been made low-resistance are highly purified (reduced impurities such as water and hydrogen) and tends to have a higher resistance.

[0236] In addition, when an impurity element such as hydrogen or nitrogen is present in an oxide semiconductor, the carrier density The hydrogen in the oxide semiconductor reacts with the oxygen that bonds with the metal atoms to form water, and the When hydrogen enters the oxygen vacancy, the carrier density increases. In addition, some of the hydrogen bonds with oxygen, which bonds with metal atoms, to generate electrons, which act as carriers. That is, the resistance of an oxide semiconductor containing nitrogen or hydrogen is reduced.

[0237] Therefore, metal elements and impurity elements such as hydrogen and nitrogen are selected for the oxide semiconductor. By selectively adding ZnO, a high-resistance region and a low-resistance region can be formed in the oxide semiconductor. In other words, by selectively reducing the resistance of the oxide 230, the oxide 23 processed into an island shape can be 0, there is a region that functions as a semiconductor with a low carrier density, and a source region or a drain region. It is possible to provide a region with low resistance that functions as a barrier.

[0238] Here, the oxide 230b selectively made low-resistance is enclosed by a dashed line in FIG. 21(B). An expanded view of region 239 is shown in FIG.

[0239] As shown in FIG. 24, the oxide 230 serves as a channel forming region for the transistor. The region 234 and the region 231 (region 231a) functioning as a source region or a drain region. and region 231b), and region 232 (region 234) provided between region 231 and region 234. The region 232 has a first region 232a and a second region 232b.

[0240] The region 231 that functions as a source region or a drain region has a low oxygen concentration and low resistance. The region 234 that functions as a channel forming region is a source region or has a higher oxygen concentration and a lower carrier density than the region 231 that functions as the drain region. The region 232 is a high resistance region. The region 232 also functions as a source region or a drain region. The oxygen concentration is higher and the carrier density is lower than that of the region 231, and the region 232 is used as a channel forming region. This region has a lower oxygen concentration and a higher carrier density than the region 234 that functions as a gate electrode.

[0241] The region 231 contains at least metal elements and impurity elements such as hydrogen and nitrogen. Preferably, the concentration of one of the regions is higher than that of the region 232 and the region 234 .

[0242] For example, the region 231 contains aluminum, ruthenium, and the like in addition to the metal elements contained in the oxide 230. Any of the metallic elements selected from aluminum, titanium, tantalum, tungsten, chromium, etc. It is preferable to have one or more metal elements.

[0243] To form the region 231, for example, a film having a metal element is provided in contact with the oxide 230. After the region 231 is formed, the film containing the metal element is patterned into an island shape. The film containing the metal element is a metal film, a film containing a metal element, or the like. An oxide film containing a metal element or a nitride film containing a metal element can be used. A layer 242 may be formed at the interface between the film having the oxide 230 and the oxide film. Layer 242 may be formed on the top and sides of oxide 230. Note that layer 242 may be formed on the top and sides of oxide 230. a layer having a metal compound containing a component of the film having the metal element and a component of the oxide 230; For example, the layer 242 may be a metal element in the oxide 230. The added metal element may form an alloy layer.

[0244] By adding a metal element to the oxide 230, a metal compound is formed in the oxide 230. This can reduce the resistance of the region 231. Note that the metal compound does not necessarily have to be an oxide. For example, the metal element may not be formed in the conductive material 230. 0), a metal compound may be formed on the surface of the oxide 230. The layer 242 is formed on the surface of the conductor 110 or at the interface between the conductor 110 and the oxide 230. It may also be included.

[0245] Therefore, the region 231 may also include a low resistance region of the layer 242. If at least a portion of the transistor 200 functions as a source region or a drain region, There is a match.

[0246] Region 232 has an area overlapping with insulator 275. Region 232 is made of aluminum, Metallic elements such as ruthenium, titanium, tantalum, tungsten, and chromium, as well as hydrogen and and nitrogen, the concentration of at least one of the impurity elements is preferably higher than that of region 234. For example, by providing a film containing the above metal element in contact with the region 231 of the oxide 230, The component in the film containing the metal element and the component in the oxide semiconductor form a metal compound. The metal compound may attract hydrogen contained in the oxide 230. Therefore, the concentration of hydrogen in the region 232 near the region 231 may become high.

[0247] Note that either or both of the region 232a and the region 232b are connected to the conductor 260. The conductor 260 and the region 260 may be overlapped. 232a and region 232b are allowed to overlap.

[0248] Also, in FIG. 24, regions 234, 231, and 232 are formed in oxide 230b. For example, but not limited to, these regions are formed by layer 242, layer 242 and oxide The compound layer formed between the oxide 230, the oxide 230a, and the oxide 230c also have a shape. 24, the boundaries of each region may be formed with respect to the top surface of the oxide 230. Although the display is shown almost vertically, this embodiment is not limited to this. 32 protrudes toward the conductor 260 near the surface of the oxide 230b, and In the vicinity, the shape may recede toward the conductor 240a or the conductor 240b.

[0249] Also, in oxide 230, the boundaries between the regions may be difficult to clearly detect. The concentrations of metal elements and impurity elements such as hydrogen and nitrogen detected in each region are Not only is there a gradual change between each area, but there is also a continuous change within each area (also called gradation) That is, the closer to the channel forming region, the more the metal elements and water It is sufficient that the concentrations of impurity elements such as silicon and nitrogen are reduced.

[0250] To selectively reduce the resistance of the oxide 230, for example, aluminum, ruthenium, titanium, It contains metal elements such as tantalum, tungsten, and chromium that increase electrical conductivity, as well as a small amount of impurities. At least one of the impurities may be added to the desired region. For example, the element may be an element that can be captured by oxygen vacancies. Examples of suitable elements include hydrogen, boron, carbon, nitrogen, fluorine, phosphorus, sulfur, chlorine, and rare gases. Representative examples of rare gases include helium, neon, argon, krypton, and xenonium. There are others.

[0251] The region 231 contains the above-mentioned metal element for increasing conductivity, an element for forming oxygen vacancies, or an oxygen vacancy. By increasing the content of elements that are captured by the losses, the carrier density is increased and resistance is reduced. It is possible.

[0252] In order to reduce the resistance of the region 231, for example, the above-mentioned gold is provided in contact with the region 231 of the oxide 230. The film containing the metal element may be a metal film, a metal element film, or a film containing the metal element. An oxide film containing a metal element, a nitride film containing a metal element, or the like can be used. The film containing the elements includes at least an insulator 250, a metal oxide 252, a conductor 260, an insulating material, and a metal oxide 252. The insulating layer 270, the insulating layer 271, and the insulating layer 275 may be disposed on the oxide 230. It is preferable that the film containing the metal element has a thickness of 10 nm or more and 200 nm or less. The film containing the metal element may be, for example, aluminum, ruthenium, titanium, or titanium. The film contains a metal element such as aluminum, tungsten, or chromium. The film is formed by sputtering, CVD, MBE, PLD, or ALD. This can be done using

[0253] The oxide 230 comes into contact with the film containing the metal element, and the film containing the metal element The components of the oxide 230 and the components of the oxide 230 form a metal compound, which reduces the resistance and forms a region 231. In addition, at the interface between the oxide 230 and the film containing the metal element, or in the vicinity of the interface, A portion of the oxygen in the oxide 230 located therein is absorbed into the layer 242, creating oxygen vacancies in the oxide 230. In some cases, a region 231 is formed by forming a thin film and reducing the resistance.

[0254] In addition, when the oxide 230 and the film containing the metal element are in contact with each other, the oxide 230 is heated in an atmosphere containing nitrogen. By the heat treatment, the metal element is removed from the film containing the metal element. The metal element, which is a component of the film having the metal element, is converted into the oxide 230 or the component of the oxide 230 The metal element diffuses into the film containing the metal element, and the oxide 230 and the metal element are The oxide 230 and the film containing the metal compound form a metal compound, which reduces the resistance. A layer 242 is formed between the film containing the metal element and the oxide 230. The element may be alloyed with the metal element of the film containing the metal element. The alloy may contain alloys. The alloys are in a relatively stable state and are used in highly reliable semiconductor devices. Placement can be provided.

[0255] The heat treatment is carried out at a temperature of, for example, 250°C or higher and 650°C or lower, preferably 300°C or higher and 500°C or lower. The heat treatment may be carried out at a temperature of 320°C or higher and more preferably 450°C or lower. The heat treatment may be carried out under reduced pressure. After heat treatment in an inert gas atmosphere, heat treatment may be performed in an atmosphere containing an oxidizing gas. .

[0256] Furthermore, hydrogen in the oxide 230 diffuses into the region 231, and oxygen vacancies present in the region 231 are filled. When the water enters the oxygen vacancy in the region 234, it becomes relatively stable. The element escapes from the oxygen vacancy by heat treatment at 250° C. or higher, diffuses into the region 231, and The oxygen enters the oxygen vacancies present in the region 231 and becomes relatively stable. Therefore, the region 231 has a lower resistance, and the region 234 has a higher purity (free of impurities such as water and hydrogen). This reduces the resistance and makes the material more resistive.

[0257] On the other hand, regions 234 and 232 of oxide 230 are covered by conductor 260 and insulator 275. The oxide 230 region 234, In the region 232, the oxygen atoms in the oxide 230 have the above-mentioned metal element. This prevents absorption into the membrane.

[0258] In addition, the film containing the metal element is provided with a region 231 of oxide 230 and a region adjacent to the region 231. The oxygen in the region 232 is absorbed, and oxygen vacancies are formed in the region 231 and the region 232. Hydrogen in the oxide 230 enters the oxygen vacancies, forming a region 231. The carrier density in the region 231 of the oxide 230 and the region 232 increases. The region 232 is made to have a low resistance.

[0259] Here, when the film containing the metal element has the property of absorbing hydrogen, the oxide 230 The hydrogen is absorbed into the film, thus reducing the hydrogen impurities in the oxide 230. The film containing the metal element is subsequently patterned into the conductor 110. Thus, most of the absorbed hydrogen is removed from the oxide 230.

[0260] After forming the layer 242, a part of the film containing the metal element is removed to form the island-shaped conductor 11. The thickness of the film containing the metal element is made sufficiently thick, for example, 10 nm to 200 nm. By setting the thickness to about m or less, the conductor 110 can be given sufficient conductivity. The conductor 110 also has a thickness of 10 nm to 200 nm, similar to the film containing the metal element. The following are preferred, for example aluminum, ruthenium, titanium, tantalum, tungsten. It is preferable that the conductor 110 contains a metal element such as chromium. Alternatively, the film may be an oxide film containing a metal element or a nitride film containing a metal element.

[0261] A layer 242 is formed between the conductor 110 and the oxide 230. The layer 242 is formed by the metal element. The metal element of the film having the element and the metal element of the oxide 230 may be alloyed. The resistance between the conductor 110 and the region 231b may be reduced.

[0262] As shown in FIG. 21(B), the conductor 110 is formed by passing through the openings of the insulators 570 and 571. The transistor 500 is connected to a conductor 560, which functions as the gate of the transistor 500, via the gate electrode 560. By using a conductor 110 with sufficient conductivity, the transistor 200 and the transistor 500, and the initialized voltage at node N11 or node N12 Furthermore, the transistor 200 and the transistor By forming the pad 500 in the same layer and connecting it with the conductor 110, an extra plug is formed, The transistor 200 and the transistor 500 do not need to be connected in the upper or lower layer. The number of plugs to be formed in the layer in which the transistor 200 and the transistor 500 are formed is determined as follows: Therefore, the transistor 200 and the transistor 5 can be connected through the plug. It is possible to suppress the diffusion of impurities such as hydrogen into 00.

[0263] Here, in a transistor using an oxide semiconductor, a channel is formed in the oxide semiconductor. If impurities and oxygen vacancies exist in the region, the electrical characteristics may be easily changed, resulting in poor reliability. In addition, there are cases where oxygen vacancies exist in the region where the channel is formed in the oxide semiconductor. Therefore, the region where the channel is formed is likely to be normally on. It is preferred that oxygen vacancies in region 234 be reduced as much as possible.

[0264] 24, the insulator 250, the region 232 of oxide 230b, and the oxide In contact with the object 230c, more oxygen than the oxygen required for the stoichiometric composition (also called excess oxygen) is In other words, it is preferable to provide the insulator 275 containing excess oxygen. diffuses into the region 234 of the oxide 230, Oxygen deficiency can be reduced.

[0265] In order to provide an excess oxygen region in the insulator 275, the insulator 273 and the insulator 275 are The oxide film is preferably formed by sputtering. By using this method, it is possible to form an insulator film with few impurities such as water or hydrogen. When using the sputtering method, for example, a facing target type sputtering device can be used. It is preferable to form a film using a facing target sputtering device. Since the surface to be coated is not exposed to the high electric field region between the targets, Deposition of an insulator film that is less susceptible to plasma damage and becomes insulator 273 This is preferable because it can reduce film formation damage to the oxide 230. The film formation method using a jet-type sputtering device is called VDSP (Vapor Deposit Sputtering). The product can be referred to as ion SP (registered trademark).

[0266] When forming a film by sputtering, there are ions and sputtered materials between the target and the substrate. For example, the target is connected to a power source and is given a potential E0. In addition, the substrate is given a potential E1 such as a ground potential. It may be floating. In addition, there is an area between the target and the substrate that has a potential E2. The magnitude relationship of the potentials is E2>E1>E0.

[0267] Ions in the plasma are accelerated by the potential difference E2-E0 and collide with the target. The sputtered particles are ejected from the target. The film is formed by the deposition of ions on the surface of the film. The ions recoil from the nozzle, pass through the film formed as recoil ions, and reach the insulator in contact with the surface on which the film is to be formed. In addition, ions in the plasma may be trapped in the plasma due to the potential difference E2-E1. At this time, some ions reach the inside of the insulator 275. As the ions are trapped in the insulator 275, the region where the ions are trapped becomes It is formed in the insulator 275. That is, when the ions are ions containing oxygen, An excess oxygen region forms in the insulator 275 .

[0268] Introducing excess oxygen into the insulator 275 creates an excess oxygen region in the insulator 275. The excess oxygen in the insulator 275 is delivered to the region 234 of the oxide 230, and the oxide The oxygen deficiency of the oxide 230 can be compensated for.

[0269] The insulator 275 may be made of silicon oxide, silicon oxynitride, silicon nitride oxide, or a material having vacancies. It is preferable to use silicon oxide, which has an excess oxygen content. Materials such as silicon oxynitride are also suitable. On the other hand, compared to the above-mentioned silicon oxynitride and other materials, The oxide 230 is formed by sputtering an oxide film on the oxide 230. Therefore, the insulator 27 having the excess oxygen region is unlikely to form. 5 around the region 234 of the oxide 230, The excess oxygen in the insulator 275 can be effectively provided.

[0270] The insulator 273 is preferably made of aluminum oxide. By performing heat treatment in the state where the oxide 230 is in close proximity to the oxide 230, hydrogen in the oxide 230 is extracted. In addition, a layer 242 is provided between the oxide 230 and the aluminum oxide. When the aluminum oxide absorbs hydrogen in the layer 242, the hydrogen-reduced layer 242 becomes Therefore, the hydrogen concentration in the oxide 230 can be reduced. In addition, the heat treatment can be performed in a state where the insulator 273 and the oxide 230 are in close proximity. By doing this, oxygen is transferred from the insulator 273 to the oxide 230, the insulator 224, or the insulator 222. may be able to supply.

[0271] By combining the above configurations or steps, the resistance of the oxide 230 can be selectively reduced. It is possible to do so.

[0272] That is, when forming a low resistance region in the oxide 230, the conductor 2 60 and the insulator 275 are used as a mask, and the oxide 230 has low resistance in a self-aligned manner. Therefore, when multiple transistors 200 are formed at the same time, the voltage between the transistors is The channel length of the transistor 200 can be set as follows: The width of the conductor 260 is determined by the width of the conductor 260 and the thickness of the insulator 275. By using the minimum processing dimensions, the transistor 200 can be miniaturized.

[0273] From the above, by selecting the range of each area appropriately, it is possible to achieve a circuit design that meets the requirements. A transistor having the desired electrical characteristics can be easily provided.

[0274] In addition, oxide semiconductors can be deposited by sputtering or other methods, making them suitable for highly integrated semiconductors. The transistor can be used for a semiconductor device. Semiconductor transistors have extremely low leakage current (off-state current) when they are off. Therefore, a semiconductor device with low power consumption can be provided. Since the current is small, the initialized potential at the node N11 or the node N12 can be maintained for a long period of time. It can be held.

[0275] As described above, a semiconductor device including a transistor with large on-state current can be provided. Alternatively, a semiconductor device including a transistor with low off-state current can be provided. Also, fluctuations in electrical characteristics are suppressed, resulting in stable electrical characteristics and improved reliability. A semiconductor device can be provided.

[0276] The detailed configuration of the semiconductor device 600 will be described below. If the transistor 500 is not mounted, the detailed configuration of the transistor 200 will not be the same as the detailed configuration of the transistor 500. Please refer to the detailed description of the configuration.

[0277] As shown in FIG. 21(A) and FIG. 22(A), the conductor 203 extends in the channel width direction. The conductor 203 is extended and functions as a wiring for applying a potential to the conductor 203. is preferably embedded in the insulator 212.

[0278] The conductor 205 is disposed so as to overlap the oxide 230 and the conductor 260. The conductor 205 is preferably provided on and in contact with the conductor 203. Preferably, the insulating material 214 and the insulating material 216 are embedded therein.

[0279] Here, the conductor 260 functions as a first gate (also called a front gate) electrode. The conductor 205 may also be used as a second gate (also called a back gate) electrode. In this case, the potential applied to the conductor 205 may be changed to the potential applied to the conductor 260. The threshold voltage of the transistor 200 is controlled by changing the potential independently of the potential of the transistor 200. In particular, applying a negative potential to the conductor 205 can control the transistor. By increasing the threshold voltage of the transistor 200 to be greater than 0 V, it is possible to reduce the off-state current. Therefore, applying a negative potential to the conductor 205 increases the current density of the conductor 260 compared to when no negative potential is applied. This can reduce the drain current when the potential applied to is 0V.

[0280] In addition, by providing a conductor 205 on the conductor 203, the conductor 205 functions as a first gate electrode. The distance between the conductor 260 having the function of wiring and the conductor 203 is appropriately designed. That is, the insulator 214 and the insulator 215 are provided between the conductor 203 and the conductor 260. The provision of the conductive body 216 reduces the parasitic capacitance between the conductive body 203 and the conductive body 260. This allows the dielectric strength between the conductor 203 and the conductor 260 to be increased.

[0281] In addition, by reducing the parasitic capacitance between the conductor 203 and the conductor 260, the transistor 20 This improves the switching speed of the transistor and makes it possible to produce a transistor with high frequency characteristics. In addition, by increasing the dielectric strength between the conductor 203 and the conductor 260, the transistor Therefore, the reliability of the insulator 214 and the insulator 216 can be improved. It is preferable to make the film thickness thicker. The direction in which the conductor 203 extends is not limited to this. For example, it may be extended in the channel length direction of the transistor 200 .

[0282] As shown in FIG. 21(A), the conductor 205 is made of an oxide 230 and a conductor 260. The conductor 205 is arranged so as to overlap the region 234 of the oxide 230. In particular, as shown in FIG. 22(A), the conductor 205 is made of oxide 2 The region 234 of the channel 30 extends beyond the end portion thereof intersecting with the channel width direction. That is, it is preferable that the outer region of the side surface of the oxide 230 in the channel width direction In this case, it is preferable that the conductor 205 and the conductor 260 overlap with each other via an insulator. It's nice.

[0283] With the above configuration, when a potential is applied to the conductor 260 and the conductor 205, The electric field generated by the conductor 260 and the electric field generated by the conductor 205 are connected, and the oxide 230 This can electrically surround the channel forming region formed in the semiconductor layer.

[0284] That is, the electric field of the conductor 260 functioning as the first gate electrode and the electric field of the second gate electrode The electric field of the conductor 205, which functions as a pole, causes the channel forming region of the region 234 to In this specification, the first gate electrode and the second gate electrode The structure of a transistor in which the electric field of the gate electrode electrically surrounds the channel formation region is called This is called a surrounded channel (S-channel) structure.

[0285] The conductor 205 is in contact with the inner walls of the openings of the insulators 214 and 216. A first conductor is formed on the inner surface of the first conductive body, and a second conductor is further formed on the inner surface of the first conductive body. The height of the upper surface of the second conductor and the height of the upper surface of the insulator 216 can be made to be approximately the same. In the transistor 200, the first conductor of the conductor 205 and the second conductor of the conductor 205 Although a body stacking configuration is shown, the present invention is not limited to this. The conductor 205 may be configured as a single layer or a laminated structure of three or more layers.

[0286] Here, the first conductor of the conductor 205 or the conductor 203 is a hydrogen atom, a hydrogen molecule, or a water molecule. molecules, nitrogen atoms, nitrogen molecules, nitrogen oxide molecules (N2O, NO, NO2, etc.), copper atoms, etc. Use a conductive material that has the function of suppressing the diffusion of impurities (i.e., impurities are difficult to penetrate) Alternatively, it is preferable to have a function of suppressing the diffusion of oxygen (for example, oxygen atoms, oxygen molecules, etc.). It is preferable to use a conductive material that has the function of preventing oxygen from permeating. In the specification, the function of suppressing the diffusion of impurities or oxygen means the function of suppressing the diffusion of the impurities or the The function is to suppress the diffusion of one or all of the oxygen.

[0287] The first conductor of the conductor 205 or the conductor 203 has a function of suppressing the diffusion of oxygen. As a result, the second conductor of the conductor 205 or the conductor 203 is oxidized, and the conductivity decreases. The conductive material having the function of suppressing oxygen diffusion is For example, tantalum, tantalum nitride, ruthenium, or ruthenium oxide may be used. Therefore, the first conductor of the conductor 205 or the conductor 203 is preferably: The conductive material may be a single layer or a multilayer. This allows impurities such as hydrogen and water to be absorbed. Diffusion to the transistor 200 side is suppressed through the conductor 203 and the conductor 205. It is possible.

[0288] The second conductor of the conductor 205 is mainly composed of tungsten, copper, or aluminum. It is preferable to use a conductive material that has the following characteristics. Although shown in the figure, it may have a laminated structure, for example, titanium, titanium nitride and the above conductive material. It may also be laminated.

[0289] In addition, the second conductor of the conductor 203 functions as a wiring, so that the second conductor of the conductor 205 It is preferable to use a conductor having a higher conductivity than the conductor, for example, copper or aluminum. A conductive material containing rubber as a main component can be used. Alternatively, the conductive material may have a laminated structure, for example, a laminate of titanium, titanium nitride and the conductive material. Good too.

[0290] In particular, it is preferable to use copper for the conductor 203. Copper has low resistance and is therefore suitable for use in wiring, etc. On the other hand, copper is easily diffused, so it diffuses into the oxide 230 and This may cause a deterioration in the electrical characteristics of the transistor 200. Use materials such as aluminum oxide or hafnium oxide that have low copper permeability. This can suppress the diffusion of copper.

[0291] It should be noted that the conductor 205, the insulator 214, and the insulator 216 do not necessarily have to be provided. In this case, a part of the conductor 203 can function as a second gate electrode.

[0292] The insulators 210 and 214 prevent impurities such as water or hydrogen from penetrating the transistor from the substrate side. It is preferable that the insulating film functions as a barrier insulating film that prevents the inclusion of foreign matter in the transistor 200. Therefore, the insulators 210 and 214 are made of hydrogen atoms, hydrogen molecules, water molecules, and nitrogen atoms. , diffusion of impurities such as nitrogen molecules, nitrogen oxide molecules (N2O, NO, NO2, etc.), copper atoms, etc. It is preferable to use an insulating material that has the function of suppressing the impurities (i.e., the impurities are difficult to penetrate). Or, it has a function of suppressing the diffusion of oxygen (for example, oxygen atoms, oxygen molecules, etc.) (previous It is preferable to use an insulating material (which is difficult for oxygen to permeate). , an insulator that functions as a barrier insulating film similar to the insulator 210 or the insulator 214 is provided. This allows impurities such as water or hydrogen to penetrate through the insulator 280 and into the transistor. This can prevent the foreign matter from being mixed into the tank 200.

[0293] For example, aluminum oxide or the like is used as the insulator 210, and silicon nitride or the like is used as the insulator 214. It is preferable to use a capacitor or the like. The insulators 210 and 214 allow the insulation of hydrogen, water, etc. It is possible to prevent impurities from diffusing from the substrate side to the transistor 200 side. Alternatively, the insulators 210 and 214 may cause oxygen contained in the insulator 224 to be converted into a group. This can prevent diffusion to the plate side.

[0294] In addition, by forming a structure in which the conductor 205 is stacked on the conductor 203, An insulator 214 may be provided between the conductor 203 and the conductor 205. Even if a metal that easily diffuses, such as copper, is used for the second conductor, silicon nitride is used as the insulator 214. By providing the above, the metal can be prevented from diffusing into the layer above the insulator 214. This can be done.

[0295] The insulators 212, 216, and 280, which function as interlayer films, are insulating films. It is preferable that the dielectric constant of the insulating material is lower than that of the insulating material 210 or the insulating material 214. By using an interlayer film, the parasitic capacitance occurring between wirings can be reduced.

[0296] For example, the insulators 212, 216, and 280 may be silicon oxide, silicon dioxide, or the like. Silicon nitride, silicon oxide nitride, aluminum oxide, hafnium oxide, tantalum oxide, Zirconium oxide, lead zirconate titanate (PZT), strontium titanate (SrT Insulators such as (Ba,Sr)TiO3 or (Ba,Sr)TiO3 (BST) are used in single or multilayer configurations. Alternatively, these insulators may contain, for example, aluminum oxide, bismuth oxide, Germanium oxide, niobium oxide, silicon oxide, titanium oxide, tungsten oxide, iridium oxide Alternatively, tritium or zirconium oxide may be added to these insulators. Silicon oxide, silicon oxynitride or silicon nitride may be laminated on the insulator. It may be used.

[0297] The insulators 220, 222, and 224 function as gate insulators. In addition, the insulator 524 provided in the transistor 500 is also a gate insulator, similar to the insulator 224. In this embodiment, the insulator 224 and the insulator 524 are separated, but the insulator 224 and the insulator 524 may be connected.

[0298] Here, the insulator 224 in contact with the oxide 230 has more oxygen than the stoichiometric composition. In other words, the insulator 224 has an excess oxygen region. It is preferable that the insulator containing such excess oxygen is formed by bonding the oxide 230. By providing the oxide 230, oxygen vacancies in the oxide 230 are reduced, and the reliability of the transistor 200 is improved. It can improve the performance.

[0299] As an insulator having an excess oxygen region, specifically, an oxide film in which some oxygen is released by heating is used. It is preferable to use a material that releases oxygen when heated. Analysis (TDS (Thermal Desorption Spectroscopy) analysis ), the amount of oxygen released in terms of oxygen molecules is 1.0 × 10 18 molecules / c m 3 or more, preferably 1.0 × 10 19 molecules / cm 3 More than that, even more preferable 2.0 x 10 19 molecules / cm 3 or more, or 3.0 x 10 20 mol ecules / cm 3 The oxide film is as described above. The surface temperature range is between 100°C and 700°C, or between 100°C and 400°C. preferable.

[0300] Also, if the insulator 224 has an excess oxygen region, the insulator 222 may be oxygen-resistant (e.g., oxygen It has the function of suppressing the diffusion of oxygen molecules (element atoms, oxygen molecules, etc.) (the oxygen is less likely to permeate) is preferred.

[0301] The insulator 222 has a function of suppressing the diffusion of oxygen, and therefore the excess oxygen contained in the insulator 224 is prevented. The oxygen in the oxygen region is efficiently supplied to the oxide 230 without diffusing to the insulator 220 side. In addition, the conductor 205 reacts with the oxygen in the excess oxygen region of the insulator 224. This can suppress the response.

[0302] The insulator 222 may be, for example, aluminum oxide, hafnium oxide, tantalum oxide, or silica. lead zirconate titanate (PZT), strontium titanate (SrTiO3) or insulators containing so-called high-k materials such as (Ba,Sr)TiO3 (BST) It is preferable to use a single layer or a laminated layer. If the gate insulator is made thinner, problems such as leakage current may occur. By using a high-k material as an insulator, the physical thickness can be maintained. This makes it possible to reduce the gate potential during transistor operation.

[0303] In particular, it has the function of suppressing the diffusion of impurities and oxygen (the impurities and the oxygen One or both of aluminum and hafnium, which are insulating materials that are difficult for electrons to penetrate It is recommended to use an insulator containing oxide. Oxide-containing insulators include aluminum oxide, hafnium oxide, aluminum and hafnium oxide. It is preferable to use an oxide containing hafnium (hafnium aluminate). When the insulator 222 is formed using such a material, the insulator 222 is oxidized by the oxide 230. The release of impurities and the introduction of impurities such as hydrogen into the oxide 230 from the periphery of the transistor 200 are prevented. It acts as a suppressing layer.

[0304] Alternatively, for example, aluminum oxide, bismuth oxide, or germanium oxide may be added to these insulators. Niobium oxide, silicon oxide, titanium oxide, tungsten oxide, yttrium oxide, Alternatively, zirconium oxide may be added to these insulators, or these insulators may be nitrided. Silicon oxide, silicon oxynitride, or silicon nitride may be stacked on the insulator.

[0305] The insulator 220 is preferably thermally stable. For example, silicon oxide and Silicon oxide nitride and silicon oxynitride are suitable because they are thermally stable. Combining the insulator with silicon oxide or silicon oxynitride provides thermally stable and It is possible to obtain an insulator 220 having a laminated structure with a high dielectric constant.

[0306] The insulators 220, 222, and 224 each have a laminated structure of two or more layers. In this case, the laminated structure is not limited to the same material, and may be made of different materials. A laminated structure may also be used.

[0307] The oxide 230 is made up of an oxide 230a, an oxide 230b on the oxide 230a, and an oxide 23 The oxide 230a is formed on the oxide 230b. Therefore, the diffusion of impurities from the structure formed below the oxide 230a to the oxide 230b occurs. Furthermore, by having the oxide 230c on the oxide 230b, Diffusion of impurities from a structure formed above the oxide 230c to the oxide 230b It can be suppressed.

[0308] The oxide 230 has a layered structure made up of oxides with different atomic ratios of metal atoms. Specifically, it is preferable that the metal oxide used for the oxide 230a has a content of 0.01% or less among the constituent elements. The atomic ratio of element M is the atomic ratio of element M in the constituent elements of the metal oxide used for oxide 230b. It is preferable that the atomic ratio of M is larger than that of M. In addition, the metal oxide used for the oxide 230a is In the metal oxide used for the oxide 230b, the atomic ratio of the element M to In is It is preferable that the atomic ratio of element M to In is larger than that of element M. In the metal oxide used in the oxide 230a, the atomic ratio of In to element M is In the metal oxide, the atomic ratio of In to M is preferably larger than that of In. The oxide 230c is a metal oxide that can be used for the oxide 230a or the oxide 230b. can be used.

[0309] In addition, the energy of the conduction band minimum of the oxide 230a and the oxide 230c is It is preferable that the energy of the oxide is higher than the energy of the bottom of the conduction band of the oxide. The electron affinity of oxide 230a and oxide 230c is smaller than the electron affinity of oxide 230b. It is preferable.

[0310] Here, at the junctions of oxide 230a, oxide 230b, and oxide 230c, In other words, the oxide 230a, the oxide 230b, and The conduction band edge at the junction of the oxide 230c is also called a continuous junction. To achieve this, the interface between the oxide 230a and the oxide 230b, and the defect density of the intermixed layer formed at the interface between oxide 230b and oxide 230c. It is better to lower the level.

[0311] Specifically, oxide 230a and oxide 230b, and oxide 230b and oxide 230c are oxides. By having a common element other than the element (as the main component), a mixed layer with low defect level density is formed. For example, if oxide 230b is an In-Ga-Zn oxide, oxide 2 30a and oxide 230c, In-Ga-Zn oxide, Ga-Zn oxide, oxide Gallium or the like may be used.

[0312] At this time, the main path of the carriers is the oxide 230b. By configuring the oxide 230c as described above, the interface between the oxide 230a and the oxide 230b and the oxide The defect level density at the interface between the substrate 230b and the oxide 230c can be reduced. Therefore, the influence of interface scattering on carrier conduction is reduced, and the transistor 200 has a high On-current can be obtained.

[0313] The oxide 230 has a region 231, a region 232, and a region 234. At least a portion of the region 231 has an area adjacent to the insulator 273. has at least an area that overlaps with the insulator 275.

[0314] When the transistor 200 is turned on, the region 231a or the region 231b becomes a source. On the other hand, at least a portion of region 234 functions as a source region or a drain region. The region 232 is formed between the region 231 and the region 234. By providing the transistor 200 with the above structure, the on-state current is increased and the transistor 200 is prevented from The off-state current (off current) can be reduced.

[0315] In the transistor 200, the region 232 is provided to separate the source and drain regions. A high resistance region is formed between a region 231 that functions as a gate electrode and a region 234 where a channel is formed. Since no oxide film is formed, the on-state current and mobility of the transistor can be increased. Furthermore, by providing the region 232, the source region and the drain region are separated in the channel length direction. Since the region and the first gate electrode (conductor 260) do not overlap, unnecessary capacitance is not generated between them. Furthermore, by providing the region 232, it is possible to suppress the formation of leakage current when the semiconductor device is not electrically conductive. The flow can be reduced.

[0316] In other words, by selecting the range of each area appropriately, it is possible to obtain the power required to match the circuit design. It is possible to easily provide a transistor having such a characteristic. For example, the transistor 20 0 has a small off-state current, and the transistor 500 has a large on-state current. It is possible.

[0317] The oxide 230 is preferably a metal oxide that functions as an oxide semiconductor. For example, the metal oxide that becomes the region 234 has a band gap of 2 eV or more, preferably 2 It is preferable to use metals with a wide band gap of 0.5 eV or more. By using an oxide, the off-state current of a transistor can be reduced.

[0318] A transistor using an oxide semiconductor has extremely low leakage current in a non-conducting state. Therefore, a semiconductor device with low power consumption can be provided. Since the film can be formed using the above materials, it can be used for transistors that constitute highly integrated semiconductor devices. can be done.

[0319] The insulator 250 functions as a gate insulator. The insulator 250 is preferably an insulator that releases oxygen when heated. For example, it is preferable to form the film by using the oxygen atom converted by TDS analysis. The amount of desorption is 1.0×10 18 molecules / cm 3 or more, preferably 1.0 × 10 19 molecules / cm 3 More preferably, 2.0 × 10 19 molecu les / cm 3 or more, or 3.0 x 10 20 molecules / cm 3 Acid that is more than The surface temperature of the film during the TDS analysis was 100°C or higher and 70°C or lower. A range of 0°C or less is preferred.

[0320] Specifically, silicon oxide having excess oxygen, silicon oxynitride, silicon nitride oxide, and nitride silicon dioxide, fluorine-doped silicon dioxide, carbon-doped silicon dioxide, carbon and Nitrogen-doped silicon oxide and vacant silicon oxide can be used. Silicon oxide and silicon oxynitride are preferred because they are stable to heat.

[0321] An insulator that releases oxygen when heated is used as the insulator 250 and is attached to the top surface of the oxide 230c. By providing the insulating layer 250, oxygen can be effectively transferred from the insulating layer 250 to the region 234 of the oxide 230b. In addition, like the insulator 224, water or hydrogen in the insulator 250 can be supplied. It is preferable that the impurity concentration of the insulator 250 is reduced. It is preferable to set it to 20 nm or less.

[0322] In addition, in order to efficiently supply excess oxygen contained in the insulator 250 to the oxide 230, The metal oxide 252 may be provided. Thus, the metal oxide 252 prevents oxygen diffusion from the insulator 250. By providing the metal oxide 252 that suppresses the diffusion of oxygen, The diffusion of excess oxygen from the insulator 250 to the conductor 260 is suppressed. In addition, the reduction in the amount of excess oxygen supplied to the conductor 26 due to the excess oxygen can be suppressed. It is possible to suppress the oxidation of 0.

[0323] The metal oxide 252 may function as a part of the first gate electrode. For example, an oxide semiconductor that can be used as the oxide 230 can be used as the metal oxide 252. In this case, the conductor 260 can be formed as a film by sputtering. The electrical resistance of the oxide 252 can be reduced to make it a conductor. The electrode can be called a de Conductor electrode.

[0324] The metal oxide 252 may also function as part of the gate insulator. Therefore, when silicon oxide or silicon oxynitride is used for the insulator 250, the metal oxide 252 is preferably made of a metal oxide, which is a high-k material with a high relative dielectric constant. This laminated structure is stable against heat and has a high dielectric constant. Therefore, the gate voltage applied during transistor operation can be adjusted while maintaining the physical film thickness. In addition, the equivalent oxide thickness (E OT) can be made thinner.

[0325] Although the metal oxide 252 in the transistor 200 is shown as a single layer, it may have a stacked structure of two or more layers. For example, a metal oxide that functions as a part of the gate electrode and a gate insulator A metal oxide that functions as a part of the metal oxide may be laminated.

[0326] When the metal oxide 252 functions as a gate electrode, the conductor 260 The on-current of the transistor 200 can be improved without weakening the effect of the electric field. Alternatively, when it functions as a gate insulator, the insulator 250 and the metal oxide 252 are The physical thickness of the conductive material 260 and the oxide 230 maintains a distance between the conductive material 260 and the oxide 230. Therefore, the leakage current between the insulator 260 and the oxide 230 can be suppressed. 50 and the metal oxide 252, the conductor 260 and the oxide 23 0 and the electric field strength applied from the conductor 260 to the oxide 230. It can be easily adjusted as needed.

[0327] Specifically, by reducing the resistance of an oxide semiconductor that can be used for the oxide 230, Metal oxide 252 can be used. Alternatively, hafnium, aluminum, gallium Aluminum, yttrium, zirconium, tungsten, titanium, tantalum, nickel, germanium Metal oxide containing one or more metals selected from the group consisting of ammonium, magnesium, etc. Compounds can be used.

[0328] In particular, the insulator contains oxides of either or both of aluminum and hafnium. Aluminum oxide, hafnium oxide, oxides containing aluminum and hafnium (haf It is preferable to use hafnium aluminate. In particular, hafnium aluminate is It has higher heat resistance than hafnium oxide film. Therefore, it is possible to prevent crystallization during heat treatment in the subsequent process. It is preferable because it is difficult to convert the metal oxide 252 into the metal oxide. It may be designed appropriately depending on the transistor characteristics.

[0329] The conductor 260 functioning as the first gate electrode is made up of the conductor 260a and the conductor 260b. Conductor 260b is on conductor 260a. Conductor 260a is the same as the first conductor of conductor 205. hydrogen atoms, hydrogen molecules, water molecules, nitrogen atoms, nitrogen molecules, nitrogen oxide molecules (NO, NO, Conductive materials that have the function of suppressing the diffusion of impurities such as NO2 and copper atoms are used. Alternatively, it is preferable that the function of suppressing the diffusion of oxygen (for example, oxygen atoms, oxygen molecules, etc.) It is preferable to use a conductive material having the following properties.

[0330] The conductor 260a has a function of suppressing the diffusion of oxygen, and thus the insulator 250 and the gold The excess oxygen contained in the metal oxide 252 oxidizes the conductor 260b, causing a decrease in conductivity. Examples of conductive materials that have the function of suppressing oxygen diffusion include For example, it is preferable to use tantalum, tantalum nitride, ruthenium, or ruthenium oxide. Desirable.

[0331] The conductor 260b is made of a conductive material mainly composed of tungsten, copper, or aluminum. In addition, since the conductor 260 functions as a wiring, it is preferable to use a conductive material. It is preferable to use a highly conductive material, such as tungsten, copper, or aluminum. The conductive material having a main component of the conductive material 260b can be used. For example, a laminate of titanium, titanium nitride and the above conductive material may be used.

[0332] As shown in FIG. 22(A), the conductor 205 intersects with the channel width direction of the oxide 230. When the conductor 260 extends in a region outside the edge of the conductor 260, In this case, it is preferable that the conductor 205 overlaps with the insulator 250 interposed therebetween. In the outer region of the side of the oxide 230, the conductor 205, the insulator 250, and the conductor 26 0 preferably forms a laminated structure.

[0333] With the above configuration, when a potential is applied to the conductor 260 and the conductor 205, The electric field generated by the conductor 260 and the electric field generated by the conductor 205 are connected, and the oxide 230 This can electrically surround the channel forming region formed in the semiconductor layer.

[0334] That is, the electric field of the conductor 260 functioning as the first gate electrode and the electric field of the second gate electrode The electric field of the conductor 205, which functions as a pole, causes the channel forming region of the region 234 to It can be electrically surrounded.

[0335] Furthermore, an insulator 270 that functions as a barrier film may be placed on the conductor 260b. The insulator 270 has a function of suppressing the permeation of impurities such as water or hydrogen, and oxygen. It is advisable to use an insulating material, such as aluminum oxide or hafnium oxide. This prevents the conductor 260 from being oxidized by oxygen from above the insulator 270. In addition, it is possible to prevent water or hydrogen from entering from above the insulator 270. The impurities are mixed into the oxide 230 through the conductor 260 and the insulator 250. can be suppressed.

[0336] It is also preferable to place an insulator 271 on the insulator 270, which functions as a hard mask. By providing the insulator 271, the side surface of the conductor 260 is Approximately perpendicular, specifically, the angle between the side surface of the conductor 260 and the surface of the substrate is 75 degrees or more and 100 degrees or less. The angle can be preferably set to 80 degrees or more and 95 degrees or less. By processing the insulating material into a desired shape, the insulating material 275 to be formed next can be formed into a desired shape. .

[0337] The insulator 271 has a function of suppressing the permeation of impurities such as water or hydrogen, and oxygen. By using an insulating material having such a property, the insulating material may also function as a barrier film. The insulator 270 may not be provided.

[0338] The insulator 275, which functions as a buffer layer, is formed on the side of the oxide 230c and the side of the insulator 250. , a side of the metal oxide 252, a side of the conductor 260, a side of the insulator 270, and the insulator 2 It is installed adjacent to the side of 71.

[0339] For example, the insulator 275 may be silicon oxide, silicon oxynitride, silicon nitride oxide, silicon nitride, or silicon nitride. Silicon, fluorine-doped silicon oxide, carbon-doped silicon oxide, carbon and nitrogen It is preferable to use silicon oxide doped with silicon dioxide, silicon oxide having pores, or resin. In particular, silicon oxide and silicon oxynitride are preferable because they are thermally stable. In particular, silicon oxide and silicon oxide with vacancies can easily form excess oxygen regions in later processes. This is preferable because it can be formed.

[0340] The insulator 275 also preferably has an excess oxygen region. The insulator 275 is provided in contact with the oxide 230c and the insulator 250. This effectively supplies oxygen from the insulator 250 to the region 234 of the oxide 230b. In addition, the concentration of impurities such as water or hydrogen in the insulator 275 is reduced. It is preferable that:

[0341] It is preferable to use an insulator with a large relative dielectric constant for the insulator 130, such as the insulator 222. Any insulator that can be used may be used. For example, one of aluminum and hafnium Alternatively, an insulator containing oxides of both aluminum and hafnium can be used. Insulators containing one or both oxides include aluminum oxide, hafnium oxide, and aluminum. Hafnium and oxides containing hafnium (hafnium aluminate) can be used. The insulator 130 may also have a laminated structure, for example, silicon oxide, Silicon nitride, silicon oxynitride, silicon nitride, aluminum oxide, hafnium oxide , oxides containing aluminum and hafnium (hafnium aluminate), etc. For example, hafnium oxide, oxide It is preferable to form a laminated structure by depositing aluminum and hafnium oxide in this order. The thickness of the hafnium and aluminum oxide films is 0.5 nm or more and 5 nm or less, respectively. By using such a laminated structure, it is possible to obtain a capacitor with a large capacitance value and a small leakage current. It can be element 100.

[0342] As shown in FIG. 21(A), in the top view, the side surface of the insulator 130 is opposite to the conductor 110 and the The surface of the insulating material 120 is aligned with the side of the insulating material 120, but is not limited to this. Without patterning 130, the insulator 130 is formed on the transistor 200 and the transistor 5 It may be configured to cover 00.

[0343] The conductor 120 is made of a conductive material mainly composed of tungsten, copper, or aluminum. Although not shown, the conductor 120 may have a laminated structure. For example, a laminate of titanium, titanium nitride and the above conductive material may be used.

[0344] Insulator 273 includes at least layer 242, insulator 275, layer 542, insulator 575, and The insulator 273 is formed by sputtering. The body 275 and the insulator 575 can be provided with an excess oxygen region. Oxygen can be supplied from the excess oxygen region into oxide 230 and oxide 530. In addition, an insulator 273 is provided on the layer 242 of the oxide 230 and the layer 542 of the oxide 530. By this, hydrogen in the oxide 230 and the oxide 530 is extracted to the insulator 273. can be done.

[0345] For example, the insulator 273 may be hafnium, aluminum, gallium, yttrium, or di Zr, tungsten, titanium, tantalum, nickel, germanium, or magnesium It is possible to use a metal oxide containing one or more metals selected from the group consisting of cadmium, cadmium, and sulphur. Cut.

[0346] In particular, aluminum oxide has a high barrier property and is a thin film of 0.5 nm to 3.0 nm. Even if the temperature is low, the diffusion of hydrogen and nitrogen can be suppressed.

[0347] Further, an insulator 274 is provided over the insulator 273. The insulator 274 has a barrier property and It is preferable to use a film with a reduced hydrogen concentration. For example, the insulator 274 is a nitride film. Silicon oxide, silicon nitride, silicon oxide with fluorine added, etc. are preferably used. By providing the insulating film 273 having a heat-transmitting property and the insulating film 274 having a barrier property, It is possible to suppress the diffusion of impurities from other structures into the transistor 200. .

[0348] In addition, it is preferable to provide an insulator 280 that functions as an interlayer film on the insulator 274. The insulator 280, like the insulator 224, has a low impurity concentration such as water or hydrogen in the film. It is preferable that the thickness of the insulating material 280 is reduced. By forming the insulator by a sputtering method, impurities in the insulator 280 can be removed. It is possible to reduce the amount of

[0349] In addition, the conductor 2 is inserted into the openings formed in the insulator 280, the insulator 274, and the insulator 273. Conductor 40a, conductor 240b, conductor 540a, and conductor 540b are arranged. The conductor 40a and the conductor 240b are disposed opposite each other with the conductor 260 interposed therebetween. The conductor 240a and the conductor 540b are provided facing each other with the conductor 560 in between. The height of the top surfaces of the conductors 240b, 540a, and 540b is greater than that of the insulator 28. 0 may be on the same plane as the top surface of

[0350] The conductor 2 is in contact with the inner walls of the openings of the insulator 280, the insulator 274, and the insulator 273. At least a portion of the bottom of the opening is covered with a region 23 of oxide 230. 1a is located, and the conductor 240a contacts the region 231a. The same is true for 540b.

[0351] Here, as shown in FIG. 23, the conductor 240a may overlap the side surface of the oxide 230. In particular, the conductor 240a is preferably formed on the side surface of the oxide 230 intersecting with the channel width direction. Therefore, it is preferable that the side surface of the A7 side overlaps with both or one of the side surfaces of the A8 side. In addition, the conductor 240a is on the A1 side ( A2 side) of the source region. The oxide 230 is formed so as to overlap with the side of the region 231 which will be the gate or drain region. This increases the projected area of ​​the contact portion between the conductor 240a and the transistor 200. The contact area of ​​the contact portion is increased, and the contact between the conductor 240a and the transistor 200 is improved. This reduces the resistance of the source and drain electrodes of the transistor. The on-current can be increased while miniaturizing the electrode. The conductor 110 in contact with the region 231 that will become the source or drain region is also formed with an oxide 230. and layer 242. In addition, the conductors 540a and 540b are The same is true for

[0352] Conductor 240a, conductor 240b, conductor 540a, and conductor 540b are made of tungsten. It is preferable to use a conductive material whose main component is iron, copper, or aluminum. The conductors 240a, 240b, 540a, and 540b are laminated structures. It may also be possible to use the following.

[0353] Here, for example, when forming openings in the insulators 280, 274, and 273, Then, in the oxide 230, the low-resistance region of the region 231 is removed, and the low-resistance region is removed. In this case, the oxide 230 of the conductor 240 may be exposed. The conductor used for the conductive material (hereinafter also referred to as the first conductor of the conductive material 240) is a metal film. It is preferable to use a nitride film containing a metal element or an oxide film containing a metal element. The oxide 230 that is not made resistive contacts the first conductor of the conductor 240, forming a metallization. Oxygen vacancies are formed in the compound or oxide 230, and regions 231 of the oxide 230 become low resistance. Therefore, the resistance of the oxide 230 in contact with the first conductor of the conductor 240 is reduced. Therefore, the contact resistance between the oxide 230 and the conductor 240 can be reduced. The first conductor of the conductor 240 is, for example, aluminum, ruthenium, titanium, or tantalum. It is preferable that the conductor 540 contains a metal element such as tungsten. That's fine.

[0354] In addition, when the conductor 240 and the conductor 540 are formed in a laminated structure, the insulator 280 and the insulator 2 74 and the conductor in contact with the insulator 273, similar to the first conductor of the conductor 205, In addition, a conductive material having a function of suppressing the permeation of impurities such as water or hydrogen can be used. For example, tantalum, tantalum nitride, titanium, titanium nitride, ruthenium or oxide It is preferable to use ruthenium chloride or the like. In addition, it is preferable to use ruthenium chloride or the like to suppress the permeation of impurities such as water or hydrogen. The conductive material having the function of controlling the temperature may be used in a single layer or a multilayer structure. By this, impurities such as hydrogen and water from the upper layer of the insulator 280 are absorbed into the conductor 240 and the conductor The inclusion of the oxide 230 and the oxide 530 can be suppressed through the dielectric 540. do.

[0355] Although not shown, the conductive material 240 and the conductive material 540 are in contact with each other on their upper surfaces and function as wiring. The conductor that functions as the wiring may be made of tungsten, copper, or aluminum. It is preferable to use a conductive material containing aluminum as the main component. It may have a layer structure, for example, a laminate of titanium, titanium nitride and the above conductive material. The conductor is embedded in an opening provided in an insulator, similar to the conductor 203. It may be formed so as to include

[0356] <Materials for semiconductor devices> The following describes constituent materials that can be used in semiconductor devices. Unless otherwise specified, the materials that can be used for the transistor 200 are It shall be possible to use it for the transistor 500.

[0357] The following materials are deposited by sputtering, chemical vapor deposition (CVD), Vapor Deposition (Vapor Deposition), Molecular Beam Epitaxy (MBE) cular beam epitaxy (PLD), pulsed laser deposition (PLD) Laser Deposition (ALD) or Atomic Layer Deposition (ALD) This can be done using a method such as Layer Deposition.

[0358] The CVD method is a plasma CVD (PECVD) method that uses plasma. enhanced CVD method, thermal CVD (TCVD) D) method, and photo-CVD (Photo CVD) method, which uses light. Depending on the source gas, metal CVD (MCVD) and metal organic CVD ( MOCVD (Metal Organic CVD) method.

[0359] The plasma CVD method can produce high-quality films at relatively low temperatures. This is a film formation method that can suppress plasma damage to the workpiece because it does not use a plasma. For example, wiring, electrodes, elements (transistors, capacitors, etc.) included in a semiconductor device When a charge is received from the plasma, it may be charged up. The accumulated charge may destroy the wiring, electrodes, elements, etc. contained in the semiconductor device. On the other hand, in the case of thermal CVD, which does not use plasma, such plasma damage does not occur. In addition, in the thermal CVD method, Since no plasma damage occurs, a film with few defects can be obtained.

[0360] The ALD method is also a film formation method that can suppress plasma damage to the workpiece. Therefore, a film with few defects can be obtained. For this reason, films formed by ALD are not suitable for other film formation methods. In some cases, the impurity content of the film may be higher than that of the film formed by the conventional method. Quantitative analysis was performed using X-ray photoelectron spectroscopy (XPS). This can be done using a microscope.

[0361] The CVD and ALD methods are film formation methods in which particles emitted from a target are deposited. Unlike the conventional method, this is a film formation method in which a film is formed by a reaction on the surface of the object to be treated. This is a film forming method that is less affected by the shape of the workpiece and has good step coverage. The ALD method has excellent step coverage and thickness uniformity, making it suitable for the production of thin films with high aspect ratios. It is suitable for coating the surface of high openings. However, the ALD method has a relatively low film formation rate. Because the deposition rate is slow, it cannot be used in combination with other deposition methods such as CVD, which has a high deposition rate. In some cases this may be preferable.

[0362] In the CVD and ALD methods, the composition of the resulting film can be controlled by the flow rate ratio of the source gases. For example, in the CVD and ALD methods, the flow rate ratio of the source gases can be adjusted to any desired value. In addition, for example, in the CVD method and the ALD method, it is possible to form a film having a composition. By changing the flow rate ratio of the source gases while When forming a film while changing the flow rate ratio of the source gases, multiple film forming chambers can be used. Compared to forming a film by using a vacuum pump, the time required for film formation is shorter because there is no time required for transportation or pressure adjustment. Therefore, the productivity of the semiconductor device can be improved. be.

[0363] The constituent materials may be processed using a lithography method. Dry etching and wet etching can be used. This method is suitable for microfabrication.

[0364] In the lithography method, first, the resist is exposed to light through a mask. The resist mask is formed by removing or leaving the resist pattern using a developer. By etching through a mask, a conductor, a semiconductor, an insulator, or the like can be formed as desired. It can be processed into any shape. For example, KrF excimer laser light, ArF excimer laser The resist is exposed using light, EUV (Extreme Ultraviolet) light, etc. A resist mask can be formed by irradiating the substrate with light. For example, a liquid immersion technique may be used, in which the substrate is exposed to light by filling the substrate with water. An electron beam or an ion beam may be used. In this case, the pattern is drawn directly on the resist, so the above-mentioned resist exposure mask is not required. The resist mask is used for dry etching such as ashing, and for wet etching. dry etching followed by wet etching; or It can be removed by wet etching followed by dry etching, etc. .

[0365] Moreover, instead of the resist mask, a hard mask made of an insulator or a conductor may be used. When a hard mask is used, an insulating film or a conductive film that will be the hard mask material is formed on the constituent material. A resist mask is formed thereon, and the hard mask material is etched to form a desired pattern. The etching of the component material can form a hard mask of the desired shape. This may be done after removing the resist mask, or may be done while the resist mask is left in place. In some cases, the resist mask may disappear during etching. After etching, the hard mask may be removed by etching. If there is no effect on the subsequent process or if it can be used in the subsequent process, it is not necessary to remove the hard mask. There is no need to.

[0366] The dry etching equipment is a capacitively coupled plasma (CCP) with parallel plate electrodes. Capacitively Coupled Plasma etching equipment is used. The capacitively coupled plasma etching apparatus having parallel plate electrodes can Alternatively, a high frequency power supply may be applied to one of the electrodes. A configuration in which a plurality of different high frequency power supplies are applied to the electrodes may also be used. Alternatively, a high frequency power supply of the same frequency may be applied to each of the parallel plate electrodes. Alternatively, a high-frequency power supply having a high-density plasma source may be used. Dry etching equipment with a high density plasma source can be used. The device may be, for example, an inductively coupled plasma (ICP) d Plasma etching equipment or the like can be used.

[0367] <<Substrate>> The substrate on which the transistor 200 and the transistor 500 are formed may be, for example, an insulator. A substrate, a semiconductor substrate, or a conductive substrate may be used. An insulating substrate may be, for example, a glass substrate. substrate, quartz substrate, sapphire substrate, stabilized zirconia substrate (yttria stabilized zirconia Examples of semiconductor substrates include silicon and silicon dioxide. Semiconductor substrates such as ruthenium, or silicon carbide, silicon germanium, or gallium arsenide Examples include compound semiconductor substrates made of silicon, indium phosphide, zinc oxide, and gallium oxide. Furthermore, the semiconductor substrate having an insulating region inside the semiconductor substrate, for example, SOI (Si As for conductive substrates, graphite-based Plates, metal substrates, alloy substrates, conductive resin substrates, etc. Or, substrates with metal nitrides There are also substrates with conductive or semiconductive materials on insulating substrates. a substrate on which a conductor or an insulator is provided; a substrate on which a conductor or an insulator is provided; a substrate on which a semiconductor is provided; There are substrates on which conductors or insulators are provided, or elements are provided on these substrates. The elements provided on the substrate may include a capacitance element, a resistance element, a switch, and the like. There are elements, light-emitting elements, memory elements, etc.

[0368] A flexible substrate may be used as the substrate. As a method for this, a transistor is fabricated on a non-flexible substrate and then peeled off. Alternatively, there is a method of transferring the substrate to a flexible substrate. It is preferable to provide a release layer between the substrate and the substrate. The substrate may also be stretchable. The material may have the property of returning to its original shape when the bending or pulling is stopped. The substrate may have a thickness of, for example, 5 μm or more and 700 μm or less, preferably Preferably, it is 10 μm or more and 500 μm or less, and more preferably, it is 15 μm or more and 300 μm or less. The thickness of the substrate is reduced, and the weight of the semiconductor device having the transistor is reduced. Furthermore, by making the substrate thin, it is possible to achieve stretchability even when glass or other materials are used. Some have the property of returning to their original shape when bending or pulling is stopped. Therefore, it is possible to reduce the impact that is applied to the semiconductor device on the board when it is dropped, etc. That is, a robust semiconductor device can be provided.

[0369] The flexible substrate may be, for example, a metal, an alloy, a resin, or a glass, or any of these. The substrate may be a sheet or film made of woven fibers. For flexible substrates, the lower the linear expansion coefficient, the more environmentally friendly they are. The substrate that is flexible is preferably a substrate having a linear expansion coefficient of 1. x10 -3 / K or less, 5×10 -5 / K or less, or 1×10 -5 / K or less Examples of resins that can be used include polyester, polyolefin, polyamide (nano), and Iron, aramid, etc.), polyimide, polycarbonate, acrylic, etc. In particular, Aramid has a low coefficient of linear expansion and is therefore suitable for use as a flexible substrate.

[0370] <<Insulators>> The insulators include oxides, nitrides, oxynitrides, nitride oxides, and metal oxides that have insulating properties. , metal oxide nitrides, metal nitride oxides, etc.

[0371] For example, as transistors become smaller and more highly integrated, the gate insulator becomes thinner. , leakage current and other problems may occur. By using igh-k materials, the voltage required for transistor operation can be reduced while maintaining the physical film thickness. On the other hand, the insulator that functions as the interlayer film should be made of a material with a low dielectric constant. Therefore, depending on the function of the insulator, the parasitic capacitance between the wiring can be reduced. It is advisable to select materials accordingly.

[0372] Insulators with high dielectric constants include gallium oxide, hafnium oxide, and zirconium oxide. oxides containing aluminum, aluminum and hafnium, oxides containing aluminum and hafnium oxides with silicon and hafnium, oxides with silicon and hafnium or nitrides with silicon and hafnium.

[0373] Insulators with low dielectric constants include silicon oxide, silicon oxynitride, and silicon nitride oxide. silicon nitride, silicon oxide with fluorine, silicon oxide with carbon, silicon oxide with added hydrogen and nitrogen, silicon oxide with pores, or resin. .

[0374] In particular, silicon oxide and silicon oxynitride are thermally stable. For example, by combining it with resin, it is possible to create a thermally stable laminated structure with a low dielectric constant. Examples of resins include polyester, polyolefin, polyamide (nylon), , aramid, etc.), polyimide, polycarbonate, or acrylic. For example, silicon oxide and silicon oxynitride can be combined with insulators with high dielectric constants. This makes it possible to obtain a thermally stable laminated structure with a high relative dielectric constant.

[0375] In addition, a transistor using an oxide semiconductor suppresses the permeation of impurities such as hydrogen and oxygen. By surrounding the transistor with an insulator that has the function of stabilizing the electrical characteristics of the transistor, can be done.

[0376] Examples of insulators that have the function of suppressing the permeation of impurities such as hydrogen and oxygen include porosity. Uron, carbon, nitrogen, oxygen, fluorine, magnesium, aluminum, silicon, phosphorus, chlorine , argon, gallium, germanium, yttrium, zirconium, lanthanum, neodymium Insulators containing titanium, hafnium or tantalum may be used in a single layer or in a multilayer configuration. Specifically, it is an insulator that has the function of suppressing the permeation of impurities such as hydrogen and oxygen. Aluminum oxide, magnesium oxide, gallium oxide, germanium oxide, yttrium oxide aluminum, zirconium oxide, lanthanum oxide, neodymium oxide, hafnium oxide or tantalum oxide Metal oxides such as silicon dioxide, silicon nitride oxide, silicon nitride, etc. can be used.

[0377] For example, the insulator 273 may be hafnium, aluminum, gallium, yttrium, or di Zr, tungsten, titanium, tantalum, nickel, germanium, or magnesium It is possible to use a metal oxide containing one or more metals selected from the group consisting of cadmium, cadmium, and sulphur. Cut.

[0378] In particular, aluminum oxide has a high barrier property and is a thin film of 0.5 nm to 3.0 nm. Even if the hafnium oxide is used, it is possible to suppress the diffusion of hydrogen and nitrogen. Although its barrier properties are lower than those of aluminum, its barrier properties can be improved by increasing the film thickness. Therefore, by adjusting the thickness of the hafnium oxide film, it is possible to control the amount of hydrogen and nitrogen. The amount of addition can be adjusted appropriately.

[0379] For example, the insulator 224 and the insulator 250, which function as part of the gate insulator, are It is preferable that the insulator has an oxygen-rich region. For example, a silicon oxide having an oxygen-rich region is preferable. By forming a structure in which silicon or silicon oxynitride is in contact with the oxide 230, the oxide 230 becomes effective. This can compensate for the oxygen deficiency that occurs.

[0380] Also, for example, aluminum is used in the insulator 222, which functions as part of the gate insulator. Insulators containing oxides of one or more of hafnium and gallium may be used. In particular, the insulators containing oxides of either or both aluminum and hafnium are Examples include aluminum oxide, hafnium oxide, and oxides containing aluminum and hafnium. It is preferable to use hafnium aluminate.

[0381] For example, the insulator 220 may be silicon oxide or silicon oxynitride, which are thermally stable. It is preferable to use a film that is stable to heat and has a high relative dielectric constant as the gate insulator. By using a laminated structure with the film, the equivalent oxide film thickness of the gate insulator ( It is possible to reduce the thickness of the EOT.

[0382] By using the above stacked structure, the influence of the electric field from the gate electrode is not weakened, and the on-current In addition, the physical thickness of the gate insulator allows the gate electrode and the By keeping the distance between the gate electrode and the region where the channel is formed, This can suppress the leakage current between the two.

[0383] The insulators 212, 216, 271, 275, and 280 are relatively It is preferable to have an insulator with a low dielectric constant. For example, the insulator may be silicon oxide, oxide, or the like. Silicon nitride, silicon oxynitride, silicon nitride, silicon oxide doped with fluorine, carbon silicon oxide doped with oxygen, silicon oxide doped with carbon and nitrogen, silicon oxide with vacancies Preferably, the insulator comprises silicon or resin, or silicon oxide. , silicon oxynitride, silicon nitride oxide, silicon nitride, fluorine-doped silicon oxide , carbon-doped silicon oxide, carbon- and nitrogen-doped silicon oxide, or vacancy-containing silicon oxide. It is preferable that the insulating film has a laminated structure of silicon oxide and resin. Silicon nitride is thermally stable, so by combining it with resin, it becomes thermally stable and A laminated structure with a low dielectric constant can be obtained. Examples of resins include polyester, Polyolefin, polyamide (nylon, aramid, etc.), polyimide, polycarbonate Or acrylic.

[0384] The insulators 210, 214, 270, and 273 may be hydrogen or the like. An insulator having a function of suppressing the permeation of impurities and oxygen may be used. The insulator 273 may be, for example, aluminum oxide, hafnium oxide, or magnesium oxide. um, gallium oxide, germanium oxide, yttrium oxide, zirconium oxide, laminar oxide metal oxides such as tantalum, neodymium oxide or tantalum oxide, silicon oxide nitride or Silicon dioxide or the like may be used.

[0385] <<Conductors>> Conductors include aluminum, chromium, copper, silver, gold, platinum, tantalum, nickel, and titanium. Niobium, molybdenum, tungsten, hafnium, vanadium, niobium, manganese, magnesium Metal elements selected from sulphur, zirconium, beryllium, indium, ruthenium, etc. It is possible to use a material containing one or more of these elements. Highly conductive semiconductors such as silicon, and silicides such as nickel silicide may also be used.

[0386] Alternatively, a plurality of conductive layers made of the above materials may be stacked. Alternatively, a laminated structure may be used in which a material containing a metal element and a conductive material containing oxygen are combined. In addition, a laminated structure in which a material containing the above-mentioned metal element and a conductive material containing nitrogen are combined is also provided. In addition, the material containing the metal element, the conductive material containing oxygen, and the conductive material containing nitrogen may be used. It may also have a laminated structure in which a conductive material containing the metal oxide is combined.

[0387] When an oxide is used for the channel formation region of a transistor, Conductors that function as such are made by combining materials containing the aforementioned metal elements with conductive materials containing oxygen. In this case, it is preferable to use a laminated structure in which an oxygen-containing conductive material is used as a channel. It is preferable to provide the conductive material containing oxygen on the side of the channel formation region. Therefore, oxygen released from the conductive material is easily supplied to the channel formation region.

[0388] In particular, the metal oxide in which the channel is formed is used as a conductor that functions as a gate electrode. It is preferable to use a conductive material containing the metal element and oxygen. Conductive materials containing elements such as titanium nitride and tantalum nitride may also be used. Any conductive material containing nitrogen may be used. Indium tin oxide, tungsten oxide, etc. Indium oxide containing tungsten oxide, indium zinc oxide containing tungsten oxide, titanium oxide Indium oxide containing titanium oxide, indium tin oxide containing titanium oxide, indium zinc oxide Alternatively, silicon-doped indium tin oxide may be used. Gallium zinc oxide may also be used. By using such a material, a channel is formed. In some cases, the metal oxides surrounding the outer insulating layer can trap hydrogen. It may be possible to capture hydrogen that enters the body, etc.

[0389] The conductor 260, the conductor 203, the conductor 205, and the conductor 240 are made of aluminum. Aluminum, chromium, copper, silver, gold, platinum, tantalum, nickel, titanium, molybdenum, tungsten Niobium, hafnium, vanadium, niobium, manganese, magnesium, zirconium, beryllium A material containing one or more metal elements selected from the group consisting of sulphur, indium, ruthenium, etc. is used. In addition, it is possible to use polycrystalline silicon containing impurity elements such as phosphorus. Highly conductive semiconductors and silicides such as nickel silicide may also be used.

[0390] <<Metal oxides>> The oxide 230 is preferably a metal oxide that functions as an oxide semiconductor. Metal oxides applicable to the oxide 230 according to the present invention will be described below.

[0391] The metal oxide preferably contains at least indium or zinc, particularly indium. and zinc. In addition to these, aluminum, gallium, iridium, It is preferable that the alloy contains tritium or tin. Also, boron, titanium, iron, Nickel, germanium, zirconium, molybdenum, lanthanum, cerium, neodymium, One selected from hafnium, tantalum, tungsten, magnesium, etc., may contain multiple types.

[0392] Here, the metal oxide is an In-M-Zn oxide having indium, element M, and zinc. The element M is aluminum, gallium, yttrium, or sulfur. Other elements that can be used for element M include boron, titanium, iron, and nickel. Kel, germanium, zirconium, molybdenum, lanthanum, cerium, neodymium, hafnium However, the element M is In some cases, a combination of the above elements may be used.

[0393] In this specification and the like, metal oxides containing nitrogen are also referred to as metal oxides. Nitrogen-containing metal oxides are also called metal oxynitrides (met). It may also be called hydroxybenzoxanthate (hydroxybenzoxanthate).

[0394] [Metal oxide composition] Hereinafter, a CAC (Cl) that can be used in a transistor disclosed in one embodiment of the present invention will be described. This paper explains the structure of the oud-Aligned Composite OS.

[0395] In this specification and the like, CAAC (c-axis aligned crystal ), and when written as CAC (Cloud-Aligned Composite) CAAC represents an example of a crystal structure, and CAC represents a function or a material configuration. Represents an example.

[0396] CAC-OS or CAC-metal oxide is a material that has the function of conductivity in some parts. The material has an insulating function in part and a semiconductor function in the whole. In addition, CAC-OS or CAC-metal oxide is used as the active layer of a transistor. When used in the above, the conductive function is the function of allowing electrons (or holes) to flow as carriers, The insulating function is the function of preventing the flow of electrons, which act as carriers. By making these functions work in a complementary manner, the switching function (On / Off This function (which allows the CAC-OS or CAC-metal oxide to In CAC-OS or CAC-metal oxide, each function can be By separating them, the functions of both can be maximized.

[0397] Also, CAC-OS or CAC-metal oxide is used in conductive and insulating areas. The conductive region has the above-mentioned conductive function, and the insulating region has the above-mentioned insulating function. In addition, the conductive region and the insulating region in the material are formed by nanoparticle layers. The conductive and insulating regions may be separated by a bell. In addition, the conductive area may be observed as a cloud-like connected area with a blurred periphery. This may be the case.

[0398] In addition, in CAC-OS or CAC-metal oxide, the conductive region and the insulating region are The peripheral region is 0.5 nm to 10 nm, preferably 0.5 nm to 3 nm. The following sizes may be dispersed in the material:

[0399] In addition, CAC-OS or CAC-metal oxide has different band gaps. For example, CAC-OS or CAC-metal oxi de is a component with a wide gap due to the insulating region and a component with a narrow gap due to the conductive region. In this configuration, when carriers flow, In the narrow gap component, carriers mainly flow. The component having a wide gap acts complementary to the component having a narrow gap. Carriers also flow into the wide-gap component in conjunction with the component with a wide gap. AC-OS or CAC-metal oxide is placed in the channel formation region of the transistor. When used, the transistor has a high current driving force in the on state, i.e., a large on-current. Furthermore, high field-effect mobility can be obtained.

[0400] That is, CAC-OS or CAC-metal oxide is a matrix composite material. (matrix composite), or metal matrix composite It can also be called a matrix composite.

[0401] [Metal oxide structures] Oxide semiconductors (metal oxides) are divided into single-crystal oxide semiconductors and other non-single-crystal oxide semiconductors. As a non-single-crystal oxide semiconductor, for example, CAAC-OS (ca xis aligned crystalline oxide semiconductor tor), polycrystalline oxide semiconductor, nc-OS (nanocrystalline oxide de semiconductor), pseudo-amorphous oxide semiconductor (a-like OS: amorphous-like oxide semiconductor) and amorphous and oxide semiconductors.

[0402] CAAC-OS has a c-axis orientation and multiple nanocrystals are connected in the ab-plane direction. The crystal structure has distortion. The distortion is the area where multiple nanocrystals are connected. In the region, the direction of the lattice arrangement is changed between a region with a uniform lattice arrangement and another region with a uniform lattice arrangement. This refers to the part where the sound changes.

[0403] Nanocrystals are basically hexagonal, but they are not limited to regular hexagonal shapes and may be non-regular hexagonal. The distortion may also have lattice arrangements such as pentagons and heptagons. In CAAC-OS, clear grain boundaries (grain boundaries) are observed even near the strain. It is difficult to confirm the presence of grains due to distortion of the lattice arrangement. This is because the CAAC-OS has a crystalline structure in the ab-plane direction. The oxygen atoms are not densely packed, and the bond distance between atoms is shortened by the substitution of metal elements. This is because distortion can be tolerated by changing the frequency.

[0404] In addition, the CAAC-OS has a layer containing indium and oxygen (hereinafter referred to as an In layer) and an element A layered crystal structure in which layers containing M, zinc, and oxygen (hereinafter referred to as (M, Zn) layers) are stacked. It is noted that indium and element M tend to have a layered structure. It is possible, and when the element M in the (M,Zn) layer is replaced with indium, (In,M,Zn) Also, when indium in the In layer is replaced with element M, (In,M ) layer.

[0405] CAAC-OS is a metal oxide with high crystallinity. Since it is difficult to identify grain boundaries, the decrease in electron mobility caused by grain boundaries is unlikely to occur. In addition, the crystallinity of metal oxides can be reduced by the incorporation of impurities or the generation of defects. Therefore, CAAC-OS is a metal oxide with few impurities and defects (such as oxygen vacancies). Therefore, the physical properties of the metal oxide having the CAAC-OS are stable. Therefore, metal oxides having CAAC-OS are heat-resistant and highly reliable.

[0406] nc-OS is a material that can be used in microscopic areas (e.g., areas between 1 nm and 10 nm, especially areas between 1 nm and 3 nm). The nc-OS has periodic atomic arrangement in the nanometer range (nm or less). There is no regularity in the crystal orientation between the crystals. Therefore, no orientation is observed throughout the film. Therefore, depending on the analysis method, nc-OS may be distinguished from a-like OS or amorphous oxide semiconductor. It may be difficult to distinguish between the two.

[0407] The a-like OS is a metal oxide semiconductor with a structure between the nc-OS and amorphous oxide semiconductor. A-like OS has voids or low density areas. e-OS has lower crystallinity than nc-OS and CAAC-OS.

[0408] Oxide semiconductors (metal oxides) have a variety of structures, each with different properties. The oxide semiconductor of one embodiment of the present invention is an amorphous oxide semiconductor, a polycrystalline oxide semiconductor, an a-lik The crystalline structure may have two or more of e-OS, nc-OS, and CAAC-OS.

[0409] [Transistors with metal oxides] Next, the case where the above metal oxide is used for a channel formation region of a transistor will be described. do.

[0410] By using the above metal oxide in the channel formation region of a transistor, a high field effect It is possible to realize a highly reliable transistor. It is possible.

[0411] It is also preferable to use a metal oxide with a low carrier density for the transistor. When the carrier density of the oxide film is reduced, the impurity concentration in the metal oxide film is reduced. In this specification and the like, the impurity concentration is low and the defect level density is low. Low density is called high purity intrinsic or substantially high purity intrinsic. For example, metal oxides are Carrier density is 8×10 11 / cm 3 Less than 1 x 10 11 / cm 3 Less than, more Preferably 1 x 10 10 / cm 3 Less than 1 x 10 -9 / cm 3 That's all you need to do. .

[0412] Furthermore, a highly pure intrinsic or substantially highly pure intrinsic metal oxide film has a low density of defect states. Therefore, the trap level density may also be low.

[0413] In addition, the charges trapped in the trap levels of metal oxides take a long time to disappear. Therefore, gold, which has a high density of trap states, A transistor having a metal oxide in a channel formation region may have unstable electrical characteristics. do.

[0414] Therefore, in order to stabilize the electrical characteristics of the transistor, the impurity concentration in the metal oxide In order to reduce the impurity concentration in the metal oxide, it is effective to reduce the It is also preferable to reduce the impurity concentration in the film in contact with the film. Potassium metal, alkaline earth metal, iron, nickel, silicon, etc.

[0415] [impurities] Here, the influence of each impurity in the metal oxide will be described.

[0416] When metal oxides contain silicon or carbon, which are elements of Group 14, they can be easily converted into metal oxides. Defect levels are formed in the material. Therefore, the concentration of silicon and carbon in the metal oxide The concentration of silicon and carbon near the interface with the metal oxide was measured by secondary ion mass spectrometry (SIMS). : Secondary Ion Mass Spectrometry) concentration) to 2 x 10 18 atoms / cm 3 Less than or equal to 2 x 10 17 atoms / cm 3 The following applies.

[0417] In addition, when alkali metals or alkaline earth metals are contained in metal oxides, defect levels are formed. Therefore, alkali metals or alkaline earth metals A transistor using a metal oxide containing fluorine in the channel formation region is a normally-on transistor. Therefore, the concentration of alkali metals or alkaline earth metals in the metal oxides It is preferable to reduce the alkalinity in the metal oxide obtained by SIMS. The concentration of alkaline earth metals or alkaline earth metals is 1×10 18 atoms / cm 3 The following is preferred: Kuha 2 x 10 16 atoms / cm 3 Do the following:

[0418] In addition, when nitrogen is contained in a metal oxide, electrons that act as carriers are generated, and the carrier density increases. As a result, the concentration of nitrogen-containing metal oxides is increased, making it easier to form n-type channels. The transistor used in the region tends to be normally on. In the nitride, it is preferable that the nitrogen content in the channel forming region is reduced as much as possible. For example, the nitrogen concentration in metal oxide is 5×10 19 atoms / cm 3 Less than 5 x 10 18 atoms / cm 3 Less than or equal to 1×10 18 a toms / cm 3 Less than 5 × 10, more preferably 17 atoms / cm 3 The following applies.

[0419] In addition, the hydrogen contained in the metal oxide reacts with the oxygen that bonds with the metal atom to form water, When hydrogen enters the oxygen vacancy, the electron carrier In addition, some of the hydrogen may combine with the oxygen that is bonded to the metal atom, forming a carrier. Therefore, metal oxides containing hydrogen can produce electrons. The transistor used in the channel forming region tends to have normally-on characteristics. It is preferable that the hydrogen content in the metal oxide is reduced as much as possible. The hydrogen concentration obtained by SIMS is 1×10 20 atoms / cm 3 less than, Preferably 1 x 10 19 atoms / cm 3 less than 5 × 10 18 atom s / cm 3 less than 1×10 18 atoms / cm 3 Less than.

[0420] By using metal oxide with sufficiently reduced impurities in the channel formation region of a transistor, , and stable electrical properties can be imparted.

[0421] According to one embodiment of the present invention, a semiconductor device having favorable electrical characteristics can be provided. According to one embodiment of the present invention, a semiconductor device with low off-state current can be provided. According to one embodiment of the present invention, a semiconductor device with large on-state current can be provided. According to one embodiment of the present invention, a highly reliable semiconductor device can be provided. According to one embodiment of the present invention, a semiconductor device that can be miniaturized or highly integrated can be provided. According to one embodiment of the present invention, a semiconductor device with reduced power consumption can be provided. According to one embodiment of the present invention, a semiconductor device with high productivity can be provided. Cut.

[0422] Note that at least a part of the configurations, structures, methods, and the like shown in this embodiment are described in this specification. The present invention can be implemented by appropriately combining it with the configurations, structures, methods, etc. shown in the other embodiments described above. Cut.

[0423] (Embodiment 3) In this embodiment, an electronic component and a semiconductor device 10 according to an embodiment of the present invention are incorporated. Examples of electronic devices are shown below.

[0424] <Electronic components> An example of an electronic component incorporating the semiconductor device 10 will be described with reference to FIGS. 25(A) and 25(B). .

[0425] The electronic component 7000 shown in FIG. 25(A) is an IC chip, and has leads and a circuit portion. The electronic component 7000 is mounted on, for example, a printed circuit board 7002. A plurality of chips are combined and electrically connected on the printed circuit board 7002. This completes the production of a substrate (mounted substrate 7004) on which electronic components are mounted.

[0426] The circuit section of the electronic component 7000 is formed by stacking, for example, a substrate 7031, a layer 7032, and a layer 7033. It is a structure that

[0427] When a semiconductor substrate such as silicon is used as the substrate 7031, the substrate 7031 is provided with a CPU (C and an integrated circuit such as a central processing unit (Central Processing Unit) is formed on it. A layer 7032 having an S transistor may be formed.

[0428] The layer 7032 includes the OS transistor described in the above embodiment. The circuit 60, the drive circuit 80, the main amplifier 81, the input / output circuit 82, etc. are provided on the layer 7032. It is possible.

[0429] The layer 7033 has a plurality of memory cells MC. A memory cell using an OS transistor such as OSRAM (registered trademark) (hereinafter referred to as OS memory) ) can be used.

[0430] The OS memory can be stacked on other semiconductor elements, so the electronic component 7000 In addition, the OS transistor has low leakage current in the off state (off The current is very small, allowing for long refresh periods and low power consumption. That is, the power consumption of the electronic component 7000 can be reduced.

[0431] The OS memory may be provided in layer 7032 instead of layer 7033. The manufacturing process for IC chips can be shortened.

[0432] Layer 7033 contains not only OS memory but also ReRAM (Resistive Random Access Memory). cess Memory), MRAM (Magnetoresistive Rando m Access Memory), PRAM (Phase change RAM), A memory such as FeRAM (Ferroelectric RAM) may be provided.

[0433] In FIG. 25(A), the package of the electronic component 7000 is QFP (Quad Flat Pack). However, the packaging format is not limited to this.

[0434] The electronic component 7400 shown in FIG. 25(B) is a camera module, and an image sensor chip It has a built-in 7451.

[0435] The electronic component 7400 includes a package substrate 7411 on which an image sensor chip 7451 is fixed. , a lens cover 7421, and a lens 7435. Between the image sensor chip 7451 and the image sensor chip 7451, a driving circuit for the image sensor and a signal conversion circuit are provided. The IC chip 7490, which has circuit functions, is also installed, and is a SiP (System in Package). It is configured as a single unit (in a package).

[0436] The land 7441 is electrically connected to the electrode pad 7461, and the electrode pad 7461 is The sensor chip 7451 or IC chip 7490 is electrically connected to the wire 7471. 25(B) shows the inside of the electronic component 7400. The cover 7421 and the lens 7435 are partially omitted in the illustration.

[0437] The circuit part of the image sensor chip 7451 is formed by, for example, a substrate 7031, a layer 7032, a layer 70 33, and layer 7034 are stacked.

[0438] For details of substrate 7031, layer 7032, and layer 7033, see the description of electronic component 7000 above. To quote.

[0439] The layer 7034 has a light receiving element. The light receiving element is made of, for example, a selenium-based material for photoelectric conversion. A pn junction photodiode with a layer of selenium-based material can be used. The photoelectric conversion element has a high external quantum efficiency for visible light, making it possible to realize a highly sensitive photosensor. can be done.

[0440] Selenium-based materials can be used as p-type semiconductors. Selenium, crystalline selenium such as polycrystalline selenium, amorphous selenium, copper, indium, selenium oxide Compounds of copper, indium, gallium, and selenium (CIS) or compounds of copper, indium, gallium, and selenium (CIGS) can be used.

[0441] The n-type semiconductor in the pn junction photodiode has a wide band gap and is sensitive to visible light. It is preferable to form the insulating film from a material having light-transmitting properties. For example, zinc oxide, gallium oxide, etc. Indium oxide, tin oxide, or a mixture thereof can be used. do.

[0442] The layer 7034 has a light receiving element made of a p-type silicon semiconductor and an n-type silicon semiconductor. A pn junction photodiode using a p-type silicon semiconductor and an n-type silicon semiconductor may also be used. It is a pin junction photodiode with an i-type silicon semiconductor layer between silicon semiconductors. It is also possible.

[0443] The photodiode using silicon can be formed using single crystal silicon. At this time, the layer 7033 and the layer 7034 are electrically connected by a bonding process. The photodiode using silicon is preferably made of amorphous silicon, It can also be formed using a thin film of microcrystalline silicon, polycrystalline silicon, or the like.

[0444] <Electronic equipment> Next, examples of electronic devices equipped with the above electronic components will be described with reference to FIGS. 26 and 27. FIG.

[0445] The robot 2100 shown in FIG. 26(A) includes a computing device 2110, an illuminance sensor 2101, a microphone, and a microphone array. A microphone 2102, an upper camera 2103, a speaker 2104, a display 2105, It is equipped with a lower camera 2106, an obstacle sensor 2107, and a movement mechanism 2108.

[0446] In the robot 2100, a computing device 2110, an illuminance sensor 2101, an upper camera 210 3, the display 2105, the lower camera 2106, the obstacle sensor 2107, etc. Electronic components can be used.

[0447] The microphone 2102 has a function of detecting the user's voice and environmental sounds. The speaker 2104 has a function of emitting sound. The phone 2102 and the speaker 2104 are used to communicate with the user. is possible.

[0448] The display 2105 has the function of displaying various information. Any information desired by the user can be displayed on the display 2105. The 2105 may be equipped with a touch panel.

[0449] The upper camera 2103 and the lower camera 2106 are devices for capturing images of the surroundings of the robot 2100. The obstacle sensor 2107 detects the obstacles in the robot 210 by using the moving mechanism 2108. When moving forward, the robot can sense whether there are any obstacles in its path. 00 uses an upper camera 2103, a lower camera 2106, and an obstacle sensor 2107. It is possible to recognize the surrounding environment and move safely.

[0450] Figure 26(B) shows the mobile communication between people who speak different languages. 2 shows a situation in which simultaneous interpretation is performed by a wristwatch type information terminal 2130.

[0451] The portable information terminal 2130 has a microphone and a speaker, etc., and can pick up the user's voice. The portable information terminal 2130 has the function of recognizing the speech and translating it into the language of the person speaking. The electronic components described above can be used in a computing device.

[0452] In addition, in FIG. 26(B), the user has a portable microphone 2131. The microphone 2131 has a wireless communication function and transmits the detected sound to the portable information terminal 213. It has the ability to send to 0.

[0453] FIG. 27 is a schematic diagram showing an example of a cleaning robot.

[0454] The cleaning robot 5100 has a display 5101 on the top surface and multiple The camera 5102, the brush 5103, the operation button 5104, etc. Although not shown, the cleaning robot 5100 is equipped with tires, a suction port, etc. on its underside. The cleaning robot 5100 also has infrared sensors, ultrasonic sensors, acceleration sensors, and It is equipped with various sensors such as a water sensor, a light sensor, and a gyro sensor. The terminal 5100 is equipped with a wireless communication means.

[0455] The above electronic components can be used in the camera 5102.

[0456] The cleaning robot 5100 moves by itself, detects the dust 5120, and sucks it out from the suction port on the bottom. It can suck up dirt.

[0457] In addition, the cleaning robot 5100 analyzes the image captured by the camera 5102 and detects the wall, furniture, or It can detect obstacles such as steps. Image analysis can also detect obstacles such as wiring. If an object that may get tangled in the brush 5103 is detected, the rotation of the brush 5103 can be stopped. can.

[0458] The display 5101 can display the remaining battery level and the amount of dust sucked. In addition, the route traveled by the cleaning robot 5100 can be displayed on the display 5101. Alternatively, a touch panel may be provided on the display 5101, and an operation button 5104 may be operated. It may be displayed on the display 5101.

[0459] The cleaning robot 5100 communicates with a portable information terminal 5140 such as a smartphone. The image captured by the camera 5102 can be displayed on the portable information terminal 5140. Therefore, the owner of the Cleaning Robot 5100 can check the state of the room even when they are away from home. You can find out.

[0460] This embodiment may be implemented in appropriate combination with other embodiments described in this specification. It is possible. [Explanation of symbols]

[0461] ASW1 Analog Switch ASW4 Analog Switch BL_1 wiring BL_2 wiring C0 Capacitor element C11 Capacitor element C12 Capacitor element E0 potential E1 potential E2 potential E2-E0 potential difference E2-E1 potential difference GBL_1 wiring GBL_2 wiring IN1 input terminal IN2 input terminal OUT1 output terminal OUT2 output terminal MC_1 memory cell MC_2 memory cell N11 node N12 node OS1 transistor OS2 transistor PL1 wiring PL2 wiring PL3 wiring R11 resistor element R12 resistor element SA1 Sense Amplifier SA2 Sense Amplifier SW1 switch SW4 switch T1 period T2 period T3 period T4 period Vbl1 potential Vbl2 potential Vn11 potential Vn12 potential WL_1 wiring WL_2 wiring 10 Semiconductor devices 21 Transistor 22 transistor 23 Transistor 24 transistors 25 transistors 26 transistors 27 Transistor 28 transistors 29 Transistor 31 Transistor 32 transistors 33 Transistor 34 transistors 35 transistors 38 transistors 41 Transistor 42 transistors 43 Transistor 44 transistors 45 transistors 46 transistors 60 Sense amplifier circuit 62 Amplifier circuit 63 Switch Circuit 64 Precharge circuit 65 Amplifier circuit 66 Amplifier circuit 70 Cell Array 80 Drive circuit 81 Main amplifier 82 Input / Output Circuit 100 Capacitive element 110 Conductors 120 Conductors 130 Insulator 200 transistors 203 Conductors 205 Conductors 210 Insulator 212 Insulator 214 Insulator 216 Insulator 220 Insulator 222 Insulator 224 Insulator 230 Oxides 230a oxide 230b oxide 230c oxide 231 areas 231a area 231b area 232 areas 232a area 232b area 234 areas 239 areas 240 Conductors 240a Conductor 240b conductor 242 layers 250 Insulator 252 Metal Oxides 260 Conductors 260a Conductor 260b conductor 270 Insulator 271 Insulators 273 Insulators 274 Insulators 275 Insulators 280 Insulator 500 transistors 503 Conductors 505 Conductors 524 Insulator 530 Oxides 530a oxide 530b oxide 530c oxide 540 Conductors 540a Conductor 540b Conductor 542 layers 550 Insulator 552 Metal Oxides 560 Conductors 560a Conductor 560b Conductor 570 Insulator 571 Insulator 575 Insulator 600 Semiconductor devices 2100 Robot 2101 Illuminance sensor 2102 Microphone 2103 Upper Camera 2104 Speaker 2105 Display 2106 Lower Camera 2107 Obstacle Sensor 2108 Moving mechanism 2110 Arithmetic equipment 2130 Portable Information Terminal 2131 Portable Microphone 5100 Cleaning Robot 5101 Display 5102 Camera 5103 Brush 5104 Operation button 5120 Garbage 5140 Portable Information Terminal 7000 electronic components 7002 Printed circuit board 7004 Mounting board 7031 PCB 7032 layers 7033 layers 7034 layers 7400 Electronic Components 7411 Package Substrate 7421 Lens Cover 7435 Lens 7441 rand 7451 image sensor chip 7461 Electrode Pads 7471 Wire 7490 IC chip

Claims

[Claim 1] An inverter; a first transistor; a second transistor; and a capacitive element; an input unit; an output unit, the semiconductor device is electrically connected to a first control line and a second control line; a first terminal of the capacitive element electrically connected to the input section; a second terminal of the capacitance element electrically connected to an input terminal of the inverter; the first transistor has a function as a switch that connects an input terminal and an output terminal of the inverter to or from a conductive state; the second transistor has a function as a switch that connects the output terminal of the inverter and the output section to conduction or non-conduction, a gate of the first transistor electrically connected to the first control line; a gate of the second transistor electrically connected to the second control line;

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