Memory device

Abstract

To provide a novel memory device.SOLUTION: A memory device has a plurality of memory cells, in which one memory cell includes: a first transistor; and a second transistor. One of a source and a drain of the first transistor is electrically connected to a gate of the second transistor through a node SN. Information written via the first transistor is held in the node SN. When an OS transistor is used as the first transistor, it is possible to eliminate the need to form a storage capacitor. By providing a region having a low relative dielectric constant outside each memory cell, external noise can be reduced and stable operation can be realized.SELECTED DRAWING: Figure 1

Description

[Technical Field]

[0001] TECHNICAL FIELD One aspect of the present invention relates to a storage device.

[0002] Another aspect of the present invention relates to an article, a method, or a manufacturing method. The term "process, machine, manufacture, or composition" is used interchangeably. One embodiment of the present invention relates to a driving method thereof or a manufacturing method thereof.

[0003] In this specification and the like, a semiconductor device is a device that can function by utilizing semiconductor characteristics. This refers to a general category of devices, including storage devices, display devices, electro-optical devices, power storage devices, semiconductor circuits, and electronic devices. In addition, the present invention may be applied to a storage device, a display device, an electro-optical device, a power storage device, etc. The device, semiconductor circuit, and electronic device can also be called a semiconductor device. [Background technology]

[0004] Silicon-based semiconductor materials are widely known as semiconductor thin films that can be used in transistors. However, other materials include oxide semiconductors (OS). ) is attracting attention. Examples of oxide semiconductors include indium oxide and zinc oxide. Not only oxides of single metals but also oxides of multi-component metals are known. Among these, research on In-Ga-Zn oxide (hereinafter referred to as IGZO) is particularly focused. is being actively carried out.

[0005] Research on IGZO has revealed that, among oxide semiconductors, it is neither single-crystal nor amorphous, AC (c-axis aligned crystalline) structure and nc (na A noncrystalline structure was found (see Non-Patent Documents 1 to 3). In Non-Patent Documents 1 and 2, oxide semiconductors having a CAAC structure are used. The technology for fabricating a transistor is also disclosed. Even oxide semiconductors with lower crystallinity than those containing SiO2 have minute crystals, as reported in Non-Patent Document 4 and and Non-Patent Document 5.

[0006] Furthermore, transistors using IGZO as the active layer have extremely low off-state current (non-specific (See Patent Document 6.) LSIs and displays that utilize these properties have been reported (non- See Patent Document 7 and Non-Patent Document 8.

[0007] In addition, a transistor having an oxide semiconductor in a channel formation region (hereinafter referred to as an “OS transistor”) Various semiconductor devices using these devices have been proposed. .

[0008] Patent Document 1 discloses an example in which an OS transistor is used in a memory cell (memory element) of a memory device. In the off state, an OS transistor allows current to flow between the source and drain ( Since the off-state current (also called "off-state current") is very small, the storage capacitance used in the memory element can be reduced. By reducing or eliminating the storage capacitance, the integration density can be reduced. High memory capacity can be achieved. [Prior art documents] [Patent documents]

[0009] [Patent Document 1] Japanese Patent Application Laid-Open No. 2012-256400 [Non-patent literature]

[0010]

Non-licensed literature 1

Non-licensed Document 2

Non-licensed Document 4

Non-licensed Document 5

Non-licensed Document 6

Non-licensed Document 7

[0011] However, reducing or eliminating the storage capacitance can lead to a decrease in data retention time and the This causes a problem that the memory element is easily affected by operational noise and the like.

[0012] An object of one embodiment of the present invention is to provide a semiconductor device with high integration density. An object of one embodiment of the present invention is to provide a semiconductor device with high operating speed. An object of one embodiment of the present invention is to provide a semiconductor device that can retain data for a long period of time. Another embodiment of the present invention is to provide a semiconductor device with reduced power consumption. An object of one embodiment of the present invention is to provide a novel semiconductor device. do.

[0013] It should be noted that the description of multiple problems does not preclude the existence of each problem. The embodiments do not necessarily solve all of these problems. These problems are also clearly evident from the description of the present invention, such as drawings and claims. This could be a form of challenge for Ming. [Means for solving the problem]

[0014] One embodiment of the present invention is a memory device having a plurality of memory cells, wherein one memory cell is The present invention has a first transistor and a second transistor. One of the drains is electrically connected to the gate of the second transistor via a node SN. The information written via the first transistor is held at node SN. By using an OS transistor as the first transistor, it is not necessary to form a storage capacitor. A region with a low dielectric constant is provided outside the memory cell.

[0015] Alternatively, one aspect of the present invention is a memory cell, a first region, a first word line, and a second word line. a first bit line and a second bit line, and the memory cell is a first transistor and a second transistor, the semiconductor layer of which is a metal oxide the first region has a plurality of voids, and the first bit line and the second bit line are arranged in a first direction. The first word line and the second word line extend in a second direction, and the gate of the first transistor The first transistor is electrically connected to the first word line, and the first transistor is connected to either the source or the drain of the first transistor. is electrically connected to the gate of the second transistor and the source or drain of the first transistor. The other input is electrically connected to the first bit line, and the other input is electrically connected to the source or drain of the second transistor. One of the terminals is electrically connected to the second word line, and the other terminal is the source or drain of the second transistor. the other of the first and second bit lines is electrically connected to the second bit line, and the first region has a region extending in a first direction. In the region extending in the first direction, each of the plurality of voids is It is a storage device having an area extending to.

[0016] Alternatively, one aspect of the present invention is a memory cell, a first region, a first word line, and a second word line. a first bit line, a second bit line, and a first conductive layer, The recell has a first transistor and a second transistor, and the semiconductor of the first transistor The body layer has a metal oxide, the first region has a plurality of voids, and the first bit line and the second bit line The lines extend in a first direction, the first word line and the second word line extend in a second direction, and the first transistor The gate of the first transistor is electrically connected to the first word line, and the source or One of the drains is electrically connected to the gate of the second transistor, and the other of the drains is electrically connected to the source of the first transistor. The other of the source and drain of the second transistor is electrically connected to the first bit line. The source or drain of the second transistor is electrically connected to the second word line. Alternatively, the other of the drains is electrically connected to a second bit line, and the first conductive layer is a region overlapping the semiconductor layer of the first transistor and one of the source and drain of the second transistor; and an area overlapping each other, the first area having an area extending in a first direction, In the region extending in the direction perpendicular to the first direction, each of the plurality of voids extends in a direction intersecting the first direction. It is a storage device that has an area.

[0017] The first conductive layer has a region that functions as a back gate of the first transistor.

[0018] The semiconductor layer preferably contains at least one of In and Zn, or both.

[0019] The first region may have a region extending in the second direction. In the region extending in the second direction, The plurality of voids are each a region extending in a direction intersecting the second direction. It is preferred that the compound has the following structure:

[0020] The area where the gate electrode of the second transistor overlaps with the semiconductor layer is For example, the area of ​​the gate electrode of the second transistor is preferably larger than the area of ​​the semiconductor layer. The area where the gate electrode of the first transistor and the semiconductor layer overlap is It is preferable that the area is 1 to 10 times the area. [Effects of the Invention]

[0021] According to one embodiment of the present invention, a semiconductor device with high integration density can be provided. According to one embodiment of the present invention, a semiconductor device with high operating speed can be provided. According to one embodiment, a semiconductor device capable of retaining data for a long period of time can be provided. According to one embodiment of the present invention, a semiconductor device with reduced power consumption can be provided. Furthermore, according to one embodiment of the present invention, a novel semiconductor device can be provided.

[0022] The description of these effects does not preclude the existence of other effects. An embodiment does not necessarily have all of these effects. Effects other than these may be included in the description, This becomes clear from the description, drawings, claims, etc. From any description, it is possible to extract effects other than these. [Brief explanation of the drawings]

[0023] [Figure 1] FIG. 1 is a diagram illustrating an example of the configuration of a semiconductor device. [Figure 2] 2A to 2C are diagrams illustrating configuration examples of a cell array and memory cells. [Figure 3] FIG. 3 is a timing chart illustrating the operation of the memory cell. [Figure 4] 4A and 4B are diagrams illustrating the electrical characteristics of a transistor. [Figure 5]5A to 5F are diagrams illustrating examples of the configuration of a memory cell. [Figure 6] FIG. 6 is a diagram illustrating an example of the configuration of a cell array. [Figure 7] FIG. 7 is a diagram illustrating an example of the configuration of a cell array. [Figure 8] FIG. 8 is a diagram illustrating an example of the configuration of a cell array. [Figure 9] FIG. 9 is a diagram illustrating an example of the configuration of a cell array. [Figure 10] 10A and 10B are diagrams illustrating an example of the configuration of a memory cell. [Figure 11] FIG. 11 is a cross-sectional view illustrating an example of the configuration of a memory cell. [Figure 12] FIG. 12 is a diagram illustrating an example of the configuration of a memory cell. [Figure 13] FIG. 13 is a cross-sectional view illustrating an example of the configuration of a memory cell. [Figure 14] FIG. 14 is a diagram illustrating an example of the configuration of a memory cell. [Figure 15] FIG. 15 is a diagram illustrating an example of the configuration of a memory cell. [Figure 16] FIG. 16 is a diagram illustrating an example of the configuration of a memory cell. [Figure 17] 17(A) and 17(B) are diagrams illustrating an example of the configuration of the low relative dielectric constant region. [Figure 18] 18(A) and 18(B) are diagrams illustrating an example of the configuration of a low relative dielectric constant region. [Figure 19] 19(A) and 19(B) are diagrams illustrating an example of the configuration of a low relative dielectric constant region. [Figure 20] 20(A) and 20(B) are diagrams illustrating an example of the configuration of the low relative dielectric constant region. [Figure 21] 21(A) and 21(B) are diagrams illustrating an example of the configuration of a low relative dielectric constant region. [Figure 22] 22(A) and 22(B) are diagrams illustrating an example of a manufacturing process for a low relative dielectric constant region. [Figure 23] 23(A) to 23(C) are diagrams illustrating an example of a manufacturing process for a low relative dielectric constant region. [Figure 24] 24(A) and 24(B) are diagrams illustrating an example of a manufacturing process for a low relative dielectric constant region. [Figure 25] FIG. 25 is a diagram illustrating an example of the configuration of a memory cell. [Figure 26] FIG. 26 is a cross-sectional view illustrating an example of the configuration of a memory cell. [Figure 27] FIG. 27 is a diagram illustrating an example of the configuration of a memory cell. [Figure 28] FIG. 28 is a cross-sectional view illustrating an example of the configuration of a memory cell. [Figure 29] 29A to 29C illustrate structural examples of transistors. [Figure 30] 30A to 30C illustrate structural examples of transistors. [Figure 31] 31(A) and 31(B) are diagrams illustrating electronic components. [Figure 32] FIG. 32 is a diagram illustrating an electronic device. [Figure 33] 33(A) to 33(E) are diagrams illustrating electronic devices. [Figure 34] 34A to 34C are diagrams illustrating electronic devices. [Figure 35] 35(A) to 35(C) are diagrams illustrating electronic devices. [Figure 36] FIG. 36 is a diagram showing various storage devices by hierarchy. [Figure 37] FIG. 37 is a diagram showing data write times and write endurances of various storage devices. [Figure 38] FIG. 38 is a diagram showing the data retention time and operating frequency of various storage devices. DETAILED DESCRIPTION OF THE INVENTION

[0024] The present invention will be described in detail with reference to the accompanying drawings. and the present invention is not limited to the above, and the form and details thereof may be changed without departing from the spirit and scope of the present invention. It will be readily apparent to those skilled in the art that various modifications may be made to the present invention. The present invention should not be construed as being limited to the contents of the embodiments and examples.

[0025] In the configuration of the invention described below, the same parts or parts having similar functions are The same reference numerals are used in common between different drawings, and repeated explanations thereof will be omitted. When referring to a function, the hatch pattern may be the same and no particular symbol may be assigned.

[0026] In each drawing described in this specification, the size of each component, the thickness of a layer, or the area is not clearly indicated. The figures may be exaggerated for clarity and are not necessarily limited to that scale. .

[0027] In this specification, the high power supply potential is referred to as the H level (also referred to as "VDD" or "H potential"). ), and low power supply potential is sometimes called the L level (also called "VSS" or "L potential"). be.

[0028] Voltage refers to the potential difference between two points, and potential refers to the electrostatic field at a certain point. It refers to the electrostatic energy (electrical potential energy) of a unit charge in a particle. Generally, the potential difference between the potential at a certain point and a reference potential (for example, ground potential) is This is simply called potential or voltage, and potential and voltage are often used synonymously. Therefore, in this specification and the like, unless otherwise specified, potential may be read as voltage. , voltage may be read as potential.

[0029] In addition, the present specification can be appropriately combined with the following embodiments and examples. In addition, when a plurality of configuration examples are shown in one embodiment, the configuration examples may be combined as appropriate. It is possible to combine

[0030] In this specification, metal oxide refers to a metal oxide in a broad sense. Metal oxides are oxides. Metal oxides are oxide insulators and oxide conductors (including transparent oxide conductors). For example, metal oxide is used in the semiconductor layer of a transistor. In this case, the metal oxide is sometimes called an oxide semiconductor. In the above description, a transistor having a metal oxide or an oxide semiconductor is used. In this specification and the like, metal oxides containing nitrogen are also referred to as metal oxides. Sometimes referred to collectively.

[0031] In addition, unless otherwise specified, the transistors shown in this specification and the like are enhancement transistors. The transistor is a normally-off n-channel field effect transistor. The threshold voltage (also referred to as "Vth") is greater than 0V.

[0032] (Embodiment 1) In this embodiment, a storage device according to one embodiment of the present invention will be described.

[0033] <Storage device> 1 is a block diagram showing an example of the configuration of a storage device. , and a cell array 201. The peripheral circuit 111 includes a row decoder 121, a word line driver circuit 122, column decoder 131, bit line driver circuit 130, output circuit 1 40 and a control logic circuit 160. The cell array 201 includes memory cells 21 1, having word lines WWL, word lines RWL, bit lines WBL, and bit lines RBL; .

[0034] The word line driver circuit 122 supplies a potential to the word line WWL and the word line RWL. The bit line driver circuit 130 includes a precharge circuit 132 and an amplifier circuit 13 3, and an input / output circuit 134. The precharge circuit 132 is connected to the bit line RBL etc. The amplifier circuit 133 has a function of precharging the data read from the wiring RBL. It has the function of amplifying the data signal.

[0035] The word line WWL, the word line RWL, the bit line WBL, and the bit line RBL are connected to the memory cell The amplified data signal is output to the The digital data signal RDATA is output to the outside of the storage device 100 via the circuit 140. Be encouraged.

[0036] The storage device 100 is supplied with VDD and VSS as power supply potentials from the outside.

[0037] The storage device 100 also receives a clock signal CLK and a chip enable signal CE from the outside. , a write enable signal WE, a read enable signal RE, an address signal ADDR, and data signal WDATA, etc. are input. The address signal ADDR is input to the row decoder 121 and a column decoder 131, and the data signal WDATA is input to the input / output circuit 13 It is entered into 4.

[0038] The control logic circuit 160 outputs a chip enable signal CE, a write enable signal CE, and a write enable signal CE. The row decoder 121 processes the read enable signal WE and the read enable signal RE. For example, when the chip enable signal CE is at a high level, When the write enable signal WE is at a low level, the row decoder 121 and the column decoder 1 31 performs a read operation, and the chip enable signal CE is high and the write enable signal When the write signal WE is at a high level, the row decoder 121 and the column decoder 131 When the chip enable signal CE is at low level, Regardless of whether the signal WE is high or low, the row decoder 121 and the column decoder The driver 131 can be in standby mode.

[0039] The signals processed by the control logic circuit 160 are not limited to these. Other signals may be input to the control logic circuit 160 as desired.

[0040] It should be noted that the above-mentioned circuits and signals can be appropriately selected or omitted as required.

[0041] The transistors constituting the cell array 201 can be OS transistors. In addition, OS transistors can be used as transistors that configure the peripheral circuit 111. By forming the cell array 201 and the peripheral circuit 111 using OS transistors, The cell array 201 and the peripheral circuit 111 can be manufactured in the same manufacturing process. This allows for lower manufacturing costs.

[0042] In addition, OS transistors are used not only in memory devices but also in CPUs (Central Processors) Sing Unit) or GPU (Graphics Processing Unit) It can also be applied to logic circuits such as those using OS transistors. The general term for these integrated circuits is also called "OS-LSI."

[0043] [Example of cell array configuration] FIG. 2A shows the details of the cell array 201. The cell array 201 has m (m is ) in each line (n is an integer greater than or equal to 1), for a total of m × n messages. The memory cells 211 are arranged in rows and columns.

[0044] 2A, the address of the memory cell 211 is also shown. For example, [1,1 ] indicates the memory cell 211 located at the address of the first row and first column, [i, j] (i is m is an integer between 1 and m, and j is an integer between 1 and n. The memory cell 211 located in the cell array 201 and the word line driver 202 are shown. The number of wirings connecting the driver circuit 122 depends on the configuration of the memory cells 211 and the number of wirings included in one column. The number of memory cells 211 to be connected is determined by the number of memory cells 211 to be connected. The number of wirings connecting the buffer circuit 130 to the memory cell 211 is determined by the configuration of the memory cell 211 and the number of wirings included in one row. It is determined by the number of memory cells 211, etc.

[0045] In this embodiment, the cell array 201 includes n bit lines WBL (WBL[1] to WBL[2]). L[n]), n bit lines RBL (RBL[1] to RBL[n]), m word lines WWL (WWL[1] to WWL[m]) and m word lines RWL (RWL[1 ] to RWL[m]).

[0046] The memory cell 211 is connected to a bit line WBL, a bit line RBL, a word line WWL, and a word line WWL. As shown in Figure 2(A), the memory cell with address [i,j] is connected to the line RWL. The word line driver 211 is connected to the word line driver 212 via the word line WWL[i] and the word line RWL[i]. The bit line WBL[j] and the bit line RBL[j] are electrically connected to the buffer circuit 122. The bit line driver circuit 130 is electrically connected to the bit line driver circuit 130 via the MOS transistor 140 .

[0047] [Example of memory cell configuration] 2B, 2C, and 5A to 5D show circuits applicable to the memory cell 211. An example of the configuration is shown in Figure 2(B). 1 shows an example of the circuit configuration of a memory cell 211A of the 2Tr1C type (also called the "2Tr1C type"). The filter 211A includes a transistor M11, a transistor M12, and a capacitance element Cs. do.

[0048] In the memory cell 211A, either the source or the drain of the transistor M11 is a capacitor. The first terminal of the element Cs is electrically connected to the gate of the transistor M12. The other of the source and drain of the transistor M11 is electrically connected to the bit line WBL. The gate of the transistor M11 is electrically connected to the word line WWL. One of the source and drain of the transistor M1 is electrically connected to the word line RWL. The other of the source and drain of the transistor 2 is electrically connected to the bit line RBL. The second terminal of the capacitance element Cs is electrically connected to the wiring CAL. This transistor functions as a wiring for applying a predetermined potential to the second terminal of Cs. the first terminal of the capacitance element Cs, and the source or drain of the transistor M12. The node to which the gates are electrically connected is called a node SN.

[0049] The bit line WBL functions as a write bit line, and the bit line RBL functions as a read bit line. The word line WWL serves as a write word line, and the word line RWL serves as a , which functions as a read word line. The transistor M11 is connected between the node SN and the bit line WB It functions as a switch that makes L conductive or non-conductive.

[0050] The data write operation and data read operation of the memory cell 211A will be explained with reference to FIG. FIG. 3 is a timing chart for explaining the operation of the memory cell 211A. Data is written by setting the word line Applying VDD to WWL turns on the transistor M11 (also called the "ON state"). This is done by electrically connecting the node SN and the bit line WBL. The potential of the word line RWL is set to VDD. The potential of the bit line RBL is also set to VDD. is preferred.

[0051] Specifically, when the transistor M11 is in the on state, A corresponding potential (for example, VDD) is applied to the bit line WBL, and the The potential is written to the node SN. After that, VSS is applied to the word line WWL, and the transistor By making the transistor M11 non-conductive (also called "off state"), the voltage of the node SN is Hold the position.

[0052] Between the gate of transistor M11 and either the source or drain of transistor M11 The word line WWL and the node SN are connected via the parasitic capacitance Cz. Therefore, when the write operation is completed, the potential of the word line WWL is changed from VDD to VS When the potential at node SN is decreased to S, the potential at node SN decreases by a voltage ΔV1.

[0053] If the capacitance of node SN is Csn, the voltage ΔV1 is the ratio of the parasitic capacitance Cz to the capacitance Csn. The larger the capacitance Csn is compared to the parasitic capacitance Cz, the smaller the voltage ΔV1 can be. Cut.

[0054] The capacitance Csn includes the parasitic capacitance Cx generated at the node SN and the gate capacitance of the transistor M12. By increasing the gate capacitance of the transistor M12, the capacitance Csn can be reduced. It can be made bigger.

[0055] The capacitance value of the parasitic capacitance Cz is proportional to the gate capacitance of the transistor M11. The parasitic capacitance Cx is proportional to the gate width of the transistor M12. If the gate capacitance of the transistor M12 is sufficiently smaller than the capacitance of the capacitor Csn, In this case, the gate capacitance of the transistor M12 is By making it larger than the capacitance of the resistor, the voltage ΔV1 can be reduced.

[0056] Data is read out by applying a signal to the bit line RBL during the data read period (Tread). A constant potential is applied to the bit line RBL, and then the bit line RBL is set to an electrically floating state. Then, a low level potential is applied to the word line RWL. A predetermined potential is applied to the bit line RBL, and then the bit line RBL is set to a floating state. This is expressed as precharging the bit line RBL.

[0057] For example, precharge the bit line RBL with VDD, then apply VSS to the word line RWL. At this time, the potential difference between the node SN and the word line RWL is equal to the threshold voltage of the transistor M12. If the potential difference is equal to or greater than the voltage, the potential of the bit line RBL decreases at a rate corresponding to the potential difference. That is, by knowing the potential change of the bit line RBL, the potential held in the node SN can be read. It is possible.

[0058] The row in which the memory cell 211A to which data is written is arranged is the row to which VDD is applied. The row in which the memory cell 211 selected by the code line WWL and from which data is read is arranged. is selected by applying VSS to the word line RWL. In the row in which the memory cell 211 is arranged, VSS is applied to the word line WWL, and data is read. The row in which the memory cell 211A that does not protrude is arranged is connected to the word line RWL and the bit line RBL By applying a potential equal to or higher than the precharge potential to the gate, the gate can be deselected.

[0059] Here, the transistors M11 and M12 have a metal oxide in the channel forming region. For example, a transistor having an oxide (OS transistor) can be used. Indium, element M (element The element M is aluminum, gallium, yttrium, copper, vanadium, beryllium, or boron. , titanium, iron, nickel, germanium, zirconium, molybdenum, lanthanum, cerium Choose from aluminum, neodymium, hafnium, tantalum, tungsten, or magnesium. A metal oxide having either one of the following may be used: In particular, metal oxides of indium, gallium, and zinc are preferred.

[0060] Since the off-state current of the OS transistor is very small, the OS transistor is used as the transistor M11. By using the capacitor, the potential written to the node SN can be maintained for a long time. Therefore, data written in the memory cell 211A can be retained for a long time.

[0061] There is no particular limitation on the transistor used for the transistor M12. Alternatively, an OS transistor, a Si transistor, or other transistors may be used. .

[0062] When a Si transistor is used for the transistor M12, the semiconductor in which the channel is formed is The silicon used for the body layer can be amorphous silicon, polycrystalline silicon, or low-temperature polysilicon (LTP). S: Low Temperature Poly-Silicon, or single crystal silicon Si transistors have higher field-effect mobility than OS transistors. Therefore, if a Si transistor is used as the readout transistor, This allows for increased speed during ejection.

[0063] An OS transistor is used for the transistor M11, and a Si transistor is used for the transistor M12. When an OS transistor is used, the two may be stacked in different layers. It can be manufactured using the same manufacturing equipment and process as the transistor. It is easy to combine OS transistors and Si transistors (hybridization), allowing for high integration. It is also easy.

[0064] In addition, if an OS transistor is used for transistor M12, the leakage current when not selected can be minimized. This can reduce the number of transistors M1 and M2, thereby improving the read accuracy. By using OS transistors for both the transistor M1 and the transistor M12, For example, the manufacturing process can be reduced to a temperature of 400°C or less. A semiconductor device can also be manufactured by

[0065] In this specification and the like, an OS transistor is used as the transistor M11, and a 2Tr1C type The memory device that consists of these memory cells is called NOSRAM (Non-volatile Oxide Random Access Memory). Semiconductor Random Access Memory .

[0066] As mentioned above, the memory cell 211A is a 2Tr1C type memory cell. 11A is a circuit for storing the accumulated charge in a transistor even when the capacitance element Cs for storing the charge is small. By amplifying it with M12, it can function as a memory. An OS transistor is used for the transistor M11 because the off-state current of the transistor is very small. This allows the capacitance element Cs to be reduced or eliminated.

[0067] FIG. 2(C) shows a DRAM (Dynamic Random Access Memory) with one transistor and one capacitor. An example of the circuit configuration of a random access memory (Random Access Memory) type memory cell 211R is shown below. The memory cell 211R includes a transistor M11 and a capacitance element Cs. .

[0068] In the memory cell 211R, either the source or the drain of the transistor M11 is a capacitor. The first terminal of the element Cs is electrically connected to the source or drain of the transistor M11. The other end is electrically connected to the bit line BL, and the gate of the transistor M11 is connected to the word line WL The second terminal of the capacitance element Cs is electrically connected to the wiring CAL. The wiring CAL is a wiring for applying a predetermined potential to the second terminal of the capacitance element CS. The source or drain of the transistor M11 and the capacitance element Cs The node to which the first terminal of is electrically connected is called node SN.

[0069] In the memory cell 211R, by using an OS transistor as the transistor M11, Therefore, the capacitance element Cs can be reduced or eliminated. The transistor M11 allows the data to be retained for a long time, which is the same as the reset of a DRAM memory cell. The refresh frequency can be reduced. Also, the refresh frequency of DRAM memory cells can be reduced. The action can be made unnecessary.

[0070] In this specification, an OS transistor is used as the transistor M11, and a DRAM type The memory device that consists of memory cells is called DOSRAM (Dynamic Oxide Semiconductor RAM). Conductor Random Access Memory).

[0071] By using OS transistors, the area occupied by memory cells can be reduced. Therefore, it is easy to miniaturize or highly integrate the memory device.

[0072] Here, we will explain the temperature dependence of the Id-Vg characteristic, which is one of the electrical characteristics of a transistor. 4A and 4B show the Id- An example of the Vg characteristic is shown below. The Id-Vg characteristic is the drain current vs. gate voltage (Vg). The horizontal axis in Figure 4(A) and Figure 4(B) shows the change in current (Id). The vertical axis in Figure 4(A) and Figure 4(B) shows Id on a logarithmic scale. is doing.

[0073] FIG. 4A shows the Id-Vg characteristics of an OS transistor. A transistor that uses silicon in the semiconductor layer where the transistor is formed ("Si transistor" or The Id-Vg characteristics of the Si-FET are shown in Fig. 4(A) and FIG. 4B shows the Id-Vg characteristics of both n-channel transistors.

[0074] As shown in Figure 4(A), the off-state current of the OS transistor increases even when it is operated in a high-temperature environment. The operating temperature of OS transistors is 125°C or higher and 150°C or lower, with a 10-digit Furthermore, the OS transistor's Vth Therefore, the frequency decreases as the operating temperature increases. On the other hand, as shown in Figure 4(B), the thermal characteristics of Si transistors tend to increase. As the temperature rises, the off-state current also increases. shifts in the positive direction, and the on-current decreases.

[0075] By using OS transistors as the transistors M11 and M12, It is possible to achieve long-term data retention even under high temperature conditions. The power consumption of the storage device can be reduced.

[0076] By using OS transistors as the transistors M11 and M12, For example, at a drive voltage of 2.5V and an operating temperature range of -40°C to 85°C, It is possible to achieve an operating frequency of 100 Hz or more.

[0077] FIG. 5A shows an example of a circuit configuration of a memory cell 211 that does not include a capacitor Cs. The memory cell 211B shown in FIG. 1 has a circuit configuration in which the capacitance element Cs is removed from the memory cell 211A. In the memory cell 211B, the charge (potential) written to the node SN is mainly transferred to the transistor. It is held by the gate capacitance of transistor M12 and the parasitic capacitance Cx. It can also be considered as part of the parasitic capacitance Cx.

[0078] In addition, a back gate is provided to one or both of the transistor M11 and the transistor M12. A transistor having the following structure may also be used.

[0079] In an actual transistor, the gate and back gate are connected to the channel forming region of the semiconductor layer. The gate and back gate are both placed on top of each other. Therefore, when one is called a "back gate," the other is called a "gate" or "front gate." One is sometimes called the "First Gate" and the other the "Second Gate." This is sometimes the case.

[0080] The back gate may be at the same potential as the gate, or at ground potential or any other potential. In addition, by changing the back gate potential independently of the gate, the transistor The threshold voltage of the transistor can be changed.

[0081] By providing a back gate and by making the gate and back gate the same potential, In the conductor layer, the area in which carriers flow is larger in the film thickness direction, so As a result, the on-current of the transistor increases and the field effect The mobility increases.

[0082] Therefore, it is necessary to make the transistor have a large on-current relative to the area it occupies. In other words, the area occupied by the transistor can be reduced relative to the required on-current. Therefore, a highly integrated semiconductor device can be realized.

[0083] The transistors M11 and M12 are transistors having back gates (4 An example of a circuit configuration using a four-terminal transistor is shown in Figure 5( 5B) to (D). The memory cell 211C shown in FIG. 5B and the memory cell 211D shown in FIG. The cell 211D and the memory cell 211E shown in FIG. 5(D) are the same as the memory cell 211B. This is an example.

[0084] In the memory cell 211C shown in FIG. 5B, the gate and back gate of the transistor M11 The gate and back gate of the transistor M12 are electrically connected. is connected to.

[0085] In the memory cell 211D shown in FIG. 5C, the back gate of the transistor M11 and The back gate of the transistor M12 is electrically connected to the wiring BGL. A predetermined potential is applied to the back gates of the transistors M11 and M12 via the can be added.

[0086] The threshold voltages of the transistors M11 and M12 are controlled by the potential of the wiring BGL. Specifically, the voltage of the transistor M11 and the transistor M1 By increasing the potential applied to the back gate of 2, the threshold voltage of each The negative shift of the threshold voltage reduces the on-state current of the transistor. This allows the operating speed of the memory cell 211D to be increased.

[0087] In addition, the potential applied to the back gates of the transistors M11 and M12 is reduced. By increasing the threshold voltage, the threshold voltages of the respective transistors are shifted to the positive side. By shifting the voltage, the off-current of the transistor is reduced, and data is written to the memory cell 211D. The data stored can be retained for a long time.

[0088] In the memory cell 211E shown in FIG. 5D, the back gate of the transistor M11 is connected to the wiring W The back gate of the transistor M12 is electrically connected to the wiring RBGL. The back gate of transistor M11 and the back gate of transistor M12 are connected to By connecting each port to a different wiring, the threshold voltage can be changed independently. It is possible.

[0089] Note that a memory device using memory cells 211B to 211E is also called NOSRAM. can.

[0090] In addition, since the transistors shown in FIGS. 5B to 5D are four-terminal elements, MT Magnetic Tunnel Junction (MRAM) agnetoresistive Random Access Memory), Re RAM (Resistive Random Access Memory), Phase Change Memory Compared to two-terminal elements such as phase-change memory, This has the advantage that input and output can be controlled independently and easily.

[0091] In addition, MRAM, ReRAM, and phase change memory are constructed at the atomic level when rewriting information. On the other hand, in the memory device of one embodiment of the present invention, when data is rewritten, the structure of the memory device may change. It operates by repeatedly charging or discharging an electric charge through a transistor. It has the characteristics of excellent durability against repeated rewriting and little structural change.

[0092] If the memory cell 211 does not have a capacitor Cs, the node SN is easily affected by noise. Specifically, due to capacitive coupling between the node SN and the adjacent memory cell, As a result, the data retention time and read accuracy are reduced. This causes degradation and reduces the reliability of the storage device.

[0093] The noise can be reduced by reducing the parasitic capacitance generated between adjacent memory cells. In one aspect of the present invention, in order to reduce the parasitic capacitance between adjacent memory cells, Low dielectric constant region (LDR) The dielectric constant of the LDR is smaller than that of the adjacent insulating layer. That's fine.

[0094] For example, as shown in FIG. 5(E), an LDR 221 is provided outside the memory cell 211E. FIG. 6 shows memory cells 211[i,j] to 211[i,j] arranged in a matrix. i+1,j+2] and the LDR 221 shown in FIG. 5(E). In this example, the memory cell 211E shown in FIG. 5(D) is used as the memory cell 211.

[0095] 7 shows a modification of FIG. 6. As shown in FIG. 7, several LDRs 221 are connected. The LDR 221 shown in FIG. 7 has a region extending along the word line and a bipolar transistor. The area extends along the bit line.

[0096] Also, as shown in FIG. 5(F), one memory cell 211E is completely surrounded by an LDR 221. FIG. 8 shows memory cells 211[i,j] to 211[i,j] arranged in a matrix. 5(F) and the LDR 221 shown in FIG. In FIG. 8, the memory cell 211 is a memory cell 211E. The LDR 221 also has a region extending along the word line and a region extending along the bit line. do.

[0097] By providing an LDR, the influence of noise can be reduced and the reliability of the storage device can be improved. .

[0098] This embodiment mode can be implemented by appropriately combining with the configurations described in other embodiment modes. It is possible.

[0099] (Embodiment 2) In this embodiment, a planar configuration example and a cross-sectional configuration example of the memory cell 211 and the LDR 221 are shown. An example will be described with reference to the drawings.

[0100] FIG. 9 shows memory cells 211[i,j] to 211[i,j] arranged in a matrix. i+1,j+2]. Note that Fig. 9 shows a planar configuration example corresponding to the circuit diagram shown in Fig. 7. 10 is an example of a surface configuration.

[0101] In FIG. 9, two adjacent memory cells 211 are arranged in mirror symmetry. For example, memory cell 211[i,j] and memory cell 211[i,j+1] are mirror symmetric. In addition, the memory cell 211[i,j] and the memory cell 211[i+1,j] are also mirror symmetric. By arranging the memory cells 211 in this manner, contact plugs are formed between adjacent memory cells. This allows for sharing of memory cells 211 and allows for efficient arrangement of memory cells 211. This allows the degree of integration of the memory cells 211 to be increased.

[0102] <Plane configuration example> FIG. 10A shows an example of the planar configuration of the memory cell 211[i+1,j] in FIG.

[0103] One of the source and drain of the transistor M11 is connected to the conductive layer 360 via the electrode 341. The conductive layer 360 functions as the gate electrode of the transistor M12. The region including the electrode 341 and the conductive layer 360 functions as a node SN. The other of the source and drain of the transistor M11 is electrically connected to the conductive layer 339. 339 functions as a bit line WBL.

[0104] One of the source and drain of the transistor M12 is connected to the conductive layer 33 via the conductive layer 312. 3, and the other of the source or drain of the transistor M12 is electrically connected to the conductive layer 3 The conductive layer 333 functions as a word line RWL, and the conductive layer 338 functions as a bit line RBL.

[0105] The conductive layer 305 shown in FIG. 10A functions as a wiring RBGL, and the conductive layer 306 functions as a wiring The conductive layer 261 functions as the word line WBGL. A portion of the conductive layer 305 functions as a word line RWL. A part of the conductive layer 306 functions as a back gate electrode of the transistor M11. It functions as a gate electrode.

[0106] 9 and 10, the LDR 221 is connected along the bit line RBL (conductive layer 338). The region extends along the word line RWL, and the region extends along the word line RWL.

[0107] The memory cell 211 of one embodiment of the present invention does not include a capacitor Cs. The occupied area of ​​211 can be reduced. However, when the occupied area is reduced, It is easily affected by noise generated from adjacent memory cells. This makes it possible to reduce noise transmitted to node SN.

[0108] However, reducing the noise transmitted to node SN means that the noise generated at node SN is This also means that the parasitic capacitance of the node SN is reduced. The gate capacitance of the transistor M12 becomes dominant. The overlapping area of ​​the semiconductor layer 260 and the conductive layer 360 of the transistor M12 is increased. The gate capacitance of the transistor M12 may be increased. is effective in improving the potential drop of the node SN that occurs when the write operation is completed.

[0109] Specifically, the area where the semiconductor layer of the transistor M12 and the gate electrode overlap is It is preferably 1 to 5 times the area of ​​the semiconductor layer of M11 and the gate electrode overlapping each other, and more preferably 1 to 1 It is more preferable that the ratio is 0 times or less, and even more preferable that the ratio is 1 time or more and 50 times or less.

[0110] <Example of cross-sectional configuration> FIG. 11 shows the A1-A2 region, B1-B2 region, and C1 region shown by the dashed lines in FIG. 10(A). FIG. 10 is a diagram showing an example of a cross-sectional configuration of the -C2 portion.

[0111] In FIG. 11, a transistor M12 is provided on a substrate 301. The transistor M11 can have the same layered structure as the transistor M12. The insulating layer 309 and the insulating layer 326 are provided on the conductive layer 305 and the conductive layer 306. The insulating layer 322 and the insulating layer 324 are embedded in the insulating layer 326. is provided, and the semiconductor layer 260 is provided on the insulating layer 324 .

[0112] Furthermore, an insulating layer 354 and an insulating layer 380 are provided on the insulating layer 324 and the semiconductor layer 260. In addition, the conductive layer 360 and the conductive layer 261 are embedded in the insulating layer 380. An insulating layer 374 is provided on the insulating layer 380, the conductive layer 360, and the conductive layer 261, and the insulating layer 374 is provided on the insulating layer 380, the conductive layer 360, and the conductive layer 261. An insulating layer 381 is provided on layer 374 .

[0113] In addition, a conductive layer 312, a conductive layer 313, and a conductive layer 314 are provided over the insulating layer 381. The conductive layer 312 is electrically connected to either the source or the drain of the transistor M12. The conductive layer 313 is electrically connected to the other of the source and drain of the transistor M12. is connected.

[0114] In addition, an insulating layer 31 is formed on the insulating layer 381, the conductive layer 312, the conductive layer 313, and the conductive layer 314. 1 and an insulating layer 315 are provided on the insulating layer 315. A conductive layer 332 and a conductive layer The conductive layer 332 is connected to the conductive layer 31 via the contact plug 317. 3, and the conductive layer 333 is electrically connected to the conductive layer 314 via the contact plug 318. and is electrically connected.

[0115] On the insulating layer 315, the conductive layer 332, and the conductive layer 333, the insulating layer 331, the insulating layer 319, and the conductive layer 333 are formed. and an insulating layer 334 are provided. The LDR 221 is provided in a part of the insulating layer 319. The LDR221 is made up of multiple LDS235 (Low Dielectric Constant) c constant Space) for LDR221 and LDS235 will be explained later.

[0116] An insulating layer 334 is provided on the insulating layer 319 and the LDS 235. An insulating layer 335 and an insulating layer 336 are provided on the insulating layer 336. A conductive layer 338 is provided on the insulating layer 336. The conductive layer 338 is electrically connected to the conductive layer 332 via the contact plug 337. An insulating layer 343 is provided on the insulating layer 336 and the conductive layer 338.

[0117] <<Variation 1>> 12 and 13, a part of the conductive layer 306 is deformed to form the conductive layer 306. By overlapping the node SN with the node SN, the parasitic capacitance Cx generated at the node SN may be increased. 12 is a diagram showing an example of the planar configuration of the memory cell 211[i+1,j]. FIG. 1 is a diagram showing an example of the cross-sectional structure of the G1-G2 region indicated by the dashed dotted line.

[0118] 12 and 13, one of the source and drain of the transistor M11, the conductive layer 3 41 and the conductive layer 306 are provided so as to overlap as much as possible. By forming the capacitor Cs, the parasitic capacitance Cx associated with the node SN can be increased without providing a capacitance element Cs. It is possible.

[0119] In FIG. 12, the conductive layer 306 is hatched to clearly show the conductive layer 306. The conductive layer 306 is made of the same material and in the same manner as the conductive layer 305 that is not hatched. They can be formed simultaneously using the method.

[0120] <<Variation 2>> 14, the area of ​​the conductive layer 306 is increased, and the conductive layer 306 and the memory cell 2 The overlapping area of ​​11[i+1,j] may be increased.

[0121] <<Variation 3>> 15, the area of ​​the conductive layer 305 overlapping with the node SN is increased. The parasitic capacitance Cx associated with the node SN may be increased.

[0122] In FIG. 15, a portion of conductive layer 305 is modified to form the source or drain of transistor M11. On the other hand, the conductive layer 341 and the conductive layer 305 are provided so as to overlap as much as possible. By configuring in this way, the parasitic capacitance of the node SN can be reduced without providing a capacitance element Cs. The capacitance Cx can be increased.

[0123] In FIG. 15, the conductive layer 305 is hatched to clearly show the conductive layer 305. The conductive layer 305 is made of the same material and in the same manner as the conductive layer 306 that is not hatched. They can be formed simultaneously using the method.

[0124] <<Variation 4>> 16, the area of ​​the conductive layer 305 is increased, and the conductive layer 305 and the memory cell 2 The overlapping area of ​​11[i+1,j] may be increased.

[0125] <About the constituent materials> 〔substrate〕 There is no significant limitation on the material used as the substrate. For example, it can be an insulating substrate, a semiconductor substrate, or a conductive substrate. A conductive substrate may be used.

[0126] Examples of insulating substrates include glass substrates, quartz substrates, sapphire substrates, and stabilized zirconia substrates. substrates (such as yttria-stabilized zirconia substrates), resin substrates, etc.

[0127] The semiconductor substrate may be a semiconductor substrate made of silicon, germanium, or the like. Plates, or silicon carbide, silicon germanium, gallium arsenide, indium phosphide, acid There are also compound semiconductor substrates made of zinc oxide and gallium oxide. A semiconductor substrate having an insulating region, such as SOI (Silicon On Insulator) Alternatively, a substrate or the like may be used.

[0128] Conductive substrates include graphite substrates, metal substrates, alloy substrates, conductive resin substrates, etc. The substrates include substrates having metal nitrides and substrates having metal oxides. a substrate in which a conductor or a semiconductor is provided on a solid substrate, a substrate in which a conductor or an insulator is provided on a semiconductor substrate, and a substrate in which a semiconductor or an insulator is provided on a conductive substrate. The substrate may have elements mounted thereon. These include capacitance elements, resistance elements, switching elements, light-emitting elements, and memory elements. Use of semiconductor elements such as transistors and FIN-type transistors In other words, the substrate is not limited to being a simple support substrate, but can also be used as a substrate for other devices such as transistors. The substrate may also have a hole formed thereon.

[0129] [Insulating layer] Materials used for the insulating layer include oxides, nitrides, oxynitrides, and nitride oxides having insulating properties. , metal oxides, metal oxynitrides, metal oxynitrides, etc.

[0130] For example, as transistors become smaller and more highly integrated, the gate insulating layer becomes thinner. , problems such as leakage current may occur. By using igh-k materials, the voltage required for transistor operation can be reduced while maintaining the physical film thickness. On the other hand, the insulator that functions as the interlayer insulating layer uses a material with a low relative dielectric constant. This reduces the parasitic capacitance between the wirings. The material can be selected accordingly.

[0131] Insulators with high dielectric constants include gallium oxide, hafnium oxide, and zirconium oxide. oxides containing aluminum, aluminum and hafnium, oxides containing aluminum and hafnium oxides with silicon and hafnium, oxides with silicon and hafnium or nitrides with silicon and hafnium.

[0132] Insulators with low dielectric constants include silicon oxide, silicon oxynitride, and silicon nitride oxide. silicon nitride, silicon oxide with fluorine, silicon oxide with carbon, silicon oxide with added hydrogen and nitrogen, silicon oxide with pores, or resin. do.

[0133] In addition, when an OS transistor is used as a transistor, the transistor is Insulating layers (insulating layer 309, insulating layer 32) that have the function of suppressing the permeation of impurities and oxygen 2, insulating layer 354, and insulating layer 374, etc., to It has the function of suppressing the permeation of impurities such as hydrogen and oxygen. Examples of suitable insulators include boron, carbon, nitrogen, oxygen, fluorine, magnesium, and aluminum. aluminum, silicon, phosphorus, chlorine, argon, gallium, germanium, yttrium, A single layer of insulator containing zirconium, lanthanum, neodymium, hafnium, or tantalum Specifically, it is possible to suppress the permeation of impurities such as hydrogen and oxygen. Insulators that have this function include aluminum oxide, magnesium oxide, gallium oxide, Germanium oxide, yttrium oxide, zirconium oxide, lanthanum oxide, neodymium oxide , hafnium oxide, tantalum oxide, and other metal oxides, aluminum nitride, Use of metal nitrides such as titanium, titanium nitride, silicon nitride oxide, and silicon nitride. can be done.

[0134] The insulating layer that functions as a gate insulating layer has a region containing oxygen that is desorbed by heating. For example, an insulator having a region containing oxygen that is desorbed by heating is preferable. By forming a structure in which silicon nitride or silicon oxynitride is in contact with the semiconductor layer 260, The oxygen deficiency in layer 260 can be compensated for.

[0135] In this specification and the like, the term "nitride oxide" refers to a compound containing more nitrogen than oxygen. Also, oxynitrides refer to compounds that contain more oxygen than nitrogen. The content of Measurements can be made using techniques such as kScattering Spectrometry. .

[0136] In addition, when an oxide semiconductor, which is a type of metal oxide, is used as the semiconductor layer, In order to prevent an increase in the hydrogen concentration in the insulating layer, it is preferable to reduce the hydrogen concentration in the insulating layer. The hydrogen concentration in the insulating layer was measured using secondary ion mass spectroscopy (SIMS). Ion Mass Spectrometry) is 2×10 20 atoms / cm 3 Less than or equal to 5 x 10 19 atoms / cm 3 Less than 1×10, more preferably 19 atoms / cm 3 Less than 5 × 10, more preferably 18 atoms / cm 3 The following In particular, it is preferable to reduce the hydrogen concentration in the insulating layer in contact with the semiconductor layer.

[0137] In addition, when an oxide semiconductor, which is a type of metal oxide, is used as the semiconductor layer, In order to prevent an increase in the nitrogen concentration in the insulating layer, it is preferable to reduce the nitrogen concentration in the insulating layer. The nitrogen concentration in the insulating layer was measured by SIMS to be 5×10 19 atoms / cm 3 below, Preferably 5 x 10 18 atoms / cm 3 Less than 1×10, more preferably 18 atom s / cm 3 Less than 5 × 10, more preferably 17 atoms / cm 3 The following applies.

[0138] In addition, at least a region of the insulating layer that is in contact with the semiconductor layer and at least a region of the insulating layer that is in contact with the semiconductor layer are The region to be formed preferably has few defects, and is typically determined by electron spin resonance (ESR) It is preferable to have fewer signals observed in electron spin resonance. For example, the signal mentioned above is the E' center observed at a g value of 2.001. The E' center is caused by a dangling bond of silicon. For example, When a silicon oxide layer or a silicon oxynitride layer is used as the insulating layer, the E' center The resulting spin density is 3×10 17 spins / cm 3 Less than or equal to 5 x 10 16 s pins / cm 3 A silicon oxide layer or a silicon oxynitride layer as follows may be used.

[0139] In addition, if signals due to nitrogen dioxide (NO2) are observed in addition to the signals mentioned above, The signal is split into three signals due to the nuclear spin of N, The g value is 2.037 or more and 2.039 or less (considered the first signal), and 2.001 or more and 2. 003 or less (second signal), and 1.964 or more and 1.966 or less (third signal). This is observed in the sciatic nerve.

[0140] For example, the spin density of the signal caused by nitrogen dioxide (NO2) as an insulating layer is 1× 10 17 spins / cm 3 More than 1×10 18 spins / cm 3 Using an insulating layer that is less than It is preferable to have

[0141] In addition, nitrogen oxides (NO x ) forms a level in the insulating layer The level is located within the energy gap of the oxide semiconductor layer. Things (NO x ) diffuses to the interface between the insulating layer and the oxide semiconductor layer, the level As a result, the trapped electrons are transported between the insulating layer and the oxide. Since it remains near the interface of the semiconductor layer, it shifts the threshold voltage of the transistor in the positive direction. Therefore, it is recommended to use a film with a low content of nitrogen oxides as the insulating layer. By using the ion implantation method, the shift in the threshold voltage of the transistor can be reduced.

[0142] Nitrogen oxides (NO x As an insulating layer with a small amount of ) released, for example, a silicon oxynitride layer is used. The silicon oxynitride layer can be analyzed by thermal desorption spectroscopy (TDS). In the normal desorption spectroscopy, nitrogen oxides ( NO x ) is a membrane that releases more ammonia than water, and typically The amount is 1 x 10 18 pieces / cm 3 5x10 or more19 pieces / cm 3 The following is the case. The amount of monia released is higher when the temperature of the heat treatment in TDS is 50°C or higher and 650°C or lower, or This is the total amount in the range of 0°C to 550°C.

[0143] Nitrogen oxides (NO x ) reacts with ammonia and oxygen during heat treatment, By using an insulating layer with a high monia emission rate, nitrogen oxides (NO x ) is reduced.

[0144] In addition, at least one of the insulating layers in contact with the oxide semiconductor layer is formed from a material that releases oxygen by heating. Specifically, it is preferable to form the insulating layer by using an insulating layer having a surface temperature of 100°C. TDS is performed by heat treatment at temperatures between 100 and 500°C. The amount of oxygen released, converted to oxygen atoms, is 1.0 × 10 18 atoms / cm 3 That's it, 1. 0×10 19 atoms / cm 3 or more, or 1.0×10 20 atoms / cm 3 End It is preferable to use an insulating layer in which the The oxygen that is released is also called "excess oxygen."

[0145] Alternatively, an insulating layer containing excess oxygen can be formed by adding oxygen to an insulating layer. The treatment to add oxygen is carried out by heat treatment or plasma treatment in an oxidizing atmosphere. Alternatively, ion implantation, ion doping, plasma immersion ion implantation, etc. Oxygen may be added by using an oxygen injection method or the like. , 16 O2 or18 Oxygen gas such as O2, nitrous oxide gas, or ozone gas In this specification, the process of adding oxygen is referred to as "oxygen doping." The oxygen doping treatment may be performed by heating the substrate.

[0146] The insulating layer may be made of polyimide, acrylic resin, benzocyclobutene resin, polyamide resin, or the like. Organic materials having heat resistance, such as amides and epoxy resins, can be used. In addition to the electrical materials, low-k materials, siloxane resins, PSG (Lingala It is possible to use materials such as BPSG (borophosphorus glass) and BPSG (borophosphorus glass). The insulating layer may be formed by stacking a plurality of insulating layers formed of the insulating material.

[0147] Siloxane-based resin is a Si-OS compound formed using siloxane-based materials as starting materials. The siloxane resin corresponds to a resin containing an i bond. Alternatively, an organic group having a fluoro group may be used. That's fine.

[0148] The method for forming the insulating layer is not particularly limited. Depending on the material used for the insulating layer, a firing process may be used. In this case, the insulating layer firing process can be performed in combination with other heat treatment processes, which can improve efficiency. This makes it possible to manufacture transistors efficiently.

[0149] The method for forming the insulating layer is not particularly limited. Depending on the material used for the insulating layer, a firing process may be used. In this case, the insulating layer firing process can be performed in combination with other heat treatment processes, which can improve efficiency. This makes it possible to manufacture transistors efficiently.

[0150] [Conductive Layer] The conductive layer may be made of aluminum, chromium, copper, silver, gold, platinum, tantalum, nickel, or titanium. Niobium, molybdenum, tungsten, hafnium, vanadium, niobium, manganese, magnesium Sodium, zirconium, beryllium, indium, ruthenium, iridium, strontium a metal element selected from the group consisting of ruthenium, lanthanum, etc., or an alloy containing the above-mentioned metal element; It is preferable to use an alloy or the like that combines the above-mentioned metal elements. For example, tantalum nitride , titanium nitride, tungsten, nitrides containing titanium and aluminum, tantalum and aluminum Ruthenium nitrides, ruthenium oxides, ruthenium nitrides, strontium and ruthenium It is preferable to use oxides containing lanthanum and nickel, or oxides containing lanthanum and nickel. titanium nitride, titanium and aluminum nitride, tantalum and aluminum nitride Ruthenium nitrides, ruthenium oxides, ruthenium nitrides, oxides containing strontium and ruthenium Oxides containing lanthanum and nickel are conductive materials that are resistant to oxidation or absorb oxygen. It is preferable because it is a material that maintains conductivity even after the addition of impurity elements such as phosphorus. Highly conductive semiconductors, such as polycrystalline silicon, and silicon silicides, such as nickel silicide, A reside may also be used.

[0151] Alternatively, a plurality of conductive layers made of the above materials may be stacked. Alternatively, a laminated structure may be used in which a material containing a metal element and a conductive material containing oxygen are combined. In addition, a laminated structure combining a material containing the above-mentioned metal element and a conductive material containing nitrogen is also available. Also, the material containing the metal element, the conductive material containing oxygen, and the nitrogen A laminated structure in which a conductive material containing the above is combined may also be used.

[0152] When an oxide semiconductor, which is a type of metal oxide, is used as the semiconductor layer, the gate electrode The conductive layer that functions as the conductive layer includes a material containing the metal element described above, a conductive material containing oxygen, and In this case, it is preferable to use a laminated structure in which the conductive material containing oxygen is It is preferable to provide the conductive material containing oxygen on the channel forming region side. By doing so, oxygen released from the conductive material is more easily supplied to the channel formation region.

[0153] In particular, the conductive layer that functions as the gate electrode is made of a metal oxide that is included in the metal oxide in which the channel is formed. It is preferable to use a conductive material containing the metal element and oxygen. Conductive materials containing elements such as titanium nitride and tantalum nitride may also be used. Any nitrogen-containing conductive material may be used. Indium tin oxide (ITO) is also suitable. Indium Tin Oxide, Indium Oxide with Tungsten Oxide, Tungsten Oxide Indium zinc oxide containing stainless steel, indium oxide containing titanium oxide, titanium oxide Including indium tin oxide, indium zinc oxide, silicon-doped indium tin oxide Alternatively, nitrogen-containing indium gallium zinc oxide may be used. By using such a material, hydrogen contained in the metal oxide in which the channel is formed can be captured. Alternatively, hydrogen that enters from the outer insulator may be captured. It may be possible.

[0154] The conductive material used for the contact plugs and the like is, for example, tungsten, poly A highly embeddable conductive material such as silicon may be used. The material is combined with a barrier layer (diffusion prevention layer) such as a titanium layer, titanium nitride layer, or tantalum nitride layer. They may also be used in combination.

[0155] [Semiconductor layer] The semiconductor layer may be a single crystal semiconductor, a polycrystalline semiconductor, a microcrystalline semiconductor, an amorphous semiconductor, or the like. The semiconductor materials may be, for example, silicon. Silicon, germanium, etc. can also be used. Compound semiconductors such as silicon, gallium arsenide, oxide semiconductors, nitride semiconductors, and organic semiconductors etc. can be used.

[0156] In addition, when an organic semiconductor is used as the semiconductor layer, low molecular weight organic materials with aromatic rings or π-electron Conjugated conductive polymers such as rubrene, tetracene, pentaerythritol, and the like can be used. tetracyanoquinodimethane, polythiophene, polyacetylene Polyparaphenylene vinylene, polyparaphenylene vinylene, etc. can be used.

[0157] In addition, semiconductor layers may be stacked. When semiconductor layers are stacked, each layer may have a different crystal state. Alternatively, different semiconductor materials may be used.

[0158] In addition, the band gap of oxide semiconductors, which are a type of metal oxide, is 2 eV or more. By using an oxide semiconductor for the conductor layer, a transistor with extremely low off-state current can be realized. Specifically, the voltage between the source and drain is 3.5V, and the temperature is room temperature (typically 25°C). ) and the off-current per 1 μm of channel width is 1×10 -20 Less than A, 1 x 10 - 22Less than A or 1 x 10 -24 A. That is, the on-off ratio In addition, a transistor using an oxide semiconductor for a semiconductor layer (OS transistor) has high dielectric strength between source and drain. Therefore, it has good reliability. Furthermore, a transistor with a large output voltage and high breakdown voltage can be provided. Furthermore, it is possible to provide a highly reliable memory device. A storage device may be provided.

[0159] Crystalline silicon transistors tend to have higher mobility than OS transistors. Crystalline Si transistors have the advantage of achieving extremely low off-state current, similar to OS transistors. Therefore, the semiconductor material used in the semiconductor layer should be selected appropriately depending on the purpose and application. For example, depending on the purpose and application, it is necessary to select between OS transistors and crystalline Si transistors. A transistor or the like may also be used in combination.

[0160] When an oxide semiconductor layer is used as the semiconductor layer, the oxide semiconductor layer is formed by a sputtering method. When the oxide semiconductor layer is formed by a sputtering method, the oxide semiconductor This is preferable because the density of the oxide semiconductor layer can be increased. In this case, the sputtering gas may be a rare gas (typically argon), oxygen, or a rare gas A mixed gas of argon and oxygen can be used. Also, the sputtering gas must be highly purified. For example, oxygen gas and rare gases used as sputtering gases have a dew point of -60°C or lower. Preferably, a gas highly purified to a temperature of -100°C or lower is used. By forming the oxide semiconductor layer using a ring gas, moisture and other substances can be incorporated into the oxide semiconductor layer. It can be prevented as much as possible.

[0161] In addition, when the oxide semiconductor layer is formed by a sputtering method, It is preferable to remove as much moisture as possible from the film formation chamber. For example, using a cryopump A suction-type vacuum pump was used to create a high vacuum (5×10 -7 Pa to 1 x 10 - 4 It is preferable to exhaust the gas to a pressure of about 100 Pa, especially when the sputtering device is in standby mode. The partial pressure of gas molecules equivalent to H2O (gas molecules equivalent to m / z = 18) in the deposition chamber is 1×10 -4 Pa or less, and 5×10 -5 It is more preferable to set the value to 0.05 Pa or less. I wish.

[0162] [Metal oxides] By changing the composition of elements contained in metal oxides, conductors, semiconductors, and insulators can be created. Metal oxides that have conductive properties are sometimes called "conductive oxides." Metal oxides with semiconductor properties are sometimes called "oxide semiconductors." A metal oxide having the above structure is sometimes called an "insulating oxide."

[0163] Oxide semiconductors, which are a type of metal oxide, often contain at least indium or zinc. It is particularly preferable that the material contains indium and zinc. It is preferable that aluminum, gallium, yttrium, or tin is contained. Boron, silicon, titanium, iron, nickel, germanium, zirconium, molybdenum lanthanum, cerium, neodymium, hafnium, tantalum, tungsten, or magnesium It may contain one or more elements selected from the group consisting of cadmium, cadmium, and cadmium-containing metals.

[0164] Here, a case where the oxide semiconductor contains indium, an element M, and zinc is considered. The element M is aluminum, gallium, yttrium, or tin. Applicable elements for element M include boron, silicon, titanium, iron, nickel, and germanium. , zirconium, molybdenum, lanthanum, cerium, neodymium, hafnium, tantalum, Tungsten, magnesium, etc. However, the element M can be a combination of multiple of the above elements. There are cases where it is okay to match them.

[0165] In this specification and the like, metal oxides containing nitrogen are also referred to as metal oxides. Nitrogen-containing metal oxides are also called metal oxynitrides (met). It may also be called hydroxybenzoxanthate (hydroxybenzoxanthate).

[0166] [Metal oxide structures] Oxide semiconductors (metal oxides) are divided into single-crystal oxide semiconductors and other non-single-crystal oxide semiconductors. Examples of non-single-crystal oxide semiconductors include CAAC-OS and polycrystalline Oxide semiconductor, nc-OS (nanocrystalline oxide semiconductor) conductor), pseudo-amorphous oxide semiconductor (a-like OS) s-like oxide semiconductor), and amorphous oxide semiconductor etc.

[0167] CAAC-OS has a c-axis orientation and multiple nanocrystals are connected in the ab-plane direction. The crystal structure has distortion. The distortion is the area where multiple nanocrystals are connected. In the region, the lattice arrangement is changed between a region with a uniform lattice arrangement and another region with a uniform lattice arrangement. Indicates the point where the direction is changing.

[0168] Nanocrystals are basically hexagonal, but they are not limited to regular hexagonal shapes and may be non-regular hexagonal. The distortion may also have lattice arrangements such as pentagons and heptagons. In CAAC-OS, clear grain boundaries (grain boundaries) are observed even near the strain. It is difficult to confirm the crystal structure due to the distortion of the lattice arrangement. This is because the CAAC-OS is aligned in the ab-plane direction. In this case, the arrangement of oxygen atoms is not dense, and the bond distance between atoms is reduced by the substitution of metal elements. This is because distortion can be tolerated by changing the

[0169] In addition, the CAAC-OS has a layer containing indium and oxygen (hereinafter referred to as an In layer) and an element A layered crystal structure in which layers containing M, zinc, and oxygen (hereinafter referred to as (M, Zn) layers) are stacked. It is noted that indium and element M tend to have a layered structure. It is possible, and when the element M in the (M,Zn) layer is replaced with indium, (In,M,Zn) Also, when indium in the In layer is replaced with element M, (In,M ) layer.

[0170] CAAC-OS is a metal oxide with high crystallinity. Since it is difficult to identify grain boundaries, the decrease in electron mobility caused by grain boundaries is unlikely to occur. In addition, the crystallinity of metal oxides can be reduced by the incorporation of impurities or the generation of defects. Therefore, CAAC-OS is a metal oxide with few impurities and defects (such as oxygen vacancies). Therefore, the physical properties of the metal oxide having the CAAC-OS are stable. Therefore, metal oxides having CAAC-OS are heat-resistant and highly reliable.

[0171] nc-OS is a material that can be used in microscopic areas (e.g., areas between 1 nm and 10 nm, especially areas between 1 nm and 3 nm). The nc-OS has periodic atomic arrangement in the nanometer range (nm or less). There is no regularity in the crystal orientation between the crystals. Therefore, no orientation is observed throughout the film. Therefore, depending on the analysis method, nc-OS may be distinguished from a-like OS or amorphous oxide semiconductor. It may be difficult to distinguish between the two.

[0172] In addition, In-G, a type of metal oxide containing indium, gallium, and zinc, α-Zn oxide (hereinafter referred to as IGZO) can take on a stable structure by forming it into the above-mentioned nanocrystals. In particular, IGZO tends to have difficulty growing crystals in the atmosphere, so it is difficult to grow large crystals. (Here, crystals of a few mm or a few cm) In some cases, it may be structurally more stable to form the crystals as a solid.

[0173] The a-like OS is a metal oxide semiconductor with a structure between the nc-OS and amorphous oxide semiconductor. A-like OS has voids or low density areas. e-OS has lower crystallinity than nc-OS and CAAC-OS.

[0174] Oxide semiconductors (metal oxides) have a variety of structures, each with different properties. The oxide semiconductor of one embodiment of the present invention is an amorphous oxide semiconductor, a polycrystalline oxide semiconductor, an a-lik The crystalline structure may have two or more of e-OS, nc-OS, and CAAC-OS.

[0175] [Transistors with metal oxides] Next, the case where the above metal oxide is used for a channel formation region of a transistor will be described. do.

[0176] By using the above metal oxide in the channel formation region of a transistor, a high field effect It is possible to realize a highly reliable transistor. It is possible.

[0177] It is also preferable to use a metal oxide with a low carrier density for the transistor. In the case of lowering the carrier density of the oxide, the impurity concentration in the metal oxide is lowered, In this specification and the like, the impurity concentration is low and the defect level density is low. For example, metal oxides are called high-purity intrinsic or substantially high-purity intrinsic. Rear density is 8x10 11 cm -3 Less than 1 x 10 11 cm -3 Less than or even better Preferably 1 x 10 10 cm -3 Less than 1 x 10 -9 cm -3 That's all there is to it.

[0178] Furthermore, highly pure intrinsic or substantially highly pure intrinsic metal oxides have a low density of defect states. Therefore, the trap level density may also be low.

[0179] In addition, the charges trapped in the trap levels of metal oxides take a long time to disappear. Therefore, gold, which has a high density of trap states, A transistor having a metal oxide in a channel formation region may have unstable electrical characteristics. do.

[0180] Therefore, in order to stabilize the electrical characteristics of the transistor, the impurity concentration in the metal oxide In order to reduce the impurity concentration in the metal oxide, it is effective to reduce the It is also preferable to reduce the impurity concentration in the film in contact with the film. Potassium metal, alkaline earth metal, iron, nickel, silicon, etc.

[0181] [impurities] Here, the influence of each impurity in the metal oxide will be described.

[0182] In addition, when alkali metals or alkaline earth metals are contained in metal oxides, defect levels are formed. Therefore, alkali metals or alkaline earth metals A transistor using a metal oxide containing fluorine in the channel formation region is a normally-on transistor. Therefore, the concentration of alkali metals or alkaline earth metals in the metal oxides It is preferable to reduce the alkalinity in the metal oxide obtained by SIMS. The concentration of alkaline earth metals or alkaline earth metals is 1×10 18 atoms / cm 3 The following is preferred: Kuha 2 x 10 16 atoms / cm 3 Do the following:

[0183] In addition, the hydrogen contained in the metal oxide reacts with the oxygen that bonds with the metal atom to form water, Oxygen vacancies may be formed in the channel formation region of the metal oxide. If the oxygen vacancy is large, the transistor tends to have normally-on characteristics. When hydrogen enters the metal, electrons, which act as carriers, are generated. It can bond with oxygen, which bonds with hydrogen atoms, to produce electrons, which are carriers. A transistor using a metal oxide containing such a metal oxide tends to have normally-on characteristics.

[0184] For this reason, it is preferable that the amount of hydrogen in the metal oxide is reduced as much as possible. In the metal oxide, the hydrogen concentration obtained by SIMS is 1×10 20 atoms / cm 3 Less than 1 x 10 19 atoms / cm 3 less than 5 × 10 18 atoms / cm 3 less than 1×10 18 atoms / cm 3 Less than and A metal oxide with sufficiently reduced impurities is used for the channel formation region of a transistor. This allows stable electrical properties to be imparted.

[0185] It is preferable to use a thin film with high crystallinity as the metal oxide used as the semiconductor of a transistor. The use of this thin film can improve the stability or reliability of a transistor. The thin film may be, for example, a thin film of a single crystal metal oxide or a thin film of a polycrystalline metal oxide. However, the thin film of a single crystal metal oxide or the thin film of a polycrystalline metal oxide may be used as the base. Forming it on a plate requires high temperature or laser heating processes. This increases the cost of the system and also reduces the throughput.

[0186] In 2009, an In-Ga-Zn oxide with a CAAC structure (called CAAC-IGZO) was developed. The discovery of the compound 'B' has been reported in Non-Patent Document 1 and Non-Patent Document 2. CAAC-IGZO has a c-axis orientation, the grain boundaries are not clearly visible, and it can be grown at low temperatures. It has been reported that it is possible to form a thin film on a substrate using CAAC-IGZO. The resulting transistors have been reported to have excellent electrical properties and reliability.

[0187] In 2013, an In-Ga-Zn oxide with an nc structure (called nc-IGZO) was developed. ) was discovered (see Non-Patent Document 3). Here, nc-IGZO is a microscopic region (for example, a region of 1 nm or more and 3 nm or less) It has been reported that there is no regularity in the crystal orientation between the domains.

[0188] Non-Patent Documents 4 and 5 describe the above CAAC-IGZO, nc-IGZO, and Average crystal size of IGZO thin films with low crystallinity and low crystallinity by electron beam irradiation In the case of a thin film of IGZO with low crystallinity, before the electron beam irradiation, Even in the case of IGZO, crystalline IGZO of about 1 nm has been observed. In this case, completely amorphous structure Furthermore, it has been reported that the presence of IGZO with low crystallinity could not be confirmed. Compared with thin films, CAAC-IGZO thin films and nc-IGZO thin films are more resistant to electron beam irradiation. Therefore, CAAC is a promising semiconductor for transistors. It is preferable to use a thin film of -IGZO or a thin film of nc-IGZO.

[0189] A transistor using a metal oxide has an extremely small leakage current in a non-conducting state. Specifically, the off-state current per 1 μm of transistor channel width is yA / μm (10 -24 It has been shown in Non-Patent Document 6 that the order of magnitude of the resistance is A / μm. Low-power CPUs have been developed that utilize the low leakage current characteristics of transistors. (See Non-Patent Document 7).

[0190] Furthermore, the transistor using metal oxide has a low leakage current characteristic. The application of transistors to display devices has been reported (see Non-Patent Document 8). The displayed image changes several dozen times per second. The refresh rate is also called the drive frequency. Such high-speed screen switching, which is difficult for the human eye to perceive, is the cause of eye fatigue. Therefore, the refresh rate of the display device is reduced to improve image clarity. It has been proposed to reduce the number of times the display is rewritten. This driving method can reduce the power consumption of the display device. This is called idling stop (IDS) drive.

[0191] The discovery of the CAAC structure and nc structure has led to the discovery of metal oxides with the CAAC structure or nc structure. Improvement of the electrical characteristics and reliability of transistors using the above method, and reduction of manufacturing process costs. This contributes to improving throughput. Research is currently underway into the application of this transistor to display devices and LSIs, taking advantage of its properties. There are.

[0192] [Film formation method] Insulating materials for forming insulating layers, conductive materials for forming conductive layers, or semiconductors The semiconductor material for forming the layer is deposited by sputtering, spin coating, CVD (Chemical Vapor Deposition) mical vapor deposition) method (thermal CVD method, MOCVD (Met al Organic Chemical Vapor Deposition) method, P ECVD (Plasma Enhanced CVD) method, High Density Plasma CVD (Hi gh density plasma CVD) method, LPCVD (low pressu re CVD) method, APCVD (atmospheric pressure CVD) method), ALD (Atomic Layer Deposition) method, or , MBE (Molecular Beam Epitaxy) method, or PLD (Pu Laser Deposition method, dip method, spray coating method, droplet Using the ejection method (inkjet method, etc.) and printing method (screen printing, offset printing, etc.) It can be formed by

[0193] The plasma CVD method can produce high-quality films at relatively low temperatures. When a film formation method that does not use plasma, such as a thermal CVD method, is used, damage to the surface to be formed is generated. For example, the wiring, electrodes, and elements (transistors, capacitors) included in the memory device Some elements (such as quantum elements) may become charged up by receiving charge from the plasma. At this time, the accumulated charge destroys the wiring, electrodes, elements, etc. contained in the memory device. On the other hand, in the case of a film formation method that does not use plasma, such plasma damage may occur. Since no defects occur, the yield of the memory device can be increased. Since no damage occurs, a film with few defects can be obtained.

[0194] In addition, the ALD method utilizes the self-regulating properties of atoms to deposit atoms one layer at a time. This allows for ultra-thin film deposition, film deposition on structures with high aspect ratios, and pinholes. It is possible to form films with few defects, excellent coating properties, and low temperature film formation. In addition, the ALD method uses plasma, which is called PEALD (Plasma E ALD). This includes the enhanced ALD method, which uses plasma to form films at lower temperatures. In addition, the precursors used in the ALD method do not contain impurities such as carbon. Therefore, films formed by the ALD method may be different from films formed by other film formation methods. The amount of impurities may be higher than that of the film that has been removed. , X-ray Photoelectron Spectroscopy (XPS) This can be done using oscopy.

[0195] The CVD and ALD methods are film formation methods in which particles emitted from a target are deposited. Unlike the conventional method, this is a film formation method in which a film is formed by a reaction on the surface of the object to be treated. This is a film forming method that is less affected by the shape of the workpiece and has good step coverage. The ALD method has excellent step coverage and thickness uniformity, making it suitable for the production of thin films with high aspect ratios. It is suitable for coating the surface of high openings. However, the ALD method has a relatively low film formation rate. Because the deposition rate is slow, it cannot be used in combination with other deposition methods such as CVD, which has a high deposition rate. In some cases this may be preferable.

[0196] In the CVD and ALD methods, the composition of the resulting film can be controlled by the flow rate ratio of the source gases. For example, in the CVD and ALD methods, the flow rate ratio of the source gases can be adjusted to any desired value. In addition, for example, in the CVD method and the ALD method, it is possible to form a film having a composition. By changing the flow rate ratio of the source gases while controlling the temperature, a film with a continuously changing composition can be formed. When forming a film while changing the flow rate ratio of the source gases, multiple film forming chambers can be used. Compared to forming a film by hand, the time required for film formation is shortened by the time required for transport and pressure adjustment. Therefore, the productivity of the storage device may be improved.

[0197] <Low Dielectric Constant Region (LDR)> [Configuration example] Next, a configuration example of the LDR 221 will be described with reference to FIGS. The arrows indicating the X, Y, and Z directions are also shown. The Z directions are directions that are perpendicular to each other.

[0198] FIG. 17A is a plan view of the same memory cell 211[i+1,j] as FIG. Figure 17(B) is a perspective schematic view of the part 350 shown in Figure 17(A). , insulating layer 315, insulating layer 331, insulating layer 319, and LDR 221 are shown.

[0199] As described above, the LDR 221 includes a plurality of LDSs 235. The LDSs 235 are formed on the insulating layer 3. 19 can be provided by selectively removing a portion of the LDS235. The length of the opening is "Length GL", the width of the opening of LDS235 is "Width GW", The height (depth) is "height GH".

[0200] The LDR 221 has a region extending in the Y direction and a region extending in the X direction. In (B), in the region extending in the Y direction of the LDR 221, the LDS 235 has a length GL The direction of length GL is aligned with the X direction. It is not necessary to completely match the LDS23 in the region extending in the Y direction of the LDR221. 5 is arranged so that the direction of the length GL intersects with the Y direction.

[0201] In FIG. 17B, in the region extending in the X direction of the LDR 221, the LDS 235 is arranged so that the direction of length GL coincides with the Y direction. However, the direction of length GL It is not necessary to completely match the Y direction. , LDS235 may be disposed so that the direction of the length GL intersects with the X direction.

[0202] As shown in FIGS. 18A and 18B, in the region extending in the Y direction of the LDR 221, In this case, the LDS235 is arranged so that the direction of the length GL coincides with or approximately coincides with the Y direction. In the region of the LDR 221 extending in the X direction, the LDS 235 may be formed to have a length GL. The direction may be aligned with or approximately aligned with the X direction. Fig. 18(B) is a top view of the part 351 shown in Fig. 18(A).

[0203] If the length GL is too long compared to the height GH and width GW of the LDS235, This may reduce the mechanical strength and reduce the reliability of the memory cell 211. This may reduce the reliability of the device 100. Specifically, The insulating layer 319 sandwiched between the adjacent LDS235 is easily damaged. The rank is also called "rib".

[0204] Therefore, as shown in Figs. 19(A) and 19(B), the LDS235 is set to a constant length G It is preferable to arrange them by dividing them into sections every L. Specifically, the length GL is 50 times or less the width GW. The length GL is preferably 20 times or less the height GH, and more preferably 30 times or less. 19A is a perspective view of the portion 350. The magnification is preferably 10 times or less, and more preferably 10 times or less. FIG. 19(B) is a top view of the part 352 shown in FIG. 19(A).

[0205] The part of the insulating layer sandwiched between adjacent LDS235 layers is also called the "rib." The height GH is It is preferably 20 times or less, more preferably 10 times or less, the width RW of the rib (see FIG. 22(B)). .

[0206] As shown in Figures 20(A) and 20(B), even if the direction of the length GL is changed every certain section, FIG. 20(A) is a perspective view of the part 350. FIG. 20(B) is a perspective view of the part 350. 20(A) and 20(B), the length is changed at regular intervals. The direction of GL is rotated by 90 degrees, but the angle of rotation for each fixed section is not limited to 90 degrees. .

[0207] Also, when the LDS235 is viewed from the Z direction, the shape of the LDS235 consists of only straight lines. For example, as shown in FIG. 21(A), the LDS235 does not have a bending portion. Alternatively, as shown in FIG. 21(B), the LDS 235 may have a curved portion. In the region of R221 extending in the Y direction, LDS235 extends in a direction intersecting the Y direction. It has an area where it exists.

[0208] [Example of manufacturing process] Next, an example of a manufacturing process for the LDR 221 will be described with reference to FIGS. In this embodiment, the manufacturing process from the formation of the insulating layer 331 to the formation of the insulating layer 343 will be described. 22 to 24 show the A1-A2 region and B1-B2 region shown by the dashed line in FIG. 10(A). 22 to 24 correspond to cross-sectional views of the conductive layer 3. Only the area crossing 38 is shown.

[0209] After forming the insulating layer 331 to cover the conductive layer 332, the insulating layer 319 is formed (FIG. 22(A)). In this embodiment, an aluminum oxide layer is formed as the insulating layer 331 by the ALD method. The insulating layer 331 may have a multi-layer structure. For example, it may be formed by depositing aluminum oxide by the ALD method. An aluminum oxide layer is formed on the aluminum oxide layer by a sputtering method. Alternatively, an aluminum oxide layer may be formed by sputtering. An aluminum oxide layer is formed on the aluminum oxide layer by the ALD method. A film-forming structure may also be used.

[0210] Next, an insulating layer to be the insulating layer 319 is formed on the insulating layer 331. A silicon oxynitride layer is formed by CVD as an insulating layer that will become the insulating layer 319. Heat treatment may be performed before forming the insulating layer that will become the insulating layer 319. The insulating layer 319 may be formed continuously without exposure to the air. By performing the treatment, moisture and hydrogen adsorbed on the surface of the insulating layer 331 are removed. As a result, the moisture concentration and hydrogen concentration in the insulating layer 331 and the insulating layer 319 can be reduced. Cut.

[0211] The heat treatment is carried out at a temperature of 250°C or higher and 650°C or lower, preferably 300°C or higher and 500°C or lower, and more preferably The heat treatment is preferably performed at a temperature of 320° C. or higher and 450° C. or lower. Inert gas atmosphere, or oxidizing gas is 10 ppm or more, 1% or more, or 10% The heat treatment may be carried out under reduced pressure. After heat treatment in a nitrogen or inert gas atmosphere, the oxygen removed is replaced with The treatment may be carried out in an atmosphere containing an oxidizing gas at 10 ppm or more, 1% or more, or 10% or more.

[0212] Next, the insulating layer 319 is subjected to CMP (Chemical Mechanical Polishing). As a result, an insulating layer 319 having a flat upper surface can be formed. .

[0213] Next, a portion of the insulating layer 319 is selectively removed using a lithography method, and the LDS235 (See FIG. 22(B)).

[0214] In the lithography method, first, the resist is exposed to light through a mask. The resist mask is formed by removing or leaving the exposed area using a developer. By etching through the resist mask, a conductor, a semiconductor, an insulator, etc. can be formed as desired. For example, KrF excimer laser light, ArF excimer laser light, The resist is removed using ultraviolet light, EUV (Extreme Ultraviolet) light, etc. A resist mask can be formed by exposing the substrate to light. A liquid immersion technique may be used, in which the substrate is exposed to light by filling the substrate with liquid (for example, water). Alternatively, an electron beam or an ion beam may be used. In this case, the mask is not required. The resist mask can be removed by ashing or other methods. Dry etching process, wet etching process, dry etching process followed by wet etching or by performing wet etching followed by dry etching. It can be done.

[0215] Moreover, instead of the resist mask, a hard mask made of an insulator or a conductor may be used. When a hard mask is used, an insulating film or a conductive film that is a hard mask material is formed on the insulating layer 319. A resist mask is formed thereon, and the hard mask material is etched to form a desired pattern. The etching of the insulating layer 319 can be performed by etching the resist. This may be done after removing the resist mask, or may be done while the resist mask is left in place. In some cases, the resist mask may disappear during etching. After etching, the hard mask may be removed by etching. If there is no effect on the subsequent process or if it can be used in the subsequent process, it is not necessary to remove the hard mask. There is no need to do so.

[0216] After forming a resist mask and / or hard mask, an insulating layer is formed by dry etching. An opening is formed in the insulating layer 319, reaching the insulating layer 331. The opening functions as the LDS 235. The openings may be formed by wet etching, but it is more preferable to use dry etching. The insulating layer 331 is preferably formed by etching the insulating layer 319. It is preferable to use a material that functions as an etching stopper when forming 35. For example, when silicon oxynitride is used for the insulating layer 319 forming the LDS 235, the insulating layer 331 may be made of silicon nitride, aluminum oxide, hafnium oxide, or the like.

[0217] The dry etching equipment used for etching is a capacitive coupling device with parallel plate electrodes. Capacitively Coupled Plasma (CCP) A capacitively coupled plasma etching device with parallel plate electrodes can be used. The measuring device may be configured to apply a high frequency voltage to one of the parallel plate electrodes. A configuration in which a plurality of different high frequency voltages are applied to one of the parallel plate electrodes may also be used. Alternatively, a high frequency voltage of the same frequency may be applied to each of the parallel plate electrodes. It is also possible to apply high frequency voltages of different frequencies to the row and plate electrodes. A dry etching apparatus having a high density plasma source can be used. The dry etching equipment includes, for example, an inductively coupled plasma (ICP) A Deeply Coupled Plasma etching device or the like can be used.

[0218] The width GW of LDS235 is preferably 3 nm or more and 20 nm or less, and more preferably 3 nm or more and 10 nm or less. If the width GW is too large, the insulating layer 334 to be formed next may enter the LDS 235. Therefore, if the width GW is too large, the LDS235 may become too small. do.

[0219] The width R of the insulating layer 319 sandwiched between the adjacent LDS 235, which corresponds to the "rib" described above, is W is preferably 0.5 to 5 times the width GW, and more preferably 0.5 to 3 times the width GW. It is preferable that the width RW is large. If W is too large, the effect of reducing the parasitic capacitance of the LDR221 will be weakened. If the width RW is too small, the parasitic capacitance of LDR221 will be reduced. The mechanical strength becomes weaker than necessary.

[0220] Subsequently, an insulating layer 334 is formed on the insulating layer 319 and the LDS 235. The formation of the film is carried out by a sputtering method or a CVD method under conditions that result in poor coverage. In particular, the sputtering method is preferable because it is easy to form a film under poor coating conditions. In the embodiment, a silicon nitride layer is formed by sputtering as the insulating layer 334 ( See Figure 23(A).

[0221] LDS 235 is a gap surrounded by insulating layers 331, 319, and 334. This allows the relative dielectric constant of LDS235 to be about 1. In addition, when the insulating layer 334 is formed under reduced pressure, LDS2 35 may be in a reduced pressure state. For example, the insulating layer 334 may be formed by sputtering. When forming a thin film, if a gas containing oxygen is used as the sputtering gas, LDS23 5 may contain oxygen. In this case, the LDS235 acts as an oxygen reservoir. It can be done.

[0222] The LDS 235 may be left as an air gap or may have a dielectric constant greater than that of the insulating layer 319. For example, the insulating layer 319 may be made of silicon oxide with a relative dielectric constant of 3.8. When the dielectric constant is 2.4, polyethylene and polyethylene with a dielectric constant of 2.1 are used in LDS235. Propylene may be filled in. By providing a structure to the LDS235, the LDR221 The mechanical strength of the film can be improved.

[0223] Subsequently, insulating layers 335 and 336 are formed on the insulating layer 334 (FIG. 23(B)). In this embodiment, a silicon oxynitride layer is formed as the insulating layer 335 by a CVD method. In addition, a silicon nitride layer is formed as the insulating layer 336 by the CVD method. A CMP process may be performed after the formation of the edge layer 335 or after the formation of the insulating layer 336 .

[0224] Next, insulating layer 336, insulating layer 335, insulating layer 334, insulating layer 319, and insulating layer 331 A part of the insulating layer 342 is removed to form an opening 342 reaching the conductive layer 332 (see FIG. 23(C)).

[0225] Next, a conductive layer is formed in the opening 342 and on the insulating layer 336 to form a contact plug 337. The conductive film is formed by plating, sputtering, CVD, MBE, This can be done by using a PLD method, an ALD method, or the like. Then, a tungsten layer is formed by sputtering. Then, the tungsten layer is formed by CMP. 3B, a portion of the conductive layer is removed to expose the insulating layer 336. As a result, the conductive layer is only present within the opening 342. The resulting film remains, forming a contact plug 337 (see FIG. 24(A)).

[0226] Next, a conductive layer 338 is formed over the insulating layer 336, and an insulating layer 343 is formed over the conductive layer 338. In this way, LDR221 can be formed.

[0227] <<Variation 1>> The LDR 221 may be provided on an insulating layer other than the insulating layer 319. Other examples of arrangement of the LDR 221 25 to 28. FIG. 25 shows the memory cells 211[i+1, 26 is a top view of the C1-C2 region indicated by the dashed line in FIG. 25 and the D1- This is a cross-sectional view of the D2 region.

[0228] In FIGS. 25 and 26, the LDR 221 is provided not only on the insulating layer 319 but also on the insulating layer 315. 25 and 26 show an example in which the LDR 221 provided on the insulating layer 315 is DR221a. Also, LDS235 included in LDR221a is shown as LDS23 5a. In addition, an insulating layer 344 and an insulating layer 345 are formed between the insulating layer 315 and the conductive layer 333. 5 is set.

[0229] The insulating layer 311 can be formed using the same material and method as the insulating layer 331. The insulating layer 315 can be formed using the same material and method as the insulating layer 319. The insulating layer 345 can be formed from the same material and by the same method as the insulating layer 334. It can be formed from the same materials and in the same manner as the edge layer 335 .

[0230] Therefore, LDS235a can be formed in the same manner as LDS235. In addition, the provision of LDR221a further reduces the parasitic capacitance between adjacent memory cells. can be reduced.

[0231] In addition, the conductive layer 261 (word line WWL[i+1]) and the conductive layer 333 (word line RWL[i By providing an LDR221a between the LDR221a and the LDR221b, the parasitic capacitance between the LDR221a and the LDR221b can be reduced. By providing the LDR 221a at the wiring intersection, the signal distortion is reduced, and the recording This can improve the reliability of the storage device and reduce the power consumption of the storage device. do.

[0232] <<Variation 2>> 27 is a top view of the memory cell 211[i+1,j]. FIG. 1 is a cross-sectional view of the E1-E2 region indicated by the chain line.

[0233] As shown in FIGS. 27 and 28, the LDR2 21 may be provided so as to cover the memory cell. 28 shows an example in which the LDR 221 is provided on the insulating layer 319 other than the side. Although the LDR 221 is not provided on the conductive layer 346 to which the tact plug 347 is electrically connected, The LDR 221 may be formed on the conductive layer 346 as long as it does not interfere with the contact plug 347. It is okay to set one up.

[0234] Although not shown, similar to the LDR 221 shown in FIGS. 27 and 28, the LDR 22 1a may be provided so as to overlap the memory cell. By widening the placement range, the parasitic capacitance between adjacent memory cells can be further reduced. In addition, the parasitic capacitance between conductive layers can be further reduced, reducing signal distortion. This reduces the power consumption of the storage device, thereby improving the reliability of the storage device. It is possible.

[0235] This embodiment mode can be implemented by appropriately combining with the configurations described in other embodiment modes. It is possible.

[0236] (Embodiment 3) In this embodiment, it can be used for the transistor M11 and the transistor M12. A structural example of a transistor will be described with reference to the drawings.

[0237] <Transistor structure example 1> An example of the structure of the transistor 200A will be described with reference to FIGS. 29(A), (B), and (C). FIG. 29(A) is a top view of the transistor 200A. FIG. 29(B) is a top view of the transistor 200A. 29(A) is a cross-sectional view of the L1-L2 region indicated by the dashed line. 29(A) is a cross-sectional view of the W1-W2 portion shown by the line. For clarity, some elements are omitted in the illustration.

[0238] 29(A), (B), and (C) show a transistor 200A and a layer functioning as an interlayer insulating layer. The insulating layer 309, insulating layer 316, insulating layer 322, insulating layer 324, insulating layer 354, Layer 380, insulating layer 374, and insulating layer 381 are also shown. A and a conductive layer 340 (conductive layer 340a, and conductive layer 340b). An insulating layer 341 (insulating layer 341a and insulating layer 341b) is provided in contact with the side surface of 40. do.

[0239] The interlayer insulating layer may be formed of silicon oxide, silicon oxynitride, silicon nitride oxide, or aluminum oxide. nium, hafnium oxide, tantalum oxide, zirconium oxide, lead zirconate titanate (P ZT), strontium titanate (SrTiO3) or barium strontium titanate Insulators such as (Ba,Sr)TiO3 can be used in single or multilayer configurations. or these insulators may contain, for example, aluminum oxide, bismuth oxide, germanium oxide, Niobium oxide, silicon oxide, titanium oxide, tungsten oxide, yttrium oxide, dioxide Alternatively, these insulators may be nitrided. Silicon oxide, silicon oxynitride or silicon nitride may be laminated on the body.

[0240] The transistor 200A includes a conductive layer 360 (conductive layer 360) that functions as a first gate electrode. a, and conductive layer 360b), conductive layer 305 serving as a second gate electrode, and an insulating layer 349 functioning as a first gate insulating layer and an insulating layer 348 functioning as a second gate insulating layer; layer 322 and insulating layer 324, and a semiconductor layer 260 (semiconductor) having a region where a channel is to be formed. Conductor layer 260a, semiconductor layer 260b, and semiconductor layer 260c) and source or drain A conductive layer 342a serving as one of the gates and a conductive layer 342b serving as the other of the source and drain It includes a conductive layer 342b and an insulating layer 354.

[0241] The conductive layer 305 is disposed so as to be embedded in the insulating layer 316, and the insulating layer 322 is disposed so as to be embedded in the insulating layer 322. 316 and conductive layer 305. Insulating layer 324 is disposed on insulating layer 322. In addition, the semiconductor layer 260 (semiconductor layer 260a, semiconductor layer 260b, and semiconductor The conductive layer 260c is disposed on the insulating layer 324. The insulating layer 349 is disposed on the semiconductor layer 260. The conductive layer 360 (conductive layer 360a and conductive layer 360b) is disposed on the insulating layer 34. It is located on the 9.

[0242] The conductive layer 342a and the conductive layer 342b are disposed in contact with a part of the upper surface of the semiconductor layer 260b. The insulating layer 354 covers a part of the upper surface of the insulating layer 324, the side surface of the semiconductor layer 260a, and the semiconductor layer 2 60b, a side surface of the conductive layer 342a, an upper surface of the conductive layer 342a, a side surface of the conductive layer 342b, and is disposed in contact with the upper surface of the conductive layer 342b.

[0243] The insulating layer 341 is formed on the side walls of the openings formed in the insulating layers 380, 374, and 381. The first conductor of the conductive layer 340 is provided in contact with the side surface of the first conductor. The second conductor of the conductive layer 340 is provided on the conductive layer 340. In the transistor 200A, the height of the upper surface of the insulating layer 381 can be made to be approximately the same. 3 shows a configuration in which a first conductor of a layer 340 and a second conductor of a conductive layer 340 are stacked. However, the present invention is not limited to this. For example, the conductive layer 340 may be a single layer or It may be configured as a laminated structure of three or more layers. Ordinal numbers may be assigned to indicate the order of appearance to distinguish them.

[0244] The semiconductor layer 260 includes a semiconductor layer 260a disposed on the insulating layer 324 and a semiconductor layer 260b. a semiconductor layer 260b disposed on the a, and a and a semiconductor layer 260c, part of which is in contact with the upper surface of the semiconductor layer 260b. By providing the semiconductor layer 260a below the semiconductor layer 260b, This can suppress the diffusion of impurities from the structure formed in the semiconductor layer 260b to the semiconductor layer 260b. Furthermore, by providing the semiconductor layer 260c on the semiconductor layer 260b, the semiconductor layer 260c It is possible to suppress the diffusion of impurities from the structure formed above into the semiconductor layer 260b. do.

[0245] The transistor 200A uses an oxide semiconductor, which is a type of metal oxide, for the semiconductor layer 260. It is preferable that

[0246] A transistor using an oxide semiconductor for a semiconductor layer in which a channel is formed has a Therefore, the leakage current (off-state current) is extremely small. In addition, since the oxide semiconductor can be formed by a sputtering method or the like, This makes it easier to realize a highly integrated semiconductor device.

[0247] For example, the semiconductor layer 260 may be an In-M-Zn oxide (wherein the element M is gallium, yttrium, or yttrium). Smoke, tin, copper, vanadium, beryllium, boron, titanium, iron, nickel, germanium , zirconium, molybdenum, lanthanum, cerium, neodymium, hafnium, tantalum, One or more metal oxides selected from tungsten, magnesium, etc. In particular, the element M may be gallium, yttrium, or tin. The semiconductor layer 260 may be formed of an In-M oxide, an In-Zn oxide, or an M-Zn oxide. It may be used.

[0248] In the transistor 200A, a first gate (also referred to as a top gate) electrode is formed on the The conductive layer 360 is formed in a self-aligned manner so as to fill the openings formed in the insulating layer 380, etc. By forming the conductive layer 360 in this manner, the conductive layer 342a and the conductive layer 3 42b, the conductive layer 360 can be reliably placed in the region between the conductive layer 360 and the substrate 42b without alignment. Cut.

[0249] The conductive layer 360 includes a conductive layer 360a and a conductive layer 360b disposed on the conductive layer 360a. For example, the conductive layer 360a has a bottom surface and a side surface of the conductive layer 360b. It is preferable that the conductive layer 3 is disposed so as to surround the surface. The top surface of 60 is approximately flush with the top surface of insulating layer 349 and the top surface of oxide 330c.

[0250] The conductive layer 305 may function as a second gate (also referred to as a bottom gate) electrode. In this case, the potential applied to the conductive layer 305 is linked to the potential applied to the conductive layer 360. By changing the threshold voltage (Vth) of the transistor 200A independently, the In particular, by applying a negative potential to the conductive layer 305, the transistor By increasing the Vth of the capacitor 200A above 0V, it is possible to reduce the off-state current. Therefore, when a negative potential is applied to the conductive layer 305, the conductive layer 360 This can reduce the drain current when the potential applied to is 0V.

[0251] In addition, for example, the conductive layer 305 and the conductive layer 360 are connected via the channel forming region of the semiconductor layer 260. By providing the conductive layer 305 and the conductive layer 360 so as to overlap each other, when a voltage is applied to the conductive layer 305 and the conductive layer 360, the conductive layer The electric field generated from the conductive layer 360 and the electric field generated from the conductive layer 305 are connected, and the semiconductor layer 2 The 60 channel forming regions can be covered.

[0252] That is, the electric field of the conductive layer 360 functioning as the first gate electrode and the electric field of the second gate electrode The electric field of the conductive layer 305, which functions as an electrode, electrically connects the channel forming region. In this specification and the like, the first gate electrode and the second gate electrode The structure of a transistor in which the channel formation region is electrically surrounded by the electric field of This is called a rounded channel (S-channel) structure.

[0253] The insulating layer 322 and the insulating layer 354 are formed of at least hydrogen (e.g., hydrogen atoms, hydrogen molecules, etc.). It is preferable that the insulating layer 322 and the insulating layer The edge layer 354 inhibits the diffusion of oxygen (e.g., at least one of oxygen atoms, oxygen molecules, etc.). For example, the insulating layer 322 and the insulating layer 354 each have the following functions: Therefore, the insulating layer 324 has a function of suppressing the diffusion of either or both of hydrogen and oxygen. The insulating layer 322 and the insulating layer 354 are preferably made of a material having a higher hydrogen content than the insulating layer 349. It is preferable that the insulating layer 32 has a function of suppressing the diffusion of one or both of silicon and oxygen. 2 and insulating layer 354, respectively, are more likely to contain one or both of hydrogen and oxygen than insulating layer 380. It is preferable that the catalyst has a function of suppressing the diffusion of the other component.

[0254] In this specification and the like, a film having a function of suppressing the diffusion of hydrogen or oxygen is referred to as a hydrogen film. Or a membrane that is difficult to permeate oxygen, a membrane that is low in permeability to hydrogen or oxygen, a membrane that is low in permeability to hydrogen or oxygen It may be called a film having barrier properties against hydrogen or oxygen. When the barrier film has conductivity, the barrier film may be called a conductive barrier film.

[0255] 29(B), the insulating layer 354 is formed between the conductive layer 342a and the conductive layer 342b. b and the side surfaces where the conductive layers 342a and 342b face each other. The side surfaces of the conductive layer 342a and the conductive layer 342b and the side surfaces of the semiconductor layer 260a and the semiconductor layer 260b It is preferable that the insulating layer 38 contacts the upper surface of the insulating layer 324 and a part of the upper surface of the insulating layer 324. 0 is formed by the insulating layer 354, insulating layer 324, semiconductor layer 260a, and semiconductor layer 260b. Therefore, impurities such as hydrogen contained in the insulating layer 380 are 324, it is possible to suppress contamination into the semiconductor layer 260a and the semiconductor layer 260b. do.

[0256] 29(B), the transistor 200A has an insulating layer 374 and a conductive layer 3 60, the insulating layer 349, and the semiconductor layer 260c. With such a structure, impurities such as hydrogen contained in the insulating layer 381 and the like can be absorbed by the insulating layer 381. Therefore, the electrical characteristics of the transistor can be improved. Furthermore, adverse effects on the reliability of the transistor can be suppressed.

[0257] With the above structure, a transistor with large on-state current can be provided. In this case, a transistor with a small off-state current can be provided. To provide a semiconductor device having stable electrical characteristics and improved reliability. This can be done.

[0258] <Transistor structure example 2> An example of the structure of the transistor 200B will be described with reference to FIGS. FIG. 30(A) is a top view of the transistor 200B. FIG. 30(B) is a top view of the transistor 200B. 30(C) is a cross-sectional view of the L1-L2 region indicated by the dashed line in FIG. 30(A) is a cross-sectional view of the W1-W2 portion shown by the line. For clarity, some elements are omitted in the illustration.

[0259] The transistor 200B is a modified example of the transistor 200A. To avoid this, differences from the transistor 200A will be mainly described.

[0260] The conductive layer 360 functioning as the first gate electrode is made up of a conductive layer 360a and a conductive layer 360b. The conductive layer 360a has a conductive layer 360b on the surface thereof. The conductive layer 360a is made of hydrogen atoms, hydrogen molecules, water molecules, copper atoms, and the like. It is preferable to use a conductive material that has the function of suppressing the diffusion of impurities such as electrons. has a function of suppressing the diffusion of oxygen (for example, at least one of oxygen atoms, oxygen molecules, etc.). It is preferable to use a conductive material that can

[0261] Since the conductive layer 360a has the function of suppressing the diffusion of oxygen, the material selection for the conductive layer 360b is easy. In other words, the presence of the conductive layer 360a allows the conductive layer 360b to be This suppresses oxidation of the material, thereby preventing a decrease in electrical conductivity.

[0262] In addition, the upper surface and side surfaces of the conductive layer 360, the side surfaces of the insulating layer 349, and the semiconductor layer 260c It is preferable to provide an insulating layer 354 so as to cover the side surface. When an insulating material is used that has the function of suppressing the diffusion of impurities such as hydrogen and oxygen, For example, it is preferable to use aluminum oxide or hafnium oxide. Other examples include magnesium oxide, gallium oxide, germanium oxide, and yttrium oxide. metals such as sodium, zirconium oxide, lanthanum oxide, neodymium oxide or tantalum oxide Oxide, silicon nitride oxide, silicon nitride, or the like can be used.

[0263] By providing the insulating layer 354, oxidation of the conductive layer 360 can be suppressed. By providing the layer 354, impurities such as water and hydrogen contained in the insulating layer 580 can be prevented from being generated in the transistor. This can prevent the light from diffusing to the station 200B.

[0264] The transistor 200B includes a conductive layer 360 in a portion of the conductive layer 342a and a portion of the conductive layer 342b. Since the parasitic capacitance of the transistor 200A is larger than that of the transistor 200A, the parasitic capacitance of the transistor 200A is larger than that of the transistor 200A. However, the operating frequency of the insulating layer 38 tends to be lower than that of the transistor 200A. 0, etc., and burying the conductive layer 360, insulating layer 349, etc. is not required. , and has higher productivity than the transistor 200A.

[0265] This embodiment mode can be implemented by appropriately combining with the configurations described in other embodiment modes. It is possible.

[0266] (Fourth embodiment) In this embodiment, a memory device or a semiconductor device according to one embodiment of the present invention can be applied to an electronic device. This section describes products and electronic devices.

[0267] The memory device or semiconductor device according to one embodiment of the present invention can be incorporated into various electronic devices. In particular, a semiconductor device according to one embodiment of the present invention can be used as a memory built into an electronic device. Examples of electronic devices include television sets, desktop Or notebook type personal computers, computer monitors, digital cameras, etc. Digital Signage, large-scale games such as pachinko machines In addition to electronic devices with relatively large screens such as smartphones, digital cameras, digital video cameras, etc. digital photo frames, mobile phones, portable game consoles, personal digital assistants, sound reproduction equipment Examples include placement, etc.

[0268] The electronic device according to one embodiment of the present invention may include an antenna. This allows the display of images, information, etc. on the display unit. If the device has a secondary battery, the antenna may be used for contactless power transmission.

[0269] The electronic device according to one embodiment of the present invention includes a sensor (force, displacement, position, velocity, acceleration, angular velocity, rotation speed, etc.). , distance, light, liquid, magnetic, temperature, chemical, sound, time, hardness, electric field, current, voltage, power, (including the ability to measure radiation, flow rate, humidity, gradient, vibration, odor or infrared radiation) It may be possible.

[0270] The electronic device according to one embodiment of the present invention can have various functions. Still images, videos, text images, etc.) on the display, touch panel function, calendar It has the functions of displaying the date, time, etc., and running various software (programs). functions, wireless communication functions, and functions to read programs or data recorded on recording media. They may have abilities, etc.

[0271] <Electronic components> An example of an electronic component incorporating the storage device 100 is shown in FIGS.

[0272] FIG. 31(A) shows an electronic component 700 and a substrate on which the electronic component 700 is mounted (mounting substrate 704 31(A) shows a perspective view of an electronic component 700. The electronic component 700 shown in FIG. 31(A) is an IC semiconductor device. The electronic component 700 is mounted on, for example, a printed circuit board 702. A plurality of such IC semiconductor devices are combined and each is electrically connected to a printed circuit board 702. By electrically connecting the components, the mounting substrate 704 is completed.

[0273] The electronic component 700 includes the memory device 100 shown in the above embodiment as a circuit unit. In FIG. 31(A), the package of the electronic component 700 is a QFP (Quad Flat Pack). However, the form of the package is not limited to this.

[0274] 31(B) shows a perspective view of the electronic component 730. The electronic component 730 is a SiP (System in Package) m in package) or MCM (Multi Chip Module) The electronic component 730 is an interposer mounted on a package substrate 732 (printed circuit board). An interposer 731 is provided, and a semiconductor device 735 and a plurality of memory devices are provided on the interposer 731. A station 100 is provided.

[0275] In the electronic component 730, the storage device 100 is configured as a high bandwidth memory (HBM). The semiconductor device 735 is used as a CP Integrated circuits such as U, GPU, and FPGA can be used.

[0276] The package substrate 732 is a ceramic substrate, a plastic substrate, or a glass epoxy substrate. The interposer 731 can be a silicon interposer, a resin interposer, or the like. An interposer or the like can be used.

[0277] The interposer 731 has a plurality of wirings and electrically connects a plurality of integrated circuits with different terminal pitches. The wiring can be provided in a single layer or multiple layers. The interposer 731 supports the integrated circuit provided on the interposer 731 to the package substrate 73. 2. The interposer 731 is sometimes called a "rewiring substrate" or "intermediate substrate." and a through electrode is provided in the package substrate 732, and the through electrode is used to electrically connect the integrated circuit and the package substrate 732. In addition, in silicon interposers, TSV (Transmission Through-Vessel) is used as a through electrode. Through Silicon Via can also be used.

[0278] It is preferable to use a silicon interposer as the interposer 731. Silicon Since an interposer does not require active elements, it can be manufactured at a lower cost than an integrated circuit. On the other hand, the wiring of the silicon interposer can be formed using the semiconductor process. This makes it easy to form fine wiring, which is difficult to do with resin interposers.

[0279] HBM requires many wires to achieve a wide memory bandwidth. Therefore, the interposer that implements HBM requires fine, high-density wiring. Therefore, a silicon interposer can be used for implementing HBM. preferable.

[0280] In addition, in SiP and MCM using silicon interposers, the integrated circuit and the interposer The reliability is less likely to be affected by differences in the expansion coefficient between the silicon interposer and the silicon interposer. The silicon interposer has a high level of surface flatness, making it easy to mount the integrated circuit on the silicon interposer and the silicon interposer. In particular, it is possible to mount multiple integrated circuits on an interposer in parallel. In a 2.5D package (2.5-dimensional mounting), a silicon interposer is used. It is preferable that

[0281] A heat sink (heat sink) may be provided on top of the electronic component 730. If provided, it is preferable to align the height of the integrated circuit provided on the interposer 731. For example, in the electronic component 730 shown in this embodiment, the memory device 100 and the semiconductor device 735 It is preferable to make the heights of the respective electrodes uniform.

[0282] In order to mount the electronic component 730 on another substrate, electrodes 733 are attached to the bottom of the package substrate 732. 31B shows an example in which the electrode 733 is formed using a solder ball. By providing solder balls in a matrix on the bottom of the package substrate 732, a BGA (Ba 11 Grid Array) mounting can be realized. Also, the electrodes 733 can be formed with conductive pins. Conductive pins may be provided in a matrix on the bottom of the package substrate 732. This allows for PGA (Pin Grid Array) implementation.

[0283] The electronic component 730 is not limited to BGA and PGA, and may be mounted on other substrates using various mounting methods. For example, SPGA (Staggered Pin Grid Arrangement) ay), LGA (Land Grid Array), QFP (Quad Flat P ackage), QFJ(Quad Flat J-leaded package), Or QFN (Quad Flat Non-leaded package) A packaging method can be used.

[0284] <Electronic equipment> Next, examples of electronic devices equipped with the above electronic components will be described with reference to FIGS. 32 and 35. cormorant.

[0285] The robot 7100 shown in FIG. 32 is equipped with an illumination sensor, a microphone, a camera, a speaker, a Displays, various sensors (infrared sensors, ultrasonic sensors, acceleration sensors, piezo sensors, The electronic component 730 is equipped with a processor, a sensor, a gyro sensor, etc., and a movement mechanism. For example, the electronic component 700 has a function to control these peripheral devices. It has the function of storing data acquired by the sensor.

[0286] The microphone has a function of detecting acoustic signals such as the user's voice and environmental sounds. The speaker also has the function of emitting audio signals such as voice and warning sounds. The 7100 analyzes the audio signal input through the microphone and outputs the necessary audio. The robot 7100 can emit audio signals from a speaker. , and a speaker can be used to communicate with the user.

[0287] The camera has a function of capturing images of the surroundings of the robot 7100. The robot 7100 has the function of moving using a moving mechanism. It can capture images, analyze them, and detect whether or not there are any obstacles when moving.

[0288] The flying object 7120 has a propeller, a camera, a battery, etc., and is an autonomous flying object. The electronic component 730 has the function of controlling these peripheral devices.

[0289] For example, image data captured by a camera is stored in the electronic component 700. It can analyze image data and detect the presence or absence of obstacles when moving. The remaining battery capacity is estimated from the change in the battery storage capacity by the electronic component 730. can be done.

[0290] The cleaning robot 7140 has a display on the top surface and multiple cameras on the sides. The cleaning robot has a brush, operation buttons, various sensors, etc. The 7140 is equipped with tires, a suction nozzle, etc. The cleaning robot 7140 is self-propelled. It can detect dust and suck it up through a suction port on the bottom.

[0291] For example, the electronic component 730 analyzes the image captured by the camera and detects obstacles such as walls, furniture, or steps. It can determine whether there are any obstacles. In addition, image analysis can be used to detect wires and other objects that are tangled in the brushes. If such an object is detected, the brush can stop rotating.

[0292] An automobile 7160 is shown as an example of a moving object. The automobile 7160 has an engine, tires, brakes, and For example, the electronic components 730 include navigation information, , based on data such as speed, engine condition, gear selection, and brake usage , and controls to optimize the driving state of the automobile 7160. For example, The image data is stored in electronic component 700 .

[0293] In the above description, an automobile is used as an example of a moving body. For example, the moving object may be a train, a monorail, a ship, or an aircraft (helicopter). , unmanned aerial vehicles (drones), airplanes, rockets, etc., and these movements Applying a computer according to one aspect of the present invention to the body gives it a system that utilizes artificial intelligence. It is possible.

[0294] The electronic component 700 and / or the electronic component 730 may be a TV device 7200 (television receiver). device), smartphone 7210, PC 7220 (personal computer), 7230 , can be incorporated into game console 7240, game console 7260, etc.

[0295] For example, the electronic component 730 built into the TV device 7200 functions as an image engine. For example, the electronic component 730 can perform functions such as noise reduction and resolution up-conversion. Which image processing is performed?

[0296] The smartphone 7210 is an example of a mobile information terminal. The electronic component 730 includes a microphone, a camera, a speaker, various sensors, and a display unit. These peripheral devices are controlled by

[0297] The PC7220 and PC7230 are examples of notebook PCs and desktop PCs, respectively. The keyboard 7232 and the monitor device 7233 are connected to the computer 7230 by wireless or wired means. It is possible to connect.

[0298] The game console 7240 is an example of a portable game console. The game console 7260 is a stationary game console for home use. The game console 7260 is an example of a game console. The game console 7260 includes a controller 7262, which can be connected wirelessly or via a wire. The controller 7262 is connected to the electronic component 700 and / or the electronic component 73. You can also include 0.

[0299] The semiconductor device of one embodiment of the present invention may be applied to a game machine that is not limited to the above. As a game machine using such a semiconductor device, for example, an amusement facility (game center, amusement park) Arcade game machines installed in stadiums, etc., and batting practice machines installed in sports facilities Examples include pitching machines.

[0300] The memory device or semiconductor device according to one embodiment of the present invention may be a memory card (e.g., an SD card), Various removable storage devices such as USB memory and SSD (Solid State Drive) Figure 33 shows some examples of the configuration of removable storage devices. The memory device or semiconductor device according to one embodiment of the present invention can be used in various storage devices, removable storage devices, and the like. It can be used for memory.

[0301] 33A is a schematic diagram of a USB memory. The USB memory 1100 includes a housing 1101, The device includes a cap 1102, a USB connector 1103, and a circuit board 1104. are housed in a housing 1101. For example, a substrate 1104 includes a memory chip 1105 , and a controller chip 1106 are attached. The memory device or semiconductor device of one embodiment of the present invention can be incorporated into a semiconductor device such as a semiconductor memory device.

[0302] Figure 33(B) is a schematic diagram of the external appearance of an SD card, and Figure 33(C) shows the internal structure of an SD card. The SD card 1110 includes a housing 1111, a connector 1112, and a board. The substrate 1113 is housed in a housing 1111. For example, the substrate 111 3 has a memory chip 1114 and a controller chip 1115 attached. By providing a memory chip 1114 on the back side of the board 1113, the capacity of the SD card 1110 can be increased. In addition, a wireless chip having a wireless communication function is provided on the substrate 1113. This allows the memory to be transmitted wirelessly between the host device and the SD card 1110. This allows data to be read from and written to the memory chip 1114. The semiconductor device described in the above embodiment can be incorporated into the chip 1114 or the like.

[0303] FIG. 33(D) is a schematic diagram of the external appearance of the SSD, and FIG. 33(E) is a schematic diagram of the internal structure of the SSD. The SSD 1150 includes a housing 1151, a connector 1152, and a board 1153. The board 1153 is housed in the housing 1151. For example, the board 1153 has a memory The chip 1154, memory chip 1155, and controller chip 1156 are installed. The memory chip 1155 is a working memory for the controller chip 1156. For example, a DOSRAM chip may be used. By providing 4, the capacity of the SSD 1150 can be increased. The semiconductor device described in the above embodiment can be incorporated into the chip 1154 or the like.

[0304] The alarm device 8100 shown in FIG. 34(A) is a residential fire alarm, and includes a detection unit and a semiconductor device. The semiconductor device 8101 includes the electronic component 700 and / or By using the electronic component 730, the alarm device 8100 can save power. Therefore, the reliability of the alarm device 8100 can be improved. can be done.

[0305] The air conditioner shown in FIG. 34(A) has an indoor unit 8200 and an outdoor unit 8204. The indoor unit 8200 includes a housing 8201, an air outlet 8202, a semiconductor device 8203, etc. In FIG. 34A, the semiconductor device 8203 is provided in an indoor unit 8200. However, the semiconductor device 8203 may be provided in the outdoor unit 8204. Even if the semiconductor device 8203 is provided in both the indoor unit 8200 and the outdoor unit 8204, The semiconductor device 8203 may use the electronic component 700 and / or the electronic component 730 described above. This allows the air conditioner to save energy. This allows for more reliable operation of the air conditioner.

[0306] An electric refrigerator-freezer 8300 shown in FIG. 34(A) includes a housing 8301, a refrigerator door 8302, a refrigerator 34(A) includes a freezing compartment door 8303, a semiconductor device 8304, and the like. The semiconductor device 8304 is provided inside the housing 8301. And / or by using the electronic component 730, the electric refrigerator-freezer 8300 can be made energy-efficient. In addition, stable operation can be achieved even in high temperature environments. It can improve the reliability of the 300.

[0307] In this embodiment, an electric refrigerator-freezer and an air conditioner are used as examples of electrical appliances. The semiconductor device of one embodiment of the present invention can be used in other electronic appliances. Other electrical appliances include vacuum cleaners, microwave ovens, electric ovens, and Rice cooker, water heater, induction cooker, water server, heating and cooling appliances (air conditioner) appliances), washing machines, dryers, and audiovisual equipment.

[0308] FIG. 34(B) shows an example of an electric vehicle. The electric vehicle 9700 has a secondary battery 9701. The power output of the secondary battery 9701 is adjusted by a control circuit 9702. The control circuit 9702 includes a semiconductor device (not shown) and a The control circuit 9702 and the processing unit 9704 are controlled by the processing unit 9704. By using the electronic components 700 and / or 730 described above, an electric vehicle 970 0 can save power. Also, stable operation can be achieved even in high temperature environments. The reliability of the electric vehicle 9700 can be improved.

[0309] The drive unit 9703 is a DC motor or an AC motor alone, or a motor and an internal combustion engine. The processing device 9704 is configured by combining the operation information of the driver of the electric vehicle 9700. Information (acceleration, deceleration, stopping, etc.) and driving information (uphill and downhill slopes, etc., Based on input information (load information, etc.), a control signal is output to the control circuit 9702. 9702 controls the power supplied from the secondary battery 9701 in response to a control signal from the processing unit 9704. The energy is adjusted to control the output of the drive unit 9703. If an AC motor is installed, In this case, although not shown, an inverter for converting direct current to alternating current is also built in.

[0310] The computer 5400 shown in Figure 35(A) is an example of a large-scale computer. A rack 5410 stores a plurality of rack-mounted computers 5420 .

[0311] The computer 5420 can have the configuration shown in the perspective view of FIG. In 5(B), a computer 5420 has a motherboard 5430, which includes: It has a plurality of slots 5431. A PC card 5421 is inserted into the slot 5431. are.

[0312] The PC card 5421 can have the configuration shown in the perspective view of FIG. 35(C), for example. The PC card 5421 shown in FIG. 35(C) is a processing card equipped with a CPU, a GPU, a storage device, etc. The PC card 5421 has a board 5422. 422 includes a connection terminal 5423, a connection terminal 5424, a connection terminal 5425, and a semiconductor device 54 26, a semiconductor device 5427, a semiconductor device 5428, and a connection terminal 5429. In addition, in FIG. 35(C), a semiconductor device 5426, a semiconductor device 5427, and a semiconductor device Although semiconductor devices other than device 5428 are shown in the figure, these semiconductor devices will be described below. The semiconductor device 5426, the semiconductor device 5427, and the semiconductor device 5428 are described below. Please take this into consideration.

[0313] The connection terminal 5429 has a shape that can be inserted into a slot 5431 of a motherboard 5430. The connection terminal 5429 connects the PC card 5421 to the motherboard 5430. The standard for the connection terminal 5429 is, for example, For example, PCIe is one example.

[0314] The connection terminals 5423, 5424, and 5425 are, for example, a PC card 542 1, and can be used as an interface for supplying power, inputting signals, etc. In addition, for example, the interface for outputting signals calculated by the PC card 5421 is The connection terminal 5423, the connection terminal 5424, and the connection terminal 54 The 25 standards include, for example, USB (Universal Serial Bus), SATA (Serial ATA), SCSI (Small Compute r System Interface). Also, connection terminal 5423, When outputting video signals from connection terminals 5424 and 5425, the respective standards are Examples of such standards include HDMI (registered trademark).

[0315] The semiconductor device 5426 has a terminal (not shown) for inputting and outputting signals. By inserting the terminal into a socket (not shown) provided on the board 5422, The device 5426 and the board 5422 can be electrically connected.

[0316] The semiconductor device 5427 has a plurality of terminals, and the terminals are connected to the wiring board 5422. For example, by performing reflow soldering on the wire, the semiconductor device 5427 and the board are connected. The semiconductor device 5427 can be, for example, FPGA (Field Programmable Gate Array), GPU, The semiconductor device 5427 can be an electronic component 730. Cut.

[0317] The semiconductor device 5428 has a plurality of terminals, and the terminals are connected to the wiring board 5422. The semiconductor device 5428 and the board are connected by, for example, reflow soldering the wires. The semiconductor device 5428 can be electrically connected to the board 5422. The electronic component 700 can be used as the semiconductor device 5428. can.

[0318] The computer 5400 can also function as a parallel computer. This makes it possible to perform the large-scale calculations required for, for example, artificial intelligence learning and inference. Cut.

[0319] By using the semiconductor device of one embodiment of the present invention in the various electronic devices, the size of the electronic devices can be reduced. This allows for smaller size, higher speed, and lower power consumption. This reduces the heat generated by the circuit itself, peripheral circuits, and This reduces the impact on the module, and also ensures stable operation even in high-temperature environments. Therefore, the reliability of the electronic device can be improved.

[0320] This embodiment mode can be implemented by appropriately combining with the configurations described in other embodiment modes. It is possible.

[0321] (Embodiment 5) The OS-LSI shown in the above embodiment can be applied to various storage devices. A storage device that can be replaced with an OS-LSI will be described with reference to FIGS.

[0322] Generally, memory is divided into working memory and long-term memory. It can be broadly divided into:

[0323] Working memory is a storage device that is directly read and written by a CPU or other computing device during processing. Therefore, working memory requires high operating speed and high rewrite durability. Depending on its purpose, working memory is classified into registers, cache, main memory, etc. In addition, SRAM is often used as the cache and DRAM as the main memory. stomach.

[0324] Storage is also called "external storage device" or "auxiliary storage device." It is connected to a computing device such as a CPU via an external bus. Although it is slower than working memory, it has a large storage capacity and is used for long-term data storage. Storage includes NOR flash memory, NAND flash memory (NAND flash, HDD, magnetic tape, etc. are used.

[0325] Figure 36 shows the operating speed and rewrite speed of registers, cache, main memory, and storage. The resistance levels are shown.

[0326] In recent years, ReRAM (Resistive Random Access Memory) has become a popular next-generation memory. ccess Memory), MRAM (Magnetoresistive Rand om Access Memory), PCM (Phase-Change Memory) y) are being considered.

[0327] For example, ReRAM has low rewrite endurance, making it difficult to apply it to working memory. The application of RAM to SRAM is also being researched, but it is easily affected by external magnetism and has poor high temperature resistance. Also, PCM requires a high voltage to write data, which can easily increase power consumption. water.

[0328] Figure 37 shows the data write time (time required to write data) and write speed for various storage devices. The storage device using OS-LSI has a short data writing time and high write tolerance. It also has high resistance to wear.

[0329] Figure 38 shows the data retention time and operating frequency of various storage devices after power supply is stopped. -LSI-based storage devices can retain data for more than a year even if the power supply is cut off. In addition, storage devices using OS-LSI have a high operating frequency and can achieve high-speed operation. .

[0330] The storage device using the OS-LSI shown in the above embodiment has a high operating speed and can be used for a long period of time. It is possible to retain data for a long period of time even at high temperatures, and consumes little power. Therefore, a storage device using an OS-LSI can be used as both a working memory and a storage device. By using OS-LSI, it is possible to realize universal memory. It can be realized.

[0331] This embodiment mode can be implemented by appropriately combining with the configurations described in other embodiment modes. It is possible. [Explanation of symbols]

[0332] 100: memory device, 111: peripheral circuit, 121: row decoder, 122: word line driver 130: bit line driver circuit; 131: column decoder; 132: precharger 133: Amplification circuit; 134: Input / output circuit; 140: Output circuit; 160: Control circuit cell logic circuit, 201: cell array, 211: memory cell

Claims

1. a memory cell having a first transistor and a second transistor; a first insulating layer having a region overlying the first transistor and a region overlying the second transistor; a second insulating layer having a region located on the first insulating layer; a gate of the first transistor electrically connected to a first word line; one of the source and the drain of the first transistor is electrically connected to the gate of the second transistor; the other of the source and the drain of the first transistor is electrically connected to a first bit line; one of the source and the drain of the second transistor is electrically connected to a second word line; the other of the source and the drain of the second transistor is electrically connected to a second bit line; a first conductive layer having a region that functions as a first word line; a second conductive layer having a region that functions as a first bit line; a third conductive layer having a region that functions as a second word line; a fourth conductive layer having a region that functions as a second bit line; the second insulating layer has a plurality of voids; the second conductive layer and the fourth conductive layer each have a region extending in a first direction; the first conductive layer and the third conductive layer each have a region extending in a second direction; At least one of the plurality of voids has a region extending in a direction intersecting the first direction, and has an overlap with at least one of the first conductive layer and the third conductive layer in the region; The fourth conductive layer has a region that overlaps with at least one of the plurality of voids.

2. In claim 1, the first conductive layer is located below at least one of the plurality of voids; the third conductive layer is located below at least one of the plurality of voids; The fourth conductive layer is located above at least one of the plurality of voids.

3. In claim 1 or 2, In a region overlapping with the fourth conductive layer, each of the plurality of voids extends in a direction intersecting the second direction.

4. In any one of claims 1 to 3, a third insulating layer above the first conductive layer and below the third conductive layer; The third insulating layer has a plurality of voids.

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