Semiconductor device and manufacturing method for semiconductor device

Abstract

To provide a manufacturing method for reducing the parasitic capacitance of a semiconductor device.SOLUTION: A semiconductor device includes: a first transistor 110 disposed in a first layer 100 and including a first channel member 120, a source member 150, and a drain member 160, in which the source member is connected to the channel member at one end of the channel member and the drain member is connected to the channel member at the other end of the channel member; and a second transistor 210 disposed in a second layer 200 over the first layer and including a second channel member 220, a source member 250, and a drain member 260, in which the source member is connected to the second channel member at one end of the second channel member, the drain member is connected to the second channel member at the other end of the second channel member, and in a plan view of the semiconductor device, the first channel member and the second channel member are disposed so as to partially overlap with each other in a second direction y that is perpendicular to a first direction x.SELECTED DRAWING: Figure 2A

Description

[Technical Field]

[0001] SUMMARY Exemplary embodiments of the present disclosure relate to semiconductor devices and methods for manufacturing semiconductor devices. [Background technology]

[0002] Patent Document 1 discloses a method for manufacturing a 3D semiconductor device. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] Special Publication No. 2022-543413 Summary of the Invention [Problem to be solved by the invention]

[0004] The present disclosure provides techniques that can reduce parasitic capacitance in semiconductor devices. [Means for solving the problem]

[0005] In one exemplary embodiment of the present disclosure, there is provided a semiconductor device including: a first transistor disposed on a first layer, the first transistor including a first channel, a first source, and a first drain, the first channel including one end and the other end in a first direction, the first source being connected to the first channel at one end of the first channel, and the first drain being connected to the first channel at the other end of the first channel; and a second transistor disposed on a second layer above the first layer, the second transistor including a second channel, a second source, and a second drain, the second channel including one end and the other end in the first direction, the second source being connected to the second channel at one end of the second channel, and the second drain being connected to the second channel at the other end of the second channel, and the first channel and the second channel being arranged to partially overlap in a second direction perpendicular to the first direction in a plan view of the semiconductor device. [Effects of the Invention]

[0006] According to one exemplary embodiment of the present disclosure, a technique capable of reducing parasitic capacitance in a semiconductor device can be provided. [Brief explanation of the drawings]

[0007] [Figure 1] FIG. 1 is a diagram schematically showing a planar layout of a portion of a semiconductor device 1 according to an embodiment of the present disclosure. [Figure 2A] 1 is a diagram showing an example of a cross-sectional structure of a semiconductor device 1. FIG. [Figure 2B] 1 is a diagram showing an example of a cross-sectional structure of a semiconductor device 1. FIG. [Figure 2C] 1 is a diagram showing an example of a cross-sectional structure of a semiconductor device 1. FIG. [Figure 3] 3 is a flowchart showing an example of a method for manufacturing the semiconductor device 1. [Figure 4A] FIG. 2 is a diagram showing an example of a cross-sectional structure of a part of the substrate 20 after step ST1 has been performed. [Figure 4B]FIG. 2 is a diagram showing an example of a cross-sectional structure of a part of the substrate 20 after step ST1 has been performed. [Figure 4C] FIG. 2 is a diagram showing an example of a cross-sectional structure of a part of the substrate 20 after step ST1 has been performed. [Figure 5] FIG. 10 is a diagram showing an example of a cross-sectional structure of a part of the substrate 10 after step ST2 has been performed. [Figure 6A] 10 is a diagram showing an example of a cross-sectional structure of a portion of the substrate 10 and the substrate 20 after step ST3 has been performed. FIG. [Figure 6B] 10 is a diagram showing an example of a cross-sectional structure of a portion of the substrate 10 and the substrate 20 after step ST3 has been performed. FIG. [Figure 6C] 10 is a diagram showing an example of a cross-sectional structure of a portion of the substrate 10 and the substrate 20 after step ST3 has been performed. FIG. [Figure 7A] FIG. 10 is a diagram showing an example of a cross-sectional structure of a part of the substrate 20 in step ST4. [Figure 7B] FIG. 10 is a diagram showing an example of a cross-sectional structure of a part of the substrate 20 in step ST4. [Figure 7C] FIG. 10 is a diagram showing an example of a cross-sectional structure of a part of the substrate 20 in step ST4. [Figure 8A] FIG. 10 is a diagram showing an example of a cross-sectional structure of a part of the substrate 20 in step ST4. [Figure 8B] FIG. 10 is a diagram showing an example of a cross-sectional structure of a part of the substrate 20 in step ST4. [Figure 8C] FIG. 10 is a diagram showing an example of a cross-sectional structure of a part of the substrate 20 in step ST4. [Figure 9A] FIG. 10 is a diagram showing an example of a cross-sectional structure of a part of the substrate 20 in step ST4. [Figure 9B] FIG. 10 is a diagram showing an example of a cross-sectional structure of a part of the substrate 20 in step ST4. [Figure 9C] FIG. 10 is a diagram showing an example of a cross-sectional structure of a part of the substrate 20 in step ST4. [Figure 10A] FIG. 10 is a diagram showing an example of a cross-sectional structure of a part of the substrate 20 in step ST4. [Figure 10B] FIG. 10 is a diagram showing an example of a cross-sectional structure of a part of the substrate 20 in step ST4. [Figure 10C]FIG. 10 is a diagram showing an example of a cross-sectional structure of a part of the substrate 20 in step ST4. [Figure 11A] FIG. 10 is a diagram showing an example of a cross-sectional structure of a part of the substrate 20 in step ST4. [Figure 11B] FIG. 10 is a diagram showing an example of a cross-sectional structure of a part of the substrate 20 in step ST4. [Figure 11C] FIG. 10 is a diagram showing an example of a cross-sectional structure of a part of the substrate 20 in step ST4. [Figure 12A] FIG. 10 is a diagram showing an example of a cross-sectional structure of a part of the substrate 20 in step ST4. [Figure 12B] FIG. 10 is a diagram showing an example of a cross-sectional structure of a part of the substrate 20 in step ST4. [Figure 12C] FIG. 10 is a diagram showing an example of a cross-sectional structure of a part of the substrate 20 in step ST4. [Figure 13A] FIG. 10 is a diagram showing an example of a cross-sectional structure of a part of the substrate 20 in step ST4. [Figure 13B] FIG. 10 is a diagram showing an example of a cross-sectional structure of a part of the substrate 20 in step ST4. [Figure 13C] FIG. 10 is a diagram showing an example of a cross-sectional structure of a part of the substrate 20 in step ST4. [Figure 14A] FIG. 10 is a diagram showing an example of a cross-sectional structure of a part of the substrate 20 in step ST4. [Figure 14B] FIG. 10 is a diagram showing an example of a cross-sectional structure of a part of the substrate 20 in step ST4. [Figure 14C] FIG. 10 is a diagram showing an example of a cross-sectional structure of a part of the substrate 20 in step ST4. [Figure 15A] FIG. 10 is a diagram showing an example of a cross-sectional structure of a part of the substrate 20 after step ST5 has been performed. [Figure 15B] FIG. 10 is a diagram showing an example of a cross-sectional structure of a part of the substrate 20 after step ST5 has been performed. [Figure 15C] FIG. 10 is a diagram showing an example of a cross-sectional structure of a part of the substrate 20 after step ST5 has been performed. [Figure 16A] FIG. 10 is a diagram showing an example of a cross-sectional structure of a part of the substrate 30 after step ST6 has been performed. [Figure 16B] FIG. 10 is a diagram showing an example of a cross-sectional structure of a part of the substrate 30 after step ST6 has been performed. [Figure 16C] FIG. 10 is a diagram showing an example of a cross-sectional structure of a part of the substrate 30 after step ST6 has been performed. [Figure 17A] FIG. 10 is a diagram showing an example of a cross-sectional structure of a part of the substrate 30 after step ST7 has been performed. [Figure 17B] FIG. 10 is a diagram showing an example of a cross-sectional structure of a part of the substrate 30 after step ST7 has been performed. [Figure 17C] FIG. 10 is a diagram showing an example of a cross-sectional structure of a part of the substrate 30 after step ST7 has been performed. DETAILED DESCRIPTION OF THE INVENTION

[0008] Hereinafter, each embodiment of the present disclosure will be described.

[0009] In one exemplary embodiment, a semiconductor device is provided, comprising: a first transistor disposed on a first layer, the first transistor including a first channel, a first source, and a first drain, the first channel having one end and the other end in a first direction, the first source connected to the first channel at one end of the first channel, and the first drain connected to the first channel at the other end of the first channel; and a second transistor disposed on a second layer above the first layer, the second transistor including a second channel, a second source, and a second drain, the second channel having one end and the other end in the first direction, the second source connected to the second channel at one end of the second channel, and the second drain connected to the second channel at the other end of the second channel, the first channel and the second channel being arranged to overlap in a second direction perpendicular to the first direction in a plan view of the semiconductor device.

[0010] In one exemplary embodiment, the first transistor includes a first dielectric film arranged around a first channel and a first gate electrode arranged around the first dielectric film, and the second transistor includes a second dielectric film arranged around a second channel and a second gate electrode arranged around the second dielectric film, the second gate electrode having a portion that does not overlap with the first gate electrode in a planar view of the semiconductor device.

[0011] In one exemplary embodiment, a semiconductor device includes a first wiring disposed below a first layer, a dielectric layer disposed between the first layer and a second layer, and a first plug electrically connecting the first wiring and a second gate electrode, the first plug being disposed through the dielectric layer in a portion where the second gate electrode does not overlap with the first gate electrode, and electrically connecting the first wiring and the second gate electrode.

[0012] In one exemplary embodiment, the first transistor includes a plurality of first channels, the plurality of first channels being arranged to overlap in a plan view of the semiconductor device, the first source being connected to the plurality of first channels, and the first drain being connected to the plurality of first channels.

[0013] In one exemplary embodiment, a method for manufacturing a semiconductor device is provided. A method for manufacturing a semiconductor device includes the steps of: forming a first transistor disposed in a first layer, the first transistor including a first channel, a first source, and a first drain, the first channel having one end and the other end in a first direction, the first source being connected to the first channel at one end of the first channel, and the first drain being connected to the first channel at the other end of the first channel; and forming a second transistor in a second layer above the first layer, the second transistor including a second channel, a second source, and a second drain, the second channel having one end and the other end in the first direction, the second source being connected to the second channel at one end of the second channel, and the second drain being connected to the second channel at the other end of the second channel, and the first channel and the second channel being arranged to overlap partially in a second direction perpendicular to the first direction in a plan view of the semiconductor device.

[0014] Hereinafter, each embodiment of the present disclosure will be described in detail with reference to the drawings. Note that identical or similar elements in each drawing are denoted by the same reference numerals, and redundant explanations will be omitted. Unless otherwise specified, positional relationships such as up, down, left, and right will be described based on the positional relationships shown in the drawings. The dimensional ratios in the drawings do not represent actual ratios, and the actual ratios are not limited to the illustrated ratios. Furthermore, in this disclosure, arranging or forming component A "above" or "below" component B may include both arranging or forming component A above or below component B in contact with component B, and arranging or forming component A above or below component B via component C.

[0015] Fig. 1 is a diagram schematically illustrating a planar layout of a portion of a semiconductor device 1 according to an embodiment of the present disclosure. The semiconductor device 1 illustrated in Fig. 1 includes a first channel region CR1, a second channel region CR2, a source / drain region SDR, and a gate region GR, and Fig. 1 illustrates an example of the positional relationship of the first channel region CR1, the second channel region CR2, the source / drain region SDR, and the gate region GR in the xy plane illustrated in Fig. 1. In the present disclosure, viewing the semiconductor device 1 in the z direction illustrated in Fig. 1 is also referred to as a "planar view."

[0016] The first channel region CR1 is a region in which a plurality of channel members 120, which will be described later, are arranged. In the semiconductor device 1, the plurality of channel members 120 are arranged in the first channel region CR1 such that their longitudinal direction is aligned with the x direction shown in FIG. 1 and their width direction is aligned with the y direction shown in FIG. 1. That is, the plurality of channel members 120 are arranged in each of the first channel regions CR1 such that their longitudinal direction is aligned with the x direction. The x direction is an example of a first direction, and the y direction is an example of a second direction.

[0017] The second channel region CR2 is a region where a plurality of channel members 120, which will be described later, are arranged. In the semiconductor device 1, the plurality of channel members 120 are arranged in the second channel region CR2 such that their longitudinal directions are aligned with the x direction shown in Fig. 1 and their width directions are aligned with the y direction shown in Fig. 1. That is, the plurality of channel members 120 are arranged in each of the second channel regions CR2 such that their longitudinal directions are aligned with the x direction.

[0018] The first channel region CR1 and the second channel region CR2 are arranged so that they partially overlap each other in the y direction. In FIG. 1, the region where the first channel region CR1 and the second channel region CR2 overlap is indicated by an overlap region OR. That is, in the semiconductor device 1, the channel members 120 and 120 are arranged so that they partially overlap each other in the y direction.

[0019] The source / drain regions SDR are regions in which source members 150, source members 250, drain members 160, and drain members 260, which will be described later, are arranged. In the semiconductor device 1, these sources and / or drains are arranged in the source / drain regions SDR so that their longitudinal direction is along the y direction shown in FIG. 1 and their width direction is along the x direction shown in FIG. 1. That is, in each of the source / drain regions SDR, these sources and / or drains are arranged so that their longitudinal direction is aligned along the y direction. Note that in the source / drain regions SDR, the source member 150 or the drain member 160 may be arranged so as to partially overlap with the source member 250 or the drain member 260 in the y direction.

[0020] The gate region GR is a region in which the gate electrodes 130 and 230 described below are arranged. In the semiconductor device 1, the gate electrodes 130 and 230 are arranged in the gate region GR so that their longitudinal directions are aligned with the y direction shown in FIG. 1 and their width directions are aligned with the x direction shown in FIG. 1. That is, the gate electrodes 130 and 230 are arranged in each of the gate regions GR so that their longitudinal directions are aligned with the y direction. Note that the gate electrodes 130 and 230 may be arranged so that they partially overlap in the y direction.

[0021] In the semiconductor device 1, the first transistor 110 and the second transistor 210 may be arranged at the intersections of the first channel region CR1 and the second channel region CR2 and the gate region GR. That is, in the semiconductor device 1 illustrated in FIG. 1, the first transistor 110 and the second transistor 210 are arranged in an array on the xy plane.

[0022] 2A to 2C are diagrams showing an example of the cross-sectional structure of the semiconductor device 1. Fig. 2A shows the XX' cross section in Fig. 1. Fig. 2B shows the Y1-Y1' cross section in Fig. 1. Fig. 2C shows the Y2-Y2' cross section in Fig. 1.

[0023] 2A to 2C, the semiconductor device 1 includes a substrate 30, a first layer 100, a second layer 200, and a dielectric layer 300. The first layer 100 is disposed above the substrate 30. The dielectric layer 300 is disposed above the first layer 100. The second layer 200 is disposed above the dielectric layer 300.

[0024] The first layer 100 includes a first transistor 110, wiring 170, wiring 180, and a dielectric film 190. The first layer 100 may also include a transistor layer in which the first transistor 110 is disposed, and a wiring layer in which the wiring 170 and wiring 180 are disposed. In the drawings of the present disclosure, the dielectric film 190 is illustrated as a single layer for the sake of convenience, but may actually include multiple dielectric layers depending on the manufacturing process of the first layer 100.

[0025] The first transistor 110 includes a plurality of channel members 120, a gate electrode 130, a gate dielectric film 140, a source member 150, and a drain member 160. As an example, the first transistor 110 may be a complementary field effect transistor (CFET).

[0026] The multiple channel members 120 are arranged so as to be stacked in the z direction. In the first transistor 110, three or more channel members 120 may be stacked. The channel members 120 are arranged so as to overlap one another in a plan view of the semiconductor device 1. Furthermore, the channel members 120 may be arranged at predetermined intervals in the x direction and the y direction, with multiple stacked channel members 120 acting as one unit. In the example shown in FIGS. 2A to 2C, three stacked channel members 120 are arranged in the x direction and two in the y direction as part of the semiconductor device 1.

[0027] Each of the channel members 120 has one end and the other end in the x direction. One end of each channel member 120 is connected to a source member 150. The other end of each channel member 120 is connected to a drain member 160. Note that multiple stacked channel members 120 may be connected to one source member 150 and one drain member 160.

[0028] The channel member 120 has a function of electrically connecting the source member 150 and the drain member 160. That is, a channel is formed inside the channel member 120 in response to a voltage applied to the gate electrode 130. Then, the source member 150 can be electrically connected to the drain member 160 via the channel.

[0029] The channel member 120 may be formed of a semiconductor material. As an example, the semiconductor material may be single-crystal silicon. The channel member 120 may be formed of an n-type or p-type semiconductor material. When the stacked channel members 120 are formed of single-crystal silicon, one channel member 120 and the other channel members 120 may have the same crystal orientation or different crystal orientations. As an example, the crystal orientation may be the (100) plane, the (110) plane, and / or the (111) plane. The same may be true for the channel member 220. The channel member 120 may be formed of a semiconductor material having a polarity different from that of the channel member 220. As an example, the channel member 120 may be formed of a p-type semiconductor material, while the channel member 220 may be formed of an n-type semiconductor material.

[0030] The source member 150 may be configured to include two surfaces that face each other in the x-direction, and the source member 150 is connected to the channel member 120 at one of the two surfaces, and is connected to the other channel member 120 at the other surface.

[0031] The source member 150 may be formed of a semiconductor material. For example, the semiconductor material may be single-crystal silicon. The source member 150 may be formed of a semiconductor material having a polarity different from that of the semiconductor material forming the channel member 120. For example, when the channel member 120 is formed of a semiconductor material having a p-type, the source member 150 may be formed of a semiconductor material having an n-type.

[0032] The drain member 160 may be configured to include two surfaces opposing each other in the x direction. The drain member 160 is connected to the channel member 120 at one of the two surfaces. The drain member 160 is connected to the other channel member 120 at the other surface. The source member 150 and the drain member 160 may be arranged to overlap each other when the semiconductor device 1 is viewed in the x direction (when viewed from right to left in FIG. 2A ).

[0033] A source electrode 152 is formed on the source member 150. At least a portion of the source electrode 152 may be disposed to be located below the source member 150 in the z direction. That is, the source electrode 152 may be disposed between the source member 150 and the plug 172 in the z direction and electrically connect the source member 150 and the plug 172.

[0034] A drain electrode 162 is formed on the drain member 160. At least a portion of the drain electrode 162 may be disposed so as to be located lower than the drain member 160 in the z direction. That is, the drain electrode 162 may be disposed between the drain member 160 and the plug 172 in the z direction and electrically connect the drain member 160 and the plug 172. Note that the plug 172 connected to the drain electrode 162 is not shown in FIGS. 2A and 2B.

[0035] The source electrode 152 and the drain electrode 162 may be formed of a conductive material. The conductive material may be a metal. The source electrode 152 may form an alloy with the source member 150 at a connection surface with the source member 150. The drain electrode 162 may form an alloy with the drain member 160 at a connection surface with the drain member 160. The alloy may be a silicide.

[0036] The wiring layer included in the first layer 100 is configured to include wiring 170, plugs 172, wiring 180, and plugs 182. The wiring 170, plugs 172, wiring 180, and plugs 182 can be arranged in any layout when viewed in a plan view of the semiconductor device 1. Furthermore, the number of wirings stacked in the z direction in the wiring layer can be set arbitrarily.

[0037] The wiring 170 is disposed so as to be located below the first transistor 110. The plug 172 electrically connects the first transistor 110 and the wiring 170. Specifically, the plug 172 includes one end connected to the first transistor 110 and the other end connected to the wiring 170. As shown in FIG. 2C , the plug 172 can be disposed so as to electrically connect the gate electrode 130 and the wiring 170. As shown in FIG. 2B , the plug 172 can be disposed so as to electrically connect the second transistor 210 disposed in the second layer 200 and the wiring 170.

[0038] The wiring 180 is disposed so as to be located below the wiring 170. The plug 182 electrically connects the wiring 170 and the wiring 180. Specifically, the plug 182 has one end and the other end, and the one end is connected to the wiring 170 and the other end is connected to the wiring 180. Note that the one end of the plug 182 may be connected to the first transistor 110 and / or the second transistor 210.

[0039] The second layer 200 includes a second transistor 210, wiring 270, wiring 280, and a dielectric film 290. Each component included in the second layer 200 may have the same configuration and / or function as the corresponding component in the first layer 100. Below, the components included in the second layer 200 and their functions will be described, focusing on the differences from the corresponding components in the first layer 100.

[0040] The second transistor 210 includes a plurality of channel members 220, a gate electrode 230, a gate dielectric layer 240, a source member 250, and a drain member 260. As an example, the second transistor 210 may be a complementary field effect transistor (CFET).

[0041] The multiple channel members 220 are arranged so as to be stacked in the z direction. In the second transistor 210, three or more channel members 220 may be stacked. Furthermore, the number of channel members 220 stacked in the second transistor 210 may be different from the number of channel members 120 stacked in the first transistor 110. The channel members 220 are arranged so as to overlap one another in a plan view of the semiconductor device 1. Furthermore, the channel members 220 may be arranged at predetermined intervals in the x direction and the y direction, with multiple stacked channel members 220 acting as one unit. In the example shown in FIGS. 2A to 2C, two stacked channel members 220 are arranged as part of the semiconductor device 1, three in the x direction and two in the y direction.

[0042] 2A, the channel member 220 included in the second transistor 210 may be arranged to overlap in the x direction with the channel member 120 included in the corresponding first transistor 110. On the other hand, as shown in FIG. 2C, the channel member 220 included in the second transistor 210 may be arranged to partially overlap in the y direction with the channel member 120 included in the corresponding first transistor 110. In other words, the channel member 220 may be arranged to not partially overlap in the y direction with the channel member 120.

[0043] In the example shown in FIG. 2C, the length of the portion of the channel member 120 that does not overlap with the channel member 220 in the y direction is W1. Furthermore, the length of the portion of the channel member 220 that does not overlap with the channel member 120 in the y direction is W2. Furthermore, the length of the portion where the channel member 120 and the channel member 220 overlap in the y direction is W3. The values ​​of the lengths W1, W2, and W3 may be set arbitrarily. The length W1 may be the same as the length W2, or may be different. In other words, the length of the channel member 120 in the y direction may be the same as the length of the channel member 220 in the y direction, or may be different. Furthermore,

[0044] The ratio of W3 to the length (W1+W3) of the channel member 120 in the y direction and the ratio of W3 to the length (W2+W3) of the channel member 220 in the y direction can be set arbitrarily. For example, the ratio can be 90% to 60%, 60% to 40%, or 40% to 10%.

[0045] 2C, the gate electrode 130 included in the first transistor 110 can be arranged in the y direction according to the position of the channel member 120. The gate electrode 230 included in the second transistor 210 can be arranged in the y direction according to the position of the channel member 220.

[0046] 2B, in the y direction, the source member 150 and the drain member 160 included in the first transistor 110 can be arranged according to the position of the channel member 120. Also, in the y direction, the source member 150 and the drain member 260 included in the second transistor 210 can be arranged according to the position of the channel member 220.

[0047] 2B , at least a portion of the source electrode 252 may be disposed above or below the source member 250. For example, when at least a portion of one source electrode 252 is disposed below the corresponding source member 250, at least a portion of another source electrode 252 adjacent to the one source electrode 252 may be disposed above the corresponding source member 250. For example, when at least a portion of one source electrode 252 is disposed to the right of the corresponding source member 250, at least a portion of the other source electrode 252 adjacent to the one source electrode 252 may be disposed to the left of the corresponding source member 250. For example, when at least a portion of one source electrode 252 is disposed to the right or left of the corresponding source member 250, at least a portion of the source electrode 152 corresponding to the one source electrode 252 may be disposed to the left or right of the corresponding source member 150. The same applies to the drain electrode 262.

[0048] FIG. 3 is a flowchart showing an example of a method for manufacturing a semiconductor device 1 (hereinafter also referred to as "this manufacturing method"). This manufacturing method includes a step of forming a second transistor on a substrate (step ST1), a step of forming a laminated film on the substrate (step ST2), a step of bonding the substrates together (step ST3), a step of forming a first transistor (step ST4), a step of forming wiring connected to the first transistor (step ST5), a step of inverting the substrate (step ST6), and a step of forming wiring connected to the second transistor (step ST7). Each step will be described below with reference to FIGS. 4 to 18. In the following description, the term "substrate" will be used to refer to both the substrate and the structure formed on the substrate.

[0049] 4A to 4C are diagrams showing an example of a cross-sectional structure of a portion of the substrate 20 after step ST1 has been performed. As shown in FIGS. 4A to 4C, in step ST1, a second transistor 210, a dielectric film 290, and a dielectric film 300-2 are formed on the substrate 20. The second transistor 210 and the dielectric film 290 may be formed in the same manner as the first transistor 110 and the dielectric film 190 formed in step ST4, which will be described later. The dielectric film 300-2 is formed on the second transistor 210 and the dielectric film 290. The dielectric film 300-2 may be formed on the entire surface of the substrate 20.

[0050] FIG. 5 is a diagram showing an example of a cross-sectional structure of a portion of the substrate 10 after step ST2 has been performed. As shown in FIG. 5, in step ST2, a stacked film 124 and a dielectric film 300-1 are formed on the substrate 10. The stacked film 124 is formed by alternately stacking channel members 120 and dummy members 122. As an example, the channel member 120 may be a silicon (Si) film. Also, as an example, the dummy member 122 may be a silicon germanium (SiGe) film. Both the silicon film and the silicon germanium film may be single-crystalline films. The dielectric film 300-1 is formed on the stacked film 124. The channel member 120, the dummy member 122, and the dielectric film 300-1 may all be formed on the entire surface of the substrate 10.

[0051] 6A to 6C are diagrams showing an example of the cross-sectional structure of a portion of the substrate 10 and the substrate 20 after step ST3 has been performed. As shown in Fig. 6A to 6C, the substrate 10 and the substrate 20 are bonded together so that the dielectric film 300-1 on the substrate 10 and the dielectric film 300-2 on the substrate 20 are bonded to each other.

[0052] 7A to 14C are diagrams showing an example of a cross-sectional structure of a portion of the substrate 20 in step ST4. Hereinafter, the flow of forming the first transistor 110 in step ST4 will be described with reference to FIGS.

[0053] First, as shown in FIGS. 7A to 7C, a portion of the stacked film 124 is etched to form a recess RC1 in the stacked film 124. First, the substrate 10 is removed. Then, the stacked film 124 is etched using a mask patterned on the stacked film 124. Here, as shown in FIG. 7A, the stacked film 124 is etched so that the position of the recess RC1 overlaps the position of the source member 250 and the drain member 260 in the x direction. Furthermore, as shown in FIG. 7C, the stacked film 124 is etched so that a portion of the stacked film 124 overlaps a portion of the channel member 220 in the y direction.

[0054] Next, as shown in FIGS. 8A to 8C, a portion of the dummy member 122 included in the stacked film 124 is etched. First, as shown in FIGS. 8A and 8C, a mask member 126 is formed on the stacked film 124. As shown in FIG. 8A, the mask member 126 is formed to have a length shorter than that of the channel member 120 in the x direction. Furthermore, as shown in FIG. 8C, the mask member 126 is formed so as to cover the upper and side surfaces of the stacked film 124. The mask member 126 may be formed of the same material as the channel member 120. As an example, the mask member 126 may be formed of polycrystalline silicon. Then, a portion of the dummy member 122 is etched using the mask member 126 as a mask. The dummy member 122 is etched selectively with respect to the channel member 120. Specifically, the dummy member 122 may be etched so that the channel member 120 protrudes from the dummy member 122 at both ends of the stacked film 124 in the x direction.

[0055] Next, as shown in FIGS. 9A to 9C, a source member 150, a drain member 160, and a dielectric film 190 are formed. First, the source member 150 and the drain member 160 are epitaxially grown at the end of the channel member 120. As an example, the channel member 120 is formed of single crystal silicon, and the source member 150 and the drain member 160 are formed by epitaxially growing single crystal silicon from the end of the channel member 120. Then, after the dielectric film 190 is formed, the upper surface of the dielectric film 190 is planarized. As an example, the dielectric film 190 can be planarized by CMP.

[0056] 10A to 10C, the mask member 126 and the dummy member 122 are removed. First, the mask member 126 is selectively removed with respect to the dielectric film 190. Then, the dummy member 122 is selectively removed with respect to the channel member 120 and the dielectric film 190. The dummy member 122 and the mask member 126 can be removed by wet etching.

[0057] 11A to 11C, a gate dielectric film 140 is formed on the surfaces of the channel member 120 and the dielectric film 190. As an example, the gate dielectric film 140 can be formed by growing a high-k material on the surfaces of the channel member 120 and the dielectric film 190 by CVD.

[0058] 12A to 12C, the gate electrode 130 is formed. The gate electrode 130 may be formed by growing a metal material by CVD in the space defined by the channel member 120 and the dielectric film 190. The upper surfaces of the gate electrode 130 and the dielectric film 190 may be planarized.

[0059] 13A to 13C, a portion of the dielectric film 190 is etched to form a recess RC2. The recess RC2 can be formed by etching the dielectric film 190 so as to expose a portion of the source member 150 and a portion of the drain member 160. The dielectric film 190 can be etched through a patterned mask.

[0060] Next, as shown in FIGS. 14A to 14C, the source electrode 152 and the drain electrode 162 are formed. The source electrode 152 and the drain electrode 162 are formed in the recess RC2. As an example, the source electrode 152 and the drain electrode 162 can be formed by filling the recess RC2 with a metal material. After the source electrode 152 and the drain electrode 162 are formed, the source electrode 152 and the drain electrode 162 may be heated to form an alloy at the contact surfaces between the source electrode 152 and the source member 150 and the drain member 160. As described above, in step ST4, the first transistor 110 is formed.

[0061] 15A to 15C are diagrams showing an example of a cross-sectional structure of a portion of the substrate 20 after step ST5 has been performed. As shown in Fig. 15A to 15C, in step ST5, a dielectric film 190 is further formed, and a plug 172, an interconnect 170, a plug 182, and an interconnect 180 are also formed. Then, the substrate 30 is bonded onto the dielectric film 190.

[0062] 16A to 16C are diagrams showing an example of a cross-sectional structure of a portion of the substrate 30 after step ST6 has been performed. As shown in Fig. 16A to 16C, the substrates 20 and 30 are inverted. Furthermore, the substrate 20 is removed.

[0063] 17A to 17C are diagrams showing an example of a cross-sectional structure of a portion of the substrate 30 after step ST7 has been performed. As shown in Fig. 17A to 17C, in step ST7, a dielectric film 290 is further formed, and a plug 272, a wiring 270, a plug 282, and a wiring 280 are also formed. Through the above steps, the semiconductor device 1 is formed.

[0064] According to an embodiment of the present disclosure, in a semiconductor device 1 in which a first transistor 110 and a second transistor 210 are stacked, the channel member 220 included in the second transistor 210 can be arranged offset with respect to the channel member 120 included in the first transistor 110. This increases the degree of freedom in the arrangement of each component included in the semiconductor device 1. Consequently, the parasitic capacitance in the semiconductor device 1 can be reduced.

[0065] The present disclosure may include, for example, the following configurations.

[0066] (Appendix 1) A semiconductor device comprising: a first transistor disposed in the first layer, the first transistor including a first channel, a first source, and a first drain, the first channel including one end and the other end in a first direction, the first source connected to the first channel at the one end of the first channel, and the first drain connected to the first channel at the other end of the first channel; a second transistor disposed on a second layer above the first layer, the second transistor including a second channel, a second source, and a second drain, the second channel having one end and the other end in the first direction, the second source connected to the second channel at the one end of the second channel, the second drain connected to the second channel at the other end of the second channel, and the first channel and the second channel being disposed to partially overlap in a second direction perpendicular to the first direction in a plan view of the semiconductor device; A semiconductor device comprising:

[0067] (Appendix 2) The first transistor is a first dielectric film disposed around the first channel; a first gate electrode disposed around the first dielectric film; Including, The second transistor is a second dielectric film disposed around the second channel; a second gate electrode disposed around the second dielectric film, the second gate electrode having a portion that does not overlap with the first gate electrode in a plan view of the semiconductor device; 2. The semiconductor device of claim 1, comprising:

[0068] (Appendix 3) a first wiring disposed below the first layer; a dielectric layer disposed between the first layer and the second layer; a first plug electrically connecting the first wiring and the second gate electrode, the first plug being disposed so as to penetrate the dielectric layer in a portion where the second gate electrode does not overlap the first gate electrode, and electrically connecting the first wiring and the second gate electrode; 3. The semiconductor device of claim 2, comprising:

[0069] (Appendix 4) the first transistor includes a plurality of the first channels; the plurality of first channels are arranged to overlap each other in a plan view of the semiconductor device; the first source is connected to the plurality of first channels; 4. The semiconductor device according to claim 1, wherein the first drain is connected to the plurality of first channels.

[0070] (Appendix 5) 1. A method for manufacturing a semiconductor device, comprising: forming a first transistor disposed in a first layer, the first transistor including a first channel, a first source, and a first drain, the first channel having one end and another end in a first direction, the first source connected to the first channel at the one end of the first channel, and the first drain connected to the first channel at the other end of the first channel; forming a second transistor in a second layer above the first layer, the second transistor including a second channel, a second source, and a second drain, the second channel including one end and the other end in the first direction, the second source connected to the second channel at the one end of the second channel, the second drain connected to the second channel at the other end of the second channel, and the first channel and the second channel arranged to partially overlap in a second direction perpendicular to the first direction in a plan view of the semiconductor device; A method for manufacturing a semiconductor device, comprising:

[0071] The exemplary embodiments described above may be modified in various ways without departing from the scope and spirit of the present disclosure. For example, some components in one embodiment may be added to other embodiments within the scope of ordinary creativity of a person skilled in the art. Also, some components in one embodiment may be replaced with corresponding components in other embodiments. [Explanation of symbols]

[0072] 1...semiconductor device, 100...first layer, 110...first transistor, 200...second layer, 210...second transistor, 300...dielectric layer

Claims

1. A semiconductor device comprising: a first transistor disposed in the first layer, the first transistor including a first channel, a first source, and a first drain, the first channel including one end and the other end in a first direction, the first source connected to the first channel at the one end of the first channel, and the first drain connected to the first channel at the other end of the first channel; a second transistor disposed in a second layer above the first layer, the second transistor including a second channel, a second source, and a second drain, the second channel including one end and the other end in the first direction, the second source connected to the second channel at the one end of the second channel, the second drain connected to the second channel at the other end of the second channel, and the first channel and the second channel arranged to partially overlap in a second direction perpendicular to the first direction in a plan view of the semiconductor device; A semiconductor device comprising:

2. The first transistor is a first dielectric film disposed around the first channel; a first gate electrode disposed around the first dielectric film; Including, The second transistor is a second dielectric film disposed around the second channel; a second gate electrode disposed around the second dielectric film, the second gate electrode having a portion that does not overlap with the first gate electrode in a plan view of the semiconductor device; The semiconductor device of claim 1 , comprising:

3. a first wiring disposed below the first layer; a dielectric layer disposed between the first layer and the second layer; a first plug electrically connecting the first wiring and the second gate electrode, the first plug being disposed so as to penetrate the dielectric layer in a portion where the second gate electrode does not overlap the first gate electrode, and electrically connecting the first wiring and the second gate electrode; The semiconductor device of claim 2 , comprising:

4. the first transistor includes a plurality of the first channels; the plurality of first channels are arranged to overlap each other in a plan view of the semiconductor device; the first source is connected to the plurality of first channels; The semiconductor device of claim 1 , wherein the first drain is connected to the plurality of first channels.

5. 1. A method for manufacturing a semiconductor device, comprising: forming a first transistor disposed in a first layer, the first transistor including a first channel, a first source, and a first drain, the first channel including one end and another end in a first direction, the first source connected to the first channel at the one end of the first channel, and the first drain connected to the first channel at the other end of the first channel; forming a second transistor in a second layer above the first layer, the second transistor including a second channel, a second source, and a second drain, the second channel including one end and the other end in the first direction, the second source connected to the second channel at the one end of the second channel, the second drain connected to the second channel at the other end of the second channel, and the first channel and the second channel arranged to partially overlap in a second direction perpendicular to the first direction in a plan view of the semiconductor device; A method for manufacturing a semiconductor device, comprising:

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