Computing device and method thereof

Abstract

To provide a method and device for designing an appropriate computation scheme that performs transformation efficiently in a butterfly process.SOLUTION: A computing device 200 which performs a butterfly process upon a sequence of 2N pieces of input data includes a first buffer, a second buffer, a fetch unit, an arithmetic unit, and a control unit. The control unit causes the fetch unit to read 2h pieces of input data from a memory as a first group of input data to the first buffer, causes the arithmetic unit to perform h stages of the butterfly process upon the first group of input data to generate a first group of updated data, causes, when the first group of update data is generated, the fetch unit to read another 2h pieces of input data from the memory as a second group of input data to the second buffer, and causes the fetch unit to write the first group of updated data to the memory.SELECTED DRAWING: Figure 3

Description

[Technical Field]

[0001] (CROSS-REFERENCE TO RELATED APPLICATIONS) This application claims the benefit of prior U.S. Provisional Application No. 63 / 554,140, ​​filed February 15, 2024, which is incorporated by reference in its entirety.

[0002] The present disclosure relates to computing devices, and more particularly to computing devices that perform number theoretic transforms (NTTs) or fast Fourier transforms (FFTs). [Background technology]

[0003] The Discrete Fourier Transform (DFT) is widely used in signal and image processing because it allows the analysis of the frequency components of a signal. The Fast Fourier Transform (FFT) is a widely used algorithm for computing the DFT, known for its efficiency and speed. The Fast Fourier Transform (FFT) reduces the computational complexity of the DFT to O(n 2 ) to O(n log n), where n is the number of input data points. This makes it particularly useful for real-time signal processing and other applications where speed is important.

[0004] On the other hand, number theoretic transforms (NTTs) are variations of FFTs specifically designed for operations over finite fields. NTT is used in lattice cryptography, which is important for post-quantum cryptography and homomorphic encryption schemes.

[0005] To facilitate the FFT and NTT calculations, a butterfly processing scheme is proposed. Butterfly processing involves combining and reordering input data in a particular way to efficiently compute a transform. However, butterfly processing typically requires two input data and two updated data outputs per calculation, making memory bandwidth a significant challenge in hardware implementations. Therefore, how to design an appropriate computation scheme to perform the transformation more efficiently becomes a problem to be solved. Summary of the Invention

[0006] One aspect of the present disclosure provides a computing device. The computing device includes: N It is configured to perform butterfly processing on a sequence of N input data (where N is a positive integer). The computing device includes a first buffer, a second buffer, a fetch unit, an arithmetic unit, and a control unit. The fetch unit is coupled to a memory, the first buffer, and the second buffer. The arithmetic unit is coupled to the first buffer and the second buffer and configured to perform arithmetic operations required for the butterfly processing. The control unit controls the fetch unit to N 2 of the input data h The input data (h is equal to or greater than 2 and less than N) is configured to be read from the memory as a first input data group to be stored in the first buffer. The control unit is further configured to cause the arithmetic unit to perform h stages of the butterfly processing on the first set of input data to generate a first set of updated data to be stored in the first buffer. The control unit further controls the fetch unit to generate the first update data group. N Another 2 of the input data h When the input data is read from the memory as a second input data group and the first update data group is generated, the fetch unit N Another 2 of the input data h The input data is configured to be read from the memory as a second set of input data to be stored in the second buffer. The control unit is further configured to cause the fetch unit to write the first set of update data to the memory.

[0007] Another aspect of the present disclosure is a method for manufacturing a semiconductor device comprising: N A method is provided for operating a computing device to perform a butterfly operation on a sequence of N input data, where N is a positive integer. The computing device includes a first buffer, a second buffer, a fetch unit, and an arithmetic unit. The method further comprises: N 2 of the input data h a step of reading input data (where h is 2 or more and less than N) from a memory as a first input data group to the first buffer; a step of executing h stages of the butterfly processing on the first input data group by the arithmetic unit to generate a first updated data group to the first buffer; and a step of fetching the 2 N Another 2 of the input data h The method includes reading the input data from the memory as a second input data group for the second buffer, and writing the first updated data group to the memory by the fetch unit. [Brief explanation of the drawings]

[0008] The present disclosure can be more fully understood by reference to the detailed description and claims when considered in conjunction with the drawings, wherein like reference numerals refer to like elements throughout.

[0009] [Figure 1] This shows the NTT butterfly processing scheme according to the Cooley-Tukey algorithm. [Figure 2] 1 illustrates a computing system according to a comparative embodiment of the present disclosure. [Figure 3] 1 illustrates a computing system according to one embodiment of the present disclosure. [Figure 4]4 shows a flowchart of a method for operating the computing device of FIG. 3 to perform butterfly processing according to one embodiment of the present disclosure. [Figure 5] 4 illustrates the structure of data path control in the computing device of FIG. 3 for NTT butterfly processing according to one embodiment of the present disclosure. [Figure 6] The butterfly processing scheme of INTT according to the Gentleman-Sande algorithm is shown. [Figure 7] 4 illustrates a datapath control structure in the computing device of FIG. 3 for butterfly processing of INTT according to one embodiment of the present disclosure. DETAILED DESCRIPTION OF THE INVENTION

[0010] To facilitate the computation of complex Fourier transforms, Cooley and Tukey proposed a well-known algorithm to re-express a larger-size discrete Fourier transform (DFT) into several smaller-size DFTs. For example, a DFT of complex size N can be re-expressed as N1 DFTs of size N2 (where N, N1, and N2 are positive integers, N=N1·N2), and such re-expression can be performed recursively, thereby reducing the complexity of the DFT.

[0011] Based on the Cooley-Tukey algorithm, a butterfly processing scheme has been developed to perform fast Fourier transforms (FFTs) or number-theoretic transforms (NTTs) in hardware. Figure 1 shows the NTT butterfly processing scheme according to the Cooley-Tukey algorithm. In Figure 1, the butterfly process is N It is used to transform an input polynomial of degree -1 (in this embodiment, N is equal to 4), and the 16 coefficients of the input polynomial become X[0] to X

[15] of the input data for the butterfly processing. In such a case, the butterfly processing shown in Figure 1 can derive the transformed data X'[0] to X'

[15] as the coefficients of the transformed polynomial according to the input data X[0] to X

[15] and the predetermined twiddle factors φ[1] to φ

[15] .

[0012] The butterfly processing scheme shown in FIG. 1 includes N stages (ie, four stages ST1, ST2, ST3 and ST4). In the first stage ST1, the input data X[0] and the input data X[8] are searched, and modular multiplication of the input data X[8] and the predetermined twiddle factor φ[1] by the predetermined coefficient q can be performed. In such a case, the intermediate data X1[0] of the first stage ST1 can be derived by adding the input data X[0] and the result of the modular multiplication, and the intermediate data X1[8] of the first stage ST1 can be derived by subtracting the result of the modular multiplication from the input data X[0]. That is, the intermediate data X1[0] and X1[8] can be expressed as the following equations (1) and (2).

[0013] X1[0]=X[0]+X[8]·φ[1]mod q (1) X1[8]=X[0]-X[8]·φ[1]mod q (2)

[0014] Similarly, other intermediate data in the first stage ST1 can be derived by the same calculation operation. For example, modular multiplication by a predetermined coefficient q can be performed on the input data X[9] and a predetermined twiddle factor φ[1], and the intermediate data X1[1] of the first stage ST1 can be derived by adding the result of the modular multiplication performed on the input data X[1] and the input data X[9]. Furthermore, X1[9] of the intermediate data of the first stage ST1 can be derived by subtracting the result of the modular multiplication performed on X[9] of the input data from X[1] of the input data.

[0015] The arithmetic operations used to derive the intermediate data in the first stage ST1 are further applied to other stages to derive intermediate data or final transformed data. For example, in the second stage ST2, intermediate data X1[0] and intermediate data X1[4] are searched, and modular multiplication of intermediate data X1[4] and a predetermined twiddle factor φ[2] by a predetermined coefficient q can be performed. In such a case, X2[0] of the intermediate data of the second stage ST2 can be derived by adding the result of the modular multiplication performed on the intermediate data X1[0] and X1[4] of the intermediate data, and X2[4] of the intermediate data of the second stage ST2 can be derived by subtracting the result of the modular multiplication performed on the intermediate data X1[4] from X1[0] of the intermediate data.

[0016] FIG. 2 illustrates a computing system 10 according to one comparative embodiment of the present disclosure. The computing system 10 is capable of performing the butterfly processing of FIG. The computing system 10 includes a computing device 100 and a memory 12 . In this embodiment, the computing device 100 can complete one stage of calculation for two pieces of input data per cycle. For example, the computing device 100 can derive intermediate data X1[0] and X1[8] based on input data X[0] and X[8] in one cycle, and derive intermediate data X1[1] and X1[9] based on input data X[1] and X[9] in another cycle.

[0017] In such a case, to maximize the utilization of the computing device 100, the computing device 100 needs to read two data from the memory 12 and write two data back to the memory 12 in each cycle, i.e., the memory 12 needs to support two read operations and two write operations per cycle (assuming each word of the memory 12 has the capacity to store only one input data). However, most memories support only two accesses (e.g., two read operations, two write operations, or one read and one write operation) in one cycle, requiring additional design work and circuit area for the memory to support four accesses in one cycle (e.g., a four-port memory). As a result, using a quad-port memory significantly increases costs and causes significant power consumption due to high frequency access operations.

[0018] FIG. 3 illustrates a computing system 20 according to one embodiment of the present disclosure. The computing system 20 includes a memory 22 and a computing device 200 . Compared to computing device 100, computing device 200 can reduce the required memory bandwidth while maintaining efficient utilization of the processing units within computing device 200, thereby simplifying hardware requirements and reducing power consumption.

[0019] The computing device 200 includes a first buffer 210, a second buffer 220, a fetch unit 230, an arithmetic unit 240, and a control unit 250. The fetch unit 230 may be coupled to the memory 22 , the first buffer 210 and the second buffer 220 . Fetch unit 230 can read data from memory 22 and write data to memory 22 . The first buffer 210 and the second buffer 220 can behave as ping-pong buffers, sequentially receiving data read from memory 22 by fetch unit 230 and sending data to fetch unit 230 for sequential writing to memory 22. The calculation unit 240 is coupled to the first buffer 210 and the second buffer 220, and can perform calculation operations necessary for butterfly processing based on the data stored in the first buffer 210 and the second buffer 220, and can store the calculation results in the first buffer 210 and the second buffer 220 and return them. The control unit 250 can control the data flow between the fetch unit 230, the first buffer 210, the second buffer 220 and the arithmetic unit 240 to perform the butterfly processing. Portions of computing device 200 may be implemented in digital electronic circuitry, firmware, software, and / or combinations thereof. Additionally, memory 22 may be static random access memory (SRAM), although the present disclosure is not limited thereto.

[0020] In this embodiment, the calculation device 200 performs FFT or NTT 2 N The butterfly process can be performed on a sequence of N input data, where N is a positive integer. In such a case, each of the first buffer 210 and the second buffer 220 has two N 2 of the input data h It can have a capacity to store (h is 2 or more and less than N) pieces of input data. Therefore, the computing device 200 may request the fetch unit 230 to retrieve two h The input data can be successively read and stored in the first buffer 210, etc. Then, the calculation unit 240 reads the corresponding input data according to the calculation order determined by the butterfly processing, and calculates the two input data stored in the first buffer 210. h Based on the input data, calculations for h stages of butterfly processing can be performed.

[0021] Furthermore, the computing device 200 may have the fetch unit 230 fetch another two input data from the memory 22 while the arithmetic unit 240 performs calculations on the input data stored in the first buffer 210. h The input data can be read and stored in the second buffer 220. In other words, by alternately using the first buffer 210 and the second buffer 220 to buffer input data for multiple stages of butterfly processing calculations, the computing device 200 can achieve appropriate data scheduling that can maintain high hardware utilization of the arithmetic unit 240 while reducing the bandwidth required for the memory 22.

[0022] In some embodiments, the arithmetic unit 240 can complete the calculation of one stage of butterfly processing for two input data within one cycle. Therefore, the calculation unit 240 is h To perform h-stage butterfly processing on data, the number of iterations is h 2 h-1 It takes a cycle. In such a case, the fetch unit 230 may use a delay of h 2 to keep the arithmetic unit 240 busy. h-1 Within a cycle, 2 h Read data and h To write (i.e. read) data, it takes h 2 h-2 It takes 2 cycles to write. h-2 (requires cycles). That is, the fetch unit 230 N At least one of the input data

number

number

[0023] FIG. 4 shows a flowchart of a method M1 for operating a computing device 200 to perform butterfly processing according to one embodiment of the present disclosure. The method M1 includes steps S110 to S117.

[0024] In this embodiment, the computing system 20 is capable of performing the butterfly processing shown in FIG. 1 (N equals 4 and h equals 2) according to the method M1. In such a case, the first buffer 210 and the second buffer 220 each have a capacity of 2 2 (i.e., 4) input data, in this case, a total of 2 4 The butterfly process is performed on the (i.e., 16) pieces of input data. For example, the first buffer 210 may include four registers R[0], R[1], R[2], and R[3], each for storing input data, as shown in FIG. Similarly, the second buffer 220 may include four registers R'[0], R'[1], R'[2], and R'[3], each for storing input data.

[0025] Table 1 shows a portion of the data scheduling for the computing device 200 that performs the NTT butterfly processing shown in FIG.

[0026] [Table 1(1)] [Table 1(2)]

[0027] 1, 4 and Table 1, in step S110, the control unit 250 instructs the fetch unit 230 to retrieve four pieces of input data from the memory as a first input data group into two pieces (i.e., h·2 h-2 ) can be read in successive cycles. The control unit 250 can cause the first buffer 210 to write the first set of input data. In this embodiment, h is equal to 2. N The first input data of the input data, 2N (2 of the input data N-1 +1)th input data, 2 N (2 of the input data N-2 +1)th input data, and 2 N (2 of the input data N-1 +2 N-2 +1)th input data may be included. For example, in Table 1, the fetch unit 230 fetches input data X[0] (i.e., the first input data among the 16 input data X[0] to X

[15] ) and input data X[8] (i.e., the second input data among the 16 input data X[0] to X

[15] ). N-1 +1)-th input data) can be read from the memory 22 in the first cycle #1, and further, X[4] of the input data (i.e., X[0] to X

[15] of the 16 input data) can be read from the memory 22 in the first cycle #2. N-2 +1)th input data) and input data X

[12] (i.e., (2 out of 16 input data X[0] to X

[15] ) N-1 +2 N-2 +1)th input data) can be read from memory 22 in the second cycle #2. In this embodiment, the memory 22 can deliver the read data within the next cycle after receiving a read request within the first cycle #1, thereby allowing the fetch unit 230 to store the input data X[0] and X[8] in registers R[0] and R[2], respectively, within the second cycle #2, and further store the input data X[4] and X

[12] in registers R[1] and R[3], respectively, within the third cycle #3.

[0028] In step S111, when at least a portion of the first input data group is stored in the first buffer 210, the control unit 250 causes the arithmetic unit 240 to perform two-stage (i.e., h-stage) butterfly processing on the first input data group stored in the first buffer 210 to generate a first updated data group (i.e., intermediate data X2[0], X2[8], X2[4] and X2

[12] ). The control unit 250 can cause the first buffer 210 to write the first set of updated data. In some embodiments, the computation unit 240 can complete the calculations required for one stage of butterfly processing on two input data within one cycle. For example, as shown in Table 1, the arithmetic unit 240 may derive intermediate data X1[0] and X1[8] based on the input data X[0] and X[8] stored in registers R[0] and R[2] in the third cycle #3, and derive intermediate data X1[4] and X1

[12] based on the input data X[4] and X

[12] stored in registers R[1] and R[3] in the fourth cycle #4.

[0029] Correspondingly, the intermediate data X1[0], X1[8], X1[4], and X1

[12] of the butterfly processing in the first stage ST1 are stored in the first buffer 210 in-place. In other words, intermediate data X1[0] can be stored in register R[0], which originally stored the corresponding input data X[0], and intermediate data X1[4] can be stored in register R[1], which originally stored the corresponding input data X[4].

[0030] Next, the arithmetic unit 240 may derive intermediate data X2[0] and X2[4] based on the intermediate data X1[0] and X1[4] stored in registers R[0] and R[1] in a fifth cycle #5, and may derive intermediate data X2[8] and X2

[12] based on the intermediate data X1[8] and X1

[12] stored in registers R[2] and R[3] in a sixth cycle #6. Then, the control unit 250 causes the first buffer 210 to store the first updated data group (i.e., X2[0], X2[4], X2[8], and X2

[12] of the intermediate data of the butterfly processing in the second stage ST2). In this embodiment, the intermediate data X2[0] and X2[4] are stored in registers R[0] and R[1] of the first buffer 210 in the fifth cycle #5, and the intermediate data X2[8] and X2

[12] are stored in registers R[2] and R[3] of the first buffer 210 in the sixth cycle #6.

[0031] In step S112, when the calculation unit 240 generates the first update data group, the control unit 250 can cause the fetch unit 230 to read the input data X[1], X[9], X[5], and X

[13] from the memory 22 as the second input data group in the fifth cycle #5 and the sixth cycle #6. The control unit 250 can also cause the second buffer 220 to store the second set of input data. In this embodiment, the input data X[1] and X[9] retrieved in the fifth cycle #5 are stored in the registers R'[0] and R'[2] of the second buffer 220, respectively, in the sixth cycle #6, and the input data X[5] and X

[13] retrieved in the sixth cycle #6 are stored in the registers R'[1] and R'[3] of the second buffer 220, respectively, in the seventh cycle #7.

[0032] That is, when the arithmetic unit 240 performs the second stage ST2 butterfly processing calculations on the intermediate data X1[0], X1[4], X1[8] and X1

[12] , the fetch unit 230 can read the input data from the memory 22 for subsequent calculations. Subsequently, since the first buffer 210 needs to store the intermediate data X2[0], X2[4], X2[8], and X2

[12] of the butterfly processing of the second stage ST2 derived by the arithmetic unit 240, the input data X[1], X[9], X[5], and X

[13] fetched by the fetch unit 230 are stored in the second buffer 220, thereby avoiding data contention in the first buffer 210.

[0033] In step S113, when at least a portion of the second input data group is stored in the second buffer 220, the control unit 250 causes the arithmetic unit 240 to perform two-stage butterfly processing on the second input data group (i.e., input data X[1], X[9], X[5], X

[13] ) to generate a second updated data group. The control unit 250 can cause the second buffer 220 to store the second update data group. Specifically, as shown in Table 1, the arithmetic unit 240 may derive X1[1] and X1[9] of the intermediate data of the butterfly processing of the first stage ST1 in the seventh cycle #7 based on the input data X[1] and X[9] stored in the registers R'[0] and R'[2], and may derive X1[5] and X1

[13] of the intermediate data of the butterfly processing of the first stage ST1 in the eighth cycle #8 based on the input data X[5] and X

[13] stored in the registers R'[1] and R'[3]. In this embodiment, the intermediate data X1[1], X1[5], X1[9], and X1

[13] are stored in place in registers R'[0], R'[1], R'[2], and R'[3], respectively.

[0034] Next, the arithmetic unit 240 may derive intermediate data X2[1] and X2[5] of the butterfly processing of the second stage ST2 in the ninth cycle #9 based on the intermediate data X1[1] and X1[5] stored in the registers R'[0] and R'[1], and may derive intermediate data X2[9] and X2

[13] of the butterfly processing of the second stage ST2 in the tenth cycle #10 based on the intermediate data X1[9] and X1

[13] stored in the registers R'[2] and R'[3]. Then, the control unit 250 can cause the second buffer 220 to store the second updated data group (i.e., X2[1], X2[5], X2[9], and X2

[13] of the intermediate data of the butterfly processing in the second stage ST2). In this embodiment, the intermediate data X2[1] and X2[5] are stored in registers R'[0] and R'[1] of the second buffer 220 in the ninth cycle #9, and the intermediate data X2[9] and X2

[13] are stored in registers R'[2] and R'[3] of the second buffer 220 in the tenth cycle #10.

[0035] In step S114, when step S113 is executed and the arithmetic unit 240 generates the second update data group (i.e., X2[1], X2[5], X2[9], and X2

[13] of the intermediate data of the butterfly processing in the second stage ST2), the control unit 250 instructs the fetch unit 230 to store the first update data group in the memory 22 as two (i.e., h·2 h-2 ) can be written in successive cycles. For example, the fetch unit 230 may write intermediate data X2[0] and X2[8] to replace input data X[0] and X[8] in the memory 22 in the seventh cycle #7, and may write intermediate data X2[4] and X2

[12] to replace input data X[4] and X

[12] in the memory 22 in the eighth cycle #8.

[0036] Furthermore, in step S115, when step S113 is executed within the ninth cycle #9 and the tenth cycle #10 and the calculation unit 240 generates a second update data group (i.e., X2[1], X2[5], X2[9] and X2

[13] of the intermediate data of the butterfly processing of the second stage ST2), the control unit 250 can cause the fetch unit 230 to read the input data X[2], X

[10] , X[6] and X

[14] from the memory 22 as a third input data group. The control unit 250 can cause the first buffer 210 to store the third set of input data for subsequent calculations.

[0037] In step S116, when at least a portion of the third input data group is stored in the first buffer 210, the control unit 250 causes the arithmetic unit 240 to perform two-stage butterfly processing on the third input data group (i.e., input data X[2], X

[10] , X[6], X

[14] ) to generate a third updated data group. In step S117, when step S116 is executed and the arithmetic unit 240 generates the third update data group, the control unit 250 instructs the fetch unit 230 to store the second update data group in the memory 22 as two (i.e., h·2 h-2 ) can be written in successive cycles. For example, the fetch unit 230 may write intermediate data X2[1] and X2[9] to replace input data X[1] and X[9] in the memory 22 in the 11th cycle #11, and may write intermediate data X2[5] and X2

[13] to replace input data X[5] and X

[13] in the memory 22 in the 12th cycle #12.

[0038] By repeating steps S110 to S117, the calculation device 200 can update the input data X[0] to X

[15] with the intermediate data X2[0] to X2

[15] of the butterfly processing of the second stage ST2, and further update the intermediate data X2[0] to X2

[15] of the butterfly processing of the second stage ST2 with the transformed data X'[0] to X'

[15] , thereby completing the butterfly processing.

[0039] In the computing system 20 and the method M1, a first buffer 210 and a second buffer 220 are used to store a plurality of input data (e.g., two h Because the input data are stored alternately, the data scheduling of the butterfly process can be optimized to allow the fetch unit 230 and the arithmetic unit 240 to be properly pipelined, thereby reducing the memory bandwidth required for the memory 22 while maintaining the hardware utilization of the computing device 200.

[0040] Furthermore, since the data flow of the butterfly processing is predetermined and the calculation operations of the butterfly processing at all stages are basically the same, a general data access scheme for the registers R[0] to R[3] of the first buffer 210 and the registers R'[0] to R'[3] of the second buffer 220 can be derived. FIG. 5 illustrates the structure of data path control in a computing device 200 for NTT butterfly processing according to one embodiment of the present disclosure. That is, the structure shown in FIG. 5 can operate according to method M1 of FIG. 4 to realize the NTT butterfly processing scheme shown in FIG. As shown in FIG. 5, the computing device 200 further includes a plurality of multiplexers (MUX) M1 to M14. MUXes M1-M14 may be controlled by control unit 250 (control lines coupled between control unit 250, MUXes M1-M14, and control unit 250 are not shown in FIG. 5 for simplicity).

[0041] In this embodiment, the arithmetic unit 240 includes an adder 242 , a subtractor 244 and a modular multiplier 246 . Adder 242 has a first input terminal coupled to first input terminal IN1 of arithmetic unit 240, a second input terminal, and an output terminal coupled to first output terminal OUT1 of arithmetic unit 240. Subtractor 244 has a first input terminal coupled to first input terminal IN1 of arithmetic unit 240, a second input terminal, and an output terminal coupled to second output terminal OUT2 of arithmetic unit 240. The remainder multiplier 246 has a first input terminal coupled to the second input terminal IN2 of the arithmetic unit 240, a second input terminal configured to receive a corresponding twiddle factor (i.e., a corresponding one of the twiddle factors φ[1] to φ

[15] ), and an output terminal coupled to the second input terminal of the adder 242 and the second input terminal of the subtractor 244. In some embodiments, adder 242 and subtractor 244 may each be implemented by an adder that supports signed addition, although this disclosure is not limited in this respect.

[0042] MUX M1 has a first input terminal coupled to fetch unit 230, a second input terminal coupled to a first output terminal OUT1 of arithmetic unit 240, and an output terminal coupled to register R[0]. MUX M2 has a first input terminal coupled to fetch unit 230, a second input terminal coupled to a first output terminal OUT1 of arithmetic unit 240, a third input terminal coupled to a second output terminal OUT2 of arithmetic unit 240, and an output terminal coupled to register R[1]. MUX M3 has a first input terminal coupled to fetch unit 230, a second input terminal coupled to a first output terminal OUT1 of arithmetic unit 240, a third input terminal coupled to a second output terminal OUT2 of arithmetic unit 240, and an output terminal coupled to register R[2]. MUX M4 has a first input terminal coupled to fetch unit 230, a second input terminal coupled to second output terminal OUT2 of arithmetic unit 240, and an output terminal coupled to register R[3].

[0043] MUX M5 has a first input terminal coupled to fetch unit 230, a second input terminal coupled to a first output terminal OUT1 of arithmetic unit 240, and an output terminal coupled to register R'[0]. MUX M6 has a first input terminal coupled to fetch unit 230, a second input terminal coupled to a first output terminal OUT1 of arithmetic unit 240, a third input terminal coupled to a second output terminal OUT2 of arithmetic unit 240, and an output terminal coupled to register R'[1]. MUX M7 has a first input terminal coupled to fetch unit 230, a second input terminal coupled to a first output terminal OUT1 of arithmetic unit 240, a third input terminal coupled to a second output terminal OUT2 of arithmetic unit 240, and an output terminal coupled to register R'[2]. MUX M8 has a first input terminal coupled to fetch unit 230, a second input terminal coupled to second output terminal OUT2 of arithmetic unit 240, and an output terminal coupled to register R'[3].

[0044] MUX M9 has a first input terminal coupled to register R[1], a second input terminal coupled to register R[2], a third input terminal coupled to register R[3], and an output terminal. MUX M10 has a first input terminal coupled to register R'[1], a second input terminal coupled to register R'[2], a third input terminal coupled to register R'[3], and an output terminal. MUX M11 has a first input terminal coupled to the output terminal of MUX M9, a second input terminal coupled to the output terminal of MUX M10, and an output terminal coupled to a second input terminal IN2 of arithmetic unit 240.

[0045] MUX M12 has a first input terminal coupled to register R[0], a second input terminal coupled to register R[1], a third input terminal coupled to register R[2], and an output terminal. MUX M13 has a first input terminal coupled to register R'[0], a second input terminal coupled to register R'[1], a third input terminal coupled to register R'[2], and an output terminal. MUX M14 has a first input terminal coupled to the output terminal of MUX M12, a second input terminal coupled to the output terminal of MUX M13, and an output terminal coupled to a first input terminal IN1 of arithmetic unit 240.

[0046] As a result, by controlling the multiplexers M1 to M14, the control unit 250 can control the data flow of the calculation device 200, so that the arithmetic unit 240 receives and calculates corresponding data, and stores the calculation results in corresponding registers accordingly, to complete the calculation of the butterfly processing of each stage.

[0047] In some embodiments, computing device 200 may further include data path control units 232 and 234 for controlling the data flow between fetch unit 230 and registers R[0]-R[3], and the data flow between fetch unit 230 and registers R'[0]-R'[3]. In some embodiments, each of data path control units 232 and 234 may include a multiplexer, a demultiplexer, or a combination thereof, that is, data path control units 232 and 234 may be implemented in digital electronic circuitry.

[0048] In this embodiment, the computing system 20 is used to run NTT, although the present disclosure is not limited thereto. In some embodiments, the computing system 20 may be used to perform an FFT by simply modifying the input data and twiddle factors.

[0049] Additionally, in some embodiments, the computing system 20 may be used to perform an inverse NTT (INTT) and an inverse FFT (IFFT). FIG. 6 shows the scheme of butterfly processing of INTT according to the Gentleman-Sande algorithm. In Figure 6, the butterfly processing of INTT is N (In this embodiment, N is equal to 4) The input data Y[0] to Y

[15] are divided into 2 N The pieces of conversion data Y'[0] to Y'

[15] are converted. The butterfly process of INTT shown in Figure 6 is an inverse version of the butterfly process of NTT shown in Figure 1, with the twiddle factors φ'[1] to φ'

[15] reversed.

[0050] For example, Y1[0] of the intermediate data of the first stage ST1 of the butterfly processing in FIG. 6 can be derived by adding Y[0] of the input data and Y[1] of the input data, and Y1[1] of the intermediate data of the first stage ST1 of the butterfly processing in FIG. 6 can be derived by subtracting Y[1] of the input data from Y[0] of the input data and performing modular multiplication of the twiddle factor φ'[1] corresponding to the subtraction result by a predetermined coefficient q. That is, Y1[0] and Y1[1] of the intermediate data can be expressed as the following equations (3) and (4).

[0051] Y1[0]=Y[0]+Y1 (3) Y1[1]=(Y[0]-Y[1])·φ'[1]mod q (4)

[0052] In this embodiment, the computing device 200′ as shown in FIG. 7 differs from the computing device 200 in that the arithmetic unit 240 is replaced with an arithmetic unit 240′ for calculating equations (3) and (4), and may be used to perform the butterfly processing of INTT shown in FIG. 6. For example, the computing device 200' may have the fetch unit 230 fetch two h The input data can be successively read and stored in the first buffer 210, etc. Then, the calculation unit 240' reads the corresponding input data according to the calculation order determined by the butterfly processing of the INTT, and calculates the two input data stored in the first buffer 210. h Based on the input data, calculations for h stages of butterfly processing of INTT can be performed.

[0053] Furthermore, the computing device 200' may have the fetch unit 230 fetch another two input data from the memory 22 while the arithmetic unit 240' performs calculations on the input data stored in the first buffer 210. h The input data can be read and stored in the second buffer 220. That is, when performing the butterfly processing of INTT, the computing device 200' can alternately buffer input data using the first buffer 210 and the second buffer 220 so that the fetch unit 230 and the arithmetic unit 240' can be properly pipelined, thereby maintaining high hardware utilization of the arithmetic unit 240' while reducing the memory bandwidth required for the memory 22. In this embodiment, the computing system 20 may be used to perform INTT, although the present disclosure is not limited thereto. In some embodiments, the computing system 20 may be used to perform the IFFT by simply modifying the input data and twiddle factors.

[0054] Table 2 shows a portion of the data scheduling for the computing device 200' that performs the butterfly processing of INTT shown in FIG.

[0055] [Table 2(1)] [Table 2(2)]

[0056] Referring to FIG. 6 and Table 2, the control unit 250 instructs the fetch unit 230 to retrieve four input data from the memory 22 into two (i.e., h 2 h-2 ) can be read in successive cycles. In this embodiment, h is equal to 2. For example, the input data read in the first cycle #1 and the second cycle #2 is 2 N The first input data (e.g., data Y[0]) of the input data, 2 N The second input data (for example, data Y[1]) of the input data, 2 N The third input data (e.g., data Y[2]) among the input data, and N The input data may include the fourth input data (for example, data Y[3]) among the input data.

[0057] Since the data flow of the butterfly processing of the INTT is predetermined and the calculation operations of the butterfly processing of all stages are basically the same, a general data access scheme can be derived for the registers R[0] to R[3] of the first buffer 210 and the registers R'[0] to R'[3] of the second buffer 220. FIG. 7 illustrates the structure of datapath control in a computing device 200' for butterfly processing of INTT according to one embodiment of the present disclosure. That is, the structure shown in FIG. 7 can operate according to the method M1 of FIG. 4 to realize the butterfly processing scheme of INTT shown in FIG.

[0058] As shown in FIG. 7, the muxes M1 to M14 used in the data path control structure for the butterfly processing of NTT in FIG. 5 may be used in the butterfly processing of INTT in FIG. Comparing the structure shown in FIG. 5 with the structure shown in FIG. 7, the difference is that the arithmetic unit 240' is reconfigured according to the arithmetic operations required for butterfly processing of INTT. Specifically, the first input terminal IN1 of the arithmetic unit 240′ is coupled to the first input terminal of the adder 242 and the first input terminal of the subtractor 244, the second input terminal IN2 of the arithmetic unit 240′ is coupled to the second input terminal of the adder 242 and the second input terminal of the subtractor 244, the first output terminal OUT1 of the arithmetic unit 240′ is coupled to the output terminal of the adder 242, and the second output terminal OUT2 of the arithmetic unit 240′ is coupled to the output terminal of the remainder multiplier 246. The output terminal of the subtractor 244 is also coupled to a first input terminal of a remainder multiplier 246 . A second input terminal of the remainder multiplier 246 is configured to receive a corresponding twiddle factor (ie, a corresponding one of the twiddle factors Φ'[1] to Φ'

[15] ). In some embodiments, the computation unit 240' may include a multiplexer (not shown in FIGS. 5 and 7) for rearranging the data flow, such that the computation unit 240' has the configuration shown in FIG. 5 when performing an NTT or FFT, and can be changed to have the configuration shown in FIG. 7 for performing an INTT or IFFT.

[0059] By appropriately controlling the multiplexers M1 to M14 by the control unit 250, the computing device 200′ can perform the butterfly processing of INTT and alternately store multiple input data using the first buffer 210 and the second buffer 220, thereby optimizing the data scheduling of the butterfly processing and enabling the fetch unit 230 and the arithmetic unit 240′ to be appropriately pipelined. As a result, the memory bandwidth required for memory 22 can be reduced and hardware utilization of computing device 200' can be maintained.

[0060] In summary, the computing device, computing system, and method for operating the computing device provided in the embodiments of the present disclosure use two buffers to store multiple input data (e.g., two h Since the input data are stored alternately, the data scheduling of the butterfly processing can be optimized, and the operations of the fetch unit and the arithmetic unit can be appropriately pipelined. As a result, the memory bandwidth required for the memory can be reduced, and the hardware utilization of the computing device can be maintained.

Claims

1. 2 Ｎ 1. A computing device configured to perform a butterfly operation on a sequence of N input data, where N is a positive integer, comprising: A first buffer; A second buffer; a fetch unit coupled to a memory, the first buffer, and the second buffer; an arithmetic unit coupled to the first buffer and the second buffer and configured to perform arithmetic operations necessary for the butterfly processing; a control unit, the control unit comprising: The fetch unit Ｎ 2 of the input data ｈ (h is equal to or greater than 2 and less than N) input data are read from the memory as a first input data group to be stored in the first buffer; causing the arithmetic unit to perform h stages of the butterfly processing on the first input data group to generate a first updated data group to be stored in the first buffer; When the first update data group is generated, the second update data group is Ｎ Another two of the input data ｈ reading the input data from the memory as a second input data group to be stored in the second buffer; A computing device configured to cause the fetch unit to write the first set of update data to the memory.

2. The control unit further comprises:

2. The computing device of claim 1, wherein when at least a portion of the second input data group is stored in the second buffer, the computing unit is configured to perform h stages of the butterfly processing on the second input data group to generate a second updated data group to be stored in the second buffer.

3. The computing device of claim 2 , wherein, upon generating the second set of update data, the control unit is configured to cause the fetch unit to write the second set of update data to the memory.

4. The control unit further comprises: When the second update data group is generated, the second update data group is Ｎ Another two of the input data ｈ 3. The computing device of claim 2, configured to cause the input data to be read from the memory as a third group of input data stored in the first buffer.

5. 2. The computing device according to claim 1, wherein when at least a portion of the first input data group is stored in the first buffer, the control unit causes the arithmetic unit to perform h stages of the butterfly processing on the first input data group.

6. The computing device of claim 1 , wherein intermediate data generated in a first stage of the h-stage butterfly processing for the first set of input data is stored in the first buffer in place.

7. The computing device according to claim 1 , wherein the arithmetic unit is configured to complete a calculation required for one stage of the butterfly processing on two input data within one cycle.

8. The butterfly processing is for a fast Fourier transform (FFT) or a number theoretic transform (NTT), and the arithmetic unit an adder having a first input terminal coupled to the first input terminal of the arithmetic unit, a second input terminal, and an output terminal coupled to the first output terminal of the arithmetic unit; a subtractor having a first input terminal coupled to the first input terminal of the arithmetic unit, a second input terminal, and an output terminal coupled to the second output terminal of the arithmetic unit; 2. The computing device of claim 1, further comprising: a modular multiplier having a first input terminal coupled to the second input terminal of the arithmetic unit, a second input terminal configured to receive a corresponding twiddle factor, and an output terminal coupled to the second input terminal of the adder and the second input terminal of the subtractor.

9. a first multiplexer (MUX) having a first input terminal coupled to the fetch unit, a second input terminal coupled to a first output terminal of the arithmetic unit, and an output terminal coupled to a first register of the first buffer; a second MUX having a first input terminal coupled to the fetch unit, a second input terminal coupled to the first output terminal of the arithmetic unit, a third input terminal coupled to the second output terminal of the arithmetic unit, and an output terminal coupled to a second register of the first buffer; a third MUX having a first input terminal coupled to the fetch unit, a second input terminal coupled to the first output terminal of the arithmetic unit, a third input terminal coupled to the second output terminal of the arithmetic unit, and an output terminal coupled to a third register of the first buffer; a fourth MUX having a first input terminal coupled to the fetch unit, a second input terminal coupled to the second output terminal of the arithmetic unit, and an output terminal coupled to a fourth register of the first buffer; a fifth MUX having a first input terminal coupled to the fetch unit, a second input terminal coupled to the first output terminal of the arithmetic unit, and an output terminal coupled to a first register of the second buffer; a sixth MUX having a first input terminal coupled to the fetch unit, a second input terminal coupled to the first output terminal of the arithmetic unit, a third input terminal coupled to the second output terminal of the arithmetic unit, and an output terminal coupled to a second register of the second buffer; a seventh MUX having a first input terminal coupled to the fetch unit, a second input terminal coupled to the first output terminal of the arithmetic unit, a third input terminal coupled to the second output terminal of the arithmetic unit, and an output terminal coupled to a third register of the second buffer; 8. The computing device of claim 7, further comprising: an eighth MUX having a first input terminal coupled to the fetch unit, a second input terminal coupled to the second output terminal of the arithmetic unit, and an output terminal coupled to a fourth register of the second buffer.

10. a ninth MUX having a first input terminal coupled to a second register of the first buffer, a second input terminal coupled to a third register of the first buffer, a third input terminal coupled to a fourth register of the first buffer, and an output terminal; a tenth MUX having a first input terminal coupled to the second register of the second buffer, a second input terminal coupled to the third register of the second buffer, a third input terminal coupled to the fourth register of the second buffer, and an output terminal; 9. The computing device of claim 8, further comprising: an eleventh MUX having a first input terminal coupled to the output terminal of the ninth MUX, a second input terminal coupled to the output terminal of the tenth MUX, and an output terminal coupled to the second input terminal of the arithmetic unit.

11. a twelfth MUX having a first input terminal coupled to a first register of the first buffer, a second input terminal coupled to a second register of the first buffer, a third input terminal coupled to a third register of the first buffer, and an output terminal; a thirteenth MUX having a first input terminal coupled to the first register of the second buffer, a second input terminal coupled to the second register of the second buffer, a third input terminal coupled to the third register of the second buffer, and an output terminal; 9. The computing device of claim 8, further comprising: a fourteenth MUX having a first input terminal coupled to the output terminal of the twelfth MUX, a second input terminal coupled to the output terminal of the thirteenth MUX, and an output terminal coupled to the first input terminal of the arithmetic unit.

12. 2 Ｎ 1. A method of operating a computing device including a first buffer, a second buffer, a fetch unit and an arithmetic unit to perform a butterfly operation on a sequence of N input data, where N is a positive integer, the method comprising: The fetch unit Ｎ 2 of the input data ｈ reading input data (h is greater than or equal to 2 and less than N) from memory as a first set of input data into the first buffer; performing h stages of the butterfly processing on the first input data group by the arithmetic unit to generate a first updated data group for the first buffer; When the first update data group is generated, the fetch unit Ｎ Another two of the input data ｈ reading the input data from the memory as a second set of input data into the second buffer; and writing, by the fetch unit, the first set of update data to the memory.

13. 13. The method of claim 12, further comprising the step of, when at least a portion of the second input data group is stored in the second buffer, performing h stages of the butterfly processing on the second input data group by the arithmetic unit to generate a second updated data group for the second buffer.

14. The method of claim 13 , wherein the step of writing the first set of update data to the memory by the fetch unit is performed when the second set of update data is generated.

15. When the second update data group is generated, the fetch unit Ｎ Another two of the input data ｈ 14. The method of claim 13, further comprising reading the input data from the memory as a third group of input data into the first buffer.

16. 13. The method of claim 12, wherein the step of performing h stages of the butterfly processing on the first input data group by the arithmetic unit to generate a first updated data group for the first buffer is executed when at least a portion of the first input data group is stored in the first buffer.

17. 13. The method of claim 12, further comprising storing, by the first buffer, intermediate data generated in a first stage of the h-stage butterfly processing on the first set of input data in an in-place manner.

18. h is equal to 2, the butterfly processing is for NTT or FFT, and the first input data set is Ｎ The first input data of the input data, Ｎ Of the input data (2 Ｎ－２ +1)th input data, Ｎ Of the input data (2 Ｎ－１ +1)th input data, and the 2 Ｎ Of the input data (2 Ｎ－１ +2 Ｎ－２ 13. The method of claim 12, wherein the input data includes the (+1)th input data.

19. h is equal to 2, the butterfly processing is for an INTT or IFFT, and the first set of input data is Ｎ The first input data of the input data and the second input data Ｎ The second input data of the input data, Ｎ the third input data among the input data, and Ｎ and a fourth input data of the input data.

20. The step of performing h stages of the butterfly processing on the first input data group by the arithmetic unit to generate a first updated data group for the first buffer includes:

13. The method of claim 12, further comprising the step of completing, by the arithmetic unit, calculations required for one stage of the butterfly processing on two input data within one cycle.

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