Photoelectric conversion device

Abstract

To provide a suitable structure of a trench part in a configuration in which a plurality of photoelectric conversion parts are provided for one microlens.SOLUTION: A photoelectric conversion device has: a semiconductor substrate having a first principal surface and a second principal surface; a microlens array; a plurality of pixels each having a plurality of photoelectric conversion parts on a plurality of rows and a plurality of columns arranged inside the substrate and arranged in correspondence with one microlens, and a first trench part separating the plurality of photoelectric conversion parts from each other; and a second trench part provided between the adjacent two pixels. A first area between one and the other of a plurality of first portions and a second area between one and the other of a plurality of second portions each have a semiconductor area included in the semiconductor substrate. In plan view, at a depth position between the first principal surface and the second principal surface, a part of the first trench part is arranged at a position overlapping the first area and a position overlapping the second area.SELECTED DRAWING: Figure 7

Description

[Technical Field]

[0001] The present disclosure relates to a photoelectric conversion device that converts light into an electrical signal. [Background technology]

[0002] 2. Description of the Related Art Photoelectric conversion devices that generate signal charges corresponding to incident light are known.

[0003] Known examples of such photoelectric conversion devices include a configuration in which trenches are provided between multiple photoelectric conversion units, as in Patent Document 1. By providing these trenches, it is believed that the multiple photoelectric conversion units can be suitably electrically isolated from each other. [Prior art documents] [Patent documents]

[0004] [Patent Document 1] U.S. Patent Publication No. 2016 / 0056200 Summary of the Invention [Problem to be solved by the invention]

[0005] In the technology described in Patent Document 1, a suitable structure of the trench portion in a configuration in which a plurality of photoelectric conversion portions are provided for one microlens is not sufficiently considered.

[0006] The technique of the present disclosure provides a suitable trench structure in a configuration in which a plurality of photoelectric conversion units are provided for one microlens. [Means for solving the problem]

[0007] One aspect of the present disclosure relates to a semiconductor substrate having a first main surface on which light is incident and a second main surface opposite to the first main surface, a microlens array having a plurality of microlenses, a corresponding one of the plurality of microlenses, a plurality of photoelectric conversion units arranged in a plurality of rows and a plurality of columns corresponding to the one microlens, and a first trench portion separating the plurality of photoelectric conversion units, and a first trench portion separating two adjacent pixels from the plurality of pixels. a photoelectric conversion unit included in one of the two adjacent pixels and a second trench unit provided between the photoelectric conversion unit included in the other of the two adjacent pixels, and in the first main surface, in a plan view with respect to the first main surface, the first trench unit has a plurality of first portions extending in a first direction and a plurality of second portions extending in a second direction intersecting with the first direction, and a first region between one and the other of the plurality of first portions and a second region between one and the other of the plurality of second portions each have a semiconductor region included in the semiconductor substrate, This photoelectric conversion device is characterized in that, at a depth position between the first main surface and the second main surface, a portion of the first trench portion is arranged at a position overlapping the first region and a position overlapping the second region in the planar view.

[0008] Another side surface includes a semiconductor substrate having a first main surface on which light is incident and a second main surface opposite to the first main surface, a microlens array having a plurality of microlenses, a corresponding one of the plurality of microlenses, a plurality of photoelectric conversion units arranged in a plurality of rows and a plurality of columns corresponding to the one microlens, and a first trench portion separating the plurality of photoelectric conversion units, and a photoelectric conversion unit included in one of two adjacent pixels among the plurality of pixels and a first trench portion provided between the photoelectric conversion unit included in the other of the two adjacent pixels. and a second trench portion formed by forming a first trench portion on the second main surface, wherein, in a plan view relative to the second main surface, the first trench portion has a plurality of first portions extending in a first direction and a plurality of second portions extending in a second direction intersecting the first direction, a first region between one and another of the plurality of first portions and a second region between one and another of the plurality of second portions each have a semiconductor region included in the semiconductor substrate, and a portion of the first trench portion is arranged at a depth position between the first main surface and the second main surface at a position overlapping the first region and a position overlapping the second region in the plan view.

[0009] Another aspect of the present invention relates to a semiconductor substrate having a first main surface on which light is incident and a second main surface opposite to the first main surface, a microlens array having a plurality of microlenses, a corresponding one of the plurality of microlenses, a plurality of photoelectric conversion units arranged in a plurality of rows and a plurality of columns corresponding to the one microlens, the photoelectric conversion units being arranged inside the semiconductor substrate and corresponding to the one microlens, and a first trench portion separating the plurality of photoelectric conversion units, and a photoelectric conversion unit included in one of two adjacent pixels among the plurality of pixels, and a first trench portion separating the adjacent photoelectric conversion units. and a second trench portion provided between the first main surface and the photoelectric conversion portion included in the other of the two matching pixels, wherein in the first main surface, when viewed in a plane relative to the first main surface, the first trench portion has a first portion extending in a first direction, in the second main surface, when viewed in a plane relative to the second main surface, the first portion and the third portion have overlapping portions in a plane relative to the first main surface, and a semiconductor region included in the semiconductor substrate is arranged between the first portion and the third portion. [Effects of the Invention]

[0010] The technique of the present disclosure can provide a suitable trench structure in a configuration in which a plurality of photoelectric conversion units are provided for one microlens. [Brief explanation of the drawings]

[0011] [Figure 1] Block diagram showing the overall configuration of a photoelectric conversion device [Figure 2] Diagram showing the unit configuration [Figure 3] Diagram showing the unit configuration [Figure 4] Block diagram showing a partial configuration of a photoelectric conversion device [Figure 5] 1 is a drive timing diagram illustrating the operation of a photoelectric conversion device; [Figure 6] 1 is a diagram showing the configuration of a stacked photoelectric conversion device; [Figure 7] Plan view of a photoelectric conversion device [Figure 8] Cross-sectional view of a photoelectric conversion device [Figure 9] Cross-sectional view of a photoelectric conversion device [Figure 10] Cross-sectional view of a photoelectric conversion device [Figure 11] Cross-sectional view of a photoelectric conversion device [Figure 12] Plan view of a photoelectric conversion device [Figure 13] Cross-sectional view of a photoelectric conversion device [Figure 14] Plan view of a photoelectric conversion device [Figure 15] Cross-sectional view of a photoelectric conversion device [Figure 16] Cross-sectional view of a photoelectric conversion device [Figure 17] Cross-sectional view of a photoelectric conversion device [Figure 18] Cross-sectional view of a photoelectric conversion device [Figure 19] Plan view of a photoelectric conversion device [Figure 20] Cross-sectional view of a photoelectric conversion device [Figure 21] Plan view of a photoelectric conversion device [Figure 22] Plan view of a photoelectric conversion device [Figure 23] Cross-sectional view of a photoelectric conversion device [Figure 24] Cross-sectional view of a photoelectric conversion device [Figure 25] Cross-sectional view of a photoelectric conversion device [Figure 26] Cross-sectional view of a photoelectric conversion device [Figure 27] Plan view of a photoelectric conversion device [Figure 28] Equipment configuration diagram DETAILED DESCRIPTION OF THE INVENTION

[0012] Each embodiment will be described below with reference to the drawings.

[0013] In the following embodiments, an image pickup device will be mainly described as an example of a photoelectric conversion device. However, the embodiments are not limited to image pickup devices and can be applied to other examples of photoelectric conversion devices. For example, a distance measurement device (a device that measures distance using focus detection or TOF (Time Of Flight)) or a photometry device (a device that measures the amount of incident light) can be used.

[0014] Furthermore, the conductivity types of the semiconductor regions and wells and the dopants to be implanted described in the following embodiments are merely examples and are not limited to the conductivity types and dopants described in the embodiments. The conductivity types and dopants described in the embodiments can be changed as appropriate, and the potentials of the semiconductor regions and wells will be changed as appropriate in accordance with this change.

[0015] The conductivity types of the transistors described in the following embodiments are merely examples and are not limited to those described in the examples. The conductivity types described in the embodiments can be changed as appropriate, and the potentials of the gate, source, and drain of the transistors can be changed as appropriate.

[0016] For example, in the case of a transistor operated as a switch, the low and high levels of the potential supplied to the gate may be reversed in accordance with the change in the conductivity type. The conductivity types of the semiconductor regions described in the following examples are merely examples and are not limited to the conductivity types described in the examples. The conductivity types described in the examples can be changed as appropriate, and the potential of the semiconductor regions is accordingly changed accordingly.

[0017] In the following embodiments, the connection between elements of a circuit may be described. In this case, even if another element is interposed between the elements of interest, the elements of interest are treated as being connected to each other unless otherwise specified. For example, assume that element A is connected to one node of a capacitive element C having multiple nodes, and element B is connected to the other node. Even in such a case, element A and element B are treated as being connected to each other unless otherwise specified.

[0018] Metallic components such as wiring and pads described herein may be composed of a single metal element or a mixture (alloy). For example, wiring described as copper wiring may be composed of copper alone or may be composed primarily of copper with other components. Furthermore, for example, pads connected to external terminals may be composed of aluminum alone or may be composed primarily of aluminum with other components. The copper wiring and aluminum pads shown here are merely examples and can be replaced with various metals.

[0019] Furthermore, the wiring and pads shown here are examples of metal members used in photoelectric conversion devices, and the present invention can also be applied to other metal members.

[0020] (First embodiment) 1 is a block diagram showing a schematic configuration of a photoelectric conversion device according to this embodiment. The photoelectric conversion device includes a CPU (Central Processing Unit) 1, a control unit 2, a vertical scanning unit 3, a pixel array 4, a column circuit unit 5, a horizontal scanning unit 6, and a signal output unit 7. The various circuits constituting the photoelectric conversion device may be formed on one or more semiconductor substrates.

[0021] The CPU 1 is a processor that controls the photoelectric conversion device by executing a program. The CPU 1 may be provided within the photoelectric conversion device, or may be provided within a photoelectric conversion system in which the photoelectric conversion device is installed, i.e., outside the photoelectric conversion device.

[0022] The control unit 2 is a control circuit that receives control signals such as synchronization signals output from the CPU 1 and setting signals indicating operation modes and the like, and supplies control signals to the vertical scanning unit 3, the column circuit unit 5, and the horizontal scanning unit 6.

[0023] The vertical scanning unit 3 is a scanning circuit including a shift register, a gate circuit, a buffer circuit, etc. The vertical scanning unit 3 receives control signals such as a vertical synchronization signal, a horizontal synchronization signal, and a clock signal from the control unit 2 and performs reset scanning and readout scanning of the pixel array 4. Note that reset scanning is an operation of sequentially releasing the reset state of the photoelectric conversion units of some or all rows of pixels of the pixel array 4 and setting them into a charge accumulation state, thereby starting exposure. Also, readout scanning is an operation of sequentially outputting signals based on the charges accumulated in the photoelectric conversion units of some or all rows of pixels of the pixel array 4. The vertical scanning unit 3 corresponds to a driver that outputs drive signals to the pixel array 4 to drive the pixel array 4 row by row.

[0024] The pixel array 4 has a plurality of pixels P(1,1) to P(a,b) arranged in N rows and M columns, and a plurality of vertical output lines Vline(1) to Vline(b) in M ​​columns. Here, the row direction refers to the horizontal direction in the drawing, and the column direction refers to the vertical direction in the drawing. The subscripts in parentheses next to the pixels P(a,b) indicate the column number and row number, respectively. The row number of the topmost row in FIG. 1 is the first row, and the column number of the leftmost row in FIG. 1 is the first column. Note that when it is not necessary to indicate the column number and row number, the subscripts indicating the column number and row number may be omitted.

[0025] The column circuit unit 5 includes an amplifier circuit, an analog-to-digital conversion (hereinafter referred to as "AD conversion") circuit, and a column memory. Each of these circuits is arranged corresponding to one of the vertical output lines Vline(1) to Vline(b). The column circuit unit 5 amplifies signals read from the pixel array 4, performs AD conversion, and stores the signals in the column memory as digital signals. The horizontal scanning unit 6 is a scanning circuit including a shift register, a gate circuit, a buffer circuit, etc. Upon receiving a control signal from the control unit 2, the horizontal scanning unit 6 sequentially scans the signals stored in the memory of the column circuit unit 5 and outputs them to the signal output unit 7.

[0026] The signal output unit 7 includes a digital processing unit, a parallel-serial conversion circuit, and an output circuit such as LVDS (Low Voltage Differential Signaling), etc. The signal output unit 7 digitally processes the signal output from the horizontal scanning unit 6 and outputs it as serial data to the outside of the photoelectric conversion device.

[0027] It is not essential that the column circuit unit 5 has an AD conversion function; for example, the configuration may be modified so that AD conversion is performed outside the photoelectric conversion device. In this case, the configurations of the horizontal scanning unit 6 and the signal output unit 7 are also modified appropriately to suit analog signal processing. FIG. 2 is a circuit diagram of a pixel P included in the pixel array 4 according to this embodiment. FIG. 2 shows the configurations of pixel P(x, y) in the xth column and yth row and pixel P(x, y+1) in the xth column and y+1th row.

[0028] A unit U(m,n) includes two rows of pixels P. The unit U(m,n) shown in Figure 2 includes a pixel P(x,y) and a pixel P(x,y+1).

[0029] Each unit U has photoelectric conversion units PD1 to PD8, a floating diffusion FD, transfer transistors M1 to M8, a reset transistor M9, an amplification transistor M10, and a selection transistor M11. In the unit U, the eight photoelectric conversion units PD1 to PD8 share one floating diffusion FD. Note that while a configuration in which one amplification transistor M10 is provided in one unit 250 has been shown here, a configuration in which multiple amplification transistors M10-1, M10-2, and M10-3 are provided may also be used, as shown in FIG. 3, and the number of amplification transistors is not limited.

[0030] Each of the photoelectric conversion units PD1 to PD8 is a photoelectric conversion element that photoelectrically converts incident light to generate and accumulate electric charges corresponding to the incident light. Each of the photoelectric conversion units PD1 to PD8 is, for example, a photodiode. The anode of the photodiode constituting each of the photoelectric conversion units PD1 to PD8 is connected to a node at ground potential. The cathode of the photodiode constituting each of the photoelectric conversion units PD1 to PD8 is connected to the source of the transfer transistor M1 to M8, respectively. Note that, although a configuration in which eight PD1 to PD8 share one FD is shown here, this is not limiting. One FD may be arranged to correspond to one PD1, or one FD may be arranged to correspond to four PD1 to PD4.

[0031] The drains of the transfer transistors M1 to M8 are connected to a floating diffusion FD, which is a connection node between the source of the reset transistor M9 and the gate of the amplification transistor M10. The drain of the reset transistor M9 and the drain of the amplification transistor M10 are electrically connected to a power supply line having a pixel power supply potential VCC. The source of the amplification transistor M10 is connected to the drain of the selection transistor M11. The source of the selection transistor M11 is electrically connected to a current source (not shown) via the vertical output line Vline(m). This allows the amplification transistor M10 and the current source to operate as a source follower circuit. In other words, the amplification transistor M10 functions as an output unit that can output a signal corresponding to the potential of the floating diffusion FD to the vertical output line Vline(m). The floating diffusion FD includes a capacitance component (floating diffusion capacitance), and this capacitance component allows it to function as a charge storage unit.

[0032] Control signals PTX1(n) to PTX8(n) are input to the gates of the transfer transistors M1 to M8, respectively, from the vertical scanning unit 3. The transfer transistors M1 to M8 transfer the charges accumulated in the photoelectric conversion units PD1 to PD8 to the floating diffusion FD based on the control signals PTX1(n) to PTX8(n), respectively. That is, each of the transfer transistors M1 to M8 functions as a charge transfer unit. The floating diffusion FD holds the transferred charges.

[0033] A control signal PRES(n) is input to the gate of the reset transistor M9 from the vertical scanning unit 3. The reset transistor M9 resets the potential of the floating diffusion FD to a predetermined potential based on the control signal PRES(n).

[0034] A control signal PSEL(n) is input to the gate of the selection transistor M11 from the vertical scanning unit 3. The control signal PSEL(n) is a signal that selects a row from which a signal is to be output, and the selection transistor M11 becomes conductive or non-conductive based on the control signal PSEL(n). The subscript n of each control signal indicates the row number of the corresponding row.

[0035] A transistor is assumed to be in a conductive state when the control signal input to its gate is high level, and in a non-conductive state when it is low level. Also, a high level corresponds to a logical value of "1" and a low level corresponds to a logical value of "0."

[0036] When the transfer transistors M1 to M8 are non-conductive, the photoelectric conversion units PD1 to PD8 are in an accumulation state in which they accumulate charges generated by photoelectric conversion. When the transfer transistors M1 to M8 are in an conductive state and the reset transistor M9 is in an conductive state, the photoelectric conversion units PD1 to PD8 are in a non-accumulation state in which no charges are accumulated, i.e., a reset state. When any of the transfer transistors M1 to M8 are in an conductive state and the reset transistor M9 is in an non-conductive state, the pixel P(m,n) is in a readout state in which the charges of the photoelectric conversion units PD1 to PD8 can be transferred to the floating diffusion FD and read out. Note that the resetting of the photoelectric conversion units PD1 to PD8 may be controlled by a charge discharging transistor configured to electrically connect the cathodes of the photoelectric conversion units PD1 to PD8 to a power supply line having a power supply potential.

[0037] In this embodiment, each transistor is an N-channel MOS transistor, but it may be a P-channel MOS transistor, in which case the level of each control signal may be changed as appropriate.

[0038] 4 is a block diagram showing the configuration of the control unit 2 according to this embodiment. The control unit 2 includes a synchronization signal generation unit 21, a vertical scanning control unit 23, a column circuit control unit 24, and a horizontal scanning control unit 25.

[0039] The synchronization signal generating section 21, under the control of the CPU 1, generates a vertical synchronization signal and a horizontal synchronization signal used to control the operation timing of each section for readout scanning and reset scanning.

[0040] The vertical scanning control unit 23 generates control signals for controlling the driving of the vertical scanning unit 3 and outputs them to the vertical scanning unit 3. The vertical scanning unit 3 outputs the control signals RES, SEL, and TX1 to TX8 in accordance with the control signals from the vertical scanning control unit 23. These control signals may be given a subscript indicating the row number. Hereinafter, the control signals output from the vertical scanning unit 3 will be collectively referred to as pixel drive pulses.

[0041] The column circuit control unit 24 generates a control signal for controlling the driving of the column circuit unit 5 and outputs it to the column circuit unit 5. The horizontal scanning control unit 25 generates a control signal for controlling the driving of the horizontal scanning unit 6 and outputs it to the horizontal scanning unit 6.

[0042] Next, the pixel drive pulses output from the vertical scanning unit 3 will be described with reference to Fig. 5. Fig. 5 is a timing chart of control signals output from the vertical scanning unit 3 according to this embodiment. Fig. 5 shows the timing of pixel drive pulses corresponding to three rows of pixels P, including the n-1th, nth, and n+1th rows. Note that the timing of the pixel drive pulses for the n-1th and n+1th rows is shifted in the time direction relative to the timing of the nth row, so the following description will focus on the pixel drive pulse for the nth row, and descriptions of the other rows will be omitted.

[0043] During the period before time t1, the control signal RES[n] and the control signals TX1[n] to TX8[n] are maintained at high level. As a result, the photoelectric conversion units PD1 to PD8 are maintained in a reset state. In addition, the control signal SEL[n] is maintained at low level, and the selection transistor M11 is in a non-conductive state.

[0044] At time t1, the control signals TX1[n] to TX8[n] transition to low level, thereby releasing the reset state of the photoelectric conversion units PD1 to PD8.

[0045] At time t2, the control signal TX1[n] transitions to high level, and the photoelectric conversion unit to which the control signal TX1[n] is input is temporarily reset. Then, at time t3, the control signal TX1[n] transitions to low level. These operations cause the photoelectric conversion unit to which the control signal TX1[n] is input to start accumulating charges.

[0046] At time t4, the control signal TX2[n] transitions to high level, and the photoelectric conversion unit to which the control signal TX2[n] is input is temporarily reset. Then, at time t5, the control signal TX2[n] transitions to low level. These operations cause the photoelectric conversion unit to which the control signal TX2[n] is input to start accumulating charges.

[0047] Similarly, during the period from time t6 to time t17, pulses of control signals TX3[n] to TX8[n] are output, and accumulation in each photoelectric conversion unit is started sequentially. A series of operations from time t2 to time t17 is called reset scanning of the nth row.

[0048] Furthermore, the length of the period from time t17, which is immediately after the reset scan of the nth row, to time t18, when the next operation starts, can be set appropriately. By adjusting the length of this period, it is possible to control the charge accumulation time in the photoelectric conversion units PD1 to PD8. The length of this period is set, for example, by a control signal from the CPU 1. Figure 5 shows a case where the length of the period from time t17 to time t18 is approximately the shortest.

[0049] At time t18, the control signal SEL[n] transitions to high level, turning on the selection transistor M11. This electrically connects the amplification transistor M10 of the pixel P(m,n) to the vertical output line Vline(m) via the selection transistor M11. This operation enables a signal based on the potential of the floating diffusion FD to be output to the vertical output line Vline(m) of the mth column.

[0050] Between time t18 and time t19, the control signal RES[n] transitions to low level, thereby releasing the reset state of the floating diffusion FD.

[0051] After the reset of the floating diffusion FD is released, at time t19, the control signal TX1[n] transitions to high level. This operation transfers the charge accumulated in the photoelectric conversion unit to which the control signal TX1[n] is input to the floating diffusion FD. Then, a signal corresponding to the potential of the floating diffusion FD is output to the vertical output line Vline(m) of the mth column. The signal output to the vertical output line Vline(m) is amplified and AD converted by the column circuit unit 5, and then stored in the column memory as a digital signal.

[0052] After that, at time t20, the control signal TX1[n] transitions to low level, completing the transfer operation of the charges accumulated in the photoelectric conversion unit. That is, the period from time t3 to time t20 corresponds to the charge accumulation period in the photoelectric conversion unit.

[0053] Between time t20 and time t21, the control signal RES[n] transitions to high level, and after a predetermined time, transitions to low level again. This operation resets the potential of the floating diffusion FD.

[0054] At time t21, the control signal TX2[n] transitions to high level, and a transfer operation similar to that at time t19 begins. After that, at time t22, the control signal TX2[n] transitions to low level, and the transfer operation of the charges accumulated in the photoelectric conversion unit is completed.

[0055] Similarly, during the period from time t23 to time t34, pulses of control signals TX3[n] to TX8[n] are output, and transfer operations from each photoelectric conversion unit to the floating diffusion FD are performed sequentially. The series of operations from time t19 to time t34 is called readout scanning of the nth row.

[0056] At time t35, the control signal SEL[n] transitions to low level, and the selection transistor M11 becomes non-conductive, thereby electrically disconnecting the amplification transistor M10 of the pixel P from the vertical output line Vline(m).

[0057] At time t36, the control signals TX1[n] to TX8[n] transition to high level. This resets the photoelectric conversion units PD1 to PD8. In this way, a series of operations from the start of charge accumulation in the unit U on the nth row to the end of readout scanning on the nth row is completed.

[0058] Here, the operation of reading out signal charges from PD1 to PD8 one by one by individually controlling the control signals TX1[n] to TX8[n] has been described, but the present invention is not limited to this operation. For example, when performing focus detection focusing on the vertical direction of the subject, signals may be simultaneously read out from adjacent PDs in the row direction. That is, the control signal TX1[n] and the control signal TX3[n] may be synchronized, and the control signal TX2[n] and the control signal TX4[n] may be synchronized. Furthermore, when performing focus detection focusing on the horizontal direction of the subject, the control signal TX1[n] and the control signal TX2[n] may be synchronized, and the control signal TX3[n] and the control signal TX4[n] may be synchronized.

[0059] FIG. 6 is a configuration diagram of a photoelectric conversion device of this embodiment. The photoelectric conversion device of this embodiment has a stacked sensor structure in which a first substrate SUB1 and a second substrate SUB2, which are semiconductor substrates, are stacked. The first substrate SUB1 is typically formed using single crystal silicon. The second substrate SUB2 may also be formed using single crystal silicon. However, this is not a limitation, and the first substrate SUB1 and the second substrate SUB2 may also be compound semiconductor substrates that combine multiple materials. In other words, the first substrate SUB1 and the second substrate SUB2 can each be a variety of semiconductor substrates.

[0060] Furthermore, the arrangement of the members shown in FIG. 1 on each of the first substrate SUB1 and the second substrate SUB2 can be changed as appropriate.

[0061] This embodiment is not limited to a stacked sensor, but may be a back-illuminated non-stacked sensor in which the second substrate SUB2 serves as a support substrate and all of the components shown in FIG.

[0062] The pixel array 4 shown in FIG. 1 is disposed on the first substrate SUB1. Meanwhile, the second substrate SUB2 is provided with the components of the configuration shown in FIG. 1 other than the pixel array 4. Electrical connection between the first substrate SUB1 and the second substrate SUB2 can be achieved using a known method. For example, a via structure having a metal portion penetrating the first substrate SUB1 may be provided, and this via structure may connect the wiring between the first substrate SUB1 and the bonding surface to the wiring between the second substrate SUB2 and the bonding surface. This connection method is sometimes called Through Silicon Via (TSV). As another form, an exposed metal junction is provided inside the insulating film on the bonding surface on the first substrate SUB1 side. This metal junction is connected to the wiring between the first substrate SUB1 and the bonding surface. Similarly, an exposed metal junction is provided inside the insulating film on the bonding surface on the second substrate SUB2 side. This metal junction is connected to the wiring between the second substrate SUB2 and the bonding surface. The metal bonding portions provided on the bonding surface on the first substrate SUB1 side and the bonding surface on the second substrate SUB2 side are bonded to each other, and the insulating films are bonded to each other. This allows electrical connection between the wiring between the first substrate SUB1 and the bonding surface and the wiring between the second substrate SUB2 and the bonding surface. This bonding method is sometimes called hybrid bonding.

[0063] 7 is a plan view relating to the structure of a pixel P of this embodiment. This plan view is a plan view of the first main surface, which is the main surface onto which light is incident, of the first substrate SUB1.

[0064] The pixel P has N-type semiconductor regions 11 to 14 provided in PD1 to PD4, respectively. PD1 shown in FIG. 3 has a semiconductor region 11. Similarly, PD2, PD3, and PD4 have semiconductor regions 12, 13, and 14, respectively. The pixel P also has a trench portion 22 as a first trench portion, which is an isolation portion within the pixel that electrically isolates the N-type semiconductor regions 11 to 14. In a plan view of the first main surface, the trench portion 22 has a plurality of first portions SEP1-1 and SEP1-2 extending in a first direction, which is the row direction, and a plurality of second portions SEP2-1 and SEP2-2 extending in a second direction, which is the column direction. The first and second directions intersect with each other. In the first main surface, a semiconductor region 23 provided in a first substrate SUB1, which is a semiconductor substrate, is provided in the first region between SEP1-1 and SEP1-2 and in the second region between SEP2-1 and SEP2-2. In this embodiment, the first region and the second region can be considered to be the same region. The first region is the region between one and the other of the multiple first portions SEP1-1 and SEP1-2. The second region is the region between one and the other of the multiple second portions SEP2-1 and SEP2-2.

[0065] In addition, in a plan view of the first main surface, a portion of a trench portion 22 provided inside the first substrate SUB1 is provided at a position overlapping with the semiconductor region 23. The semiconductor region 23 serves as a path for charge transfer from one of the multiple N-type semiconductor regions 11-14 to the other. As a result, even if a large amount of charge is generated inside some of the multiple N-type semiconductor regions 11-14 upon which high-intensity light is incident, the charge can be transferred to the other semiconductor regions 11-14. This allows the multiple semiconductor regions 11-14 to store charge corresponding to the incident light, thereby expanding the dynamic range on the high-intensity side. In particular, the dynamic range on the high-intensity side can be expanded while suppressing a decrease in the linearity of the output signal of the pixel P relative to the amount of incident light.

[0066] The conductivity type of the semiconductor region 23 is preferably the same as that of the semiconductor regions 11 to 14, since it is a path for the charges generated by the semiconductor regions 11 to 14 to move. A semiconductor region of a different conductivity type from the semiconductor regions 11 to 14 may be provided between the semiconductor region 23 and the trench portion 22. That is, in the conductivity type described in this embodiment, a P-type semiconductor region may be provided. This P-type semiconductor region serves to reduce the flow of dark current components generated by the trench portion 22 into the semiconductor regions 11 to 14.

[0067] Between the plurality of pixels P, trench portions 21 are provided as second trench portions that are separation portions between one pixel and the other pixel. In a plan view relative to the first main surface, trench portions 21 have a portion extending in a first direction, which is the row direction, and a portion extending in a second direction, which is the column direction. In a plan view relative to the first main surface, trench portions 21 extend across multiple rows and columns of pixels P.

[0068] Furthermore, a microlens ML is arranged at a position overlapping with the N-type semiconductor regions 11-14 arranged across two rows and two columns in one pixel P in a plan view relative to the first principal surface. The photoelectric conversion device has a microlens array in which the microlenses ML are arranged corresponding to each of the plurality of pixels P. Light transmitted through one microlens ML is incident on the four N-type semiconductor regions 11-14. With this configuration, signals based on the amount of light incident on each of the PDs 1-4 can be individually obtained by driving the PDs according to the timing chart shown in FIG. 5. Phase difference components in the row direction and phase difference components in the column direction can be obtained. This enables focus detection focusing on the vertical direction and horizontal direction of the subject to be performed.

[0069] Next, FIG. 8 shows a cross-sectional view corresponding to the position of line AA' shown in FIG.

[0070] Of the components shown in Figure 8, the same components as those shown in Figure 7 are assigned the same reference numerals as those in Figure 7. The first substrate SUB1 has a first main surface F1, which is the first main surface onto which light is incident, and a second main surface F2, which is the main surface opposite to the first main surface F1. An insulating film 31 is provided on the second main surface F2. A wiring layer 30 including wiring 32 is provided on the insulating film 31. Although not shown in Figure 8, the second main surface F2 is also the surface on which the gate electrodes of each transistor shown in Figure 3 are provided.

[0071] Between the first main surface F1 and the microlenses ML, color filters 52 and an insulating film 51 are provided. The optical layer 50 includes the microlenses ML, the color filters 52, and the insulating film 51.

[0072] In the cross-sectional view taken along line AA' in FIG. 7, both the trench portion 21 and the trench portion 22 extend in the depth direction of the first substrate SUB1, from one of the first main surface F1 and the second main surface F2 of the first substrate SUB1 to the other. Both the trench portion 21 and the trench portion 22 are in contact with an isolation portion 24 on the second main surface F2 side. The isolation portion 24 has a structure also known as shallow trench isolation (STI). This STI can be fabricated by a known manufacturing method. Then, an etching process is performed from the formed isolation portion 24 to form a hole extending to the first main surface F1. The trench portions 21 and 22 can be formed by filling this hole with an insulating material, a metal material, polysilicon, or the like. A pinning film, such as a single-layer film of an aluminum oxide film or a tantalum oxide film, or a laminated film combining multiple films, may be provided on the sidewalls of the trench portions 21 and 22. In this embodiment, the trench portion 21 and the trench portion 22 have a deep trench isolation (DTI) structure formed from the second main surface F2 toward the first main surface F1. In the cross section shown in FIG. 7, the trench portion 21 and the trench portion 22 are formed with the same width W1. While FIG. 7 shows the trench portions 21 and 22 extending from the second main surface F2 to the first main surface F1 with the same width, this configuration is not limiting. The trench portions 21 and 22 may be formed to become thinner toward the first main surface F1. The length L1 of the semiconductor region 23 along the first direction is preferably equal to or less than half the length L2 of the pixel P along the first direction. For example, if the length L2 of the pixel P is 1 μm, the length L1 of the semiconductor region 23 along the first direction is set to 0.5 μm or less. This makes it possible to achieve at least one of electrical isolation and optical isolation between PD1 to PD4, and efficiency in charge transfer to other PDs when some of PD1 to PD4 are saturated.

[0073] Next, Fig. 9 shows a cross-sectional view taken along line BB' in Fig. 7. Of the components shown in Fig. 9, the same components as those shown in Figs. 7 and 8 are denoted by the same reference numerals as those in Figs. 7 and 8.

[0074] 8, the bottom of trench portion 22 contacts semiconductor region 23. That is, the bottom of trench portion 22 is located at a depth between second main surface F2 and first main surface F1. Trench portion 22 has a width W2 that is smaller than width W1 of trench portion 21. By reducing the width of trench portion 22, the etching rate when etching the semiconductor substrate to form trench portion 22 can be reduced.

[0075] Next, Fig. 10 shows a cross-sectional view taken along line CC' in Fig. 7. Of the components shown in Fig. 10, the same components as those shown in Figs. 7, 8, and 9 are denoted by the same reference numerals as those in Figs. 7, 8, and 9.

[0076] In Fig. 10, a semiconductor region 23 is formed at a position between SEP1-1 and SEP1-2 shown in Fig. 7. A trench portion 22 is provided between this semiconductor region 23 and the second main surface F2.

[0077] Next, Fig. 11 shows a cross-sectional view taken along line DD' in Fig. 7. Of the components shown in Fig. 11, the same components as those shown in Figs. 7 to 10 are denoted by the same reference numerals as those in Figs. 7 to 10.

[0078] The depth DP1 of the semiconductor region 23 is preferably equal to or less than half the length DP2 between the first principal surface F1 and the second principal surface F2. For example, when DP2 is 3 μm, DP1 is preferably equal to or less than 1.5 μm. This makes it possible to achieve at least one of electrical isolation and optical isolation between PD1 to PD4 and the efficiency of charge transfer to other PDs when some of PD1 to PD4 are saturated.

[0079] 11, the trench portion 21 extends across a plurality of pixels P. The trench portion 21 extends in the depth direction from one of the first main surface F1 and the second main surface F2 to the other.

[0080] In the structure shown in this embodiment, in a plan view of the first main surface F1, the semiconductor region 23 is formed in the region between SEP1-1 and SEP1-2, which are part of the trench portion 22, and between SEP2-1 and SEP2-2. This makes it possible to expand the dynamic range on the high-luminance side, as described above. In particular, it is possible to expand the dynamic range on the high-luminance side while suppressing a decrease in the linearity of the output signal of the pixel P relative to the amount of incident light.

[0081] (Second embodiment) The present embodiment will be described, focusing on the differences from the first embodiment.

[0082] FIG. 12 shows a plan view of the first main surface F1 of the photoelectric conversion device of this embodiment. In the first embodiment, the semiconductor region 23 was provided at a position overlapping the center portion of the microlens ML in a planar view. From another perspective, in the first embodiment, one semiconductor region 23 was connected to all of the semiconductor regions 11 to 14 arranged in two rows and two columns. In this embodiment, a plurality of semiconductor regions 23 are provided in one pixel P. In the example shown in FIG. 12, a semiconductor region 23 is provided that connects two of the N-type semiconductor regions 11 to 14.

[0083] Trench portion 22 has SEP3-1, SEP3-2, SEP3-3, and SEP3-4 in the first direction. Trench portion 22 also has SEP4-1, SEP4-2, SEP4-3, and SEP4-4 in the second direction. Semiconductor regions 23 are provided in a first region between SEP3-1 and SEP3-2, a second region between SEP3-3 and SEP3-4, a third region between SEP4-1 and SEP4-2, and a fourth region between SEP4-3 and SEP4-4.

[0084] Figure 13 shows a cross-sectional view taken along line C1-C2 in Figure 12. Of the components shown in Figure 13, the same components as those shown in Figures 7 to 10 are denoted by the same reference numerals as those in Figures 7 to 10. As shown in Figure 13, by providing multiple semiconductor regions 23, the directionality of the movement of charges generated in the multiple N-type semiconductor regions 11 to 14 can be improved.

[0085] (Third embodiment) The present embodiment will be described focusing on the differences from the first embodiment. In the first embodiment, the trench portions 21 and 22 were formed in the direction from the second main surface F2 to the first main surface F1. In this embodiment, the trench portions 21 and 22 are formed in the direction from the first main surface F1 to the second main surface F2. Furthermore, while the semiconductor region 23 was provided on the first main surface F1 in the first embodiment, in this embodiment it is provided on the second main surface F2. Note that in this embodiment as well, photodiodes PD1 to PD4 are arranged in two rows and two columns for one microlens.

[0086] Fig. 14 is a plan view showing the structure of the photovoltaic device of this embodiment as viewed from the second main surface F2. Of the components shown in Fig. 14, the same components as those shown in Fig. 7 are denoted by the same reference numerals as those in Fig. 7.

[0087] In the second main surface F2, trench portion 22 has portions SEP5-1 and SEP5-2 extending in a first direction, which is the row direction, and portions SEP6-1 and SEP6-2 extending in a second direction, which is the column direction, in a plan view of second main surface F2. In the second main surface F2, a semiconductor region 23 provided in first substrate SUB1, which is a semiconductor substrate, is provided in the region between SEP5-1 and SEP5-2, which is the region between SEP6-1 and SEP6-2. Note that, in a plan view of second main surface F2, a portion of trench portion 22 provided inside first substrate SUB1 is provided at a position overlapping with this semiconductor region 23. Semiconductor region 23 provides a path for charge to move from one of multiple N-type semiconductor regions 11 to 14 to the other. As a result, even if a large amount of charge is generated in some of the multiple N-type semiconductor regions 11-14 that are exposed to high-intensity light, the charge can be transferred to the other semiconductor regions 11-14. As a result, the multiple semiconductor regions 11-14 can be used to store charge corresponding to the incident light, thereby expanding the dynamic range on the high-intensity side. In particular, the dynamic range on the high-intensity side can be expanded while suppressing a decrease in the linearity of the output signal of the pixel P relative to the amount of incident light.

[0088] Next, FIG. 15 shows a cross-sectional view corresponding to the position of line AA' shown in FIG.

[0089] Of the components shown in FIG. 15, the same components as those shown in FIG. 14 are denoted by the same reference numerals as those in FIG.

[0090] In the cross-sectional view taken along line AA' in FIG. 15, the trench portions 21 and 22 both extend in the depth direction of the first substrate SUB1, from one of the first main surface F1 and the second main surface F2 of the first substrate SUB1 to the other. After forming the wiring layer 30 and before forming the optical layer 50, an etching process is performed from the first main surface F1 toward the second main surface F2 to form holes extending to the depth of the second main surface F2. The trench portions 21 and 22 can then be formed by filling these holes with an insulating material or a metal material. In this embodiment, the trench portions 21 and 22 have a deep trench isolation (DTI) structure formed from the first main surface F1 toward the second main surface F2. In the cross-section shown in FIG. 15, the trench portions 21 and 22 have the same width W1. 15, the trench portions 21 and 22 extend with the same width from the first main surface F1 to the second main surface F2, but this is not limiting. The trench portions 21 and 22 can be formed to become thinner as they approach the second main surface F2.

[0091] Next, Fig. 16 shows a cross-sectional view taken along line BB' in Fig. 14. Of the components shown in Fig. 16, the same components as those shown in Figs. 14 and 15 are denoted by the same reference numerals as those in Figs. 14 and 15.

[0092] In the cross-sectional view shown in Figure 16, the bottom of trench portion 22 contacts semiconductor region 23. In other words, the bottom of trench portion 22 is located at a depth between second main surface F2 and first main surface F1. Trench portion 22 has a width W2 that is smaller than width W1 of trench portion 21. Note that, although widths W1 and W2 are shown at different depths in Figure 16 for convenience of illustration, it is preferable to compare them at the same depth.

[0093] Next, Fig. 17 shows a cross-sectional view taken along line CC' in Fig. 14. Of the components shown in Fig. 17, the same components as those shown in Figs. 14 to 16 are denoted by the same reference numerals as those in Figs. 14 to 16.

[0094] In Fig. 17, a semiconductor region 23 is formed at a position between SEP5-1 and SEP5-2 shown in Fig. 14. A trench portion 22 is provided between this semiconductor region 23 and the first main surface F1.

[0095] The depth DP3 of the semiconductor region 23 is preferably equal to or less than half the length DP2 between the first principal surface F1 and the second principal surface F2. For example, when DP3 is 3 μm, DP2 is preferably equal to or less than 1.5 μm. This makes it possible to achieve at least one of electrical isolation and optical isolation between PD1 to PD4 and the efficiency of charge transfer to other PDs when some of PD1 to PD4 are saturated.

[0096] Next, Fig. 18 shows a cross-sectional view taken along line DD' in Fig. 14. Of the components shown in Fig. 14, the same components as those shown in Figs. 14 to 17 are denoted by the same reference numerals as those used in Figs. 7 to 10.

[0097] 18, the trench portion 21 extends across a plurality of pixels P. The trench portion 21 extends in the depth direction from one of the first main surface F1 and the second main surface F2 to the other.

[0098] In the structure shown in this embodiment, in a plan view of the second main surface F2, the semiconductor region 23 is formed in the region between SEP5-1 and SEP5-2, which are part of the trench portion 22, and between SEP6-1 and SEP6-2. This makes it possible to expand the dynamic range on the high-luminance side, as described above. In particular, it is possible to expand the dynamic range on the high-luminance side while suppressing a decrease in the linearity of the output signal of the pixel P relative to the amount of incident light.

[0099] (Fourth embodiment) The photoelectric conversion device of this embodiment will be described, focusing on the differences from the third embodiment.

[0100] Fig. 19 shows a plan view of the second main surface F2 of the photoelectric conversion device of this embodiment. In the third embodiment, one semiconductor region 23 was connected to all of the semiconductor regions 11 to 14 arranged in two rows and two columns. In this embodiment, a plurality of semiconductor regions 23 are provided in one pixel P. In the example shown in Fig. 19, a semiconductor region 23 is provided that connects two of the N-type semiconductor regions 11 to 14.

[0101] Trench portion 22 has SEP6-1, SEP6-2, SEP6-3, and SEP6-4 in the first direction. Trench portion 22 also has SEP7-1, SEP7-2, SEP7-3, and SEP7-4 in the second direction. Semiconductor regions 23 are provided in each of the region between SEP6-1 and SEP6-2, the region between SEP6-3 and SEP6-4, the region between SEP7-1 and SEP7-2, and the region between SEP7-3 and SEP7-4.

[0102] Figure 20 shows a cross-sectional view taken along line C3-C4 in Figure 19. Of the components shown in Figure 20, the same components as those shown in Figures 16 to 19 are denoted by the same reference numerals as those in Figures 16 to 19. As shown in Figure 20, by providing multiple semiconductor regions 23, the directionality of the movement of charges generated in the multiple N-type semiconductor regions 11 to 14 can be improved.

[0103] (Fifth embodiment) The photoelectric conversion device of this embodiment will be described, focusing on the differences from the third embodiment.

[0104] In the photovoltaic conversion device of this embodiment, each of the trench portions 21 and 22 includes a portion extending from the first main surface F1 and a portion extending from the second main surface F2.

[0105] 21(a) and 21(b) show a photoelectric conversion device of this embodiment, with (a) being a plan view seen from the second main surface F2 and (b) being a plan view seen from the first main surface F1. Of the components shown in FIGS. 21(a) and 21(b), components having the same functions as those shown in the previous embodiment are assigned the same reference numerals as in the previous embodiment. In the photoelectric conversion device of this embodiment, trench portions 21a are provided in a lattice pattern on the second main surface F2. Trench portions 21b are provided in a lattice pattern on the first main surface F1.

[0106] 22 is a plan view of a plane (a plane parallel to the first and second main surfaces F1 and F2) at a depth position between the second main surface F2 and the first main surface F1. This depth position corresponds to a depth D1 shown in FIGS. 23 to 25, which will be described later.

[0107] In a plan view of the first main surface, the trench portion 22a has portions SEP8-1 and SEP8-2 extending in a first direction, which is the row direction, and portions SEP9-1 and SEP9-2 extending in a second direction, which is the column direction. In the region between SEP8-1 and SEP8-2 on the first main surface, a semiconductor region 23 provided in the first substrate SUB1, which is a semiconductor substrate, is provided. Note that, in a plan view of the first main surface, a portion of the trench portion 22a provided inside the first substrate SUB1 is provided at a position overlapping with the semiconductor region 23. The semiconductor region 23 serves as a path for charge transfer from one of the multiple N-type semiconductor regions 11-14 to the other. This allows charge transfer to the other semiconductor regions 11-14, even if a large amount of charge is generated in some of the multiple N-type semiconductor regions 11-14 that are exposed to high-intensity light. This allows charges corresponding to incident light to be accumulated using the semiconductor regions 11 to 14, thereby expanding the dynamic range on the high-luminance side. In particular, the dynamic range on the high-luminance side can be expanded while suppressing a decrease in the linearity of the output signal of the pixel P relative to the amount of incident light.

[0108] FIG. 23 is a cross-sectional view taken along line A-A' in FIGS. 21 and 22. The trench portion 21 includes a trench portion 21a extending from the second main surface F2 toward the first main surface F1 and a trench portion 21b extending from the first main surface F1 toward the second main surface F2. The trench portion 21a and the trench portion 21b are in contact with each other inside the first substrate SUB1. The depthwise extension lengths of the trench portion 21a and the trench portion 21b can be appropriately set according to the respective process conditions. Typically, the respective lengths can be M / 2, where M is the depthwise length from the first main surface F1 to the second main surface F2. Note that while FIG. 23 illustrates the trench portion 21a and the trench portion 21b as being in contact with each other at their bottom surfaces, this is not a limitation. For example, when trench portion 21b is formed, a structure (metal, insulating material, polysilicon, etc.) inside trench portion 21a may function as an etching stopper, so that the bottom surface of trench portion 21b is located inside trench portion 21a. In this way, contact between trench portion 21a and trench portion 21b allows at least one of electrical isolation and optical isolation between multiple pixels P to be appropriately achieved.

[0109] The trench portion 22 includes a trench portion 22a extending from the second main surface F2 toward the first main surface F1 and a trench portion 22b extending from the first main surface F1 toward the second main surface F2. The trench portion 22a and the trench portion 22b are adjacent to each other inside the first substrate SUB1. The depth lengths of the trench portions 22a and 22b can be appropriately set depending on the process conditions. Typically, the trench portions 22a and 22b can be set to M / 2, where M is the depth length from the first main surface F1 to the second main surface F2. Note that while FIG. 23 illustrates the trench portions 22a and 22b as having their bottom surfaces adjacent to each other, this is not a limitation. For example, during the formation of the trench portion 22b, a structure (such as a metal, insulating material, or polysilicon) inside the trench portion 22a may function as an etching stopper, so that the bottom surface of the trench portion 22b is located inside the trench portion 22a. In this way, by the trench portion 22a and the trench portion 22b being in contact with each other, at least one of electrical isolation and optical isolation between the PD1 to PD4 included in one pixel P can be appropriately achieved.

[0110] Furthermore, the width W6 of trench portion 21a is wider than the width W5 of trench portion 21b. While trench portions 21a and 22a have the same width W6, this is not intended to be limiting and may be different. Furthermore, trench portions 21b and 22b have the same width W5, this is not intended to be limiting and may be different.

[0111] FIG. 24 is a cross-sectional view taken along line BB' in FIGS. 21 and 22. Trench portion 22a extends to a position shallower than depth position D1 when viewed from second main surface F2. The bottom surface of trench portion 22a contacts semiconductor region 23. The bottom surface of trench portion 22b contacts semiconductor region 23. In other words, trench portion 22a and trench portion 22b do not contact each other. Furthermore, width W7 of trench portion 22a is smaller than width W6 of trench portion 21a. Furthermore, width W8 of trench portion 22b is smaller than width W5 of trench portion 21b. The relationship between widths W5 to W8 in this embodiment is as follows: W6>W5>W7>W8···(1)

[0112] The relationship is not limited to that of formula (1), but it is sufficient if the relationships W6>W7 and W5>W8 are satisfied. W6=W5>W7=W8 (2) W5>W6>W7=W8 (3) W5>W6>W8>W7···(4) The relationship may be any of the relationships expressed by equations (2) to (4). In Fig. 24, widths W6 and W7 are shown at different depth positions for convenience of illustration, but it is preferable to compare them at the same depth position. Similarly, widths W5 and W8 are shown at different depth positions for convenience of illustration, but it is preferable to compare them at the same depth position.

[0113] 21(a), 21(b), and 24, in the first main surface F1, the first trench portion 22 has a trench portion 22b, which is a first portion extending in a first direction, in a plan view relative to the first main surface F1. In addition, in the second main surface F2, the first trench portion 22 has a trench portion 22a, which is a third portion extending in the first direction, in a plan view relative to the second main surface F2. The trench portions 22a and 22b have overlapping portions in a plan view relative to the first main surface F1. A semiconductor region 23 included in the first substrate SUB1 is provided between the trench portions 22a and 22b.

[0114] 25 is a cross-sectional view taken along line CC' in FIGS. 21 and 22. In this cross-sectional view, semiconductor region 23 is disposed in a region surrounded by trench portions 22a and 22b. Also, a portion of semiconductor region 23 is disposed between SEP8-1 and SEP8-2 shown in FIG. 21. With this structure, when some of PD1 to PD4 are saturated, charge can be transferred to some of the other PDs.

[0115] The depth DP4 of the semiconductor region 23 is preferably equal to or less than half the length DP2 between the first principal surface F1 and the second principal surface F2. For example, when DP3 is 3 μm, DP4 is preferably equal to or less than 1.5 μm. This makes it possible to achieve at least one of electrical isolation and optical isolation between PD1 to PD4 and the efficiency of charge transfer to other PDs when some of PD1 to PD4 are saturated.

[0116] 21 and 22. Trench portion 21a and trench portion 21b are adjacent to each other and extend across multiple pixels P. This allows the photoelectric conversion units of the multiple pixels P to be electrically isolated from each other.

[0117] In this embodiment, the dynamic range on the high-luminance side can also be expanded, particularly while suppressing a decrease in the linearity of the output signal of pixel P relative to the amount of incident light.

[0118] This embodiment can also be modified into the structure shown in FIG. 27. FIG. 27 is a plan view of the semiconductor region 23 of this embodiment, viewed from above with respect to a plane at depth D1 (a plane parallel to the first main surface F1 and the second main surface F2). In this modification, the semiconductor region 23 of this embodiment is modified into a configuration in which a plurality of semiconductor regions 23 are arranged, as in the second and fourth embodiments. This configuration allows the directionality of the charge movement in the semiconductor regions 11 to 14 to be imparted.

[0119] (Sixth embodiment) This embodiment can be applied to any of the first to fifth embodiments. FIG. 28(a) is a schematic diagram illustrating a device 9191 including a semiconductor device 930 of this embodiment. The photoelectric conversion device (imaging device) of each of the above-described embodiments can be used as the semiconductor device 930. The device 9191 including the semiconductor device 930 will be described in detail. The semiconductor device 930 can include a semiconductor device 910. The semiconductor device 930 can include, in addition to the semiconductor device 910, a package 920 that houses the semiconductor device 910. The package 920 can include a base to which the semiconductor device 910 is fixed and a lid such as glass that faces the semiconductor device 910. The package 920 can further include bonding members such as bonding wires and bumps that connect terminals provided on the base to terminals provided on the semiconductor device 910.

[0120] The equipment 9191 can include at least one of an optical device 940, a control device 950, a processing device 960, a display device 970, a storage device 980, and a mechanical device 990. The optical device 940 corresponds to the semiconductor device 930. The optical device 940 is, for example, a lens, a shutter, or a mirror, and includes an optical system that guides light to the semiconductor device 930. The control device 950 controls the semiconductor device 930. The control device 950 is, for example, a semiconductor device such as an ASIC.

[0121] The processing device 960 processes the signal output from the semiconductor device 930. The processing device 960 is a semiconductor device such as a CPU or ASIC for configuring an AFE (analog front end) or a DFE (digital front end). The display device 970 is an EL display device or a liquid crystal display device that displays information (images) obtained by the semiconductor device 930. The storage device 980 is a magnetic device or a semiconductor device that stores information (images) obtained by the semiconductor device 930. The storage device 980 is a volatile memory such as an SRAM or a DRAM, or a non-volatile memory such as a flash memory or a hard disk drive.

[0122] The mechanical device 990 has a moving part or a propulsion part such as a motor or an engine. In the device 9191, the signal output from the semiconductor device 930 is displayed on the display device 970, or transmitted to the outside by a communication device (not shown) provided in the device 9191. For this purpose, the device 9191 preferably further includes a memory device 980 and a processing device 960 in addition to the memory circuit and arithmetic circuit provided in the semiconductor device 930. The mechanical device 990 may be controlled based on the signal output from the semiconductor device 930.

[0123] The device 9191 is also suitable for electronic devices such as information terminals with a photographing function (for example, smartphones and wearable devices) and cameras (for example, interchangeable lens cameras, compact cameras, video cameras, and surveillance cameras). The mechanical device 990 in the camera can drive components of the optical device 940 for zooming, focusing, and shutter operation. Alternatively, the mechanical device 990 in the camera can move the semiconductor device 930 for vibration isolation operations.

[0124] Furthermore, the device 9191 may be transportation equipment such as a vehicle, a ship, or an aircraft (drone, aircraft, etc.). The mechanical device 990 in transportation equipment can be used as a moving device. The device 9191 as transportation equipment is suitable for transporting the semiconductor device 930 or for assisting and / or automating driving (piloting) using a photographing function. The processing device 960 for assisting and / or automating driving (piloting) can perform processing for operating the mechanical device 990 as a moving device based on information obtained by the semiconductor device 930. Alternatively, the device 9191 may be a medical device such as an endoscope, a measuring device such as a distance measuring sensor, an analytical device such as an electron microscope, an office machine such as a copier, or an industrial device such as a robot.

[0125] According to the above-described embodiment, it is possible to obtain good pixel characteristics. Therefore, the value of the semiconductor device can be increased. In this case, increasing the value corresponds to at least one of adding functions, improving performance, improving characteristics, improving reliability, improving manufacturing yield, reducing environmental impact, reducing costs, reducing size, and reducing weight.

[0126] Therefore, if the semiconductor device 930 according to this embodiment is used in the equipment 9191, the value of the equipment can also be improved. For example, by installing the semiconductor device 930 in a transport equipment, excellent performance can be obtained when photographing the exterior of the transport equipment or measuring the external environment. Therefore, when manufacturing and selling transport equipment, deciding to install the semiconductor device according to this embodiment in the transport equipment is advantageous in terms of improving the performance of the transport equipment itself. In particular, the semiconductor device 930 is suitable for transport equipment that performs driving assistance and / or automatic driving of the transport equipment using information obtained by the semiconductor device.

[0127] The photoelectric conversion system and the moving object of this embodiment will be described with reference to FIGS. 28(b) and 28(c).

[0128] FIG. 28(b) shows an example of a photoelectric conversion system related to an in-vehicle camera. The photoelectric conversion system S8 includes a photoelectric conversion device 80. The photoelectric conversion device 80 is the photoelectric conversion device (imaging device) described in any of the above embodiments. The photoelectric conversion system S8 includes an image processing unit 801 that performs image processing on multiple pieces of image data acquired by the photoelectric conversion device 80, and a parallax acquisition unit 802 that calculates parallax (phase difference of parallax images) from the multiple pieces of image data acquired by the photoelectric conversion system S8. Here, the photoelectric conversion system S8 may include an optical system (not shown) that guides light to the photoelectric conversion device 80, such as a lens, shutter, or mirror. Furthermore, multiple photoelectric conversion units that are approximately conjugate with the pupil of the optical system may be arranged in pixels of the photoelectric conversion device 80. For example, multiple photoelectric conversion units that are approximately conjugate with the pupil are arranged corresponding to one microlens. The photoelectric conversion units receive light beams that have passed through different positions of the pupil of the optical system, and the photoelectric conversion device 80 outputs image data corresponding to the light beams that have passed through the different positions. The parallax acquisition unit 802 may then calculate parallax using the output image data. The photoelectric conversion system S8 also includes a distance acquisition unit 803 that calculates the distance to an object based on the calculated parallax, and a collision determination unit 804 that determines whether or not there is a possibility of a collision based on the calculated distance. Here, the parallax acquisition unit 802 and the distance acquisition unit 803 are examples of distance information acquisition means that acquire information about the distance to the object. The distance information includes information about the parallax, the defocus amount, the distance to the object, and the like. The collision determination unit 804 may use any of this distance information to determine the possibility of a collision. The distance information may be acquired using ToF (Time of Flight). The distance information acquisition means may be implemented by dedicated hardware or a software module. Furthermore, it may be realized by an FPGA (Field Programmable Gate Array), an ASIC (Application Specific Integrated Circuit), or a combination thereof. The photoelectric conversion system S8 is connected to a vehicle information acquisition device 810 and can acquire vehicle information such as vehicle speed, yaw rate, and steering angle.The photoelectric conversion system S8 is also connected to a control ECU 820, which is a control device that outputs a control signal to generate a braking force to the vehicle based on the determination result of the collision determination unit 804. The photoelectric conversion system S8 is also connected to an alarm device 830 that issues an alarm to the driver based on the determination result of the collision determination unit 804. For example, if the determination result of the collision determination unit 804 indicates a high possibility of a collision, the control ECU 820 performs vehicle control to avoid the collision and mitigate damage by applying the brakes, releasing the accelerator, suppressing engine output, etc. The alarm device 830 warns the user by sounding an alarm or the like, displaying alarm information on the screen of a car navigation system or the like, vibrating the seat belt or steering wheel, etc.

[0129] In this embodiment, the photoelectric conversion system S8 captures images of the surroundings of the vehicle, for example, the front or rear. Fig. 28(c) shows the photoelectric conversion system S8 when capturing an image of the area in front of the vehicle (imaging range 850). The vehicle information acquisition device 810 sends instructions to the photoelectric conversion system S8 or the photoelectric conversion device 80. This configuration can further improve the accuracy of distance measurement.

[0130] While the above describes an example of control to prevent collisions with other vehicles, the present invention can also be applied to other applications, such as automatic driving control to follow other vehicles and automatic driving control to prevent vehicles from drifting out of their lanes. Furthermore, the photoelectric conversion system S8 can be applied not only to automobiles and other vehicles, but also to moving bodies (mobile devices) such as ships, aircraft, and industrial robots. The moving body includes one or both of a driving force generating unit that generates a driving force primarily used to move the moving body and a rotating body primarily used to move the moving body. The driving force generating unit can be an engine, a motor, or the like. The rotating body can be a tire, a wheel, a ship's screw, an aircraft's propeller, or the like. In addition to moving bodies, the present invention can be applied to a wide range of devices that use object recognition, such as intelligent transport systems (ITS).

[0131] [Modified embodiment] The present invention is not limited to the above-described embodiment, and various modifications are possible.

[0132] For example, an example in which part of the configuration of any one of the embodiments is added to another embodiment, or an example in which part of the configuration of another embodiment is replaced with another embodiment, is also included in the embodiments of the present invention.

[0133] Furthermore, the equipment and photoelectric conversion system shown in the sixth embodiment are examples of photoelectric conversion systems to which the photoelectric conversion device can be applied, and the photoelectric conversion system to which the photoelectric conversion device of the present invention can be applied is not limited to the configurations shown in Figures 13 and 14.

[0134] It should be noted that the above-described embodiments are merely examples of specific embodiments for carrying out the present invention, and the technical scope of the present invention should not be construed as being limited by these embodiments. In other words, the present invention can be carried out in various forms without departing from its technical concept or main features.

[0135] As used herein, expressions such as "A or B," "at least one of A and B," "at least one of A or / and B," "one or more of A or / and B," and the like, include all possible combinations of the listed items unless expressly defined otherwise. That is, the above expressions are understood to disclose all cases, including cases containing at least one A, cases containing at least one B, and cases containing both at least one A and at least one B. This applies equally to combinations of three or more elements.

[0136] The above-described embodiments can be modified as appropriate without departing from the spirit of the present invention. The disclosure of this specification includes not only what is described herein but also all matters that can be understood from the specification and the accompanying drawings. The disclosure of this specification also includes the complement of the concepts described herein. In other words, if the specification contains a statement that "A is greater than B," even if the statement that "A is not greater than B" is omitted, the specification can still be said to disclose that "A is not greater than B." This is because the statement that "A is greater than B" presupposes that the case in which "A is not greater than B" is taken into consideration.

[0137] The present disclosure includes the following configurations.

[0138] (Configuration 1) a semiconductor substrate having a first main surface onto which light is incident and a second main surface opposite to the first main surface; a microlens array having a plurality of microlenses; a plurality of pixels each including a corresponding one of a plurality of microlenses, a plurality of photoelectric conversion units arranged in a plurality of rows and a plurality of columns corresponding to the one microlens and disposed inside the semiconductor substrate, and a first trench portion separating the plurality of photoelectric conversion units; a second trench portion provided between a photoelectric conversion portion included in one of two adjacent pixels among the plurality of pixels and a photoelectric conversion portion included in the other of the two adjacent pixels; In the first main surface, in a plan view with respect to the first main surface, the first trench portion has a plurality of first portions extending in a first direction and a plurality of second portions extending in a second direction intersecting the first direction, a first region between one and another of the plurality of first portions and a second region between one and another of the plurality of second portions each have a semiconductor region included in the semiconductor substrate; a photoelectric conversion device characterized in that a portion of the first trench portion is arranged at a depth position between the first main surface and the second main surface, at a position overlapping the first region and a position overlapping the second region in the planar view.

[0139] (Configuration 2) a semiconductor substrate having a first main surface onto which light is incident and a second main surface opposite to the first main surface; a microlens array having a plurality of microlenses; a plurality of pixels each including a corresponding one of a plurality of microlenses, a plurality of photoelectric conversion units arranged in a plurality of rows and a plurality of columns corresponding to the one microlens and disposed inside the semiconductor substrate, and a first trench portion separating the plurality of photoelectric conversion units; a second trench portion provided between a photoelectric conversion portion included in one of two adjacent pixels among the plurality of pixels and a photoelectric conversion portion included in the other of the two adjacent pixels; In the second main surface, in a plan view with respect to the second main surface, the first trench portion has a plurality of first portions extending in a first direction and a plurality of second portions extending in a second direction intersecting the first direction, a first region between one and another of the plurality of first portions and a second region between one and another of the plurality of second portions each have a semiconductor region included in the semiconductor substrate; a photoelectric conversion device characterized in that a portion of the first trench portion is arranged at a depth position between the first main surface and the second main surface, at a position overlapping the first region and a position overlapping the second region in the planar view.

[0140] (Configuration 3) a semiconductor substrate having a first main surface onto which light is incident and a second main surface opposite to the first main surface; a microlens array having a plurality of microlenses; a plurality of pixels each including a corresponding one of a plurality of microlenses, a plurality of photoelectric conversion units arranged in a plurality of rows and a plurality of columns corresponding to the one microlens and disposed inside the semiconductor substrate, and a first trench portion separating the plurality of photoelectric conversion units; a second trench portion provided between a photoelectric conversion portion included in one of two adjacent pixels among the plurality of pixels and a photoelectric conversion portion included in the other of the two adjacent pixels; In the first main surface, the first trench portion has a first portion extending in a first direction in a plan view with respect to the first main surface, In the second main surface, the first trench portion has a third portion extending in a first direction in a plan view with respect to the second main surface, the first portion and the third portion have a portion that overlaps with each other in a plan view with respect to the first main surface, The photoelectric conversion device, wherein a semiconductor region included in the semiconductor substrate is disposed between the first portion and the third portion.

[0141] (Configuration 4) An apparatus including the semiconductor device according to any one of configurations 1 to 3, an optical device corresponding to the semiconductor device; a control device for controlling the semiconductor device; a processing device that processes a signal output from the semiconductor device; a display device that displays information obtained by the semiconductor device; a storage device that stores information obtained by the semiconductor device; and and a mechanical device that operates based on information obtained by the semiconductor device. [Explanation of symbols]

[0142] 11, 12, 13, 14 Semiconductor area 21, 22 Trench section 23 Semiconductors SUB1 Semiconductor substrate F1 First main surface F2 Second principal surface ML Micro Lens

Claims

1. a semiconductor substrate having a first main surface onto which light is incident and a second main surface opposite to the first main surface; a microlens array having a plurality of microlenses; a plurality of pixels each including a corresponding one of a plurality of microlenses, a plurality of photoelectric conversion units arranged in a plurality of rows and a plurality of columns corresponding to the one microlens and disposed inside the semiconductor substrate, and a first trench portion separating the plurality of photoelectric conversion units; a second trench portion provided between a photoelectric conversion portion included in one of two adjacent pixels among the plurality of pixels and a photoelectric conversion portion included in the other of the two adjacent pixels; In the first main surface, in a plan view with respect to the first main surface, the first trench portion has a plurality of first portions extending in a first direction and a plurality of second portions extending in a second direction intersecting the first direction, a first region between one and another of the plurality of first portions and a second region between one and another of the plurality of second portions each have a semiconductor region included in the semiconductor substrate, a photoelectric conversion device characterized in that a portion of the first trench portion is arranged at a depth position between the first main surface and the second main surface, at a position overlapping the first region and a position overlapping the second region in the planar view.

2. a semiconductor substrate having a first main surface onto which light is incident and a second main surface opposite to the first main surface; a microlens array having a plurality of microlenses; a plurality of pixels each including a corresponding one of a plurality of microlenses, a plurality of photoelectric conversion units arranged in a plurality of rows and a plurality of columns corresponding to the one microlens and disposed inside the semiconductor substrate, and a first trench portion separating the plurality of photoelectric conversion units; a second trench portion provided between a photoelectric conversion portion included in one of two adjacent pixels among the plurality of pixels and a photoelectric conversion portion included in the other of the two adjacent pixels; In the second main surface, in a plan view with respect to the second main surface, the first trench portion has a plurality of first portions extending in a first direction and a plurality of second portions extending in a second direction intersecting the first direction, a first region between one and another of the plurality of first portions and a second region between one and another of the plurality of second portions each have a semiconductor region included in the semiconductor substrate, a photoelectric conversion device characterized in that a portion of the first trench portion is arranged at a depth position between the first main surface and the second main surface, at a position overlapping the first region and a position overlapping the second region in the planar view.

3. a semiconductor substrate having a first main surface onto which light is incident and a second main surface opposite to the first main surface; a microlens array having a plurality of microlenses; a plurality of pixels each including a corresponding one of a plurality of microlenses, a plurality of photoelectric conversion units arranged in a plurality of rows and a plurality of columns corresponding to the one microlens and disposed inside the semiconductor substrate, and a first trench portion separating the plurality of photoelectric conversion units; a second trench portion provided between a photoelectric conversion portion included in one of two adjacent pixels among the plurality of pixels and a photoelectric conversion portion included in the other of the two adjacent pixels; In the first main surface, the first trench portion has a first portion extending in a first direction in a plan view with respect to the first main surface, In the second main surface, the first trench portion has a third portion extending in a first direction in a plan view with respect to the second main surface, the first portion and the third portion have a portion that overlaps with each other in a plan view with respect to the first main surface, A photoelectric conversion device, characterized in that a semiconductor region included in the semiconductor substrate is disposed between the first portion and the third portion.

4. An apparatus comprising the semiconductor device according to any one of claims 1 to 3, an optical device corresponding to the semiconductor device; a control device for controlling the semiconductor device; a processing device that processes a signal output from the semiconductor device; a display device that displays information obtained by the semiconductor device; a storage device that stores information obtained by the semiconductor device; and and a mechanical device that operates based on information obtained by the semiconductor device.

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