Light detection device and electronic appliance

Abstract

To reduce the size of a light detection device.SOLUTION: A light detection device is provided with a pixel including a photoelectric conversion unit, a charge holding unit that holds charges generated by the photoelectric conversion unit, a transfer unit that transfers the charges accumulated in the photoelectric conversion unit to the charge holding unit, and an amplification transistor that amplifies signal voltages corresponding to the charges held in the charge holding unit. The charge holding unit is shared by four pixels and is disposed at a center of four transfer units. A first small pixel group including a first charge holding unit, a first region where transistors including the amplification transistor are disposed, a second small pixel group including a second charge holding unit, and a third small pixel group including a third charge holding unit are disposed in this order. A first distance between the first charge holding unit and the second charge holding unit and a second distance between the second charge holding unit and the third charge holding unit are different. The present art is applicable to a light detection device, for example.SELECTED DRAWING: Figure 2

Description

[Technical Field]

[0001] The present technology relates to a photodetector and an electronic device, and for example, to a photodetector and an electronic device that can be made smaller. [Background technology]

[0002] It has been proposed to further reduce the size of imaging elements such as CMOS (Complementary Metal Oxide Semiconductor) image sensors by standardizing FDs (floating diffusions) (see, for example, Patent Document 1). [Prior art documents] [Patent documents]

[0003] [Patent Document 1] International Publication No. 2016 / 158439 Summary of the Invention [Problem to be solved by the invention]

[0004] As image sensors become smaller, the transistors also need to be made smaller, which can lead to a deterioration in transistor performance. It is therefore desirable to further miniaturize image sensors and ensure that their performance does not deteriorate even when miniaturized.

[0005] The present disclosure has been made in view of the above circumstances, and aims to make it possible to further reduce the size of a light detection device such as an imaging device. [Means for solving the problem]

[0006] According to one aspect of the present technology, there is provided a photodetector device including: a pixel having a photoelectric conversion unit; a charge retention unit that retains charges generated by the photoelectric conversion unit; a transfer unit that transfers the charges accumulated in the photoelectric conversion unit to the charge retention unit; and an amplification transistor that amplifies a signal voltage corresponding to the charges retained in the charge retention unit; the charge retention unit is shared by four of the pixels and is disposed at the center of the four transfer units; a first small pixel group including a first of the charge retention units, a first region in which a transistor including the amplification transistor is disposed, a second small pixel group including the second of the charge retention units, and a third small pixel group including a third of the charge retention units are disposed in this order; and a first distance between the first charge retention unit and the second charge retention unit and a second distance between the second charge retention unit and the third charge retention unit are different.

[0007] an amplifier transistor that amplifies a signal voltage corresponding to the charge held in the charge holding unit; a pixel having a photoelectric conversion unit; a charge holding unit that holds a charge generated by the photoelectric conversion unit; a transfer unit that transfers the charge accumulated in the photoelectric conversion unit to the charge holding unit; and an amplifier transistor that amplifies a signal voltage corresponding to the charge held in the charge holding unit, wherein the charge holding unit is shared by four of the pixels and is arranged at the center of the four transfer units; a first small pixel group including a first of the charge holding units, a first region in which a transistor including the amplifier transistor is arranged, a second small pixel group including the second of the charge holding units, and a third small pixel group including a third of the charge holding units are arranged in this order; and a photodetector device in which a first distance between the first charge holding unit and the second charge holding unit and a second distance between the second charge holding unit and the third charge holding unit are different; and

[0008] According to one aspect of the present technology, a photodetector device includes a pixel having a photoelectric conversion unit, a charge retention unit that retains charges generated by the photoelectric conversion unit, a transfer unit that transfers the charges accumulated in the photoelectric conversion unit to the charge retention unit, and an amplification transistor that amplifies a signal voltage corresponding to the charges retained in the charge retention unit. The charge retention unit is shared by four pixels and is disposed at the center of the four transfer units. A first small pixel group including a first charge retention unit, a first region in which a transistor including an amplification transistor is disposed, a second small pixel group including a second charge retention unit, and a third small pixel group including a third charge retention unit are disposed in this order. A first distance between the first charge retention unit and the second charge retention unit is different from a second distance between the second charge retention unit and the third charge retention unit.

[0009] An electronic device according to one aspect of the present technology includes the photodetector device.

[0010] The photodetector and the electronic device may be independent devices or may be internal blocks that form a single device. [Brief explanation of the drawings]

[0011] [Figure 1] 1 is a diagram illustrating a configuration example of an embodiment of a photodetector to which the present technology is applied. [Figure 2] FIG. 2 is a diagram illustrating an example of the configuration of a pixel group according to the first embodiment. [Figure 3] FIG. 2 is a diagram illustrating an example of the configuration of a pixel group according to the first embodiment. [Figure 4] FIG. 10 is a diagram for explaining the arrangement of transistors. [Figure 5] FIG. 10 is a diagram for explaining the distance between FDs. [Figure 6] FIG. 10 is a diagram for explaining the distance between FDs. [Figure 7] FIG. 10 is a diagram illustrating an example of the configuration of a pixel group according to the second embodiment. [Figure 8]FIG. 10 is a diagram illustrating an example of the configuration of a pixel group according to the second embodiment. [Figure 9] FIG. 11 is a diagram illustrating an example of the configuration of a pixel group according to the third embodiment. [Figure 10] FIG. 11 is a diagram illustrating an example of the configuration of a pixel group according to the third embodiment. [Figure 11] FIG. 13 is a diagram illustrating an example of the configuration of a pixel group in the fourth embodiment. [Figure 12] FIG. 13 is a diagram illustrating an example of the configuration of a pixel group in the fourth embodiment. [Figure 13] FIG. 13 is a diagram illustrating an example of the configuration of a pixel group in the fifth embodiment. [Figure 14] FIG. 13 is a diagram illustrating an example of the configuration of a pixel group in the fifth embodiment. [Figure 15] FIG. 20 is a diagram illustrating an example of the configuration of a pixel group in the sixth embodiment. [Figure 16] FIG. 20 is a diagram illustrating an example of the configuration of a pixel group in the sixth embodiment. [Figure 17] FIG. 20 is a diagram illustrating an example of the configuration of a pixel group in the seventh embodiment. [Figure 18] FIG. 20 is a diagram illustrating an example of the configuration of a pixel group in the seventh embodiment. [Figure 19] FIG. 10 is a diagram for explaining the arrangement of transistors. [Figure 20] FIG. 10 is a diagram for explaining the distance between FDs. [Figure 21] FIG. 23 is a diagram illustrating an example of the configuration of a pixel group in the eighth embodiment. [Figure 22] FIG. 23 is a diagram illustrating an example of the configuration of a pixel group in the eighth embodiment. [Figure 23] FIG. 23 is a diagram illustrating an example of the configuration of a pixel group according to the ninth embodiment. [Figure 24] FIG. 23 is a diagram illustrating an example of the configuration of a pixel group according to the ninth embodiment. [Figure 25] FIG. 23 is a diagram illustrating an example of the configuration of a pixel group according to the tenth embodiment. [Figure 26] FIG. 23 is a diagram illustrating an example of the configuration of a pixel group according to the tenth embodiment. [Figure 27] FIG. 23 is a diagram illustrating an example of the configuration of a pixel group in the eleventh embodiment. [Figure 28] FIG. 23 is a diagram illustrating an example of the configuration of a pixel group in the eleventh embodiment. [Figure 29] FIG. 23 is a diagram illustrating an example of the configuration of a pixel group in the twelfth embodiment. [Figure 30] FIG. 23 is a diagram illustrating an example of the configuration of a pixel group in the twelfth embodiment. [Figure 31] FIG. 23 is a diagram illustrating an example of the configuration of a pixel group in the thirteenth embodiment. [Figure 32] FIG. 23 is a diagram illustrating an example of the configuration of a pixel group in the thirteenth embodiment. [Figure 33] FIG. 23 is a diagram illustrating an example of the configuration of a pixel group in the fourteenth embodiment. [Figure 34] FIG. 23 is a diagram illustrating an example of the configuration of a pixel group in the fourteenth embodiment. [Figure 35] FIG. 23 is a diagram illustrating an example of the configuration of a pixel group in the fifteenth embodiment. [Figure 36] FIG. 23 is a diagram illustrating an example of the configuration of a pixel group in the fifteenth embodiment. [Figure 37] FIG. 23 is a diagram illustrating an example of the configuration of a pixel group in the sixteenth embodiment. [Figure 38] FIG. 23 is a diagram illustrating an example of the configuration of a pixel group in the sixteenth embodiment. [Figure 39] FIG. 23 is a diagram illustrating an example of the configuration of a pixel group in the seventeenth embodiment. [Figure 40] FIG. 23 is a diagram illustrating an example of the configuration of a pixel group in the seventeenth embodiment. [Figure 41]FIG. 23 is a diagram illustrating an example of the configuration of a pixel group in the eighteenth embodiment. [Figure 42] FIG. 23 is a diagram illustrating an example of the configuration of a pixel group in the eighteenth embodiment. [Figure 43] FIG. 23 is a diagram illustrating an example of the configuration of a pixel group in the nineteenth embodiment. [Figure 44] FIG. 23 is a diagram illustrating an example of the configuration of a pixel group in the nineteenth embodiment. [Figure 45] FIG. 23 is a diagram illustrating an example of the configuration of a pixel group in the twentieth embodiment. [Figure 46] FIG. 23 is a diagram illustrating an example of the configuration of a pixel group in the twentieth embodiment. [Figure 47] FIG. 21 is a diagram illustrating an example of the configuration of a pixel group in the twenty-first embodiment. [Figure 48] FIG. 21 is a diagram illustrating an example of the configuration of a pixel group in the twenty-first embodiment. [Figure 49] FIG. 22 is a diagram illustrating an example of the configuration of a pixel group according to the twenty-second embodiment. [Figure 50] FIG. 22 is a diagram illustrating an example of the configuration of a pixel group according to the twenty-second embodiment. [Figure 51] FIG. 23 is a diagram illustrating an example of the configuration of a pixel group in the twenty-third embodiment. [Figure 52] FIG. 23 is a diagram illustrating an example of the configuration of a pixel group in the twenty-third embodiment. [Figure 53] FIG. 24 is a diagram illustrating an example of the configuration of a pixel group in the twenty-fourth embodiment. [Figure 54] FIG. 24 is a diagram illustrating an example of the configuration of a pixel group in the twenty-fourth embodiment. [Figure 55] FIG. 25 is a diagram illustrating an example of the configuration of a pixel group in the twenty-fifth embodiment. [Figure 56] FIG. 25 is a diagram illustrating an example of the configuration of a pixel group in the twenty-fifth embodiment. [Figure 57]FIG. 26 is a diagram illustrating an example of the configuration of a pixel group according to the twenty-sixth embodiment. [Figure 58] FIG. 26 is a diagram illustrating an example of the configuration of a pixel group according to the twenty-sixth embodiment. [Figure 59] FIG. 27 is a diagram illustrating an example of the configuration of a pixel group according to the twenty-seventh embodiment. [Figure 60] FIG. 27 is a diagram illustrating an example of the configuration of a pixel group according to the twenty-seventh embodiment. [Figure 61] FIG. 28 is a diagram illustrating an example of the configuration of a pixel group according to the twenty-eighth embodiment. [Figure 62] FIG. 28 is a diagram illustrating an example of the configuration of a pixel group according to the twenty-eighth embodiment. [Figure 63] FIG. 29 is a diagram illustrating an example of the configuration of a pixel group according to the twenty-ninth embodiment. [Figure 64] FIG. 29 is a diagram illustrating an example of the configuration of a pixel group according to the twenty-ninth embodiment. [Figure 65] FIG. 23 is a diagram illustrating an example of the configuration of a pixel group in the 30th embodiment. [Figure 66] FIG. 23 is a diagram illustrating an example of the configuration of a pixel group in the 30th embodiment. [Figure 67] FIG. 23 is a diagram illustrating an example of the configuration of a pixel group in the thirty-first embodiment. [Figure 68] FIG. 23 is a diagram illustrating an example of the configuration of a pixel group in the thirty-first embodiment. [Figure 69] FIG. 23 is a diagram illustrating an example of the configuration of a pixel group in the thirty-second embodiment. [Figure 70] FIG. 23 is a diagram illustrating an example of the configuration of a pixel group in the thirty-second embodiment. [Figure 71] FIG. 33 is a diagram illustrating an example of the configuration of a pixel group in the thirty-third embodiment. [Figure 72] FIG. 33 is a diagram illustrating an example of the configuration of a pixel group in the thirty-third embodiment. [Figure 73]FIG. 23 is a diagram illustrating an example of the configuration of a pixel group in the thirty-fourth embodiment. [Figure 74] FIG. 23 is a diagram illustrating an example of the configuration of a pixel group in the thirty-fourth embodiment. [Figure 75] FIG. 23 is a diagram illustrating an example of the configuration of a pixel group in the thirty-fifth embodiment. [Figure 76] FIG. 23 is a diagram illustrating an example of the configuration of a pixel group in the thirty-fifth embodiment. [Figure 77] FIG. 23 is a diagram illustrating an example of the configuration of a pixel group in the thirty-sixth embodiment. [Figure 78] FIG. 23 is a diagram illustrating an example of the configuration of a pixel group in the thirty-sixth embodiment. [Figure 79] FIG. 1 is a block diagram illustrating an example of the configuration of an electronic device. [Figure 80] FIG. 1 is a diagram illustrating an example of a schematic configuration of an endoscopic surgery system. [Figure 81] FIG. 2 is a block diagram showing an example of the functional configuration of a camera head and a CCU. [Figure 82] 1 is a block diagram showing an example of a schematic configuration of a vehicle control system; [Figure 83] FIG. 2 is an explanatory diagram showing an example of the installation positions of an outside-vehicle information detection unit and an imaging unit. DETAILED DESCRIPTION OF THE INVENTION

[0012] Hereinafter, modes for carrying out the present technology (hereinafter referred to as embodiments) will be described.

[0013] <Configuration example of imaging device> FIG. 1 shows a configuration example of an embodiment of a photodetector to which the present technology is applied.

[0014] The photodetector 1 in Fig. 1 is configured with a pixel array section 3 in which pixels 2 are arranged in a two-dimensional array, and a peripheral circuit section around the pixel array section, which includes a vertical drive circuit 4, a column signal processing circuit 5, a horizontal drive circuit 6, an output circuit 7, a control circuit 8, etc.

[0015] The pixel 2 includes a photodiode as a photoelectric conversion element and a plurality of pixel transistors, such as a transfer transistor, a selection transistor, a reset transistor, and an amplification transistor, which are configured as MOS transistors.

[0016] The control circuit 8 receives an input clock and data instructing the operation mode and the like, and outputs data such as internal information of the photodetector 1. That is, the control circuit 8 generates clock signals and control signals that serve as references for the operation of the vertical drive circuit 4, column signal processing circuit 5, horizontal drive circuit 6, etc., based on a vertical synchronization signal, a horizontal synchronization signal, and a master clock. The control circuit 8 outputs the generated clock signals and control signals to the vertical drive circuit 4, column signal processing circuit 5, horizontal drive circuit 6, etc.

[0017] The vertical drive circuit 4 is configured with, for example, a shift register, selects a predetermined pixel drive line 10, supplies a pulse to the selected pixel drive line 10 for driving the pixels 2, and drives the pixels 2 row by row. That is, the vertical drive circuit 4 selects and scans each pixel 2 in the pixel array section 3 row by row in the vertical direction, and supplies a pixel signal based on a signal charge generated in the photoelectric conversion section of each pixel 2 according to the amount of received light to the column signal processing circuit 5 through the vertical signal line 9.

[0018] The column signal processing circuits 5 are arranged for each column of pixels 2, and perform signal processing such as noise removal for each pixel column on signals output from one row of pixels 2. For example, the column signal processing circuits 5 perform signal processing such as CDS (Correlated Double Sampling) or DDS (Double Data Sampling) for removing fixed pattern noise specific to each pixel, and AD conversion.

[0019] The horizontal drive circuit 6 is configured, for example, by a shift register, and sequentially outputs horizontal scanning pulses to select each of the column signal processing circuits 5 in turn, causing each of the column signal processing circuits 5 to output a pixel signal to the horizontal signal line 11.

[0020] The output circuit 7 processes and outputs signals sequentially supplied from each of the column signal processing circuits 5 via a horizontal signal line 11. The output circuit 7 may perform only buffering, or may perform black level adjustment, column variation correction, various digital signal processing, etc. The input / output terminal 13 exchanges signals with the outside.

[0021] The photodetector 1 configured as above is a CMOS image sensor called a column AD type, in which a column signal processing circuit 5 that performs CDS processing or DDS processing and AD conversion processing is arranged for each pixel column.

[0022] First Embodiment FIG. 2 is a diagram showing an example of the planar configuration of the pixel array section 3 of the photodetector 1 in the first embodiment, and FIG. 3 is a diagram showing an example of the cross-sectional configuration along line AA' in FIG.

[0023] 2 shows a portion configured of 16 pixels 2 arranged in a 4×4 array. In the first embodiment, the explanation will be continued taking as an example a case where the 16 pixels share a floating diffusion (FD).

[0024] A small pixel group 20 is formed by four pixels 2 arranged in a 2x2 array, and four sets (four units) of small pixel groups 20 form a large pixel group 50a. The small pixel group 20-1 shown in the upper left of the figure includes pixels 2-1, 2-2, 2-3, and 2-4. The small pixel group 20-2 shown in the upper right of the figure includes pixels 2-5, 2-6, 2-7, and 2-8. The small pixel group 20-3 shown in the lower left of the figure includes pixels 2-9, 2-10, 2-11, and 2-12. The small pixel group 20-4 shown in the lower right of the figure includes pixels 2-13, 2-14, 2-15, and 2-16.

[0025] As shown in FIG. 3, each pixel 2 includes a PD (photodiode) 31, and the charge accumulated in the PD 31 is transferred to the FD 23 by a transfer gate 22 of a transfer transistor.

[0026] Each of the pixels 2-1 to 2-4 in the small pixel group 20-1 includes a PD 31-1 to PD 31-4 (not shown) and a transfer gate 22-1 to 22-4. An FD 23-1 is provided in the center of the area in which the transfer gates 22-1 to 22-4 are arranged. A contact 24-1 is provided in the FD 23-1, and the contact 24-1 is connected to a wiring 40 in a stacked wiring layer (not shown).

[0027] Each of the pixels 2-5 to 2-8 in the small pixel group 20-2 includes a PD31-5 to PD31-8 (not shown) and a transfer gate 22-5 to 22-8. An FD 23-2 is provided in the center of the area in which the transfer gates 22-5 to 22-8 are arranged. A contact 24-2 is provided in the FD 23-2, and the contact 24-2 is connected to a wiring 40 in a stacked wiring layer (not shown).

[0028] Each of the pixels 2-9 to 2-12 in the small pixel group 20-3 includes a PD31-9 to PD31-12 (not shown) and a transfer gate 22-9 to 22-12. An FD 23-3 is provided in the center of the area in which the transfer gates 22-9 to 22-12 are arranged. A contact 24-3 is provided in the FD 23-3, and the contact 24-3 is connected to a wiring 40 in a stacked wiring layer (not shown).

[0029] Each of the pixels 2-13 to 2-16 in the small pixel group 20-4 includes a PD31-13 to PD31-16 (not shown) and a transfer gate 22-13 to 22-16. An FD23-4 is provided at the center of each of the transfer gates 22-13 to 22-16. A contact 24-4 is provided in the FD23-4, and the contact 24-4 is connected to a wiring 40 in a stacked wiring layer (not shown).

[0030] FDs 23-1 to 23-4 provided in each of the small pixel groups 20-1 to 20-4 are connected to wiring 40. Wiring 40 is also connected to FD 23-5, which is provided above the center of the large pixel group 50 in the drawing, via contact 24-5. Therefore, FDs 23-1 to 23-5 function as a single FD and are configured to be shared by pixels 2-1 to 2-16 in the large pixel group 50. Hereinafter, when there is no need to distinguish between FDs 23-1 to 23-5 individually or when it is intended to indicate that they function as a single FD, they will be referred to simply as FD 23.

[0031] A reset transistor 25 is provided above the FD23-5 in the drawing, and the FD23 is configured to be reset by the reset transistor 25.

[0032] 2, an amplifier transistor 26 is provided on the lower side, and a contact 24-6 is provided at the gate of the amplifier transistor 26. This contact 24-6 is connected to a wiring 40. FDs 23-1 to 23-5 are connected to the amplifier transistor 26 via the wiring 40.

[0033] The amplifier transistor 26 has a transfer gate connected to the FD 23 and a drain connected to a power supply VDD 28, and serves as an input part of a readout circuit, a so-called source follower circuit, that reads out a signal corresponding to the charge held in the FD 23. That is, the amplifier transistor 26 has a source connected to the vertical signal line 9 (VSL region 29) via the selection transistor 27, and thereby forms a source follower circuit together with a constant current source (not shown) connected to one end of the vertical signal line 9.

[0034] 2, the reset transistor 25, amplification transistor 26, and selection transistor 27 are arranged in a vertical line in the center of the large pixel group 50. Contacts connected to the power supply VDD28 and contacts connected to the vertical signal line 9 (VSL region 29) are also arranged in a vertical line together with the transistors in the center of the large pixel group 50.

[0035] An example of the cross-sectional configuration along line A-A' in Figure 2 will be described with reference to Figure 3. Pixel 2-11, pixel 2-12, amplifier transistor 26, pixel 2-15, and pixel 2-16 are arranged in this order along line A-A'. In Figure 3, the lower side is the light incident surface, and the upper side is the wiring layer (not shown) side. An inter-pixel separator 32-11 is provided on the left side of PD 31-11 to separate it from pixel 2 (not shown), and an inter-pixel separator 32-12 is provided on the right side to separate it from PD 31-12.

[0036] An inter-pixel isolation portion 32-13 is provided between PD31-12 and PD31-15, an inter-pixel isolation portion 32-14 is provided between PD31-15 and PD31-16, and an inter-pixel isolation portion 32-15 is provided between PD31-16 and PD31 (not shown) of the adjacent pixel 2. The inter-pixel isolation portion 32 can be made of an oxide film.

[0037] A cell well 35-11 and a flat isolation section 33-11 are provided above the inter-pixel isolation section 32-11 in the drawing. A cell well 35-12 and a flat isolation section 33-12 are provided above the inter-pixel isolation section 32-12 in the drawing. A cell well 35-13 is provided above the inter-pixel isolation section 32-13 in the drawing, and a flat isolation section 33-13, a channel region 37 of the amplification transistor 26, and a flat isolation section 33-14 are provided above the cell well 35-13 in the drawing.

[0038] A cell well 35-14 and a flat isolation section 33-15 are provided above the inter-pixel isolation section 32-14 in the drawing. A cell well 35-15 and a flat isolation section 33-16 are provided above the inter-pixel isolation section 32-15 in the drawing.

[0039] The cell well 35 and the flat isolation section 33 are regions in which P-type impurities are diffused, and are provided to separate pixels (elements). The element isolation section provided on the surface side of the silicon substrate on which the PD 31 is formed (the upper side in FIG. 3, the surface on which the transfer gate 22 is formed) is referred to as the flat isolation section 33, and the element isolation section located deeper in the silicon substrate from the surface side is referred to as the cell well 35. The flat isolation section 33 and the cell well 35 may be regions with different concentrations of P-type impurities, or may have approximately the same concentration and be formed as an integrated unit.

[0040] If the PD 31 is configured to include a region in which N-type impurities are diffused, the cell well 35 and the FLAT isolation part 33 are formed in a region in which P-type impurities are diffused. If the PD 31 is configured to include a region in which P-type impurities are diffused, the cell well 35 and the FLAT isolation part 33 are formed in a region in which N-type impurities are diffused.

[0041] A transfer gate 22-11 is provided on PD31-11, which is located between FLAT separation unit 33-11 and FLAT separation unit 33-12. A transfer gate 22-12 is provided on PD31-12, which is located between FLAT separation unit 33-12 and FLAT separation unit 33-13. A transfer gate 22-15 is provided on PD31-15, which is located between FLAT separation unit 33-14 and FLAT separation unit 33-15. A transfer gate 22-16 is provided on PD31-16, which is located between FLAT separation unit 33-15 and FLAT separation unit 33-16.

[0042] The active area and transistor arrangement will be further explained with reference to Figure 4. Figure 4 is a diagram showing large pixel groups 50a-1 and 50a-2 arranged above and below each other. The pixels 2 are separated by inter-pixel isolation sections 32 (Figure 3), and an element isolation section is provided within the active area of ​​each pixel 2. The element isolation section is, for example, a cell well 35 or a flat isolation section 33.

[0043] The active region 70-1 is provided with a reset transistor 25-1. The active region 70-2 is provided with a select transistor 27-1, an amplifying transistor 26-1, and a reset transistor 25-2. The active region 70-3 is provided with a select transistor 27-2 and an amplifying transistor 26-2.

[0044] The active region 70-1 is formed across the large pixel group 50a-1 and a large pixel group 50a (not shown) located above the large pixel group 50a-1. The active region 70-2 is formed across the large pixel group 50a-1 and a large pixel group 50a-2 located below the large pixel group 50a-1. The active region 70-3 is formed across the large pixel group 50a-2 and a large pixel group 50a (not shown) located below the large pixel group 50a-2.

[0045] Focus on the large pixel group 50a-1. Pixels 2-1 to 2-16 arranged within the large pixel group 50a-1 use a reset transistor 25-1 arranged in an active region 70-1, and a selection transistor 27-1 and an amplification transistor 26-1 arranged in an active region 70-2. Pixel 2 within the large pixel group 50a-1 performs processing using a transistor arranged in an active region 70-2 formed within its own large pixel group 50a-1 and a transistor arranged in an active region 70-1 formed across the other large pixel groups 50a.

[0046] By adopting such a configuration, the transistors can be arranged so that the distance between the wirings 40 is the shortest.

[0047] The power supply VDD28 is configured to be shared by the large pixel group 50a. The power supply VDD28-2 is provided in an active region 70-2 formed across the large pixel group 50a-1 and the large pixel group 50a-2, at the boundary between the large pixel group 50a-1 and the large pixel group 50a-2, and is configured to be shared by the pixels 2 arranged in both the large pixel group 50a-1 and the large pixel group 50a-2.

[0048] The distance between adjacent FDs 23 will be explained with reference to Figures 5 and 6. Figure 5 shows an example of the planar configuration of horizontally adjacent superpixel groups 50a-1 and 50a-2. Figure 6, like Figure 3, shows an example of the cross-sectional configuration taken along line A-A' in Figure 2.

[0049] 5, one pixel 2 is formed with a length A in both the vertical and horizontal directions. The length of one side of a pixel 2 is the distance from the center to the center of inter-pixel isolation portions 32 between pixels 2. Referring to FIG. 6, for example, the distance from the center of inter-pixel isolation portion 32-11 on the left side of pixel 2-11 shown at the left end of the figure to inter-pixel isolation portion 32-12 on the right side is length A.

[0050] Length A is also the distance from the center of inter-pixel isolation portion 32 to contact 24 connected to FD 23. For example, referring to FIG. 5, the distance from contact 24-3 in small pixel group 20-3 located to the lower left of large pixel group 50a-1 to the center of inter-pixel isolation portion 32 provided between contact 24-3 and the adjacent large pixel group 50a (not shown) located on the left side of the drawing is length A.

[0051] At the center of the large pixel group 50a-1, contact 24-5 provided on FD23-5, contact 24-6 connected to the amplification transistor 26, contact 24-7 connected to the vertical signal line 9, and contact 24-8 connected to the power supply VDD are arranged in a row.

[0052] The distance from the center of the inter-pixel isolation portion 32 between pixels 2 in the small pixel group 20 to the contact 24 arranged at the center of the large pixel group 50a-1 is length B. Since the center of the inter-pixel isolation portion 32 between pixels 2 in the small pixel group 20 is also the position where the contact 24 connected to the FD 23 is located, the distance between the contact 24 connected to the FD 23 and the contact 24 connected to the transistor is length B.

[0053] For example, the distance between contact 24-3 at the center of small pixel group 20-3 and contact 24-6 connected to amplification transistor 26 in large pixel group 50a-1 is length B. When viewed in cross section, as shown in FIG. 6, for example, the distance from the center of inter-pixel isolation portion 32-12 between pixel 2-11 and pixel 2-12 to the center of the gate of amplification transistor 26 is length B.

[0054] 6, the horizontal length of the PD 31 is length C. The length of the PD 31 arranged in the small pixel group 20 is configured to be length C.

[0055] The relationship between length A, length B, and length C is length C<length A<length B. Focusing on length A and length B, the spacing at which the FDs 23 are arranged will now be explained. The distance between FD23-3 and FD23-4 within the large pixel group 50a-1 is the sum of the distance between the contact 24-3 of FD23-3 and the contact 24-6 of the amplifier transistor 26 (length B) and the distance between the contact 24-6 of the amplifier transistor 26 and the contact 24-4 of FD23-4 (length B), so is (2 × length B).

[0056] The distance between FD23-4 in large pixel group 50a-1 and FD23-7 in large pixel group 50a-2 is the sum of the distance from the center of inter-pixel isolation section 32 to contact 24-4 of FD23-4 (length A) and the distance from the center of inter-pixel isolation section 32 to contact 24-11 of FD23-7 (length A), so is (2 x length A).

[0057] Contacts 24-3, 24-4, and 24-11 are adjacently arranged in a straight line. The distance between contacts 24-3 and 24-4 is (2 × length B), while the distance between contacts 24-4 and 24-11 is (2 × length A), which are different distances. That is, in this case, the distance between FD23-3 and FD23-4, which are adjacent to each other, is different from the distance between FD23-4 and FD23-7, which are adjacent to each other. That is, the distances between FD23 are not equal, but are different.

[0058] In this way, the FD23 and transistors are arranged so that the distance between adjacent FD23s with a transistor (area in which the transistor is arranged) between them is different from the distance between adjacent FD23s without a transistor (area in which the transistor is arranged) between them.

[0059] The FDs 23 are arranged so that they are spaced apart from one another at different distances, but the sizes of the PDs 31 are configured to be equal, as shown in Fig. 6. To make the sizes of the PDs 31 equal, for example, in the cross-sectional configuration example shown in Fig. 6, the cell well 35-13 below the amplifying transistor 26 is formed larger than the other cell wells 35, and PD31-12 and PD31-15 are adjusted so that they are not larger than the other PDs 31.

[0060] With this configuration, even if the photodetector 1 is miniaturized, it is possible to maintain the area for arranging the transistors while ensuring the charge transfer area, thereby achieving both the transistor characteristics and the charge transfer characteristics.

[0061] <Second embodiment> Fig. 7 shows an example of the planar configuration of the large pixel group 50b in the second embodiment, and Fig. 8 is a diagram showing an example of the cross-sectional configuration of the large pixel group 50b taken along line A-A' in Fig. 7. In the large pixel group 50b in the second embodiment shown in Figs. 7 and 8, parts that are the same as those in the large pixel group 50a in the first embodiment shown in Figs. 2 and 3 are designated by the same reference numerals, and descriptions thereof will be omitted where appropriate.

[0062] 7 and 8, the large pixel group 50b in the second embodiment is similar to the large pixel group 50a in the first embodiment except that the transfer gate 22b is a transfer gate having a vertical structure. As shown in Fig. 8, the transfer gate 22b of the transfer transistor has a shape that combines a planar electrode provided in a planar shape on the front surface of the semiconductor substrate and a vertical electrode provided vertically within the semiconductor substrate (inside the PD 31).

[0063] 7, the vertical electrode portion of the transfer gate 22 is formed in a circular shape in a plan view. The vertical electrode portion is formed in a circular or polygonal shape.

[0064] By configuring the transfer gate 22 to have a vertical electrode, the transfer efficiency can be improved.

[0065] In the second embodiment, as in the first embodiment, the distance between adjacent FDs 23 is different between where a transistor is sandwiched and where it is not sandwiched. The size of the PD 31 is adjusted to be the same in each pixel 2. Therefore, as in the first embodiment, even if the photodetector 1 is miniaturized, it is possible to ensure a charge transfer area while maintaining the area for arranging the transistor, thereby achieving both transistor characteristics and charge transfer characteristics.

[0066] <Third embodiment> Fig. 9 shows an example of the planar configuration of the superpixel group 50c in the third embodiment, Fig. 10A shows an example of the cross-sectional configuration of the superpixel group 50c taken along line A-A' in Fig. 9, and Fig. 10B is a diagram showing an example of the cross-sectional configuration of the superpixel group 50c taken along line B-B' in Fig. 9. In the superpixel group 50c in the third embodiment shown in Figs. 9 and 10, parts that are the same as those in the superpixel group 50a in the first embodiment shown in Figs. 2 and 3 are designated by the same reference numerals, and descriptions thereof will be omitted where appropriate.

[0067] The subpixel group 50c in the third embodiment shown in Figures 9 and 10 differs from the subpixel group 50a in the first embodiment in that the transfer gate 22c is a transfer gate having a vertical structure, but is otherwise similar.

[0068] 10, the transfer gate 22c of the transfer transistor is configured by combining a planar electrode provided in a planar shape on the front surface of the semiconductor substrate with a vertical electrode provided vertically within the semiconductor substrate. The transfer gate 22c is also formed in a shape that sandwiches the portion corresponding to the inter-pixel isolation portion.

[0069] 10A, an STI 61-12 is formed on the cell well 35-12 (on the substrate surface side) formed in the inter-pixel isolation portion 32-12 between PD31-11 and PD31-12. A transfer gate 22c-11 of PD31-11 and a transfer gate 22c-12 of PD31-12 are formed on either side of the STI 61-12. The transfer gate 22c has a vertical electrode in contact with the STI 61.

[0070] 10A, an STI 61-16 is formed on the cell well 35-14 (on the substrate surface side) formed in the inter-pixel isolation portion 32-14 provided between PD31-15 and PD31-15. A transfer gate 22c-15 of PD31-15 and a transfer gate 22c-16 of PD31-16 are formed on either side of the STI 61-16.

[0071] B of Fig. 10 is a diagram showing an example of the cross-sectional configuration of the large pixel group 50c taken along line B-B' in Fig. 9. Pixels 2-1, 2-3, and 2-4 are arranged along line B-B'. As shown in B of Fig. 10, an STI 61-3 is formed on the substrate surface side between PD 31-1 included in pixel 2-1 and PD 31-3 included in pixel 2-3. The transfer gate 22c-1 of the transfer transistor of pixel 2-1 and the transfer gate 22c-3 of the transfer transistor of pixel 2-3 are configured with vertical electrodes, sandwiching the STI 61-3.

[0072] 10B, the transfer gate 22c-3 disposed on the pixel 2-3 has vertical electrodes formed on both ends of the transfer gate 22c-3 so as to sandwich the PD 31-3, and a flat electrode provided on the substrate formed on the top of the transfer gate 22c-3. The transfer gate 22c-3 is formed in a shape that appears to be Π-shaped in cross section.

[0073] An STI 61-4 is formed on the substrate surface side between PD 31-3 included in pixel 2-3 and PD 31-4 included in pixel 2-4. A transfer gate 22c-3 of the transfer transistor of pixel 2-3 and a transfer gate 22c-4 of the transfer transistor of pixel 2-4 are configured with vertical electrodes on either side of the STI 61-4.

[0074] In the third embodiment, since the transfer gates 22 of the transfer transistors are configured close to each other, in order to reduce the influence thereof, an STI 61 is provided between the transfer gates 22c. The STI 61 can be formed of an oxide film.

[0075] 9, the vertical electrode portion of the transfer gate 22c is formed in a trapezoidal shape in a plan view, with its bottom side facing the STI 61. Note that the vertical electrode portion of the transfer gate 22c is not limited to a trapezoidal shape in a plan view, and may have another shape.

[0076] By configuring the transfer gate 22c to have a vertical electrode, the transfer efficiency can be improved.

[0077] In the third embodiment, as in the first embodiment, the distance between adjacent FDs 23 is different between where a transistor is sandwiched and where it is not sandwiched. The size of the PD 31 is adjusted to be the same in each pixel 2. Therefore, as in the first embodiment, even if the photodetector 1 is miniaturized, it is possible to ensure a charge transfer area while maintaining the area for arranging the transistor, thereby achieving both transistor characteristics and charge transfer characteristics.

[0078] <Fourth embodiment> Fig. 11 shows an example of the planar configuration of the superpixel group 50d in the fourth embodiment, and Fig. 12 shows an example of the cross-sectional configuration of the superpixel group 50d taken along line A-A' in Fig. 11. In the superpixel group 50d in the fourth embodiment shown in Figs. 11 and 12, parts that are the same as those in the superpixel group 50a in the first embodiment shown in Figs. 2 and 3 are designated by the same reference numerals, and descriptions thereof will be omitted where appropriate.

[0079] The large pixel group 50d in the fourth embodiment shown in FIGS. 11 and 12 differs from the large pixel group 50a in the first embodiment in that the element isolation in the region where the transistors are arranged is performed by STI, but is otherwise similar.

[0080] An STI 71 is formed around the active area where the reset transistor 25, the selection transistor 27, and the amplification transistor 26 are arranged, in the vertical direction of the central area of ​​the large pixel group 50.

[0081] In cross section, as shown in FIG. 12, STIs 71 are formed on both sides of the channel region 37 of the amplifying transistor 26 to isolate it from other elements.

[0082] In the fourth embodiment, as in the first embodiment, the distance between adjacent FDs 23 is different between where a transistor is sandwiched and where it is not sandwiched. The size of the PD 31 is adjusted to be the same in each pixel 2. Therefore, as in the first embodiment, even if the photodetector 1 is miniaturized, it is possible to ensure a charge transfer area while maintaining the area for arranging the transistor, thereby achieving both transistor characteristics and charge transfer characteristics.

[0083] <Fifth embodiment> Fig. 13 shows an example of the planar configuration of the large pixel group 50e in the fifth embodiment, and Fig. 14 shows an example of the cross-sectional configuration of the large pixel group 50e taken along line A-A' in Fig. 13. In the large pixel group 50e in the fifth embodiment shown in Figs. 13 and 14, parts that are the same as those in the large pixel group 50b in the second embodiment shown in Figs. 7 and 8 are designated by the same reference numerals, and descriptions thereof will be omitted where appropriate.

[0084] The large pixel group 50e in the fifth embodiment shown in Figures 13 and 14 differs from the large pixel group 50b in the second embodiment in that the element isolation in the region where the transistors are arranged is performed by STI, but is otherwise similar.

[0085] An STI 71 is formed around the active area where the reset transistor 25, the selection transistor 27, and the amplification transistor 26 are arranged, in the vertical direction of the central area of ​​the large pixel group 50.

[0086] 14, in cross section, STI 71 is formed on both sides of the channel region 37 of the amplifier transistor 26 to isolate it from other elements. The transfer gate 22 has a vertical electrode.

[0087] In the fifth embodiment, as in the first embodiment, the distance between adjacent FDs 23 is different between where a transistor is sandwiched and where it is not sandwiched. The size of the PE 31 is adjusted to be the same in each pixel 2. Therefore, as in the first embodiment, even if the photodetector 1 is miniaturized, it is possible to ensure a charge transfer area while maintaining the area for arranging the transistor, thereby achieving both transistor characteristics and charge transfer characteristics.

[0088] Sixth Embodiment Fig. 15 shows an example of the planar configuration of the superpixel group 50f in the sixth embodiment, Fig. 16A shows an example of the cross-sectional configuration of the superpixel group 50f taken along line A-A' in Fig. 15, and Fig. 16B is a diagram showing an example of the cross-sectional configuration of the superpixel group 50f taken along line B-B' in Fig. 15. In the superpixel group 50f in the sixth embodiment shown in Figs. 15 and 16, parts that are the same as those in the superpixel group 50c in the third embodiment shown in Figs. 9 and 10 are designated by the same reference numerals, and descriptions thereof will be omitted where appropriate.

[0089] The large pixel group 50f in the sixth embodiment shown in Figures 15 and 16 differs from the large pixel group 50c in the third embodiment in that the element isolation in the region where the transistors are arranged is performed by STI, but is otherwise similar.

[0090] An STI 71 is formed around the active area where the reset transistor 25, the selection transistor 27, and the amplification transistor 26 are arranged, in the vertical direction of the central area of ​​the large pixel group 50.

[0091] 16A, in cross section, STI 71 is formed on both sides of the channel region 37 of the amplifying transistor 26 to isolate it from other elements. The transfer gate 22 has a vertical electrode, is formed in a Π shape, and is configured to sandwich the PD 31.

[0092] In the sixth embodiment, as in the first embodiment, the distance between adjacent FDs 23 is different between where a transistor is sandwiched and where it is not sandwiched. The size of the PD 31 is adjusted to be the same in each pixel 2. Therefore, as in the first embodiment, even if the photodetector 1 is miniaturized, it is possible to ensure a charge transfer area while maintaining the area for arranging the transistor, thereby achieving both transistor characteristics and charge transfer characteristics.

[0093] Seventh Embodiment Fig. 17 shows an example of the planar configuration of the large pixel group 50g in the seventh embodiment, and Fig. 18A shows an example of the cross-sectional configuration of the large pixel group 50g taken along line A-A' in Fig. 17. In the large pixel group 50g in the seventh embodiment shown in Figs. 17 and 18, parts that are the same as those in the large pixel group 50a in the first embodiment shown in Figs. 2 and 3 are designated by the same reference numerals, and descriptions thereof will be omitted where appropriate.

[0094] In the seventh embodiment shown in FIG. 17, the FD 23 is also shared by 16 pixels 2. The small pixel group 20-1 shown in the upper left of the figure includes pixels 2-1, 2-2, 2-3, and 2-4. The small pixel group 20-2 shown in the upper right of the figure includes pixels 2-5, 2-6, 2-7, and 2-8. The small pixel group 20-3 shown in the lower left of the figure includes pixels 2-9, 2-10, 2-11, and 2-12. The small pixel group 20-4 shown in the lower right of the figure includes pixels 2-13, 2-14, 2-15, and 2-16.

[0095] As shown in FIG. 18, each pixel 2 includes a PD 31, and charges accumulated in the PD 31 are transferred to the FD 23 by a transfer gate 22 of a transfer transistor. The pixels 2-1 to 2-4 of the small pixel group 20-1 each include a PD 31-1 to PD31-4 (not shown) and transfer gates 22-1 to 22-4. FD 23-1 is provided in the center of the area where the transfer gates 22-1 to 22-4 are arranged. FD 23-1 includes a contact 24-1, which is connected to a wiring 40 in a stacked wiring layer (not shown).

[0096] Each of the pixels 2-5 to 2-8 in the small pixel group 20-2 includes a PD31-5 to PD31-8 (not shown) and a transfer gate 22-5 to 22-8. An FD 23-2 is provided in the center of the area in which the transfer gates 22-5 to 22-8 are arranged. A contact 24-2 is provided in the FD 23-2, and the contact 24-2 is connected to a wiring 40 in a stacked wiring layer (not shown).

[0097] Each of the pixels 2-9 to 2-12 in the small pixel group 20-3 includes a PD31-9 to PD31-12 (not shown) and a transfer gate 22-9 to 22-12. An FD 23-3 is provided in the center of the area in which the transfer gates 22-9 to 22-12 are arranged. A contact 24-3 is provided in the FD 23-3, and the contact 24-3 is connected to a wiring 40 in a stacked wiring layer (not shown).

[0098] Each of the pixels 2-13 to 2-16 in the small pixel group 20-4 includes a PD31-13 to PD31-16 (not shown) and a transfer gate 22-13 to 22-16. An FD23-4 is provided at the center of each of the transfer gates 22-13 to 22-16. A contact 24-4 is provided in the FD23-4, and the contact 24-4 is connected to a wiring 40 in a stacked wiring layer (not shown).

[0099] FDs 23-1 to 23-4 provided in each of the small pixel groups 20-1 to 20-4 are connected to wiring 40. The wiring 40 is also connected via contact 24-5 to FD 23-5 provided to the right of the center of the large pixel group 50 in the drawing. Therefore, FDs 23-1 to 23-5 function as a single FD, and are configured to be shared and used by pixels 2-1 to 2-16 in the large pixel group 50.

[0100] A reset transistor 25 is provided to the right of FD23-5 in the drawing. An amplifier transistor 26 is provided on the left in FIG. 17, and a contact 24-6 is provided at the gate of the amplifier transistor 26. This contact 24-6 is connected to a wiring 40. FDs 23-1 to 23-5 are connected to the amplifier transistor 26 via the wiring 40.

[0101] 17, the reset transistor 25, amplification transistor 26, and selection transistor 27 are arranged in a row in the horizontal direction in the central part of the large pixel group 50. Contacts connected to the power supply VDD28 and contacts connected to the vertical signal line 9 (VSL region 29) are also arranged in a row in the horizontal direction together with the transistors in the central part of the large pixel group 50. In this way, the large pixel group 50g in the seventh embodiment differs from the large pixel group 50a in the first embodiment in that the transistors are arranged in the horizontal direction, but is otherwise basically the same.

[0102] An example of the cross-sectional configuration along line A-A' in Figure 17 will be described further with reference to Figure 18. Pixel 2-1, pixel 2-3, amplifier transistor 26, pixel 2-9, and pixel 2-11 are arranged in this order along line A-A'. In Figure 17, the lower side is the light incident surface, and the upper side is the wiring layer (not shown). An inter-pixel isolation section 32-1 is provided on the left side of PD 31-1 to isolate it from pixel 2 (not shown), and an inter-pixel isolation section 32-2 is provided on the right side to isolate it from PD 31-3.

[0103] An inter-pixel isolation portion 32-3 is provided between PD31-3 and PD31-9, an inter-pixel isolation portion 32-4 is provided between PD31-9 and PD31-11, and an inter-pixel isolation portion 32-5 is provided between PD31-11 and PD31 (not shown) of the adjacent pixel 2. The inter-pixel isolation portion 32 can be made of an oxide film.

[0104] A cell well 35-1 and a flat isolation section 33-1 are provided above the inter-pixel isolation section 32-1 in the drawing. A cell well 35-2 and a flat isolation section 33-2 are provided above the inter-pixel isolation section 32-2 in the drawing. A cell well 35-3 is provided above the inter-pixel isolation section 32-3 in the drawing, and a flat isolation section 33-3, a channel region 37 of the amplification transistor 26, and a flat isolation section 33-4 are provided above the cell well 35-3 in the drawing.

[0105] A cell well 35-4 and a flat isolation section 33-5 are provided above the inter-pixel isolation section 32-4 in the drawing. A cell well 35-5 and a flat isolation section 33-6 are provided above the inter-pixel isolation section 32-5 in the drawing. The cell well 35-5 and the flat isolation section 33-6 are regions in which P-type impurities are diffused, and are provided to isolate pixels (elements).

[0106] A transfer gate 22-1 is provided on PD31-1, which is located between FLAT separation unit 33-1 and FLAT separation unit 33-2. A transfer gate 22-3 is provided on PD31-3, which is located between FLAT separation unit 33-2 and FLAT separation unit 33-3. A transfer gate 22-9 is provided on PD31-9, which is located between FLAT separation unit 33-4 and FLAT separation unit 33-5. A transfer gate 22-11 is provided on PD31-11, which is located between FLAT separation unit 33-5 and FLAT separation unit 33-6.

[0107] The active area and the arrangement of transistors will be further explained with reference to Figure 19. Figure 19 is a diagram showing a large pixel group 50g-1 (on the right side of the figure) and a large pixel group 50g-2 (on the left side of the figure) that are adjacent in the horizontal direction. The pixels 2 are separated by inter-pixel separation sections 32 (Figure 18), and an element separation section is provided in the active area of ​​each pixel 2. The element separation section is, for example, a cell well 35 or a flat separation section 33.

[0108] The active region 70-1 is provided with a reset transistor 25-1. The active region 70-2 is provided with a select transistor 27-1, an amplifying transistor 26-1, and a reset transistor 25-2. The active region 70-3 is provided with a select transistor 27-2 and an amplifying transistor 26-2.

[0109] The active region 70-1 is formed across the large pixel group 50g-1 and a large pixel group 50g (not shown) located to the right of the large pixel group 50g-1. The active region 70-2 is formed across the large pixel group 50g-1 and a large pixel group 50g-2 located to the left of the large pixel group 50g-1. The active region 70-3 is formed across the large pixel group 50g-2 and a large pixel group 50g (not shown) located to the left of the large pixel group 50g-2.

[0110] Focus on the large pixel group 50g-1. Pixels 2-1 to 2-16 arranged within the large pixel group 50g-1 use a reset transistor 25-1 arranged in the active region 70-1, and a selection transistor 27-1 and an amplification transistor 26-1 arranged in the active region 70-2. Pixel 2 within the large pixel group 50g-1 performs processing using a transistor arranged in the active region 70-2 formed within its own large pixel group 50g-1 and a transistor arranged in the active region 70-1 formed across the other large pixel groups 50g.

[0111] By adopting such a configuration, the transistors can be arranged so that the distance between the wirings 40 is the shortest.

[0112] The power supply VDD28 is configured to be shared by the large pixel group 50g. The power supply VDD28-2 is provided in an active region 70-2 formed across the large pixel group 50g-1 and the large pixel group 50g-2, and is provided at the boundary between the large pixel group 50g-1 and the large pixel group 50g-2, and is configured to be shared by the pixels 2 arranged in both the large pixel group 50g-1 and the large pixel group 50g-2.

[0113] The distance between adjacent FDs 23 will be further described with reference to Fig. 20. Fig. 20 shows an example of the planar configuration of superpixel groups 50g-1 and 50g-2 that are adjacent to each other and aligned vertically.

[0114] 20, one pixel 2 is formed with a length A in both the vertical and horizontal directions. The length of one side of a pixel 2 is the distance from the center to the center of the inter-pixel isolation portion 32 between pixels 2. For example, the distance from the center of the inter-pixel isolation portion 32 above pixel 2-11 shown in the upper left of the figure to the inter-pixel isolation portion 32 below is length A.

[0115] Length A is also the distance from the center of inter-pixel isolation portion 32 to contact 24 connected to FD 23. For example, referring to FIG. 20, the distance from contact 24-1 in small pixel group 20-1 located at the upper left of large pixel group 50g-1 to the center of inter-pixel isolation portion 32 provided between contact 24-1 and the adjacent large pixel group 50g (not shown) located at the upper side in the figure is length A.

[0116] Arranged in a row in the horizontal direction in the center of the large pixel group 50g-1 are contact 24-5 provided on FD23-5, contact 24-6 connected to the amplification transistor 26, contact 24-7 connected to the vertical signal line 9, and contact 24-8 connected to the power supply VDD.

[0117] The distance from the center of the inter-pixel isolation portion 32 between the pixels 2 in the small pixel group 20 to the contact 24 arranged in the center of the large pixel group 50g-1 is length B. Since the center of the inter-pixel isolation portion 32 between the pixels 2 in the small pixel group 20 is also the position where the contact 24 connected to the FD 23 is located, the distance between the contact 24 connected to the FD 23 and the contact 24 connected to the transistor is length B.

[0118] For example, the distance between the contact 24-1 at the center of the small pixel group 20-1 and the contact 24-6 connected to the amplification transistor 26 in the large pixel group 50g-1 is length B.

[0119] 6, in the large pixel group 50g shown in Fig. 20, the horizontal length of each PD 31 is set to length C. The length of the PDs 31 arranged in the small pixel group 20 is set to length C, and the size of the PDs 31 in each pixel 2 is set to be uniform.

[0120] There is a relationship of length A<length B, and the spacing at which the FDs 23 are arranged will be explained below, focusing on length A and length B. The distance between FD23-1 and FD23-3 within large pixel group 50g-1 is the sum of the distance between the contact 24-1 of FD23-1 and the contact 24-6 of the amplifier transistor 26 (length B) and the distance between the contact 24-6 of the amplifier transistor 26 and the contact 24-3 of FD23-3 (length B), so is (2 × length B).

[0121] The distance between FD23-3 in large pixel group 50g-1 and FD23-11 in large pixel group 50g-2 is the sum of the distance from the center of inter-pixel separation section 32 to contact 24-3 of FD23-3 (length A) and the distance from the center of inter-pixel separation section 32 to contact 24-11 of FD23-11 (length A), so is (2 x length A).

[0122] Contacts 24-1, 24-3, and 24-11 are adjacently arranged in a straight line. The distance between contacts 24-1 and 24-3 is (2 × length B), while the distance between contacts 24-3 and 24-11 is (2 × length A), which are different distances. In other words, in this case, the distance between FD23-1 and FD23-3, which are adjacent to each other, is different from the distance between FD23-3 and FD23-11, which are adjacent to each other. In other words, the distances between FD23 are not equal, but are different.

[0123] In this way, the FD23 and transistors are arranged so that the distance between adjacent FD23s with a transistor (area in which the transistor is arranged) between them is different from the distance between adjacent FD23s without a transistor (area in which the transistor is arranged) between them.

[0124] The FDs 23 are arranged so that they are spaced apart from one another at different distances, but the sizes of the PDs 31 are configured to be equal, as in the case described with reference to Fig. 6. To make the sizes of the PDs 31 equal, for example, in the cross-sectional configuration example shown in Fig. 18, the cell well 35-3 below the amplifying transistor 26 is formed larger than the other cell wells 35, and PD31-3 and PD31-9 are adjusted so that they are not larger than the other PDs 31.

[0125] With this configuration, even if the photodetector 1 is miniaturized, it is possible to maintain the area for arranging the transistors while ensuring the charge transfer area, thereby achieving both the transistor characteristics and the charge transfer characteristics.

[0126] In the seventh embodiment, as in the first embodiment, the distance between adjacent FDs 23 is different between where a transistor is sandwiched and where it is not sandwiched. The size of the PD 31 is adjusted to be the same in each pixel 2. Therefore, as in the first embodiment, even if the photodetector 1 is miniaturized, it is possible to ensure a charge transfer area while maintaining the area for arranging the transistor, thereby achieving both transistor characteristics and charge transfer characteristics.

[0127] <Eighth embodiment> Fig. 21 shows an example of the planar configuration of the superpixel group 50h in the eighth embodiment, and Fig. 22 shows an example of the cross-sectional configuration of the superpixel group 50h taken along line A-A' in Fig. 21. In the superpixel group 50h in the eighth embodiment shown in Figs. 21 and 22, parts that are the same as those in the superpixel group 50g in the seventh embodiment shown in Figs. 17 and 18 are designated by the same reference numerals, and descriptions thereof will be omitted where appropriate.

[0128] 21 and 22, the large pixel group 50h in the second embodiment is similar to the large pixel group 50g in the seventh embodiment except that the transfer gates 22h have a vertical structure. As shown in Fig. 22, the transfer gates 22h of the transfer transistors are formed by combining a planar electrode provided in a planar shape on the front surface of the semiconductor substrate with a vertical electrode provided vertically within the semiconductor substrate.

[0129] 21, the vertical electrode portion of the transfer gate 22h is formed in a circular shape in a plan view. The vertical electrode portion is formed in a circular shape or a polygonal shape.

[0130] By configuring the transfer gate 22h to have a vertical electrode, the transfer efficiency can be improved.

[0131] In the eighth embodiment, as in the first embodiment, the distance between adjacent FDs 23 is different between where a transistor is sandwiched and where it is not sandwiched. The size of the PD 31 is adjusted to be the same in each pixel 2. Therefore, as in the first embodiment, even if the photodetector 1 is miniaturized, it is possible to secure a charge transfer area while maintaining the area for arranging the transistor, thereby achieving both transistor characteristics and charge transfer characteristics.

[0132] <Ninth embodiment> Fig. 23 shows an example of the planar configuration of the superpixel group 50i in the ninth embodiment, Fig. 24A shows an example of the cross-sectional configuration of the superpixel group 50i taken along line A-A' in Fig. 23, and Fig. 24B is a diagram showing an example of the cross-sectional configuration of the superpixel group 50i taken along line B-B' in Fig. 23. In the superpixel group 50i in the ninth embodiment shown in Figs. 23 and 24, parts that are the same as those in the superpixel group 50g in the seventh embodiment shown in Figs. 17 and 18 are designated by the same reference numerals, and descriptions thereof will be omitted where appropriate.

[0133] The superpixel group 50i in the ninth embodiment shown in Figures 23 and 24 differs from the superpixel group 50g in the seventh embodiment in that the transfer gates 22i are transfer gates having a vertical structure, but is otherwise similar.

[0134] As shown in Fig. 24, the transfer gate 22i of the transfer transistor is configured in a shape that combines a planar electrode provided in a planar shape on the front surface of the semiconductor substrate and a vertical electrode provided vertically within the semiconductor substrate. The transfer gate 22i is formed in a shape that sandwiches a portion corresponding to the inter-pixel isolation portion. The transfer gate 22i is formed in a Π shape, similar to the transfer gate 22c in the third embodiment described with reference to Figs. 9 and 10.

[0135] 24A, for example, an STI 61-3 is formed on a cell well 35-2 (on the substrate surface side) formed in the inter-pixel isolation portion 32-2 provided between PD31-1 and PD31-3. A transfer gate 22i-1 of PD31-1 and a transfer gate 22i-3 of PD31-3 are formed on either side of the STI 61-3. The other transfer gates 22i are also formed to have vertical electrodes in contact with the STI 61.

[0136] B of Figure 24 is a diagram showing an example of the cross-sectional configuration of the large pixel group 50i taken along line B-B' in Figure 23. Pixels 2-5, 2-7, and 2-8 are arranged along line B-B'. As shown in B of Figure 24, an STI 61-7 is formed on the substrate surface side between PD 31-5 included in pixel 2-5 and PD 31-7 included in pixel 2-7, and a transfer gate 22i-5 of the transfer transistor of pixel 2-5 and a transfer gate 22i-7 of the transfer transistor of pixel 2-7 are configured with vertical electrodes so as to sandwich (contact) this STI 61-3.

[0137] 24B, the transfer gate 22i-7 arranged on the pixel 2-7 has vertical electrodes formed on both ends of the transfer gate 22i-7 so as to sandwich the PD 31-7, and a flat electrode provided on the substrate is formed on the top of the transfer gate 22i-7. The transfer gate 22i-7 is formed in a shape that appears to be Π-shaped in cross section.

[0138] In the ninth embodiment, the transfer gates 22i of the transfer transistors are configured close to each other, and therefore, in order to reduce the influence thereof, an STI 61 is provided between the transfer gates 22i. The STI 61 can be formed of an oxide film.

[0139] 23, the vertical electrode portion of the transfer gate 22i is formed in a trapezoidal shape in a plan view, with its bottom side facing the STI 61. Note that the vertical electrode portion of the transfer gate 22i is not limited to a trapezoidal shape in a plan view, and may have another shape.

[0140] By configuring the transfer gate 22i to have a vertical electrode, the transfer efficiency can be improved.

[0141] In the ninth embodiment, as in the first embodiment, the distance between adjacent FDs 23 is different between where a transistor is sandwiched and where it is not. The size of the PD 31 is adjusted to be the same in each pixel 2. Therefore, as in the first embodiment, even if the photodetector 1 is miniaturized, it is possible to ensure a charge transfer area while maintaining the area for arranging the transistor, thereby achieving both transistor characteristics and charge transfer characteristics.

[0142] <Tenth embodiment> Figure 25 shows an example of the planar configuration of the superpixel group 50j in the tenth embodiment, and Figure 26 is a diagram showing an example of the cross-sectional configuration of the superpixel group 50j taken along line A-A' in Figure 25. In the superpixel group 50j in the tenth embodiment shown in Figures 25 and 26, parts that are the same as those in the superpixel group 50g in the seventh embodiment shown in Figures 17 and 18 are designated by the same reference numerals, and descriptions thereof will be omitted where appropriate.

[0143] The large pixel group 50j in the tenth embodiment shown in Figures 25 and 26 differs from the large pixel group 50g in the seventh embodiment in that the element isolation in the region where the transistors are arranged is performed by STI, but is otherwise similar.

[0144] An STI 71 is formed around the active region where the reset transistor 25, the selection transistor 27, and the amplification transistor 26 are arranged, and in the lateral direction of the central region of the large pixel group 50j.

[0145] In cross section, as shown in FIG. 26, STIs 71 are formed on both sides of the channel region 37 of the amplifying transistor 26 to isolate it from other elements.

[0146] In the tenth embodiment, as in the first embodiment, the distance between adjacent FDs 23 is different between where a transistor is sandwiched and where it is not sandwiched. The size of the PD 31 is adjusted to be the same in each pixel 2. Therefore, as in the first embodiment, even if the photodetector 1 is miniaturized, it is possible to ensure a charge transfer area while maintaining the area for arranging the transistor, thereby achieving both transistor characteristics and charge transfer characteristics.

[0147] <Eleventh embodiment> Figure 27 shows an example of the planar configuration of the superpixel group 50k in the eleventh embodiment, and Figure 28 is a diagram showing an example of the cross-sectional configuration of the superpixel group 50k taken along line A-A' in Figure 27. In the superpixel group 50k in the eleventh embodiment shown in Figures 27 and 28, parts that are the same as those in the superpixel group 50h in the eighth embodiment shown in Figures 21 and 22 are designated by the same reference numerals, and descriptions thereof will be omitted where appropriate.

[0148] The large pixel group 50k in the eleventh embodiment shown in Figures 27 and 28 differs from the large pixel group 50h in the eighth embodiment in that the element isolation in the region where the transistors are arranged is performed by STI, but is otherwise similar.

[0149] An STI 71 is formed around the active area where the reset transistor 25, the selection transistor 27, and the amplification transistor 26 are arranged, in the lateral direction of the central area of ​​the large pixel group 50k.

[0150] 28, in cross section, STI 71 is formed on both sides of the channel region 37 of the amplifier transistor 26 to isolate it from other elements. Also, the transfer gate 22k has a vertical electrode.

[0151] In the eleventh embodiment, as in the first embodiment and the like, the distance between adjacent FDs 23 is configured to be different between where a transistor is sandwiched and where it is not sandwiched. The size of the PD 31 is adjusted to be the same in each pixel 2. Therefore, as in the seventh embodiment, even if the photodetector 1 is miniaturized, it is possible to secure a charge transfer area while maintaining the area for arranging the transistor, and it is possible to achieve both transistor characteristics and charge transfer characteristics.

[0152] <Twelfth embodiment> Fig. 29 shows an example of the planar configuration of the superpixel group 50m in the twelfth embodiment, Fig. 30A shows an example of the cross-sectional configuration of the superpixel group 50m taken along line A-A' in Fig. 29, and Fig. 30B is a diagram showing an example of the cross-sectional configuration of the superpixel group 50m taken along line B-B' in Fig. 29. In the superpixel group 50m in the twelfth embodiment shown in Figs. 29 and 30, parts that are the same as those in the superpixel group 50i in the ninth embodiment shown in Figs. 23 and 24 are designated by the same reference numerals, and descriptions thereof will be omitted where appropriate.

[0153] The large pixel group 50m in the twelfth embodiment shown in Figures 29 and 30 differs from the large pixel group 50i in the ninth embodiment in that the element isolation in the region where the transistors are arranged is performed by STI, but is otherwise similar.

[0154] An STI 71 is formed around the active area where the reset transistor 25, the selection transistor 27, and the amplification transistor 26 are arranged, in the lateral direction of the central area of ​​the large pixel group 50.

[0155] 30A, in cross section, STI 71 is formed on both sides of the channel region 37 of the amplifier transistor 26 to isolate it from other elements. The transfer gate 22m has a vertical electrode, is formed in a Π shape, and is configured to sandwich the PD 31.

[0156] In the twelfth embodiment, as in the first embodiment, the distance between adjacent FDs 23 is different between where a transistor is sandwiched and where it is not sandwiched. The size of the PD 31 is adjusted to be the same in each pixel 2. Therefore, as in the first embodiment, even if the photodetector 1 is miniaturized, it is possible to ensure a charge transfer area while maintaining the area for arranging the transistor, thereby achieving both transistor characteristics and charge transfer characteristics.

[0157] <Thirteenth embodiment> Figure 31 shows an example of the planar configuration of the superpixel group 50n in the thirteenth embodiment, and Figure 32 shows an example of the cross-sectional configuration of the superpixel group 50n taken along line A-A' in Figure 31. In the superpixel group 50n in the thirteenth embodiment shown in Figures 31 and 32, parts that are the same as those in the superpixel group 50a in the first embodiment shown in Figures 2 and 3 are designated by the same reference numerals, and their description will be omitted where appropriate.

[0158] The large pixel groups 50n in the thirteenth embodiment differ from the large pixel groups 50a in the first embodiment in the area in which the active regions are formed and the arrangement of transistors arranged in the active regions, but are otherwise similar. The large pixel groups 50n in the thirteenth embodiment differ from the large pixel groups 50a in the first embodiment in that the transistors used in one large pixel group 50n are arranged in the active region provided within that large pixel group 50n.

[0159] 31, an active region 70 is provided within the large pixel group 50n. The active region 70 includes a reset transistor 25, an amplifier transistor 26, and a selection transistor 27. Signals from each pixel 2, from pixel 2-1 to pixel 2-16, arranged within the large pixel group 50n are processed by the reset transistor 25, amplifier transistor 26, and selection transistor 27, which are also arranged within the active region 70. The pixels 2 within the large pixel group 50n are configured to perform processing using transistors arranged within the active region 70 formed within their own large pixel group 50n.

[0160] When each pixel 2 in the large pixel group 50n is configured to perform processing using a transistor arranged in one active region 70 within such a large pixel group 50n, wiring 40 including a bent portion is arranged as shown in Figure 31.

[0161] The pixels 2-1 to 2-4 of the small pixel group 20-1 are provided with transfer gates 22-1 to 22-4, respectively, and an FD 23-1 is provided in the center of the area where the transfer gates 22-1 to 22-4 are arranged. The FD 23-1 is provided with a contact 24-1, and the contact 24-1 is connected to a wiring 40 in a stacked wiring layer (not shown).

[0162] The pixels 2-5 to 2-8 of the small pixel group 20-2 are provided with transfer gates 22-5 to 22-8, respectively, and an FD 23-2 is provided in the center of the area where the transfer gates 22-5 to 22-8 are arranged. The FD 23-2 is provided with a contact 24-2, and the contact 24-2 is connected to a wiring 40 in a stacked wiring layer (not shown).

[0163] The pixels 2-9 to 2-12 of the small pixel group 20-3 are provided with transfer gates 22-9 to 22-12, respectively, and an FD 23-3 is provided in the center of the area where the transfer gates 22-9 to 22-12 are arranged. The FD 23-3 is provided with a contact 24-3, and the contact 24-3 is connected to a wiring 40 in a stacked wiring layer (not shown).

[0164] The pixels 2-13 to 2-16 of the small pixel group 20-4 include transfer gates 22-13 to 22-16, respectively, and FDs 23-4 are provided at the centers of the transfer gates 22-13 to 22-16. The FDs 23-4 are provided with contacts 24-4, which are connected to wiring 40 in a stacked wiring layer (not shown).

[0165] The FDs 23-1 to 23-4 provided in each of the small pixel groups 20-1 to 20-4 are connected to a wiring 40. The wiring 40 is also connected to a contact 24-6 of the amplification transistor 26 provided in the center of the large pixel group 50n. The wiring 40 connecting the FDs 23-1 to 23-4 (contacts 24-1 to 24-4) and the contact 24-6 is arranged in an H shape. This shape allows the wiring 40 to be routed as quickly as possible.

[0166] The wiring 40 is also connected via a contact 24-5 to an FD 23-5 that is provided above the center of the large pixel group 50 in the drawing. In the example shown in Fig. 31, the contact 24-2 and the contact 24-5 are connected, and therefore the wiring 40 provided between the contact 24-2 and the contact 24-5 has a bent portion.

[0167] In the superpixel group 50n in the thirteenth embodiment, the FDs 23-1 to 23-5 also function as a single FD, and are configured to be shared by the pixels 2-1 to 2-16 in the superpixel group 50.

[0168] An example of the cross-sectional configuration along line A-A' in FIG. 31 will be described further with reference to FIG. 32. Pixel 2-1, pixel 2-2, reset transistor 25, pixel 2-5, and pixel 2-6 are arranged in this order along line A-A'. In FIG. 31, the lower side is the light incident surface, and the upper side is the wiring layer (not shown). An inter-pixel separator 32-1 is provided on the left side of PD 31-1 to separate it from pixel 2 (not shown), and an inter-pixel separator 32-2 is provided on the right side to separate it from PD 31-2.

[0169] An inter-pixel isolation portion 32-3 is provided between PD31-2 and PD31-5, an inter-pixel isolation portion 32-4 is provided between PD31-5 and PD31-6, and an inter-pixel isolation portion 32-5 is provided between PD31-6 and PD31 (not shown) of the adjacent pixel 2. The inter-pixel isolation portion 32 can be made of an oxide film.

[0170] A cell well 35-1 and a flat isolation section 33-1 are provided above the inter-pixel isolation section 32-1 in the drawing. A cell well 35-2 and a flat isolation section 33-2 are provided above the inter-pixel isolation section 32-2 in the drawing. A cell well 35-3 is provided above the inter-pixel isolation section 32-3 in the drawing, and a flat isolation section 33-3, a channel region 37 of the reset transistor 25, and a flat isolation section 33-4 are provided above the cell well 35-3 in the drawing.

[0171] A cell well 35-4 and a flat isolation section 33-5 are provided above the inter-pixel isolation section 32-4 in the drawing. A cell well 35-5 and a flat isolation section 33-6 are provided above the inter-pixel isolation section 32-5 in the drawing. The cell well 35-5 and the flat isolation section 33-6 are regions in which P-type impurities are diffused, and are provided to isolate pixels (elements).

[0172] A transfer gate 22-1 is provided on PD 31-1, which is located between FLAT separation unit 33-1 and FLAT separation unit 33-2. A transfer gate 22-2 is provided on PD 31-2, which is located between FLAT separation unit 33-2 and FLAT separation unit 33-3. A transfer gate 22-5 is provided on PD 31-5, which is located between FLAT separation unit 33-4 and FLAT separation unit 33-5. A transfer gate 22-6 is provided on PD 31-6, which is located between FLAT separation unit 33-5 and FLAT separation unit 33-6.

[0173] The distance relationship between adjacent FDs 23 described with reference to Figures 5 and 6 also applies to the superpixel groups 50n shown in Figures 31 and 32. For example, the distance between adjacent FDs 23 in adjacent superpixel groups 50n is (2 x length A), and the distance between adjacent FDs 23 across a transistor in the superpixel group 50n is (2 x length B).

[0174] The FDs 23 and transistors are arranged so that the distance between adjacent FDs 23 with a transistor between them is different from the distance between adjacent FDs 23 without a transistor between them.

[0175] The FDs 23 are arranged so that they are spaced apart from one another at different distances, but the sizes of the PDs 31 are configured to be equal, as in the case described with reference to Fig. 6. To make the sizes of the PDs 31 equal, for example, in the cross-sectional configuration example shown in Fig. 32, the cell well 35-3 below the amplifying transistor 26 is formed larger than the other cell wells 35, and PD31-2 and PD31-5 are adjusted so that they are not larger than the other PDs 31.

[0176] With this configuration, even if the photodetector 1 is miniaturized, it is possible to maintain the area for arranging the transistors while ensuring the charge transfer area, thereby achieving both the transistor characteristics and the charge transfer characteristics.

[0177] In the thirteenth embodiment, as in the first embodiment and the like, the distance between adjacent FDs 23 is configured to be different between where a transistor is sandwiched and where it is not sandwiched. The size of the PD 31 is adjusted to be the same in each pixel 2. Therefore, as in the first embodiment, even if the photodetector 1 is miniaturized, it is possible to ensure a charge transfer area while maintaining the area for arranging the transistor, and it is possible to achieve both transistor characteristics and charge transfer characteristics.

[0178] <Fourteenth embodiment> Fig. 33 shows an example of the planar configuration of the superpixel group 50p in the fourteenth embodiment, and Fig. 34 shows an example of the cross-sectional configuration of the superpixel group 50p taken along line A-A' in Fig. 33. In the superpixel group 50p in the fourteenth embodiment shown in Figs. 33 and 34, parts that are the same as those in the superpixel group 50n in the thirteenth embodiment shown in Figs. 31 and 32 are designated by the same reference numerals, and descriptions thereof will be omitted where appropriate.

[0179] The large pixel group 50p in the fourteenth embodiment shown in Figures 33 and 34 differs from the large pixel group 50n in the thirteenth embodiment in that the transfer gate 22p is a transfer gate having a vertical structure, but is otherwise similar. As shown in Figure 34, the transfer gate 22p of the transfer transistor has a shape that combines a planar electrode provided in a planar shape on the front surface of the semiconductor substrate and a vertical electrode provided vertically within the semiconductor substrate.

[0180] 33, the vertical electrode portion of the transfer gate 22 is formed in a circular shape in a plan view. The vertical electrode portion is formed in a circular shape or a polygonal shape.

[0181] By configuring the transfer gate 22p to have a vertical electrode, the transfer efficiency can be improved.

[0182] In the fourteenth embodiment, as in the first embodiment and the like, the distance between adjacent FDs 23 is configured to be different between where a transistor is sandwiched and where it is not sandwiched. The size of the PD 31 is adjusted to be the same in each pixel 2. Therefore, as in the thirteenth embodiment, even if the photodetector 1 is miniaturized, it is possible to secure a charge transfer area while maintaining the area for arranging the transistor, and it is possible to achieve both transistor characteristics and charge transfer characteristics.

[0183] <Fifteenth embodiment> Fig. 35 shows an example of the planar configuration of the superpixel group 50q in the fifteenth embodiment, Fig. 36A shows an example of the cross-sectional configuration of the superpixel group 50q taken along line A-A' in Fig. 35, and Fig. 36B is a diagram showing an example of the cross-sectional configuration of the superpixel group 50q taken along line B-B' in Fig. 35. In the superpixel group 50q in the fifteenth embodiment shown in Figs. 35 and 36, parts that are the same as those in the superpixel group 50n in the thirteenth embodiment shown in Figs. 31 and 32 are designated by the same reference numerals, and descriptions thereof will be omitted where appropriate.

[0184] The superpixel group 50q in the fifteenth embodiment shown in Figures 35 and 36 differs from the superpixel group 50n in the thirteenth embodiment in that the transfer gate 22q is a transfer gate having a vertical structure, but is otherwise similar.

[0185] 36, the transfer gate 22q of the transfer transistor is configured in a shape that combines a planar electrode provided in a planar shape on the front surface of the semiconductor substrate and a vertical electrode provided vertically within the semiconductor substrate. The transfer gate 22q is also formed in a shape that sandwiches the portion corresponding to the inter-pixel isolation portion 32.

[0186] 36A, an STI 61-9 is formed on the cell well 35-12 (on the substrate surface side) provided between PD31-9 and PD31-10. A transfer gate 22q-9 of PD31-9 and a transfer gate 22q-10 of PD31-10 are formed so as to sandwich (contact) this STI 61-9. An STI 61 is also formed between the other pixels 2, and a transfer gate 22q of PD31 is formed so as to sandwich (contact) this STI 61.

[0187] B of Figure 36 is a diagram showing an example of the cross-sectional configuration of the large pixel group 50q taken along line B-B' in Figure 35. Pixels 2-1, 2-3, and 2-4 are arranged along line B-B'. As shown in B of Figure 36, an STI 61-3 is formed on the substrate surface side between PD 31-1 included in pixel 2-1 and PD 31-3 included in pixel 2-3. The transfer gate 22q-1 of the transfer transistor of pixel 2-1 and the transfer gate 22q-3 of the transfer transistor of pixel 2-3 are configured with vertical electrodes, sandwiching the STI 61-3.

[0188] 36B, the transfer gate 22q-3 arranged on the pixel 2-3 has vertical electrodes formed on both ends of the transfer gate 22q-3, sandwiching the PD 31-3, and a flat electrode provided on the substrate formed on the top of the transfer gate 22q-3. The transfer gate 22q-3 is formed in a shape that appears to be Π-shaped in cross section.

[0189] In the fifteenth embodiment, the transfer gates 22q of the transfer transistors are configured close to each other, and therefore, in order to reduce the influence thereof, an STI 61 is provided between the transfer gates 22q. The STI 61 can be formed of an oxide film.

[0190] 35, the vertical electrode portion of the transfer gate 22q is formed in a trapezoidal shape in a plan view, with its bottom side facing the STI 61. Note that the vertical electrode portion of the transfer gate 22q is not limited to a trapezoidal shape in a plan view, and may have another shape.

[0191] By configuring the transfer gate 22q to have a vertical electrode, the transfer efficiency can be improved.

[0192] In the fifteenth embodiment, as in the first embodiment and the like, the distance between adjacent FDs 23 is configured to be different between where a transistor is sandwiched and where it is not sandwiched. The size of the PD 31 is adjusted to be the same in each pixel 2. Therefore, as in the first embodiment, even if the photodetector 1 is miniaturized, it is possible to ensure a charge transfer area while maintaining the area for arranging the transistor, and it is possible to achieve both transistor characteristics and charge transfer characteristics.

[0193] <16th embodiment> Fig. 37 shows an example of the planar configuration of the superpixel group 50r in the sixteenth embodiment, and Fig. 38 is a diagram showing an example of the cross-sectional configuration of the superpixel group 50r taken along line A-A' in Fig. 37. In the superpixel group 50r in the sixteenth embodiment shown in Figs. 37 and 38, parts that are the same as those in the superpixel group 50n in the thirteenth embodiment shown in Figs. 31 and 32 are designated by the same reference numerals, and descriptions thereof will be omitted where appropriate.

[0194] The large pixel group 50r in the sixteenth embodiment shown in Figures 37 and 38 differs from the large pixel group 50n in the thirteenth embodiment in that the element isolation in the region where the transistors are arranged is performed by STI, but is otherwise similar.

[0195] An STI 71 is formed around the active area where the reset transistor 25, the selection transistor 27, and the amplification transistor 26 are arranged, in the vertical direction of the central area of ​​the large pixel group 50.

[0196] In cross section, as shown in FIG. 38, STIs 71 are formed on both sides of the channel region 37 of the reset transistor 25 to isolate it from other elements.

[0197] In the sixteenth embodiment, as in the first embodiment and the like, the distance between adjacent FDs 23 is configured to be different between where a transistor is sandwiched and where it is not sandwiched. The size of the PD 31 is adjusted to be the same in each pixel 2. Therefore, as in the first embodiment, even if the photodetector 1 is miniaturized, it is possible to ensure a charge transfer area while maintaining the area for arranging the transistor, and it is possible to achieve both transistor characteristics and charge transfer characteristics.

[0198] <Seventeenth embodiment> Figure 39 shows an example of the planar configuration of the superpixel group 50s in the seventeenth embodiment, and Figure 40 is a diagram showing an example of the cross-sectional configuration of the superpixel group 50s taken along line A-A' in Figure 39. In the superpixel group 50s in the seventeenth embodiment shown in Figures 39 and 40, parts that are the same as those in the superpixel group 50p in the fourteenth embodiment shown in Figures 33 and 34 are designated by the same reference numerals, and descriptions thereof will be omitted where appropriate.

[0199] The large pixel group 50s in the seventeenth embodiment shown in Figures 39 and 40 differs from the large pixel group 50p in the fourteenth embodiment in that the element isolation in the region where the transistors are arranged is performed by STI, but is otherwise similar.

[0200] An STI 71 is formed around the active area where the reset transistor 25, the selection transistor 27, and the amplification transistor 26 are arranged, in the vertical direction of the central area of ​​the large pixel group 50.

[0201] 40, in a cross-sectional view, STIs 71 are formed on both sides of the channel region 37 of the reset transistor 25 to isolate it from other elements. The transfer gate 22s has a vertical electrode.

[0202] In the seventeenth embodiment, as in the first embodiment, the distance between adjacent FDs 23 is different between where a transistor is sandwiched and where it is not sandwiched. The size of the PE 31 is adjusted to be the same in each pixel 2. Therefore, as in the first embodiment, even if the photodetector 1 is miniaturized, it is possible to secure a charge transfer area while maintaining the area for arranging the transistor, thereby achieving both transistor characteristics and charge transfer characteristics.

[0203] <Eighteenth embodiment> Fig. 41 shows an example of the planar configuration of the superpixel group 50t in the eighteenth embodiment, Fig. 42A shows an example of the cross-sectional configuration of the superpixel group 50t taken along line A-A' in Fig. 41, and Fig. 42B is a diagram showing an example of the cross-sectional configuration of the superpixel group 50t taken along line B-B' in Fig. 41. In the superpixel group 50t in the eighteenth embodiment shown in Figs. 41 and 42, parts that are the same as those in the superpixel group 50q in the fifteenth embodiment shown in Figs. 35 and 36 are designated by the same reference numerals, and descriptions thereof will be omitted where appropriate.

[0204] The large pixel group 50t in the eighteenth embodiment shown in Figures 41 and 42 differs from the large pixel group 50q in the fifteenth embodiment in that the element isolation in the region where the transistors are arranged is performed by STI, but is otherwise similar.

[0205] An STI 71 is formed around the active area where the reset transistor 25, the selection transistor 27, and the amplification transistor 26 are arranged, in the vertical direction of the central area of ​​the large pixel group 50.

[0206] 42A, in a cross-sectional view, STIs 71 are formed on both sides of the channel region 37 of the amplifier transistor 26 to isolate it from other elements. The transfer gate 22t has vertical electrodes, is formed in a Π shape, and is configured to sandwich the PD 31.

[0207] In the 18th embodiment, as in the first embodiment and the like, the distance between adjacent FDs 23 is configured to be different between where a transistor is sandwiched and where it is not sandwiched. The size of the PD 31 is adjusted to be the same in each pixel 2. Therefore, as in the 11th embodiment, even if the photodetector 1 is miniaturized, it is possible to ensure a charge transfer area while maintaining the area for arranging the transistor, and it is possible to achieve both transistor characteristics and charge transfer characteristics.

[0208] <Nineteenth embodiment> Fig. 43 shows an example of the planar configuration of the superpixel group 50u in the nineteenth embodiment, and Fig. 44 shows an example of the cross-sectional configuration of the superpixel group 50u taken along line A-A' in Fig. 43. In the superpixel group 50u in the nineteenth embodiment shown in Figs. 43 and 44, parts that are the same as those in the superpixel group 50n in the thirteenth embodiment shown in Figs. 31 and 32 are designated by the same reference numerals, and descriptions thereof will be omitted where appropriate.

[0209] 43, the 19th embodiment also has a configuration in which 16 pixels 2 share the FD 23. The pixels 2-1 to 2-4 of the small pixel group 20-1 each include a transfer gate 22-1 to 22-4, and the FD 23-1 is provided in the center of the area in which the transfer gates 22-1 to 22-4 are arranged. The FD 23-1 is provided with a contact 24-1, and the contact 24-1 is connected to a wiring 40 in a stacked wiring layer (not shown).

[0210] The pixels 2-5 to 2-8 of the small pixel group 20-2 are provided with transfer gates 22-5 to 22-8, respectively, and an FD 23-2 is provided in the center of the area where the transfer gates 22-5 to 22-8 are arranged. The FD 23-2 is provided with a contact 24-2, and the contact 24-2 is connected to a wiring 40 in a stacked wiring layer (not shown).

[0211] The pixels 2-9 to 2-12 of the small pixel group 20-3 are provided with transfer gates 22-9 to 22-12, respectively, and an FD 23-3 is provided in the center of the area where the transfer gates 22-9 to 22-12 are arranged. The FD 23-3 is provided with a contact 24-3, and the contact 24-3 is connected to a wiring 40 in a stacked wiring layer (not shown).

[0212] The pixels 2-13 to 2-16 of the small pixel group 20-4 include transfer gates 22-13 to 22-16, respectively, and FDs 23-4 are provided at the centers of the transfer gates 22-13 to 22-16. The FDs 23-4 are provided with contacts 24-4, which are connected to wiring 40 in a stacked wiring layer (not shown).

[0213] The FDs 23-1 to 23-4 provided in each of the small pixel groups 20-1 to 20-4 are connected to a wiring 40. The wiring 40 is also connected to a contact 24-6 of the amplification transistor 26 provided in the center of the large pixel group 50u. The wiring 40 connecting the FDs 23-1 to 23-4 (contacts 24-1 to 24-4) and the contact 24-6 is arranged in an H shape (a shape obtained by rotating the H by 90 degrees in FIG. 43).

[0214] The wiring 40 is also connected to FD23-5, which is provided to the left of the center of the large pixel group 50u in the drawing, via contact 24-5. In the example shown in Fig. 43, since contact 24-1 and contact 24-5 are connected, the wiring 40 provided between contact 24-1 and contact 24-5 has a shape that includes a bent portion.

[0215] In the superpixel group 50u of the nineteenth embodiment, the FDs 23-1 to 23-5 also function as a single FD, and are configured to be shared by the pixels 2-1 to 2-16 in the superpixel group 50u.

[0216] 43, the reset transistor 25, amplification transistor 26, and selection transistor 27 are arranged in a row in the horizontal direction in the center of the large pixel group 50. Contacts connected to the power supply VDD28 and contacts connected to the vertical signal line 9 (VSL region 29) are also arranged in a row in the horizontal direction together with the transistors in the center of the large pixel group 50. In this way, the large pixel group 50u in the 19th embodiment differs from the large pixel group 50n in the 13th embodiment in that the transistors are arranged in the horizontal direction, but in other respects they are basically the same.

[0217] An example of the cross-sectional configuration along line A-A' in FIG. 43 will be further described with reference to FIG. 44. Pixel 2-5, pixel 2-7, amplifier transistor 26, pixel 2-13, and pixel 2-15 are arranged in this order along line A-A'. In FIG. 43, the lower side is the light incident surface, and the upper side is the wiring layer (not shown) side. Inter-pixel isolation portions 32 are provided between PDs 31. Inter-pixel isolation portions 32 can be formed of an oxide film.

[0218] A cell well 35 and a flat isolation portion 33 are provided above the inter-pixel isolation portion 32 in the drawing. The cell well 35 and the flat isolation portion 33 are regions in which P-type impurities are diffused, and are provided to separate pixels (elements).

[0219] The distance relationship between adjacent FDs 23 described with reference to Figures 5 and 6 also applies to the superpixel groups 50u shown in Figures 43 and 44. For example, the distance between adjacent FDs 23 between adjacent superpixel groups 50u is (2 x length A), and the distance between adjacent FDs 23 across a transistor in a superpixel group 50n is (2 x length B).

[0220] The FDs 23 and transistors are arranged so that the distance between adjacent FDs 23 with a transistor between them is different from the distance between adjacent FDs 23 without a transistor between them.

[0221] The FDs 23 are arranged so that they are spaced apart from one another at different distances, but the sizes of the PDs 31 are configured to be equal, as in the case described with reference to Fig. 6. To make the sizes of the PDs 31 equal, for example, in the cross-sectional configuration example shown in Fig. 44, the cell well 35-7 below the amplifying transistor 26 is formed larger than the other cell wells 35, and adjustments are made so that PD31-7 and PD31-13 are not larger than the other PDs 31.

[0222] With this configuration, even if the photodetector 1 is miniaturized, it is possible to maintain the area for arranging the transistors while ensuring the charge transfer area, thereby achieving both the transistor characteristics and the charge transfer characteristics.

[0223] In the 19th embodiment, as in the first embodiment, the distance between adjacent FDs 23 is configured to be different between where a transistor is sandwiched and where it is not sandwiched. The size of the PD 31 is adjusted to be the same in each pixel 2. Therefore, as in the first embodiment, even if the photodetector 1 is miniaturized, it is possible to ensure a charge transfer area while maintaining the area for arranging the transistor, making it possible to achieve both transistor characteristics and charge transfer characteristics.

[0224] <Twentieth embodiment> Figure 45 shows an example of the planar configuration of the superpixel group 50v in the twentieth embodiment, and Figure 46 is a diagram showing an example of the cross-sectional configuration of the superpixel group 50v taken along line A-A' in Figure 45. In the superpixel group 50v in the nineteenth embodiment shown in Figures 45 and 46, parts that are the same as those in the superpixel group 50u in the nineteenth embodiment shown in Figures 43 and 44 are designated by the same reference numerals, and descriptions thereof will be omitted where appropriate.

[0225] The large pixel group 50v in the twentieth embodiment shown in Figures 45 and 46 differs from the large pixel group 50u in the nineteenth embodiment in that the transfer gate 22v is a transfer gate having a vertical structure, but is otherwise similar. As shown in Figure 46, the transfer gate 22v of the transfer transistor has a shape that combines a planar electrode provided in a planar shape on the front surface of the semiconductor substrate and a vertical electrode provided vertically within the semiconductor substrate.

[0226] 46, the vertical electrode portion of the transfer gate 22v is formed in a circular shape in a plan view. The vertical electrode portion is formed in a circular or polygonal shape.

[0227] By configuring the transfer gate 22v to have a vertical electrode, the transfer efficiency can be improved.

[0228] In the twentieth embodiment, as in the first embodiment and the like, the distance between adjacent FDs 23 is configured to be different between where a transistor is sandwiched and where it is not sandwiched. The size of the PD 31 is adjusted to be the same in each pixel 2. Therefore, as in the first embodiment, even if the photodetector 1 is miniaturized, it is possible to ensure a charge transfer area while maintaining the area for arranging the transistor, and it is possible to achieve both transistor characteristics and charge transfer characteristics.

[0229] <Twenty-first embodiment> Fig. 47 shows an example of the planar configuration of the superpixel group 50w in the 21st embodiment, Fig. 48A shows an example of the cross-sectional configuration of the superpixel group 50w taken along line A-A' in Fig. 47, and Fig. 48B is a diagram showing an example of the cross-sectional configuration of the superpixel group 50w taken along line B-B' in Fig. 47. In the superpixel group 50w in the 21st embodiment shown in Figs. 47 and 48, parts that are the same as those in the superpixel group 50u in the 19th embodiment shown in Figs. 43 and 44 are designated by the same reference numerals, and descriptions thereof will be omitted where appropriate.

[0230] The superpixel group 50w in the 21st embodiment shown in Figures 47 and 48 differs from the superpixel group 50u in the 19th embodiment in that the transfer gate 22w is a transfer gate having a vertical structure, but is otherwise similar.

[0231] As shown in Fig. 48, the transfer gate 22w of the transfer transistor is configured in a shape that combines a planar electrode provided in a planar shape on the front surface of the semiconductor substrate with a vertical electrode provided vertically within the semiconductor substrate. The transfer gate 22w is formed in a shape that sandwiches (contacts) the portion corresponding to the inter-pixel isolation portion. The transfer gate 22w is formed in a Π shape, similar to the transfer gate 22c in the third embodiment described with reference to Figs. 9 and 10.

[0232] 48A, for example, an STI 61-7 is formed on (the substrate surface side of) a cell well 35-6 formed in an inter-pixel isolation portion 32-6 provided between PD31-5 and PD31-7. A transfer gate 22w-5 of PD31-5 and a transfer gate 22w-7 of PD31-7 are formed so as to sandwich (contact) this STI 61-7. The other transfer gate 22w is also formed to have a vertical electrode in contact with the STI 61.

[0233] B of Figure 48 is a diagram showing an example of the cross-sectional configuration of the large pixel group 50w taken along line B-B' in Figure 47. Pixels 2-1, 2-3, and 2-4 are arranged along line B-B'. As shown in B of Figure 48, an STI 61-3 is formed on the substrate surface side between PD 31-1 included in pixel 2-1 and PD 31-3 included in pixel 2-3, and the transfer gate 22w-1 of the transfer transistor of pixel 2-1 and the transfer gate 22w-3 of the transfer transistor of pixel 2-3 are configured with vertical electrodes on either side of the STI 61-3.

[0234] 48B, the transfer gate 22w-3 disposed on the pixel 2-3 has vertical electrodes formed on both ends of the transfer gate 22w-3 so as to sandwich the PD 31-3 therebetween, and a flat electrode provided on the substrate is formed on the top of the transfer gate 22w-3. The transfer gate 22w-3 is formed in a shape that appears to be Π-shaped in cross section.

[0235] In the twentieth embodiment, the transfer gates 22w of the transfer transistors are configured close to each other, and therefore, in order to reduce the influence thereof, an STI 61 is provided between the transfer gates 22w. The STI 61 can be formed of an oxide film.

[0236] 47, the vertical electrode portion of the transfer gate 22w is formed in a trapezoidal shape in a plan view, with its bottom side facing the STI 61. Note that the vertical electrode portion of the transfer gate 22w is not limited to a trapezoidal shape in a plan view, and may have another shape.

[0237] By configuring the transfer gate 22w to have a vertical electrode, the transfer efficiency can be improved.

[0238] In the 21st embodiment, as in the first embodiment, the distance between adjacent FDs 23 is different between where a transistor is sandwiched and where it is not. The size of the PDs 31 is adjusted to be the same in each pixel 2. Therefore, as in the first embodiment, even if the photodetector 1 is miniaturized, it is possible to ensure a charge transfer area while maintaining the area for arranging the transistor, thereby achieving both transistor characteristics and charge transfer characteristics.

[0239] <Twenty-second embodiment> Figure 49 shows an example of the planar configuration of the superpixel group 50x in the 22nd embodiment, and Figure 50 is a diagram showing an example of the cross-sectional configuration of the superpixel group 50x taken along line A-A' in Figure 49. In the superpixel group 50x in the 22nd embodiment shown in Figures 49 and 50, parts that are the same as those in the superpixel group 50u in the 19th embodiment shown in Figures 43 and 44 are designated by the same reference numerals, and descriptions thereof will be omitted where appropriate.

[0240] The large pixel group 50x in the 22nd embodiment shown in Figures 49 and 50 differs from the large pixel group 50u in the 19th embodiment in that the element isolation in the region where the transistors are arranged is performed by STI, but is otherwise similar.

[0241] An STI 71 is formed around the active area where the reset transistor 25, the selection transistor 27, and the amplification transistor 26 are arranged, in the lateral direction of the central area of ​​the large pixel group 50x.

[0242] In cross section, as shown in FIG. 50, STIs 71 are formed on both sides of the channel region 37 of the amplifying transistor 26 to isolate it from other elements.

[0243] In the 22nd embodiment, as in the first embodiment and the like, the distance between adjacent FDs 23 is configured to be different between where a transistor is sandwiched and where it is not sandwiched. The size of the PD 31 is adjusted to be the same in each pixel 2. Therefore, as in the first embodiment, even if the photodetector 1 is miniaturized, it is possible to ensure a charge transfer area while maintaining the area for arranging the transistor, and it is possible to achieve both transistor characteristics and charge transfer characteristics.

[0244] <Twenty-third embodiment> Figure 51 shows an example of the planar configuration of the superpixel group 50y in the 23rd embodiment, and Figure 52 shows an example of the cross-sectional configuration of the superpixel group 50y taken along line A-A' in Figure 51. In the superpixel group 50y in the 23rd embodiment shown in Figures 51 and 52, parts that are the same as those in the superpixel group 50v in the 20th embodiment shown in Figures 45 and 46 are designated by the same reference numerals, and descriptions thereof will be omitted where appropriate.

[0245] The large pixel group 50y in the 23rd embodiment shown in Figures 51 and 52 differs from the large pixel group 50v in the 20th embodiment in that the element isolation in the region where the transistors are arranged is performed by STI, but is otherwise similar.

[0246] An STI 71 is formed around the active area where the reset transistor 25, the selection transistor 27, and the amplification transistor 26 are arranged, in the lateral direction of the central area of ​​the large pixel group 50x.

[0247] 52, in cross section, STI 71 is formed on both sides of the channel region 37 of the amplifier transistor 26 to isolate it from other elements. Also, the transfer gate 22y has a vertical electrode.

[0248] In the 22nd embodiment, as in the first embodiment and the like, the distance between adjacent FDs 23 is configured to be different between where a transistor is sandwiched and where it is not sandwiched. The size of the PD 31 is adjusted to be the same in each pixel 2. Therefore, as in the 18th embodiment, even if the photodetector 1 is miniaturized, it is possible to ensure a charge transfer area while maintaining the area for arranging the transistor, and it is possible to achieve both transistor characteristics and charge transfer characteristics.

[0249] <Twenty-fourth embodiment> Figure 53 shows an example of the planar configuration of the superpixel group 50z in the 24th embodiment, Figure 54A shows an example of the cross-sectional configuration of the superpixel group 50z taken along line A-A' in Figure 53, and Figure 54B is a diagram showing an example of the cross-sectional configuration of the superpixel group 50z taken along line B-B' in Figure 53. In the superpixel group 50z in the 24th embodiment shown in Figures 53 and 54, parts that are similar to those in the superpixel group 50w in the 21st embodiment shown in Figures 47 and 48 are designated by similar reference numerals, and descriptions thereof will be omitted where appropriate.

[0250] The large pixel group 50z in the 24th embodiment shown in Figures 53 and 54 differs from the large pixel group 50w in the 24th embodiment in that the element isolation in the region where the transistors are arranged is performed by STI, but is otherwise similar.

[0251] An STI 71 is formed around the active area where the reset transistor 25, the selection transistor 27, and the amplification transistor 26 are arranged, in the lateral direction of the central area of ​​the large pixel group 50.

[0252] 54A, in cross section, STIs 71 are formed on both sides of the channel region 37 of the amplifying transistor 26 to isolate it from other elements. The transfer gate 22z has vertical electrodes, is formed in a Π shape, and is configured to sandwich the PD 31.

[0253] In the 24th embodiment, as in the first embodiment and the like, the distance between adjacent FDs 23 is configured to be different between where a transistor is sandwiched and where it is not sandwiched. The size of the PD 31 is adjusted to be the same in each pixel 2. Therefore, as in the first embodiment, even if the photodetector 1 is miniaturized, it is possible to ensure a charge transfer area while maintaining the area for arranging the transistor, and it is possible to achieve both transistor characteristics and charge transfer characteristics.

[0254] <Twenty-fifth embodiment> Figure 55 shows an example of the planar configuration of the superpixel group 50aa in the 25th embodiment, and Figure 56 is a diagram showing an example of the cross-sectional configuration of the superpixel group 50aa taken along line A-A' in Figure 55. In the superpixel group 50aa in the 25th embodiment shown in Figures 55 and 56, parts that are the same as those in the superpixel group 50a in the first embodiment shown in Figures 2 and 3 are designated by the same reference numerals, and descriptions thereof will be omitted where appropriate.

[0255] The large pixel group 50aa shown in Figure 55 is made up of 16 pixels 2 in a 2 x 8 arrangement. In the 25th embodiment, the 16 pixels share the FD 23. While the large pixel group 50 in the first to 24th embodiments is made up of 16 pixels 2, with 2 x 2 small pixel groups 20 formed in four 2 x 2 units, the large pixel group 50 in the 25th and subsequent embodiments is different in that the 2 x 2 small pixel groups 20 are made up of 16 pixels 2, with 1 x 4 units formed in four 1 x 4 units.

[0256] A small pixel group 20 is formed by four pixels 2 arranged in a 2×2 array, and a large pixel group 50aa is formed by four sets of small pixel groups 20. In the example shown in Figure 55, the large pixel group 50aa is made up of four small pixel groups 20 arranged in the vertical direction.

[0257] The large pixel group 50aa-1 includes, from the top in the figure, small pixel groups 20-1, 20-2, 20-3, and 20-4. The large pixel group 50aa-2, which is located to the right of the large pixel group 50aa-1 in the figure, includes, from the top in the figure, small pixel groups 20-5, 20-6, 20-7, and 20-8.

[0258] In the following explanation, we will mainly use the large pixel group 50aa-1 as an example. The small pixel group 20-1 shown in the upper left of the figure includes pixels 2-1, 2-2, 2-3, and 2-4. The small pixel group 20-2, located below the small pixel group 20-1 in the figure, includes pixels 2-5, 2-6, 2-7, and 2-8.

[0259] The small pixel group 20-3, which is arranged below the small pixel group 20-2 in the drawing, includes pixels 2-9, 2-10, 2-11, and 2-12. The small pixel group 20-4, which is arranged below the small pixel group 20-3 in the drawing, includes pixels 2-13, 2-14, 2-15, and 2-16.

[0260] As shown in FIG. 56, each pixel 2 includes a PD 31, and the charge stored in the PD 31 is transferred to the FD 23 by a transfer gate 22 of a transfer transistor.

[0261] Each of the pixels 2-1 to 2-4 in the small pixel group 20-1 includes a PD 31-1 to PD 31-4 (not shown) and a transfer gate 22-1 to 22-4. An FD 23-1 is provided in the center of the area in which the transfer gates 22-1 to 22-4 are arranged. A contact 24-1 is provided in the FD 23-1, and the contact 24-1 is connected to a wiring 40 in a stacked wiring layer (not shown).

[0262] Each of the pixels 2-5 to 2-8 in the small pixel group 20-2 includes a PD31-5 to PD31-8 (not shown) and a transfer gate 22-5 to 22-8. An FD 23-2 is provided in the center of the area in which the transfer gates 22-5 to 22-8 are arranged. A contact 24-2 is provided in the FD 23-2, and the contact 24-2 is connected to a wiring 40 in a stacked wiring layer (not shown).

[0263] Each of the pixels 2-9 to 2-12 in the small pixel group 20-3 includes a PD31-9 to PD31-12 (not shown) and a transfer gate 22-9 to 22-12. An FD 23-3 is provided in the center of the area in which the transfer gates 22-9 to 22-12 are arranged. A contact 24-3 is provided in the FD 23-3, and the contact 24-3 is connected to a wiring 40 in a stacked wiring layer (not shown).

[0264] Each of the pixels 2-13 to 2-16 in the small pixel group 20-4 includes a PD31-13 to PD31-16 (not shown) and a transfer gate 22-13 to 22-16. An FD23-4 is provided at the center of each of the transfer gates 22-13 to 22-16. A contact 24-4 is provided in the FD23-4, and the contact 24-4 is connected to a wiring 40 in a stacked wiring layer (not shown).

[0265] FDs 23-1 to 23-4 provided in each of the small pixel groups 20-1 to 20-4 are connected to wiring 40. In the example shown in Fig. 55, FDs 23-1 to 23-4 are arranged in a straight line in the vertical direction, and therefore wiring 40 connecting FDs 23-1 to 23-4 is also arranged in a straight line in the vertical direction.

[0266] The wiring 40 is located between the superpixel group 50aa-1 and the superpixel group 50aa-2, and is also connected via a contact 24-11 to the FD 23-11 located below the center of the drawing. Therefore, the FDs 23-1 to 23-4 and 23-11 function as a single FD, and are configured to be shared by the pixels 2-1 to 2-16 in the superpixel group 50. Hereinafter, when there is no need to distinguish between the FDs 23-1 to 23-4 and 23-11, or when it is intended to indicate that they function as a single FD, they will be referred to simply as FD23.

[0267] A reset transistor 25-2 is provided above the FD23-11 in the drawing, and the FD23 is configured to be reset by the reset transistor 25-2.

[0268] 55, an amplifier transistor 26-1 is provided near the center, and a contact 24-12 is provided at the gate of the amplifier transistor 26-1. This contact 24-12 is connected to a wiring 40. FDs 23-1 to 23-4 and 23-11 are connected to the amplifier transistor 26-2 via the wiring 40.

[0269] The amplifier transistor 26 has a transfer gate connected to the FD 23 and a drain connected to a power supply VDD 28, and serves as an input part of a readout circuit, a so-called source follower circuit, that reads out a signal corresponding to the charge held in the FD 23. That is, the amplifier transistor 26 has a source connected to the vertical signal line 9 (VSL region 29) via the selection transistor 27, and thereby forms a source follower circuit together with a constant current source (not shown) connected to one end of the vertical signal line 9.

[0270] 55, the reset transistor 25, amplification transistor 26, and selection transistor 27 are arranged in a vertical line between the large pixel group 50aa-1 and the large pixel group 50aa-2. Contacts connected to the power supply VDD28 and contacts connected to the vertical signal line 9 (VSL region 29) are also arranged in a vertical line together with the transistors between the large pixel groups 50.

[0271] The cross-sectional configuration example taken along line A-A' in Figure 55 will be further described with reference to Figure 56. Along line A-A', pixels 2-7 and 2-8 included in large pixel group 50aa-1, amplifier transistor 26, and pixels 2-23 and 2-24 included in large pixel group 50aa-2 are lined up in this order. In Figure 56, the lower side is the light incident surface, and the upper side is the wiring layer (not shown) side.

[0272] An inter-pixel isolation section 32-7 is provided on the left side of PD31-7 to isolate it from pixel 2 (not shown), and an inter-pixel isolation section 32-8 is provided on the right side to isolate it from PD31-8. An inter-pixel isolation section 32-9 is provided between PD31-8 and PD31-23, an inter-pixel isolation section 32-10 is provided between PD31-23 and PD31-24, and an inter-pixel isolation section 32-11 is provided between PD31-24 and PD31 (not shown) of the adjacent pixel 2. The inter-pixel isolation section 32 can be made of an oxide film.

[0273] A cell well 35-7 and a flat isolation section 33-7 are provided above the inter-pixel isolation section 32-7 in the drawing. A cell well 35-8 and a flat isolation section 33-8 are provided above the inter-pixel isolation section 32-8 in the drawing. A cell well 35-9 is provided above the inter-pixel isolation section 32-9 in the drawing, and a flat isolation section 33-9, a channel region 37 of the amplification transistor 26-1, and a flat isolation section 33-10 are provided above the cell well 35-9 in the drawing.

[0274] A cell well 35-10 and a flat isolation section 33-11 are provided above the inter-pixel isolation section 32-10 in the drawing. A cell well 35-11 and a flat isolation section 33-12 are provided above the inter-pixel isolation section 32-11 in the drawing. The cell well 35-11 and the flat isolation section 33-12 are regions in which P-type impurities are diffused, and are provided to isolate pixels (elements).

[0275] A transfer gate 22-7 is provided on PD31-7, which is located between FLAT separation unit 33-7 and FLAT separation unit 33-8. A transfer gate 22-8 is provided on PD31-8, which is located between FLAT separation unit 33-8 and FLAT separation unit 33-9. A transfer gate 22-23 is provided on PD31-23, which is located between FLAT separation unit 33-10 and FLAT separation unit 33-11. A transfer gate 22-24 is provided on PD31-24, which is located between FLAT separation unit 33-11 and FLAT separation unit 33-12.

[0276] The pixels 2 are separated by inter-pixel isolation portions 32, and an element isolation portion is provided in the active region of each pixel 2. The element isolation portion is, for example, a cell well 35 or a flat isolation portion 33. Referring to FIG. 55, a reset transistor 25-1 is provided in the active region 70-1. A selection transistor 27-1, an amplification transistor 26-1, and a reset transistor 25-2 are provided in the active region 70-2. A selection transistor 27-2 and an amplification transistor 26-2 are provided in the active region 70-3.

[0277] The active region 70-1 is formed across the large pixel group 50aa-1 and a large pixel group 50aa (not shown) located above the large pixel group 50aa-2. The active region 70-2 is located between the large pixel group 50aa-1 and the large pixel group 50aa-2. The active region 70-3 is formed across the large pixel group 50aa-1 and a large pixel group 50aa (not shown) located below the large pixel group 50aa-2.

[0278] Focus on the large pixel group 50aa-1. Pixels 2-1 to 2-16 arranged within the large pixel group 50aa-1 use a selection transistor 27-1, an amplification transistor 26-1, and a reset transistor 25-2 arranged in an active region 70-2. Pixel 2 within the large pixel group 50aa-1 is configured to perform processing using transistors arranged within an active region 70-2 formed in an area adjacent to the large pixel group 50aa-1 (an area included in the large pixel group 55aa-1).

[0279] By adopting such a configuration, the transistors can be arranged so that the distance between the wirings 40 is the shortest.

[0280] The distance relationship between adjacent FDs 23 described with reference to Figures 5 and 6 also applies to the superpixel groups 50aa shown in Figures 55 and 56. For example, the distance between adjacent FDs 23 between adjacent superpixel groups 50aa without a transistor between them is (2 x length), and the distance between adjacent FDs 23 between adjacent superpixel groups 50aa with a transistor between them is (2 x length B).

[0281] The FDs 23 and transistors are arranged so that the distance between adjacent FDs 23 with a transistor between them is different from the distance between adjacent FDs 23 without a transistor between them.

[0282] The FDs 23 are arranged so that they are spaced apart from one another at different distances, but the sizes of the PDs 31 are configured to be equal, as in the case described with reference to Fig. 6. To make the sizes of the PDs 31 equal, for example, in the cross-sectional configuration example shown in Fig. 56, the cell well 35-9 below the amplifying transistor 26 is formed larger than the other cell wells 35, and PD31-8 and PD31-23 are adjusted so that they are not larger than the other PDs 31.

[0283] With this configuration, even if the photodetector 1 is miniaturized, it is possible to maintain the area for arranging the transistors while ensuring the charge transfer area, thereby achieving both the transistor characteristics and the charge transfer characteristics.

[0284] In the 25th embodiment, as in the first embodiment and the like, the distance between adjacent FDs 23 is configured to be different between where a transistor is sandwiched and where it is not sandwiched. The size of the PD 31 is adjusted to be the same in each pixel 2. Therefore, as in the first embodiment, even if the photodetector 1 is miniaturized, it is possible to ensure a charge transfer area while maintaining the area for arranging the transistor, and it is possible to achieve both transistor characteristics and charge transfer characteristics.

[0285] <Twenty-sixth embodiment> Figure 57 shows an example of the planar configuration of the superpixel group 50ab in the 26th embodiment, and Figure 58 shows an example of the cross-sectional configuration of the superpixel group 50ab taken along line A-A' in Figure 57. In the superpixel group 50ab in the 26th embodiment shown in Figures 57 and 58, parts that are the same as those in the superpixel group 50aa in the 25th embodiment shown in Figures 55 and 56 are designated by the same reference numerals, and descriptions thereof will be omitted where appropriate.

[0286] 57 and 58, the large pixel group 50ab in the 26th embodiment is similar to the large pixel group 50aa in the 25th embodiment except that the transfer gate 22ab has a vertical structure. As shown in FIG. 58, the transfer gate 22ab of the transfer transistor has a shape that combines a planar electrode provided in a planar shape on the front surface of the semiconductor substrate with a vertical electrode provided vertically within the semiconductor substrate.

[0287] 57, the vertical electrode portion of the transfer gate 22ab is formed in a circular shape in a plan view. The vertical electrode portion is formed in a circular or polygonal shape.

[0288] By configuring the transfer gate 22ab to have a vertical electrode, the transfer efficiency can be improved.

[0289] In the 26th embodiment, as in the first embodiment and the like, the distance between adjacent FDs 23 is configured to be different between where a transistor is sandwiched and where it is not sandwiched. The size of the PD 31 is adjusted to be the same in each pixel 2. Therefore, as in the first embodiment, even if the photodetector 1 is miniaturized, it is possible to ensure a charge transfer area while maintaining the area for arranging the transistor, making it possible to achieve both transistor characteristics and charge transfer characteristics.

[0290] <Twenty-seventh embodiment> Figure 59 shows an example of the planar configuration of the superpixel group 50ac in the 27th embodiment, Figure 60A shows an example of the cross-sectional configuration of the superpixel group 50ac taken along line A-A' in Figure 59, and Figure 60B is a diagram showing an example of the cross-sectional configuration of the superpixel group 50ac taken along line B-B' in Figure 59. In the superpixel group 50ac in the 27th embodiment shown in Figures 59 and 60, parts that are similar to those in the superpixel group 50aa in the 25th embodiment shown in Figures 55 and 56 are designated by the same reference numerals, and descriptions thereof will be omitted where appropriate.

[0291] The superpixel group 50ac in the 27th embodiment shown in Figures 59 and 60 differs from the superpixel group 50aa in the 25th embodiment in that the transfer gates 22ac are transfer gates having a vertical structure, but is otherwise similar.

[0292] 60, the transfer gate 22ac of the transfer transistor is configured in a shape that combines a planar electrode provided in a planar shape on the front surface of the semiconductor substrate and a vertical electrode provided vertically in the semiconductor substrate. The transfer gate 22ac is also formed in a shape that sandwiches the portion corresponding to the inter-pixel isolation portion.

[0293] 60A, an STI 61-8 is formed on (the substrate surface side) of a cell well 35-12 provided between PD31-7 and PD31-8. A transfer gate 22-7ac of PD31-7 and a transfer gate 22-8ac of PD31-8 are formed on either side of (contacting) this STI 61-8. Similarly, an STI 61 is formed on (the substrate surface side) of a cell well 35 provided between PD31, and a transfer gate 22ac of PD31 is formed on (the substrate surface side) of the cell well 35 on either side of (contacting) the STI 61.

[0294] B of Figure 60 is a diagram showing an example of the cross-sectional configuration of the large pixel group 50ac taken along line B-B' in Figure 59. Pixels 2-1, 2-3, and 2-4 are arranged along line B-B'. As shown in B of Figure 60, an STI 61-3 is formed on the substrate surface side between PD 31-1 included in pixel 2-1 and PD 31-3 included in pixel 2-3. A transfer gate 22ac-1 of the transfer transistor of pixel 2-1 and a transfer gate 22ac-3 of the transfer transistor of pixel 2-3 are configured with vertical electrodes so as to sandwich (contact) this STI 61-3.

[0295] 60B, the transfer gate 22ac-3 disposed on the pixel 2-3 has vertical electrodes formed on both ends of the transfer gate 22ac-3 so as to sandwich the PD 31-3, and a flat electrode provided on the substrate formed on the top of the transfer gate 22ac-3. The transfer gate 22ac-3 is formed in a shape that appears to be Π-shaped in cross section.

[0296] In the 27th embodiment, since the transfer gates 22ac of the transfer transistors are configured close to each other, an STI 61 is provided between the transfer gates 22ac to reduce the influence thereof. The STI 61 can be formed of an oxide film.

[0297] 59, the vertical electrode portion of the transfer gate 22ac is formed in a trapezoidal shape in a plan view, with the bottom side facing the STI 61. Note that the vertical electrode portion of the transfer gate 22ac is not limited to a trapezoidal shape in a plan view, and may have another shape.

[0298] By configuring the transfer gate 22ac to have a vertical electrode, the transfer efficiency can be improved.

[0299] In the 27th embodiment, as in the first embodiment and the like, the distance between adjacent FDs 23 is configured to be different between where a transistor is sandwiched and where it is not sandwiched. The size of the PD 31 is adjusted to be the same in each pixel 2. Therefore, as in the first embodiment, even if the photodetector 1 is miniaturized, it is possible to ensure a charge transfer area while maintaining the area for arranging the transistor, and it is possible to achieve both transistor characteristics and charge transfer characteristics.

[0300] <Twenty-eighth embodiment> Figure 61 shows an example of the planar configuration of the superpixel group 50ad in the 28th embodiment, and Figure 62 shows an example of the cross-sectional configuration of the superpixel group 50ad taken along line A-A' in Figure 61. In the superpixel group 50ad in the 28th embodiment shown in Figures 61 and 62, parts that are the same as those in the superpixel group 50aa in the 25th embodiment shown in Figures 55 and 56 are designated by the same reference numerals, and descriptions thereof will be omitted where appropriate.

[0301] The large pixel group 50ad in the 28th embodiment shown in Figures 61 and 62 differs from the large pixel group 50aa in the 25th embodiment in that the element isolation in the region where the transistors are arranged is performed by STI, but in other respects they are similar.

[0302] An STI 71 is formed around the active area where the reset transistor 25, the selection transistor 27, and the amplification transistor 26 are arranged, in the vertical direction of the central area of ​​the large pixel group 50.

[0303] In cross section, as shown in FIG. 62, STIs 71 are formed on both sides of the channel region 37 of the amplifying transistor 26-1 to isolate it from other elements.

[0304] In the 28th embodiment, as in the first embodiment, the distance between adjacent FDs 23 is different between where a transistor is sandwiched and where it is not. The size of the PDs 31 is adjusted to be the same in each pixel 2. Therefore, as in the first embodiment, even if the photodetector 1 is miniaturized, it is possible to ensure a charge transfer area while maintaining the area for arranging the transistor, thereby achieving both transistor characteristics and charge transfer characteristics.

[0305] <Twenty-ninth embodiment> Figure 63 shows an example of the planar configuration of the superpixel group 50ae in the 29th embodiment, and Figure 64 is a diagram showing an example of the cross-sectional configuration of the superpixel group 50ae taken along line A-A' in Figure 63. In the superpixel group 50ae in the 29th embodiment shown in Figures 63 and 64, parts that are the same as those in the superpixel group 50ab in the 26th embodiment shown in Figures 57 and 58 are designated by the same reference numerals, and their description will be omitted where appropriate.

[0306] The large pixel group 50ae in the 29th embodiment shown in Figures 63 and 64 differs from the large pixel group 50ab in the 26th embodiment in that the element isolation in the region where the transistors are arranged is performed by STI, but is otherwise similar.

[0307] An STI 71 is formed around the active area where the reset transistor 25, the selection transistor 27, and the amplification transistor 26 are arranged, in the vertical direction of the central area of ​​the large pixel group 50.

[0308] 64, in cross section, STIs 71 are formed on both sides of the channel region 37 of the amplifier transistor 26-1 to isolate it from other elements. The transfer gate 22ae has a vertical electrode.

[0309] In the 29th embodiment, as in the first embodiment and the like, the distance between adjacent FDs 23 is configured to be different between where a transistor is sandwiched and where it is not sandwiched. The size of the PE 31 is adjusted to be the same in each pixel 2. Therefore, as in the first embodiment, even if the photodetector 1 is miniaturized, it is possible to ensure a charge transfer area while maintaining the area for arranging the transistor, and it is possible to achieve both transistor characteristics and charge transfer characteristics.

[0310] <Thirtieth embodiment> Figure 65 shows an example of the planar configuration of the superpixel group 50af in the 30th embodiment, Figure 66A shows an example of the cross-sectional configuration of the superpixel group 50af taken along line A-A' in Figure 65, and Figure 66B is a diagram showing an example of the cross-sectional configuration of the superpixel group 50af taken along line B-B' in Figure 65. In the superpixel group 50af in the 30th embodiment shown in Figures 65 and 66, parts that are similar to those in the superpixel group 50ac in the 27th embodiment shown in Figures 59 and 60 are designated by the same reference numerals, and descriptions thereof will be omitted where appropriate.

[0311] The large pixel group 50af in the 30th embodiment shown in Figures 65 and 66 differs from the large pixel group 50ac in the 27th embodiment in that the element isolation in the region where the transistors are arranged is performed by STI, but is otherwise similar.

[0312] An STI 71 is formed around the active area where the reset transistor 25, the selection transistor 27, and the amplification transistor 26 are arranged, in the vertical direction of the central area of ​​the large pixel group 50.

[0313] 66A, in cross section, STIs 71 are formed on both sides of the channel region 37 of the amplifier transistor 26-1 to isolate it from other elements. The transfer gate 22af has vertical electrodes, is formed in a Π shape, and is configured to sandwich the PD 31.

[0314] In the 30th embodiment, as in the first embodiment and the like, the distance between adjacent FDs 23 is configured to be different between where a transistor is sandwiched and where it is not sandwiched. The size of the PD 31 is adjusted to be the same in each pixel 2. Therefore, as in the first embodiment, even if the photodetector 1 is miniaturized, it is possible to ensure a charge transfer area while maintaining the area for arranging the transistor, and it is possible to achieve both transistor characteristics and charge transfer characteristics.

[0315] <Thirty-first embodiment> Figure 67 shows an example of the planar configuration of the superpixel group 50ag in the 31st embodiment, and A in Figure 68 shows an example of the cross-sectional configuration of the superpixel group 50af taken along line A-A' in Figure 67. In the superpixel group 50ag in the 31st embodiment shown in Figures 67 and 68, parts that are the same as those in the superpixel group 50aa in the 25th embodiment shown in Figures 55 and 56 are designated by the same reference numerals, and descriptions thereof will be omitted where appropriate.

[0316] The large pixel group 50ag shown in Figure 67 is made up of 16 pixels 2 in an 8 x 2 array. A small pixel group 20 is formed by four pixels 2 in a 2 x 2 array, and the large pixel group 50ag is made up of four sets of small pixel groups 20 in a 4 x 1 array.

[0317] In the example shown in Figure 67, the large pixel group 50ag is made up of four horizontally arranged small pixel groups 20. From the left in the figure, the large pixel group 50ag-1 includes the small pixel group 20-1, the small pixel group 20-2, the small pixel group 20-3, and the small pixel group 20-4. The large pixel group 50ag-2, which is arranged above the large pixel group 50ag-1 in the figure, includes, from the left in the figure, the small pixel group 20-5, the small pixel group 20-6, the small pixel group 20-7, and the small pixel group 20-8.

[0318] In the following explanation, the large pixel group 50ag-1 will be mainly used as an example. The small pixel group 20-1 shown on the left side of the drawing includes pixels 2-1, 2-2, 2-3, and 2-4. The small pixel group 20-2, located to the right of the small pixel group 20-1 in the drawing, includes pixels 2-5, 2-6, 2-7, and 2-8.

[0319] The small pixel group 20-3, which is located to the right of the small pixel group 20-2 in the drawing, includes pixels 2-9, 2-10, 2-11, and 2-12. The small pixel group 20-4, which is located to the right of the small pixel group 20-3 in the drawing, includes pixels 2-13, 2-14, 2-15, and 2-16.

[0320] As shown in FIG. 68, each pixel 2 includes a PD 31, and the charge stored in the PD 31 is transferred to the FD 23 by a transfer gate 22 of a transfer transistor.

[0321] Each of the pixels 2-1 to 2-4 in the small pixel group 20-1 includes a PD 31-1 to PD 31-4 (not shown) and a transfer gate 22-1 to 22-4. An FD 23-1 is provided in the center of the area in which the transfer gates 22-1 to 22-4 are arranged. A contact 24-1 is provided in the FD 23-1, and the contact 24-1 is connected to a wiring 40 in a stacked wiring layer (not shown).

[0322] Each of the pixels 2-5 to 2-8 in the small pixel group 20-2 includes a PD31-5 to PD31-8 (not shown) and a transfer gate 22-5 to 22-8. An FD 23-2 is provided in the center of the area in which the transfer gates 22-5 to 22-8 are arranged. A contact 24-2 is provided in the FD 23-2, and the contact 24-2 is connected to a wiring 40 in a stacked wiring layer (not shown).

[0323] Each of the pixels 2-9 to 2-12 in the small pixel group 20-3 includes a PD31-9 to PD31-12 (not shown) and a transfer gate 22-9 to 22-12. An FD 23-3 is provided in the center of the area in which the transfer gates 22-9 to 22-12 are arranged. A contact 24-3 is provided in the FD 23-3, and the contact 24-3 is connected to a wiring 40 in a stacked wiring layer (not shown).

[0324] Each of the pixels 2-13 to 2-16 in the small pixel group 20-4 includes a PD31-13 to PD31-16 (not shown) and a transfer gate 22-13 to 22-16. An FD23-4 is provided at the center of each of the transfer gates 22-13 to 22-16. A contact 24-4 is provided in the FD23-4, and the contact 24-4 is connected to a wiring 40 in a stacked wiring layer (not shown).

[0325] FDs 23-1 to 23-4 provided in each of the small pixel groups 20-1 to 20-4 are connected to wiring 40. In the example shown in Fig. 67, FDs 23-1 to 23-4 are arranged in a straight line in the horizontal direction, and therefore wiring 40 connecting FDs 23-1 to 23-4 is also arranged in a straight line in the horizontal direction.

[0326] The wiring 40 is connected between the superpixel group 50ag-1 and the superpixel group 50ag-2 and is also connected to the FD 23-11, which is located to the left of the center in the drawing, via a contact 24-11. Therefore, the FDs 23-1 to 23-4 and 23-11 function as a single FD, and are configured to be shared by the pixels 2-1 to 2-16 in the superpixel group 50.

[0327] A reset transistor 25-1 is provided on the right side of the FD23-11 in the drawing, and the FD23 is configured to be reset by the reset transistor 25-1.

[0328] In Fig. 67, an amplifier transistor 26-2 is provided on the right side from the center, and a contact 24-12 is provided at the gate of the amplifier transistor 26-2. This contact 24-12 is connected to a wiring 40. FDs 23-1 to 23-4 and 23-11 are connected to the amplifier transistor 26-2 via the wiring 40.

[0329] The amplifier transistor 26-2 has a transfer gate connected to the FD 23 and a drain connected to a power supply VDD 28, and serves as an input part of a readout circuit, a so-called source follower circuit, that reads out a signal corresponding to the charge held in the FD 23. That is, the amplifier transistor 26 has a source connected to the vertical signal line 9 (VSL region 29) via the selection transistor 27-2, and thereby forms a source follower circuit together with a constant current source (not shown) connected to one end of the vertical signal line 9.

[0330] 67, a reset transistor 25-1, an amplification transistor 26-2, and a selection transistor 27-2 are arranged in the active region 70-2, and these transistors are arranged in a row in the horizontal direction between the large pixel groups 50ag-1 and 50ag-2. Contacts connected to the power supply VDD28 and contacts connected to the vertical signal line 9 (VSL region 29) are also arranged in a row in the horizontal direction together with the transistors in the region between the large pixel groups 50ag.

[0331] An example of the cross-sectional configuration along line A-A' in Figure 67 will be described with reference to Figure 68. Along line A-A', pixels 2-25 and 2-27 included in large pixel group 50ag-2, amplifier transistor 26-2, and pixels 2-9 and 2-11 included in large pixel group 50ag-1 are lined up in this order. In Figure 67, the lower side is the light incident surface and the upper side is the wiring layer (not shown) side. Inter-pixel isolation sections 32 are provided between PDs 31 to isolate adjacent PDs 31 (pixels 2). Inter-pixel isolation sections 32 can be made of an oxide film.

[0332] A cell well 35 and a flat isolation portion 33 are provided above the inter-pixel isolation portion 32 in the drawing. The cell well 35 and the flat isolation portion 33 are regions in which P-type impurities are diffused, and are provided to separate pixels (elements).

[0333] The pixels 2 are separated from one another by inter-pixel isolation portions 32, and an element isolation portion is provided in the active region of each pixel 2. The element isolation portion is, for example, a cell well 35 or a flat isolation portion 33. Referring to FIG. 67, a reset transistor 25-1 is provided in the active region 70-1. A selection transistor 27-1, an amplification transistor 26-1, and a reset transistor 25-2 are provided in the active region 70-2. A selection transistor 27-2 and an amplification transistor 26-2 are provided in the active region 70-3.

[0334] The active region 70-1 is formed across the large pixel group 50ag-1 and a large pixel group 50ag (not shown) located to the left of the large pixel group 50ag-2. The active region 70-2 is located between the large pixel group 50ag-1 and the large pixel group 50ag-2. The active region 70-3 is formed across the large pixel group 50ag-1 and a large pixel group 50ag (not shown) located to the right of the large pixel group 50ag-2.

[0335] Focus on the large pixel group 50ag-1. Pixels 2-1 to 2-16 arranged within the large pixel group 50ag-1 use a selection transistor 27-1, an amplification transistor 26-1, and a reset transistor 25-2 arranged in an active region 70-2. Pixel 2 within the large pixel group 50ag-1 is configured to perform processing using transistors arranged within the active region 70-2 formed in an area adjacent to the large pixel group 50ag-1 (an area included in the large pixel group 50ag-1).

[0336] By adopting such a configuration, the transistors can be arranged so that the distance between the wirings 40 is the shortest.

[0337] The distance relationship between adjacent FDs 23 described with reference to Figures 5 and 6 also applies to the superpixel groups 50ag shown in Figures 67 and 68. For example, the distance between adjacent FDs 23 in adjacent superpixel groups 50ag without an area in which transistors are arranged between them is (2 x length A), and the distance between adjacent FDs 23 in the superpixel group 50ag across an area in which transistors are arranged between them is (2 x length B).

[0338] The FDs 23 and transistors are arranged so that the distance between adjacent FDs 23 with a transistor between them is different from the distance between adjacent FDs 23 without a transistor between them.

[0339] The FDs 23 are arranged so that they are spaced apart from one another by different distances, but the sizes of the PDs 31 are configured to be equal, as in the case described with reference to Fig. 6. To make the sizes of the PDs 31 equal, for example, in the cross-sectional configuration example shown in Fig. 68, the cell well 35-27 below the amplifying transistor 26-2 is formed larger than the other cell wells 35, and adjustments are made so that PD31-27 and PD31-9 are not larger than the other PDs 31.

[0340] With this configuration, even if the photodetector 1 is miniaturized, it is possible to maintain the area for arranging the transistors while ensuring the charge transfer area, thereby achieving both the transistor characteristics and the charge transfer characteristics.

[0341] In the thirty-first embodiment, as in the first embodiment and the like, the distance between adjacent FDs 23 is configured to be different between where a transistor is sandwiched and where it is not sandwiched. The size of the PD 31 is adjusted to be the same in each pixel 2. Therefore, as in the first embodiment, even if the photodetector 1 is miniaturized, it is possible to ensure a charge transfer area while maintaining the area for arranging the transistor, and it is possible to achieve both transistor characteristics and charge transfer characteristics.

[0342] <Thirty-second embodiment> Figure 69 shows an example of the planar configuration of the superpixel group 50ah in the 32nd embodiment, and Figure 70 is a diagram showing an example of the cross-sectional configuration of the superpixel group 50ah taken along line A-A' in Figure 69. In the superpixel group 50ah in the 32nd embodiment shown in Figures 69 and 70, parts that are the same as those in the superpixel group 50ag in the 31st embodiment shown in Figures 67 and 68 are designated by the same reference numerals, and descriptions thereof will be omitted where appropriate.

[0343] The large pixel group 50ah in the 26th embodiment shown in Figures 69 and 70 differs from the large pixel group 50ag in the 31st embodiment in that the transfer gates 22ah have a vertical structure, but are otherwise similar. As shown in Figure 70, the transfer gates 22ah of the transfer transistors have a shape that combines a planar electrode provided in a planar manner on the front surface of the semiconductor substrate with a vertical electrode provided vertically within the semiconductor substrate.

[0344] As shown in Fig. 69, the vertical electrode portion of the transfer gate 22ah is formed in a circular shape in a plan view. The vertical electrode portion is formed in a circular or polygonal shape.

[0345] By configuring the transfer gate 22ah to have a vertical electrode, the transfer efficiency can be improved.

[0346] In the 32nd embodiment, as in the first embodiment and the like, the distance between adjacent FDs 23 is configured to be different between where a transistor is sandwiched and where it is not sandwiched. The size of the PD 31 is adjusted to be the same in each pixel 2. Therefore, as in the first embodiment, even if the photodetector 1 is miniaturized, it is possible to ensure a charge transfer area while maintaining the area for arranging the transistor, and it is possible to achieve both transistor characteristics and charge transfer characteristics.

[0347] <Thirty-third embodiment> Figure 71 shows an example of the planar configuration of the superpixel group 50ai in the 33rd embodiment, Figure 72A shows an example of the cross-sectional configuration of the superpixel group 50ai taken along line A-A' in Figure 71, and Figure 72B is a diagram showing an example of the cross-sectional configuration of the superpixel group 50ai taken along line B-B' in Figure 71. In the superpixel group 50ai in the 33rd embodiment shown in Figures 71 and 72, parts that are the same as those in the superpixel group 50ag in the 31st embodiment shown in Figures 67 and 68 are designated by the same reference numerals, and descriptions thereof will be omitted as appropriate.

[0348] The superpixel group 50ai in the 33rd embodiment shown in Figures 71 and 72 differs from the superpixel group 50ag in the 31st embodiment in that the transfer gates 22ai are transfer gates having a vertical structure, but is otherwise similar.

[0349] As shown in Fig. 72, the transfer gate 22ai of the transfer transistor is configured in a shape that combines a planar electrode provided in a planar shape on the front surface of the semiconductor substrate and a vertical electrode provided vertically in the semiconductor substrate. The transfer gate 22ai is formed in a shape that sandwiches a portion corresponding to the inter-pixel isolation portion. The transfer gate 22i is formed in a Π shape, similar to the transfer gate 22c in the third embodiment described with reference to Figs. 9 and 10.

[0350] 72B, the transfer gate 22ai-3 arranged on the pixel 2-3 has vertical electrodes formed on both ends of the transfer gate 22ai-3, sandwiching the PD 31-3, and a flat electrode provided on the substrate formed on the top of the transfer gate 22ai-3. The transfer gate 22ai-3 is formed in a shape that appears to be Π-shaped in cross section.

[0351] In the 33rd embodiment, the transfer gates 22ai of the transfer transistors are configured close to each other, and therefore, in order to reduce the influence thereof, an STI 61 is provided between the transfer gates 22ai. The STI 61 can be formed of an oxide film.

[0352] 71, the vertical electrode portion of the transfer gate 22ai is formed in a trapezoidal shape in a plan view, with its bottom side facing the STI 61. Note that the vertical electrode portion of the transfer gate 22ai is not limited to a trapezoidal shape in a plan view, and may have another shape.

[0353] By configuring the transfer gate 22ai to have a vertical electrode, the transfer efficiency can be improved.

[0354] In the 33rd embodiment, as in the first embodiment and the like, the distance between adjacent FDs 23 is configured to be different between where a transistor is sandwiched and where it is not sandwiched. The size of the PD 31 is adjusted to be the same in each pixel 2. Therefore, as in the first embodiment, even if the photodetector 1 is miniaturized, it is possible to ensure a charge transfer area while maintaining the area for arranging the transistor, and it is possible to achieve both transistor characteristics and charge transfer characteristics.

[0355] <34th embodiment> Figure 73 shows an example of the planar configuration of the superpixel group 50aj in the 34th embodiment, and Figure 74 shows an example of the cross-sectional configuration of the superpixel group 50aj taken along line A-A' in Figure 73. In the superpixel group 50aj in the 34th embodiment shown in Figures 73 and 74, parts that are the same as those in the superpixel group 50ag in the 31st embodiment shown in Figures 67 and 68 are designated by the same reference numerals, and their description will be omitted where appropriate.

[0356] The large pixel group 50aj in the 34th embodiment shown in Figures 73 and 74 differs from the large pixel group 50ag in the 31st embodiment in that the element isolation in the region where the transistors are arranged is performed by STI, but in other respects they are similar.

[0357] An STI 71 is formed around the active region where the reset transistor 25, the selection transistor 27, and the amplification transistor 26 are arranged, and in the lateral direction of the central region of the large pixel group 50aj.

[0358] In cross section, as shown in FIG. 74, STIs 71 are formed on both sides of the channel region 37 of the amplifying transistor 26-2 to isolate it from other elements.

[0359] In the thirty-fourth embodiment, as in the first embodiment and the like, the distance between adjacent FDs 23 is configured to be different between where a transistor is sandwiched and where it is not sandwiched. The size of the PD 31 is adjusted to be the same in each pixel 2. Therefore, as in the first embodiment, even if the photodetector 1 is miniaturized, it is possible to ensure a charge transfer area while maintaining the area for arranging the transistor, and it is possible to achieve both transistor characteristics and charge transfer characteristics.

[0360] <35th embodiment> Figure 75 shows an example of the planar configuration of the superpixel group 50ak in the 35th embodiment, and Figure 76 is a diagram showing an example of the cross-sectional configuration of the superpixel group 50ak taken along line A-A' in Figure 75. In the superpixel group 50ak in the 35th embodiment shown in Figures 75 and 76, parts that are the same as those in the superpixel group 50ah in the 32nd embodiment shown in Figures 69 and 70 are designated by the same reference numerals, and descriptions thereof will be omitted where appropriate.

[0361] The large pixel group 50ak in the 35th embodiment shown in Figures 75 and 76 differs from the large pixel group 50ah in the 32nd embodiment in that the element isolation in the region where the transistors are arranged is performed by STI, but is otherwise similar.

[0362] An STI 71 is formed around the active region where the reset transistor 25, the selection transistor 27, and the amplification transistor 26 are arranged, in the vertical direction of the central region of the large pixel group 50ak.

[0363] 76, in cross section, STIs 71 are formed on both sides of the channel region 37 of the amplifier transistor 26-2 to isolate it from other elements. Also, the transfer gate 22ak has a vertical electrode.

[0364] In the 35th embodiment, as in the first embodiment and the like, the distance between adjacent FDs 23 is configured to be different between where a transistor is sandwiched and where it is not sandwiched. The size of the PD 31 is adjusted to be the same in each pixel 2. Therefore, as in the 31st embodiment, even if the photodetector 1 is miniaturized, it is possible to ensure a charge transfer area while maintaining the area for arranging the transistor, and it is possible to achieve both transistor characteristics and charge transfer characteristics.

[0365] <36th embodiment> Figure 77 shows an example of the planar configuration of the superpixel group 50am in the 36th embodiment, Figure 78A shows an example of the cross-sectional configuration of the superpixel group 50am taken along line A-A' in Figure 77, and Figure 78B is a diagram showing an example of the cross-sectional configuration of the superpixel group 50am taken along line B-B' in Figure 77. In the superpixel group 50am in the 36th embodiment shown in Figures 77 and 78, parts that are the same as those in the superpixel group 50ai in the 33rd embodiment shown in Figures 71 and 72 are designated by the same reference numerals, and descriptions thereof will be omitted as appropriate.

[0366] The large pixel group 50am in the 36th embodiment shown in Figures 77 and 78 differs from the large pixel group 50ai in the 33rd embodiment in that the element isolation in the region where the transistors are arranged is performed by STI, but is otherwise similar.

[0367] An STI 71 is formed around the active area where the reset transistor 25, the selection transistor 27, and the amplification transistor 26 are arranged, in the vertical direction of the central area of ​​the large pixel group 50.

[0368] 78A, STIs 71 are formed on both sides of the channel region 37 of the amplifier transistor 26-2 to isolate it from other elements. The transfer gate 22am has vertical electrodes, is formed in a Π shape, and is configured to sandwich the PD 31.

[0369] In the 36th embodiment, as in the first embodiment and the like, the distance between adjacent FDs 23 is configured to be different between where a transistor is sandwiched and where it is not sandwiched. The size of the PD 31 is adjusted to be the same in each pixel 2. Therefore, as in the first embodiment, even if the photodetector 1 is miniaturized, it is possible to ensure a charge transfer area while maintaining the area for arranging the transistor, making it possible to achieve both transistor characteristics and charge transfer characteristics.

[0370] <Application examples to electronic devices> The present technology is not limited to application to imaging elements. That is, the present technology can be applied to general electronic devices that use imaging elements in image capture units (photoelectric conversion units), such as imaging devices such as digital still cameras and video cameras, portable terminal devices with imaging functions, and copiers that use imaging elements in image reading units. The imaging element may be formed as a single chip, or may be in the form of a module having imaging functions in which the imaging unit and a signal processing unit or an optical system are packaged together.

[0371] FIG. 79 is a block diagram showing an example configuration of an imaging device as an electronic device to which the present technology is applied.

[0372] 79 includes an optical unit 1001 including a lens group and the like, an image sensor (image capturing device) 1002 that employs the configuration of the photodetector 1 in FIG. 1, and a DSP (Digital Signal Processor) circuit 1003 that is a camera signal processing circuit. The image sensor 1000 also includes a frame memory 1004, a display unit 1005, a recording unit 1006, an operation unit 1007, and a power supply unit 1008. The DSP circuit 1003, frame memory 1004, display unit 1005, recording unit 1006, operation unit 1007, and power supply unit 1008 are interconnected via a bus line 1009.

[0373] The optical unit 1001 takes in incident light (image light) from a subject and forms an image on the imaging surface of the image sensor 1002. The image sensor 1002 converts the amount of incident light formed on the imaging surface by the optical unit 1001 into an electrical signal on a pixel-by-pixel basis and outputs the signal as a pixel signal. The photodetector 1 in FIG. 1 can be used as this image sensor 1002.

[0374] The display unit 1005 is configured with a thin display such as an LCD (Liquid Crystal Display) or an organic EL (Electro Luminescence) display, and displays moving images or still images captured by the imaging element 1002. The recording unit 1006 records the moving images or still images captured by the imaging element 1002 on a recording medium such as a hard disk or semiconductor memory.

[0375] An operation unit 1007, under user operation, issues operation commands for various functions of the image sensor 1000. A power supply unit 1008 appropriately supplies various types of power to the DSP circuit 1003, frame memory 1004, display unit 1005, recording unit 1006, and operation unit 1007 as operating power sources.

[0376] <Application example to endoscopic surgery system> The technology according to the present disclosure (the present technology) can be applied to various products. For example, the technology according to the present disclosure may be applied to an endoscopic surgery system.

[0377] FIG. 80 is a diagram showing an example of a schematic configuration of an endoscopic surgery system to which the technology according to the present disclosure (the present technology) can be applied.

[0378] Figure 80 shows an operator (doctor) 11131 performing surgery on a patient 11132 on a patient bed 11133 using an endoscopic surgery system 11000. As shown in the figure, the endoscopic surgery system 11000 is composed of an endoscope 11100, other surgical tools 11110 such as an insufflation tube 11111 and an energy treatment tool 11112, a support arm device 11120 that supports the endoscope 11100, and a cart 11200 on which various devices for endoscopic surgery are mounted.

[0379] The endoscope 11100 is composed of a lens barrel 11101, a region of a predetermined length from the tip of which is inserted into a body cavity of a patient 11132, and a camera head 11102 connected to the base end of the lens barrel 11101. In the example shown, the endoscope 11100 is configured as a so-called rigid scope having a rigid lens barrel 11101, but the endoscope 11100 may also be configured as a so-called flexible scope having a flexible lens barrel.

[0380] An opening into which an objective lens is fitted is provided at the tip of the lens barrel 11101. A light source device 11203 is connected to the endoscope 11100, and light generated by the light source device 11203 is guided to the tip of the lens barrel by a light guide extending inside the lens barrel 11101, and is irradiated via the objective lens towards an object to be observed inside the body cavity of the patient 11132. The endoscope 11100 may be a direct-viewing endoscope, an oblique-viewing endoscope, or a side-viewing endoscope.

[0381] An optical system and an image sensor are provided inside the camera head 11102, and light reflected from the object of observation (observation light) is collected onto the image sensor by the optical system. The observation light is photoelectrically converted by the image sensor to generate an electrical signal corresponding to the observation light, i.e., an image signal corresponding to the observed image. The image signal is sent to a camera control unit (CCU) 11201 as RAW data.

[0382] The CCU 11201 is configured with a CPU (Central Processing Unit), a GPU (Graphics Processing Unit), etc., and comprehensively controls the operations of the endoscope 11100 and the display device 11202. Furthermore, the CCU 11201 receives an image signal from the camera head 11102, and performs various image processing on the image signal, such as development processing (demosaic processing), to display an image based on the image signal.

[0383] Under the control of the CCU 11201, the display device 11202 displays an image based on an image signal that has been subjected to image processing by the CCU 11201.

[0384] The light source device 11203 is configured from a light source such as an LED (light emitting diode), and supplies irradiation light to the endoscope 11100 when photographing an operation site or the like.

[0385] The input device 11204 is an input interface for the endoscopic surgery system 11000. A user can input various information and instructions to the endoscopic surgery system 11000 via the input device 11204. For example, the user inputs an instruction to change the imaging conditions (type of irradiating light, magnification, focal length, etc.) of the endoscope 11100.

[0386] The treatment tool control device 11205 controls the driving of the energy treatment tool 11112 for cauterizing tissue, incising, sealing blood vessels, etc. The insufflation device 11206 inflates the body cavity of the patient 11132 through the insufflation tube 11111 in order to ensure a clear field of view for the endoscope 11100 and a working space for the surgeon. The recorder 11207 is a device capable of recording various types of information related to the surgery. The printer 11208 is a device capable of printing various types of information related to the surgery in various formats such as text, images, or graphs.

[0387] The light source device 11203 that supplies illumination light to the endoscope 11100 when photographing the surgical site can be configured from a white light source configured from, for example, an LED, a laser light source, or a combination of these. When the white light source is configured from a combination of RGB laser light sources, the output intensity and output timing of each color (each wavelength) can be controlled with high precision, making it possible to adjust the white balance of the captured image in the light source device 11203. In this case, it is also possible to capture images corresponding to each RGB in a time-division manner by irradiating the object of observation with laser light from each RGB laser light source in a time-division manner and controlling the drive of the image sensor of the camera head 11102 in synchronization with the irradiation timing. According to this method, a color image can be obtained without providing a color filter to the image sensor.

[0388] Furthermore, the light source device 11203 may be controlled to change the intensity of light it outputs at predetermined time intervals. By controlling the driving of the image sensor of the camera head 11102 in synchronization with the timing of the change in light intensity to acquire images in a time-division manner and combining the images, it is possible to generate an image with a high dynamic range that is free of so-called blocked-up shadows and blown-out highlights.

[0389] The light source device 11203 may also be configured to supply light in a predetermined wavelength band corresponding to special light observation. Special light observation, for example, utilizes the wavelength dependence of light absorption in body tissues to irradiate light with a narrower band than the light irradiated during normal observation (i.e., white light), thereby capturing high-contrast images of specific tissues, such as blood vessels on the surface of mucous membranes, known as narrow-band imaging. Alternatively, special light observation may be performed using fluorescence observation, in which images are obtained using fluorescence generated by irradiating excitation light. Fluorescence observation can involve irradiating excitation light onto body tissues and observing the fluorescence from the tissues (autofluorescence observation), or locally injecting a reagent such as indocyanine green (ICG) into the body tissue and irradiating the tissue with excitation light corresponding to the fluorescent wavelength of the reagent to obtain a fluorescent image. The light source device 11203 may be configured to supply narrow-band light and / or excitation light corresponding to such special light observation.

[0390] FIG. 81 is a block diagram showing an example of the functional configuration of the camera head 11102 and the CCU 11201 shown in FIG.

[0391] The camera head 11102 has a lens unit 11401, an imaging unit 11402, a drive unit 11403, a communication unit 11404, and a camera head control unit 11405. The CCU 11201 has a communication unit 11411, an image processing unit 11412, and a control unit 11413. The camera head 11102 and the CCU 11201 are connected to each other by a transmission cable 11400 so that they can communicate with each other.

[0392] The lens unit 11401 is an optical system provided at the connection point with the lens barrel 11101. Observation light taken in from the tip of the lens barrel 11101 is guided to the camera head 11102 and enters the lens unit 11401. The lens unit 11401 is composed of a combination of multiple lenses including a zoom lens and a focus lens.

[0393] The imaging unit 11402 may include one imaging element (a so-called single-chip type) or multiple imaging elements (a so-called multi-chip type). When the imaging unit 11402 is configured as a multi-chip type, for example, each imaging element may generate an image signal corresponding to each of RGB, and a color image may be obtained by combining these signals. Alternatively, the imaging unit 11402 may be configured to have a pair of imaging elements for acquiring image signals for the right eye and the left eye corresponding to 3D (dimensional) display. 3D display allows the surgeon 11131 to more accurately grasp the depth of the biological tissue at the surgical site. Note that when the imaging unit 11402 is configured as a multi-chip type, multiple lens units 11401 may be provided corresponding to each imaging element.

[0394] Furthermore, the imaging unit 11402 does not necessarily have to be provided in the camera head 11102. For example, the imaging unit 11402 may be provided inside the lens barrel 11101, immediately after the objective lens.

[0395] The driving unit 11403 is configured by an actuator, and moves the zoom lens and focus lens of the lens unit 11401 by a predetermined distance along the optical axis under the control of the camera head control unit 11405. This allows the magnification and focus of the image captured by the imaging unit 11402 to be adjusted appropriately.

[0396] The communication unit 11404 is configured by a communication device for transmitting and receiving various types of information to and from the CCU 11201. The communication unit 11404 transmits the image signal obtained from the imaging unit 11402 to the CCU 11201 via the transmission cable 11400 as RAW data.

[0397] Furthermore, the communication unit 11404 receives a control signal for controlling the driving of the camera head 11102 from the CCU 11201 and supplies the control signal to the camera head control unit 11405. The control signal includes information on the imaging conditions, such as information specifying the frame rate of the captured image, information specifying the exposure value at the time of imaging, and / or information specifying the magnification and focus of the captured image.

[0398] The image capturing conditions such as the frame rate, exposure value, magnification, and focus may be appropriately specified by the user, or may be automatically set by the control unit 11413 of the CCU 11201 based on the acquired image signal. In the latter case, the endoscope 11100 is equipped with so-called AE (Auto Exposure) function, AF (Auto Focus) function, and AWB (Auto White Balance) function.

[0399] The camera head control unit 11405 controls the driving of the camera head 11102 based on a control signal received from the CCU 11201 via the communication unit 11404 .

[0400] The communication unit 11411 is configured by a communication device for transmitting and receiving various information to and from the camera head 11102. The communication unit 11411 receives an image signal transmitted from the camera head 11102 via the transmission cable 11400.

[0401] Furthermore, the communication unit 11411 transmits to the camera head 11102 a control signal for controlling the driving of the camera head 11102. The image signal and the control signal can be transmitted by electrical communication, optical communication, or the like.

[0402] The image processing unit 11412 performs various image processing operations on the image signal, which is RAW data sent from the camera head 11102 .

[0403] The control unit 11413 performs various controls related to the imaging of the surgical site, etc. by the endoscope 11100 and the display of the captured image obtained by imaging the surgical site, etc. For example, the control unit 11413 generates a control signal for controlling the driving of the camera head 11102.

[0404] Furthermore, the control unit 11413 causes the display device 11202 to display a captured image showing the surgical site, etc., based on the image signal that has been image processed by the image processing unit 11412. At this time, the control unit 11413 may recognize various objects in the captured image using various image recognition technologies. For example, the control unit 11413 can recognize surgical tools such as forceps, specific biological parts, bleeding, mist generated when using the energy treatment tool 11112, etc., by detecting the shape and color of the edges of objects included in the captured image. When displaying the captured image on the display device 11202, the control unit 11413 may use the recognition results to superimpose various surgical support information on the image of the surgical site. By superimposing the surgical support information and presenting it to the surgeon 11131, the burden on the surgeon 11131 can be reduced and the surgeon 11131 can proceed with the surgery reliably.

[0405] The transmission cable 11400 connecting the camera head 11102 and the CCU 11201 is an electrical signal cable for communication of electrical signals, an optical fiber for optical communication, or a composite cable of these.

[0406] In the illustrated example, communication is performed by wire using the transmission cable 11400, but communication between the camera head 11102 and the CCU 11201 may also be performed wirelessly.

[0407] <Application to moving objects> The technology according to the present disclosure (the present technology) can be applied to various products. For example, the technology according to the present disclosure may be realized as a device mounted on any type of moving body, such as an automobile, an electric vehicle, a hybrid electric vehicle, a motorcycle, a bicycle, personal mobility, an airplane, a drone, a ship, or a robot.

[0408] FIG. 82 is a block diagram showing a schematic configuration example of a vehicle control system, which is an example of a mobile object control system to which the technology according to the present disclosure can be applied.

[0409] The vehicle control system 12000 includes a plurality of electronic control units connected via a communication network 12001. In the example shown in Fig. 82, the vehicle control system 12000 includes a drive system control unit 12010, a body system control unit 12020, an outside-vehicle information detection unit 12030, an inside-vehicle information detection unit 12040, and an integrated control unit 12050. Also shown as functional components of the integrated control unit 12050 are a microcomputer 12051, an audio / video output unit 12052, and an in-vehicle network I / F (Interface) 12053.

[0410] The drivetrain control unit 12010 controls the operation of devices related to the drivetrain of the vehicle in accordance with various programs. For example, the drivetrain control unit 12010 functions as a control device for a drive force generating device for generating a drive force of the vehicle, such as an internal combustion engine or a drive motor, a drive force transmission mechanism for transmitting the drive force to the wheels, a steering mechanism for adjusting the steering angle of the vehicle, a braking device for generating a braking force of the vehicle, etc.

[0411] The body system control unit 12020 controls the operation of various devices equipped in the vehicle body according to various programs. For example, the body system control unit 12020 functions as a control device for a keyless entry system, a smart key system, a power window device, or various lamps such as headlamps, backup lamps, brake lamps, turn signals, and fog lamps. In this case, radio waves transmitted from a portable device that serves as a key or signals from various switches may be input to the body system control unit 12020. The body system control unit 12020 receives these radio waves or signals and controls the vehicle's door lock device, power window device, lamps, etc.

[0412] The outside-vehicle information detection unit 12030 detects information outside the vehicle equipped with the vehicle control system 12000. For example, an imaging unit 12031 is connected to the outside-vehicle information detection unit 12030. The outside-vehicle information detection unit 12030 causes the imaging unit 12031 to capture images outside the vehicle and receives the captured images. The outside-vehicle information detection unit 12030 may perform object detection processing or distance detection processing for people, cars, obstacles, signs, characters on the road surface, etc., based on the received images.

[0413] The imaging unit 12031 is an optical sensor that receives light and outputs an electrical signal according to the amount of light received. The imaging unit 12031 can output the electrical signal as an image, or as distance measurement information. The light received by the imaging unit 12031 may be visible light or invisible light such as infrared light.

[0414] The in-vehicle information detection unit 12040 detects information inside the vehicle. For example, a driver state detection unit 12041 that detects the state of the driver is connected to the in-vehicle information detection unit 12040. The driver state detection unit 12041 includes, for example, a camera that captures an image of the driver, and the in-vehicle information detection unit 12040 may calculate the degree of fatigue or concentration of the driver based on the detection information input from the driver state detection unit 12041, or may determine whether the driver is dozing off.

[0415] The microcomputer 12051 can calculate control target values ​​for the driving force generating device, steering mechanism, or braking device based on the information inside and outside the vehicle acquired by the outside-vehicle information detection unit 12030 or the inside-vehicle information detection unit 12040, and output control commands to the drivetrain control unit 12010. For example, the microcomputer 12051 can perform cooperative control aimed at realizing the functions of an ADAS (Advanced Driver Assistance System), including avoiding or mitigating collisions between vehicles, following based on the distance between vehicles, maintaining vehicle speed, warning of vehicle collisions, or warning of vehicle lane departure.

[0416] In addition, the microcomputer 12051 can perform cooperative control for the purpose of autonomous driving, which allows the vehicle to travel autonomously without relying on driver operation, by controlling the driving force generating device, steering mechanism, braking device, etc. based on information about the surroundings of the vehicle obtained by the outside vehicle information detection unit 12030 or the inside vehicle information detection unit 12040.

[0417] Furthermore, the microcomputer 12051 can output a control command to the body system control unit 12020 based on the information about the outside of the vehicle acquired by the outside information detection unit 12030. For example, the microcomputer 12051 can control the headlamps according to the position of a preceding vehicle or an oncoming vehicle detected by the outside information detection unit 12030, and perform cooperative control for the purpose of preventing glare, such as switching from high beams to low beams.

[0418] The audio / video output unit 12052 transmits at least one output signal of audio and / or video to an output device capable of visually or audibly notifying information to passengers in the vehicle or to the outside of the vehicle. In the example of Fig. 82, an audio speaker 12061, a display unit 12062, and an instrument panel 12063 are exemplified as output devices. The display unit 12062 may include, for example, at least one of an on-board display and a head-up display.

[0419] FIG. 83 is a diagram showing an example of the installation position of the imaging unit 12031.

[0420] In FIG. 83, the imaging unit 12031 includes imaging units 12101, 12102, 12103, 12104, and 12105.

[0421] The imaging units 12101, 12102, 12103, 12104, and 12105 are provided, for example, at positions such as the front nose, side mirrors, rear bumper, back door, and the top of the windshield inside the vehicle cabin of the vehicle 12100. The imaging unit 12101 provided at the front nose and the imaging unit 12105 provided at the top of the windshield inside the vehicle cabin mainly acquire images of the front of the vehicle 12100. The imaging units 12102 and 12103 provided at the side mirrors mainly acquire images of the sides of the vehicle 12100. The imaging unit 12104 provided at the rear bumper or back door mainly acquires images of the rear of the vehicle 12100. The imaging unit 12105 provided at the top of the windshield inside the vehicle cabin is mainly used to detect preceding vehicles, pedestrians, obstacles, traffic lights, traffic signs, lanes, etc.

[0422] 83 shows an example of the imaging ranges of the imaging units 12101 to 12104. Imaging range 12111 indicates the imaging range of the imaging unit 12101 provided on the front nose, imaging ranges 12112 and 12113 indicate the imaging ranges of the imaging units 12102 and 12103 provided on the side mirrors, respectively, and imaging range 12114 indicates the imaging range of the imaging unit 12104 provided on the rear bumper or back door. For example, by overlaying the image data captured by the imaging units 12101 to 12104, a bird's-eye view image of the vehicle 12100 viewed from above can be obtained.

[0423] At least one of the imaging units 12101 to 12104 may have a function of acquiring distance information. For example, at least one of the imaging units 12101 to 12104 may be a stereo camera made up of multiple imaging elements, or may be an imaging element having pixels for phase difference detection.

[0424] For example, the microcomputer 12051 can calculate the distance to each three-dimensional object within the imaging ranges 12111 to 12114 and the change in this distance over time (relative speed with respect to the vehicle 12100) based on the distance information obtained from the imaging units 12101 to 12104, thereby extracting as a preceding vehicle, in particular, the three-dimensional object that is the closest three-dimensional object on the path of the vehicle 12100 and traveling in approximately the same direction as the vehicle 12100 at a predetermined speed (for example, 0 km / h or higher). Furthermore, the microcomputer 12051 can set a vehicle-to-vehicle distance to be maintained in advance in front of the preceding vehicle, and perform automatic braking control (including follow-up stop control), automatic acceleration control (including follow-up start control), etc. In this way, cooperative control can be performed for the purpose of automatic driving, which runs autonomously without relying on driver operation.

[0425] For example, the microcomputer 12051 classifies and extracts three-dimensional object data regarding three-dimensional objects into two-wheeled vehicles, ordinary vehicles, large vehicles, pedestrians, utility poles, and other three-dimensional objects based on distance information obtained from the imaging units 12101 to 12104, and can use the data for automatic obstacle avoidance. For example, the microcomputer 12051 distinguishes obstacles around the vehicle 12100 into obstacles that are visible to the driver of the vehicle 12100 and obstacles that are difficult to see. The microcomputer 12051 then determines the collision risk, which indicates the degree of risk of collision with each obstacle, and when the collision risk is equal to or greater than a set value and a collision is possible, the microcomputer 12051 can provide driving assistance for collision avoidance by outputting an alarm to the driver via the audio speaker 12061 or the display unit 12062, or by performing forced deceleration or avoidance steering via the drivetrain control unit 12010.

[0426] At least one of the image capturing units 12101 to 12104 may be an infrared camera that detects infrared rays. For example, the microcomputer 12051 can recognize a pedestrian by determining whether or not a pedestrian is present in the images captured by the image capturing units 12101 to 12104. The pedestrian recognition is performed, for example, by extracting feature points from the images captured by the image capturing units 12101 to 12104, which are infrared cameras, and then performing pattern matching on a series of feature points that indicate the outline of an object to determine whether or not the object is a pedestrian. When the microcomputer 12051 determines that a pedestrian is present in the images captured by the image capturing units 12101 to 12104 and recognizes the pedestrian, the audio / image output unit 12052 controls the display unit 12062 to superimpose a rectangular outline on the recognized pedestrian for emphasis. The audio / image output unit 12052 may also control the display unit 12062 to display an icon or the like indicating the pedestrian at a desired position.

[0427] In this specification, a system refers to an entire device made up of multiple devices.

[0428] The effects described in this specification are merely examples and are not limiting, and other effects may also be present.

[0429] It should be noted that the embodiments of the present technology are not limited to the above-described embodiments, and various modifications are possible within the scope of the present technology.

[0430] The present technology can also be configured as follows. (1) a pixel including a photoelectric conversion unit; a charge storage unit that stores charges generated by the photoelectric conversion unit; a transfer unit that transfers the charges accumulated in the photoelectric conversion unit to the charge storage unit; an amplifying transistor that amplifies a signal voltage corresponding to the charge held in the charge holding portion; Equipped with the charge storage unit is shared by four of the pixels and is disposed at the center of the four transfer units; a first small pixel group including the first charge retention portion, a first region in which a transistor including the amplification transistor is arranged, a second small pixel group including the second charge retention portion, and a third small pixel group including the third charge retention portion are arranged in this order; a first distance between the first charge retention portion and the second charge retention portion and a second distance between the second charge retention portion and the third charge retention portion are different from each other; Light detection device. (2) The small pixel group is composed of four pixels of 2×2, The large pixel group is composed of four 2x2 units of the small pixel group, The first region is arranged in the vertical or horizontal direction of the central region of the large pixel group. The photodetector according to (1) above. (3) The small pixel group is composed of four pixels of 2×2, The large pixel group is composed of four 1x4 units of the small pixel group, The first region is disposed between a first large pixel group and a second large pixel group adjacent to the first large pixel group. The photodetector according to (1) above. (4) The small pixel group is composed of four pixels of 2×2, The large pixel group is composed of four small pixel groups of 4 × 1 units, The first region is disposed between a first large pixel group and a second large pixel group adjacent to the first large pixel group. The photodetector according to (1) above. (5) the first to fourth charge retention units included in the small pixel group are connected to a fifth charge retention unit provided in the first region, The first to fifth charge holding units are shared by 16 pixels included in the large pixel group. The photodetector according to any one of (2) to (4) above. (6) the first sub-pixel group, the first region, and the second sub-pixel group are included in a first large pixel group; The third small pixel group is included in a second large pixel group adjacent to the first large pixel group. The photodetector according to any one of (2) to (5) above. (7) The transfer unit has an electrode in the photoelectric conversion unit. The photodetector according to any one of (1) to (6) above. (8) A region in which P-type or N-type impurities are diffused is provided between the transfer sections. The photodetector according to any one of (1) to (7) above. (9) An oxide film is provided between the transfer sections. The photodetector according to any one of (1) to (7) above. (10) The transfer section has an electrode in contact with the oxide film. The photodetector according to (9) above. (11) The first region includes an element isolation portion formed of an oxide film. The photodetector according to any one of (1) to (10) above. (12) a transistor for processing a signal from a pixel included in the large pixel group is disposed in the first region provided across the large pixel group and the other large pixel group; The first to fifth charge holding portions are connected by linear wiring. The photodetector according to (5) above. (13) a transistor for processing a signal from a pixel included in the large pixel group is disposed in the first region provided in the large pixel group itself; Among the wirings connecting the first to fifth charge retention units, the wiring connected to the fifth charge retention unit has a bent portion. The photodetector according to (5) above. (14) a pixel including a photoelectric conversion unit; a charge storage unit that stores charges generated by the photoelectric conversion unit; a transfer unit that transfers the charges accumulated in the photoelectric conversion unit to the charge storage unit; an amplifying transistor that amplifies a signal voltage corresponding to the charge held in the charge holding portion; Equipped with the charge storage unit is shared by four of the pixels and is disposed at the center of the four transfer units; a first small pixel group including the first charge retention portion, a first region in which a transistor including the amplification transistor is arranged, a second small pixel group including the second charge retention portion, and a third small pixel group including the third charge retention portion are arranged in this order; a first distance between the first charge retention portion and the second charge retention portion and a second distance between the second charge retention portion and the third charge retention portion are different from each other; a photodetector; a processing unit that processes a signal from the photodetector; An electronic device comprising: [Explanation of symbols]

[0431] 1 photodetector, 2 pixel, 5 column signal processing circuit, 6 horizontal drive circuit, 7 output circuit, 8 control circuit, 9 vertical signal line, 10 pixel drive line, 11 horizontal signal line, 13 input / output terminal, 20 small pixel group, 22 transfer gate, 24 contact, 25 reset transistor, 26 amplification transistor, 27 selection transistor, 29 VSL region, 31 PD, 32 inter-pixel isolation section, 33 FLAT isolation section, 35 cell well, 37 channel region, 40 wiring, 50 large pixel group, 70 active region

Claims

1. a pixel including a photoelectric conversion unit; a charge storage unit that stores charges generated by the photoelectric conversion unit; a transfer unit that transfers the charges accumulated in the photoelectric conversion unit to the charge storage unit; an amplifying transistor that amplifies a signal voltage corresponding to the charge held in the charge holding portion; Equipped with the charge storage unit is shared by four of the pixels and is disposed at the center of the four transfer units; a first small pixel group including the first charge retention portion, a first region in which a transistor including the amplification transistor is arranged, a second small pixel group including the second charge retention portion, and a third small pixel group including the third charge retention portion are arranged in this order; A first distance between the first charge holding portion and the second charge holding portion is different from a second distance between the second charge holding portion and the third charge holding portion. Light detection device.

2. The small pixel group is composed of four pixels, 2×2, The large pixel group is composed of four 2×2 units of the small pixel group, The first region is arranged in the vertical or horizontal direction of the central region of the large pixel group. The photodetector device according to claim 1 .

3. The small pixel group is composed of four pixels, 2×2, The large pixel group is composed of four 1×4 units of the small pixel group, The first region is disposed between a first large pixel group and a second large pixel group adjacent to the first large pixel group. The photodetector device according to claim 1 .

4. The small pixel group is composed of four pixels, 2×2, The large pixel group is composed of four small pixel groups of 4×1 units, The first region is disposed between a first large pixel group and a second large pixel group adjacent to the first large pixel group. The photodetector device according to claim 1 .

5. the first to fourth charge retention units included in the small pixel group are connected to a fifth charge retention unit provided in the first region, The first to fifth charge holding units are shared by 16 pixels included in the large pixel group. The photodetector device according to claim 2 .

6. the first sub-pixel group, the first region, and the second sub-pixel group are included in a first large pixel group; The third small pixel group is included in a second large pixel group adjacent to the first large pixel group. The photodetector device according to claim 2 .

7. The transfer unit has an electrode in the photoelectric conversion unit. The photodetector device according to claim 1 .

8. A region in which P-type or N-type impurities are diffused is provided between the transfer sections. The photodetector device according to claim 1 .

9. An oxide film is provided between the transfer sections. The photodetector device according to claim 1 .

10. The transfer section has an electrode in contact with the oxide film. The photodetector device according to claim 9 .

11. The first region includes an element isolation portion formed of an oxide film. The photodetector device according to claim 1 .

12. a transistor for processing a signal from a pixel included in the large pixel group is disposed in the first region provided across the large pixel group and the other large pixel group; The first to fifth charge holding portions are connected by linear wiring.

6. The photodetector according to claim 5.

13. a transistor for processing a signal from a pixel included in the large pixel group is disposed in the first region provided in the large pixel group itself; Among the wirings connecting the first to fifth charge retention units, the wiring connected to the fifth charge retention unit has a bent portion.

6. The photodetector according to claim 5.

14. a pixel including a photoelectric conversion unit; a charge storage unit that stores charges generated by the photoelectric conversion unit; a transfer unit that transfers the charges accumulated in the photoelectric conversion unit to the charge storage unit; an amplifying transistor that amplifies a signal voltage corresponding to the charge held in the charge holding portion; Equipped with the charge storage unit is shared by four of the pixels and is disposed at the center of the four transfer units; a first small pixel group including the first charge retention portion, a first region in which a transistor including the amplification transistor is arranged, a second small pixel group including the second charge retention portion, and a third small pixel group including the third charge retention portion are arranged in this order; A first distance between the first charge holding portion and the second charge holding portion is different from a second distance between the second charge holding portion and the third charge holding portion. a photodetector; a processing unit that processes a signal from the photodetector; An electronic device comprising:

Images