Electro-optical device, and electronic apparatus

Abstract

To provide an electro-optical device that can reduce a cost for the device, and an electronic apparatus.SOLUTION: An electro-optical device comprises: a pixel electrode; a TFT provided in correspondence with the pixel electrode; a capacitive element 16B having a first capacitive electrode 16B1 electrically connected to the pixel electrode, a capacitive insulating layer 16B2, and a second capacitive electrode 16B3 provided via the first capacitive electrode 16B1 and the capacitive insulating layer 16B2; and a first relay layer 16B3a electrically connected to the pixel electrode and the TFT and provided on the same layer as the second capacitive electrode 16B3. The first capacitive electrode 16B1 extends to a position overlapping the first relay layer 16B3a in plan view, and is electrically connected to the first relay layer 16B3a.SELECTED DRAWING: Figure 7

Description

[Technical Field]

[0001] The present invention relates to an electro-optical device and an electronic device. [Background technology]

[0002] Patent Document 1 discloses the configuration of an electro-optical device in which a capacitor including a second capacitor electrode to which the potential of the pixel electrode is applied and a relay electrode to which the potential of the pixel electrode is applied are provided in the same layer below the pixel electrode. The capacitor is formed in a trench portion. The relay electrode is connected via an electrode in a contact hole to electrically connect to the transistor in the lower layer. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] Japanese Patent Application Publication No. 2018-40969 Summary of the Invention [Problem to be solved by the invention]

[0004] However, in the configuration of Patent Document 1, the trench portion and the contact hole, which are arranged in the same layer, must be formed in separate steps, which poses a problem of increasing the number of steps. [Means for solving the problem]

[0005] The electro-optical device comprises a capacitive element having a pixel electrode, a transistor corresponding to the pixel electrode, a first capacitance electrode electrically connected to the pixel electrode, a capacitance insulating layer, and a second capacitance electrode provided between the first capacitance electrode and the capacitance insulating layer, and a first relay layer electrically connected to the pixel electrode and the transistor and provided in the same layer as the second capacitance electrode, wherein the first capacitance electrode extends to a position overlapping with the first relay layer in a planar view and is electrically connected to the first relay layer.

[0006] The electronic device includes the electro-optical device described above. [Brief explanation of the drawings]

[0007] [Figure 1] FIG. 1 is a plan view showing the configuration of a liquid crystal device as an electro-optical device. [Figure 2] FIG. 2 is a cross-sectional view of the liquid crystal device shown in FIG. 1 taken along line HH. [Figure 3] FIG. 2 is an equivalent circuit diagram showing the electrical configuration of the liquid crystal device. [Figure 4] FIG. 2 is a plan view showing the arrangement of pixels of a liquid crystal device. [Figure 5] FIG. 4 is a cross-sectional view showing the structure of a non-opening region of the liquid crystal device. [Figure 6] FIG. 2 is a plan view showing the configuration of a pixel. [Figure 7] FIG. 7 is a cross-sectional view of the pixel shown in FIG. 6 taken along line AA. [Figure 8] FIG. 7 is a cross-sectional view of the pixel shown in FIG. 6 taken along line BB. [Figure 9] 5A to 5C are plan views showing a method for manufacturing pixels of a liquid crystal device. [Figure 10] FIG. 10 is a cross-sectional view of the pixel shown in FIG. 9 taken along line AA. [Figure 11] 5A to 5C are plan views showing a method for manufacturing pixels of a liquid crystal device. [Figure 12] FIG. 12 is a cross-sectional view of the pixel shown in FIG. 11 taken along line AA. [Figure 13] 5A to 5C are plan views showing a method for manufacturing pixels of a liquid crystal device. [Figure 14] FIG. 14 is a cross-sectional view of the pixel shown in FIG. 13 taken along line AA. [Figure 15] 5A to 5C are plan views showing a method for manufacturing pixels of a liquid crystal device. [Figure 16] FIG. 16 is a cross-sectional view of the pixel shown in FIG. 15 taken along line AA. [Figure 17] 5A to 5C are plan views showing a method for manufacturing pixels of a liquid crystal device. [Figure 18] FIG. 18 is a cross-sectional view of the pixel shown in FIG. 17 taken along line AA. [Figure 19] FIG. 1 is a schematic diagram showing the configuration of a projector as an electronic device. [Figure 20]FIG. 10 is a cross-sectional view showing the configuration of a connection portion of a modified example. DETAILED DESCRIPTION OF THE INVENTION

[0008] DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, embodiments of the present invention will be described with reference to the accompanying drawings. In the drawings, the dimensions of some components may be shown on different scales to make the components easier to see.

[0009] In the following figures, the three mutually perpendicular axes will be referred to as the X-axis, Y-axis, and Z-axis. The direction along the X-axis will be referred to as the "X-direction," the direction along the Y-axis will be referred to as the "Y-direction," and the direction along the Z-axis will be referred to as the "Z-direction." The direction of the arrow is the + direction, and the direction opposite to the + direction is referred to as the - direction. Note that viewing from the +Z direction or -Z direction is also referred to as planar view or planar.

[0010] Furthermore, in the following description, for example, the expression "on the substrate" in relation to a substrate means that the substrate is placed in contact with the substrate, that the substrate is placed via another structure, or that a portion of the substrate is placed in contact with the substrate and a portion of the substrate is placed via another structure.

[0011] In this embodiment, an active drive type liquid crystal device 100 having a TFT (Thin Film Transistor) as a switching element for each pixel will be described as an example of the electro-optical device. The liquid crystal device 100 is used as a light modulation device in, for example, a projector as an electronic device, which will be described later.

[0012] First, the configuration of a liquid crystal device 100 will be described with reference to FIGS.

[0013] As shown in FIGS. 1 and 2, a liquid crystal device 100 of this embodiment includes an element substrate 10 and an opposing substrate 20 arranged opposite to each other, and a liquid crystal layer 15 sandwiched between the pair of substrates.

[0014] The base material 11a of the element substrate 10 and the base material 11b of the counter substrate 20 are made of a light-transmitting material such as a quartz substrate or a glass substrate. In this embodiment, light-transmitting material refers to a property that allows at least 85% or more of light in the visible light region to be transmitted.

[0015] The element substrate 10 is slightly larger than the counter substrate 20. The element substrate 10 and the counter substrate 20 are bonded together via a sealant 14 arranged in a frame shape along the outer edge of the counter substrate 20, and a liquid crystal layer 15 is formed by sealing a liquid crystal having positive or negative dielectric anisotropy in the gap therebetween.

[0016] An adhesive such as a thermosetting or ultraviolet-curing epoxy resin is used as the sealing material 14. The sealing material 14 contains spacers (not shown) for maintaining a constant gap between the pair of substrates.

[0017] A display region E in which a plurality of pixels P are arranged in a matrix is ​​provided inside the sealant 14. A light-shielding portion 18 surrounding the display region E is provided on the counter substrate 20 between the sealant 14 and the display region E. The light-shielding portion 18 is made of, for example, a light-shielding metal or metal oxide. Note that the display region E may include dummy pixels arranged to surround the plurality of pixels P in addition to the plurality of pixels P that contribute to display.

[0018] The element substrate 10 is provided with a terminal section in which a plurality of external connection terminals 41 are arranged. A data line driving circuit 22 is provided between a first side of the element substrate 10 along the terminal section and the sealing material 14. In addition, an inspection circuit 25 is provided between the sealing material 14 and the display region E along a second side opposite to the first side.

[0019] Furthermore, a scanning line driving circuit 24 is provided between the sealant 40 and the display region E along the third and fourth sides that are perpendicular to the first side and face each other. A plurality of wirings (not shown) that connect the two scanning line driving circuits 24 are provided between the sealant 14 on the second side and the inspection circuit 25.

[0020] Wiring lines connected to the data line driving circuit 22 and the scanning line driving circuit 24 are connected to a plurality of external connection terminals 41 arranged along the first side. Hereinafter, the direction along the first side will be referred to as the X direction, and the directions along the third and fourth sides will be referred to as the Y direction. The X direction corresponds to the first direction in this embodiment, and the Y direction corresponds to the second direction in this embodiment.

[0021] 2, the element substrate 10 includes a base material 11a, TFTs 30 as transistors formed on the surface of the base material 11a facing the liquid crystal layer 15, pixel electrodes 27, and an alignment film 28 covering the pixel electrodes 27. The TFTs 30 and the pixel electrodes 27 are components of pixels P. Details of the pixels P will be described later.

[0022] The counter substrate 20 includes a base material 11b, and a light-shielding portion 18, a common electrode 31, a planarizing layer (not shown), an alignment film 32, and the like, which are laminated in this order on the surface of the base material 11b facing the liquid crystal layer 15.

[0023] 1, the light-shielding portion 18 surrounds the display area E and is provided at a position overlapping the scanning line driving circuit 24 and the inspection circuit 25 in plan view. This serves to block light incident on the peripheral circuits including these driving circuits from the counter substrate 20 side, preventing the peripheral circuits from malfunctioning due to light. In addition, the light is blocked to prevent unnecessary stray light from entering the display area E, ensuring high contrast in the display of the display area E.

[0024] The planarization layer is made of an inorganic material such as silicon oxide, has light-transmitting properties, and is provided to cover the light-shielding portion 18. The planarization layer is, for example, a silicon oxide film formed using a plasma CVD method or the like. The planarization layer has a thickness that is sufficient to reduce the unevenness of the surface of the common electrode 31 formed on the planarization layer.

[0025] The common electrode 31 is made of a transparent conductive film such as ITO (Indium Tin Oxide) or IZO (Indium Zinc Oxide). The common electrode 31 covers the planarizing layer and is electrically connected to wiring on the element substrate 10 side by vertical conductive parts 26 provided at the four corners of the counter substrate 20, as shown in FIG.

[0026] The alignment film 28 covering the pixel electrodes 27 and the alignment film 32 covering the common electrode 31 are set based on the optical design of the liquid crystal device 100, and employ obliquely evaporated films (inorganic alignment films) made of inorganic materials such as silicon oxide. The alignment films 28 and 32 may employ organic alignment films such as polyimide instead of inorganic alignment films.

[0027] The liquid crystal device 100 is a transmissive type, and employs an optical design of a normally white mode in which the pixel P displays bright when not driven, or a normally black mode in which the pixel P displays dark when not driven. The liquid crystal device 100 is used with polarizing elements arranged on both the light incident side and light exit side according to the optical design.

[0028] Next, the electrical configuration of the liquid crystal device 100 will be described with reference to FIG.

[0029] 3, the liquid crystal device 100 has a plurality of scanning lines 3a and a plurality of data lines 6a that are insulated from each other and intersect at right angles, and a capacitance line 3b, at least in a display region E. The data lines 6a correspond to signal lines.

[0030] In the region partitioned by the scanning lines 3a and the data lines 6a, a pixel electrode 27, a TFT 30, and a capacitance element 16 are provided, which constitute the pixel circuit of the pixel P.

[0031] The scanning line 3a is electrically connected to the gate of the TFT 30. The data line 6a is electrically connected to a first source / drain region 30d (see FIG. 5) of the TFT 30. The pixel electrode 27 is electrically connected to a second source / drain region 30s (see FIG. 5) of the TFT 30.

[0032] The data lines 6a are connected to a data line driving circuit 22 (see FIG. 1). Image signals D1, D2, ..., Dn are supplied from the data line driving circuit 22 to each pixel P via the data lines 6a. The scanning lines 3a are connected to a scanning line driving circuit 24 (see FIG. 1). Scanning signals SC1, SC2, ..., SCm are supplied from the scanning line driving circuit 24 to each pixel P via the scanning lines 3a.

[0033] The image signals D1 to Dn supplied from the data line driving circuit 22 may be supplied to the data lines 6a in this order in a line-sequential manner, or may be supplied to adjacent data lines 6a in groups. The scanning line driving circuit 24 supplies scanning signals SC1 to SCm to the scanning lines 3a in a line-sequential manner in pulse form at predetermined timing.

[0034] The liquid crystal device 100 is configured such that the TFTs 30, which are switching elements, are turned on for a certain period of time in response to input of scanning signals SC1 to SCm, and thereby the image signals D1 to Dn supplied from the data lines 6a are written at a predetermined timing to the pixel electrodes 27. The image signals D1 to Dn, which have a predetermined level and are written to the liquid crystal layer 15 via the pixel electrodes 27, are held between the pixel electrodes 27 and the common electrode 31 for a certain period of time.

[0035] In order to prevent leakage of the held image signals D1 to Dn, a capacitive element 16 is connected in parallel to the liquid crystal capacitance formed between the pixel electrode 27 and the common electrode 31. In this embodiment, the capacitive element 16 includes a capacitive element 16A and a capacitive element 16B (see FIG. 5).

[0036] Next, the pixel arrangement will be described with reference to FIG.

[0037] 4, the pixel P in the liquid crystal device 100 has, for example, an aperture region that is substantially rectangular in plan view. The aperture region is surrounded by light-shielding non-aperture regions that extend in the X and Y directions and are arranged in a grid pattern.

[0038] The non-opening region extending in the X direction is provided with the scanning lines 3a shown in Fig. 3. The scanning lines 3a are made of a light-blocking conductive material, and at least a part of the non-opening region is formed by the scanning lines 3a.

[0039] The non-opening region extending in the Y direction is provided with the data lines 6a and the capacitance lines 3b shown in Fig. 3. The data lines 6a and the capacitance lines 3b are made of a light-shielding conductive material, and they form at least a part of the non-opening region.

[0040] The non-aperture region can be configured not only by signal lines provided on the element substrate 10 side, but also by light-shielding portions 18 (see FIG. 1) patterned in a grid shape on the counter substrate 20 side.

[0041] The TFT 30 and the capacitance element 16 shown in Fig. 3 are provided near the intersection of the non-aperture region. By providing the TFT 30 near the intersection of the non-aperture region, which has light-shielding properties, it is possible to prevent the TFT 30 from malfunctioning due to light and to ensure the aperture ratio in the aperture region. By providing the TFT 30 and the capacitance element 16 near the intersection, the width of the non-aperture region near the intersection is wider than other parts.

[0042] A pixel electrode 27 is provided in the pixel P. The pixel electrode 27 has a substantially square shape in a plan view, and is provided in the aperture region so that the outer edge of the pixel electrode 27 overlaps with the non-aperture region.

[0043] Next, the configuration of the pixel P will be described with reference to Fig. 5. The pixel P shown in Fig. 5 is a schematic cross-sectional view for easily explaining the structure of the element substrate 10.

[0044] As shown in FIG. 5, the element substrate 10 has a scanning line 3a arranged on a base material 11a, the scanning line 3a functioning as a light-shielding portion made of a metal element, alloy, metal silicide, polysilicide, a laminate of these, or conductive polysilicon, containing at least one of high-melting-point metals such as Ti, Cr, Mo, Ta, and W.

[0045] The scanning lines 3a are preferably formed using metal silicide from the viewpoints of blocking return light incident from the base material 11a side and not reflecting incident light incident from the counter substrate 20 side. The scanning lines 3a in this embodiment are made of, for example, WSi (tungsten silicide). The thickness of the scanning lines 3a is, for example, 200 nm.

[0046] A first interlayer insulating layer 12a is disposed on the scanning lines 3a. The first interlayer insulating layer 12a is made of, for example, silicon oxide. The thickness of the first interlayer insulating layer 12a is, for example, 450 nm.

[0047] A semiconductor layer 30a of the TFT 30 is disposed on the first interlayer insulating layer 12a. The semiconductor layer 30a is made of, for example, polysilicon. Impurity ions are selectively implanted into the semiconductor layer 30a to form a first source / drain region 30d including an LDD (Lightly Doped Drain) structure, a channel region 30c, and a second source / drain region 30s including an LDD structure. The thickness of the semiconductor layer 30a is, for example, 40 nm.

[0048] A gate insulating layer 30b is disposed on the semiconductor layer 30a. The gate insulating layer 30b is made of, for example, silicon oxide. The thickness of the gate insulating layer 30b is, for example, 90 nm.

[0049] A gate electrode 30g is disposed on the gate insulating layer 30b. The gate electrode 30g may be, for example, a conductive polysilicon film with a metal silicide film stacked thereon. The gate electrode 30g is electrically connected to the scanning line 3a via a contact electrode (not shown).

[0050] A second interlayer insulating layer 12b is disposed on the gate electrode 30g, the gate insulating layer 30b, and the first interlayer insulating layer 12a. The second interlayer insulating layer 12b is made of, for example, silicon oxide. The thickness of the second interlayer insulating layer 12b is, for example, 300 nm.

[0051] A first shield layer 13a is disposed on the second interlayer insulating layer 12b. The first shield layer 13a is formed by depositing and patterning a conductive film. The first shield layer 13a is disposed so as to overlap the gate electrode 30g with the second interlayer insulating layer 12b interposed therebetween. The first shield layer 13a is made of, for example, a metal nitride film such as TiN. The thickness of the first shield layer 13a is 150 nm.

[0052] A third interlayer insulating layer 12c is disposed on the first shield layer 13a and the second interlayer insulating layer 12b. The third interlayer insulating layer 12c is made of, for example, silicon oxide. The thickness of the third interlayer insulating layer 12c is, for example, 400 nm.

[0053] Contact holes CNT17a and CNT17b are formed in the third interlayer insulating layer 12c, the second interlayer insulating layer 12b, and the gate insulating layer 30b, penetrating to the semiconductor layer 30a at positions overlapping with the first source-drain region 30d and the second source-drain region 30s of the semiconductor layer 30a. A first source-drain electrode 16d is disposed on the third interlayer insulating layer 12c from inside the contact hole CNT17a that penetrates to the first source-drain region 30d. A second source-drain electrode 16s is disposed on the third interlayer insulating layer 12c from inside the contact hole CNT17b that penetrates to the second source-drain region 30s.

[0054] The conductive film used for the first source-drain electrode 16d and the second source-drain electrode 16s may be made of a low-resistance wiring material, such as a metal such as Al (aluminum) or Ti (titanium), or a metal compound thereof. The conductive film of this embodiment has a four-layer structure of, from the substrate 11a side, a Ti (titanium) layer / TiN (titanium nitride) layer / Al (aluminum) layer / TiN (titanium nitride) layer.

[0055] From the substrate 11a side, the Ti layer has a thickness of, for example, 20 nm. The TiN layer has a thickness of, for example, 50 nm. The Al layer has a thickness of, for example, 300 nm. The TiN layer has a thickness of, for example, 150 nm. The first shield layer 13a is disposed between the gate electrode 30g and the first source / drain electrode 16d.

[0056] A fourth interlayer insulating layer 12d is disposed on the first source-drain electrode 16d and the second source-drain electrode 16s. The fourth interlayer insulating layer 12d is made of, for example, silicon oxide. The fourth interlayer insulating layer 12d has a thickness of, for example, 200 nm. A portion of the first source-drain electrode 16d is used as a second capacitor electrode 16A3.

[0057] A contact hole CNT17c is formed in the fourth interlayer insulating layer 12d in a portion overlapping with the first source-drain electrode 16d. A capacitive insulating layer 16A2 and a second shield layer 13b, which also functions as a first capacitive electrode 16A1, are arranged from inside the contact hole CNT17c to on the fourth interlayer insulating layer 12d. The first capacitive electrode 16A1, the capacitive insulating layer 16A2, and the second capacitive electrode 16A3 are stacked to form the capacitive element 16A.

[0058] The capacitive insulating layer 16A2 may be, for example, a multilayer film formed by repeatedly laminating an aluminum oxide (Al2O3) film and a hafnium oxide (HfO2) film in this order. The capacitive insulating layer 16A2 may have a thickness of, for example, 34 nm. The second capacitive electrode 16A3 may be, for example, a titanium nitride (TiN) film. The second shield layer 13b may have a thickness of, for example, 200 nm.

[0059] A fifth interlayer insulating layer 12e is disposed on the second shield layer 13b and the fourth interlayer insulating layer 12d. The fifth interlayer insulating layer 12e is made of, for example, silicon oxide. The thickness of the fifth interlayer insulating layer 12e is, for example, 600 nm.

[0060] In the fifth interlayer insulating layer 12e and the fourth interlayer insulating layer 12d, a contact hole CNT17d is formed in a portion overlapping with the first source-drain electrode 16d, and a contact hole CNT17e is formed in a portion overlapping with the second source-drain electrode 16s.

[0061] A relay layer 6b is disposed from inside the contact hole CNT17d to on the fifth interlayer insulating layer 12e. A data line 6a is disposed from inside the contact hole CNT17e to on the fifth interlayer insulating layer 12e. The relay layer 6b functions to electrically connect the first source-drain electrode 16d and the pixel electrode 27.

[0062] The conductive film constituting the relay layer 6b and the data line 6a may have, for example, a three-layer structure of TiN layer / Al layer / TiN layer from the substrate 11a side. From the substrate 11a side, the thickness of the TiN layer is, for example, 50 nm. The thickness of the Al layer is, for example, 350 nm. The thickness of the TiN layer is, for example, 200 nm.

[0063] A sixth interlayer insulating layer 12f is disposed on the relay layer 6b, the data line 6a, and the fifth interlayer insulating layer 12e. The sixth interlayer insulating layer 12f is made of, for example, silicon oxide. The surface of the sixth interlayer insulating layer 12f is planarized by, for example, chemical mechanical polishing (CMP). The thickness of the sixth interlayer insulating layer 12f is, for example, 900 nm.

[0064] In the sixth interlayer insulating layer 12f and the fifth interlayer insulating layer 12e, a contact hole CNT17f is formed in a portion overlapping with the second shield layer 13b. In the sixth interlayer insulating layer 12f, a contact hole CNT17g is formed in a portion overlapping with the relay layer 6b.

[0065] A capacitance line 3b is arranged from inside the contact hole CNT17f to on the sixth interlayer insulating layer 12f. A relay layer 3c serving as a second relay layer is arranged from inside the contact hole CNT17g to on the sixth interlayer insulating layer 12f.

[0066] The conductive film constituting the capacitance line 3b and the relay layer 3c may have a two-layer structure of Al layer / TiN layer from the base material 11a side. The thickness of the Al layer is, for example, 200 nm. The thickness of the TiN layer is, for example, 200 nm.

[0067] A seventh interlayer insulating layer 12g is disposed on the capacitor line 3b, the relay layer 3c, and the sixth interlayer insulating layer 12f. The seventh interlayer insulating layer 12g has a contact hole CNT17h formed in a portion overlapping with the relay layer 3c, and a trench portion 17i formed as a groove in a portion overlapping with the capacitor line 3b.

[0068] The seventh interlayer insulating layer 12g is made of, for example, silicon oxide. The seventh interlayer insulating layer 12g has a thickness of, for example, 1000 nm. The trench portion 17i has a depth of, for example, 600 nm.

[0069] A relay layer 16B3a serving as a first relay layer having a function as a relay electrode that electrically connects the pixel electrode 27 and the TFT 30 is disposed from inside the contact hole CNT17h to on the seventh interlayer insulating layer 12g. A capacitive element 16B is disposed from inside the trench portion 17i to on the seventh interlayer insulating layer 12g.

[0070] The capacitive element 16B has a three-layer structure including, from the top, a first capacitive electrode 16B1, a capacitive insulating layer 16B2, and a second capacitive electrode 16B3. The first capacitive electrode 16B1 extends to a position overlapping with the relay layer 16B3a in a plan view and is electrically connected to the relay layer 16B3a.

[0071] The first capacitor electrode 16B1 is made of, for example, a metal nitride film such as TiN. The thickness of the first capacitor electrode 16B1 is, for example, 200 nm. The capacitor insulating layer 16B2 is, for example, a multilayer film in which an aluminum oxide (Al2O3) film and a hafnium oxide (HfO2) film are repeatedly laminated in this order. The thickness of the capacitor insulating layer 16B2 is, for example, 30 nm. The second capacitor electrode 16B3 is made of, for example, a metal nitride film such as TiN. The thickness of the second capacitor electrode 16B3 is, for example, 200 nm.

[0072] The first capacitance electrode 16B1 is provided so as to cover the side surfaces of the second capacitance electrode 16B3 via the capacitance insulating layer 16B2. Since the first capacitance electrode 16B1 is provided so as to cover the side surfaces of the capacitance insulating layer 16B2 and the second capacitance electrode 16B3, it is possible to increase the area in which the capacitance element 16B is formed, thereby improving the capacitance of the capacitance element 16B.

[0073] A relay layer 16B3a electrically connected to the relay layer 3c is disposed on the relay layer 3c. A capacitive element 16 having a second capacitive electrode 16B3 electrically connected to the capacitance line 3b is disposed on the capacitance line 3b.

[0074] The relay layer 16B3a is electrically connected to the first capacitor electrode 16B1 in a region exposed from the insulating layer 16B2a. The capacitor element 16B is configured by stacking three layers: the first capacitor electrode 16B1, a capacitor insulating layer 16B2, and a second capacitor electrode 16B3.

[0075] An eighth interlayer insulating layer 12h is disposed on the first capacitor electrode 16B1 and the seventh interlayer insulating layer 12g. The eighth interlayer insulating layer 12h is made of, for example, silicon oxide. The surface of the eighth interlayer insulating layer 12h is planarized by, for example, CMP processing. The thickness of the eighth interlayer insulating layer 12h is, for example, 400 nm.

[0076] A ninth interlayer insulating layer 12i is disposed on the eighth interlayer insulating layer 12h. A contact hole CNT17j is formed in the ninth interlayer insulating layer 12i at a portion overlapping the first capacitor electrode 16B1. A pixel electrode 27 is disposed on the ninth interlayer insulating layer 12i from inside the contact hole CNT17j.

[0077] The pixel electrode 27 is made of, for example, ITO (Indium Tin Oxide) or IZO (Indium Zinc Oxide). This allows the pixel electrode 27 to be electrically connected to the first capacitor electrode 16B1 via the contact hole CNT17j. The thickness of the pixel electrode 27 is set in consideration of light transmittance so as to obtain a transmittance of at least 85% or more in the visible light wavelength range, and is, for example, 140 nm.

[0078] Next, the configurations of the relay layer 16B3a and the capacitive element 16B will be described in detail with reference to FIGS.

[0079] As shown in Figures 6 and 7, the capacitive element 16B has a first capacitive electrode 16B1 electrically connected to the pixel electrode 27, a capacitive insulating layer 16B2, and a second capacitive electrode 16B3 provided via the first capacitive electrode 16B1 and the capacitive insulating layer 16B2.

[0080] The first capacitor electrode 16B1 is electrically connected to the pixel electrode 27 and the TFT 30. Specifically, the first capacitor electrode 16B1 is electrically connected to the TFT 30 via a relay layer 16B3a.

[0081] As shown in Fig. 7, the relay layer 16B3a is provided in the same layer as the second capacitor electrode 16B3. As shown in Fig. 6, the first capacitor electrode 16B1 is disposed so as to extend to a position overlapping with the relay layer 16B3a in a plan view. The first capacitor electrode 16B1 is electrically connected to the relay layer 16B3a in a region exposed from the insulating layer 16B2a. The length of the exposed region in the X direction is, for example, 0.3 μm to 0.4 μm.

[0082] In this way, the relay layer 16B3a and the first capacitor electrode 16B1 are electrically connected in the region of the first relay layer 16B3a exposed from the insulating layer 16B2a, i.e., the connection portion 19, so that the first capacitor electrode 16B1 to which the potential of the pixel electrode 27 is applied can be electrically connected to the relay layer 16B3a without using a separate contact hole. The width of the first capacitor electrode 16B1 in the second direction is, for example, the same as the width of the first relay layer 16B3a in the first direction (see FIG. 8).

[0083] 6, the second capacitor electrode 16B3 has a main body 21a and a protrusion 21b protruding from the main body 21a in the first and second directions. The relay layer 16B3a is provided separate from the protrusion 21b. The relay layer 16B3a and the protrusion 21b extend in the first direction.

[0084] In this way, since the relay layer 16B3a is provided separate from the protrusion 21b, the potential of the relay layer 16B3a and the potential of the protrusion 21b can be arranged separately. The relay layer 16B3a has the same potential as, for example, the pixel electrode 27. The potential of the protrusion 21b is, for example, the potential of the capacitance line 3b.

[0085] As described above, the seventh interlayer insulating layer 12g has a contact hole CNT17h formed therein for electrically connecting the relay layer 16B3a and the TFT 30. As shown in Fig. 6, the contact hole CNT17h, the region of the relay layer 16B3a exposed from the insulating layer 16B2a, i.e., the connection portion 19, and the protrusion 21b of the second capacitor electrode 16B3 are provided along the first direction.

[0086] In this way, the contact hole CNT17h, the connection portion 19, and the protrusion portion 21b are provided along the first direction, and therefore, for example, by arranging them so as to overlap with the scanning line 3a, it is possible to prevent a decrease in the aperture ratio.

[0087] As described above, the first capacitance electrode 16B1 extends to a position where it overlaps with the relay layer 16B3a, and the relay layer 16B3a and the first capacitance electrode 16B1 are electrically connected. Therefore, the first capacitance electrode 16B1 to which the potential of the pixel electrode 27 is applied can be electrically connected to the relay layer 16B3a without using a separate contact hole to electrically connect the relay layer 16B3a and the first capacitance electrode 16B1.

[0088] 9 to 18, a method for manufacturing the liquid crystal device 100 will be described. Note that the method for manufacturing the relay layer 16B3a including the connection portion 19 and the capacitor element 16B of the liquid crystal device 100 will be mainly described.

[0089] 9 and 10, a contact hole CNT17h and a trench portion 17i are formed in a seventh interlayer insulating layer 12g made of silicon oxide or the like. Specifically, for example, using photolithography and etching, the contact hole CNT17h is formed in the seventh interlayer insulating layer 12g in a portion overlapping with the relay layer 3c, and the trench portion 17i is formed in the seventh interlayer insulating layer 12g in a portion overlapping with the capacitance line 3b.

[0090] 11 and 12, a relay layer 16B3a and a second capacitor electrode 16B3 that constitutes the capacitor element 16B are formed. Specifically, a metal nitride film such as TiN is formed on the seventh interlayer insulating layer 12g, and then patterned to form the relay layer 16B3a on the seventh interlayer insulating layer 12g from inside the contact hole CNT17h, and the second capacitor electrode 16B3 on the seventh interlayer insulating layer 12g from inside the trench portion 17i.

[0091] 13 and 14, a capacitive insulating layer 16B2 is formed to cover the relay layer 16B3a, the second capacitive electrode 16B3, and the seventh interlayer insulating layer 12g. The capacitive insulating layer 16B2 is a multilayer film formed by repeatedly laminating, for example, an aluminum oxide (Al2O3) film and a hafnium oxide (HfO2) film in this order.

[0092] 15 and 16, the capacitive insulating layer 16B2 is patterned. Specifically, the patterning is performed by, for example, etching, so as to leave the capacitive insulating layer 16B2 on the relay layer 16B3a and on the second capacitive electrode 16B3.

[0093] The capacitor insulating layer 16B2 in the region on the relay layer 16B3a that will become the connection portion 19 is removed by etching. By etching the capacitor insulating layer 16B2 in the connection portion 19, the upper side of the underlying relay layer 16B3a is also removed, exposing a part of the relay layer 16B3a.

[0094] 17 and 18, the connection portion 19 of the relay layer 16B3a and the capacitor element 16B are completed. Specifically, a metal nitride film such as TiN that will become the first capacitor electrode 16B1 is formed to cover the capacitor insulating layer 16B2, the insulating layer 16B2a, the exposed relay layer 16B3a, and the seventh interlayer insulating layer 12g. Thereafter, as shown in FIG. 7, the first capacitor electrode 16B1 is patterned so that the first capacitor electrode 16B1 remains in the region connecting the main body 21a and protrusion 21b of the second capacitor electrode 16B3 to the relay layer 16B3a in a plan view.

[0095] As a result, the first capacitor electrode 16B1 and the relay layer 16B3a are electrically connected at the connection portion 19. The first capacitor electrode 16B1, the capacitor insulating layer 16B2, and the second capacitor electrode 16B3 are stacked to complete the capacitor element 16B.

[0096] In this way, the relay layer 16B3a and the first capacitor electrode 16B1 are electrically connected in the region exposed from the insulating layer 16B2a, i.e., the connection portion 19, so that, for example, after forming the capacitor element 16B, there is no need to form a contact hole in a separate process to electrically connect the relay layer 16B3a and the capacitor electrode 16B1, thereby reducing the number of manufacturing processes.

[0097] Next, the configuration of a projector 1000 as an electronic device to which the liquid crystal device 100 is applied will be described with reference to FIG.

[0098] 19, the projector 1000 includes a polarized illumination device 1100 arranged along a system optical axis L, and two dichroic mirrors 1104 and 1105 as light separation elements. The projector also includes three reflecting mirrors 1106, 1107, and 1108, and five relay lenses 1201, 1202, 1203, 1204, and 1205. The projector also includes three transmissive liquid crystal light valves 1210, 1220, and 1230 as light modulation devices, a cross dichroic prism 1206 as a light combining element, and a projection lens 1207.

[0099] Polarized illumination device 1100 comprises lamp unit 1101 as a light source, which is a white light source such as an extra-high pressure mercury lamp or a halogen lamp, integrator lens 1102 , and polarization conversion element 1103 .

[0100] Dichroic mirror 1104 reflects red light (R) and transmits green light (G) and blue light (B) out of the polarized light beam emitted from polarized lighting device 1100. Another dichroic mirror 1105 reflects green light (G) that has passed through dichroic mirror 1104 and transmits blue light (B).

[0101] Red light (R) reflected by dichroic mirror 1104 is reflected by reflecting mirror 1106 and then passes through relay lens 1205 before entering liquid crystal light valve 1210. Green light (G) reflected by dichroic mirror 1105 passes through relay lens 1204 before entering liquid crystal light valve 1220. Blue light (B) transmitted through dichroic mirror 1105 passes through a light guide system consisting of three relay lenses 1201, 1202, and 1203 and two reflecting mirrors 1107 and 1108 before entering liquid crystal light valve 1230.

[0102] Liquid crystal light valves 1210, 1220, and 1230 are arranged opposite the entrance surfaces of cross dichroic prism 1206 for the respective color lights. The color lights incident on liquid crystal light valves 1210, 1220, and 1230 are modulated based on video information (video signals) and emitted toward cross dichroic prism 1206. This prism is made up of four right-angle prisms bonded together, and a dielectric multilayer film that reflects red light and a dielectric multilayer film that reflects blue light are formed on the inner surface in a cross shape. These dielectric multilayer films combine the three color lights to generate light that represents a color image. The combined light is projected onto screen 1300 by projection lens 1207, which is a projection optical system, and the image is enlarged and displayed.

[0103] The liquid crystal light valve 1210 is an application of the liquid crystal device 100 of the above embodiment. A pair of polarizing elements arranged in a crossed Nicol configuration are arranged with a gap between them on the incident side and the exit side of the colored light of the liquid crystal device 100. The other liquid crystal light valves 1220 and 1230 are similar.

[0104] In the above embodiment, a transmissive liquid crystal device 100 is exemplified as an electro-optical device, but the liquid crystal device 100 may be a reflective liquid crystal device or an LCOS (Liquid Crystal on Silicon) liquid crystal device.

[0105] Furthermore, the liquid crystal device 100 has been described as an example of an electro-optical device, but the present invention is not limited to this and may be applied to, for example, an organic EL (electro luminescence) device, an electrophoretic display panel using microcapsules, or the like.

[0106] The electronic device is not limited to the exemplified three-panel projector 1000. For example, it may be a single-panel, two-panel, or projector 1000 equipped with four or more liquid crystal devices 100. The electronic device may also be a PDA (Personal Digital Assistant), digital still camera, television, video camera, car navigation device, in-vehicle display, electronic organizer, electronic paper, calculator, word processor, workstation, videophone, POS (Point of Sale), printer, scanner, copier, video player, device equipped with a touch panel, or the like.

[0107] As described above, the liquid crystal device 100 of this embodiment comprises a pixel electrode 27, a TFT 30 provided corresponding to the pixel electrode 27, a capacitance element 16B having a first capacitance electrode 16B1 electrically connected to the pixel electrode 27, a capacitance insulating layer 16B2, and a second capacitance electrode 16B3 provided via the first capacitance electrode 16B1 and the capacitance insulating layer 16B2, and a relay layer 16B3a electrically connected to the pixel electrode 27 and the TFT 30 and provided in the same layer as the second capacitance electrode 16B3, and the first capacitance electrode 16B1 extends to a position overlapping with the relay layer 16B3a in a planar view and is electrically connected to the relay layer 16B3a.

[0108] According to this configuration, the first capacitance electrode 16B1 extends to a position where it overlaps with the relay layer 16B3a, and the relay layer 16B3a and the first capacitance electrode 16B1 are electrically connected. Therefore, the first capacitance electrode 16B1 to which the potential of the pixel electrode 27 is applied can be electrically connected to the relay layer 16B3a without using a separate contact hole to electrically connect the relay layer 16B3a and the first capacitance electrode 16B1.

[0109] Furthermore, the liquid crystal device 100 of this embodiment preferably includes an insulating layer 16B2a provided in the same layer as the capacitive insulating layer 16B2 so as to cover the relay layer 16B3a, and the relay layer 16B3a is electrically connected to the first capacitive electrode 16B1 in a region exposed from the insulating layer 16B2a. With this configuration, the relay layer 16B3a and the first capacitive electrode 16B1 are electrically connected in a region exposed from the insulating layer 16B2a, so that the first capacitive electrode 16B1 to which the potential of the pixel electrode 27 is applied can be electrically connected to the relay layer 16B3a without using a separate contact hole.

[0110] Furthermore, in the liquid crystal device 100 of this embodiment, the second capacitor electrode 16B3 preferably has a main body 21a and a protrusion 21b protruding from the main body 21a along the first direction, and the relay layer 16B3a is provided separately from the protrusion 21b and extends along the first direction. With this configuration, since the relay layer 16B3a is provided separately from the protrusion 21b, the potential of the relay layer 16B3a and the potential of the protrusion 21b can be formed separately. The relay layer 16B3a is at a potential connected to, for example, the pixel electrode 27. The potential of the protrusion 21b is at the potential of, for example, the capacitor line 3b.

[0111] Furthermore, the liquid crystal device 100 of this embodiment preferably has a contact hole CNT17h for electrically connecting the relay layer 16B3a and the TFT 30, and the contact hole CNT17h, the region of the relay layer 16B3a exposed from the insulating layer 16B2a, and the protrusion 21b of the second capacitor electrode 16B3 are arranged along the first direction. With this configuration, the contact hole CNT17h, the exposed region, and the protrusion 21b are arranged along the first direction, so that, for example, by arranging them so as to overlap with the scanning line 3a, a decrease in the aperture ratio can be suppressed.

[0112] In the liquid crystal device 100 of this embodiment, the first capacitor electrode 16B1 is preferably provided so as to cover the side surfaces of the second capacitor electrode 16B3 with the capacitor insulating layer 16B2 interposed therebetween. With this configuration, the first capacitor electrode 16B1 is provided so as to cover the side surfaces of the capacitor insulating layer 16B2 and the second capacitor electrode 16B3, which makes it possible to increase the area in which the capacitor element 16B is formed, thereby improving the capacitance of the capacitor element 16B.

[0113] The liquid crystal device 100 of this embodiment preferably further includes a capacitance line 3b electrically connected to the second capacitance electrode 16B3, a relay layer 3c provided in the same layer as the capacitance line 3b and electrically connected to the relay layer 16B3a and the TFT 30, and a seventh interlayer insulating layer 12g provided to cover the capacitance line 3b and the relay layer 3c, having a trench portion 17i at a position overlapping the second capacitance electrode 16B3 in a plan view, and having a contact hole CNT17h for electrically connecting the relay layer 16B3a and the relay layer 3c. This configuration makes it possible to provide a liquid crystal device 100 having a structure including the capacitance line 3b, the relay layer 3c, and the seventh interlayer insulating layer 12g in addition to the capacitance element 16B.

[0114] Furthermore, the projector 1000 of this embodiment includes the above-described liquid crystal device 100. With this configuration, since the projector 1000 includes the above-described liquid crystal device 100, it is possible to provide a projector 1000 that can reduce costs.

[0115] Modifications of the above-described embodiment will now be described.

[0116] 8 described above, the first capacitor electrode 16B1 and the relay layer 16B3a do not necessarily have to have the same width at the connection portion 19, but may have a configuration as shown in FIG. 20. In the connection portion 19 of the modified example shown in FIG. 20, the width of the exposed relay layer 16B3a in the Y direction (the second direction) is narrower than the width of the first capacitor electrode 16B1 in the Y direction. Furthermore, the first capacitor electrode 16B1 is provided so as to cover the side surface of the relay layer 16B3a.

[0117] As described above, in the liquid crystal device 100 of this modified example, the region of the relay layer 16B3a that is exposed from the insulating layer 16B2a is preferably narrower in the second direction intersecting the first direction than the first capacitance electrode 16B1, and the first capacitance electrode 16B1 is preferably provided so as to cover the side surface of the relay layer 16B3a. With this configuration, the first capacitance electrode 16B1 is provided so as to cover the side surface of the relay layer 16B3a, which increases the contact area between the relay layer 16B3a and the first capacitance electrode 16B1 and improves the conductivity between the relay layer 16B3a and the first capacitance electrode 16B1. [Explanation of symbols]

[0118] 3a...scanning line, 3b...capacitance line, 3c...relay layer as second relay layer, 6a...data line, 6b...relay layer, 10...element substrate, 11a, 11b...base material, 12a...first interlayer insulating layer, 12b...second interlayer insulating layer, 12c...third interlayer insulating layer, 12d...fourth interlayer insulating layer, 12e...fifth interlayer insulating layer, 12f...sixth interlayer insulating layer, 12g...seventh interlayer insulating layer, 12h...eighth interlayer insulating layer, 12i...ninth interlayer insulating layer, 13a...first shield layer, 13b...second shield layer , 14...sealing material, 15...liquid crystal layer, 16, 16A, 16B...capacitive element, 16A2, 16B2...capacitive insulating layer, 16A1, 16B1...first capacitive electrode, 16A3, 16B3...second capacitive electrode, 16B3a...relay layer as first relay layer, 16B2a...insulating layer, 16d...first source / drain electrode, 16s...second source / drain electrode, 17i...trench portion as groove, 18...light-shielding portion, 19...connecting portion, 20...opposite substrate, 21a...main body portion, 21b...protruding portion , 22...data line driving circuit, 24...scanning line driving circuit, 25...inspection circuit, 26...vertical conductive portion, 27...pixel electrode, 28, 32...alignment film, 30...TFT as transistor, 30a...semiconductor layer, 30b...gate insulating layer, 30c...channel region, 30d...first source / drain region, 30g...gate electrode, 30s...second source / drain region, 31...common electrode, 40...sealing material, 41...external connection terminal, 100...liquid crystal device, 1000...projector 1100...polarized lighting device, 1101...lamp unit, 1102...integrator lens, 1103...polarized light conversion element, 1104, 1105...dichroic mirror, 1106, 1107, 1108...reflection mirror, 1201, 1202, 1203, 1204, 1205...relay lens, 1206...cross dichroic prism, 1207...projection lens, 1210, 1220, 1230...liquid crystal light valve, 1300...screen

Claims

1. A pixel electrode; a transistor provided corresponding to the pixel electrode; a capacitance element including a first capacitance electrode electrically connected to the pixel electrode, a capacitance insulating layer, and a second capacitance electrode provided between the first capacitance electrode and the capacitance insulating layer; a first relay layer electrically connected to the pixel electrode and the transistor and provided in the same layer as the second capacitance electrode; The electro-optical device, wherein the first capacitance electrode extends to a position overlapping the first relay layer in a plan view and is electrically connected to the first relay layer.

2. 2. The electro-optical device according to claim 1, an insulating layer provided in the same layer as the capacitance insulating layer so as to cover the first relay layer; The electro-optical device, wherein the first relay layer is electrically connected to the first capacitor electrode in a region exposed from the insulating layer.

3. 2. The electro-optical device according to claim 1, the second capacitance electrode has a main body portion and a protrusion portion protruding from the main body portion along a first direction, The electro-optical device, wherein the first relay layer is provided apart from the protruding portion and extends along the first direction.

4. 4. The electro-optical device according to claim 3, a region of the first relay layer that is exposed from the insulating layer has a width in a second direction intersecting with the first direction that is narrower than a width of the first capacitance electrode; The electro-optical device, wherein the first capacitance electrode is provided so as to cover a side surface of the first relay layer.

5. 4. The electro-optical device according to claim 3, a contact hole for electrically connecting the first relay layer and the transistor; The contact hole, the region of the first relay layer that is exposed from the insulating layer, and the protruding portion of the second capacitor electrode are provided along the first direction.

6. 2. The electro-optical device according to claim 1, The electro-optical device, wherein the first capacitor electrode is provided so as to cover a side surface of the second capacitor electrode via the capacitor insulating layer.

7. 2. The electro-optical device according to claim 1, a capacitance line electrically connected to the second capacitance electrode; a second relay layer provided in the same layer as the capacitance line and electrically connected to the first relay layer and the transistor; an interlayer insulating layer provided to cover the capacitance line and the second relay layer, the interlayer insulating layer having a groove at a position overlapping the second capacitance electrode in a plan view, and a contact hole for electrically connecting the first relay layer and the second relay layer; An electro-optical device comprising:

8. An electronic device comprising the electro-optical device according to claim 1 .

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