Array substrate capable of keeping costs of wrong wiring low, display panel, and manufacturing method of array substrate

Abstract

To provide an array substrate, a display panel, and a manufacturing method of the array substrate which keep costs of wrong wiring low.SOLUTION: An array substrate 30 includes: a plurality of first wires 51 which extend along an outer peripheral edge part of a display region AA in a non-display region NAA and which are provided in the extension direction while having a first gap 51G in between; and a plurality of second wires 55 which are arranged at positions superimposed on end parts 51A of the first wires 51 in planer view and which are provided with a second gap 55G in between. Each of the second wires 55 has a smaller plane size compared to each of the first wires 51, and is connected to each of the first wires 51 in an interlaminar manner. The second gap 55G is smaller than the first gap 51G.SELECTED DRAWING: Figure 4

Description

[Technical Field]

[0001] The present technology relates to an array substrate, a display panel, and a method for manufacturing an array substrate that can suppress wiring defects at low cost. [Background technology]

[0002] In the manufacture of display panels and the like, if ESD (electrostatic discharge) occurs in a photomask used in photolithography, the planar pattern of the photomask may be deformed. It is known that deformation of the photomask can cause wiring defects such as short circuits in the wiring formed using the photomask. Patent Document 1 discloses a technology for suppressing ESD that occurs in the photomask in order to prevent such a situation. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] Japanese Patent Publication No. 2020-16845

[0004] The photomask described in Patent Document 1 has a light-shielding portion formed from a light-shielding layer whose main component is chromium, and an antistatic layer containing chromium, which is formed at least in the light-transmitting region without the light-shielding portion. By forming the conductive antistatic layer in addition to the light-shielding portion, it is said that electrostatic damage to the photomask due to ESD can be prevented. Summary of the Invention [Problem to be solved by the invention]

[0005] However, the photomask described in Patent Document 1 increases costs due to the provision of an antistatic layer. Furthermore, when using this photomask for exposure, it is necessary to monitor the manufacturing process to prevent a decrease in exposure transmittance, which reduces work efficiency and increases work costs.

[0006] The technology described in this specification was developed based on the above-described circumstances, and aims to suppress wiring defects at low cost. [Means for solving the problem]

[0007] (1) An array substrate related to the technology described in the present specification is an array substrate having a display area and a non-display area surrounding the display area, and in the non-display area, the array substrate is provided with: a plurality of first wirings made of a first conductive film, the plurality of first wirings extending along the outer periphery of the display area and arranged at a first interval in the extension direction; and a plurality of second wirings made of a second conductive film arranged on the first conductive film via a first insulating film, the plurality of second wirings being provided at positions overlapping ends of the first wirings in a plan view and arranged at a second interval, each second wiring having a smaller planar size than each first wiring, and connected to each first wiring via a contact portion penetrating the insulating film, and the second interval is smaller than the first interval.

[0008] (2) In addition to the above (1), the array substrate may be configured such that the end of each of the second wirings on the second interval side has a protruding shape.

[0009] (3) In addition to the above (1) or (2), the array substrate may have an end portion of each of the first wirings that is non-protruding.

[0010] (4) In addition to any one of (1) to (3) above, the array substrate may have a plurality of TFTs arranged in a matrix in the display area, the gate electrode of each TFT being made of the first conductive film, and the source electrode of each TFT being made of the second conductive film.

[0011] (5) A display panel relating to the technology described in the present specification comprises an array substrate described in any one of (1) to (4) above, an opposing substrate arranged opposite the array substrate with an internal space between them, and a liquid crystal layer sealed in the internal space.

[0012] (6) A display panel relating to the technology described in this specification comprises an array substrate described in any one of (1) to (4) above, a light-emitting element arranged on the array substrate, and a sealing layer arranged to cover the light-emitting element.

[0013] (7) A manufacturing method of an array substrate according to the technology described in the present specification is a manufacturing method of an array substrate having a display area in which a plurality of TFTs are arranged in a matrix and a non-display area surrounding the display area, the method comprising: forming a first conductive film on an upper layer side of an insulating substrate; etching and patterning the formed first conductive film using a first photomask; forming a plurality of first wirings in the non-display area that extend along the outer periphery of the display area and are arranged at first intervals in the extension direction; forming an insulating film on the plurality of first wirings; and etching the formed insulating film using a second photomask. and forming contact holes in the insulating film; depositing a second conductive film on the patterned insulating film; and connecting the second conductive film to the plurality of first wirings by embedding the second conductive film in the contact holes; and etching and patterning the second conductive film connected to the plurality of first wirings using a third photomask, thereby forming a plurality of second wirings at positions overlapping ends of the first wirings in a plan view; the light-shielding portion of the third photomask has a planar size smaller than the light-shielding portion of the first photomask; and the plurality of second wirings are arranged at second intervals smaller than the first intervals.

[0014] (8) In addition to the above (7), the method for manufacturing the array substrate may be such that the end of each of the second wirings on the second interval side is formed to have a protruding shape.

[0015] (9) In addition to the above (7) or (8), the method for manufacturing the array substrate may further include forming the end of each of the first wirings so as to have a non-protruding shape.

[0016] (10) Furthermore, in addition to any one of (7) to (9) above, the method for manufacturing the array substrate may be such that the first conductive film is a gate metal film constituting the gate electrode of each of the TFTs, and the second conductive film is a source metal film constituting the source electrode of each of the TFTs. [Effects of the Invention]

[0017] According to the technology described in this specification, wiring defects can be suppressed at low cost. [Brief explanation of the drawings]

[0018] [Figure 1] 1 is a plan view of a liquid crystal panel according to a first embodiment; [Figure 2] Cross section of line II-II in Figure 1 [Figure 3] Circuit diagram showing pixel arrangement in the display area of ​​the array substrate [Figure 4] FIG. 2 is a plan view showing a layout pattern of a framed area IV in FIG. 1; [Figure 5] Cross section of line VV in Figure 4 [Figure 6A] 6A and 6B are diagrams showing a manufacturing process of the array substrate shown in FIG. 5; [Figure 6B] 6B is a diagram showing a manufacturing process of the array substrate subsequent to FIG. 6A. [Figure 6C] 6B shows a manufacturing process of the array substrate subsequent to FIG. 6B. [Figure 6D] 6D is a diagram showing the manufacturing process of the array substrate subsequent to FIG. 6C. [Figure 6E] 6D shows a manufacturing process of the array substrate. [Figure 6F] 6B is a diagram showing the manufacturing process of the array substrate subsequent to FIG. 6E. [Figure 6G] FIG. 6C is a diagram showing the manufacturing process of the array substrate subsequent to FIG. 6F. [Figure 6H] FIG. 6C is a diagram showing the manufacturing process of the array substrate subsequent to FIG. 6G. [Figure 6I] 6H shows the manufacturing process of the array substrate. [Figure 7] FIG. 1 is a plan view showing a layout pattern according to a first comparative example; [Figure 8]FIG. 10 is an exploded perspective view showing the configuration of an organic EL panel according to another embodiment. DETAILED DESCRIPTION OF THE INVENTION

[0019] <Embodiment 1> Embodiment 1 will be described with reference to FIGS. 1 to 6I. In this embodiment, a liquid crystal panel 10 (an example of a display panel) is illustrated, but the present invention is also applicable to other types of display panels (for example, an organic EL panel 110 shown in FIG. 8). Note that X-axis, Y-axis, and Z-axis are shown in some of the drawings, and the directions of these axes are drawn so as to be common to all the drawings. In addition, in each cross-sectional view, the upper side of the drawing is the front side, and the lower side of the drawing is the back side.

[0020] As shown in Fig. 1, the liquid crystal panel 10 is divided into a display area (active area) AA, which is capable of displaying an image and is located in the center, and a non-display area (non-active area) NAA, which is located on the outer periphery of the display area AA and has a frame-like (picture frame-like) shape in a plan view. In Fig. 1, the dashed-dotted line represents the outline of the display area AA, and the area outside the dashed-dotted line is the non-display area NAA. The planar shape of the liquid crystal panel 10 is not limited, but in this embodiment, it has an overall horizontally elongated rectangular shape, with the long side aligned with the X-axis, the short side aligned with the Y-axis, and the thickness aligned with the Z-axis in each drawing.

[0021] As shown in FIG. 2, the liquid crystal panel 10 is formed by bonding a pair of substrates 20 and 30 together. Between the pair of substrates 20 and 30, there are provided at least a liquid crystal layer 18 and a sealing portion 19 that seals the liquid crystal layer 18. The liquid crystal layer 18 contains liquid crystal molecules, which are a substance whose optical properties change when an electric field is applied. The sealing portion 19 has a rectangular frame shape in a plan view as a whole, and surrounds the liquid crystal layer 18 in the non-display area NAA. Polarizing plates 10C and 10D are attached to the outer surfaces of the pair of substrates 20 and 30, respectively.

[0022] Of the pair of substrates 20, 30, the one disposed on the front side (display surface side) is the counter substrate (color filter substrate) 20, and the one disposed on the back side is the array substrate (active matrix substrate, TFT substrate) 30. The counter substrate 20 and the array substrate 30 are both configured by laminating various films 20A, 30A on the inner surface (liquid crystal layer 18 side) of a glass substrate GS (an example of an insulating substrate) that is nearly transparent and has excellent light transmissivity. A backlight device that irradiates light onto the liquid crystal panel 10 is provided on the back side (array substrate 30 side) of the liquid crystal panel 10, thereby forming a liquid crystal display device.

[0023] 1, the array substrate 30 has a long side dimension that is approximately the same as that of the counter substrate 20, and a short side dimension that is longer than that of the counter substrate 20. Therefore, when the array substrate 30 and the counter substrate 20 are attached with the seal portion 19 so that one of the long sides is aligned, an exposed portion of the array substrate 30 is produced that does not overlap with the counter substrate 20. A driver 12 for driving the liquid crystal panel 10 is mounted on this non-overlapping portion by COG (Chip On Glass), and a flexible substrate 14 is connected to the non-overlapping portion. One end of the flexible substrate 14 is connected to the non-display area NAA of the liquid crystal panel 10, and the other end is connected to the control substrate, and various signals supplied from the control substrate are transmitted to the liquid crystal panel 10.

[0024] 3, a large number of source wirings (data lines, signal lines) 33 extending along the Y-axis direction and gate wirings (scanning lines) 34 extending along the X-axis direction perpendicular to the source wirings 33 are formed in a grid pattern in the display area AA of the array substrate 30. In each area surrounded by the source wirings 33 and the gate wirings 34, TFTs 37 (Thin Film Transistors) serving as switching elements and pixel electrodes 38 are formed. A large number of TFTs 37 and pixel electrodes 38 are arranged in a matrix pattern throughout the entire display area AA.

[0025] A common electrode to which a reference potential is supplied is provided in the display area AA of the array substrate 30. The common electrode may be provided on the counter substrate 20. When signals are input to the TFTs 37 from the source lines 33 and gate lines 34, the pixel electrodes 38 connected to the TFTs 37 are charged, causing a change in the potential difference between the pixel electrodes 38 and the common electrode. By controlling the electric field applied to the liquid crystal layer 18 using this potential difference, the orientation state of the liquid crystal molecules is appropriately switched, and the liquid crystal panel 10 is driven.

[0026] The source wiring 33 is connected to the driver 12 via lead-out wiring, and a data signal (image signal) is supplied to the source wiring 33 from a source drive circuit in the driver 12. The gate wiring 34 is connected to a GDM (Gate Driver Monolithic circuit) section monolithically formed in the non-display area NAA, and a scanning signal is supplied to the gate wiring 34 from the GDM section. The GDM section is connected to the flexible substrate 14 via lead-out wiring, and a signal is supplied from the control substrate through the flexible substrate 14.

[0027] As shown in Fig. 1, spare wiring 50 is formed in the non-display area NAA of the array substrate 30. The spare wiring 50 acts like a lightning rod, intentionally inducing ESD in the non-display area NAA to prevent ESD caused by static electricity or the like entering from outside the liquid crystal panel 10.

[0028] The auxiliary wiring 50 extends in the non-display area NAA along the outer periphery of the display area AA. The position of the auxiliary wiring 50 may be any position as long as it extends along the outer periphery of the display area AA, and there are no limitations on the positional relationship with other components provided in the non-display area NAA (for example, the GDM section described above, common electrode wiring for supplying a reference potential signal to the common electrode, and test wiring for performing an operation test of the liquid crystal panel).

[0029] Although the auxiliary wiring 50 according to the present embodiment has a rectangular frame shape that surrounds the entire outer periphery of the display area AA, it does not have to be formed along the entire periphery as long as it extends along the outer periphery of the display area AA. For example, the auxiliary wiring 50 may be U-shaped, surrounding three sides of the rectangular outer periphery of the display area AA, or L-shaped, surrounding two sides.

[0030] A plurality of auxiliary wirings 50 (four in this embodiment) are provided in the extension direction, spaced apart by a gap 50G (more specifically, a second gap 55G of a second auxiliary wiring 55, which will be described later). The area between the ends of the auxiliary wirings 50 that face each other across the gap 50G (more specifically, between the ends 55A of the second auxiliary wiring 55, which will be described later, on the second gap 55G side) is an ESD-inducing area. In this embodiment, four gaps 50G are formed, one near each corner of the rectangular display area AA, but they may be formed in areas other than the corners, and the number of gaps may be other than four.

[0031] The auxiliary wiring 50 includes first auxiliary wiring 51 (an example of a first wiring) and second auxiliary wiring 55 (an example of a second wiring). The first auxiliary wiring 51 occupies the majority of the auxiliary wiring 50 and extends along the outer periphery of the display area AA. As shown in FIGS. 4 and 5 , the first auxiliary wiring 51 is arranged at first intervals 51G in its extension direction, and the number of first auxiliary wiring 51 is the same as that of the auxiliary wiring 50 (four in this embodiment). The first intervals 51G are greater than the intervals 50G (more specifically, the second intervals 55G of the second auxiliary wiring 55). It is preferable that the ends 51A of the first auxiliary wiring 51 have a non-protruding shape so as not to act as discharge protrusions.

[0032] The second auxiliary wiring 55 is formed at a position overlapping the end 51A of the first auxiliary wiring 51 in a plan view. The planar size of the second auxiliary wiring 55 is sufficiently smaller than that of the first auxiliary wiring 51, and the second auxiliary wiring 55 is provided only near the end 51A of the first auxiliary wiring 51. More specifically, the second auxiliary wiring 55 is formed so as to extend from the end 51A of the first auxiliary wiring 51 in the extension direction of the first auxiliary wiring 51. The second auxiliary wiring 55 can also be said to be a multi-layered extension portion of the first auxiliary wiring 51.

[0033] The second auxiliary wires 55 according to this embodiment are formed on the end portions 51A of all the first auxiliary wires 51 (two for each of the four first auxiliary wires 51, a total of eight end portions 51A). The end portions 51A of the first auxiliary wires 51 are provided with second auxiliary wires 55, and the end portions (extending end portions) 55A of the second auxiliary wires 55 face each other with a second gap 55G therebetween.

[0034] Therefore, the second auxiliary wiring 55 is arranged at a second interval 55G that is smaller than the first interval 51G. The shape of the extending end 55A of the second auxiliary wiring 55 (the end on the second interval 55G side) is not limited, but it is preferably formed into a protruding shape so as to function as a discharge protrusion. The other end 55B of the second auxiliary wiring 55 is interlayer-connected to the end 51A of the first auxiliary wiring 51 by a contact portion 55B1 that penetrates the first insulating film 61, as shown in FIG.

[0035] Next, a manufacturing method of the array substrate 30 in the portion where the above-mentioned spare wiring 50 is disposed will be described with reference to FIGS. 6A to 6I. First, a gate metal film L1 (an example of a first conductive film) is formed on a glass substrate GS using a plasma CVD (chemical vapor deposition) method, a sputtering method, or the like (FIG. 6A). The gate metal film L1 becomes a layer that constitutes the first spare wiring 51, the gate wiring 34, and the gate electrode 37G of the TFT 37. The gate metal film L1 and a source metal film L5 (an example of a second conductive film) described later are made of a single layer film of a metal such as copper (Cu), an alloy, or a laminate film thereof.

[0036] Next, a first resist film L2 is applied onto the gate metal film L1. Known photoresist materials used in photolithography are appropriately used for the first resist film L2, as well as the second resist film L4 and third resist film L6 described below. The applied first resist film L2 is covered with a first photomask 91 and exposed using an exposure device (FIG. 6B). The first photomask 91, as well as the second photomask 92 and third photomask 93 described below, have a typical structure used in photolithography, such as a transparent substrate 91A, 92A, 93A on which light-shielding portions 91B, 92B, 93B made of a light-shielding material such as chromium are formed.

[0037] Next, the exposed first resist film L2 is developed to form a first resist pattern. Using the first resist pattern as a mask, the gate metal film L1 is etched to form the first preliminary wiring 51, and the resist pattern is then removed (FIG. 6C). After the first preliminary wiring 51 is formed, a gate insulating film L3 is formed on the upper side thereof (FIG. 6D). The gate insulating film L3 becomes a layer that constitutes the first insulating film 61 and the gate insulating film of the TFT 37 (an insulating film between the gate electrode 37G and the semiconductor film). The gate insulating film L3 and the second insulating film 62 and third insulating film 64, which will be described later, are made of a transparent inorganic insulating material, such as silicon oxide (SiOx), silicon oxynitride (SiON), silicon nitride (SiNx), or the like, which is a single layer or a laminate thereof.

[0038] Next, a second resist film L4 is applied on the gate insulating film L3. The applied second resist film L4 is covered with a second photomask 92 and exposed by an exposure device (FIG. 6E). The exposed second resist film L4 is developed to form a second resist pattern. Using the second resist pattern as a mask, the gate insulating film L3 is etched to form the first insulating film 61, and the second resist pattern is removed (FIG. 6F). The second photomask 92 has a light-transmitting portion 92B1 for forming a contact hole 61CH in the first insulating film 61.

[0039] After the first insulating film 61 is formed, a source metal film L5 is formed on the upper side thereof (FIG. 6G). The source metal film L5 becomes a layer that forms the second auxiliary wiring 55, the source wiring 33, and the source electrode 37S and drain electrode 37D of the TFT 37. Next, a third resist film L6 is applied onto the source metal film L5. The applied third resist film L6 is covered with a third photomask 93 and exposed using an exposure device (FIG. 6H). The exposed third resist film L6 is developed to form a third resist pattern. The source metal film L5 is etched using the third resist pattern as a mask to form the second auxiliary wiring 55, and the third resist pattern is removed (FIG. 6I). After the second auxiliary wiring 55 is formed, a second insulating film 62, a planarizing film 63, and a third insulating film 64 are sequentially formed by photolithography to form the array substrate 30 shown in FIG. 5. The planarization film 63 is made of a transparent organic insulating material such as acrylic resin (PMMA, etc.) or polyimide resin, and its thickness is greater than that of the other insulating films.

[0040] In a manufacturing process using photolithography, the light-shielding portion of the photomask may become charged, causing ESD. In particular, the first photomask 91 has a large planar size similar to the first auxiliary wiring 51, and therefore the amount of charge that accumulates is large. Therefore, when the auxiliary wiring 950 is formed in a single layer (formed only by the first auxiliary wiring 951 made of the gate metal film L1) as in Comparative Example 1 shown in FIG. 7 , ESD is likely to occur between the ends of the first photomask used for its formation. When ESD occurs, the planar pattern of the first photomask is deformed, and there is a concern that defects such as short circuits may occur in the wiring formed using the deformed first photomask.

[0041] Therefore, for example, if the first interval 951G of the first auxiliary wiring 951 is increased, ESD occurring in the first photomask 91 can be suppressed, but ESD also becomes less likely to occur in the first auxiliary wiring 951. As a result, the auxiliary wiring 950 made up of the first auxiliary wiring 951 cannot fulfill its original role as an ESD inducing portion.

[0042] In this regard, the spare wire 50 according to this embodiment has a two-layer structure of a first spare wire 51 and a second spare wire 55. More specifically, by forming the second spare wire 55 at the end 51A of the first spare wire 51, the extending end portions 55A of the second spare wire 55 are made to serve as ESD inducing locations. The interval (second interval 55G) between the extending end portions 55A of the second spare wire 55 is smaller than the first interval 51G of the first spare wire 51. Therefore, ESD is induced between the extending end portions 55A of the second spare wire 55.

[0043] Furthermore, the second auxiliary wiring 55 only needs to be provided at a position overlapping the end 51A of the first auxiliary wiring 51 in a plan view, and since its planar size is sufficiently smaller than that of the first auxiliary wiring 51, the planar size of the light-shielding portion 93B of the third photomask 93 used to form the second auxiliary wiring 55 in the manufacturing process is also sufficiently small. This reduces the amount of charge stored in the light-shielding portion 93B of the third photomask 93. As a result, unexpected ESD is prevented from occurring between the light-shielding portions 93B of the third photomask 92.

[0044] Therefore, the auxiliary wiring 50 according to this embodiment does not require an antistatic layer to be provided on the photomask as in the prior art, and wiring defects caused by ESD occurring on the photomask can be suppressed at low cost. In particular, by forming the second auxiliary wiring 55 from the same layer (source metal film L2) as the source wiring 33, etc., it is no longer necessary to add a new conductive film to the array substrate 30 to provide the second auxiliary wiring 55, and cost increases can be reliably suppressed.

[0045] The first gap 51G of the first auxiliary wiring 51 is set to a distance that does not cause ESD. The distance depends on the planar size of the first auxiliary wiring 51 (and thus the amount of charge stored in the first auxiliary wiring 51), but since the insulation distance in air is generally 1 kV / mm, it is preferable that the distance be, for example, 10 μm or more.

[0046] The second interval 55G of the second auxiliary wiring 55 is set to a distance effective for inducing ESD. This distance is set to the minimum value of the plane pattern interval patterned by, for example, photolithography (the minimum limit value defined by the exposure resolution of the resist film), for example, 5 μm or less.

[0047] <Other embodiments> The present invention is not limited to the embodiments and modifications described above with reference to the drawings, and the following embodiments, for example, are also included within the technical scope of the present invention.

[0048] (1) The stacking order of various thin films on the array substrate 30 is an example, and for example, the gate metal film L1 may be disposed above the source metal film L2 with an insulating film interposed therebetween. Also, the first auxiliary wiring 51 may be made of the source metal film L2, and the second auxiliary wiring 55 may be made of the gate metal film L2.

[0049] (2) The present technology can also be applied to other types of display panels, such as organic EL panels. As shown in Fig. 8, the organic EL panel 110 includes at least an array substrate 130, an organic light-emitting layer (light-emitting element) 118 formed on the array substrate 130, and a sealing layer 119 formed to cover the light-emitting element 118. [Explanation of symbols]

[0050] 10, 110...liquid crystal panel (display panel), 18...liquid crystal layer, 20...counter substrate, 30, 130...array substrate, 51...first auxiliary wiring (first wiring), 37...TFT, 37G...gate electrode, 37S...source electrode, 51A...end, 51G...first interval, 55...second auxiliary wiring (second wiring), 55A...end, 55B1...contact portion, 55G...second interval, 61...first insulating film, 61CH...contact hole, 91...first photomask, 91B...light-shielding portion, 92...second photomask, 93...third photomask, 93B...light-shielding portion, 118...light-emitting element, 119...sealing layer, AA...display area, GS...glass substrate (insulating substrate), L1...gate metal film (first conductive film), L2...source metal film (second conductive film), L3...gate insulating film (insulating film), NAA...non-display area

Claims

1. An array substrate having a display area and a non-display area surrounding the display area, In the non-display area, a plurality of first wirings made of a first conductive film, the first wirings extending along an outer periphery of the display area and arranged at first intervals in the extending direction; a plurality of second wirings made of a second conductive film disposed on the first conductive film with a first insulating film interposed therebetween, the second wirings being provided at positions overlapping ends of the first wirings in a plan view and being disposed at second intervals, the second wirings have a planar size smaller than that of the first wirings, and are connected to the first wirings via contact portions that penetrate the first insulating film; The second distance is smaller than the first distance.

2. The array substrate according to claim 1 , wherein an end of each of the second wirings on the second spacing side has a protrusion shape.

3. 3. The array substrate according to claim 1, wherein the end portions of the first wirings are non-protruding.

4. A plurality of TFTs are arranged in a matrix in the display area, 3. The array substrate according to claim 1, wherein a gate electrode of each of said TFTs is made of said first conductive film, and a source electrode of each of said TFTs is made of said second conductive film.

5. an array substrate according to claim 1 or 2; an opposing substrate disposed opposite the array substrate with an internal space therebetween; a liquid crystal layer sealed in the internal space.

6. an array substrate according to claim 1 or 2; a light-emitting element disposed on the array substrate; a sealing layer disposed so as to cover the light-emitting element.

7. 1. A method for manufacturing an array substrate having a display area in which a plurality of TFTs are arranged in a matrix and a non-display area surrounding the display area, comprising: A first conductive film is formed on an upper layer side of an insulating substrate; the formed first conductive film is etched and patterned using a first photomask to form a plurality of first wirings in the non-display area, the first wirings extending along an outer periphery of the display area and arranged at first intervals in the extending direction; forming a first insulating film on the plurality of first wirings; the formed first insulating film is etched and patterned through a second photomask, and contact holes are formed in the first insulating film; forming a second conductive film on the patterned first insulating film and burying the second conductive film in the contact holes to connect the second conductive film to the plurality of first wirings; the second conductive film connected to the plurality of first wirings is etched and patterned via a third photomask to form a plurality of second wirings at positions overlapping with ends of the first wirings in a plan view; the light-shielding portion of the third photomask has a planar size smaller than that of the light-shielding portion of the first photomask; The method for manufacturing an array substrate, wherein the plurality of second wirings are arranged at second intervals that are smaller than the first intervals.

8. The method for manufacturing an array substrate according to claim 7 , wherein an end portion of each of the second wirings on the second interval side is formed to have a protrusion shape.

9. 9. The method for manufacturing an array substrate according to claim 7, wherein the end portions of the first wirings are formed to have a non-protruding shape.

10. the first conductive film is a gate metal film that constitutes a gate electrode of each of the TFTs, 9. The method for manufacturing an array substrate according to claim 7, wherein the second conductive film is a source metal film that constitutes a source electrode of each of the TFTs.

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