Semiconductor device

Abstract

To provide a semiconductor device capable of miniaturization or high integration.SOLUTION: A semiconductor device includes a stack of a first interlayer film having a first opening part and a second interlayer film having a second opening part. In the first opening part, a part of a structure of two or more trench-type capacitors is provided. In the second opening part, a part of a structure of two or more vertical transistors is provided. The second opening part includes a region overlapping with the first opening part. An upper electrode of the first vertical transistor and an upper electrode of the second vertical transistor include a cutoff part at a position overlapping with the second opening part. In a plan view, the outline of the cutoff part coincides or substantially coincides with the outline of the second opening part.SELECTED DRAWING: Figure 2

Description

[Technical Field]

[0001] 1. Field of the Invention One embodiment of the present invention relates to a semiconductor device, a memory device, and an electronic device. Another embodiment of the present invention relates to a manufacturing method of a semiconductor device.

[0002] One embodiment of the present invention is not limited to the above technical field, and examples of the technical field of one embodiment of the present invention include a semiconductor device, a display device, a light-emitting device, a power storage device, a memory device, an electronic device, a lighting device, an input device (for example, a touch sensor), an input / output device (for example, a touch panel), a driving method thereof, or a manufacturing method thereof.

[0003] In this specification and the like, a semiconductor device is a device that utilizes semiconductor characteristics, and refers to a circuit including a semiconductor element (transistor, diode, photodiode, etc.), a device having such a circuit, etc. Also, it refers to any device that can function by utilizing semiconductor characteristics. For example, an integrated circuit, a chip including an integrated circuit, and an electronic component in which a chip is housed in a package are examples of semiconductor devices. Furthermore, memory devices, display devices, light-emitting devices, lighting devices, and electronic devices may themselves be semiconductor devices and each may have a semiconductor device. [Background technology]

[0004] In recent years, the development of semiconductor devices has progressed, and semiconductor devices mainly use LSIs (Large Scale Integration), CPUs (Central Processing Units), memories (storage devices), etc. A CPU is an aggregate of semiconductor elements that have integrated circuits (including transistors and memories) formed into chips by processing a semiconductor wafer and on which electrodes serving as connection terminals are formed.

[0005] 2. Description of the Related Art Integrated circuits (ICs) such as LSIs, CPUs, and memories are mounted on circuit boards, such as printed wiring boards, and are used as components of various electronic devices.

[0006] Furthermore, technology for constructing transistors using semiconductor thin films formed on substrates with insulating surfaces has attracted attention. Such transistors are widely used in electronic devices such as integrated circuits (ICs) and display devices. While silicon-based semiconductor materials are widely known as semiconductor materials applicable to transistors, oxide semiconductors have also attracted attention as other materials.

[0007] Furthermore, it is known that a transistor using an oxide semiconductor has an extremely small leakage current in an off state. For example, Patent Document 1 discloses a CPU or the like with low power consumption that utilizes the property of a transistor using an oxide semiconductor that the leakage current is small. Furthermore, for example, Patent Document 2 discloses a memory device or the like that can retain stored data for a long period of time by utilizing the property of a transistor using an oxide semiconductor that the leakage current is small.

[0008] In addition, with the recent trend toward smaller and lighter electronic devices, there is an increasing demand for higher density integrated circuits. There is also a demand for improved productivity of semiconductor devices including integrated circuits. For example, Patent Document 3 and Non-Patent Document 1 disclose a technique for increasing the density of integrated circuits by stacking a first transistor using an oxide semiconductor film and a second transistor using an oxide semiconductor film to provide multiple memory cells in an overlapping manner. Patent Document 4 also discloses a technique for increasing the density of integrated circuits by vertically arranging the channel of a transistor using an oxide semiconductor film. [Prior art documents] [Patent documents]

[0009] [Patent Document 1] Japanese Patent Application Laid-Open No. 2012-257187 [Patent Document 2] Japanese Patent Application Laid-Open No. 2011-151383 [Patent Document 3] International Publication No. 2021 / 053473 [Patent Document 4] Japanese Patent Application Laid-Open No. 2013-211537 [Non-patent literature]

[0010] [Non-Patent Document 1] M. Oota et al., “3D-Stacked CAAC-In-Ga-Zn Oxide FETs with Gate Length of 72nm”, IEDM Tech. Dig., 2019, pp.50-53 Summary of the Invention [Problem to be solved by the invention]

[0011] An object of one embodiment of the present invention is to provide a transistor, a semiconductor device, or a memory device that can be miniaturized or highly integrated.An object of one embodiment of the present invention is to provide a highly reliable transistor, a semiconductor device, or a memory device.An object of one embodiment of the present invention is to provide a semiconductor device or a memory device with low power consumption.An object of one embodiment of the present invention is to provide a semiconductor device or a memory device with high operation speed.An object of one embodiment of the present invention is to provide a semiconductor device or a memory device including a transistor with favorable electrical characteristics.An object of one embodiment of the present invention is to provide a semiconductor device or a memory device including a transistor with high on-state current.An object of one embodiment of the present invention is to provide a semiconductor device or a memory device including a transistor with low parasitic capacitance.An object of one embodiment of the present invention is to provide a manufacturing method of the transistor, the semiconductor device, or the memory device.

[0012] Note that the description of these problems does not preclude the existence of other problems. One embodiment of the present invention does not necessarily have to solve all of these problems. Problems other than these can be extracted from the description in the specification, drawings, and claims. [Means for solving the problem]

[0013] One embodiment of the present invention provides a semiconductor device including a first insulating layer, a second insulating layer, a first capacitor, a second capacitor, a first transistor, and a second transistor, wherein the first insulating layer has a first opening, the second insulating layer has a second opening, the second insulating layer is located on the first insulating layer, the second opening has a region overlapping with the first opening, and the first capacitor includes a first electrode provided along a sidewall of the first opening, a dielectric provided to cover the first electrode, and a dielectric disposed within the first opening. a second electrode having a region facing the first electrode with the dielectric sandwiched therebetween; a second capacitor having the first electrode, a dielectric, and a third electrode having a region facing the first electrode with the dielectric sandwiched therebetween in the first opening; the first transistor having a first oxide semiconductor layer; the second transistor having a second oxide semiconductor layer; and the first oxide semiconductor layer and the second oxide semiconductor layer each having a region provided along a sidewall of the second opening.

[0014] Alternatively, one embodiment of the present invention includes a first capacitor, a second capacitor, a first transistor, a second transistor, a first insulating layer, a second insulating layer, a third insulating layer, and a fourth insulating layer, the first capacitor includes a first conductive layer, a second conductive layer, and a fifth insulating layer, the second capacitor includes the first conductive layer, the third conductive layer, and a fifth insulating layer, the first transistor includes a first oxide semiconductor layer, a fourth conductive layer, a fifth conductive layer, a sixth conductive layer, and a sixth insulating layer, and the second transistor includes a second oxide semiconductor layer and , a fifth conductive layer, a seventh conductive layer, an eighth conductive layer, and a sixth insulating layer, wherein the first insulating layer has a first opening, the first conductive layer has a region located within the first opening, the fifth insulating layer is located on the first conductive layer, the second conductive layer and the third conductive layer each have a region facing the first conductive layer within the first opening with the fifth insulating layer sandwiched therebetween, the second insulating layer is located on the second conductive layer and the third conductive layer, the fourth conductive layer and the seventh conductive layer are located on the second insulating layer, and the fourth conductive layer is electrically connected to the second conductive layer. the seventh conductive layer is electrically connected to the third conductive layer; the third insulating layer is located on the fourth conductive layer and the seventh conductive layer; the fifth conductive layer is located on the third insulating layer; the fourth insulating layer is located on the third insulating layer and the fifth conductive layer; the sixth conductive layer and the eighth conductive layer are provided spaced apart from each other on the fourth insulating layer; the fourth insulating layer, the fifth conductive layer, and the third insulating layer have a second opening, and the second opening has a portion overlapping with the fourth conductive layer, a portion overlapping with the seventh conductive layer, and a second opening located between the fourth conductive layer and the seventh conductive layer. the sixth insulating layer covers a sidewall of the second opening; the first oxide semiconductor layer has a region facing the fifth conductive layer within the second opening with the sixth insulating layer therebetween, a region in contact with the fourth conductive layer within the second opening, and a region in contact with the sixth conductive layer outside the second opening; and the second oxide semiconductor layer has a region facing the fifth conductive layer within the second opening with the sixth insulating layer therebetween, a region in contact with the seventh conductive layer within the second opening, and a region in contact with the eighth conductive layer outside the second opening.

[0015] Alternatively, in the above aspect, the first conductive layer may have a region along the sidewall of the first opening.

[0016] Alternatively, in the above aspect, the semiconductor device may have a ninth conductive layer and a tenth conductive layer, the second insulating layer may have a third opening reaching the second conductive layer and a fourth opening reaching the third conductive layer, the ninth conductive layer may be located within the third opening, the tenth conductive layer may be located within the fourth opening, the fourth conductive layer may have a region in contact with an upper surface of the ninth conductive layer, and the seventh conductive layer may have a region in contact with an upper surface of the tenth conductive layer.

[0017] Alternatively, in the above aspect, the semiconductor device may have a seventh insulating layer, the second insulating layer may have a first recess at a position overlapping with the first opening, and the seventh insulating layer may be arranged to fill at least a portion of the first recess.

[0018] Alternatively, in the above aspect, the sixth insulating layer in the second opening may be circular in plan view, and the first oxide semiconductor layer and the second oxide semiconductor layer in the second opening may each be arc-shaped in plan view.

[0019] Alternatively, in the above aspect, the fourth conductive layer may have a second recess at a position overlapping with the second opening, the sixth insulating layer may be in contact with a sidewall of the second recess, and the first oxide semiconductor layer may be in contact with at least a portion of the bottom of the second recess.

[0020] Alternatively, in the above embodiment, the fourth conductive layer may have a first layer and a second layer on the first layer, and the second layer may have a second recess.

[0021] Alternatively, in the above embodiment, the sixth insulating layer may be in contact with a part of the side surface of the sixth conductive layer facing the second opening, and the first oxide semiconductor layer may be in contact with another part of the side surface of the sixth conductive layer facing the second opening.

[0022] Alternatively, in the above aspect, the sixth insulating layer may be in contact with a part of the side surface of the fourth conductive layer facing the second opening, and the first oxide semiconductor layer may be in contact with another part of the side surface of the fourth conductive layer facing the second opening.

[0023] Alternatively, in the above aspect, the end of the first oxide semiconductor layer outside the second opening may be located closer to the second opening than the end of the sixth conductive layer outside the second opening.

[0024] Alternatively, in the above aspect, the semiconductor device may have an eighth insulating layer and an eleventh conductive layer, the eighth insulating layer being located on the first oxide semiconductor layer and the second oxide semiconductor layer, and the eleventh conductive layer having, in the second opening, a region facing the fifth conductive layer with the eighth insulating layer, the first oxide semiconductor layer, and the sixth insulating layer sandwiched therebetween, and a region facing the fifth conductive layer with the eighth insulating layer, the second oxide semiconductor layer, and the sixth insulating layer sandwiched therebetween.

[0025] Alternatively, in the above aspect, the height of the bottom surface of the portion of the 11th conductive layer located between the fourth conductive layer and the seventh conductive layer may be lower than the height of the top surface of the portion of the fourth conductive layer that does not overlap with the second opening.

[0026] Alternatively, in the above aspect, the semiconductor device may have a ninth insulating layer and a twelfth conductive layer, the ninth insulating layer being located on the eighth insulating layer and having a fifth opening at a position overlapping with the second opening, and the twelfth conductive layer being provided on the ninth insulating layer and having a region in contact with the eleventh conductive layer. [Effects of the Invention]

[0027] One embodiment of the present invention can provide a transistor, a semiconductor device, or a memory device that can be miniaturized or highly integrated. One embodiment of the present invention can provide a highly reliable transistor, a semiconductor device, or a memory device. One embodiment of the present invention can provide a semiconductor device or a memory device with low power consumption. One embodiment of the present invention can provide a semiconductor device or a memory device with high operating speed. One embodiment of the present invention can provide a semiconductor device or a memory device including a transistor with favorable electrical characteristics. One embodiment of the present invention can provide a semiconductor device or a memory device including a transistor with high on-state current. One embodiment of the present invention can provide a semiconductor device or a memory device including a transistor with low parasitic capacitance. One embodiment of the present invention can provide a manufacturing method of the above transistor, semiconductor device, or memory device.

[0028] Note that the description of these effects does not preclude the existence of other effects. One embodiment of the present invention does not necessarily have all of these effects. Effects other than these can be extracted from the description in the specification, drawings, and claims. [Brief explanation of the drawings]

[0029] [Figure 1] 1A to 1D are plan views showing an example of a semiconductor device. [Figure 2] Figures 2(A) and 2(B) are cross-sectional views showing an example of a semiconductor device. Figure 2(C) is a schematic perspective view showing an example of a semiconductor device. Figure 2(D) is a plan view showing an example of a semiconductor device. Figure 2(E) is a circuit diagram showing an example of a memory cell. [Figure 3] Fig. 3(A) is a cross-sectional view showing an example of a semiconductor device, and Fig. 3(B) is a plan view showing an example of a semiconductor device. [Figure 4] 4A and 4B are cross-sectional views showing an example of a semiconductor device. [Figure 5] 5(A) and 5(B) are cross-sectional views showing an example of a semiconductor device. [Figure 6] 6A and 6B are cross-sectional views showing an example of a semiconductor device. [Figure 7] 7A and 7B are cross-sectional views showing an example of a semiconductor device. [Figure 8] FIG. 8 is a cross-sectional view showing an example of a semiconductor device. [Figure 9] 9(A) and 9(B) are cross-sectional views showing an example of a semiconductor device. [Figure 10] 10(A) and 10(B) are cross-sectional views showing an example of a semiconductor device. [Figure 11] 11(A) and 11(B) are cross-sectional views showing an example of a semiconductor device. [Figure 12] 12A and 12B are cross-sectional views showing an example of a semiconductor device. [Figure 13] 13A and 13B are cross-sectional views showing an example of a semiconductor device. [Figure 14] 14(A) and 14(B) are cross-sectional views showing an example of a semiconductor device. [Figure 15] Fig. 15(A) is a cross-sectional view showing an example of a semiconductor device, and Fig. 15(B) and Fig. 15(C) are plan views showing an example of a semiconductor device. [Figure 16] Fig. 16(A) is a plan view showing an example of a semiconductor device, and Fig. 16(B) and Fig. 16(C) are cross-sectional views showing an example of the semiconductor device. [Figure 17] Fig. 17(A) is a plan view showing an example of a semiconductor device, and Fig. 17(B) and Fig. 17(C) are cross-sectional views showing an example of the semiconductor device. [Figure 18] Figures 18(A) and 18(D) are plan views showing an example of a semiconductor device, and Figures 18(B) and 18(C) are cross-sectional views showing an example of a semiconductor device. [Figure 19] Figures 19(A) and 19(D) are plan views showing an example of a semiconductor device, and Figures 19(B) and 19(C) are cross-sectional views showing an example of a semiconductor device. [Figure 20] Fig. 20A is a plan view illustrating an example of a method for manufacturing a semiconductor device, and Fig. 20B and Fig. 20C are cross-sectional views illustrating an example of a method for manufacturing a semiconductor device. [Figure 21] Fig. 21A is a plan view illustrating an example of a method for manufacturing a semiconductor device, and Fig. 21B and Fig. 21C are cross-sectional views illustrating an example of a method for manufacturing a semiconductor device. [Figure 22] Fig. 22A is a plan view illustrating an example of a method for manufacturing a semiconductor device, and Fig. 22B and Fig. 22C are cross-sectional views illustrating an example of a method for manufacturing a semiconductor device. [Figure 23] Fig. 23A is a plan view illustrating an example of a method for manufacturing a semiconductor device, and Fig. 23B and Fig. 23C are cross-sectional views illustrating an example of a method for manufacturing a semiconductor device. [Figure 24] Fig. 24A is a plan view illustrating an example of a method for manufacturing a semiconductor device, and Fig. 24B and Fig. 24C are cross-sectional views illustrating an example of a method for manufacturing a semiconductor device. [Figure 25] Fig. 25A is a plan view illustrating an example of a method for manufacturing a semiconductor device, and Fig. 25B and Fig. 25C are cross-sectional views illustrating an example of a method for manufacturing a semiconductor device. [Figure 26] Fig. 26A is a plan view illustrating an example of a method for manufacturing a semiconductor device, and Fig. 26B and Fig. 26C are cross-sectional views illustrating an example of a method for manufacturing a semiconductor device. [Figure 27] Fig. 27A is a plan view illustrating an example of a method for manufacturing a semiconductor device, and Fig. 27B and Fig. 27C are cross-sectional views illustrating an example of a method for manufacturing a semiconductor device. [Figure 28] Fig. 28A is a plan view illustrating an example of a method for manufacturing a semiconductor device, and Fig. 28B and Fig. 28C are cross-sectional views illustrating an example of a method for manufacturing a semiconductor device. [Figure 29] Fig. 29A is a plan view illustrating an example of a method for manufacturing a semiconductor device, and Fig. 29B and Fig. 29C are cross-sectional views illustrating an example of a method for manufacturing a semiconductor device. [Figure 30] Fig. 30A is a plan view illustrating an example of a method for manufacturing a semiconductor device, and Fig. 30B and Fig. 30C are cross-sectional views illustrating an example of a method for manufacturing a semiconductor device. [Figure 31]Fig. 31A is a plan view illustrating an example of a method for manufacturing a semiconductor device, and Fig. 31B and Fig. 31C are cross-sectional views illustrating an example of a method for manufacturing a semiconductor device. [Figure 32] Fig. 32A is a plan view illustrating an example of a method for manufacturing a semiconductor device, and Fig. 32B and Fig. 32C are cross-sectional views illustrating an example of a method for manufacturing a semiconductor device. [Figure 33] Fig. 33A is a plan view illustrating an example of a method for manufacturing a semiconductor device, and Fig. 33B and Fig. 33C are cross-sectional views illustrating an example of a method for manufacturing a semiconductor device. [Figure 34] Fig. 34A is a plan view illustrating an example of a method for manufacturing a semiconductor device, and Fig. 34B and Fig. 34C are cross-sectional views illustrating an example of a method for manufacturing a semiconductor device. [Figure 35] Fig. 35A is a plan view illustrating an example of a method for manufacturing a semiconductor device, and Fig. 35B and Fig. 35C are cross-sectional views illustrating an example of a method for manufacturing a semiconductor device. [Figure 36] Fig. 36A is a plan view illustrating an example of a method for manufacturing a semiconductor device, and Fig. 36B and Fig. 36C are cross-sectional views illustrating an example of a method for manufacturing a semiconductor device. [Figure 37] Fig. 37A is a plan view illustrating an example of a method for manufacturing a semiconductor device, and Fig. 37B and Fig. 37C are cross-sectional views illustrating an example of a method for manufacturing a semiconductor device. [Figure 38] Fig. 38A is a plan view illustrating an example of a method for manufacturing a semiconductor device, and Fig. 38B and Fig. 38C are cross-sectional views illustrating an example of a method for manufacturing a semiconductor device. [Figure 39] Fig. 39A is a plan view illustrating an example of a method for manufacturing a semiconductor device, and Fig. 39B and Fig. 39C are cross-sectional views illustrating an example of a method for manufacturing a semiconductor device. [Figure 40] Fig. 40A is a plan view illustrating an example of a method for manufacturing a semiconductor device, and Fig. 40B and Fig. 40C are cross-sectional views illustrating an example of a method for manufacturing a semiconductor device. [Figure 41]Fig. 41A is a plan view illustrating an example of a method for manufacturing a semiconductor device, and Fig. 41B and Fig. 41C are cross-sectional views illustrating an example of a method for manufacturing a semiconductor device. [Figure 42] FIG. 42 is a band diagram of an oxide semiconductor layer. [Figure 43] 43(A) and 43(B) are plan views showing an example of a semiconductor device. [Figure 44] 44(A) and 44(B) are plan views showing an example of a semiconductor device. [Figure 45] FIG. 45 is a cross-sectional view showing an example of a semiconductor device. [Figure 46] FIG. 46 is a cross-sectional view showing an example of a semiconductor device. [Figure 47] FIG. 47 is a block diagram showing an example of a semiconductor device. [Figure 48] 48(A) to 48(D) are circuit diagrams showing examples of memory cells. [Figure 49] 49(A) and 49(B) are schematic perspective views showing an example of a semiconductor device. [Figure 50] FIG. 50 is a block diagram illustrating the CPU. [Figure 51] 51(A) and 51(B) are schematic perspective views showing an example of a semiconductor device. [Figure 52] 52(A) and 52(B) are schematic perspective views showing an example of a semiconductor device. [Figure 53] FIG. 53 is a conceptual diagram illustrating the hierarchy of a storage device. [Figure 54] Figures 54(A) and 54(B) are circuit diagrams showing an example of a semiconductor device, and Figure 54(C) is a diagram showing an example of an electronic component using the semiconductor device. [Figure 55] FIG. 55 is a diagram illustrating an example of an electronic component. [Figure 56] Figures 56(A) to 56(C) are diagrams showing an example of a mainframe computer. Figure 56(D) is a diagram showing an example of space equipment. Figure 56(E) is a diagram showing an example of a storage system applicable to a data center. [Figure 57] 57(A) to 57(F) are diagrams showing examples of electronic devices. [Figure 58] 58(A) to 58(G) are diagrams showing examples of electronic devices. [Figure 59] 59(A) to 59(F) are diagrams showing examples of electronic devices. DETAILED DESCRIPTION OF THE INVENTION

[0030] The embodiments will be described in detail with reference to the drawings. However, the present invention is not limited to the following description, and it will be readily understood by those skilled in the art that various changes can be made in form and detail without departing from the spirit and scope of the present invention. Therefore, the present invention should not be interpreted as being limited to the description of the embodiments shown below.

[0031] In the configuration of the invention described below, the same parts or parts having similar functions are denoted by the same reference numerals in different drawings, and repeated explanations thereof will be omitted. Furthermore, when referring to similar functions, the same hatching pattern may be used and no particular reference numeral may be assigned.

[0032] Furthermore, for ease of understanding, the position, size, range, etc. of each component shown in the drawings may not represent the actual position, size, range, etc. Therefore, the disclosed invention is not necessarily limited to the position, size, range, etc. disclosed in the drawings.

[0033] In this specification, the ordinal numbers "first" and "second" are used for convenience and do not limit the number of components or the order of the components (for example, the order of processes or stacking). Furthermore, the ordinal numbers attached to components in one part of this specification may not match the ordinal numbers attached to the same components in other parts of this specification or in the claims.

[0034] A transistor is a type of semiconductor element that can perform functions such as amplifying current or voltage and performing a switching operation to control conduction or non-conduction. The term "transistor" as used herein includes an IGFET (Insulated Gate Field Effect Transistor) and a TFT (Thin Film Transistor).

[0035] In this specification and the like, a transistor using an oxide semiconductor or a metal oxide for a semiconductor layer and a transistor having an oxide semiconductor or a metal oxide for a channel formation region may be referred to as an OS (oxide semiconductor) transistor. A transistor having silicon for a channel formation region may be referred to as a Si transistor.

[0036] In this specification and the like, a transistor is an element having at least three terminals including a gate, a drain, and a source. A region (also referred to as a channel formation region) where a channel is formed between the drain (drain terminal, drain region, or drain electrode) and the source (source terminal, source region, or source electrode) is provided, and a current can flow between the source and the drain through the channel formation region. Note that in this specification and the like, the channel formation region refers to a region through which a current mainly flows.

[0037] Furthermore, the functions of "source" and "drain" may be interchanged when transistors of different polarities are used, or when the direction of current flow changes during circuit operation, etc. Therefore, in this specification, the terms "source" and "drain" may be used interchangeably.

[0038] Note that impurities in a semiconductor refer to, for example, elements other than the main components constituting the semiconductor. For example, an element with a concentration of less than 0.1 atomic % can be considered an impurity. The presence of impurities may, for example, increase the density of defect states in the semiconductor or reduce the crystallinity. When the semiconductor is an oxide semiconductor, impurities that change the characteristics of the semiconductor include, for example, Group 1 elements, Group 2 elements, Group 13 elements, Group 14 elements, Group 15 elements, and transition metals other than the main components of the oxide semiconductor. Specific examples include hydrogen, lithium, sodium, silicon, boron, phosphorus, carbon, and nitrogen. Note that water may also function as an impurity. For example, the inclusion of impurities may cause oxygen deficiency (V) in the oxide semiconductor. O (also referred to as "interstitial space") may be formed.

[0039] In this specification and the like, an oxynitride refers to a material having a composition in which oxygen is contained in a larger amount than nitrogen, and a nitride oxide refers to a material having a composition in which nitrogen is contained in a larger amount than oxygen.

[0040] To analyze the content of elements such as hydrogen, oxygen, carbon, or nitrogen contained in a film, for example, secondary ion mass spectrometry (SIMS) or X-ray photoelectron spectroscopy (XPS) or electron spectroscopy for chemical analysis (ESCA) can be used. XPS is suitable when the content of the target element is high (e.g., 0.5 atomic % or more, or 1 atomic % or more). On the other hand, SIMS is suitable when the content of the target element is low (e.g., less than 0.5 atomic % or less than 1 atomic %). When comparing the content of elements, it is more preferable to perform a combined analysis using both SIMS and XPS analytical techniques.

[0041] In this specification and the like, the term "content" refers to the proportion of a component contained in a film. For example, if an oxide semiconductor layer contains metal elements X, Y, and Z, and the number of atoms of each of the metal elements X, Y, and Z contained in the oxide semiconductor layer is A, then the number of atoms of each of the metal elements X, Y, and Z contained in the oxide semiconductor layer is A. X , A Y , A Z When the content of metal element X is X / (A X +A Y +A Z ) In addition, the ratio of the number of atoms of the metal element X, the metal element Y, and the metal element Z in the oxide semiconductor layer (atomic ratio) can be expressed as follows: X :B Y :B Z When the content of the metal element X is expressed as B X / (B X +B Y +B Z ) can be shown as

[0042] It should be noted that the terms "film" and "layer" can be interchangeable depending on the circumstances. For example, the term "conductive layer" can be changed to the term "conductive film." Or, for example, the term "insulating film" can be changed to the term "insulating layer."

[0043] Furthermore, in this specification, "parallel" refers to a state in which two straight lines are arranged at an angle of -10 degrees or more and 10 degrees or less. Therefore, it also includes cases in which the angle is -5 degrees or more and 5 degrees or less. Furthermore, "substantially parallel" refers to a state in which two straight lines are arranged at an angle of -20 degrees or more and 20 degrees or less. Furthermore, "perpendicular" refers to a state in which two straight lines are arranged at an angle of 80 degrees or more and 100 degrees or less. Therefore, it also includes cases in which the angle is 85 degrees or more and 95 degrees or less. Furthermore, "substantially perpendicular" refers to a state in which two straight lines are arranged at an angle of 70 degrees or more and 110 degrees or less.

[0044] In this specification, "connection" includes, as an example, "electrical connection." Note that the term "electrical connection" is sometimes used to define the connection relationship between circuit elements as an entity. Furthermore, "electrical connection" includes "direct connection" and "indirect connection." "A and B are directly connected" means that A and B are connected without the intervention of a circuit element (e.g., a transistor, a switch, etc.; wiring is not considered a circuit element). On the other hand, "A and B are indirectly connected" means that A and B are connected via one or more circuit elements.

[0045] For example, assuming that a circuit including A and B is operating, if there is a time during the operation of the circuit when an electrical signal is exchanged or an electrical potential interaction occurs between A and B, then it can be defined that "A and B are indirectly connected" as objects. Note that even if there is a time during the operation of the circuit when no electrical signal is exchanged or an electrical potential interaction occurs between A and B, it can still be defined as "A and B are indirectly connected" if there is a time during the operation of the circuit when an electrical signal is exchanged or an electrical potential interaction occurs between A and B.

[0046] An example of a case where "A and B are indirectly connected" is when A and B are connected via the source and drain of one or more transistors. On the other hand, an example of a case where it cannot be said that "A and B are indirectly connected" is when an insulator is present in the path from A to B. Specifically, there are cases where a capacitive element is connected between A and B, and cases where a transistor gate insulating film or the like is present between A and B. Therefore, it cannot be said that "the gate (A) of a transistor and the source or drain (B) of the transistor are indirectly connected."

[0047] Another example of a case where it cannot be said that "A and B are indirectly connected" is when multiple transistors are connected via their sources and drains to the path from A to B, and a constant potential V is supplied to a node between one transistor and another from a power supply, GND, etc.

[0048] In this specification, unless otherwise specified, the off-state current refers to the leakage current between the source and drain when the transistor is in the off state (also called the non-conducting state or the cut-off state). Unless otherwise specified, the off-state refers to the leakage current between the source and the gate when the voltage V gs is the threshold voltage V th (For p-channel transistors, V th This refers to a state of being (higher than)

[0049] In this specification, the term "normally-on" refers to a state in which a channel exists and a current flows through a transistor even when no voltage is applied to the gate, whereas the term "normally-off" refers to a state in which no current flows through a transistor when no potential is applied to the gate or when a ground potential is applied to the gate.

[0050] In this specification and the like, a tapered shape refers to a shape in which at least a portion of the side surface of a structure is inclined with respect to the substrate surface or the surface to be formed. For example, it is preferable to have a region in which the angle (also called the taper angle) between the inclined side surface and the substrate surface or the surface to be formed is greater than 0 degrees and less than 90 degrees. Note that the side surface of the structure, the substrate surface, and the surface to be formed do not necessarily need to be completely flat, and may be approximately planar with a slight curvature or approximately planar with a slight unevenness.

[0051] In this specification, when it is stated that A is located on B, at least a portion of A is located on B. Therefore, for example, it can be rephrased as "A has a region located on B." Similarly, when it is stated that A contacts B or A overlaps B, at least a portion of A contacts B or overlaps B. Therefore, it can be rephrased as "A has a region contacting B" or "A has a region overlapping B," respectively. Similarly, in this specification, when it is stated that A covers B, at least a portion of A covers B. Therefore, for example, it can be rephrased as "A has a region covering B."

[0052] In this specification and the like, a step disconnection refers to a phenomenon in which a layer, a film, or an electrode is separated due to the shape of the surface on which it is formed (for example, a step or the like).

[0053] In the drawings and the like relating to this specification, arrows indicating the X direction, Y direction, and Z direction may be used. In this specification and the like, the "X direction" refers to the direction along the X axis, and there may be no distinction between the forward direction and the reverse direction unless explicitly stated. The same applies to the "Y direction" and the "Z direction." The X direction, Y direction, and Z direction are directions that intersect with each other. For example, the X direction, Y direction, and Z direction are directions that are perpendicular to each other.

[0054] (Embodiment 1) In this embodiment, a semiconductor device of one embodiment of the present invention and a manufacturing method thereof will be described with reference to drawings.

[0055] One embodiment of the present invention relates to a semiconductor device including a trench capacitor and a vertical transistor. The semiconductor device of one embodiment of the present invention can include a memory cell including the trench capacitor and the vertical transistor. Therefore, the semiconductor device of one embodiment of the present invention can be used as a memory device.

[0056] In this specification and the like, a vertical transistor refers to a transistor in which the source electrode and the drain electrode are provided at different heights. For example, a transistor in which the bottom surfaces of the source electrode and the drain electrode are provided at different heights can be called a vertical transistor. Here, of the source electrode and the drain electrode, the electrode that is lower in height from a reference plane is called the lower electrode, and the electrode that is higher in height is called the upper electrode. The reference plane can be, for example, the upper surface of the substrate or the upper surface of the base insulating layer. An interlayer film is provided between the lower electrode and the upper electrode.

[0057] In this specification, a trench-type capacitor refers to a capacitor in which at least a portion of each of a pair of electrodes and a dielectric is located within an opening formed in an interlayer film, and at least one of the pair of electrodes is provided along the sidewall of the opening.

[0058] A semiconductor device according to one embodiment of the present invention includes a first interlayer film and a second interlayer film on the first interlayer film. The first interlayer film has a first opening, and the second interlayer film has a second opening. Parts of two or more trench capacitor structures are provided in the first opening. For example, at least a portion of the lower electrode, upper electrode, and dielectric of the first capacitor and at least a portion of the lower electrode, upper electrode, and dielectric of the second capacitor can be provided in the first opening.

[0059] Parts of the structures of two or more vertical transistors are provided in the second opening. Specifically, at least a part of the semiconductor layer of the first vertical transistor and at least a part of the semiconductor layer of the second vertical transistor are provided in the second opening. As a result, the channel formation regions of the first vertical transistor and the second vertical transistor are provided in the second opening.

[0060] The second opening has a region overlapping with the first opening, whereby the first vertical transistor is provided to have a region overlapping with the first trench capacitor, and the second vertical transistor is provided to have a region overlapping with the second trench capacitor.

[0061] As described above, according to one embodiment of the present invention, a semiconductor device in which the area occupied by each memory cell is small can be provided, and thus a semiconductor device that can be miniaturized or highly integrated can be provided.

[0062] <Configuration Example 1 of Semiconductor Device> 1A is a plan view illustrating an example of a semiconductor device of one embodiment of the present invention. The semiconductor device illustrated in FIG. 1A includes a capacitor 100a, a capacitor 100b, a transistor 200a, and a transistor 200b. That is, the semiconductor device illustrated in FIG. 1A includes two capacitors and two transistors.

[0063] FIG. 1(B) is a plan view showing an example of a capacitor 100a and a capacitor 100b. FIG. 1(C) is a plan view showing an example of a transistor 200a and a transistor 200b. FIGS. 1(B) and 1(C) are diagrams in which some elements are omitted from FIG. 1(A). FIG. 1(D) is a diagram in which some elements are further omitted from FIG. 1(C). Note that in the plan views of FIGS. 1(A) to 1(D), some elements, for example, some insulating layers, are omitted for clarity. Some elements may also be omitted in the subsequent plan views.

[0064] FIG. 2A is a cross-sectional view taken along dashed line A1-A2 in FIG. 1A. FIG. 2B is a cross-sectional view taken along dashed line A3-A4 in FIG. 1A. FIG. 2C is a schematic perspective view of the semiconductor device shown in FIGS. 1A to 2B. Specifically, FIG. 2C is a schematic perspective view of the semiconductor device taken along dashed line B1-B2 in FIG. 1A, and includes a capacitor 100a and a transistor 200a. Some components are omitted in FIG. 2C. FIG. 2D is a cross-sectional view taken along dashed line A5-A6 in FIG. 2A. Note that FIG. 2D is also referred to as a plan view.

[0065] In Figures 1(A) to 2(D), the X, Y, and Z directions are indicated by arrows. Note that although the same symbols X, Y, and Z are used in Figures 1(A) to 2(D), the directions do not necessarily have to match. The same applies to the plan views and cross-sectional views shown below.

[0066] FIG. 2E is a circuit diagram of the semiconductor device shown in FIGS. 1A and 2A. As shown in FIGS. 1A, 2A, and 2E, a semiconductor device of one embodiment of the present invention includes a memory cell 150a and a memory cell 150b. The memory cell 150a includes a capacitor 100a and a transistor 200a. The memory cell 150b includes a capacitor 100b and a transistor 200b. That is, the configurations shown in FIGS. 1A and 2A function as two memory cells.

[0067] Fig. 3A is an enlarged view of a region including the transistor 200a and the transistor 200b shown in Fig. 2A. Fig. 3B is an enlarged view of Fig. 2D. Fig. 4A is an enlarged view of the capacitor 100a and the capacitor 100b shown in Fig. 2A.

[0068] One of the source and drain of the transistor 200a is connected to one of a pair of electrodes of the capacitor 100a. The other of the source and drain of the transistor 200a is connected to a wiring BILa. A first gate of the transistor 200a is connected to a wiring WOL. A second gate of the transistor 200a is connected to a wiring BGL. The other of the pair of electrodes of the capacitor 100a is connected to a wiring CAL.

[0069] One of the source and drain of the transistor 200b is connected to one of a pair of electrodes of the capacitor 100b. The other of the source and drain of the transistor 200b is connected to a wiring BILb. A first gate of the transistor 200b is connected to a wiring WOL. A second gate of the transistor 200b is connected to a wiring BGL. The other of the pair of electrodes of the capacitor 100b is connected to a wiring CAL.

[0070] 1A to 2D includes an insulating layer 180 over a substrate (not shown), conductive layers 110 and 111 over the insulating layer 180, a memory cell 150a and a memory cell 150b over the conductive layer 110, an insulating layer 160 over the conductive layer 110 and the insulating layer 111, an insulating layer 185 over the insulating layer 160, an insulating layer 186 over the insulating layer 185, an insulating layer 280 over the insulating layer 185 and the insulating layer 186, and an insulating layer 281 over the insulating layer 280. The insulating layer 180, the insulating layer 111, the insulating layer 160, the insulating layer 185, the insulating layer 186, the insulating layer 280, and the insulating layer 281 function as interlayer films. The conductive layer 110 functions as a wiring CAL. Note that hereinafter, the memory cell 150a and the memory cell 150b may be collectively referred to as the memory cell 150. Furthermore, the capacitors 100a and 100b may be collectively referred to as the capacitor 100. Furthermore, the transistors 200a and 200b may be collectively referred to as the transistor 200.

[0071] The memory cell 150a has a capacitor 100a on the conductive layer 110 and a transistor 200a on the capacitor 100a. Similarly, the memory cell 150b has a capacitor 100b on the conductive layer 110 and a transistor 200b on the capacitor 100b.

[0072] Capacitor 100a has a conductive layer 115 on conductive layer 110, an insulating layer 121 on conductive layer 115, and a conductive layer 120a on insulating layer 121. Similarly, capacitor 100b has a conductive layer 115 on conductive layer 110, an insulating layer 121 on conductive layer 115, and a conductive layer 120b on insulating layer 121.

[0073] In the capacitors 100a and 100b, the conductive layers 120a and 120b function as one of a pair of electrodes (sometimes referred to as an upper electrode). In the capacitors 100a and 100b, the conductive layer 115 functions as the other of the pair of electrodes (sometimes referred to as a lower electrode). In the capacitors 100a and 100b, the insulating layer 121 functions as a dielectric. As described above, the capacitor 100 constitutes a MIM (Metal-Insulator-Metal) capacitor.

[0074] 2(A) and 2(B), an opening 190 is provided in the insulating layer 160, reaching the conductive layer 110. At least a portion of the conductive layer 115 is provided within the opening 190. The conductive layer 115 has a region in contact with the upper surface of the conductive layer 110 within the opening 190, and a region in contact with the side surface of the insulating layer 160 within the opening 190. At least a portion of each of the insulating layer 121, the conductive layer 120a, and the conductive layer 120b is provided within the opening 190.

[0075] The insulating layer 121 is provided to cover the conductive layer 115 in the opening 190. The insulating layer 121 can have a region located within the opening 190 and a region located on the insulating layer 160.

[0076] The conductive layer 120a and the conductive layer 120b have a region facing the conductive layer 115 within the opening 190, with the insulating layer 121 sandwiched therebetween. Therefore, the capacitors 100a and 100b are configured such that the upper electrode and the lower electrode face each other across a dielectric not only at the bottom of the opening 190 but also on the sidewalls of the opening 190. This allows the capacitance per unit area of ​​the capacitors 100a and 100b to be larger than, for example, a planar capacitor. The capacitance of the capacitors 100a and 100b can be increased by increasing the depth of the opening 190. Increasing the capacitance per unit area of ​​the capacitors 100a and 100b in this manner stabilizes the read operation of the semiconductor device. Furthermore, this also allows for the promotion of miniaturization and high integration of semiconductor devices.

[0077] As shown in Figures 1(A) and 1(B), opening 190 is preferably circular in plan view. By making it circular, the processing precision when forming the opening can be improved, and openings of minute sizes can be formed. Note that in this specification and the like, "circular" is not limited to a perfect circle.

[0078] 2A and 2B show an example in which the sidewall of the opening 190 is perpendicular to the top surface of the conductive layer 110. In this case, the opening 190 has a cylindrical shape. With such a structure, miniaturization or high integration of the semiconductor device can be achieved.

[0079] A conductive layer 115, an insulating layer 121, a conductive layer 120a, and a conductive layer 120b are stacked along the sidewall of the opening 190 and the upper surface of the conductive layer 110. The capacitor 100 having such a configuration may be called a trench-type capacitor or a trench capacitor.

[0080] 2A shows an example in which the conductive layer 120a and the conductive layer 120b are provided along the top surface and side surface of the insulating layer 121 in the opening 190. In this case, part of the end of the conductive layer 120a and part of the end of the conductive layer 120b can be located in the opening 190.

[0081] 2A to 2C show an example in which the insulating layer 121 is patterned. As a result, the insulating layer 160, the insulating layer 185, the insulating layer 186, and the like have regions that do not overlap with the insulating layer 121. Therefore, when an opening reaching the conductive layer 110 is provided in the insulating layer to connect the conductive layer 110 to another conductive layer, for example, it is not necessary to provide an opening in the insulating layer 121. As a result, an opening reaching the conductive layer 110 can be easily formed.

[0082] 2A and 2C show an example in which a part of the edge of the insulating layer 121 coincides with or substantially coincides with an edge of the conductive layer 120a located on the insulating layer 160. Also, FIGS. 2A and 2C show an example in which another part of the edge of the insulating layer 121 coincides with or substantially coincides with an edge of the conductive layer 120b located on the insulating layer 160. Although the details will be described later, by processing the insulating layer 121 and the conductive films to be the conductive layers 120a and 120b using the same mask, the edges of the conductive layers 120a and 120b located on the insulating layer 160 and the edge of the insulating layer 121 can have the above-described structure.

[0083] An insulating layer 185 is provided on capacitor 100a and capacitor 100b. Furthermore, an insulating layer 186 is provided on insulating layer 185. Insulating layer 185 is provided within opening 190 along the upper and side surfaces of conductive layer 120a, the upper and side surfaces of conductive layer 120b, and the upper surface of insulating layer 121. As a result, insulating layer 185 has a recess 187 at a position overlapping opening 190. Insulating layer 186 is provided so as to fill at least a portion of recess 187.

[0084] The insulating layer 185 has a region that does not overlap with the insulating layer 186. For example, after the insulating layer 186 is formed on the insulating layer 185, a planarization treatment is performed on the insulating layer 186 until at least a part of the top surface of the insulating layer 185 is exposed. This allows the insulating layer 185 to have a region that does not overlap with the insulating layer 186.

[0085] The insulating layer 186 is provided so as to fill at least a portion of the recess 187, and the upper surface of the insulating layer 186 is planarized, which facilitates the formation of the transistors 200a and 200b on the insulating layer 185. For example, the components of the transistors 200a and 200b can be prevented from being separated by a step caused by the recess 187. This increases the manufacturing yield of semiconductor devices, allowing low-cost semiconductor devices to be provided.

[0086] An opening reaching the conductive layer 120a and an opening reaching the conductive layer 120b are provided in the insulating layer 185. A conductive layer 161a is provided in the opening reaching the conductive layer 120a, and a conductive layer 161b is provided in the opening reaching the conductive layer 120b.

[0087] [Transistor 200] The transistor 200a includes a conductive layer 220a over the conductive layer 161a, the insulating layer 185, and the insulating layer 186, a conductive layer 255 over the insulating layer 280, a conductive layer 240a over the insulating layer 281, an insulating layer 225, an oxide semiconductor layer 230a over the conductive layer 220a and the conductive layer 240a, an insulating layer 250 over the oxide semiconductor layer 230a, and a conductive layer 260 over the insulating layer 250. Here, Figure 1(D) is a plan view in which the conductive layer 260, the oxide semiconductor layer 230a, and the oxide semiconductor layer 230b are omitted from Figure 1(C) and the conductive layer 240a and the conductive layer 240b are hatched.

[0088] Similarly, transistor 200b includes a conductive layer 220b on conductive layer 161b, insulating layer 185, and insulating layer 186, a conductive layer 255 on insulating layer 280, a conductive layer 240b on insulating layer 281, an insulating layer 225, an oxide semiconductor layer 230b on conductive layer 220b and conductive layer 240b, an insulating layer 250 on oxide semiconductor layer 230b, and a conductive layer 260 on insulating layer 250.

[0089] The oxide semiconductor layer 230a and the oxide semiconductor layer 230b function as semiconductor layers of the transistor 200a and the transistor 200b, respectively. The conductive layer 255 functions as first gate electrodes of the transistor 200a and the transistor 200b. The insulating layer 225 functions as a first gate insulating layer of the transistor 200a and the transistor 200b. The conductive layer 260 functions as a second gate electrode of the transistor 200a and the transistor 200b. The insulating layer 250 functions as a second gate insulating layer of the transistor 200a and the transistor 200b.

[0090] The conductive layer 220a serves as one of a source electrode and a drain electrode of the transistor 200a. The conductive layer 220b serves as one of a source electrode and a drain electrode of the transistor 200b. The conductive layer 240a serves as the other of the source electrode and the drain electrode of the transistor 200a. The conductive layer 240b serves as the other of the source electrode and the drain electrode of the transistor 200b.

[0091] The conductive layer 220a is connected to the conductive layer 120a through the conductive layer 161a. This connects the upper electrode of the capacitor 100a to one of the source electrode and drain electrode of the transistor 200a. Similarly, the conductive layer 220b is connected to the conductive layer 120b through the conductive layer 161b. This connects the upper electrode of the capacitor 100b to one of the source electrode and drain electrode of the transistor 200b. The conductive layer 161a can be in contact with, for example, the conductive layer 120a and the conductive layer 220a. The conductive layer 161b can be in contact with, for example, the conductive layer 120b and the conductive layer 220b. The conductive layer 220a can have a region in contact with, for example, the top surface of the conductive layer 161a. The conductive layer 220b can have a region in contact with, for example, the top surface of the conductive layer 161b.

[0092] The conductive layer 255 is provided to extend in the X direction, and the conductive layer 260 is provided to extend in the Y direction. The extending region of the conductive layer 255 functions as one of the wiring WOL and the wiring BGL. The extending region of the conductive layer 260 functions as the other of the wiring WOL and the wiring BGL. The conductive layer 255 and the conductive layer 260 are also referred to as functioning as gate wirings. Note that the conductive layer 255 may be provided to extend in the Y direction. Furthermore, the conductive layer 260 may be provided to extend in the X direction.

[0093] An insulating layer 280 is located on the conductive layers 220a and 220b, and an insulating layer 281 is located on the conductive layer 255.

[0094] 1(A), 1(C), 1(D), and 2(A) to 2(D), openings 290 reaching the conductive layers 220a, 220b, and the insulating layer 186 are provided in the insulating layer 280, the conductive layer 255, and the insulating layer 281. As shown in FIGS. 1(A), 1(C), and 1(D), the openings 290 are preferably circular in plan view. By making the openings circular, the processing accuracy in forming the openings can be improved as described above, and openings of a fine size can be formed.

[0095] The openings 290 include an opening in the insulating layer 280, an opening in the conductive layer 255, and an opening in the insulating layer 281. The shape and size of the openings 290 in a plan view may differ depending on the layer. When the shape of the openings 290 in a plan view is circular, the openings in each layer may or may not be concentric.

[0096] At least a portion of each of the components of the transistor 200a and the transistor 200b is provided in the opening 290. Specifically, at least a portion of each of the insulating layer 225, the oxide semiconductor layer 230a, the oxide semiconductor layer 230b, the insulating layer 250, and the conductive layer 260 is provided in the opening 290. The portions of the insulating layer 225, the oxide semiconductor layer 230a, the oxide semiconductor layer 230b, the insulating layer 250, and the conductive layer 260 that are provided in the opening 290 are provided so as to reflect the shape of the opening 290.

[0097] The insulating layer 225 is provided along the sidewall of the opening 290, the side surface of the conductive layer 220a overlapping with the opening 290, and the side surface of the conductive layer 220b overlapping with the opening 290. The oxide semiconductor layer 230a is provided along the top surface of the conductive layer 240a, the side surface of the insulating layer 225, the top surface of the conductive layer 220a, and the top surface of the insulating layer 186. The oxide semiconductor layer 230b is provided along the top surface of the conductive layer 240b, the side surface of the insulating layer 225, the top surface of the conductive layer 220b, and the top surface of the insulating layer 186. The insulating layer 250 is provided along the top surface and side surfaces of the oxide semiconductor layer 230a, the top surface and side surfaces of the oxide semiconductor layer 230b, the top surface of the insulating layer 186, the top surface and side surfaces of the conductive layer 240a, the top surface and side surfaces of the conductive layer 240b, and the top surface of the insulating layer 281. Here, the insulating layer 225 is provided along the sidewall of the opening 290, and the oxide semiconductor layer 230a and the oxide semiconductor layer 230b are provided along the side surface of the insulating layer 225. Therefore, it can be said that the oxide semiconductor layer 230a and the oxide semiconductor layer 230b are provided along the sidewall of the opening 290. Furthermore, in the opening 290, the insulating layer 250 is provided along the side surface of the oxide semiconductor layer 230a and the oxide semiconductor layer 230b. Therefore, it can be said that the insulating layer 250 is also provided along the sidewall of the opening 290.

[0098] The conductive layer 240a and the conductive layer 240b are provided on the insulating layer 281 and spaced apart from each other. The conductive layer 240a and the conductive layer 240b are provided extending in the Y direction. The extending region of the conductive layer 240a and the extending region of the conductive layer 240b function as the wiring BILa and the wiring BILb, respectively. The conductive layer 240a and the conductive layer 240b may also be provided extending in the X direction.

[0099] Conductive layer 240a and conductive layer 240b have cutouts at positions overlapping opening 290. In a plan view, the contour of the cutouts matches or roughly matches a part of the contour of opening 290. For example, when opening 290 is circular in a plan view, the cutouts have an arc shape. The sidewalls of opening 290 include the side surfaces of insulating layer 280, conductive layer 255, and insulating layer 281.

[0100] When the conductive layer 240a and the conductive layer 240b each have a cutout, the contact area between the conductive layer 240a and the oxide semiconductor layer 230a and the contact area between the conductive layer 240b and the oxide semiconductor layer 230b are larger than when the cutout is not provided. This increases the on-state current of the transistor 200a and the transistor 200b. Here, the case where the cutout is not provided refers to a case where the opposing side surfaces of the conductive layer 240a and the conductive layer 240b do not follow the outline of the opening 290 in a plan view. In this case, the shape of the conductive layer 240a and the conductive layer 240b in a plan view is, for example, a rectangle.

[0101] The insulating layer 225 is provided along at least a portion of the sidewall of the opening 290. In FIGS. 2A to 2D, the insulating layer 225 is provided so as to cover the sidewall of the opening 290. Specifically, the insulating layer 225 has a region in contact with a side surface of the insulating layer 281, a region in contact with a side surface of the conductive layer 255, and a region in contact with a side surface of the insulating layer 280 within the opening 290. The insulating layer 225 also has a region in contact with a side surface of the conductive layer 240a on the inner side (on the opening 290 side in plan view) and a region in contact with a side surface of the conductive layer 240b on the inner side (on the opening 290 side in plan view). The insulating layer 225 can also be referred to as a sidewall, a sidewall insulating layer, a sidewall protective layer, or the like.

[0102] Furthermore, the insulating layer 225 may have a region in contact with the side surface of the conductive layer 220a on the opening 290 side, and a region in contact with the side surface of the conductive layer 220b on the opening 290 side. In this case, the insulating layer 225 may have a region in contact with the insulating layer 186. Note that the insulating layer 225 may also have a region in contact with the insulating layer 185.

[0103] The oxide semiconductor layer 230a and the oxide semiconductor layer 230b are spaced apart from each other. As shown in FIG. 2D, the oxide semiconductor layer 230a and the oxide semiconductor layer 230b in the opening 290 are formed in an arc shape in a plan view.

[0104] The oxide semiconductor layer 230a and the oxide semiconductor layer 230b are provided in the opening 290 so as to cover a part of the insulating layer 225. The oxide semiconductor layer 230a and the oxide semiconductor layer 230b have a region in the opening 290 that faces the conductive layer 255 with the insulating layer 225 sandwiched therebetween. The oxide semiconductor layer 230a has a region in contact with the top surface of the conductive layer 220a in the opening 290 and a region in contact with the top surface of the conductive layer 240a outside the opening 290. Similarly, the oxide semiconductor layer 230b has a region in contact with the top surface of the conductive layer 220b in the opening 290 and a region in contact with the top surface of the conductive layer 240b outside the opening 290. The oxide semiconductor layer 230a and the oxide semiconductor layer 230b can also have a region in contact with the top surface of the insulating layer 186.

[0105] Outside the opening 290, the ends of the oxide semiconductor layer 230a and the oxide semiconductor layer 230b are located inside (closer to the opening 290) than the ends of the conductive layer 240a and the conductive layer 240b, respectively.

[0106] The insulating layer 250 is provided to cover the oxide semiconductor layer 230a and the oxide semiconductor layer 230b in the opening 290. The insulating layer 250 is provided on the insulating layer 281 to cover the top surfaces and side surfaces of the oxide semiconductor layer 230a, the oxide semiconductor layer 230b, the conductive layer 240a, and the conductive layer 240b. The insulating layer 250 can have a region in contact with the insulating layer 186. The insulating layer 250 has a recess at a position overlapping the opening 290.

[0107] The conductive layer 260 is provided so as to fill at least a part of the recessed portion of the insulating layer 250. The conductive layer 260 has, in the opening 290, a region facing the oxide semiconductor layer 230a with the insulating layer 250 sandwiched therebetween and a region facing the oxide semiconductor layer 230b with the insulating layer 250 sandwiched therebetween. The conductive layer 260 also has, in the opening 290, a region facing the conductive layer 255 with the insulating layer 225, the oxide semiconductor layer 230a, and the insulating layer 250 sandwiched therebetween and a region facing the conductive layer 255 with the insulating layer 225, the oxide semiconductor layer 230b, and the insulating layer 250 sandwiched therebetween.

[0108] As described above, the oxide semiconductor layer 230a and the oxide semiconductor layer 230b are provided in the opening 290. In addition, the transistors 200a and 200b have a structure in which one of the source electrode and the drain electrode (here, the conductive layer 220a and the conductive layer 220b) is located below and the other of the source electrode and the drain electrode (here, the conductive layer 240a and the conductive layer 240b) is located above, so that current flows vertically. In other words, a channel is formed along the sidewall of the opening 290. In other words, the transistors 200a and 200b are vertical transistors.

[0109] The conductive layer 255 has a region facing the conductive layer 260 with the insulating layer 225, the oxide semiconductor layer 230a, and the insulating layer 250 sandwiched therebetween, and a region facing the conductive layer 260 with the insulating layer 225, the oxide semiconductor layer 230b, and the insulating layer 250 sandwiched therebetween. In the oxide semiconductor layers 230a and 230b, the regions sandwiched between the conductive layer 255 and the conductive layer 260 and their vicinity function as channel formation regions of the transistors 200a and 200b, respectively. One of the region of the oxide semiconductor layer 230a near the conductive layer 220a and the region of the oxide semiconductor layer 230a near the conductive layer 240a functions as a source region, and the other functions as a drain region. Similarly, one of the region of the oxide semiconductor layer 230b near the conductive layer 220b and the region of the oxide semiconductor layer 230b near the conductive layer 240b functions as a source region, and the other functions as a drain region. That is, the channel forming region is sandwiched between the source region and the drain region.

[0110] With the above configuration, a channel formation region and at least one of a source region and a drain region can be formed in the opening 290. This allows the transistors 200a and 200b to occupy a smaller area than a planar transistor in which the channel formation region, the source region, and the drain region are provided separately on the XY plane. This allows for miniaturization or high integration of semiconductor devices.

[0111] In the semiconductor device of this embodiment, the capacitors 100a and 100b are provided in one opening 190. Furthermore, the channel formation regions of the transistors 200a and 200b are provided in one opening 290. With this configuration, the area occupied by the memory cell 150 can be reduced compared to, for example, a case where only one capacitor is provided in one opening 190 and only one channel formation region of a transistor is provided in one opening 290. Therefore, miniaturization or high integration of the semiconductor device can be achieved.

[0112] 1A to 2D each include a conductive layer 255 that functions as a first gate electrode and a conductive layer 260 that functions as a second gate electrode. The potential applied to the conductive layer 260 is changed independently of the potential applied to the conductive layer 255, so that the threshold voltage V th In particular, applying a negative potential to the conductive layer 260 can control the V th Therefore, when a negative potential is applied to the conductive layer 260, the drain current when the potential applied to the conductive layer 255 is 0 V can be made smaller than when no potential or a potential of 0 V or higher is applied to the conductive layer 260. Note that the conductive layer 255 may function as a second gate electrode, and the conductive layer 260 may function as a first gate electrode.

[0113] Alternatively, the conductive layer 260 may be connected to the conductive layer 255. By connecting the conductive layer 255 and the conductive layer 260 and applying the same potential to them, it is possible to increase the on-current, reduce variations in initial characteristics, suppress deterioration of electrical characteristics in a negative GBT (Gate Bias-Temperature) stress test, and suppress fluctuations in the on-current rise voltage at different drain voltages.

[0114] 1A to 2D each have two gate electrodes (a first gate electrode and a second gate electrode). Therefore, the transistor 200a and the transistor 200b can have favorable electrical characteristics.

[0115] The conductive layer 240a and the conductive layer 240b are preferably not located inside the opening 290. That is, the conductive layer 240a and the conductive layer 240b preferably do not have a region in contact with the side surface of the insulating layer 281 inside the opening 290. With this structure, the notches in the conductive layer 240a and the conductive layer 240b and the opening in the insulating layer 280 can be formed simultaneously. Furthermore, the insulating layer 225, the oxide semiconductor layer 230a, the oxide semiconductor layer 230b, and the like can be prevented from being divided by a step between the conductive layer 240a and the insulating layer 280, a step between the conductive layer 240b and the insulating layer 280, or the like.

[0116] As shown in FIGS. 1A, 2A, and 2C, the transistor 200a is provided to have an overlapping region with the capacitor 100a, and the transistor 200b is provided to have an overlapping region with the capacitor 100b. Furthermore, the opening 290 in which parts of the structures of the transistors 200a and 200b are provided overlaps with the opening 190 in which parts of the structures of the capacitors 100a and 100b are provided. This allows the area occupied by the memory cell 150 to be reduced compared to, for example, a case in which the openings 190 and 290 do not overlap. This allows for miniaturization or high integration of the semiconductor device. While FIG. 1A illustrates an example in which the openings 190 and 290 have the same shape in a plan view, these shapes may be different. Furthermore, the openings 190 and 290 may have different sizes in a plan view (e.g., diameters in the case of circles).

[0117] Note that parts of three or more capacitor structures may be provided in opening 190. Also, parts of three or more transistor structures may be provided in opening 290. For example, parts of four capacitor structures may be provided in opening 190, and parts of four transistor structures may be provided in opening 290.

[0118] As described above, an enlarged view of the region including the transistor 200a and the transistor 200b shown in FIG. 2A is shown in FIG. 3A. An enlarged view of FIG. 2D is shown in FIG. 3B. In FIG. 3A, an opening in the insulating layer 185 that reaches the conductive layer 120a is referred to as an opening 191a. An opening in the insulating layer 185 that reaches the conductive layer 120b is referred to as an opening 191b.

[0119] As shown in FIG. 3B , the side surface of the conductive layer 255 outside the opening 290 faces the side surface of the oxide semiconductor layer 230a and the side surface of the oxide semiconductor layer 230b, with the insulating layer 225 interposed therebetween. The side surface of the conductive layer 260 in a region including the center of the opening 290 faces the side surface of the oxide semiconductor layer 230a and the side surface of the oxide semiconductor layer 230b, with the insulating layer 250 interposed therebetween. That is, at least a part of the oxide semiconductor layer 230a located in the opening 290 becomes a channel formation region of the transistor 200a. At least a part of the oxide semiconductor layer 230b located in the opening 290 becomes a channel formation region of the transistor 200b. In this case, for example, the perimeter of the part of the oxide semiconductor layer 230a located in the opening 290 determines the channel width of the transistor 200a. The perimeter of the part of the oxide semiconductor layer 230b located in the opening 290 determines the channel width of the transistor 200b. From the above, it can be said that the channel widths of the transistors 200a and 200b are determined by the width of the opening 290 (the diameter when the opening 290 is circular in plan view) and the distance between the oxide semiconductor layer 230a and the oxide semiconductor layer 230b, for example, the distance between the end of the oxide semiconductor layer 230a and the end of the oxide semiconductor layer 230b. In FIGS. 3A and 3B, the width D of the opening 290 is shown. In FIG. 3B, the channel width W of the transistor 200a and the distance Hub between the end of the oxide semiconductor layer 230a and the end of the oxide semiconductor layer 230b are shown. Note that the distance Hub can be measured in the XY plane including the conductive layer 255.

[0120] Increasing the width D of the opening 290 increases the channel width per unit area, thereby increasing the on-current. On the other hand, the area occupied by the transistor 200, for example, the area of ​​the transistor 200 in a plan view, is roughly determined by the width of the opening 290. Reducing the width D of the opening 290 reduces the area occupied by the transistor 200, allowing for higher integration of the semiconductor device.

[0121] The width D of the opening 290 may vary in the depth direction (in the Z direction when the side surfaces of the opening 290 are perpendicular to the substrate surface). Here, the shortest distance between the two side surfaces of the opening 290 in the insulating layer 281 in a cross-sectional view is used as the width D. In other words, the minimum value of the width of the opening 290 in the insulating layer 281 is used as the width D of the opening 290. Note that the cross-sectional view here refers to the case where a cross section passing through the center (or center of gravity) of the opening 290 as seen from the Z direction is viewed from the X direction or the Y direction. Furthermore, the width of the opening 290 at the highest position in the insulating layer 281, the width of the opening 290 at the lowest position, the width of the opening 290 at the midpoint between these, or the average value of these three widths may be used as the width D.

[0122] Here, an example is shown in which the width D is determined using the width of the opening 290 in the insulating layer 281, but the method for determining the width D is not particularly limited. For example, the shortest distance between two side surfaces of the conductive layer 255 on the opening 290 side in a cross-sectional view, or the shortest distance between two side surfaces of the insulating layer 281 on the opening 290 side, can be used as the width D. Furthermore, for example, the shortest distance between the side surface on the inner side of the conductive layer 240a (on the opening 290 side in a plan view) and the side surface on the inner side of the conductive layer 240b (on the opening 290 side in a plan view) can also be used as the width D.

[0123] The width D of the opening 290 is set by the film thickness of each of the insulating layer 225, the oxide semiconductor layer 230a, the insulating layer 250, and the conductive layer 260 provided in the opening 290. The width D of the opening 290 is, for example, 5 nm or more, 10 nm or more, or 20 nm or more, and is preferably 300 nm or less, 200 nm or less, 100 nm or less, 60 nm or less, 50 nm or less, 40 nm or less, or 30 nm or less.

[0124] Note that the width D of the opening 290 is larger than the distance Hab. More specifically, the width D of the opening 290 is preferably larger than the sum of twice the thickness of the insulating layer 225 and the distance Hab. This allows the oxide semiconductor layer 230a and the oxide semiconductor layer 230b (collectively referred to as the oxide semiconductor layer 230) to be provided in the opening 290. Here, the thickness of the insulating layer 225 refers to the width of at least a part of the insulating layer 225 in the X direction in the example shown in FIG. 3A. Furthermore, the width D of the opening 290 is more preferably larger than the sum of twice the thickness of the insulating layer 225, twice the thickness of the oxide semiconductor layer 230a or the oxide semiconductor layer 230b, and the distance Hab. This prevents the thickness of the oxide semiconductor layer 230 from becoming thin (reduced), and thus prevents the area of ​​the channel formation region from becoming smaller in a plan view. Here, for example, the film thickness of the oxide semiconductor layer 230 refers to the width in the X direction of at least a part of the oxide semiconductor layer 230 located in the opening 290 in the example shown in FIG.

[0125] Furthermore, it is preferable that the distance Hab is small. By reducing the distance Hab, the channel width W can be increased. Furthermore, miniaturization or high integration of the semiconductor device can be achieved. The distance Hab is, for example, preferably 10 nm or more and 60 nm or less, more preferably 10 nm or more and 50 nm or less, even more preferably 10 nm or more and 40 nm or less, and even more preferably 10 nm or more and 30 nm or less. Furthermore, the distance Hab is, for example, preferably 5 nm or more and 50 nm or less, more preferably 5 nm or more and 40 nm or less, and even more preferably 5 nm or more and 30 nm or less.

[0126] The channel lengths of the transistors 200a and 200b are the distances between the source and drain regions. For example, when the conductive layer 255 functions as a first gate electrode, the channel lengths of the transistors 200a and 200b are the lengths of regions of the oxide semiconductor layers 230a and 230b that face the conductive layer 255 with the insulating layer 225 interposed therebetween, in a cross-sectional view. In other words, the channel lengths of the transistors 200a and 200b are determined by the thickness of the conductive layer 255. When the conductive layer 260 and the conductive layer 255 are connected to each other, the channel lengths of the transistors 200a and 200b are the lengths of regions of the oxide semiconductor layers 230a and 230b that are sandwiched between the conductive layer 260 and the conductive layer 255, in a cross-sectional view. In other words, the channel lengths of the transistors 200a and 200b are determined by the thickness of the conductive layer 255. In FIG. 3A, the channel length L of the transistor 200a is indicated by a dashed line with a double-headed arrow.

[0127] When the conductive layer 260 functions as the first gate electrode, the channel length of the transistor 200a can be determined by the thicknesses of the insulating layer 280, the conductive layer 255, the insulating layer 281, the conductive layer 240a, and the like over the conductive layer 220a in a cross-sectional view. Similarly, the channel length of the transistor 200b can be determined by the thicknesses of the insulating layer 280, the conductive layer 255, the insulating layer 281, the conductive layer 240b, and the like over the conductive layer 220b in a cross-sectional view.

[0128] The channel length of a planar transistor is limited by the exposure limit of photolithography, making further miniaturization difficult. However, the channel lengths of the transistors 200a and 200b can be set by the film thickness of the conductive layer 255, etc. Therefore, the channel lengths of the transistors 200a and 200b can be made into extremely fine structures that are equal to or less than the exposure limit of photolithography (for example, 60 nm or less, 50 nm or less, 40 nm or less, 30 nm or less, 20 nm or less, or 10 nm or less, and 0.1 nm or more, 1 nm or more, or 5 nm or more). This increases the on-state current of the transistors 200a and 200b, thereby improving their frequency characteristics.

[0129] Note that the channel lengths of the transistors 200a and 200b are determined by the film thickness of the conductive layer 255 and the like, and therefore do not affect the areas occupied by the transistors 200a and 200b, for example, the areas of the transistors 200a and 200b in a plan view. By setting the channel lengths of the transistors 200a and 200b to, for example, 1 μm or less, 500 nm or less, or 300 nm or less, productivity, yield, and the like can be improved in the formation of the opening 290 and the like.

[0130] From the above, the channel length of the transistor included in the semiconductor device of one embodiment of the present invention is preferably 0.1 nm or more, 1 nm or more, or 5 nm or more, and is preferably 1 μm or less, 500 nm or less, or 300 nm or less.

[0131] The channel length L of the transistor 200 is preferably at least shorter than the channel width W of the transistor 200. The channel length L of the transistor 200 is preferably 0.1 to 0.99 times, and more preferably 0.5 to 0.8 times, the channel width W of the transistor 200. With such a structure, a transistor with good electrical characteristics and high reliability can be realized.

[0132] Note that the channel width W of the transistor 200 may be equal to or less than the channel length L of the transistor 200. With such a structure, miniaturization or high integration of a semiconductor device can be achieved.

[0133] As described above, by forming the opening 290 so as to have a circular shape in a planar view, the insulating layer 225 at the opening 290 has an annular or ring-shaped shape in a planar view. Specifically, the insulating layer 225 has a ring-shaped portion having an opening concentric with the opening 290. The oxide semiconductor layer 230a and the oxide semiconductor layer 230b are provided in an arc shape. The insulating layer 250 and the conductive layer 260 are provided along the shapes of the insulating layer 225, the oxide semiconductor layer 230a, and the oxide semiconductor layer 230b. As a result, the distance between the conductive layer 255 and the oxide semiconductor layer 230a and the distance between the conductive layer 260 and the oxide semiconductor layer 230a are approximately uniform, and therefore a gate electric field can be applied to the oxide semiconductor layer 230a approximately uniformly. Similarly, since the distance between the conductive layer 255 and the oxide semiconductor layer 230b and the distance between the conductive layer 260 and the oxide semiconductor layer 230b are approximately uniform, a gate electric field can be applied to the oxide semiconductor layer 230b approximately uniformly.

[0134] In this embodiment, an example has been shown in which openings 190 and 290 are circular in plan view, but the present invention is not limited to this. In plan view, openings 190 and 290 can be, for example, a circle or a substantially circular shape such as an oval, a polygonal shape such as a triangle, a quadrangle (including a rectangle, a diamond, and a square), a pentagon, or a star-shaped polygon, or a shape with rounded corners of these polygons. The polygon may be either a concave polygon (a polygon with at least one interior angle exceeding 180 degrees) or a convex polygon (a polygon with all interior angles less than 180 degrees).

[0135] The conductive layer 240a and the conductive layer 240b can have a stacked structure of two or more layers. Figure 3A shows an example in which the conductive layer 240a has a two-layer structure of a conductive layer 240a1 and a conductive layer 240a2 over the conductive layer 240a1. Similarly, an example in which the conductive layer 240b has a two-layer structure of a conductive layer 240b1 and a conductive layer 240b2 over the conductive layer 240b1 is shown.

[0136] The conductive layer 220a and the conductive layer 220b can have a stacked structure of two or more layers. Figure 3A shows an example in which the conductive layer 220a has a two-layer structure of a conductive layer 220a1 and a conductive layer 220a2 on the conductive layer 220a1. Similarly, an example in which the conductive layer 220b has a two-layer structure of a conductive layer 220b1 and a conductive layer 220b2 on the conductive layer 220b1 is shown.

[0137] 3A illustrates a configuration in which the upper surface of conductive layer 220a has a recess 221a, and the upper surface of conductive layer 220b has a recess 221b. Specifically, the upper surface of conductive layer 220a2 has a recess 221a, and the upper surface of conductive layer 220b2 has a recess 221b. Note that, hereinafter, the recess 221a and the recess 221b may be collectively referred to as recess 221.

[0138] Recesses 221a and 221b are provided at positions overlapping opening 290. When conductive layer 220a has a two-layer structure of conductive layers 220a1 and 220a2, the bottom surface of recess 221a corresponds to the bottom surface of the recess in conductive layer 220a2, and the side surface of recess 221a corresponds to the side surface of the recess in conductive layer 220a2. Similarly, the bottom surface of recess 221b corresponds to the bottom surface of the recess in conductive layer 220b2, and the side surface of recess 221b corresponds to the side surface of the recess in conductive layer 220b2. The bottom of opening 290 includes the bottom surface of recess 221a and the bottom surface of recess 221b. The sidewalls of opening 290 can be considered to include the side surfaces of recess 221a, recess 221b, insulating layer 280, conductive layer 255, and insulating layer 281.

[0139] By providing the recess 221 at a position where the conductive layer 220 (conductive layer 220a and conductive layer 220b) overlaps with the opening 290, the height of the lower surface of the insulating layer 250 and the height of the lower surface of the conductive layer 260 within the opening 290 can be made lower than the height of the upper surface of the conductive layer 220 that contacts the insulating layer 280, compared to when the recess 221 is not provided. Here, the height of each surface can be determined based on the surface on which the transistor is to be formed. Here, the upper surface of the insulating layer 186 in the region that overlaps with the conductive layer 220 is used as the reference. The surface used as the reference is not limited to the surface on which the transistor is to be formed. For example, the upper surface of a substrate on which a transistor or a semiconductor device is provided may be used as the reference.

[0140] By reducing the height of the bottom surface of the conductive layer 260, a gate electric field from the conductive layer 260 can be easily applied to the channel formation regions of the oxide semiconductor layer 230a and the oxide semiconductor layer 230b. As a result, the electrical characteristics of the transistor 200a and the transistor 200b can be improved. In addition, a gate electric field from the conductive layer 260 can be easily applied to a region of the oxide semiconductor layer 230a in contact with the conductive layer 220a2 and a region of the oxide semiconductor layer 230b in contact with the conductive layer 220b2. As a result, the on-state current of the transistor 200a and the transistor 200b can be increased. In addition, the electrical characteristics of the transistor 200a and the transistor 200b can be improved whether the conductive layer 220a and the conductive layer 220b are used as the drain electrode or the conductive layer 240a and the conductive layer 240b are used as the drain electrode.

[0141] When the recess 221 is provided in the conductive layer 220a2 and the conductive layer 220b2, for example, the insulating layer 186 may be provided with a recess 222 at a position overlapping the opening 290. In this case, the height of the bottom surface of the insulating layer 250 and the height of the bottom surface of the conductive layer 260 within the opening 290 can each be made lower.

[0142] 4A is an enlarged view of the capacitor 100a and the capacitor 100b shown in FIG. 2A as described above. For example, FIG. 4A illustrates a configuration in which the upper surface of the conductive layer 110 has a recess. The recess is provided at a position overlapping the opening 190. Here, the bottom of the recess in the conductive layer 110 may be included in the bottom of the opening 190. Furthermore, the sidewall of the recess in the conductive layer 110 and the side surface of the insulating layer 160 may be included in the sidewall of the opening 190.

[0143] By providing a recess in the conductive layer 110 at a position overlapping the opening 190, the contact area between the conductive layer 110 and the conductive layer 115 can be increased compared to when the recess is not provided, and therefore the contact resistance between the conductive layer 110 and the conductive layer 115 can be reduced.

[0144] The conductive layer 115 has a region 101 with a curved corner in the recess of the conductive layer 110. This reduces electric field concentration in the insulating layer 121 near the region 101 compared to when the region 101 has a corner (right angle or acute angle) in a cross-sectional view. Furthermore, the end surface 103 of the conductive layer 115 is located at a position lower in height from the reference plane than the top surface 105 of the insulating layer 160. This reduces electric field concentration in the insulating layer 121 near the end surface 103 compared to when the end surface 103 is located on the insulating layer 160. As described above, by reducing electric field concentration in the insulating layer 121, dielectric breakdown of the insulating layer 121 can be suppressed, resulting in a highly reliable semiconductor device. For example, FIG. 4A illustrates an example in which the region 102 between the top surface 105 of the insulating layer 160 and the side surface of the opening 190 has a curved portion. In the example illustrated in FIG. 4A, the end surface 103 can be considered the top surface of the conductive layer 115.

[0145] FIG. 4B illustrates an example in which the end face 103 shown in FIG. 4A is located on the insulating layer 160. In the example illustrated in FIG. 4B, the region 102 between the upper surface 105 of the insulating layer 160 and the side surface of the opening 190 has a curved portion. Also, in the example illustrated in FIG. 4B, the end face 103 has a tapered shape. By having the curved portion of the region 102 and the tapered shape of the end face 103, even when the end face 103 is located on the insulating layer 160, electric field concentration on the insulating layer 121 near the region 102 and the end face 103 can be suppressed. This suppresses dielectric breakdown of the insulating layer 121, thereby providing a highly reliable semiconductor device. In the example illustrated in FIG. 4B, the end face 103 can be considered a side end face of the conductive layer 115.

[0146] 5A shows an example in which the conductive layer 110 shown in FIG. 4A has a two-layer structure including a conductive layer 110_1 and a conductive layer 110_2 on the conductive layer 110_1. In FIG. 5A, a configuration in which the upper surface of the conductive layer 110_2 has a recess is illustrated.

[0147] The conductive layer 110_1 can be made of a material that can be used for the conductive layer 220a1 and the conductive layer 220b1, which will be described later. The conductive layer 110_2 can be made of a material that can be used for the conductive layer 220a2 and the conductive layer 220b2, which will be described later. For example, the conductive layer 110_2 can be made of a conductive material containing oxygen. The conductive layer 110_1 is preferably made of a material that is more conductive than the conductive layer 110_2. Specifically, the conductive layer 110_2 is preferably made of an oxide conductor (e.g., ITO, ITSO, or In-Zn oxide), and the conductive layer 110_1 is preferably made of tungsten. The conductive layer 110_1 may be made of ruthenium, titanium nitride, tantalum nitride, or the like.

[0148] By using a conductive material containing oxygen for the conductive layer 110_2, it may be possible to easily form a curved portion in the region 101. In this case, it is possible to easily suppress electric field concentration in the insulating layer 121 near the region 101.

[0149] FIG. 5B shows an example in which the insulating layer 121 shown in FIG. 4A is not patterned. This allows the number of manufacturing steps for a semiconductor device to be reduced compared to when the insulating layer 121 is patterned. Meanwhile, by patterning the insulating layer 121, for example, the insulating layers 180, 111, 160, 185, 186, 280, 281, and 250 shown in FIGS. 2A to 2C have regions that do not overlap with the insulating layer 121. This eliminates the need to provide an opening in the insulating layer 121 when providing an opening in the insulating layer that reaches the conductive layer 110 to connect the conductive layer 110 to another conductive layer, for example. This allows the opening that reaches the conductive layer 110 to be formed more easily than when the insulating layer 121 is not patterned.

[0150] 6A is a diagram showing an example in which the conductive layer 220a2, the conductive layer 220b2, and the insulating layer 186 shown in FIG. 3A do not have a recess. In the example shown in FIG. 6A, the heights of the bottom surfaces of the oxide semiconductor layer 230a, the oxide semiconductor layer 230b, and the insulating layer 250 in the opening 290 can be made to coincide or approximately coincide with the heights of the bottom surfaces of the conductive layer 220a1 and the conductive layer 220b1. In addition, in the example shown in FIG. 6A, the height of the bottom surface of the insulating layer 225 can be made to coincide or approximately coincide with the heights of the top surfaces of the conductive layer 220a2 and the conductive layer 220b2.

[0151] FIG. 6B shows an example in which the conductive layer 220a2 and the conductive layer 220b2 shown in FIG. 3A have a first recess and a second recess located outside the first recess. FIG. 6B shows an example in which the first recess is deeper than the second recess. In other words, the bottom of the first recess is located lower (closer to the insulating layer 186) than the bottom of the second recess. When forming the opening 290, the second recess is provided in the conductive layer 220a2 and the conductive layer 220b2. Then, when an insulating film is formed and processed to form the insulating layer 225, the first recess is provided in the conductive layer 220a2 and the conductive layer 220b2. Therefore, in FIG. 6B, the sidewall of the second recess is aligned with the side surface of the insulating layer 280 at the opening 290. Furthermore, the sidewall of the first recess is aligned with the surface of the insulating layer 225 facing the oxide semiconductor layer 230a or 230b. Hereinafter, the first recess and the second recess may be collectively referred to as recesses.

[0152] 6(B), the insulating layer 225 is in contact with the bottom and sidewall of the recess (specifically, the second recess) of the conductive layer 220a and the conductive layer 220b, and is in contact with the side surface of the insulating layer 280, the conductive layer 255, the insulating layer 281, the conductive layer 240a, and the conductive layer 240b within the opening 290. The oxide semiconductor layer 230a is in contact with the bottom and sidewall of the recess (specifically, the first recess) of the conductive layer 220a and the side surface of the insulating layer 225 within the opening 290. Similarly, the oxide semiconductor layer 230b is in contact with the bottom and sidewall of the recess (specifically, the first recess) of the conductive layer 220b and the side surface of the insulating layer 225 within the opening 290. The insulating layer 250 is located inside the oxide semiconductor layer 230a and the oxide semiconductor layer 230b within the opening 290. The conductive layer 260 is located inside the insulating layer 250 within the opening 290 .

[0153] The conductive layer 220a2 has a first recess and a second recess, which allows the side surface of the conductive layer 220a2 to contact the oxide semiconductor layer 230a. This increases the contact area between the conductive layer 220a2 and the oxide semiconductor layer 230a, thereby reducing the contact resistance between the conductive layer 220a2 and the oxide semiconductor layer 230a. This increases the on-current of the transistor 200a. Similarly, the conductive layer 220b2 has a first recess and a second recess, which increases the on-current of the transistor 200b.

[0154] 6B illustrates a configuration in which the conductive layer 220a2 has a first recess and a second recess, but the present invention is not limited to this. FIG. 7A illustrates an example in which only the second recess is provided in the conductive layer 220a2 shown in FIG. 6B. In other words, the conductive layer 220a2 and the conductive layer 220b2 may have no recess in the region overlapping with the insulating layer 225.

[0155] Recesses can be formed in the conductive layer 220a2 and the conductive layer 220b2 in one or both of the steps of forming the opening 290 and forming the insulating layer 225. The semiconductor device shown in Figure 6(B) shows an example in which recesses are formed in the conductive layer 220a2 and the conductive layer 220b2 in both steps. On the other hand, the semiconductor device shown in Figure 7(A) shows an example in which recesses are not formed in the conductive layer 220a2 and the conductive layer 220b2 in the step of forming the opening 290, but are formed in the step of forming the insulating layer 225.

[0156] 7A, the insulating layer 225 contacts the side surface of the insulating layer 280, the side surface of the conductive layer 255, the side surface of the insulating layer 281, the side surface of the conductive layer 240a, the side surface of the conductive layer 240b, the top surface of the conductive layer 220a2, and the top surface of the conductive layer 220b2 within the opening 290. The oxide semiconductor layer 230a contacts the bottom and sidewall of the recess of the conductive layer 220a2 and the side surface of the insulating layer 225 within the opening 290. Similarly, the oxide semiconductor layer 230b contacts the bottom and sidewall of the recess of the conductive layer 220b2 and the side surface of the insulating layer 225 within the opening 290.

[0157] When recesses are formed in the conductive layer 220a2 in the step of forming the insulating layer 225, the oxide semiconductor layer 230a can contact the bottom and sidewalls of the recesses in the conductive layer 220a2. This increases the contact area between the oxide semiconductor layer 230a and the conductive layer 220a2, which is preferable because it reduces the contact resistance between the oxide semiconductor layer 230a and the conductive layer 220a2. Similarly, when recesses are formed in the conductive layer 220b2 in the step of forming the insulating layer 225, it is preferable because it reduces the contact resistance between the oxide semiconductor layer 230b and the conductive layer 220b2.

[0158] 7B is a diagram showing an example in which the insulating layer 225 does not cover the side surfaces of the conductive layer 240a2 and the conductive layer 240b2. In the example shown in FIG. 7B, the insulating layer 225 does not cover the side surfaces of the conductive layer 220a2 and the conductive layer 220b2.

[0159] The insulating layer 225 shown in FIG. 7(B) can be in contact with at least a portion of the side surface of the conductive layer 240a1 and at least a portion of the side surface of the conductive layer 240b1. The insulating layer 225 shown in FIG. 7(B) can be in contact with at least a portion of the side surface of the conductive layer 220a1 and at least a portion of the side surface of the conductive layer 220b1. The insulating layer 225 is not in contact with the side surface of the conductive layer 240a2 facing the opening 290 or the side surface of the conductive layer 240b2 facing the opening 290. The insulating layer 225 is not in contact with the side surfaces of the conductive layer 220a2 and the conductive layer 220b2. The insulating layer 225 may be in contact with at least a portion of the side surfaces of the conductive layer 240a2 and the conductive layer 240b2. The insulating layer 225 may be in contact with at least a portion of the side surfaces of the conductive layer 220a2 and the conductive layer 220b2.

[0160] 7B, the channel lengths of the transistors 200a and 200b can be shortened, and thus the transistors 200a and 200b can have large on-state current.

[0161] When the side surface of the conductive layer 240a2 facing the opening 290 has a portion that is not covered with the insulating layer 225, that portion contacts the oxide semiconductor layer 230a. Similarly, when the side surface of the conductive layer 240b2 facing the opening 290 has a portion that is not covered with the insulating layer 225, that portion contacts the oxide semiconductor layer 230b. As a result, the contact area between the oxide semiconductor layer 230a and the conductive layer 240a2 and the contact area between the oxide semiconductor layer 230b and the conductive layer 240b2 can be increased. Therefore, the contact resistance between the oxide semiconductor layer 230a and the conductive layer 240a and the contact resistance between the oxide semiconductor layer 230b and the conductive layer 240b can be reduced.

[0162] Furthermore, when the insulating layer 225 does not cover at least a portion of the side surface of the conductive layer 240a1, the portion of the conductive layer 240a1 that is not covered by the insulating layer 225 contacts the oxide semiconductor layer 230a. Similarly, when the insulating layer 225 does not cover at least a portion of the side surface of the conductive layer 240b1, the portion of the conductive layer 240b1 that is not covered by the insulating layer 225 contacts the oxide semiconductor layer 230b. This increases the contact area between the oxide semiconductor layer 230a and the conductive layer 240a, and the contact area between the oxide semiconductor layer 230b and the conductive layer 240b. This reduces the contact resistance between the oxide semiconductor layer 230a and the conductive layer 240a, and the contact resistance between the oxide semiconductor layer 230b and the conductive layer 240b.

[0163] Fig. 8 is a diagram showing an example in which the recesses of the conductive layer 220a2 and the conductive layer 220b2 shown in Fig. 6(B) have curved portions. Specifically, Fig. 8 shows an example in which the first recess and the second recess described above have curved portions.

[0164] When the recesses of the conductive layer 220a2 and the recesses of the conductive layer 220b2 have curved portions, the portions of the oxide semiconductor layer 230a, the oxide semiconductor layer 230b, the insulating layer 250, and the like provided on these recesses near the recesses may also have curved portions. In other words, these portions may have curved or concave surfaces in cross-sectional view. Furthermore, these portions may not have corners in cross-sectional view. This reduces electric field concentration on the insulating layer 250 near the recesses, improves the withstand voltage of the transistors 200a and 200b, and suppresses electrostatic breakdown of the transistors 200a and 200b. This can improve the reliability of the semiconductor device.

[0165] <Materials for semiconductor devices> Materials that can be used for the semiconductor device of this embodiment will be described below. Each layer included in the semiconductor device of this embodiment may have a single-layer structure or a stacked-layer structure. In the following, the oxide semiconductor layer 230a and the oxide semiconductor layer 230b may be collectively referred to as the oxide semiconductor layer 230. The conductive layer 120a and the conductive layer 120b may be collectively referred to as the conductive layer 120. The conductive layer 161a and the conductive layer 161b may be collectively referred to as the conductive layer 161. The conductive layer 220a and the conductive layer 220b may be collectively referred to as the conductive layer 220. The conductive layer 240a and the conductive layer 240b may be collectively referred to as the conductive layer 240.

[0166] [Oxide semiconductor layer] As described above, the oxide semiconductor layer 230 has a channel formation region. The oxide semiconductor layer 230 further has a source region and a drain region. The source region and the drain region have a higher carrier concentration than the channel formation region and are low-resistance regions. The oxide semiconductor layer 230 may have a single-layer structure or a stacked structure of two or more layers.

[0167] The crystallinity of a semiconductor material used for the oxide semiconductor layer 230 is not particularly limited, and any of an amorphous semiconductor, a single crystal semiconductor, and a semiconductor having crystallinity other than single crystal (a microcrystalline semiconductor, a polycrystalline semiconductor, or a semiconductor having a crystalline region in part) may be used. Use of a single crystal semiconductor or a crystalline semiconductor is preferable because deterioration of transistor characteristics can be suppressed.

[0168] The transistor 200 preferably includes a metal oxide (also referred to as an oxide semiconductor) functioning as a semiconductor in the oxide semiconductor layer 230 including a channel formation region. When a metal oxide functioning as a semiconductor is used for the oxide semiconductor layer 230, the transistor 200 can be referred to as an OS transistor.

[0169] An OS transistor is a transistor in which oxygen vacancies (V O ) and impurities, the electrical characteristics are likely to fluctuate and reliability may be reduced. O H) and generate electrons that serve as carriers. Therefore, if the channel formation region in the oxide semiconductor contains oxygen vacancies, the OS transistor is likely to have normally-on characteristics. Therefore, it is preferable that the oxygen vacancies and impurities in the channel formation region in the oxide semiconductor be reduced as much as possible. In other words, it is preferable that the carrier concentration in the channel formation region in the oxide semiconductor be reduced and the channel formation region in the oxide semiconductor be made i-type (intrinsic) or substantially i-type.

[0170] On the other hand, the source and drain regions of the OS transistor have more oxygen vacancies than the channel formation region. O The source and drain regions of an OS transistor preferably have a high carrier concentration and low resistance due to a high concentration of H or impurities such as hydrogen, nitrogen, or metal elements. That is, the source and drain regions of an OS transistor preferably have a high carrier concentration and low resistance compared to the channel formation region.

[0171] The band gap of a metal oxide functioning as a semiconductor is preferably 2.0 eV or more, more preferably 2.5 eV or more. By using a metal oxide with a wide band gap for the oxide semiconductor layer 230, the off-state current of the transistor 200 can be reduced. Because the off-state current of an OS transistor is small, the power consumption of the semiconductor device can be sufficiently reduced. Furthermore, because the OS transistor has high frequency characteristics, the semiconductor device can operate at high speed.

[0172] For an oxide semiconductor layer that can be used as a semiconductor layer of a transistor according to one embodiment of the present invention, refer to the description in Embodiment 2. Detailed description thereof will be omitted here.

[0173] Note that the semiconductor device of this embodiment may also be applied to a transistor using another semiconductor material for a channel formation region, such as a semiconductor made of a single element or a compound semiconductor.

[0174] Examples of semiconductors made of simple elements that can be used as semiconductor materials include silicon and germanium. Examples of silicon that can be used as semiconductor materials include single-crystal silicon, polycrystalline silicon, microcrystalline silicon, and amorphous silicon. Examples of polycrystalline silicon include low-temperature polysilicon (LTPS).

[0175] Compound semiconductors that can be used for the semiconductor material include silicon carbide, silicon germanium, gallium arsenide, indium phosphide, boron nitride, and boron arsenide. Boron nitride that can be used for the semiconductor layer preferably has an amorphous structure. Boron arsenide that can be used for the semiconductor layer preferably has a cubic crystal structure. Other examples of compound semiconductors include organic semiconductors and nitride semiconductors. The aforementioned oxide semiconductors are also a type of compound semiconductor. These semiconductor materials may contain impurities as dopants.

[0176] Furthermore, a transistor in which a layer material functioning as a semiconductor is used for a channel formation region may be applied to the semiconductor device of this embodiment mode. Note that the layer material will be described in detail in Embodiment Mode 6.

[0177] [Insulating layer] It is preferable to use an inorganic insulating film for each of the insulating layers (insulating layer 180, insulating layer 111, insulating layer 160, insulating layer 121, insulating layer 185, insulating layer 186, insulating layer 280, insulating layer 281, insulating layer 250, insulating layer 225, etc.) included in the semiconductor device. Examples of inorganic insulating films include an oxide insulating film, a nitride insulating film, an oxynitride insulating film, and a nitride oxide insulating film. Examples of oxide insulating films include a silicon oxide film, an aluminum oxide film, a magnesium oxide film, a gallium oxide film, a germanium oxide film, an yttrium oxide film, a zirconium oxide film, a lanthanum oxide film, a neodymium oxide film, a hafnium oxide film, a tantalum oxide film, a cerium oxide film, a gallium zinc oxide film, and a hafnium aluminate film. Examples of nitride insulating films include a silicon nitride film and an aluminum nitride film. Examples of oxynitride insulating films include a silicon oxynitride film, an aluminum oxynitride film, a gallium oxynitride film, an yttrium oxynitride film, and a hafnium oxynitride film. Examples of the nitride oxide insulating film include a silicon nitride oxide film and an aluminum nitride oxide film. An insulating layer included in a semiconductor device may be an organic insulating film.

[0178] For example, as transistors become more miniaturized and highly integrated, problems such as leakage current can occur due to thinner gate insulating layers. Using a high-k material for the gate insulating layer allows for lower voltage operation of the transistor while maintaining the physical film thickness. It also allows for thinner equivalent oxide thickness (EOT) of the gate insulating layer. Meanwhile, using a material with a low dielectric constant for the insulating layer that functions as an interlayer film can reduce the parasitic capacitance that occurs between wiring. Therefore, it is preferable to select materials according to the function of the insulating layer. Materials with a low dielectric constant also have high dielectric strength.

[0179] Examples of materials with a high relative dielectric constant include aluminum oxide, gallium oxide, hafnium oxide, tantalum oxide, zirconium oxide, hafnium zirconium oxide, oxides containing aluminum and hafnium, oxynitrides containing aluminum and hafnium, oxides containing silicon and hafnium, oxynitrides containing silicon and hafnium, and nitrides containing silicon and hafnium.

[0180] Examples of materials with a low relative dielectric constant include inorganic insulating materials such as silicon oxide, silicon oxynitride, and silicon nitride oxide, and resins such as polyester, polyolefin, polyamide (nylon, aramid, etc.), polyimide, polycarbonate, and acrylic resin. Other examples of inorganic insulating materials with a low relative dielectric constant include silicon oxide containing fluorine, silicon oxide containing carbon, and silicon oxide containing carbon and nitrogen. Another example is silicon oxide having vacancies. These silicon oxides may contain nitrogen.

[0181] Furthermore, a material capable of exhibiting ferroelectricity may be used for the insulating layer of a semiconductor device. Examples of materials capable of exhibiting ferroelectricity include metal oxides such as hafnium oxide, zirconium oxide, and hafnium zirconium oxide. Examples of materials capable of exhibiting ferroelectricity include a material obtained by adding element J1 (here, element J1 is one or more selected from zirconium, silicon, aluminum, gadolinium, yttrium, lanthanum, strontium, etc.) to hafnium oxide. The ratio of the number of hafnium atoms to the number of element J1 can be appropriately set; for example, the ratio of the number of hafnium atoms to the number of element J1 can be set to 1:1 or close to that. Examples of materials capable of exhibiting ferroelectricity include a material obtained by adding element J2 (here, element J2 is one or more selected from hafnium, silicon, aluminum, gadolinium, yttrium, lanthanum, strontium, etc.) to zirconium oxide. The ratio of the number of zirconium atoms to the number of atoms of element J2 can be set appropriately. For example, the ratio of the number of zirconium atoms to the number of atoms of element J2 can be set to 1:1 or close to that. Furthermore, as a material that can have ferroelectricity, lead titanate (PbTiO X Piezoelectric ceramics having a perovskite structure, such as barium strontium titanate (BST), strontium titanate, lead zirconate titanate (PZT), strontium bismuth tantalate (SBT), bismuth ferrite (BFO), or barium titanate, may also be used.

[0182] Examples of materials that may exhibit ferroelectricity include metal nitrides containing elements M1, M2, and nitrogen. Here, element M1 is one or more elements selected from aluminum, gallium, indium, etc. Furthermore, element M2 is one or more elements selected from boron, scandium, yttrium, lanthanum, cerium, neodymium, europium, titanium, zirconium, hafnium, vanadium, niobium, tantalum, chromium, etc. The ratio of the number of atoms of element M1 to the number of atoms of element M2 can be appropriately set. Furthermore, metal oxides containing element M1 and nitrogen may exhibit ferroelectricity even without element M2. Examples of materials that may exhibit ferroelectricity include materials obtained by adding element M3 to the above metal nitrides. Furthermore, element M3 is one or more elements selected from magnesium, calcium, strontium, zinc, cadmium, etc. Here, the ratio of the number of atoms of the element M1, the number of atoms of the element M2, and the number of atoms of the element M3 can be set appropriately.

[0183] Furthermore, materials that can have ferroelectricity include perovskite-type oxynitrides such as SrTaO2N and BaTaO2N, and GaFeO3 with a κ-alumina structure.

[0184] In the above description, metal oxides and metal nitrides are used as examples, but the present invention is not limited to these. For example, metal oxynitrides in which nitrogen is added to the aforementioned metal oxides, or metal oxynitrides in which oxygen is added to the aforementioned metal nitrides, may also be used.

[0185] Furthermore, as a material capable of exhibiting ferroelectricity, for example, a mixture or compound made of a plurality of materials selected from the materials listed above can be used. Alternatively, the insulating layer 121 described in the third embodiment can have a layered structure made of a plurality of materials selected from the materials listed above. However, since the crystal structure (characteristics) of the materials listed above may change depending not only on the film formation conditions but also on various processes, in this specification and the like, a material that exhibits ferroelectricity is referred to not only as a ferroelectric but also as a material capable of exhibiting ferroelectricity.

[0186] Metal oxides containing either or both of hafnium and zirconium can have ferroelectricity even in thin films of a few nm. Furthermore, metal oxides containing either or both of hafnium and zirconium can have ferroelectricity even in very small areas. Therefore, by using metal oxides containing either or both of hafnium and zirconium, miniaturization of semiconductor devices can be achieved. Metal oxides containing either or both of hafnium and zirconium include hafnium oxide, zirconium oxide, and hafnium zirconium oxide. Representative examples of hafnium zirconium oxide include HfZrO X (X is a real number greater than 0). X (X is a real number greater than 0) can also be used as a metal oxide with Y (yttrium) added. X (X is a real number greater than 0) and adding Y (yttrium) to it can enhance the ferroelectricity.

[0187] As described later, a metal oxide containing hafnium and / or zirconium is also a material for an insulating layer that has a function of capturing or fixing hydrogen. Therefore, by using a metal oxide containing hafnium and / or zirconium for at least a part of a gate insulating layer, hydrogen contained in the oxide semiconductor layer can be captured or fixed, thereby reducing the hydrogen concentration in the oxide semiconductor layer. Furthermore, a transistor having the gate insulating layer can function as a ferroelectric field effect transistor (FeFET).

[0188] In this specification, a layer of a material that can have ferroelectricity may be referred to as a ferroelectric layer, a metal oxide film, or a metal nitride film. Also, in this specification, a device having such a ferroelectric layer, a metal oxide film, or a metal nitride film may be referred to as a ferroelectric device.

[0189] Ferroelectricity is believed to be manifested by the displacement of oxygen or nitrogen in crystals contained in the ferroelectric layer due to an external electric field. Furthermore, it is believed that the manifestation of ferroelectricity depends on the crystal structure of the crystals contained in the ferroelectric layer. Therefore, for the insulating layer to exhibit ferroelectricity, the insulating layer 121 must contain crystals. In particular, it is preferable for the insulating layer to contain crystals having an orthorhombic crystal structure, as this will result in the manifestation of ferroelectricity. The crystal structure of the crystals contained in the insulating layer may be one or more selected from the group consisting of tetragonal, orthorhombic, monoclinic, and hexagonal. The insulating layer may also have an amorphous structure. In this case, the insulating layer may have a composite structure having an amorphous structure and a crystalline structure.

[0190] Furthermore, adding a Group 3 element in the periodic table to an oxide containing one or both of hafnium and zirconium increases the oxygen vacancy concentration in the oxide, making it easier to form crystals with an orthorhombic crystal structure. This is preferable because it increases the proportion of crystals with an orthorhombic crystal structure and increases the remanent polarization. On the other hand, adding too much Group 3 element may reduce the crystallinity of the oxide, making it difficult to exhibit ferroelectricity. Therefore, the content of the Group 3 element in an oxide containing one or both of hafnium and zirconium is preferably 0.1 atomic% to 10 atomic%, more preferably 0.1 atomic% to 5 atomic%, and even more preferably 0.1 atomic% to 3 atomic%. Here, the content of the Group 3 element refers to the ratio of the number of atoms of the Group 3 element to the sum of the number of atoms of all metal elements contained in the layer. The Group 3 element is preferably one or more selected from scandium, lanthanum, and yttrium, and more preferably one or both of lanthanum and yttrium.

[0191] It is preferable to use the above-mentioned material having a high relative dielectric constant for the insulating layer 121. By using a material having a high relative dielectric constant for the insulating layer 121, the insulating layer 121 can be made thick enough to suppress leakage current, and the electrostatic capacitance of the capacitor 100 can be sufficiently ensured.

[0192] Furthermore, the insulating layer 121 is preferably formed by stacking insulating layers made of a material with a high dielectric constant, and preferably by stacking a material with a high dielectric constant and a material with a higher dielectric strength than the material with a high dielectric constant. For example, the insulating layer 121 can be formed by stacking zirconium oxide, aluminum oxide, and zirconium oxide in this order. Alternatively, the insulating layer 121 can be formed by stacking zirconium oxide, aluminum oxide, zirconium oxide, and aluminum oxide in this order. Alternatively, the insulating layer 121 can be formed by stacking hafnium zirconium oxide, aluminum oxide, hafnium zirconium oxide, and aluminum oxide in this order. Using a stack of insulating layers with a relatively high dielectric strength, such as aluminum oxide, improves the dielectric strength and suppresses electrostatic breakdown of the capacitor 100.

[0193] Furthermore, the insulating layer 121 may be made of the above-mentioned material that can have ferroelectricity.

[0194] As described above, a metal oxide containing one or both of hafnium and zirconium can have ferroelectricity even when it is a thin film of only a few nm, and is therefore preferable for the insulating layer 121. The film thickness of the insulating layer 121 is preferably 100 nm or less, more preferably 50 nm or less, even more preferably 20 nm or less, and even more preferably 10 nm or less (typically, 2 nm to 9 nm). Furthermore, for example, the film thickness is preferably 8 nm to 12 nm. By using a ferroelectric layer that can be thinned, the capacitor 100 can be combined with a semiconductor element such as a miniaturized transistor to form a semiconductor device.

[0195] Furthermore, a metal oxide containing one or both of hafnium and zirconium can have ferroelectricity even in a small area, and is therefore preferable as the insulating layer 121. For example, when the area (occupied area) of the ferroelectric layer in a plan view is 100 μm 2 Below, 10μm 2 Below, 1μm 2 Less than or equal to 0.1 μm 2Even if the thickness is less than 10,000 nm, the material can still have ferroelectricity. 2 or less than 1000 nm 2 Even if the thickness is less than 100 MPa, the ferroelectric layer may still have ferroelectricity. By using a ferroelectric layer with a small area, the area occupied by the capacitor 100 can be reduced.

[0196] A ferroelectric material is an insulator that generates polarization internally when an external electric field is applied, and the polarization remains even when the electric field is removed. Therefore, a nonvolatile memory element can be formed using a capacitor (hereinafter, sometimes referred to as a ferroelectric capacitor) that uses this material as a dielectric. A nonvolatile memory element using a ferroelectric capacitor is sometimes called a Ferroelectric Random Access Memory (FeRAM), a ferroelectric memory, or the like. For example, a ferroelectric memory has a transistor and a ferroelectric capacitor, and one of the source and drain of the transistor is connected to one terminal of the ferroelectric capacitor. Therefore, when a ferroelectric capacitor is used as the capacitor 100, the semiconductor device described in this embodiment functions as a ferroelectric memory.

[0197] A transistor using a metal oxide can have stable electrical characteristics by being surrounded by an insulating layer that has a function of suppressing the permeation of impurities and oxygen. The insulating layer that has a function of suppressing the permeation of impurities and oxygen can be, for example, a single-layer or stacked insulating layer containing one or more elements selected from boron, carbon, nitrogen, oxygen, fluorine, magnesium, aluminum, silicon, phosphorus, chlorine, argon, gallium, germanium, yttrium, zirconium, lanthanum, neodymium, hafnium, and tantalum. Specifically, the insulating layer that has a function of suppressing the permeation of impurities and oxygen can be made of a metal oxide such as aluminum oxide, magnesium oxide, gallium oxide, germanium oxide, yttrium oxide, zirconium oxide, lanthanum oxide, neodymium oxide, hafnium oxide, or tantalum oxide; a metal nitride such as aluminum nitride or silicon nitride; or a metal nitride oxide such as silicon nitride oxide.

[0198] Specifically, examples of materials for the insulating layer that function to suppress the permeation of impurities such as water and hydrogen, and oxygen include metal oxides such as aluminum oxide, magnesium oxide, gallium oxide, germanium oxide, yttrium oxide, zirconium oxide, lanthanum oxide, neodymium oxide, hafnium oxide, tantalum oxide, and oxides containing aluminum and hafnium (hafnium aluminate). Other examples include nitrides such as aluminum nitride, aluminum titanium nitride, and silicon nitride. Other examples include metal nitride oxides such as silicon nitride oxide.

[0199] An insulating layer such as a gate insulating layer that is in contact with an oxide semiconductor layer or that is provided near the oxide semiconductor layer is preferably an insulating layer having a region containing oxygen that is released by heating (hereinafter, sometimes referred to as excess oxygen). For example, when an insulating layer having a region containing excess oxygen is in contact with an oxide semiconductor layer or is located near the oxide semiconductor layer, oxygen vacancies in the oxide semiconductor layer can be reduced. Examples of materials for an insulating layer that are likely to form a region containing excess oxygen include silicon oxide, silicon oxynitride, and silicon oxide having vacancies.

[0200] An insulating layer provided in contact with or near the oxide semiconductor layer is preferably a barrier insulating layer against hydrogen, which can suppress diffusion of hydrogen into the oxide semiconductor layer.

[0201] Examples of materials for the insulating layer having the function of capturing or fixing hydrogen include metal oxides such as oxides containing hafnium, oxides containing magnesium, oxides containing aluminum, oxides containing aluminum and hafnium (hafnium aluminate), oxides containing hafnium and silicon (hafnium silicate), etc. These metal oxides may further contain zirconium, and examples thereof include oxides containing hafnium and zirconium.

[0202] An insulating layer having the function of capturing or fixing hydrogen preferably has an amorphous structure. In a metal oxide having an amorphous structure, some oxygen atoms have dangling bonds, which enhances the ability to capture or fix hydrogen. Therefore, when the insulating layer has an amorphous structure, the function of capturing or fixing hydrogen can be enhanced. For example, an amorphous structure may be realized by adding silicon to the above metal oxide. For example, it is preferable to use an oxide containing hafnium and silicon (hafnium silicate).

[0203] By making the insulating layer an amorphous structure, it is possible to suppress the formation of crystal grain boundaries. By suppressing the formation of crystal grain boundaries, it is possible to improve the flatness of the insulating layer. This makes it possible to uniformize the film thickness distribution of the insulating layer and reduce areas with extremely thin film thickness, thereby improving the breakdown voltage of the insulating layer. It is also possible to uniformize the film thickness distribution of a film provided on the insulating layer. Furthermore, by suppressing the formation of crystal grain boundaries in the insulating layer, it is possible to reduce leakage current caused by defect levels at the crystal grain boundaries. Therefore, the insulating layer can function as an insulating film with low leakage current.

[0204] The insulating layer may partially include either or both of a crystalline region and a grain boundary.

[0205] The ability to capture or fix a corresponding substance can also be said to have the property of making it difficult for the corresponding substance to diffuse. Therefore, the ability to capture or fix a corresponding substance can be rephrased as barrier properties.

[0206] In this specification and the like, a barrier insulating layer refers to an insulating layer having barrier properties. The barrier properties refer to a property that makes it difficult for a corresponding substance to diffuse (also referred to as a property that makes it difficult for a corresponding substance to permeate, a property that the permeability of a corresponding substance is low, or a function that suppresses the diffusion of a corresponding substance). Note that hydrogen when described as a corresponding substance includes, for example, a hydrogen atom, a hydrogen molecule, a water molecule, and OH. -Furthermore, unless otherwise specified, impurities when described as corresponding substances refer to impurities in the channel formation region or semiconductor layer, and refer to at least one of, for example, hydrogen atoms, hydrogen molecules, water molecules, nitrogen atoms, nitrogen molecules, nitrogen oxide molecules (NO, NO, NO, etc.), copper atoms, etc. Furthermore, oxygen when described as corresponding substances refers to at least one of, for example, oxygen atoms and oxygen molecules, etc.

[0207] Examples of materials for the barrier insulating layer against hydrogen include aluminum oxide, magnesium oxide, hafnium oxide, gallium oxide, silicon nitride, and silicon nitride oxide.

[0208] Examples of materials for the barrier insulating layer against oxygen include oxides containing one or both of aluminum and hafnium, magnesium oxide, gallium oxide, gallium zinc oxide, silicon nitride, and silicon nitride oxide. Examples of oxides containing one or both of aluminum and hafnium include aluminum oxide, hafnium oxide, oxides containing aluminum and hafnium (hafnium aluminate), and oxides containing hafnium and silicon (hafnium silicate).

[0209] The insulating layers 180, 111, 160, 185, and 186 function as interlayer films, and therefore are preferably formed using the above-described material with a low dielectric constant. By using a material with a low dielectric constant for the interlayer films, the parasitic capacitance generated between wirings can be reduced.

[0210] A barrier insulating layer against hydrogen is preferably used for the insulating layer 185. When the insulating layer 185 provided below the oxide semiconductor layer 230 has a barrier property against hydrogen, diffusion of hydrogen from below the transistor 200 to the oxide semiconductor layer 230 can be suppressed. For example, a silicon nitride film is preferably used for the insulating layer 185.

[0211] The concentrations of impurities such as hydrogen and water are preferably reduced in the insulating layers 185 and 186. This can prevent impurities such as hydrogen and water from entering the channel formation region of the oxide semiconductor layer 230.

[0212] Since the insulating layer 280 functions as an interlayer film, it is preferable to use the aforementioned material with a low dielectric constant. By using a material with a low dielectric constant for the interlayer film, the parasitic capacitance generated between wirings can be reduced. For example, silicon oxide or silicon oxynitride can be used as the insulating layer 280.

[0213] The concentration of impurities such as hydrogen or water in the insulating layer 280 is preferably reduced. This can prevent impurities such as hydrogen or water from entering the channel formation region of the oxide semiconductor layer 230.

[0214] For example, an insulating layer having a region containing excess oxygen can be formed by sputtering in an oxygen-containing atmosphere. Furthermore, by using a sputtering method that does not require the use of hydrogen-containing molecules in the deposition gas, the hydrogen concentration in the insulating layer 280 can be reduced. By depositing at least a portion of the layers constituting the insulating layer 280 using a sputtering method, oxygen is supplied from the insulating layer 280 to the channel formation region of the oxide semiconductor layer 230, and oxygen vacancies and V O H can be reduced.

[0215] Note that the thickness of the insulating layer 280 on the conductive layer 220a or the conductive layer 220b affects the channel length of the transistor 200, and therefore the thickness of the insulating layer 280 is set appropriately according to the design value of the channel length of the transistor 200.

[0216] For example, FIG. 3A shows an example in which the insulating layer 280 has a single-layer structure. The insulating layer 280 can have a stacked structure of two or more layers. FIG. 9A shows an example in which the insulating layer 280 shown in FIG. 3A has a three-layer structure including an insulating layer 280_1, an insulating layer 280_2 on the insulating layer 280_1, and an insulating layer 280_3 on the insulating layer 280_2. In this case, it is preferable to use the above-mentioned material with a low relative dielectric constant for the insulating layer 280_2, and to use barrier insulating layers against oxygen for the insulating layers 280_1 and 280_3. This can suppress oxidation of the conductive layer 220 and the conductive layer 255 and prevent high resistance.

[0217] For example, it is preferable to use a silicon nitride film or an aluminum oxide film for the insulating layer 280_1 and the insulating layer 280_3, and a silicon oxide film for the insulating layer 280_2. Note that each of the insulating layer 280_1 and the insulating layer 280_3 may have a stacked structure of two or more layers.

[0218] The insulating layer 281 can be formed using an insulating material that can be used for the insulating layer 280. Note that the insulating layer 160 may have a structure similar to that that can be used for the insulating layer 280.

[0219] For example, FIG. 3A shows an example in which the insulating layer 281 has a single-layer structure. Note that the insulating layer 281 can have a stacked structure of two or more layers. For example, as shown in FIG. 9A, the insulating layer 281 can have a three-layer structure including an insulating layer 281_1, an insulating layer 281_2 on the insulating layer 281_1, and an insulating layer 281_3 on the insulating layer 281_2. In this case, it is preferable to use the above-described material with a low relative dielectric constant for the insulating layer 281_2, and to use barrier insulating layers against oxygen for the insulating layers 281_1 and 281_3. This can suppress oxidation of the conductive layer 255 and the conductive layer 240 and prevent high resistance.

[0220] For example, it is preferable to use a silicon nitride film or an aluminum oxide film for the insulating layer 281_1 and the insulating layer 281_3, and a silicon oxide film for the insulating layer 281_2. Note that each of the insulating layer 281_1 and the insulating layer 281_3 may have a stacked structure of two or more layers.

[0221] A barrier insulating layer against hydrogen is preferably used for the insulating layer 250. When the insulating layer 250 provided over the oxide semiconductor layer 230 has a barrier property against hydrogen, hydrogen contained in the conductive layer 260 can be prevented from diffusing into the oxide semiconductor layer 230. For example, a silicon nitride film is suitable as the insulating layer 250 because it has a high barrier property against hydrogen.

[0222] Furthermore, since the insulating layer 250 is in contact with the oxide semiconductor layer 230, it is preferable to use an insulating layer that has a function of capturing or fixing hydrogen. This allows hydrogen contained in the oxide semiconductor layer 230 to be more effectively captured or fixed. As a result, the hydrogen concentration in the oxide semiconductor layer 230 (particularly, the hydrogen concentration in the channel formation region of the transistor) can be reduced. Therefore, the V O By reducing H, the channel forming region can be made i-type or substantially i-type.

[0223] An insulating layer having a region containing excess oxygen is preferably used as the insulating layer 250. This allows oxygen to be supplied from the insulating layer 250 to the oxide semiconductor layer 230, thereby reducing oxygen vacancies in the oxide semiconductor layer 230. A silicon oxide film, a silicon oxynitride film, or the like is suitable for the insulating layer 250 because it has a structure that is stable against heat.

[0224] 3A shows an example in which the insulating layer 250 has a single-layer structure. Note that the insulating layer 250 can have a stacked structure of two or more layers. In this case, the insulating layer 250 is preferably formed using two or more types of films. When the insulating layer 250 is formed using two or more types of films, the insulating layer 250 can have multiple functions. Examples of the functions of the insulating layer 250 include a function of extracting hydrogen from the oxide semiconductor layer 230 and a function of suppressing diffusion of hydrogen into the oxide semiconductor layer 230.

[0225] For example, the insulating layer 250 can have a two-layer structure including a first insulating layer and a second insulating layer over the first insulating layer. In this case, the first insulating layer is in contact with the oxide semiconductor layer 230. For example, it is preferable to use an insulating layer having a function of capturing or fixing hydrogen as the first insulating layer and a barrier insulating layer against hydrogen as the second insulating layer. With such a structure, the hydrogen concentration in the oxide semiconductor layer 230 can be reduced and diffusion of hydrogen into the oxide semiconductor layer 230 can be suppressed. Therefore, a highly reliable transistor can be realized. For example, a hafnium oxide film or a hafnium silicate film can be used as the first insulating layer and a silicon nitride film can be used as the second insulating layer.

[0226] Alternatively, for example, it is preferable to use an insulating layer having a region containing excess oxygen as the first insulating layer and a barrier insulating layer against hydrogen as the second insulating layer. Alternatively, for example, it is preferable to use an insulating layer having a region containing excess oxygen as the first insulating layer and an insulating layer having a function of capturing or fixing hydrogen as the second insulating layer. With such a structure, the amount of oxygen vacancies and the hydrogen concentration in the oxide semiconductor layer 230 can be reduced, and diffusion of hydrogen into the oxide semiconductor layer 230 can be suppressed. Therefore, a highly reliable transistor can be provided.

[0227] Furthermore, for example, the insulating layer 250 can have a third insulating layer between the oxide semiconductor layer 230 and the first insulating layer. In other words, the insulating layer 250 can have a three-layer structure including a third insulating layer, a first insulating layer on the third insulating layer, and a second insulating layer on the first insulating layer.

[0228] For example, it is preferable to use an insulating layer having a region containing excess oxygen or an insulating layer containing a material with a low dielectric constant as the third insulating layer, an insulating layer having a function of capturing or fixing hydrogen as the first insulating layer, and an insulating layer having a barrier property against hydrogen and oxygen as the second insulating layer. The third insulating layer is preferably a silicon oxide film or a silicon oxynitride film. By using an oxide film for the third insulating layer in contact with the oxide semiconductor layer 230, oxygen can be supplied to the oxide semiconductor layer 230. Furthermore, providing the second insulating layer can suppress diffusion of oxygen contained in the third insulating layer into the conductive layer 260, thereby suppressing oxidation of the conductive layer 260. Furthermore, it is possible to suppress a decrease in the amount of oxygen supplied from the third insulating layer to the oxide semiconductor layer 230.

[0229] Furthermore, for example, the insulating layer 250 can have a fourth insulating layer between the oxide semiconductor layer 230 and the third insulating layer. In other words, the insulating layer 250 can have a four-layer structure including a fourth insulating layer, a third insulating layer on the fourth insulating layer, a first insulating layer on the third insulating layer, and a second insulating layer on the first insulating layer.

[0230] An insulating layer having a barrier property against oxygen is preferably used as the fourth insulating layer. Note that the first to third insulating layers can have the same structure as the layers used in the above-described three-layer structure. The fourth insulating layer is in contact with the oxide semiconductor layer 230 and the conductive layer 240. The fourth insulating layer has a barrier property against oxygen, which can prevent oxygen from being released from the oxide semiconductor layer 230. Furthermore, the side surfaces of the conductive layer 240 can be prevented from being oxidized and an oxide film can be prevented from being formed on the side surfaces. This can prevent a decrease in on-state current or a decrease in field-effect mobility of the transistor 200.

[0231] For example, an aluminum oxide film may be used as the fourth insulating layer. The aluminum oxide film has a function of capturing or fixing hydrogen, and is therefore suitable as the fourth insulating layer in contact with the oxide semiconductor layer 230. Specifically, the insulating layer 250 preferably has a four-layer structure in which an aluminum oxide film, a silicon oxide film, a hafnium oxide film, and a silicon nitride film are stacked in this order from the oxide semiconductor layer 230 side.

[0232] The insulating layer 250 is preferably a thin film. For example, by setting the thickness of the insulating layer 250 to be 1 nm or more and 20 nm or less, preferably 3 nm or more and 10 nm or less, it is possible to reduce the subthreshold swing value (also referred to as the S value), which is one of the transistor characteristics. The S value refers to the amount of change in gate voltage when the drain current is changed by one order of magnitude while the drain voltage is constant in the subthreshold region.

[0233] The thickness of each layer constituting the insulating layer 250 is preferably 0.1 nm to 10 nm, more preferably 0.1 nm to 5 nm, more preferably 0.5 nm to 5 nm, more preferably 1 nm to less than 5 nm, and even more preferably 1 nm to 3 nm. It is preferable that each layer constituting the insulating layer 250 has a region with the above-mentioned thickness in at least a portion thereof.

[0234] Typically, the thicknesses of the fourth insulating layer, the third insulating layer, the first insulating layer, and the second insulating layer are 1 nm, 2 nm, 2 nm, and 1 nm, respectively. With such a structure, the transistor can have good electrical characteristics even when miniaturized or highly integrated.

[0235] Note that the four-layer insulating layer 250 may not include the second insulating layer. For example, an insulating layer having a barrier property against oxygen may be used as the fourth insulating layer, an insulating layer containing a material with a low dielectric constant may be used as the third insulating layer, and an insulating layer having a function of capturing or fixing hydrogen may be used as the first insulating layer. Specifically, a three-layer structure in which an aluminum oxide film, a silicon oxide film, and a hafnium oxide film are stacked in this order from the oxide semiconductor layer 230 side may be used.

[0236] In addition, in forming the insulating layer 250 having a stacked structure of multiple insulating films, it is preferable to use an atomic layer deposition (ALD) process two or more times. For example, it is preferable that two or more of the multiple insulating films included in the insulating layer 250 are formed using an ALD process. By forming at least two or more types of insulating films using an ALD process, it is possible to improve the coverage and film thickness uniformity of the insulating layer 250. Furthermore, it is possible to increase productivity by successively forming two or more types of films, for example, two or more types of insulating films, using an ALD process.

[0237] The insulating layer 225 can be made of an insulating material that can be used for the insulating layer 250 .

[0238] As described above, it is preferable that oxygen vacancies and impurities be reduced as much as possible in the channel formation region of the oxide semiconductor layer. In particular, it is preferable that hydrogen be reduced as much as possible in the channel formation region of the oxide semiconductor layer.

[0239] Therefore, a barrier insulating layer against hydrogen is preferably used for the insulating layer 225 provided outside the oxide semiconductor layer 230. This can suppress diffusion of hydrogen into the oxide semiconductor layer 230 and improve the reliability of the transistor 200. For example, the insulating layer 225 is preferably a silicon nitride film, a silicon nitride oxide film, or an aluminum oxide film, and more preferably a silicon nitride film.

[0240] Note that a silicon nitride film also has a barrier property against oxygen. Therefore, using a silicon nitride film for the insulating layer 225 can prevent oxygen from being extracted from the oxide semiconductor layer 230 and oxygen vacancies from being formed in the oxide semiconductor layer 230. Furthermore, using a silicon nitride film for the insulating layer 225 can prevent excess oxygen from being supplied to the oxide semiconductor layer 230. Therefore, the channel formation region of the oxide semiconductor layer 230 can be prevented from becoming oxygen-excessive, thereby improving the reliability of the transistor 200. The insulating layer 225 may be in contact with the side surfaces of the conductive layer 240a and the conductive layer 240b in the opening 290. In this case, using a silicon nitride film for the insulating layer 225 can prevent the side surfaces of the conductive layer 240a and the conductive layer 240b in the opening 290 from being oxidized and oxide films from being formed on the side surfaces. This can prevent a decrease in on-state current or a decrease in field-effect mobility of the transistor 200.

[0241] The silicon nitride film of the insulating layer 225 is preferably formed using a PEALD (Plasma Enhanced ALD) method, which can improve the coverage of the insulating layer 225 on the sidewall of the opening 290 and form an insulating layer 225 with a uniform thickness.

[0242] The insulating layer 225 may also be made of the above-mentioned material that can have ferroelectricity.

[0243] For example, Fig. 3A shows an example in which the insulating layer 225 has a single-layer structure. Note that the insulating layer 225 can have a stacked structure of two or more layers. Fig. 9B shows an example in which the insulating layer 225 has a two-layer structure of an insulating layer 225_1 and an insulating layer 225_2.

[0244] 9B shows an example in which the insulating layer 225 has two layers: an insulating layer 225_1 in contact with the conductive layer 220, the insulating layer 280, the conductive layer 255, the insulating layer 281, and the conductive layer 240; and an insulating layer 225_2 located between the insulating layer 225_1 and the oxide semiconductor layer 230. The insulating layer 225 shown in FIG. 9B can be said to have a two-layer structure of the insulating layer 225_1 and the insulating layer 225_2 over the insulating layer 225_1.

[0245] The insulating layer 225_1 provided in contact with the side surface of the insulating layer 280 in the opening 290 preferably uses a barrier insulating layer against hydrogen, and the insulating layer 225_2 provided in contact with the oxide semiconductor layer 230 preferably uses an insulating layer having a function of capturing or fixing hydrogen. Such a structure can reduce the hydrogen concentration in the oxide semiconductor layer 230. Therefore, the electrical characteristics of the transistor can be improved, and the reliability of the transistor can be enhanced. For example, it is preferable to use a silicon nitride film for the insulating layer 225_1 and a hafnium oxide film, a hafnium silicate film, or an aluminum oxide film for the insulating layer 225_2. In this case, the insulating layer 225_1 contains silicon and nitrogen, and the insulating layer 225_2 contains one or both of hafnium and aluminum, and oxygen.

[0246] Furthermore, the insulating layer 225_1 can be a barrier insulating layer against hydrogen, and the insulating layer 225_2 can be an insulating layer having a region containing excess oxygen. With such a structure, one or both of oxygen vacancies and hydrogen in the oxide semiconductor layer 230 can be reduced. Therefore, the electrical characteristics of the transistor can be improved, and the reliability of the transistor can be improved. For example, it is preferable to use a silicon nitride film for the insulating layer 225_1 and a silicon oxide film, a silicon oxynitride film, or an aluminum oxide film for the insulating layer 225_2. In this case, the insulating layer 225_1 contains silicon and nitrogen, and the insulating layer 225_2 contains one or both of silicon and aluminum and oxygen. In particular, when a silicon oxide film is used for the insulating layer 225_2, the insulating layer 225_2 contains silicon and oxygen.

[0247] Typically, a silicon nitride film and a silicon oxide film can be used as the insulating layer 225_1 and the insulating layer 225_2, respectively. The thicknesses of the insulating layer 225_1 and the insulating layer 225_2 are set to 2 nm and 2 nm, respectively.

[0248] As described above, by wrapping the oxide semiconductor layer 230 in a ring shape with a barrier insulating layer against hydrogen and providing an insulating layer having a function of capturing or fixing hydrogen or an insulating layer including a region containing excess oxygen near the oxide semiconductor layer 230, it is possible to reduce one or both of oxygen vacancies and impurities in the oxide semiconductor layer 230. Therefore, the electrical characteristics of the transistor can be improved, and the reliability of the transistor can be improved.

[0249] 10(A) and 10(B) show another example of the configuration of the insulating layer 225 shown in Fig. 9(B). Fig. 10(A) is a diagram showing an example in which the bottom surface of the insulating layer 225_2 has a region in contact with the bottom of the recess 221a, a region in contact with the bottom of the recess 221b, and a region in contact with the bottom of the recess 222.

[0250] In the example shown in FIG. 10(B), the conductive layers 220a2 and 220b2 have a first recess and a second recess located outside the first recess. Also, in the example shown in FIG. 10(B), the insulating layer 186 has a third recess and a fourth recess located outside the third recess. The first recess is deeper than the second recess, and the third recess is deeper than the fourth recess. When forming the opening 290, the second recess is provided in the conductive layers 220a2 and 220b2, and a fourth recess is provided in the insulating layer 186. Then, when processing the insulating layer 225_1, the first recess is provided in the conductive layers 220a2 and 220b2, and a third recess is provided in the insulating layer 186.

[0251] 10(B), an insulating layer 225_1 is provided in contact with the bottom and sidewalls of the second recess and the fourth recess, and an insulating layer 225_2 is provided in contact with the bottom and sidewalls of the first recess and the third recess.

[0252] For example, the insulating layer 225_1 is formed to be in contact with the sidewall of the opening 290, the side surface of the conductive layer 220a, and the side surface of the conductive layer 220b. After that, an insulating film to be the insulating layer 225_2 is formed and processed, whereby the insulating layer 225 having the structure illustrated in FIG. 10A or 10B can be formed. Compared with the transistor 200 illustrated in FIG. 9B, the region where the insulating layer 225_1 is in contact with the oxide semiconductor layer 230 is reduced, and a structure in which the insulating layer 225_2 is in contact with the oxide semiconductor layer 230 can be realized.

[0253] The insulating layer 225 can have a three-layer structure including a first insulating layer, a second insulating layer, and a third insulating layer. For example, it is preferable that one of the first to third insulating layers is a barrier insulating layer against hydrogen, another is an insulating layer having a function of capturing or fixing hydrogen, and the others are insulating layers having a region containing excess oxygen. With such a structure, the electrical characteristics of the transistor can be improved, and the reliability of the transistor can be enhanced.

[0254] The insulating layer 225 can have a four-layer structure including a first insulating layer, a second insulating layer, a third insulating layer, and a fourth insulating layer. For example, it is preferable that one of the first to fourth insulating layers is a barrier insulating layer against hydrogen, another is an insulating layer having a function of capturing or fixing hydrogen, another is an insulating layer having a region containing excess oxygen, and the others are insulating layers having a barrier property against oxygen. With such a structure, a decrease in on-state current or a decrease in field-effect mobility of the transistor 200 can be suppressed.

[0255] Note that the stacked structure of the first to fourth insulating layers in the insulating layer 225 can be referred to the stacked structure of the first to fourth insulating layers in the insulating layer 250. Note that the stacked order in the insulating layer 225 is preferably the reverse of that in the insulating layer 250. For example, when the insulating layer 225 has a three-layer structure, the insulating layer 225 can have a three-layer structure including a second insulating layer in contact with the conductive layer 255, a first insulating layer on the second insulating layer, and a third insulating layer on the first insulating layer. In this case, the third insulating layer is in contact with the oxide semiconductor layer 230.

[0256] [Conductive layer] The conductive layers (conductive layer 110, conductive layer 115, conductive layer 120, conductive layer 161, conductive layer 220, conductive layer 240, conductive layer 255, conductive layer 260, etc.) included in the semiconductor device preferably contain a metal element selected from aluminum, chromium, copper, silver, gold, platinum, zinc, tantalum, nickel, titanium, iron, cobalt, molybdenum, tungsten, hafnium, vanadium, niobium, manganese, magnesium, zirconium, beryllium, indium, ruthenium, iridium, strontium, lanthanum, etc., or an alloy containing the above metal element as a component, or an alloy combining the above metal elements. The alloy containing the above metal element may be a nitride of the alloy or an oxide of the alloy. For example, tantalum nitride, titanium nitride, nitride containing titanium and aluminum, nitride containing tantalum and aluminum, ruthenium oxide, ruthenium nitride, oxide containing strontium and ruthenium, oxide containing lanthanum and nickel, etc. are preferably used. Furthermore, semiconductors with high electrical conductivity, such as polycrystalline silicon containing impurity elements such as phosphorus, and silicides such as nickel silicide may also be used.

[0257] Nitrogen-containing conductive materials such as tantalum nitride, titanium nitride, molybdenum nitride, tungsten nitride, ruthenium nitride, tantalum and aluminum nitride, and titanium and aluminum nitride are preferred, as are oxygen-containing conductive materials such as ruthenium oxide, strontium and ruthenium oxide, and lanthanum and nickel oxide. Materials containing metal elements such as titanium, tantalum, and ruthenium are preferred because they are resistant to oxidation, have the function of suppressing oxygen diffusion, or maintain conductivity even after absorbing oxygen. Examples of oxygen-containing conductive materials include indium oxide containing tungsten oxide, indium oxide containing titanium oxide, indium tin oxide (In-Sn oxide, also referred to as ITO), indium tin oxide containing titanium oxide, indium tin oxide containing silicon (ITSO), indium zinc oxide (In-Zn oxide, also referred to as IZO (registered trademark)), and indium zinc oxide containing tungsten oxide. In this specification and the like, a conductive film formed using a conductive material containing oxygen may be referred to as an oxide conductive film.

[0258] Conductive materials containing tungsten, copper, or aluminum as a main component are preferred because they have high conductivity.

[0259] Furthermore, a plurality of conductive layers formed from the above materials may be stacked. For example, a stacked structure may be formed by combining the above-described material containing a metal element and a conductive material containing oxygen. A stacked structure may be formed by combining the above-described material containing a metal element and a conductive material containing nitrogen. A stacked structure may be formed by combining the above-described material containing a metal element, a conductive material containing oxygen, and a conductive material containing nitrogen.

[0260] When a metal oxide is used for the channel formation region of a transistor, the conductive layer that functions as a gate electrode preferably has a stacked structure that combines a material containing the metal element and a conductive material containing oxygen. In this case, the conductive material containing oxygen is preferably provided on the channel formation region side. By providing the conductive material containing oxygen on the channel formation region side, oxygen desorbed from the conductive material is easily supplied to the channel formation region.

[0261] A conductive material with high conductivity, such as tungsten, can be used for the conductive layer 110. By using such a conductive material with high conductivity, the conductivity of the conductive layer 110 can be improved, and the conductive layer 110 can function sufficiently as the wiring CAL.

[0262] The conductive layer 115 is preferably formed using a single layer or a stacked layer of a conductive material that is resistant to oxidation or a conductive material that has a function of suppressing oxygen diffusion. For example, titanium nitride, ITSO, or the like may be used. Alternatively, for example, a structure in which titanium nitride is stacked on tungsten may be used. Alternatively, for example, a structure in which tungsten is stacked on a first titanium nitride, and then a second titanium nitride is stacked on the tungsten may be used. With such a structure, when an oxide is used for the insulating layer 121, the insulating layer 121 can prevent the conductive layer 115 from being oxidized. Furthermore, when an oxide is used for the insulating layer 160, the insulating layer 160 can prevent the conductive layer 115 from being oxidized.

[0263] The conductive layer 220 and the conductive layer 240 are each a conductive layer in contact with the oxide semiconductor layer 230. Therefore, for the conductive layer 220 and the conductive layer 240, it is preferable to use a conductive material that is not easily oxidized, a conductive material that maintains low electrical resistance even when oxidized, a metal oxide having conductivity (also referred to as an oxide conductor), or a conductive material that has a function of suppressing oxygen diffusion. Examples of such a conductive material include a conductive material containing nitrogen and a conductive material containing oxygen. This can suppress a decrease in the conductivity of the conductive layer 220 and the conductive layer 240.

[0264] By using a conductive material containing oxygen for the conductive layer 220, the conductive layer 220 can maintain its conductivity even if it absorbs oxygen. Similarly, by using a conductive material containing oxygen for the conductive layer 240, the conductive layer 240 can maintain its conductivity even if it absorbs oxygen. Furthermore, it is preferable to use, for example, ITO, ITSO, In-Zn oxide, or the like for each of the conductive layer 220 and the conductive layer 240.

[0265] When the conductive layer 220 and the conductive layer 240 each have a stacked structure, by using a conductive material containing oxygen for a layer in the stacked structure that has the largest contact area with the oxide semiconductor layer 230, the contact resistance between the conductive layer 220 and the oxide semiconductor layer 230 and between the conductive layer 240 and the oxide semiconductor layer 230 can be reduced.

[0266] For example, the conductive layer 220a shown in FIG. 3A has a two-layer structure of a conductive layer 220a1 and a conductive layer 220a2 on the conductive layer 220a1. Similarly, the conductive layer 220b has a two-layer structure of a conductive layer 220b1 and a conductive layer 220b2 on the conductive layer 220b1. In this case, the conductive layers 220a2 and 220b2 are preferably made of a conductive material that is resistant to oxidation, a conductive material that maintains low electrical resistance even when oxidized, a conductive metal oxide, or a conductive material that has a function of suppressing oxygen diffusion. The conductive layers 220a2 and 220b2 are preferably made of a conductive material containing oxygen, for example. Furthermore, the conductive layers 220a1 and 220b1 are preferably made of a material that has higher conductivity than the conductive layers 220a2 and 220b2, respectively. Specifically, it is preferable to use an oxide conductor (e.g., ITO, ITSO, or In-Zn oxide) for the conductive layer 220a2 and the conductive layer 220b2, and tungsten for the conductive layer 220a1 and the conductive layer 220b1. Alternatively, ruthenium, titanium nitride, tantalum nitride, or the like may be used for the conductive layer 220a1 and the conductive layer 220b1. By using an oxide conductor for the conductive layer 220a2 that is mainly in contact with the oxide semiconductor layer 230a, the contact resistance with the oxide semiconductor layer 230a can be reduced. Similarly, by using an oxide conductor for the conductive layer 220b2 that is mainly in contact with the oxide semiconductor layer 230b, the contact resistance with the oxide semiconductor layer 230b can be reduced. Furthermore, by using a material having a higher conductivity than an oxide conductor for the layers that constitute the conductive layer 220a and the layers that constitute the conductive layer 220b, the conductivity of the conductive layer 220a and the conductive layer 220b, respectively, can be increased.

[0267] For example, Figure 3(A) shows an example in which the conductive layer 220a1, the conductive layer 220b1, the conductive layer 220a2, and the conductive layer 220b2 all have a single-layer structure. Note that one or both of the conductive layer 220a1 and the conductive layer 220a2 may have a stacked structure of two or more layers. Similarly, one or both of the conductive layer 220b1 and the conductive layer 220b2 may have a stacked structure of two or more layers. Figure 11(A) shows an example in which the conductive layer 220a1 has a two-layer structure of a conductive layer 220a11 and a conductive layer 220a12 on the conductive layer 220a11, and the conductive layer 220b1 has a two-layer structure of a conductive layer 220b11 and a conductive layer 220b12 on the conductive layer 220b11. At this time, conductive layer 220a has a three-layer structure of conductive layer 220a11, conductive layer 220a12 on conductive layer 220a11, and conductive layer 220a2 on conductive layer 220a12. Similarly, conductive layer 220b has a three-layer structure of conductive layer 220b11, conductive layer 220b12 on conductive layer 220b11, and conductive layer 220b2 on conductive layer 220b12.

[0268] For example, the conductive layers 220a11 and 220b11 are preferably made of a conductive material that is resistant to oxidation or a conductive material that has the function of suppressing oxygen diffusion. The conductive layers 220a12 and 220b12 are preferably made of a material with high conductivity. The conductive layers 220a2 and 220b2 are preferably made of a conductive material containing oxygen (more preferably, an oxide conductor). Specifically, the conductive layers 220a11 and 220b11 are preferably made of titanium nitride, the conductive layers 220a12 and 220b12 are preferably made of tungsten, and the conductive layers 220a2 and 220b2 are preferably made of an oxide conductor (e.g., ITO, ITSO, or In-Zn oxide). In this case, the titanium nitride film is in contact with one or both of the insulating layers 185 and 186, for example, and the oxide conductive film is in contact with the oxide semiconductor layers 230a and 230b. Furthermore, an oxide conductor is used for the layer closest to the channel formation region of the oxide semiconductor layer 230a and the layer closest to the channel formation region of the oxide semiconductor layer 230b. Compared to tungsten, an oxide conductor has lower contact resistance with the oxide semiconductor layer 230a. Therefore, the current path between the source and drain can be shortened, and the on-state current of the transistors 200a and 200b can be increased. With this structure, conductivity can be maintained even when the conductive layer 220a is in contact with the oxide semiconductor layer 230a and the conductive layer 220b is in contact with the oxide semiconductor layer 230b. Furthermore, by using a metal material (here, tungsten) having higher conductivity than an oxide conductor and titanium nitride for the conductive layer 220a12 and the conductive layer 220b12, the conductivity of the conductive layer 220a and the conductive layer 220b can be increased.

[0269] For example, the conductive layer 240a shown in FIG. 3A has a two-layer structure including a conductive layer 240a1 and a conductive layer 240a2 on the conductive layer 240a1. Similarly, the conductive layer 240b shown in FIG. 3A has a two-layer structure including a conductive layer 240b1 and a conductive layer 240b2 on the conductive layer 240b1. In this case, for example, a conductive material containing oxygen is preferably used for the conductive layer 240a2 and the conductive layer 240b2. Furthermore, it is preferable to use a material having higher conductivity than the conductive layer 240a2 and the conductive layer 240b2 for the conductive layer 240a1 and the conductive layer 240b1. Specifically, it is preferable to use an oxide conductor (e.g., ITO, ITSO, or In-Zn oxide) for the conductive layer 240a2 and the conductive layer 240b2, and to use tungsten for the conductive layer 240a1 and the conductive layer 240b1. Furthermore, the conductive layer 240a1 and the conductive layer 240b1 may be made of ruthenium, titanium nitride, tantalum nitride, or the like. By using an oxide conductor for the conductive layer 240a2 that is mainly in contact with the oxide semiconductor layer 230a, the contact resistance with the oxide semiconductor layer 230a can be reduced. Similarly, by using an oxide conductor for the conductive layer 240b2 that is mainly in contact with the oxide semiconductor layer 230b, the contact resistance with the oxide semiconductor layer 230b can be reduced. By using a material having higher conductivity than an oxide conductor for the layers that constitute the conductive layer 240a and the layers that constitute the conductive layer 240b, the conductivity of the conductive layer 240a and the conductive layer 240b can be increased.

[0270] Note that the conductive layers 240a1 and 240b1 may be formed using a conductive material containing oxygen, and the conductive layers 240a2 and 240b2 may be formed using a material having higher conductivity than the conductive layers 240a1 and 240b1. In this case, the conductive layer 240a and the conductive layer 240b may be formed using the material having higher conductivity, which is closest to the channel formation regions of the oxide semiconductor layer 230a and the oxide semiconductor layer 230b, respectively. Therefore, the current path between the source and the drain can be shortened, and the on-state current of the transistor 200a and the transistor 200b can be increased.

[0271] The conductive layer 255 has a region that functions as one of the wirings WOL and BGL. The conductive layer 255 is preferably made of a highly conductive material such as tungsten. Furthermore, the conductive layer 255 is preferably made of a conductive material that is resistant to oxidation or a conductive material that has a function of suppressing oxygen diffusion. As described above, examples of the conductive material include a conductive material containing nitrogen (e.g., titanium nitride or tantalum nitride) and a conductive material containing oxygen (e.g., ruthenium oxide). This can suppress a decrease in the conductivity of the conductive layer 255.

[0272] Furthermore, the conductive layer 255 is preferably made of a conductive material containing oxygen and a metal element contained in the metal oxide in which the channel is formed. Alternatively, the conductive material containing the aforementioned metal element and nitrogen (e.g., titanium nitride, tantalum nitride, etc.) may be used. Alternatively, one or more selected from ITO, indium oxide containing tungsten oxide, indium zinc oxide containing tungsten oxide, indium oxide containing titanium oxide, indium tin oxide containing titanium oxide, In-Zn oxide, and ITSO may be used. Alternatively, indium gallium zinc oxide containing nitrogen may be used. Using such a material may allow hydrogen contained in the metal oxide in which the channel is formed to be captured. Alternatively, hydrogen introduced from an outer insulating layer or the like may be captured.

[0273] 3A shows an example in which the conductive layer 255 has a single-layer structure. Note that the conductive layer 255 can have a stacked structure of two or more layers.

[0274] As described above, the channel lengths of the transistors 200a and 200b can be set by the film thickness of the conductive layer 255. Therefore, the film thickness of the conductive layer 255 is set according to the desired channel length. The film thickness of the conductive layer 255 can be, for example, 2 nm to 50 nm, 3 nm to 30 nm, 4 nm to 20 nm, or 5 nm to 15 nm.

[0275] The conductive layer 260 can be made of any conductive material that can be used for the conductive layer 255 .

[0276] For example, FIG. 3A shows an example in which the conductive layer 260 has a single-layer structure. Note that the conductive layer 260 can have a stacked structure of two or more layers. FIG. 11B shows an example in which the conductive layer 260 shown in FIG. 3A has a two-layer structure including a conductive layer 260_1 and a conductive layer 260_2 over the conductive layer 260_1. In this case, for example, it is preferable to use a titanium nitride film as the conductive layer 260_1 and a tungsten film as the conductive layer 260_2. Alternatively, it is preferable to use a tantalum nitride film as the conductive layer 260_1 and a copper film as the conductive layer 260_2. With such a structure, the conductivity of the conductive layer 260 can be increased.

[0277] The conductive layer 260 may also have a stacked structure of three or more layers, such as a three-layer structure of a tantalum nitride film, a titanium nitride film on the tantalum nitride film, and a tungsten film on the titanium nitride film.

[0278] [substrate] Substrates for forming semiconductor devices can be, for example, insulating substrates, semiconductor substrates, or conductive substrates. Examples of insulating substrates include glass substrates, quartz substrates, sapphire substrates, stabilized zirconia substrates (e.g., yttria-stabilized zirconia substrates), and resin substrates. Examples of semiconductor substrates include semiconductor substrates made of silicon or germanium, or compound semiconductor substrates made of silicon carbide, silicon germanium, gallium arsenide, indium phosphide, zinc oxide, or gallium oxide. Examples of semiconductor substrates include those having an insulating region within the semiconductor substrate, such as an SOI (Silicon-On-Insulator) substrate. Examples of conductive substrates include graphite substrates, metal substrates, alloy substrates, and conductive resin substrates. Other examples include substrates having metal nitrides and substrates having metal oxides. Other examples include substrates having a conductor or semiconductor provided on an insulating substrate, substrates having a conductor or insulator provided on a semiconductor substrate, and substrates having a semiconductor or insulator provided on a conductive substrate. Alternatively, these substrates may have elements provided thereon. The elements provided on the substrate include a capacitor element, a resistor element, a switch element, a light-emitting element, a memory element, and the like.

[0279] The above is the description of the materials that can be used for the semiconductor device of this embodiment mode.

[0280] The semiconductor device of one embodiment of the present invention may include an insulating layer over the transistor 200. Specifically, an insulating layer may be provided over the conductive layer 260 and the insulating layer 250.

[0281] The insulating layer is preferably a barrier insulating layer against hydrogen, which can prevent hydrogen from diffusing from above the transistor 200 to the oxide semiconductor layer 230.

[0282] 3(A) shows a configuration in which the side surface of the conductive layer 240 in the opening 290 and the side surface of the insulating layer 280 in the opening 290 are aligned or approximately aligned, but the present invention is not limited to this. For example, the side surface of the conductive layer 240 in the opening 290 and the side surface of the insulating layer 280 in the opening 290 may be discontinuous. Furthermore, the inclination of the side surface of the conductive layer 240 in the opening 290 and the inclination of the side surface of the insulating layer 280 in the opening 290 may differ from each other. In this case, part of the side wall of the opening 290 has a tapered shape.

[0283] 12(A) and 12(B) are diagrams showing an example in which at least a portion of the sidewall of the opening 290 is tapered. Fig. 12(A) shows an example in which the side surface of the conductive layer 240a and the side surface of the conductive layer 240b in the opening 290 are tapered. Fig. 12(B) shows an example in which the side surface of the conductive layer 240a, the side surface of the conductive layer 240b, the side surface of the insulating layer 281, the side surface of the conductive layer 255, and the side surface of the insulating layer 280 in the opening 290 are each tapered.

[0284] By tapering the sidewall of the opening 290, the coverage of the insulating layer 225, the oxide semiconductor layer 230a, the oxide semiconductor layer 230b, the insulating layer 250, and the like can be improved, and defects such as voids can be reduced. When the sidewall of the opening 290 is tapered, for example, the taper angle (angle θ240) of the side surface of the conductive layer 240a in the opening 290, the taper angle (angle θ281) of the side surface of the conductive layer 240b in the opening 290, and the taper angle (angle θ281) of the side surface of the insulating layer 281 in the opening 290 are preferably 45 degrees or more and less than 90 degrees. Specifically, an angle of 80 degrees or more and less than 90 degrees is preferable, as described above, because this allows for miniaturization or high integration of the semiconductor device. Furthermore, an angle of 45 degrees or more or 50 degrees or more and less than 80 degrees, 75 degrees or less, 70 degrees or less, 65 degrees or less, or 60 degrees or less is preferable, because this improves the coverage of the film formed in the opening 290.

[0285] Also, for example, it is preferable that angle θ240 is smaller than angle θ281. With such a configuration, the coverage of the insulating layer 225, the oxide semiconductor layer 230a, and the like on the side surface of, for example, the conductive layer 240a in the opening 290 is improved, and defects such as voids can be reduced. Furthermore, when the insulating layer 280 has a stacked structure, the inclination of the side surface of each layer in the opening 290 may be different. Similarly, when the conductive layer 240a and the conductive layer 240b have a stacked structure, the inclination of the side surface of each layer in the opening 290 may be different.

[0286] As described above, the oxide semiconductor layer 230 can have a stacked structure of two or more layers.

[0287] 13A is a diagram showing an example in which the oxide semiconductor layer 230 included in the semiconductor device shown in FIG. 9B has a two-layer structure. The oxide semiconductor layer 230a shown in FIG. 13A can have a two-layer structure of an oxide semiconductor layer 230a1 and an oxide semiconductor layer 230a2 over the oxide semiconductor layer 230a1. Similarly, the oxide semiconductor layer 230b shown in FIG. 13A can have a two-layer structure of an oxide semiconductor layer 230b1 and an oxide semiconductor layer 230b2 over the oxide semiconductor layer 230b1.

[0288] 13B is a diagram showing an example in which the oxide semiconductor layer 230 included in the semiconductor device shown in FIG. 9B has a three-layer structure. The oxide semiconductor layer 230a shown in FIG. 13B can have a three-layer structure including an oxide semiconductor layer 230a1, an oxide semiconductor layer 230a2 on the oxide semiconductor layer 230a1, and an oxide semiconductor layer 230a3 on the oxide semiconductor layer 230a2. Similarly, the oxide semiconductor layer 230b shown in FIG. 13B can have a three-layer structure including an oxide semiconductor layer 230b1, an oxide semiconductor layer 230b2 on the oxide semiconductor layer 230b1, and an oxide semiconductor layer 230b3 on the oxide semiconductor layer 230b2.

[0289] Note that the boundary (also referred to as an interface) between the oxide semiconductor layer 230a1 and the oxide semiconductor layer 230a2 and the boundary (also referred to as an interface) between the oxide semiconductor layer 230a2 and the oxide semiconductor layer 230a3 may not be clearly visible. Similarly, the boundary (also referred to as an interface) between the oxide semiconductor layer 230b1 and the oxide semiconductor layer 230b2 and the boundary (also referred to as an interface) between the oxide semiconductor layer 230b2 and the oxide semiconductor layer 230b3 may not be clearly visible. Therefore, in Figures 13A and 13B, these boundaries are indicated by dashed lines.

[0290] For oxide semiconductor layers applicable to the oxide semiconductor layers 230a1 to 230a3 and the oxide semiconductor layers 230b1 to 230b3, the description in Embodiment 2 can be referred to.

[0291] 3A illustrates a configuration in which an end of the oxide semiconductor layer 230a in the opening 290 is located more inward than an end of the conductive layer 220a on the opening 290 side (on the side surface of the conductive layer 220b in the opening 290). FIG. 3A also illustrates a configuration in which an end of the oxide semiconductor layer 230b in the opening 290 is located more inward than an end of the conductive layer 220b on the opening 290 side (on the side surface of the conductive layer 220a in the opening 290). FIG. 3A also illustrates a configuration in which the oxide semiconductor layer 230a and the oxide semiconductor layer 230b are in contact with the top surface of the insulating layer 186 in the opening 290. The configuration in which the end of the oxide semiconductor layer 230a and the end of the oxide semiconductor layer 230b in the opening 290 are located on the insulating layer 186 makes it relatively easy to process the oxide semiconductor films that become the oxide semiconductor layers 230a and 230b.

[0292] Note that the present invention is not limited to the above-described structure as long as the opening 290 includes a region where the oxide semiconductor layer 230a and the conductive layer 220a are in contact with each other and a region where the oxide semiconductor layer 230b and the conductive layer 220b are in contact with each other. FIG. 14A illustrates an example in which the oxide semiconductor layer 230a and the oxide semiconductor layer 230b in the opening 290 illustrated in FIG. 3A are not in contact with the top surface of the insulating layer 186. By configuring the transistors 200a and 200b as illustrated in FIG. 14A, the distance between the oxide semiconductor layer 230a and the oxide semiconductor layer 230b (corresponding to the distance Hab illustrated in FIG. 3B) can be increased without reducing the contact area between the conductive layer 220a and the oxide semiconductor layer 230a and the contact area between the conductive layer 220b and the oxide semiconductor layer 230b. This shortens the distance between the conductive layer 220a and the conductive layer 220b, thereby enabling miniaturization or high integration of semiconductor devices.

[0293] FIG. 14B illustrates an example in which the film thickness (hereinafter referred to as the first film thickness) of a portion of the oxide semiconductor layer 230a shown in FIG. 3A, where the upper surface of the conductive layer 240a or the conductive layer 220a is to be formed, differs from the film thickness (hereinafter referred to as the second film thickness) of a portion of the oxide semiconductor layer 230a, where the sidewall of the opening 290 is to be formed. For example, when a portion of the oxide semiconductor layer 230a is formed by sputtering, the oxide semiconductor layer 230a may have different first and second film thicknesses. For example, as shown in FIG. 14B, the ratio of the second film thickness to the first film thickness may be less than 1, less than 0.8, or less than 0.5. In particular, the ratio of the second film thickness to the first film thickness in the oxide semiconductor layer 230a tends to decrease as the angle θ281 shown in FIG. 12B approaches 90 degrees. The above description of the first film thickness and the second film thickness also applies to the oxide semiconductor layer 230b.

[0294] 3A illustrates a structure in which an end portion of the oxide semiconductor layer 230 outside the opening 290 is located inside an end portion of the conductive layer 240. The end portion of the oxide semiconductor layer 230 outside the opening 290 is located inside an end portion of the conductive layer 240 on the opposite side of the opening 290, i.e., on the opening 290 side. In this case, the top surface of the conductive layer 240 has a region in contact with the insulating layer 250 and a region in contact with the oxide semiconductor layer 230. Specifically, the top surface of the conductive layer 240a has a region in contact with the insulating layer 250 and a region in contact with the oxide semiconductor layer 230a. The top surface of the conductive layer 240b has a region in contact with the insulating layer 250 and a region in contact with the oxide semiconductor layer 230b.

[0295] 15A is a diagram showing an example in which, outside the opening 290 shown in FIG. 3A, an edge of the oxide semiconductor layer 230 coincides or substantially coincides with an edge of the conductive layer 240 on the opposite side from the opening 290 in a plan view. The structure shown in FIG. 15A allows the steps of forming the conductive layers 240a and 240b and the steps of forming the oxide semiconductor layers 230a and 230b to be partially common. This eliminates the need to separately form the conductive layers 240a and 240b and the oxide semiconductor layers 230a and 230b, thereby reducing the number of steps.

[0296] 15(B) and 15(C) are plan views showing an example in which the shape of the opening 290 in a plan view is a substantially quadrangle with rounded corners. FIG. 15(B) shows an example in which the shape of the opening 290 in a plan view is a substantially square with rounded corners. FIG. 15(C) shows an example in which the shape of the opening 290 in a plan view is a substantially rectangle with rounded corners. Note that while FIG. 15(C) shows an example in which the shape of the opening 290 in a plan view is a substantially rectangle with long sides in the X direction, it may also be a substantially rectangle with long sides in the Y direction. Furthermore, when the shape of the opening 290 in a plan view is a substantially quadrangle, each side does not have to be parallel to the X direction and the Y direction.

[0297] 15B or 15C, the channel width per unit area of ​​the transistors 200a and 200b can be increased, thereby increasing the on-state current of the transistors 200a and 200b.

[0298] <Configuration Example 2 of Semiconductor Device> 1A to 2C. The semiconductor devices shown in FIGS. 16A to 19D include a capacitor 100 and a transistor that is partially different in configuration from the transistor 200. Note that descriptions of overlapping parts will be omitted, and only differences will be described in detail. Furthermore, even if components differ in position or shape, the same reference numerals may be used and descriptions thereof may be omitted if the functions are the same.

[0299] [Transistor 200A] FIG. 16(A) is a plan view of a semiconductor device including transistors 200Aa and 200Ab. FIG. 16(B) is a cross-sectional view taken along dashed line A1-A2 in FIG. 16(A). FIG. 16(C) is a cross-sectional view taken along dashed line A3-A4 in FIG. 16(A). Note that in FIG. 16(A), for clarity, the conductive layer 260 is hatched. For a cross-sectional view taken along dashed line A5-A6 in FIG. 16(B), refer to FIG. 2(D). Note that hereinafter, the transistors 200Aa and 200Ab may be collectively referred to as transistor 200A.

[0300] 16A to 16C includes an insulating layer 180, a conductive layer 110, an insulating layer 160, an insulating layer 185, an insulating layer 186, a conductive layer 161a, a conductive layer 161b, a capacitor 100a, and a capacitor 100b, a transistor 200Aa and a transistor 200Ab on the insulating layer 185, the insulating layer 186, the conductive layer 161a, and the conductive layer 161b, an insulating layer 280 on the insulating layer 185 and the insulating layer 186, an insulating layer 281 on the insulating layer 280, an insulating layer 284, an insulating layer 285 on the insulating layer 284, and a conductive layer 265 on the transistor 200Aa, the transistor 200Ab, the insulating layer 284, and the insulating layer 285. The insulating layer 284 has a region located between the conductive layer 260 and the insulating layer 285. The insulating layers 284 and 285 function as interlayer films.

[0301] The semiconductor device shown in FIGS. 16A to 16C differs from the semiconductor device shown in FIGS. 1A to 2C in that a conductive layer 265, an insulating layer 284, and an insulating layer 285 are included.

[0302] 16A to 16C, the conductive layer 265 is provided to extend in the Y direction. The conductive layer 265 functions as the other of the wiring WOL and the wiring BGL. Note that the conductive layer 265 may be provided to extend in the X direction.

[0303] The conductive layer 265 can be formed using a material that can be used for the conductive layer 260. For example, a high-melting-point material that has both heat resistance and conductivity, such as tungsten or molybdenum, can be used for the conductive layer 265. Alternatively, a low-resistance conductive material, such as aluminum or copper, can be used. By using a low-resistance conductive material, wiring resistance can be reduced.

[0304] The transistor 200Aa includes a conductive layer 220a, a conductive layer 255, a conductive layer 240a, an insulating layer 225, an oxide semiconductor layer 230a, an insulating layer 250, and a conductive layer 260. The transistor 200Ab includes a conductive layer 220b, a conductive layer 255, a conductive layer 240b, an insulating layer 225, an oxide semiconductor layer 230b, an insulating layer 250, and a conductive layer 260. The conductive layer 265 has a region in contact with the conductive layer 260. Note that the conductive layer 265 may be considered a component of the transistor 200Aa and the transistor 200Ab. The insulating layer 284 is provided over the insulating layer 250.

[0305] 16(B) and 16(C), the insulating layer 284 is provided so as to be located on the insulating layer 250. Furthermore, the insulating layer 284 is provided with an opening 270 that reaches the insulating layer 250 at a position overlapping the opening 290. At least a portion of the conductive layer 260 is provided within the opening 270. The conductive layer 260 contacts the insulating layer 250 within the opening 270.

[0306] The conductive layer 260 is provided to fill the opening 290 and the opening 270. The conductive layer 260 has a portion that faces the oxide semiconductor layer 230 in the opening 290 with the insulating layer 250 interposed therebetween, and a portion that is located in the opening 270.

[0307] The portion of the conductive layer 265 that does not overlap with the opening 290 is mainly located on the insulating layer 285. Therefore, the conductive layer 265 mainly overlaps with the conductive layer 240a and the conductive layer 240b via the insulating layer 284 and the insulating layer 285. This increases the distance between the conductive layer 265 and the conductive layer 240a and the distance between the conductive layer 265 and the conductive layer 240b. This reduces the parasitic capacitance between the conductive layer 265 and the conductive layer 240a and the parasitic capacitance between the conductive layer 265 and the conductive layer 240b. In particular, it is preferable that the insulating layer 285 is thick, for example, thicker than the insulating layer 284, because this increases the distance between the conductive layer 265 and the conductive layer 240a and the conductive layer 265 and the conductive layer 240b. Note that the conductive layer 240a and the conductive layer 240b may have portions that overlap with the conductive layer 265 without the insulating layer 285 interposed therebetween.

[0308] 16B shows an example in which the width of the opening 270 is smaller than the width D of the opening 290. The smaller the width of the opening 270, the greater the distance between the conductive layer 240a and the conductive layer 260 and the distance between the conductive layer 265 and the conductive layer 240b. This is preferable because it reduces the parasitic capacitance generated between the conductive layer 240a and the conductive layer 260 and the parasitic capacitance generated between the conductive layer 240b and the conductive layer 260. For example, it is preferable that the width of the opening 270 is the same as or smaller than the width of the opening 290.

[0309] It is preferable that the height of the top surface of the conductive layer 260 is the same as or approximately the same as the height of the top surface of the insulating layer 285 or the insulating layer 284. The conductive layer 265 is provided over the insulating layer 285, the insulating layer 284, and the conductive layer 260, and is in contact with the top surface of the conductive layer 260. It can also be said that the conductive layer 260 and the conductive layer 265 are connected to each other.

[0310] That is, the transistor 200A has a structure in which the parasitic capacitance generated between the other of the source electrode and the drain electrode and the gate wiring is reduced, thereby improving the frequency characteristics of a circuit using the transistor.

[0311] In this embodiment, an example in which opening 270 is circular in plan view has been shown, but the present invention is not limited to this. Shapes that can be applied to opening 270 are the same as the shapes that can be applied to opening 290 described above.

[0312] Furthermore, the width of the opening 270 may vary in the depth direction. In particular, the width of the opening 270 used here is the maximum width of the opening 270 provided in the insulating layer 284 in a cross-sectional view.

[0313] The insulating layer 284 is preferably an insulating layer having a function of capturing or fixing hydrogen. With such a structure, diffusion of hydrogen from above the insulating layer 284 to the oxide semiconductor layer 230 can be suppressed, and further, hydrogen contained in the oxide semiconductor layer 230 can be captured or fixed. Therefore, the hydrogen concentration in the oxide semiconductor layer 230 can be reduced. The insulating layer 284 can be formed using an aluminum oxide film, a hafnium oxide film, a hafnium silicate film, or the like.

[0314] Furthermore, a barrier insulating layer against hydrogen can be used as the insulating layer 284. This can suppress diffusion of hydrogen from above the insulating layer 284 to the oxide semiconductor layer 230. A silicon nitride film and a silicon nitride oxide film each have characteristics of releasing little impurities (for example, water and hydrogen) from themselves and being less permeable to oxygen and hydrogen, and therefore can be suitably used for the insulating layer 284.

[0315] When a silicon nitride film is used as the insulating layer 284, the silicon nitride film is preferably deposited by a sputtering method. The sputtering method does not require the use of hydrogen-containing molecules in the deposition gas, and therefore can reduce the hydrogen concentration in the insulating layer 284. Furthermore, by depositing the insulating layer 284 by a sputtering method, a silicon nitride film with high density can be formed.

[0316] Alternatively, the insulating layer 284 may have a stacked structure of an insulating layer having a function of capturing or fixing hydrogen and a barrier insulating layer against hydrogen. For example, the insulating layer 284 may be a stacked film of an aluminum oxide film and a silicon nitride film over the aluminum oxide film.

[0317] The insulating layer 285 functions as an interlayer film, and therefore is preferably made of the above-mentioned material having a low relative dielectric constant. For example, the insulating layer 285 preferably includes a silicon oxide film.

[0318] The above is a description of the semiconductor device having the capacitors 100a and 100b as well as the transistors 200Aa and 200Ab.

[0319] [Transistor 200B] FIG. 17A is a plan view of a semiconductor device including transistors 200Ba and 200Bb. FIG. 17B is a cross-sectional view taken along dashed-dotted line A1-A2 in FIG. 17A. FIG. 17C is a cross-sectional view taken along dashed-dotted line A3-A4 in FIG. 17A. For clarity, the conductive layer 260 in FIG. 17A is hatched. For a cross-sectional view taken along dashed-dotted line A5-A6 in FIG. 17B, refer to FIG. 2D. Below, descriptions of parts that overlap with FIGS. 16A to 16C will be omitted, and only differences will be described in detail. Hereinafter, the transistors 200Ba and 200Bb may be collectively referred to as the transistor 200B.

[0320] The semiconductor device shown in Figures 17(A) to 17(C) differs from the semiconductor device shown in Figures 16(A) to 16(C) in that the insulating layer 250 has a portion in contact with the side surface of the insulating layer 284 in the opening 270.

[0321] The insulating layer 250 contacts the oxide semiconductor layer 230 and the insulating layer 284 within the opening 270. The portion of the insulating layer 250 provided within the opening 270 is provided to reflect the shape of the opening 270. Specifically, the insulating layer 250 is provided along the sidewall of the opening 270 (the side surface of the insulating layer 284). Then, the conductive layer 260 is provided to fill at least a portion of the recess in the insulating layer 250 that reflects the shape of the opening 270.

[0322] 17A to 17C, the conductive layer 260 does not overlap with the top surface of the conductive layer 240a or the top surface of the conductive layer 240b. Therefore, the parasitic capacitance generated between the conductive layer 240a and the conductive layer 260 and the parasitic capacitance generated between the conductive layer 240b and the conductive layer 260 can be reduced.

[0323] 17(B), in a cross-sectional view, the maximum width of the conductive layer 260 is smaller than the width D of the opening 290. When the maximum width of the conductive layer 260 is smaller than the width D of the opening 290, the parasitic capacitance generated between the conductive layer 260 and the conductive layer 240a and the parasitic capacitance generated between the conductive layer 260 and the conductive layer 240b can be reduced, which is preferable. Note that, for example, as shown in FIG. 17(B), the magnitude relationship between the two widths in the semiconductor device of one embodiment of the present invention can be confirmed from a cross section parallel to the Z direction.

[0324] 17(B) shows an example in which the width of the opening 270 is smaller than the width D of the opening 290. It is more preferable that the width of the opening 270 is the same as or smaller than the width of the opening 290. This prevents the conductive layer 260 from overlapping the upper surfaces of the conductive layers 240a and 240b. This is preferable because it reduces the parasitic capacitance generated between the conductive layer 260 and the conductive layer 240a and the parasitic capacitance generated between the conductive layer 240b and the conductive layer 260.

[0325] Note that, although this embodiment mainly shows an example in which the conductive layer 260 does not overlap with the top surface of the conductive layer 240a and the top surface of the conductive layer 240b, the conductive layer 260 may have a portion overlapping with the top surface of the conductive layer 240a and a portion overlapping with the top surface of the conductive layer 240b. The smaller the overlapping portion, the smaller the parasitic capacitance generated between the conductive layer 260 and the conductive layer 240a and the parasitic capacitance generated between the conductive layer 260 and the conductive layer 240b, which is preferable. For example, the width of the opening 270 is preferably smaller than the width of the short side of the conductive layer 265 (the maximum width of the conductive layer 265 in FIG. 17(B)).

[0326] That is, the transistor 200B has a configuration in which the parasitic capacitance between the gate electrode and the other of the source electrode and the drain electrode and the parasitic capacitance between the gate wiring and the other of the source electrode and the drain electrode are reduced, thereby improving the frequency characteristics of a circuit using the transistor.

[0327] [Transistor 200C] FIG. 18(A) is a plan view of a semiconductor device including transistors 200Ca and 200Cb. FIG. 18(B) is a cross-sectional view taken along dashed line A1-A2 in FIG. 18(A). FIG. 18(C) is a cross-sectional view taken along dashed line A3-A4 in FIG. 18(A). FIG. 18(D) is a cross-sectional view taken along dashed line A5-A6 in FIG. 18(B). Note that in FIG. 18(A), the conductive layer 255 is hatched for clarity. In the following description, the transistors 200Ca and 200Cb may be collectively referred to as transistor 200C. FIG. 18(D) is also referred to as a plan view.

[0328] The semiconductor device shown in FIGS. 18(A) to 18(D) differs from the semiconductor device shown in FIGS. 1(A) to 2(D) in that the semiconductor device does not include a conductive layer 260 and an insulating layer 250 and includes an insulating layer 283.

[0329] In the transistors 200Ca and 200Cb, the conductive layer 255 functions as a gate electrode, and the insulating layer 225 functions as a gate insulating layer. The transistors 200Ca and 200Cb are single-gate transistors. Here, the conductive layer 255 has a region that functions as the wiring WOL shown in FIG. 2(E).

[0330] A barrier insulating layer against hydrogen is preferably used for the insulating layer 283. With such a structure, diffusion of hydrogen from above the transistor 200 to the oxide semiconductor layer 230 can be suppressed.

[0331] The insulating layer 283 may be made of an insulating material that can be used for the insulating layer 250.

[0332] Note that an insulating layer can be provided over the insulating layer 283 so as to fill the opening 290. The insulating layer can be formed using the insulators described in the above [Insulating Layer] in a single layer or a stacked layer.

[0333] By adopting a structure in which the conductive layer 260 is not provided, the manufacturing cost can be reduced. In addition, the area occupied by the semiconductor device can be reduced, and the semiconductor device can be miniaturized or highly integrated. On the other hand, by adopting a structure in which the conductive layer 260 is provided, a dual-gate transistor can be provided in the semiconductor device. This reduces, for example, the threshold voltage V th Therefore, the electrical characteristics of the transistor included in the semiconductor device can be improved.

[0334] [Transistor 200D] FIG. 19(A) is a plan view of a semiconductor device including transistors 200Da and 200Db. FIG. 19(B) is a cross-sectional view taken along dashed line A1-A2 in FIG. 19(A). FIG. 19(C) is a cross-sectional view taken along dashed line A3-A4 in FIG. 19(A). FIG. 19(D) is a cross-sectional view taken along dashed line A5-A6 in FIG. 19(B). Note that in FIG. 19(A), the conductive layer 260 is hatched for clarity. In the following description, the transistors 200Da and 200Db may be collectively referred to as the transistor 200D. FIG. 19(D) is also referred to as a plan view.

[0335] The semiconductor device shown in FIGS. 19A to 19D differs from the semiconductor device shown in FIGS. 1A to 2D in that the conductive layer 255 and the insulating layer 281 are not included.

[0336] In the transistors 200Da and 200Db, the conductive layer 260 functions as a gate electrode, and the insulating layer 250 functions as a gate insulating layer. The transistors 200Da and 200Db are single-gate transistors. Here, the conductive layer 260 has a region that functions as the wiring WOL shown in FIG. 2(E).

[0337] 19A to 19C show an example in which the conductive layer 260 is provided to extend in the X direction. Note that the conductive layer 260 may also be provided to extend in the Y direction, for example.

[0338] By not providing the conductive layer 255 and the insulating layer 281, the manufacturing cost of the semiconductor device can be reduced. In addition, the area occupied by the semiconductor device can be reduced, and the semiconductor device can be miniaturized or highly integrated. On the other hand, by providing the conductive layer 255 and the insulating layer 281, a dual-gate transistor can be provided in the semiconductor device. This reduces, for example, the threshold voltage V th Therefore, the electrical characteristics of the transistor included in the semiconductor device can be improved.

[0339] Note that the above-described structures of the transistor 200 can also be applied to the transistors 200A to 200D.

[0340] <Example of a method for manufacturing a semiconductor device> Next, a method for manufacturing a semiconductor device according to one embodiment of the present invention will be described. Note that with regard to materials and formation methods of elements, descriptions of parts that are the same as those described above may be omitted.

[0341] (A) in each figure shows a plan view, (B) in each figure shows a cross-sectional view corresponding to the portion indicated by the dashed line A1-A2 in (A) of each figure, and (C) in each figure shows a cross-sectional view corresponding to the portion indicated by the dashed line A3-A4 in (A) of each figure.

[0342] The thin films (insulating films, semiconductor films, conductive films, etc.) that make up semiconductor devices can be formed using methods such as sputtering, chemical vapor deposition (CVD), vacuum deposition, molecular beam epitaxy (MBE), pulsed laser deposition (PLD), and ALD.

[0343] Sputtering methods include RF sputtering, which uses a high-frequency power supply for sputtering; DC sputtering, which uses a direct current power supply; and pulsed DC sputtering, which changes the voltage applied to the electrode in a pulsed manner. RF sputtering is mainly used to deposit insulating films, while DC sputtering is mainly used to deposit metal conductive films. Pulsed DC sputtering is mainly used to deposit films of compounds such as oxides, nitrides, and carbides using reactive sputtering.

[0344] CVD methods can be further classified into plasma CVD (PECVD), which uses plasma, thermal CVD (TCVD: Thermal CVD), which uses heat, and photo CVD (Photo CVD), which uses light. They can also be further classified into metal CVD (MCVD: Metal CVD) and metal organic CVD (MOCVD: Metal Organic CVD), depending on the source gas used.

[0345] The plasma CVD method can produce high-quality films at relatively low temperatures. Furthermore, the thermal CVD method is a film formation method that does not use plasma and therefore can minimize plasma damage to the workpiece. For example, wiring, electrodes, elements (transistors, capacitors, etc.) included in a semiconductor device may become charged up by receiving electrical charge from the plasma. In this case, the accumulated electrical charge may destroy the wiring, electrodes, elements, etc. included in the semiconductor device. On the other hand, the thermal CVD method, which does not use plasma, does not cause such plasma damage, and therefore can increase the yield of semiconductor devices. Furthermore, the thermal CVD method produces films with fewer defects because no plasma damage occurs during film formation.

[0346] As the ALD method, a thermal ALD method in which a precursor and a reactant are reacted using only thermal energy, a PEALD method in which a plasma-excited reactant is used, or the like can be used.

[0347] Note that some precursors used in the ALD method contain elements such as carbon or chlorine. Therefore, films formed by the ALD method may contain larger amounts of elements such as carbon or chlorine than films formed by other film formation methods. The amounts of these elements can be quantified using XPS or SIMS. Note that the metal oxide film formation method of one embodiment of the present invention uses the ALD method, but employs a high substrate temperature during film formation and / or performs an impurity removal treatment. Therefore, the amount of carbon and chlorine contained in the film may be smaller than when the ALD method is used without these treatments.

[0348] Unlike film formation methods in which particles emitted from a target or the like are deposited, the ALD method is a film formation method in which a film is formed by a reaction on the surface of a workpiece. Therefore, it is a film formation method that is less affected by the shape of the workpiece and has good step coverage. In particular, the ALD method has excellent step coverage and excellent thickness uniformity, making it suitable for coating the surface of an opening with a high aspect ratio.

[0349] The CVD and ALD methods differ from sputtering, in which particles emitted from a target or the like are deposited. Therefore, they are film formation methods that are less affected by the shape of the workpiece and have good step coverage. In particular, the ALD method has excellent step coverage and excellent thickness uniformity, making it suitable for coating the surfaces of openings with high aspect ratios. However, because the ALD method has a relatively slow film formation rate, it may be preferable to use it in combination with other film formation methods, such as the CVD method, which has a faster film formation rate.

[0350] Furthermore, the CVD method allows for the deposition of a film with any desired composition by adjusting the flow rate ratio of the source gases. For example, the CVD method allows for the deposition of a film with a continuously changing composition by changing the flow rate ratio of the source gases during deposition. When depositing a film while changing the flow rate ratio of the source gases, the time required for film deposition can be shortened compared to when depositing a film using multiple deposition chambers, since no time is required for transport or pressure adjustment. Therefore, the productivity of semiconductor devices can be improved in some cases.

[0351] In addition, ALD allows the deposition of films with any desired composition by simultaneously introducing multiple different precursors, or by controlling the number of cycles of each precursor.

[0352] Furthermore, thin films (insulating films, semiconductor films, conductive films, etc.) constituting the semiconductor device can be formed by a wet film formation method such as spin coating, dip coating, spray coating, inkjet printing, dispensing, screen printing, offset printing, doctor knife method, slit coating, roll coating, curtain coating, or knife coating.

[0353] Furthermore, when processing a thin film that constitutes a semiconductor device, a photolithography method or the like can be used. Alternatively, the thin film may be processed by a nanoimprint method, a sandblasting method, a lift-off method, or the like. Furthermore, an island-shaped thin film may be directly formed by a film formation method using a shielding mask such as a metal mask.

[0354] There are two typical photolithography methods: One is to form a resist mask on the thin film to be processed, process the thin film by etching or the like, and then remove the resist mask. The other is to form a photosensitive thin film, and then process the thin film into the desired shape by exposure and development.

[0355] In photolithography, the light used for exposure can be, for example, i-line (wavelength 365 nm), g-line (wavelength 436 nm), h-line (wavelength 405 nm), or a mixture of these. Other light sources that can be used include ultraviolet light, KrF laser light, and ArF laser light. Exposure can also be performed by immersion exposure technology. Extreme ultraviolet (EUV) light or X-rays can also be used as the light used for exposure. An electron beam can also be used instead of the light used for exposure. Extreme ultraviolet light, X-rays, or an electron beam are preferred because they enable extremely fine processing. When exposure is performed by scanning a beam such as an electron beam, a photomask is not required.

[0356] For etching the thin film, dry etching, wet etching, sandblasting, or the like can be used.

[0357] An example of a method for manufacturing the semiconductor device shown in FIGS. 1A, 2A, and 2B will be described with reference to the drawings.

[0358] First, as shown in FIGS. 20(A), 20(B), and 20(C), an insulating layer 180 is formed over a substrate (not shown), and then a conductive layer 110 and an insulating layer 111 are formed over the insulating layer 180. For example, after the insulating layer 111 is formed over the insulating layer 180, an opening reaching the insulating layer 180 is formed in the insulating layer 111. Subsequently, a conductive film that will later become the conductive layer 110 is formed so as to fill the opening. After that, the conductive film is subjected to planarization treatment until the top surface of the insulating layer 111 is exposed. In this manner, the conductive layer 110 and the insulating layer 111 can be formed. Note that a chemical mechanical polishing (CMP) method (also referred to as a CMP treatment) is preferably used as the planarization treatment.

[0359] The conductive layer 110 may be formed by photolithography, in which case the insulating layer 111 does not need to be formed.

[0360] 21(A), 21(B), and 21(C), an insulating layer 160 is formed on the conductive layer 110 and the insulating layer 111. Then, as shown in FIGS. 21(A), 21(B), and 21(C), the insulating layer 160 is processed to form an opening 190 that reaches the conductive layer 110. Here, it is preferable to process the insulating layer 160 using anisotropic etching. In particular, processing by dry etching is preferable because it is suitable for fine processing.

[0361] 22(A), 22(B), and 22(C), a conductive film 115f, which will later become the conductive layer 115, is formed so as to cover the opening 190. The conductive film 115f is formed along the sidewall of the opening 190, the upper surface of the conductive layer 110, and the upper surface of the insulating layer 160.

[0362] Since the conductive film 115f is a layer provided in the opening 190, it is preferably formed by CVD or ALD, and more preferably by ALD, which allows the conductive film 115f to be formed with good coverage.

[0363] 23(A), 23(B), and 23(C), a mask layer 165 is applied onto the conductive film 115f. Thereafter, anisotropic etching is performed on the mask layer 165. As a result, the region of the mask layer 165 located outside the opening 190 is removed. For example, it is preferable to remove the region of the mask layer 165 located outside the opening 190 by dry etching. The mask layer 165 may be, for example, a resist mask, a SOC (Spin On Carbon) film, or a SOG (Spin On Glass) film.

[0364] 24(A), 24(B), and 24(C), the conductive film 115f is subjected to an etching process. As a result, the conductive layer 115 is formed in the opening 190. The etching process can be performed using a dry etching method or a wet etching method. In particular, processing by the dry etching method is preferable because it is suitable for fine processing.

[0365] Subsequently, the mask layer 165 is removed. The mask layer 165 can be removed by, for example, wet etching. Alternatively, the mask layer 165 may be removed by, for example, dry etching.

[0366] 25(A), 25(B), and 25(C), an insulating layer 121 is formed to cover the conductive layer 115, and a conductive film 120f, which will later become the conductive layers 120a and 120b, is formed on the insulating layer 121. The insulating layer 121 and the conductive film 120f are formed in an opening 190 with a large aspect ratio. Therefore, the insulating layer 121 and the conductive film 120f are preferably formed using a film formation method with good coverage, and more preferably, they are formed using a CVD method, an ALD method, or the like.

[0367] 26(A), 26(B), and 26(C), the conductive film 120f and the insulating layer 121 are processed. The conductive film 120f and the insulating layer 121 can be processed by photolithography. Here, it is preferable to process the conductive film 120f and the insulating layer 121 using the same photomask, since this reduces the number of steps compared to when different photomasks are used for processing. Note that the insulating layer 121 does not necessarily have to be processed.

[0368] 27(A), 27(B), and 27(C), the conductive film 120f is processed to form conductive layers 120a and 120b, thereby forming capacitors 100a and 100b.

[0369] Next, as shown in FIGS. 28(A), 28(B), and 28(C), an insulating layer 185 is formed to cover the capacitors 100a and 100b, and an insulating layer 186 is formed on the insulating layer 185. Specifically, the insulating layer 185 can be formed to cover the conductive layers 120a, 120b, and 121. The insulating layer 185 is formed along the side surfaces of the conductive layer 120a, the upper surface of the conductive layer 120a, the side surfaces of the conductive layer 120b, the upper surface of the conductive layer 120b, the side surfaces of the insulating layer 121, the upper surface of the insulating layer 121, and the upper surface of the insulating layer 160. The insulating layer 185 is formed to have a recess 187 at a position overlapping the opening 190. The insulating layer 186 is formed to fill the recess 187.

[0370] Since the insulating layers 185 and 186 are layers provided in the opening 190, they are preferably formed using a CVD method or an ALD method. For example, it is particularly preferable to form the insulating layer 185 formed along the side surfaces of the conductive layers 120a and 120b using an ALD method. It is also particularly preferable to form the insulating layer 186 formed so as to fill the opening 190 using a CVD method. Note that one or both of the insulating layers 185 and 186 may be formed using a sputtering method, for example. For example, the insulating layer 186 may be formed using a sputtering method.

[0371] 29(A), 29(B), and 29(C), the insulating layer 186 is subjected to a planarization process until the upper surface of the insulating layer 185 is exposed. CMP is a suitable method for the planarization process. Note that in FIG. 29(A), for clarity, hatching patterns are applied to the regions of the insulating layer 185 where the upper surface is exposed.

[0372] The planarization process may remove not only the insulating layer 186 but also a portion of the insulating layer 185. As a result, the film thickness in the region where the top surface of the insulating layer 185 is exposed may be thinner than the film thickness in other regions. Here, it is preferable to use a material for the insulating layer 185 that allows easy detection of the end point of the planarization process, since this can prevent a portion of the insulating layer 185 from being removed. For example, when silicon oxide is used for the insulating layer 186, silicon nitride can be used for the insulating layer 185.

[0373] By forming the insulating layer 186 so as to fill the recess 187 and planarizing the insulating layer 186, the transistors 200a and 200b can be formed more easily in a later step. For example, the conductive layer 220a, the conductive layer 220b, the oxide semiconductor layer 230a, the oxide semiconductor layer 230b, and the insulating layer 250, which will be formed in a later step, can be prevented from being divided by a step caused by the recess 187. This makes it possible to provide a method for manufacturing a semiconductor device with a high manufacturing yield.

[0374] 30(A), 30(B), and 30(C), an opening 191a reaching the conductive layer 120a and an opening 191b reaching the conductive layer 120b are formed in the insulating layer 185. Here, if the openings 191a and 191b are formed in a region where the upper surface of the insulating layer 185 is exposed, there is no need to process the insulating layer 186. Therefore, the openings 191a and 191b can be easily formed, which is preferable.

[0375] Thereafter, a conductive layer 161a is formed to fill the opening 191a, and a conductive layer 161b is formed to fill the opening 191b. For example, a conductive film that will later become the conductive layers 161a and 161b is formed on the conductive layer 120a, the conductive layer 120b, the insulating layer 185, and the insulating layer 186. Next, the conductive film is subjected to planarization treatment until the top surface of the insulating layer 186 is exposed. CMP treatment is suitable as the planarization treatment. In this manner, the conductive layers 161a and 161b can be formed. The conductive layer 161a is formed to be in contact with the conductive layer 120a, and the conductive layer 161b is formed to be in contact with the conductive layer 120b.

[0376] Next, as shown in FIGS. 31A, 31B, and 31C, a conductive layer 220a is formed on the conductive layer 161a, the insulating layer 185, and the insulating layer 186, and a conductive layer 220b is formed on the conductive layer 161b, the insulating layer 185, and the insulating layer 186. For example, a first conductive film that will later become the conductive layer 220a1 and the conductive layer 220b1 is formed, and a second conductive film that will later become the conductive layer 220a2 and the conductive layer 220b2 is formed on the first conductive film. Then, by processing the first conductive film and the second conductive film, a conductive layer 220a including the conductive layer 220a1 and the conductive layer 220a2 and a conductive layer 220b including the conductive layer 220b1 and the conductive layer 220b2 can be formed. The conductive layer 220a is formed so as to have a region in contact with the top surface of the conductive layer 161a. The conductive layer 220b is formed to have a region in contact with the upper surface of the conductive layer 161b.

[0377] 32(A), 32(B), and 32(C), an insulating layer 280 is formed over the conductive layer 220a, the conductive layer 220b, the insulating layer 185, and the insulating layer 186. After the insulating layer 280 is formed, it is preferable to perform planarization treatment using a CMP method or the like to planarize the top surface of the insulating layer 280. By performing the planarization treatment on the insulating layer 280, the surface on which the conductive layer 255, which functions as a wiring, is formed can be flattened, and discontinuity of the conductive layer 255 can be suppressed. Note that the planarization treatment is not necessarily performed, in which case the manufacturing cost can be reduced.

[0378] 32(A), 32(B), and 32(C), a conductive layer 255 is formed over the insulating layer 280. The conductive layer 255 is preferably formed by, for example, a sputtering method. By using a sputtering method that does not require the use of hydrogen-containing molecules in a deposition gas, the hydrogen concentration in the conductive layer 255 can be reduced, and entry of hydrogen into the oxide semiconductor layer 230 can be suppressed.

[0379] 33(A), 33(B), and 33(C), an insulating layer 281 is formed over the conductive layer 255 and the insulating layer 280. After the insulating layer 281 is formed, it is preferable to perform planarization treatment using a CMP method or the like to planarize the top surface of the insulating layer 281. By performing the planarization treatment on the insulating layer 281, the surfaces on which the conductive layers 240a and 240b are to be formed can be planarized, and discontinuities in the conductive layers 240a and 240b can be suppressed. Note that the planarization treatment does not have to be performed, in which case the manufacturing cost can be reduced.

[0380] Next, as shown in FIGS. 33(A), 33(B), and 33(C), a conductive film 240f1 is formed on the insulating layer 281, and a conductive film 240f2 is formed on the conductive film 240f1. The conductive film 240f1 is a conductive film that will later become the conductive layer 240a1 and the conductive layer 240b1. The conductive film 240f2 is a conductive film that will later become the conductive layer 240a2 and the conductive layer 240b2. Note that hereinafter, the conductive films 240f1 and 240f2 may be collectively referred to as the conductive film 240f.

[0381] Next, as shown in FIGS. 34(A), 34(B), and 34(C), openings 290 are formed in the conductive film 240f, the insulating layer 281, the conductive layer 255, and the insulating layer 280. The openings 290 are formed so as to expose at least a portion of the upper surfaces of the conductive layer 220a2, the conductive layer 220b2, and the insulating layer 186. At this time, recesses 221a and recesses 221b are preferably provided in the conductive layer 220a2 and the conductive layer 220b2, respectively, at positions overlapping with the openings 290. By forming the openings 290, it is preferable that the bottoms and sidewalls of the recesses 221a and recesses 221b are exposed. Furthermore, a recess 222 may be provided in the insulating layer 186 between the conductive layer 220a and the conductive layer 220b, at a position overlapping with the openings 290.

[0382] To achieve microfabrication and reduce the size of the transistor, it is preferable to use anisotropic etching to process parts of the conductive layer 220a2 and the conductive layer 220b2, parts of the insulating layer 280, parts of the conductive layer 255, and parts of the conductive film 240f when forming the opening 290. Dry etching is particularly preferable because it is suitable for microfabrication. The opening 290 may be formed under different processing conditions depending on the layer. Depending on the materials and processing conditions of conductive layer 220a2, conductive layer 220b2, insulating layer 280, conductive layer 255, insulating layer 281, conductive film 240f1, and conductive film 240f2, the slope of the side surfaces of conductive layer 220a2 and conductive layer 220b2, the slope of the side surfaces of insulating layer 280, the slope of the side surfaces of conductive layer 255, the slope of the side surfaces of insulating layer 281, the slope of the side surfaces of conductive film 240f1, and the slope of the side surfaces of conductive film 240f2 within opening 290 may differ from one another.

[0383] Furthermore, by a process for forming the opening 290 or the like, a region containing a halogen element may be provided in at least one of the bottom and sidewall of each of the recesses 221a and 221b, the side surface of the insulating layer 280, the side surface of the conductive layer 255, the side surface of the insulating layer 281, the side surface of the conductive film 240f1, and the top surface and side surface of the conductive film 240f2. Examples of such a region include a region containing fluorine, a region containing chlorine, or a region containing fluorine and chlorine. For example, a halogen element derived from the etching gas used in the dry etching may remain in such a region.

[0384] Subsequently, heat treatment is preferably carried out at a temperature of, for example, 250°C or higher and 650°C or lower, preferably 300°C or higher and 500°C or lower, and more preferably 320°C or higher and 450°C or lower.

[0385] The heat treatment is performed in a nitrogen gas or inert gas atmosphere, or an atmosphere containing an oxidizing gas at 10 ppm or more, 1% or more, or 10% or more. For example, when the heat treatment is performed in a mixed atmosphere of nitrogen gas and oxygen gas, the oxygen gas concentration is preferably about 20%. The heat treatment may be performed under reduced pressure. Alternatively, after the heat treatment in the nitrogen gas or inert gas atmosphere, the heat treatment may be performed in an atmosphere containing an oxidizing gas at 10 ppm or more, 1% or more, or 10% or more to compensate for the desorbed oxygen. By performing the above heat treatment, impurities such as hydrogen or water contained in the insulating layer 280 and the like can be reduced before the formation of the oxide semiconductor layer 230.

[0386] Furthermore, the gas used in the heat treatment is preferably highly purified. For example, the amount of moisture contained in the gas used in the heat treatment is preferably 1 ppb or less, more preferably 0.1 ppb or less, and even more preferably 0.05 ppb or less. By performing the heat treatment using a highly purified gas, it is possible to prevent moisture and the like from being absorbed into the insulating layer 280 and the like as much as possible.

[0387] 35(A), 35(B), and 35(C), an insulating film 225f, which will later become the insulating layer 225, is formed so as to cover the opening 290. The insulating film 225f is formed in contact with the exposed upper surface of the insulating layer 186 (the bottom and sidewalls of the recess 222 if the insulating layer 186 has a recess 222 at a position overlapping the opening 290), the bottoms and sidewalls of the recesses 221a and 221b, the side surfaces of the insulating layer 280, the side surfaces of the conductive layer 255, the side surfaces of the insulating layer 281, the side surfaces of the conductive film 240f1, and the upper surface and side surfaces of the conductive film 240f2.

[0388] Since the insulating film 225f is a layer provided inside the opening 290, it is preferably formed by CVD or ALD, and more preferably by ALD, which allows the insulating film 225f to be formed with good coverage.

[0389] In this embodiment, the insulating film 225f is formed by depositing a first insulating film and a second insulating film in this order using the ALD method. For example, a silicon nitride film is deposited as the first insulating film using the PEALD method, and a silicon oxide film is deposited as the second insulating film using the PEALD method. At this time, it is preferable to deposit the first insulating film and the second insulating film consecutively without exposing them to the atmosphere. By depositing the first insulating film and the second insulating film consecutively without exposing them to the atmosphere, it is possible to increase productivity. Furthermore, it is possible to reduce impurities (typically moisture, etc.) that are taken into the interface between the first insulating film and the second insulating film and the vicinity thereof.

[0390] 36(A), 36(B), and 36(C), the insulating film 225f is processed to expose the upper surface of the conductive film 240f2, and to expose the conductive layer 220a2, the conductive layer 220b2, and the insulating layer 186 in the opening 290. In the opening 290, it is preferable that the bottom of the recess 221a and the bottom of the recess 221b are exposed.

[0391] The insulating film 225f is processed by anisotropic etching, thereby removing a region of the insulating film 225f located on the upper surface of the conductive film 240f2 and a region located at the bottom of the opening 290. This allows the insulating film 225f to remain only on the side surfaces within the opening 290. In the opening 290, an insulating layer 225 is formed, which has, for example, a region in contact with the upper surface of the conductive layer 220a, a region in contact with the upper surface of the conductive layer 220b, a region in contact with the side surfaces of the insulating layer 280, a region in contact with the side surfaces of the conductive layer 255, a region in contact with the side surfaces of the insulating layer 281, a region in contact with the side surfaces of the conductive film 240f, a region in contact with the upper surface of the insulating layer 186, a region in contact with the side surfaces of the conductive layer 220a1, and a region in contact with the side surfaces of the conductive layer 220b1. The insulating film 225f is preferably processed by highly anisotropic etching using a dry etching method.

[0392] As described with reference to FIG. 6(B), when processing the insulating film 225f, a portion of the conductive layer 220a2 and the conductive layer 220b2 may be removed, and a recess (the first recess described above) may be formed in the conductive layer 220a2 and the conductive layer 220b2.

[0393] It is preferable to supply oxygen after the insulating film 225f is formed and before the insulating film 225f is processed (see FIGS. 35A to 35C). This allows oxygen to be supplied to the second insulating film, and oxygen can be supplied from the second insulating film to the oxide semiconductor layer 230 by heat or the like applied after the formation of the oxide semiconductor layer 230. Furthermore, providing the first insulating film having a barrier property against oxygen can suppress diffusion of oxygen into the conductive layer 220 and the conductive layer 240, thereby suppressing a decrease in the conductivity of the conductive layer 220 and the conductive layer 240. Therefore, the range of materials that can be selected for the conductive layer 220 and the conductive layer 240 can be expanded.

[0394] Alternatively, oxygen may be supplied after the insulating film 225f is processed (see FIGS. 36A to 36C). As a result, oxygen is supplied to the second insulating film, and oxygen can be supplied from the second insulating film to the oxide semiconductor layer 230 by heat or the like applied after the formation of the oxide semiconductor layer 230. Furthermore, by using an oxide conductor for the conductive layer 220a2, the conductive layer 220b2, and the conductive film 240f2, a decrease in the conductivity of the conductive layer 220a2, the conductive layer 220b2, and the conductive film 240f2 can be suppressed even in the case where oxygen is supplied after the second insulating film is processed.

[0395] Examples of the treatment for supplying oxygen include heat treatment in an oxygen-containing atmosphere or plasma treatment (including microwave plasma treatment) in an oxygen-containing atmosphere. Alternatively, oxygen may be supplied to the second insulating film by forming an oxide film (preferably a metal oxide film) in an oxygen-containing atmosphere by a sputtering method. The formed oxide film may be removed immediately or may be left as is. In the case where the formed oxide film is left as is, the oxide film can be used as part of the oxide semiconductor layer. Note that the oxygen-containing atmosphere includes not only oxygen gas (O2) but also atmospheres containing a gas of an oxygen-containing compound such as ozone (O3) or nitrous oxide (NO). The substrate temperature during the plasma treatment is set to be equal to or higher than room temperature (25°C) and equal to or lower than 450°C.

[0396] 37(A), 37(B), and 37(C), an oxide semiconductor film 230f, which will later become the oxide semiconductor layer 230a and the oxide semiconductor layer 230b, is formed to cover the opening 290. The oxide semiconductor film 230f is provided in contact with the bottom and sidewall of the recess 221a, the bottom and sidewall of the recess 221b, the exposed upper surface of the insulating layer 186, the side surface of the insulating layer 225, the side surface of the conductive film 240f1, and the upper surface and side surface of the conductive film 240f2.

[0397] The description in Embodiment 2 can be referred to for a method for forming the oxide semiconductor film 230f.

[0398] In this embodiment, a first oxide semiconductor film, a second oxide semiconductor film, and a third oxide semiconductor film are deposited in this order as the oxide semiconductor film 230f. The first oxide semiconductor film is an oxide semiconductor film that becomes the oxide semiconductor layer 230a1 and the oxide semiconductor layer 230b1 shown in FIG. 13B. The second oxide semiconductor film is an oxide semiconductor film that becomes the oxide semiconductor layer 230a2 and the oxide semiconductor layer 230b2 shown in FIG. 13B. The third oxide semiconductor film is an oxide semiconductor film that becomes the oxide semiconductor layer 230a3 and the oxide semiconductor layer 230b3 shown in FIG. 13B.

[0399] For example, an In-Ga-Zn oxide film is formed as the first oxide semiconductor film by thermal ALD, an indium oxide film is formed as the second oxide semiconductor film by thermal ALD, and an In-Ga-Zn oxide film is formed as the third oxide semiconductor film by sputtering.

[0400] Note that the first oxide semiconductor film and the second oxide semiconductor film are preferably formed successively without exposure to the air. By forming the first oxide semiconductor film and the second oxide semiconductor film successively without exposure to the air, productivity can be improved. Furthermore, impurities (typically, moisture, etc.) introduced into the interface between the first oxide semiconductor film and the second oxide semiconductor film and the vicinity thereof can be reduced.

[0401] After the second oxide semiconductor film is formed, oxygen may be supplied to the second oxide semiconductor film. In this way, oxygen can be supplied to the oxide semiconductor layer 230 by heat or the like applied after the process. Note that the above description can be referred to for details of the process of supplying oxygen.

[0402] Next, it is preferable to carry out a heat treatment. The temperature of the heat treatment is preferably from 100° C. to 650° C., more preferably from 250° C. to 600° C., and even more preferably from 350° C. to 550° C. For details of the heat treatment, see the above description.

[0403] The gas used in the heat treatment is preferably highly purified. When the heat treatment is performed using a highly purified gas, moisture and the like can be prevented from being introduced into the oxide semiconductor layer 230 as much as possible.

[0404] The heat treatment can reduce impurities such as carbon, hydrogen, or water in the oxide semiconductor layer 230. Reducing the impurities in the film in this manner improves the crystallinity of the oxide semiconductor layer 230, enabling the oxide semiconductor layer 230 to have a denser and more compact structure. This increases the number of crystalline regions in the oxide semiconductor layer 230, reducing in-plane variations in the crystalline regions in the oxide semiconductor layer 230. This reduces in-plane variations in the electrical characteristics of the transistor.

[0405] In addition, when the second insulating film of the insulating layer 225 contains oxygen, the heat treatment preferably supplies oxygen from the insulating film containing oxygen to the channel formation region of the oxide semiconductor layer 230. This reduces oxygen vacancies and V O H can be reduced.

[0406] In this manner, excess oxygen may be supplied to the oxide semiconductor layer 230 from an insulating layer in contact with the oxide semiconductor layer 230. The excess oxygen has a function of trapping electrons, which makes it easier for negative charges to be generated. Therefore, the threshold voltage of the transistor is shifted in the positive direction, and a normally-off transistor can be realized.

[0407] Note that microwave plasma treatment may be performed after the second oxide semiconductor film or the third oxide semiconductor film is formed. By performing the microwave plasma treatment, the concentration of impurities such as hydrogen or water contained in the oxide semiconductor layer 230 can be reduced. Furthermore, a crystalline region of the oxide semiconductor layer 230 may grow. Note that details of the microwave plasma treatment will be described in Embodiment 2.

[0408] 38(A), 38(B), and 38(C), the oxide semiconductor film 230f is processed into an island shape to expose part of the top surface of the conductive film 240f2 and part of the top surface of the insulating layer 186 at positions overlapping with the openings 290. By this processing, the oxide semiconductor layers 230a and 230b are formed.

[0409] 38(A) to 38(C), the above processing is preferably performed so that only the upper surface of the insulating layer 186 and the insulating layer 225 are exposed in the opening 290. In other words, the above processing is preferably performed so that the conductive layer 220a and the conductive layer 220b are not exposed in the opening 290. In this way, the base film in the above processing is only the insulating layer 186, which makes it relatively easy to process the oxide semiconductor film 230f.

[0410] Cleaning treatment is preferably performed to remove impurities and the like attached to the surface of the oxide semiconductor layer 230 during the above processing. Examples of cleaning methods include wet cleaning using a cleaning solution or the like (which can also be called wet etching treatment), plasma treatment using plasma, and cleaning by heat treatment. These cleaning methods may be used in combination as appropriate.

[0411] Wet cleaning may be performed using an aqueous solution prepared by diluting one or more of ammonia water, oxalic acid, phosphoric acid, and hydrofluoric acid with pure water or carbonated water. Wet cleaning may also be performed using pure water, carbonated water, or the like. Alternatively, ultrasonic cleaning may be performed using these aqueous solutions, pure water, or carbonated water. Alternatively, these cleaning methods may be combined as appropriate.

[0412] In this specification, an aqueous solution of hydrofluoric acid diluted with pure water or carbonated water may be referred to as "diluted hydrofluoric acid," and an aqueous solution of ammonia water diluted with pure water may be referred to as "diluted ammonia water." The concentration or temperature of the aqueous solution may be adjusted appropriately depending on the impurities to be removed and the configuration of the semiconductor device to be cleaned. The ammonia concentration of the diluted ammonia water is preferably 0.01% or more and 5% or less, and more preferably 0.1% or more and 0.5% or less. The hydrogen fluoride concentration of the diluted hydrofluoric acid is preferably 0.01 ppm or more and 100 ppm or less, and more preferably 0.1 ppm or more and 10 ppm or less.

[0413] The ultrasonic cleaning is preferably performed at a frequency of 200 kHz or higher, more preferably 900 kHz or higher, which can reduce damage to the oxide semiconductor layer 230 and the like.

[0414] The cleaning process may be repeated multiple times, and the cleaning solution may be changed for each cleaning process. For example, a first cleaning process may be performed using diluted hydrofluoric acid or diluted ammonia water, and a second cleaning process may be performed using pure water or carbonated water.

[0415] 39(A), 39(B), and 39(C), the conductive film 240f is processed to form the conductive layer 240a (conductive layer 240a1 and conductive layer 240a2) and the conductive layer 240b (conductive layer 240b1 and conductive layer 240b2). Specifically, the conductive layer 240a2 and the conductive layer 240b2 are formed from the conductive film 240f2, and the conductive layer 240a1 and the conductive layer 240b1 are formed from the conductive film 240f1.

[0416] 40(A), 40(B), and 40(C), an insulating layer 250 is formed to cover the opening 290. The insulating layer 250 is provided in contact with the oxide semiconductor layer 230. The insulating layer 250 is formed in the opening 290, which has a large aspect ratio. Therefore, the insulating layer 250 is preferably formed using a film formation method with good coverage, and more preferably formed using a CVD method, an ALD method, or the like.

[0417] Microwave plasma treatment is preferably performed after the insulating layer 250 is formed. By performing the microwave plasma treatment, the concentration of impurities such as hydrogen or water in the oxide semiconductor layer 230 can be reduced. Furthermore, a crystalline region of the oxide semiconductor layer 230 might grow. Details of the microwave plasma treatment will be described in Embodiment 2.

[0418] When insulating layer 250 has a four-layer structure including a fourth insulating layer, a third insulating layer on the fourth insulating layer, a first insulating layer on the third insulating layer, and a second insulating layer on the first insulating layer, microwave plasma treatment may be performed after the third insulating layer is formed. Furthermore, microwave plasma treatment may be performed again after the first insulating layer is formed. Thus, microwave plasma treatment in an oxygen-containing atmosphere may be performed multiple times (at least twice or more).

[0419] After the third insulating layer is formed, oxygen may be supplied to the third insulating layer, thereby enabling oxygen to be supplied to the oxide semiconductor layer 230. Note that the above description can be referred to for details of the process of supplying oxygen.

[0420] In this embodiment, the insulating layer 250 is formed by depositing an aluminum oxide film, a silicon oxide film, a hafnium oxide film, and a silicon nitride film in this order using the ALD method.

[0421] 41(A), 41(B), and 41(C), a conductive layer 260 is formed on the insulating layer 250. The conductive layer 260 is preferably provided so as to fill the opening 290.

[0422] The conductive layer 260 is formed in the opening 290, which has a large aspect ratio. Therefore, the conductive layer 260 is preferably formed using a film formation method with good coverage, and more preferably, using a CVD method, an ALD method, or the like.

[0423] Through the above steps, a semiconductor device of one embodiment of the present invention can be manufactured.

[0424] This embodiment mode can be combined with other embodiment modes as appropriate. In addition, in this specification, when a plurality of configuration examples are shown in one embodiment mode, the configuration examples can be combined as appropriate.

[0425] (Embodiment 2) In this embodiment, an oxide semiconductor layer that can be used as a semiconductor layer of a transistor will be described. As the oxide semiconductor layer of one embodiment of the present invention, a layer containing a metal oxide can be used as a single layer or a stacked layer. Note that in an oxide semiconductor layer with a stacked structure, it may be difficult to identify boundaries between stacked films, as will be described later.

[0426] [Metal oxides] The metal oxide according to one embodiment of the present invention preferably contains at least indium (In) or zinc (Zn), and particularly preferably contains indium as the main component. The metal oxide preferably contains two or three elements selected from indium, element M, and zinc, and particularly preferably contains indium and zinc as the main components. Here, the metal oxide may contain indium and zinc as the main components and may further contain element M. The element M is a metal element or a metalloid element having a high bond energy with oxygen, for example, a metal element or a metalloid element having a bond energy with oxygen higher than that of indium. Specific examples of element M include aluminum, gallium, tin, yttrium, titanium, vanadium, chromium, manganese, iron, cobalt, nickel, zirconium, molybdenum, hafnium, tantalum, tungsten, lanthanum, cerium, neodymium, magnesium, calcium, strontium, barium, boron, silicon, germanium, and antimony. The element M contained in the metal oxide is preferably one or more of the above elements, more preferably one or more selected from aluminum, gallium, tin, and yttrium, and even more preferably one or more selected from gallium and tin. When the element M contained in the metal oxide is gallium, the metal oxide according to one embodiment of the present invention preferably contains one or more selected from indium, gallium, and zinc. In this specification and the like, metal elements and metalloid elements may be collectively referred to as "metal elements," and the "metal element" described in this specification and the like may also include metalloid elements.

[0427] Examples of metal oxides according to one embodiment of the present invention include indium zinc oxide (In-Zn oxide, also referred to as IZO (registered trademark)), indium tin oxide (In-Sn oxide, also referred to as ITO), indium titanium oxide (In-Ti oxide), indium gallium oxide (In-Ga oxide), indium gallium aluminum oxide (In-Ga-Al oxide), indium gallium tin oxide (In-Ga-Sn oxide, also referred to as IGTO), and indium aluminum zinc oxide (In-Al-Zn oxide, IA). Examples of usable metal oxides include indium tin zinc oxide (In-Sn-Zn oxide), indium titanium zinc oxide (In-Ti-Zn oxide), indium gallium zinc oxide (In-Ga-Zn oxide, also referred to as IGZO), silicon-containing indium tin oxide (ITSO), indium gallium tin zinc oxide (In-Ga-Sn-Zn oxide, also referred to as IGZTO), and indium gallium aluminum zinc oxide (In-Ga-Al-Zn oxide, also referred to as IGAZO or IAGZO). Alternatively, examples of usable metal oxides include gallium zinc oxide (Ga-Zn oxide, also referred to as GZO), aluminum zinc oxide (Al-Zn oxide, also referred to as AZO), gallium tin oxide (Ga-Sn oxide), and aluminum tin oxide (Al-Sn oxide). Indium oxide can be used as a metal oxide according to one embodiment of the present invention. Gallium oxide, zinc oxide, and the like can be used as a metal oxide according to one embodiment of the present invention.

[0428] By increasing the content of indium in the metal oxide, the transistor can have a large on-state current and high frequency characteristics.

[0429] Note that the metal oxide may contain one or more metal elements with higher period numbers in the periodic table instead of indium. Alternatively, the metal oxide may contain one or more metal elements with higher period numbers in the periodic table in addition to indium. The greater the overlap of the orbitals of metal elements, the greater the carrier conduction in the metal oxide tends to be. Therefore, including a metal element with a higher period number in the periodic table may improve the field-effect mobility of a transistor. Examples of metal elements with higher period numbers in the periodic table include metal elements belonging to the fifth period and the sixth period. Specific examples of such metal elements include yttrium, zirconium, silver, cadmium, tin, antimony, barium, lead, bismuth, lanthanum, cerium, praseodymium, neodymium, promethium, samarium, and europium. Note that lanthanum, cerium, praseodymium, neodymium, promethium, samarium, and europium are called light rare earth elements.

[0430] The metal oxide may contain one or more nonmetallic elements, which may increase the field-effect mobility of the transistor. Examples of nonmetallic elements include carbon, nitrogen, phosphorus, sulfur, selenium, fluorine, chlorine, bromine, and hydrogen.

[0431] Furthermore, by increasing the zinc content in the metal oxide, the metal oxide can be made highly crystalline, which can suppress the diffusion of impurities in the metal oxide, thereby suppressing fluctuations in the electrical characteristics of the transistor and improving its reliability.

[0432] Furthermore, by increasing the content of element M in the metal oxide, the formation of oxygen vacancies in the metal oxide can be suppressed. Therefore, carrier generation due to oxygen vacancies is suppressed, and a transistor with a small off-state current can be obtained. Furthermore, fluctuations in the electrical characteristics of the transistor can be suppressed, and reliability can be improved.

[0433] A structural example of an oxide semiconductor layer capable of increasing the field-effect mobility of a transistor will be described. For example, a stacked structure of indium oxide and IGZO is preferably used. Specifically, the oxide semiconductor layer preferably includes indium oxide and IGZO on the indium oxide. Furthermore, it is preferable to use IGZO containing nitrogen as the oxide semiconductor layer. For example, IGZO containing nitrogen can be formed by performing NO plasma treatment during or after film formation. Furthermore, it is preferable to use at least one of indium oxide, In-Ga oxide, In-Zn oxide, and IGZTO as the oxide semiconductor layer.

[0434] In the present embodiment, an In-M-Zn oxide may be used as an example of the metal oxide.

[0435] The oxide semiconductor layer of one embodiment of the present invention preferably contains a crystalline metal oxide. Examples of the structure of a crystalline metal oxide include a c-axis aligned crystal (CAAC) structure, a polycrystalline (polycrystal) structure, and a nanocrystalline (nc) structure. By using a crystalline metal oxide for the oxide semiconductor layer, the density of defect states in the oxide semiconductor layer can be reduced. Therefore, the reliability of a transistor including the oxide semiconductor layer of one embodiment of the present invention can be improved, and the reliability of a semiconductor device including the transistor can be improved.

[0436] Note that the crystallinity of the metal oxide contained in the oxide semiconductor layer is not particularly limited. For example, the oxide semiconductor layer may contain one or more of an amorphous semiconductor (a semiconductor having an amorphous structure), a single-crystal semiconductor (a semiconductor having a single-crystal structure), or a semiconductor having crystallinity other than single crystal (a microcrystalline semiconductor, a polycrystalline semiconductor, or a semiconductor having a crystalline region in part). When the oxide semiconductor layer has crystallinity, deterioration of transistor characteristics can be suppressed in some cases.

[0437] The crystallinity of the oxide semiconductor layer can be analyzed by, for example, X-ray diffraction (XRD), transmission electron microscopy (TEM), or electron diffraction (ED), or a combination of these techniques may be used for the analysis.

[0438] The oxide semiconductor layer of one embodiment of the present invention preferably includes a metal oxide having a CAAC structure. The CAAC structure is a crystal structure in which a plurality of microcrystals (typically, a plurality of microcrystals having a hexagonal crystal structure) have c-axis orientation and are connected without being aligned in the ab-plane. Furthermore, when a cross section of an oxide semiconductor layer having a CAAC structure is observed using a high-resolution TEM image (also referred to as a multi-beam interference image), it can be confirmed that metal atoms are arranged in a layered manner in the crystal parts. Therefore, an oxide semiconductor layer having a CAAC structure can also be said to have a structure having layered crystal parts.

[0439] For example, the CAAC structure is formed so that the c-axis is perpendicular or approximately perpendicular to the surface or surface of the oxide semiconductor layer on which the oxide semiconductor layer is formed. In the CAAC structure, metal atoms are arranged in layers parallel or approximately parallel to the surface on which the oxide semiconductor layer is formed. In the region having the CAAC structure, the c-axis is preferably within 90°±20° (70° to 110°), more preferably within 90°±15° (75° to 105°), more preferably within 90°±10° (80° to 100°), and even more preferably within 90°±5° (85° to 95°) relative to the surface on which the oxide semiconductor layer is formed.

[0440] When the oxide semiconductor layer has a CAAC structure, bright spots (specifically, bright spots arranged in layers) reflecting the layered arrangement of metal atoms are observed in a cross section of the oxide semiconductor layer observed using a TEM image. Specifically, bright spots are observed to be arranged in layers parallel or approximately parallel to the surface on which the oxide semiconductor layer is formed.

[0441] When electron diffraction is performed on an oxide semiconductor layer having a CAAC structure, spots (bright points) indicating c-axis orientation are observed in the electron diffraction pattern.

[0442] Furthermore, an FFT pattern obtained by subjecting a TEM image to a fast Fourier transform (FFT) process reflects reciprocal lattice spatial information similar to that of an electron diffraction pattern.

[0443] A cross-sectional TEM image of an oxide semiconductor layer having a CAAC structure is acquired, and an FFT pattern is created by performing FFT processing on each region in the cross-sectional TEM image. The crystal axis direction of each region can be calculated from the created FFT pattern. Specifically, the direction of the line segment connecting two spots with high brightness and located at approximately equal distances from the center is defined as the crystal axis direction. Regions whose crystal axis direction calculated from the FFT pattern is preferably 70° to 110° (within 90°±20°) relative to the surface to be formed, more preferably 75° to 105° (within 90°±15°), more preferably 80° to 100° (within 90°±10°), and even more preferably 85° to 95° (within 90°±5°) can be considered to have a CAAC structure.

[0444] When an oxide semiconductor layer having a CAAC structure is viewed in a direction perpendicular to the surface on which it is formed using a TEM image, a triangular or hexagonal atomic arrangement is observed in the ab plane, and the oxide semiconductor layer has crystallinity.

[0445] [Metal oxide composition] The metal oxide according to one embodiment of the present invention preferably contains indium (In), and more preferably has a high In content. By using a metal oxide with a high In content for the oxide semiconductor layer, the on-state current of a transistor can be increased and frequency characteristics can be improved. For example, indium oxide is preferably used for the oxide semiconductor layer.

[0446] Furthermore, the metal oxide according to one embodiment of the present invention may contain zinc. When the metal oxide contains zinc, it becomes a metal oxide with high crystallinity, for example, a metal oxide having a CAAC structure. For example, an In-Zn oxide can be used for the oxide semiconductor layer. Specifically, a metal oxide having a composition of In:Zn=1:1 (atomic ratio) or a composition close to that, an In:Zn=2:1 (atomic ratio) or a composition close to that, or an In:Zn=4:1 (atomic ratio) or a composition close to that can be used. Note that a composition close to that includes a range of ±30% of the desired atomic ratio.

[0447] Furthermore, the metal oxide according to one embodiment of the present invention can contain an element M. When the metal oxide contains the element M, oxygen vacancies can be prevented from being formed in the metal oxide. Therefore, the reliability of a transistor including an oxide semiconductor layer can be improved.

[0448] For example, the oxide semiconductor layer can be made of an In-Zn oxide containing a trace amount of element M. Specifically, metal oxides having an atomic ratio of In:Ga:Zn=4:0.1:1 or a similar ratio, an atomic ratio of In:Ga:Zn=2:0.1:1 or a similar ratio, or an atomic ratio of In:Ga:Zn=1:0.1:1 or a similar ratio can be used. Furthermore, metal oxides having an atomic ratio of In:Sn:Zn=4:0.1:1 or a similar ratio, an atomic ratio of In:Sn:Zn=2:0.1:1 or a similar ratio, or an atomic ratio of In:Sn:Zn=1:0.1:1 or a similar ratio can be used.

[0449] The oxide semiconductor layer can be made of an In-Zn oxide containing an element M. Specifically, metal oxides having a composition of In:M:Zn=1:1:1 (atomic ratio) or a composition close thereto, In:M:Zn=1:1:1.2 (atomic ratio) or a composition close thereto, In:M:Zn=1:1:0.5 (atomic ratio) or a composition close thereto, In:M:Zn=1:1:2 (atomic ratio) or a composition close thereto, In:M:Zn=4:2:3 (atomic ratio) or a composition close thereto, In:M:Zn=1:3:2 (atomic ratio) or a composition close thereto, or In:M:Zn=1:3:4 (atomic ratio) or a composition close thereto can be used.

[0450] When a metal oxide is formed by sputtering, the composition of the formed metal oxide may differ from that of the sputtering target. In particular, the zinc content in the formed metal oxide may decrease to about 50% of that in the sputtering target.

[0451] Furthermore, when forming a metal oxide film containing multiple metal elements, such as In-Ga-Zn oxide, using atomic layer deposition (ALD), the ratio of the number of cycles of precursors containing each metal element can be adjusted to match the target composition. For example, to form an In-Ga-Zn oxide film with an atomic ratio of In:Ga:Zn=1:3:2, one cycle of forming an In-containing precursor and treating it with an oxidizing agent can be performed, three cycles of forming a Ga-containing precursor and treating it with an oxidizing agent can be performed, and two cycles of forming a Zn-containing precursor and treating it with an oxidizing agent can be performed. However, the ratio of the number of cycles of precursors containing each metal element and the atomic ratio of each metal element in the formed metal oxide film may not match.

[0452] The composition of the metal oxide used in the oxide semiconductor layer can be analyzed by, for example, energy dispersive X-ray spectroscopy (EDX), XPS, inductively coupled plasma-mass spectrometry (ICP-MS), or inductively coupled plasma-atomic emission spectrometry (ICP-AES). Alternatively, a combination of these techniques may be used for the analysis. Note that for elements with low content, the actual content may differ from the content obtained by analysis due to the influence of analytical accuracy. For example, when the content of element M is low, the content of element M obtained by analysis may be lower than the actual content, the content of element M may be difficult to quantify, or the content may be below the detection limit of element M.

[0453] The oxide semiconductor layer of one embodiment of the present invention may have a stacked structure of two or more layers. When the oxide semiconductor layer has a two-layer structure of a first layer and a second layer over the first layer, the second layer preferably has a different composition from the first layer. When the oxide semiconductor layer has a three-layer structure of a first layer, a second layer over the first layer, and a third layer over the second layer, the second layer preferably has a different composition from the first layer and the third layer. Note that the first layer can have the same composition as the third layer. Alternatively, the first layer and the third layer can have different compositions.

[0454] The first to third layers may each be made of the metal oxides described above.

[0455] The second layer can be made of, for example, indium oxide, In-Zn oxide, or In-Zn oxide containing a trace amount of element M. Specifically, metal oxides having an In:Zn=1:1 atomic ratio or a similar composition, an In:Zn=2:1 atomic ratio or a similar composition, or an In:Zn=4:1 atomic ratio or a similar composition can be used. For example, metal oxides having an In:Ga:Zn=4:0.1:1 atomic ratio or a similar composition, an In:Ga:Zn=2:0.1:1 atomic ratio or a similar composition, or an In:Ga:Zn=1:0.1:1 atomic ratio or a similar composition can be used. Alternatively, for example, a metal oxide having an atomic ratio of In:Sn:Zn=4:0.1:1 or a similar composition, an atomic ratio of In:Sn:Zn=2:0.1:1 or a similar composition, or an atomic ratio of In:Sn:Zn=1:0.1:1 or a similar composition can be used. Increasing the In content in the second layer can increase the on-current and improve the frequency characteristics.

[0456] The conduction band minimums of the first and third layers are preferably located closer to the vacuum level than the conduction band minimum of the second layer. In other words, the energy of the conduction band minimum of the first and third layers is preferably lower than the energy of the conduction band minimum of the second layer. In this case, the second layer is sandwiched between the first and third layers, whose conduction band minimums are located closer to the vacuum level, and can function mainly as a current path (channel).

[0457] By sandwiching the second layer between the first layer and the third layer, carriers trapped at the interface of the second layer and its vicinity can be reduced. Furthermore, the channel can be distanced from the surface of the gate insulating layer, thereby reducing the influence of surface scattering. This allows a buried-channel transistor in which the channel is distanced from the insulating layer interface to be realized, thereby increasing field-effect mobility. Furthermore, the influence of interface states that may be formed on the back gate electrode side (also referred to as the back channel side) of the oxide semiconductor layer can be reduced, thereby suppressing light degradation (e.g., negative bias light degradation) of the transistor and improving the reliability of the transistor.

[0458] For example, a band diagram of the oxide semiconductor layer 230a including the oxide semiconductor layers 230a1 to 230a3 and their vicinity, which is shown in FIG. 13B, is as shown in FIG. 42. In FIG. 42, the vertical axis represents energy, and the horizontal axis represents the film thickness direction at the center of the channel formation region. FIG. 42 shows the valence band maximum (VBM) and the conduction band minimum (CBM) of each of the oxide semiconductor layer 230a1, the oxide semiconductor layer 230a2, the oxide semiconductor layer 230a3, the insulating layer 225, and the insulating layer 250 when no voltage is applied between the gate and the source. In FIG. 42, the vacuum level Vac is indicated by a dashed line.

[0459] Note that the energy of the upper end of the valence band and the energy of the lower end of the conduction band vary depending on the constituent elements and compositions of the oxide semiconductor layer 230a1, the oxide semiconductor layer 230a2, the oxide semiconductor layer 230a3, the insulating layer 225, and the insulating layer 250. Therefore, the relationship in height between the upper ends of the valence bands and the relationship in height between the lower ends of the conduction bands will be mainly described using the band diagram in FIG. 42.

[0460] Depending on the constituent elements and compositions of the oxide semiconductor layers 230a1 to 230a3, the oxide semiconductor layer 230a2 may be sandwiched between the oxide semiconductor layers 230a1 and 230a3, whose conduction band minimums are closer to the vacuum level than the oxide semiconductor layer 230a2, as shown in FIG. 42. This structure can realize a buried channel. That is, this structure forms a path through which more current (electrons are illustrated as carriers in FIG. 42) flows in the oxide semiconductor layer 230a2. Therefore, an increase in on-state current, improvement in reliability, and the like can be achieved.

[0461] When forming a buried channel using the first to third layers, for example, the first and third layers can be made of a metal oxide with a higher Ga content than the second layer. Specifically, the first and third layers can be made of a metal oxide with an In:Ga:Zn=1:1:1 atomic ratio or a composition similar thereto, a metal oxide with an In:Ga:Zn=1:3:2 atomic ratio or a composition similar thereto, or a metal oxide with an In:Ga:Zn=1:3:4 atomic ratio or a composition similar thereto. Alternatively, Ga-Zn oxide or gallium oxide can be used. Increasing the Ga content of the first and third layers can position the conduction band minimum of each of the first and third layers closer to the vacuum level than the conduction band minimum of the second layer.

[0462] Furthermore, increasing the Ga content in the first layer and the third layer can improve the barrier properties of the first layer and the third layer against hydrogen. Therefore, hydrogen diffusion from below the first layer or above the third layer to the second layer can be suppressed. Furthermore, increasing the Ga content in the first layer and the third layer can reduce impurities such as hydrogen or water contained in the oxide semiconductor layer due to heat or the like applied after the formation of the oxide semiconductor layer. Note that the same effect may be achieved by using a metal oxide with a lower In content than the second layer for the first layer and the third layer.

[0463] For example, the third layer preferably uses a metal oxide having an atomic ratio of In:Ga:Zn=1:1:1 or a similar composition, an atomic ratio of In:Ga:Zn=1:3:2 or a similar composition, or an atomic ratio of In:Ga:Zn=1:3:4 or a similar composition, and the third layer contains indium and gallium.

[0464] Furthermore, increasing the Ga content in the first and third layers can improve the oxygen barrier properties of the first and third layers. This can suppress oxygen release from the second layer where the channel is formed, and can suppress the formation of oxygen vacancies in the second layer or an increase in the amount of oxygen vacancies in the second layer. This can improve the electrical characteristics of the transistor.

[0465] Furthermore, by increasing the Ga content in the first layer, the resistivity of the first layer can be made higher than that of the second layer in some cases. When the first layer is provided on the back channel side, providing a layer with high resistivity as the first layer can suppress a negative shift in threshold voltage or a decrease in on-current. Therefore, the threshold voltage of the transistor is shifted positively, and the transistor can be made normally off. As a result, the electrical characteristics of the transistor can be improved, and the reliability of the transistor can be improved.

[0466] The band gap of metal oxides can be evaluated by optical evaluation using a spectrophotometer, spectroscopic ellipsometry, photoluminescence, X-ray photoelectron spectroscopy, or X-ray absorption fine structure (XAFS). Furthermore, a combination of these techniques can be used for analysis. The electron affinity or the bottom of the conduction band can be determined from the ionization potential, which is the energy difference between the vacuum level and the top of the valence band, and the band gap. The ionization potential can be evaluated, for example, by ultraviolet photoelectron spectroscopy (UPS).

[0467] The first layer and the third layer may be made of a metal oxide having a higher In content than the second layer. Alternatively, one of the first layer and the third layer may be made of a metal oxide having a higher In content than the second layer, and the other may be made of a metal oxide having a higher Ga content than the second layer.

[0468] The first, second, and third layers may each be formed by stacking multiple layers having the compositions described above. For example, the first layer may be formed by stacking a metal oxide having a high In content on a metal oxide having a high Ga content. For example, the third layer may be formed by stacking a metal oxide having a high Ga content on a metal oxide having a high In content.

[0469] [Method for producing oxide semiconductor layer] The oxide semiconductor layer of one embodiment of the present invention can be formed by a sputtering method, a chemical vapor deposition (CVD) method, a vacuum evaporation method, a molecular beam epitaxy (MBE) method, a pulsed laser deposition (PLD) method, an ALD method, or the like.

[0470] The oxide semiconductor layer of one embodiment of the present invention can be manufactured by forming a metal oxide by two different deposition methods. For example, the oxide semiconductor layer of one embodiment of the present invention can be manufactured by forming a metal oxide by a first deposition method and a second deposition method.

[0471] The oxide semiconductor layer of one embodiment of the present invention can have a two-layer structure including a first layer and a second layer over the first layer. In the case where the oxide semiconductor layer has a two-layer structure, the oxide semiconductor layer can be manufactured by forming the first layer over a surface to be formed by a first film formation method and then forming the second layer thereover by a second film formation method.

[0472] The first deposition method is preferably a deposition method that causes less damage to the surface on which the oxide semiconductor layer is formed than the second deposition method. This can prevent a mixed layer from being formed at the interface between the oxide semiconductor layer and the layer on which the oxide semiconductor layer is formed. Furthermore, impurities such as silicon can be prevented from being mixed into the second layer formed on the first layer, which may improve the crystallinity of the oxide semiconductor layer.

[0473] Examples of the first film formation method include the ALD method, the CVD method, and the MBE method. Examples of the CVD method include the plasma enhanced CVD (PECVD), the thermal CVD method, the photo-CVD method, and the MOCVD method. The MBE method is a film formation method that grows a thin film with a crystalline structure that reflects the crystalline system of the substrate, and can be said to be one of the film formation methods that causes little damage to the surface on which the film is formed. Also, a wet method can be used as the first film formation method. The wet method is one of the film formation methods that causes little damage to the surface on which the film is formed. Examples of the wet method include the spray coating method.

[0474] The second film formation method is preferably a method capable of forming a crystalline metal oxide film. It is particularly preferable that the metal oxide film formed in this case has a CAAC structure. Examples of the second film formation method include a sputtering method and a PLD method. Since a metal oxide film formed by a sputtering method is likely to have crystallinity, a sputtering method is suitable as the second film formation method.

[0475] When a metal oxide is formed on a surface to be formed using the second film formation method, damage to the surface to be formed may cause alloying between components contained in the metal oxide and components contained in the layer on the surface to be formed. This alloying may result in the formation of a mixed layer at the interface between the metal oxide and the layer on the surface to be formed. This mixed layer may also be referred to as an alloyed region. The formation of the mixed layer may also be referred to as alloying.

[0476] For example, when a sputtering method is used as the second film formation method, a mixed layer may be formed by particles (also referred to as sputtering particles) emitted from a target or the like, or energy imparted to a substrate by the sputtering particles or the like. Specifically, when a metal oxide film is formed by the second film formation method using a silicon-containing insulating layer, such as a silicon oxide film, as a formation surface, silicon may be mixed into the metal oxide. There is a concern that the crystallization of the metal oxide may be inhibited by the inclusion of impurities such as silicon in the metal oxide. Furthermore, there is a concern that the use of an oxide semiconductor layer containing impurities in a transistor may adversely affect the initial characteristics or reliability of the transistor. Furthermore, even when heat treatment, which will be described later, is performed, it is difficult to improve the crystallinity of the alloyed region.

[0477] Therefore, as described above, by forming a metal oxide by the first film formation method before forming a metal oxide by the second film formation method, it is possible to prevent impurities from being mixed into the oxide semiconductor layer. Furthermore, it is possible to prevent alloying with the layer on which the metal oxide is to be formed. Therefore, it is possible to improve the initial characteristics and reliability of the transistor. Furthermore, it is possible to further increase the crystallinity of the oxide semiconductor layer.

[0478] A mixed layer may be formed at the interface between the first layer and the second layer. The mixed layer contains the components contained in the first layer and the components contained in the second layer. For example, when gallium oxide is used for the first layer and a metal oxide containing indium is used for the second layer, the mixed layer contains gallium and indium. Furthermore, when the indium content of the second layer is higher than that of the first layer, the indium content of the mixed layer is equal to or greater than that of the first layer and equal to or less than that of the second layer.

[0479] The ALD method is suitable as the first film formation method because it can suppress damage to the surface to be formed compared to the sputtering method. Furthermore, the ALD method is a film formation method with better coverage than the sputtering method, and using the ALD method as the film formation method for the first layer can improve the coverage of the oxide semiconductor layer. Therefore, the oxide semiconductor layer can be well coated on steps, openings, and the like with a high aspect ratio.

[0480] The first layer may be, for example, a metal oxide having a microcrystalline structure or an amorphous structure, which has lower crystallinity than the CAAC structure. The crystallinity of the first layer may be increased by forming a second layer having high crystallinity on the first layer having low crystallinity, or by performing heat treatment after forming the second layer, with the second layer acting as a nucleus. This may increase the crystallinity of the entire oxide semiconductor layer, including the vicinity of the interface with the surface on which it is formed.

[0481] The layer serving as the surface to be formed is, for example, an insulating film such as a silicon oxide film, a silicon oxynitride film, a silicon nitride film, a silicon nitride oxide film, an aluminum oxide film, or a hafnium oxide film. Note that, depending on the transistor structure, the layer may be a conductive film such as a titanium nitride film, a tungsten film, or an ITSO film. The layer serving as the surface to be formed does not need to be crystalline. Note that, when the layer has crystallinity, it may have a crystal structure with low lattice matching with the metal oxide contained in the oxide semiconductor layer.

[0482] The first layer is preferably formed by ALD. Here, a method for forming an In-M-Zn oxide as the first layer by ALD will be described.

[0483] First, a source gas containing an indium precursor is introduced into a reaction chamber, and the precursor is adsorbed onto the surface to be formed. Next, an oxidizing agent is introduced into the reaction chamber as a reactant and reacted with the adsorbed precursor, desorbing components other than indium while leaving indium adsorbed onto the substrate, thereby forming a layer in which indium and oxygen are combined.

[0484] Next, a source gas containing a precursor having element M is introduced into the reaction chamber and adsorbed onto the layer of indium and oxygen. Next, an oxidizing agent is introduced into the reaction chamber as a reactant and reacted with the adsorbed precursor, thereby desorbing components other than element M while leaving element M adsorbed on the substrate, thereby forming a layer of element M and oxygen.

[0485] Next, a source gas containing a zinc-containing precursor is introduced into the reaction chamber and adsorbed onto the layer of combined element M and oxygen. Next, an oxidizing agent is introduced into the reaction chamber as a reactant and reacted with the adsorbed precursor, desorbing components other than zinc while leaving zinc adsorbed on the substrate, thereby forming a layer of combined zinc and oxygen.

[0486] By repeating the above-described method, an In-M-Zn oxide can be formed as an oxide semiconductor layer on a layer that is a surface to be formed by the ALD method.

[0487] When an oxide semiconductor layer is formed by the ALD method, ozone (O), oxygen (O), water (H2O), etc. can be used as an oxidizing agent. By using ozone (O3), oxygen (O2), etc. that do not contain hydrogen as an oxidizing agent, the amount of hydrogen mixed into the oxide semiconductor layer can be reduced.

[0488] In the above, after the precursor is adsorbed, it is preferable to stop the introduction of the precursor-containing source gas, purge the reaction chamber, and then discharge the excess precursor, reaction products, etc. from the reaction chamber. Also, in the above, it is preferable to stop the introduction of the oxidant, after the adsorbed precursor is reacted with the oxidant, purge the reaction chamber, and then discharge the excess reactant, reaction products, etc. from the reaction chamber.

[0489] Furthermore, unless otherwise specified in this specification and elsewhere, when ozone, oxygen, or water is used as a reactant or oxidant, it is understood that these are not limited to gaseous or molecular states, but also include plasma, radical, and ionic states.

[0490] The second layer is preferably formed by sputtering.

[0491] In-M-Zn oxide can be used as a target for sputtering. When forming a metal oxide by sputtering, oxygen or a mixture of oxygen and a noble gas can be used as the sputtering gas. In addition, by increasing the proportion of oxygen contained in the sputtering gas, the amount of excess oxygen in the oxide film to be formed can be increased.

[0492] Furthermore, the higher the ratio of the flow rate of oxygen gas to the total film-forming gas used during deposition (hereinafter also referred to as oxygen flow rate ratio), the more crystalline the metal oxide that can be formed may be.

[0493] When a metal oxide is formed by a sputtering method, an oxygen-excess metal oxide may be formed when the ratio of oxygen contained in the sputtering gas is set to more than 30% and less than 100%, preferably 70% to 100%. A transistor using an oxygen-excess metal oxide for a channel formation region can have relatively high reliability. However, one embodiment of the present invention is not limited thereto. An oxygen-deficient metal oxide is formed when the ratio of oxygen contained in the sputtering gas is set to 1% to 30%, preferably 5% to 20%, for film formation. A transistor using an oxygen-deficient metal oxide for a channel formation region can have relatively high field-effect mobility.

[0494] When forming a metal oxide using a sputtering method, it is preferable to heat the substrate. By increasing the substrate temperature (e.g., stage temperature) during metal oxide formation, it may be possible to form a metal oxide with high crystallinity. When forming a metal oxide using a sputtering method, the substrate heating temperature is preferably, for example, 100°C or higher and 400°C or lower, and more preferably 200°C or higher and 300°C or lower.

[0495] By using the above-described manufacturing method, the thickness of the mixed layer formed at the interface between the layer to be formed and the metal oxide can be reduced, or the alloyed region formed at the interface between the layer to be formed and the metal oxide can be made thin enough to be unobservable. For example, the thickness of the alloyed region can be set to 0 nm or more and 3 nm or less, preferably 0 nm or more and 2 nm or less, more preferably 0 nm or more and 1 nm or less, and even more preferably 0 nm or more and less than 0.3 nm.

[0496] The thickness of the alloyed region may be calculated by performing a line analysis of the composition of the alloyed region and its surroundings using SIMS or EDX.

[0497] For example, EDX line analysis is performed on the alloyed region and its periphery, with the direction perpendicular to the surface on which the first layer is to be formed as the depth direction. Next, in the profile of the quantitative values ​​of each element in the depth direction obtained by this analysis, the depth at which the quantitative value of a metal that is the main component of the first layer but is not the main component of the layer that will become the surface on which the layer is to be formed (In if the first layer contains In) becomes half-maximum is defined as the depth (position) of the interface between the region and the first layer. Furthermore, the depth at which the quantitative value of an element that is the main component of the layer that will become the surface on which the layer is to be formed but is not the main component of the first layer (e.g., Si) becomes half-maximum is defined as the depth (position) of the interface between the region and the layer that will become the surface on which the layer is to be formed. From the above, the thickness of the alloyed region can be calculated.

[0498] In the oxide semiconductor layer of one embodiment of the present invention, when the thickness of the alloyed region is observed by EDX analysis, the thickness is, for example, 0 nm to 3 nm, preferably 0 nm to 2 nm, more preferably 0 nm to 1 nm, and even more preferably 0 nm to less than 0.3 nm.

[0499] For example, when SIMS analysis is performed on an oxide semiconductor layer formed on a silicon oxide film, which is a surface to be formed, the depth at which the silicon concentration is 50% of the maximum concentration of the silicon oxide film is defined as the interface, and the silicon concentration is 1.0×10 21 atoms / cm 3, preferably 5.0 x 10 20 atoms / cm 3 , more preferably 1.0 × 10 20 atoms / cm 3 The distance between the depth at which the thickness decreases and the interface is defined as thickness t. The thickness t is preferably 3 nm or less, and more preferably 2 nm or less.

[0500] By reducing the thickness of the alloyed region, the thickness t can be set to a value within the above range.

[0501] By reducing the alloyed region, the CAAC structure can be formed near the formation surface. Here, the vicinity of the formation surface refers to, for example, a region that is more than 0 nm and not more than 3 nm, preferably more than 0 nm and not more than 2 nm, more preferably 1 nm or more and not more than 2 nm, approximately perpendicularly from the formation surface of the oxide semiconductor layer.

[0502] The CAAC structure near the surface to be formed can sometimes be confirmed by observation using a TEM. For example, in cross-sectional observation of an oxide semiconductor layer using a high-resolution TEM, bright spots arranged in layers parallel to the surface to be formed are confirmed near the surface to be formed.

[0503] Furthermore, the oxide semiconductor layer of one embodiment of the present invention can have a three-layer structure including a first layer, a second layer over the first layer, and a third layer over the second layer.

[0504] When the oxide semiconductor layer has a three-layer structure, the oxide semiconductor layer can be manufactured by forming a first layer on a surface to be formed by a first film formation method, forming a second layer by a second film formation method, and then forming a third layer by the first film formation method.

[0505] Even when the first and third layers of the oxide semiconductor layer have compositions that make it difficult to form a CAAC structure when they are formed as single layers, crystal growth occurs using the second layer as a nucleus, so that the entire oxide semiconductor layer including the first and third layers can have the CAAC structure. Alternatively, the CAAC structure can be formed in a region including at least a part of each of the first and third layers and the second layer.

[0506] In particular, even when the first layer and the third layer have a high In content, the oxide semiconductor layer can have suitable crystallinity for a semiconductor layer of a transistor. In the oxide semiconductor layer of one embodiment of the present invention, the increase in the In content can improve the on-state characteristics of the transistor, and the improvement in reliability can be achieved by having a CAAC structure with high crystallinity.

[0507] The first and third layers may be made of metal oxides having the same composition as the second layer, which may increase the likelihood of CAAC formation after heat treatment.

[0508] Because the second layer has high crystallinity, the third layer can grow using the crystals of the second layer as nuclei or seeds. Therefore, even if a film formation method that easily imparts crystallinity is not used as a film formation method for the third layer, the third layer can be crystallized. Here, for example, by forming the third layer using a film formation method that has higher coverage than the second layer, the oxide semiconductor layer can have both high crystallinity and high coverage throughout the layer.

[0509] Furthermore, the second layer has excellent crystallinity because the influence of the surface on which it is formed is reduced by providing the first layer, and therefore the third layer, which is crystallized using the second layer as a nucleus or seed, is also expected to have excellent crystallinity.

[0510] When an oxide semiconductor layer is used as a semiconductor layer of a transistor, the third layer, which is the uppermost layer of the oxide semiconductor layer, may be in contact with a gate insulating layer. By increasing the crystallinity of the layer in contact with the gate insulating layer, carrier mobility can be increased when the transistor is on.

[0511] The first layer and the third layer each have high crystallinity, using the highly crystalline second layer as a nucleus or seed. Specifically, the crystallinity of the first layer may be increased by heat treatment during or after the deposition of the second layer. The crystallinity of the third layer may be increased by heat treatment during or after the deposition of the third layer. The heat treatment has the function of assisting in increasing the crystallinity.

[0512] As described above, in the method for forming an oxide semiconductor layer according to one embodiment of the present invention, the crystallinity of the upper and lower metal oxides (the first and third layers in this case) can be increased by using the second layer having a highly crystalline metal oxide (i.e., CAAC) as a nucleus or seed. This increases the crystallinity of the entire oxide semiconductor. In other words, the upper and lower metal oxides can be grown in a solid phase using the second layer as a nucleus or seed to form an oxide semiconductor layer with high crystallinity. An oxide semiconductor layer formed by such a deposition method, i.e., a CAAC film in this case, can be referred to as an axial growth CAAC (AG CAAC).

[0513] In the oxide semiconductor layer, it is preferable that a region having a CAAC structure is widely present throughout the layer. The region having a CAAC structure in the first layer is crystallinely connected to a region having a CAAC structure in the second layer. The region having a CAAC structure in the third layer is crystallinely connected to a region having a CAAC structure in the second layer. As a result, the boundary between the first layer and the second layer may not be observed. Also, the boundary between the second layer and the third layer may not be observed. The oxide semiconductor layer may be expressed as a single layer with no clearly observable interface. The oxide semiconductor layer may be expressed as a single layer.

[0514] In each of the first to third layers, in a region having the CAAC structure, for example, bright spots aligned parallel or approximately parallel to the surface on which the CAAC structure is formed are observed in cross-sectional observation using a high-resolution TEM. Furthermore, the c-axis of the CAAC structure in each of the first to third layers is preferably parallel or approximately parallel to the normal direction of the surface on which the CAAC structure is formed or the surface of the oxide semiconductor layer.

[0515] Furthermore, a portion of the first layer or the third layer may not be crystallized.

[0516] When the oxide semiconductor layer has a three-layer structure, the oxide semiconductor layer can also be manufactured by forming a first layer on a surface to be formed by a first film formation method, then forming a second layer by the first film formation method, and then forming a third layer by the second film formation method.

[0517] As mentioned above, using a metal oxide with a high In content in a transistor can increase the field-effect mobility of the transistor. However, metal oxides with a high In content tend to have a cubic crystal structure. Therefore, by using a metal oxide with a high In content in the second layer adjacent to the third layer, it is possible to form crystals that reflect the crystal orientation of the third layer.

[0518] Furthermore, it is preferable that the lattice mismatch between the crystals of the third layer and the crystals of the second layer is small. This allows the second layer to form crystals that reflect the orientation of the crystals of the third layer. In this case, for example, when a cross-section of the ox...

Claims

1. a first insulating layer, a second insulating layer, a first capacitor, a second capacitor, a first transistor, and a second transistor; the first insulating layer has a first opening; the second insulating layer has a second opening; the second insulating layer is located on the first insulating layer; the second opening has an area overlapping with the first opening, the first capacitor includes a first electrode provided along a sidewall of the first opening, a dielectric provided to cover the first electrode, and a second electrode having a region facing the first electrode within the first opening with the dielectric sandwiched therebetween; the second capacitor includes the first electrode, the dielectric, and a third electrode having a region facing the first electrode within the first opening with the dielectric therebetween; the first transistor includes a first oxide semiconductor layer; the second transistor includes a second oxide semiconductor layer; the first oxide semiconductor layer and the second oxide semiconductor layer each have a region provided along a sidewall of the second opening.

2. a first capacitor, a second capacitor, a first transistor, a second transistor, a first insulating layer, a second insulating layer, a third insulating layer, and a fourth insulating layer; the first capacitor has a first conductive layer, a second conductive layer, and a fifth insulating layer; the second capacitor has the first conductive layer, a third conductive layer, and the fifth insulating layer; the first transistor includes a first oxide semiconductor layer, a fourth conductive layer, a fifth conductive layer, a sixth conductive layer, and a sixth insulating layer; the second transistor includes a second oxide semiconductor layer, the fifth conductive layer, a seventh conductive layer, an eighth conductive layer, and the sixth insulating layer; the first insulating layer has a first opening; the first conductive layer has a region located within the first opening, the fifth insulating layer is located on the first conductive layer; the second conductive layer and the third conductive layer each have a region facing the first conductive layer in the first opening with the fifth insulating layer therebetween; the second insulating layer is located on the second conductive layer and on the third conductive layer; the fourth conductive layer and the seventh conductive layer are located on the second insulating layer; the fourth conductive layer is electrically connected to the second conductive layer; the seventh conductive layer is electrically connected to the third conductive layer; the third insulating layer is located on the fourth conductive layer and the seventh conductive layer; the fifth conductive layer is located on the third insulating layer; the fourth insulating layer is located on the third insulating layer and on the fifth conductive layer; the sixth conductive layer and the eighth conductive layer are provided on the fourth insulating layer and spaced apart from each other; the fourth insulating layer, the fifth conductive layer, and the third insulating layer have a second opening; the second opening has a portion overlapping the fourth conductive layer, a portion overlapping the seventh conductive layer, and a portion overlapping the second insulating layer located between the fourth conductive layer and the seventh conductive layer; the sixth insulating layer covers a sidewall of the second opening; the first oxide semiconductor layer has a region facing the fifth conductive layer with the sixth insulating layer sandwiched therebetween in the second opening, a region in contact with the fourth conductive layer in the second opening, and a region in contact with the sixth conductive layer outside the second opening; the second oxide semiconductor layer has a region facing the fifth conductive layer with the sixth insulating layer sandwiched therebetween in the second opening, a region in contact with the seventh conductive layer in the second opening, and a region in contact with the eighth conductive layer outside the second opening.

3. In claim 2, The first conductive layer has a region along a sidewall of the first opening.

4. In claim 2, a ninth conductive layer and a tenth conductive layer; the second insulating layer has a third opening reaching the second conductive layer and a fourth opening reaching the third conductive layer; the ninth conductive layer is located in the third opening; the tenth conductive layer is located in the fourth opening; the fourth conductive layer has a region in contact with an upper surface of the ninth conductive layer, The seventh conductive layer has a region in contact with an upper surface of the tenth conductive layer.

5. In claim 2, a seventh insulating layer; the second insulating layer has a first recess at a position overlapping the first opening, The seventh insulating layer is provided so as to fill at least a portion of the first recess.

6. In any one of claims 2 to 5, the sixth insulating layer in the second opening has a circular shape in a plan view, In the second opening, each of the first oxide semiconductor layer and the second oxide semiconductor layer has an arc shape in a plan view.

7. In any one of claims 2 to 5, the fourth conductive layer has a second recess at a position overlapping the second opening, the sixth insulating layer is in contact with a sidewall of the second recess; the first oxide semiconductor layer is in contact with at least a part of a bottom of the second recess.

8. In claim 7, the fourth conductive layer includes a first layer and a second layer on the first layer; The second layer has the second recess.

9. In any one of claims 2 to 5, the sixth insulating layer is in contact with a part of a side surface of the sixth conductive layer on the second opening side, the first oxide semiconductor layer is in contact with another part of the side surface of the sixth conductive layer on the second opening side.

10. In claim 9, the sixth insulating layer is in contact with a part of a side surface of the fourth conductive layer on the second opening side; the first oxide semiconductor layer is in contact with another part of the side surface of the fourth conductive layer on the second opening side.

11. In any one of claims 2 to 5, an end of the first oxide semiconductor layer outside the second opening is located closer to the second opening than an end of the sixth conductive layer outside the second opening.

12. In any one of claims 2 to 5, an eighth insulating layer and an eleventh conductive layer; the eighth insulating layer is located on the first oxide semiconductor layer and the second oxide semiconductor layer; the eleventh conductive layer has, in the second opening, a region facing the fifth conductive layer with the eighth insulating layer, the first oxide semiconductor layer, and the sixth insulating layer sandwiched therebetween, and a region facing the fifth conductive layer with the eighth insulating layer, the second oxide semiconductor layer, and the sixth insulating layer sandwiched therebetween.

13. In claim 12, a bottom surface of the eleventh conductive layer located between the fourth conductive layer and the seventh conductive layer is lower than a top surface of the fourth conductive layer that does not overlap with the second opening.

14. In claim 12, a ninth insulating layer and a twelfth conductive layer; the ninth insulating layer is located on the eighth insulating layer and has a fifth opening at a position overlapping the second opening; the twelfth conductive layer is provided on the ninth insulating layer and has a region in contact with the eleventh conductive layer.

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