Penetration electrode substrate

Abstract

To provide a penetration electrode substrate with a structure in which the capacitance of a capacitor is easily controllable.SOLUTION: A penetration electrode substrate includes a substrate having a first surface and a second surface on the opposite side of the first surface, a penetration electrode electrically connecting the first surface and the second surface, a first conductive layer disposed on a first surface of the substrate and electrically connected to the penetration electrode, a first insulating layer disposed on the first conductive layer, and an intermediate layer disposed between the first conductive layer and the first insulating layer. The first insulating layer includes a first insulating part disposed on the intermediate layer, a second insulating part extending from the first insulating part and covering a side surface of the intermediate layer and a side surface of the first conductive layer, and a third insulating part extending from the second insulating part and covering at least a part of the first surface of the substrate.SELECTED DRAWING: Figure 5

Description

[Technical Field]

[0001] The present disclosure relates to a through electrode substrate. [Background technology]

[0002] In recent electronic devices, semiconductor chips are attached to wiring boards via through-hole electrode substrates. Patent Document 1 describes a through-hole electrode substrate using glass as the substrate material. has been disclosed. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] WO2005 / 034594 No. Summary of the Invention [Problem to be solved by the invention]

[0004] The above-mentioned through-hole electrode substrate is a MIM (Metal-Insulator-Metal) structure in which an insulating layer is sandwiched between metal layers. The MIM structure is, for example, a MIM capacitor. When designing the capacitance of a capacitor, the size of the electrode pattern is However, it is difficult to fabricate a high density M on a through-hole electrode substrate. When forming an IM structure, there are restrictions on the size of the electrode pattern. Silicon nitride (SiN) layers are used as the dielectric constant. There is little freedom in terms of control.

[0005] The present disclosure provides a through electrode substrate having a structure that makes it easy to control the capacitance of a capacitor. [Means for solving the problem]

[0006] The present application includes multiple means for solving the above problems. For example, see the first page. and a substrate having a second surface opposite to the first surface, and a through hole electrically connecting the first surface and the second surface. a first conductive layer disposed on the first surface of the substrate and electrically connected to the through-electrode; a first insulating layer disposed on the conductive layer; and an intermediate layer disposed between the first conductive layer and the first insulating layer. and the first insulating layer comprises a first insulating portion disposed on the intermediate layer and a first insulating portion. a second insulating portion extending to cover a side surface of the intermediate layer and a side surface of the first conductive layer; and a third insulating portion covering at least a portion of the first surface of the substrate. do. [Effects of the Invention]

[0007] According to the technology of the present disclosure, a through electrode substrate having a structure that makes it easy to control the capacitance of a capacitor is provided. Further features related to the present disclosure will become apparent from the description and accompanying drawings. In addition, the problems, configurations and effects other than those described above can be achieved by the following embodiments. This is made clear by the description of the state. [Brief explanation of the drawings]

[0008] [Figure 1] 1 is a schematic cross-sectional view showing an interposer according to an embodiment of the present disclosure. [Figure 2] FIG. 2 is a cross-sectional view taken along line AA in FIG. [Figure 3] 1 is a schematic cross-sectional view of an MIM structure according to an embodiment of the present disclosure. [Figure 4] 1 is a schematic cross-sectional view of an MIM structure according to an embodiment of the present disclosure. [Figure 5] 1 is a schematic cross-sectional view of an MIM structure according to an embodiment of the present disclosure. [Figure 6] 1 shows the results of XPS measurement of the sample. DETAILED DESCRIPTION OF THE INVENTION

[0009] Hereinafter, an embodiment of the present disclosure will be described with reference to the drawings. In the drawings, the scale and aspect ratios are appropriately adjusted for the convenience of illustration and ease of understanding. , have been altered and exaggerated from the actual products.

[0010] In this specification, a numerical range expressed using "to" is the range of the numbers written before and after "to". The ranges include the lower and upper limits of the values.

[0011] Hereinafter, the form of an interposer placed between a wiring board and a semiconductor chip, etc. will be used. However, the following embodiment is not limited to this. Here, the through electrode substrate is a substrate that is disposed between a wiring substrate and a semiconductor chip or the like. Not only interposers that are used, but also IPDs (Integrators) that do not have semiconductor chips installed In this case, the upper and lower One side of the wiring substrate is electrically connected to the through electrode.

[0012] FIG. 1 is a schematic cross-sectional view showing an interposer 10 according to an embodiment of the present disclosure. 2 is a cross-sectional view taken along the line AA in FIG. 1. The interposer 10 is, for example, a metal insulating layer. It has a MIM (Metal-Insulator-Metal) structure, which is a sandwiched structure. The MIM structure can be used as a MIM capacitor. A part of the conductive layer 12 serves as the lower electrode, the first insulating layer 14 serves as the dielectric layer, and the second conductive layer 15 serves as the upper electrode. do.

[0013] The interposer 10 has a first surface 11a and a second surface 11b on the opposite side of the first surface 11a. a substrate 11 having a first conductive layer 12 disposed on a first surface 11a of the substrate 11; A first insulating layer 14 is disposed on the conductive layer 12, and a layer is formed between the first conductive layer 12 and the first insulating layer 14. and a second conductive layer 15 disposed on the first insulating layer 14. The first conductive layer 12 may be disposed directly on the first surface 11a of the substrate 11, or may be disposed on a conductive layer. The first surface 11a of the substrate 11 is provided with at least one conductive or insulating layer therebetween. For example, the first surface 11a of the substrate 11 may be covered with a resin selected from epoxy resin and polyimide resin. By disposing the insulating resin, the difference in the thermal expansion coefficient between the first conductive layer 12 and the substrate 11 can be prevented. This can relieve the stress that occurs.

[0014] The substrate 11 has a through hole 16 that electrically connects the first surface 11a and the second surface 11b. The layer 12 is connected to the fourth layer 11b disposed on the second surface 11b via a through electrode 17 formed in the through hole 16. The through-hole 16 is electrically connected to the conductive layer 22. The shape of the through-hole 16 is not limited to that shown in the figure. is a direction from the first surface 11a and the second surface 11b of the substrate 11 toward the center of the substrate 11 in the thickness direction. The sidewall of the through-hole 16 may be formed such that the width decreases as the thickness of the through-hole 16 increases. The first surface 11a of the substrate 11 may extend in the normal direction. The substrate 1 may be narrowed along the sidewall, or a part of the sidewall may have a curved shape. 1. Etching, laser processing, and a combination of laser and etching processing. The through holes 16 are formed by sandblasting, electrical discharge machining, drilling, etc. The through electrode 17 is not limited to the form shown in FIG. 1, and may be a form in which a conductive material is filled in the through hole 16. may be.

[0015] A resin layer 21 is formed on the first surface 11a and the second surface 11b of the substrate 11. On the first surface 11a of the semiconductor device 1, the resin layer 21 is formed so as to cover the MIM structure. A connection hole 18 is provided in the oil layer 21 at a position corresponding to the second conductive layer 15. The inside of the resin layer 21 is filled with a conductive member 19. The surface 21a of the resin layer 21 is provided with a third conductive member 19. On the first surface 11a side of the substrate 11, the second conductive layer 15 is formed. The semiconductor chip 50 is connected to the conductive member 19, the third conductive layer 20, and the solder balls 24. It is being done.

[0016] On the second surface 11b of the substrate 11, at a position corresponding to the fourth conductive layer 22 of the resin layer 21, A connection hole 18 is provided. The connection hole 18 is filled with a conductive member 19. A fifth conductive layer 23 is formed on the surface 21b of the resin layer 21. On the 1b side, the fourth conductive layer 22 includes the conductive member 19, the fifth conductive layer 23, and the solder balls. 24 and is connected to the wiring board 40.

[0017] According to this configuration, the interposer 10 is disposed on the first surface 11a side of the substrate 11, The semiconductor chip 50 electrically connected to the through electrode 17 and the semiconductor chip 50 arranged on the second surface 11b side of the substrate 11 are and a wiring substrate 40 electrically connected to the through electrode 17. According to the interposer 10 of this embodiment, a semiconductor chip 50 with a narrow terminal pitch can be mounted. This simplifies the mounting of the device on a large wiring board (such as a motherboard) 40.

[0018] The substrate 11 may be a glass substrate, a glass ceramic substrate, a quartz substrate, a sapphire substrate, Resin substrate, glass epoxy substrate, silicon substrate, SOI (Silicon on Ins Silicon on Sapphire (SOS) substrate, carbonized silicon Silicon (SiC) substrate, gallium arsenide (GaAs) substrate, indium phosphide (InP) substrate Plate, alumina (Al2O3) substrate, aluminum nitride (AlN) substrate, zirconium oxide A (ZrO2) substrate or a substrate in which these are laminated can be used.

[0019] Preferably, the substrate 11 is a glass substrate. Generally, the interposer has a thickness of 1000 Å near its edge. The smaller the area, the greater the displacement due to thermal deformation. , the difference in thermal expansion coefficient between this region and the wiring boards, etc., that are placed above and below the interposer This has the advantage that it can be dealt with to make it smaller.

[0020] More preferably, alkali-free glass is used for the substrate 11. Unlike soda glass, it does not contain alkaline components such as Na and K, so the glass surface Therefore, in this embodiment, the alkali metal component is not precipitated. The advantage is that, in principle, there is no risk of corrosion of the terminals of semiconductor chips that should be removed. In addition, the coefficient of thermal expansion of non-alkali glass is similar to that of silicon, It has good compatibility with the semiconductor chip to be connected in terms of thermal expansion coefficient.

[0021] The materials for each of the above-mentioned conductive layers are gold (Au), Ag (silver), copper (Cu), iron (Fe), nickel (Ni), and Nickel (Ni), platinum (Pt), palladium (Pd), ruthenium (Ru), tungsten Conductive materials such as tungsten (W) are used. It is preferable to use copper (Cu) which has a low resistance to corrosion. The thickness of the second conductive layer 15 is preferably 0.5 μm to 5 μm. For the lines, subtractive formation by etching metal foil (e.g., Cu, etc.) In addition, conductive paste (e.g., metal nanopaste) can be applied, and plating can be used. Additive forming of the above may also be employed.

[0022] The intermediate layer 13 is made of at least one of titanium (Ti), nickel (Ni), and gold (Au). In the example of FIG. 2, the intermediate layer 13 is made of titanium (Ti). The thickness is 20 nm to 200 nm, and preferably 50 nm to 100 nm.

[0023] The first insulating layer 14 of this embodiment is silicon nitride (SiN) containing carbon (C). When carbon (C) is increased in the first insulating layer 14, which is a dielectric, the relative dielectric constant decreases, and the capacitor Furthermore, when carbon (C) is increased in the first insulating layer 14, which is a dielectric, The adhesion to the titanium (Ti) intermediate layer 13 is improved. The thickness of 4 is 50 nm to 800 nm, preferably 200 nm to 400 nm. .

[0024] As shown in FIG. 2, the first insulating layer 14 is formed between the upper surface 13d of the intermediate layer 13 and the second conductive layer 15. a first insulating portion 14a disposed between the first insulating portion 14a and an intermediate layer 14b extending continuously from the first insulating portion 14a; a second insulating portion 14b covering the side surface 13e of the first conductive layer 13 and the side surface 12b of the first conductive layer 12; a third insulating layer extending continuously from the portion 14b and covering at least a portion of the first surface 11a of the substrate 11; The silicon nitride (SiN) of the first insulating layer 14 contains carbon (C). This also improves the adhesion between the third insulating portion 14c of the first insulating layer 14 and the substrate 11. do.

[0025] In the embodiment of the present disclosure, the deposition process of the conductive layer and the insulating layer is performed by chemical vapor deposition (C VD) (e.g., plasma-enhanced CVD, atomic layer deposition (ALD)), physical vapor deposition (PVD) (e.g., For example, sputtering or vapor deposition, or electroplating can be used. Photolithography can be used to pattern the conductive and insulating layers. In addition, etch-back and chemical mechanical polishing can be used as flattening processes for conductive and insulating layers. Polishing (CMP) etc. can be used.

[0026] 3 shows another example of the configuration of the intermediate layer 13. The intermediate layer 13 is a nickel layer on the first conductive layer 12. A first layer 13-1 of nickel (Ni) and a second layer 13-2 of gold (Au) disposed on the first layer 13-1. In this embodiment, the first layer 13-1 of nickel (Ni) The thickness of the second layer 13-2 of gold (Au) is 0.05 μm to 5.0 μm. The intermediate layer 13 in this example also has a thickness of 0.5 μm to 0.5 μm. 2 and 3, the intermediate layer 13 has a high It is preferable to use titanium (Ti) because this provides higher adhesion.

[0027] 4 shows another example of the configuration of the intermediate layer 13. The intermediate layer 13 is formed on the upper surface 12 of the first conductive layer 12. a first portion 13a disposed between the first insulating portion 14a of the first insulating layer 14 and the first insulating portion 14a of the first insulating layer 14; a second portion 13b extending continuously from the first portion 13a and covering the side surface 12b of the first conductive layer 12; a third portion extending continuously from the portion 13b and covering at least a portion of the first surface 11a of the substrate 11; In this example, the second insulating portion 14b of the first insulating layer 14 is formed between the intermediate layer 13 and the second insulating portion 14b. The third insulating portion of the first insulating layer 14 is disposed so as to cover at least a part of the second portion 13b. The portion 14c is disposed so as to cover at least a part of the third portion 13c of the intermediate layer 13. According to this configuration, the intermediate layer 13 extends to the first surface 11a of the substrate 11, and therefore the first insulating layer The adhesion between the edge layer 14 and the first surface 11a of the substrate 11 is improved.

[0028] 5 shows another example of the configuration of the intermediate layer 13 and the first insulating layer 14. The insulating portion 14c covers the end of the third portion 13c of the intermediate layer 13 and is connected to the first surface of the substrate 11. It may be arranged to cover at least a part of 11a.

[0029] Next, samples 1 to 5 of a plurality of silicon nitride (SiN) layers were prepared, and the relative dielectric constant and adhesion were measured. The layers of each of Samples 1 to 5 were formed on a Si wafer, and the layer thickness was 50 0 nm. Samples 1 to 3 are samples that do not contain carbon (C), and Samples 4 to 5 is a sample containing carbon (C).

[0030] Figure 6 shows the results of XP analysis using ESCA-3400 (Shimadzu Corporation) for samples 1 to 5. X-ray Photoelectron Spectroscopy (X-ray Photoelectron Spectroscopy) measurement was performed. The quantitative values ​​obtained for each of Samples 1 to 5 were as follows. [XPS measurement] Incident X-ray: Mg K α (non-monochromatic X-ray) Measurement area: 6mmφ X-ray output: 120W [Depth profile analysis] Ion gun: Ar Acceleration voltage: 0.3 kV Emission: 30mA Etching time: 30 seconds / cycle (1 to 20 cycles), 100 seconds / cycle le (21 to 45 cycles)

[0031] The relative dielectric constant and adhesion to the intermediate layer 13 were examined for Samples 1 to 5 in FIG. Samples 4 and 5, which contain carbon (C), have lower dielectric constants than samples 1 to 3. Moreover, Samples 4 and 5 had higher adhesion to the intermediate layer 13 than Samples 1 to 3. In this way, when Samples 4 and 5 are used as the first insulating layer 14, the relative dielectric constant is low. Therefore, it becomes easier to control the capacitance of the capacitor. ) increases, the adhesion of the intermediate layer 13 to titanium increases.

[0032] Samples 4 and 5, which are silicon nitride (SiN) containing carbon (C), were prepared as follows: It can be produced by the method. For example, when manufacturing Sample 4, the raw material gas tetramethylsilane is introduced into the vacuum processing chamber in advance. 30 sccm of silane and 100 sccm of nitrogen gas were introduced, and the deposition pressure was set to 1 Pa. A heater is installed on the support to control the substrate temperature at 200°C. A high frequency wave of 3 kW is applied from the top of the chamber via a matching box to generate plasma. This plasma generates a chemical reaction in the gas phase, which then causes the supporting gas in the vacuum processing chamber to react. A silicon nitride (SiN) film containing carbon (C) is formed on the substrate placed on the support. . For example, for sample 5, the amount of tetramethylsilane introduced was The film was formed under the same conditions as Sample 4, with the flow rate set to 60 sccm.

[0033] The above-mentioned interposer and through-hole electrode substrate are used in mobile phones, smartphones, wireless Local Area Network (LAN) devices, set-top boxes, music players , video players, entertainment units, navigation devices, communication devices a mobile device, a personal digital assistant (PDA), a fixed location data unit, and a computer. This can be applied to the device of choice.

[0034] The present disclosure is not limited to the above-described embodiment, and includes various other modified examples. For example, the above-described embodiments have been described in detail to clearly explain the present disclosure. However, it is not necessarily limited to having all the configurations described above. A part of the configuration of one embodiment may be replaced with a configuration of another embodiment. It is also possible to add the configuration of another embodiment to the configuration of the embodiment. It is possible to add, delete, or replace some of the components with other components. [Explanation of symbols]

[0035] 10...Interposer 11... Substrate 11a...Side 1 11b…Second side 12...First conductive layer 13...middle class 14...First insulating layer 15...Second conductive layer 16...Through hole 17...Through electrode 18...Connection hole 19...Conductive material 20...Third conductive layer 21...resin layer 22...Fourth conductive layer 23...5th conductive layer 24...Solder ball 40...wiring board 50...semiconductor chips

Claims

[Claim 1] a substrate having a first surface and a second surface opposite the first surface; a through electrode that electrically connects the first surface and the second surface; a first conductive layer disposed on the first surface of the substrate and electrically connected to the through electrode; a first insulating layer disposed on the first conductive layer; an intermediate layer disposed between the first conductive layer and the first insulating layer; The first insulating layer has a first insulating portion disposed on the intermediate layer and a second insulating portion disposed on the first insulating portion. a second insulating portion extending from the first conductive layer to cover a side surface of the intermediate layer and a side surface of the first conductive layer; a third insulating portion extending from the edge portion and covering at least a portion of the first surface of the substrate; , through-electrode substrate.

Images