Semiconductor device

Abstract

To provide a semiconductor device that can operate stably even if a transistor is a depletion type.SOLUTION: A semiconductor device of one embodiment of the invention disclosed has: a first transistor that has a function of supplying a first potential to first wiring; a second transistor that has a function of supplying a second potential to the first wiring; a third transistor that has a function of supplying a third potential for turning on the first transistor to a gate of the first transistor, and then stopping the supply of the third potential; a fourth transistor that has a function of supplying a second potential to the gate of the first transistor; and a first circuit that has a function of generating a second signal obtained by giving an offset to a first signal. The second signal is inputted to a gate of the fourth transistor. A minimum value of the second signal is less than the second potential.SELECTED DRAWING: Figure 1

Description

[Technical Field]

[0001] One embodiment of the present invention relates to a semiconductor device and a display device. [Background technology]

[0002] With the spread of large display devices such as LCD TVs, the development of display devices with higher added value is progressing. In particular, technological development is underway to construct a drive circuit using only transistors of one conductivity type. This is being actively pursued (see Patent Document 1).

[0003] FIG. 23 shows the driving circuit described in Patent Document 1. The driving circuit in Patent Document 1 A transistor M1, a transistor M2, a transistor M3, a transistor M4, and a capacitance element C1 In Patent Document 1, when the signal OUT is set to a high level, the transistor M1 The gate of the transistor M1 is set in a floating state, and the capacitance of the capacitance element C1 is used to A bootstrap operation is performed to raise the potential higher than the potential VDD. In order to make the gate of transistor M1 floating, a transistor connected to the gate of transistor M1 is The potential difference between the gate and source of a transistor (for example, transistor M4) (hereinafter referred to as Vgs) The transistor is turned off by setting the voltage (shown in the figure) to 0V.

[0004] Also, when the signal OUT is set to low level, the signal IN is set to high level, and the This causes transistor M2 and transistor M3 to be turned on. [Prior art documents] [Patent documents]

[0005] [Patent Document 1] Japanese Patent Application Laid-Open No. 2002-328643 Summary of the Invention [Problem to be solved by the invention]

[0006] If the transistor is a depletion type (also called a normally-on type), Even if the Vgs of the transistor is set to 0 [V], the transistor will not turn off. When the signal OUT is set to a high level, the transistors M3 and M4 Since the transistor M1 is not turned off, the gate of the transistor M1 cannot be left floating. If the gate of transistor M1 cannot be left floating, the bootstrap operation will not function properly. This may result in malfunctions, or even if malfunctions do not occur, The range of operable drive frequencies may be narrowed.

[0007] When the signal OUT is set to a low level, the drive voltage of the drive circuit of the display device is Therefore, the Vgs of the transistors M2 and M3 also become large. The transistors will deteriorate and eventually the drive circuit may malfunction.

[0008] In view of this, in one embodiment of the present invention, even if a transistor is a depletion type, a stable Another object of the present invention is to provide a semiconductor device that can operate stably. One of the objectives is to suppress deterioration of a transistor. [Means for solving the problem]

[0009] A semiconductor device according to one embodiment of the disclosed invention has a function of supplying a first potential to a first wiring. a first transistor having a function of supplying a second potential to a first wiring; The gate of the first transistor is connected to the second transistor to turn on the first transistor. a third transistor having a function of supplying the third potential and then stopping the supply of the third potential; a fourth transistor having a function of supplying a second potential to a gate of the first transistor; a first circuit having a function of generating a second signal by applying an offset to the first signal; The gate of the fourth transistor receives a second signal. The low level potential of the signal is a potential lower than the second potential.

[0010] A semiconductor device according to one embodiment of the disclosed invention has a function of supplying a first potential to a first wiring. a first transistor having a function of supplying a second potential to a first wiring; The gate of the first transistor is connected to the second transistor to turn on the first transistor. a third transistor having a function of supplying the third potential and then stopping the supply of the third potential; a fourth transistor having a function of supplying a second potential to a gate of the first transistor; A capacitor to which a first signal is input and a fourth potential is input to the other electrode of the capacitor. and a fifth transistor having a function of supplying a fourth transistor. The gate of the capacitor is connected to the other electrode of the capacitor. is the potential.

[0011] In the semiconductor device, the first signal is input to the gate of the second transistor. This may be done. [Effects of the Invention]

[0012] According to one embodiment of the present invention, even if the transistor is a depletion type, Also, the drain current when the transistor is off can be reduced. Therefore, it is possible to prevent malfunction of the circuit. This reduces the Vgs of the transistor, suppressing its deterioration. It is possible. [Brief explanation of the drawings]

[0013] [Figure 1] 1A to 1C illustrate a semiconductor device according to one embodiment of the present invention. [Figure 2] 1A to 1C illustrate a semiconductor device according to one embodiment of the present invention. [Figure 3] 1A to 1C illustrate a semiconductor device according to one embodiment of the present invention. [Figure 4] 1A to 1C illustrate a semiconductor device according to one embodiment of the present invention. [Figure 5] 1A to 1C illustrate a semiconductor device according to one embodiment of the present invention. [Figure 6] 1A to 1C illustrate a semiconductor device according to one embodiment of the present invention. [Figure 7] 1A to 1C illustrate a semiconductor device according to one embodiment of the present invention. [Figure 8] 1A to 1C illustrate a semiconductor device according to one embodiment of the present invention. [Figure 9] 1A to 1C illustrate a semiconductor device according to one embodiment of the present invention. [Figure 10] 1A to 1C illustrate a semiconductor device according to one embodiment of the present invention. [Figure 11] FIG. 10 is a diagram illustrating a shift register circuit according to one embodiment of the present invention. [Figure 12] FIG. 10 is a diagram illustrating a shift register circuit according to one embodiment of the present invention. [Figure 13] 1A and 1B are diagrams illustrating a display device according to one embodiment of the present invention. [Figure 14] 1A to 1C illustrate a structure of an oxide material according to one embodiment of the present invention. [Figure 15] 1A to 1C illustrate a structure of an oxide material according to one embodiment of the present invention. [Figure 16] 1A to 1C illustrate a structure of an oxide material according to one embodiment of the present invention. [Figure 17] 1A to 1C illustrate a structure of a transistor according to one embodiment of the present invention. [Figure 18] 10 is a graph showing characteristics of a transistor including an oxide semiconductor layer. [Figure 19] FIG. 10 is a graph showing the relationship between the off-state current of a transistor and the substrate temperature during measurement. [Figure 20] 1A to 1C illustrate electronic devices according to one embodiment of the present invention. [Figure 21] 1A to 1C illustrate electronic devices according to one embodiment of the present invention. [Figure 22] 1A to 1C illustrate a semiconductor device according to one embodiment of the present invention. [Figure 23] FIG. 1 is a diagram illustrating a conventional driving circuit. DETAILED DESCRIPTION OF THE INVENTION

[0014] An example of an embodiment for explaining the present invention will be described below with reference to the drawings. The contents of the embodiments may be changed without departing from the spirit and scope of the present invention. Therefore, the present invention is not limited to the description of the following embodiments. Not determined.

[0015] (Embodiment 1) In this embodiment, a signal is generated by applying an offset to the input signal, and the drive circuit is driven by this signal. An example of such a semiconductor device will be described below.

[0016] The structure of a semiconductor device of this embodiment mode will be described with reference to FIG. 1A shows a circuit diagram of a semiconductor device according to this embodiment. The circuit 100 includes a wiring 11, a wiring 12, a wiring 14, and a The circuit 110 is connected to the wiring 15, the wiring 13, the wiring 16, and the circuit 100. Depending on the configuration of the circuit 100 and the circuit 110, The wiring and the like connected to the circuit 110 may be changed as appropriate.

[0017] In the specification, when it is explicitly stated that X and Y are connected, X When X and Y are electrically connected, when X and Y are functionally connected, and when X and Y are This includes the case where Y is directly connected to Y.

[0018] A potential VL1 is supplied to the wiring 13. The potential VL1 is a predetermined potential. 3 has the function of transmitting the potential VL1.

[0019] A potential VL2 is supplied to the wiring 14. The potential VL2 is a predetermined potential. L2 is a potential lower than the potential VL1. The wiring 14 has a function of transmitting the potential VL2. do.

[0020] A potential VH is supplied to the wiring 15. The potential VH is a predetermined potential. The potential VH is higher than the potential VL1. Note that the wiring 15 has a function of transmitting the potential VH.

[0021] The wiring 13, the wiring 14, and the wiring 15 are also referred to as power supply lines. The potentials VL1, VL2, and VH are also referred to as power supply potentials. For example, it is supplied from a power supply circuit or the like.

[0022] A signal IN is input to the wiring 11. The signal IN is an input signal to the semiconductor device. The signal IN is a digital signal, and the high level potential of the signal IN is VH. The low-level potential is VL1. That is, the potential VH and the potential VL1 are selected for the wiring 11. The wiring 11 has a function of transmitting a signal IN.

[0023] A signal SE is input to the wiring 12. The signal SE is input at the timing of acquiring the offset voltage. The signal SE is a digital signal, and the high level of the signal SE The potential of the bell is a potential exceeding VL2, and the low level potential of the signal SE is VL2 or VL That is, the wiring 12 is supplied with a potential higher than the potential VL2 and a potential lower than the potential VL2. The wiring 12 has a function of transmitting a signal SE. It has.

[0024] A signal OUT is output from the wiring 16. The signal OUT is an output signal of the semiconductor device. Furthermore, the signal OUT is a digital signal, and the high level potential of the signal OUT is VH. The low level potential of the signal OUT is VL1. It has a function.

[0025] The wiring 11, the wiring 12, and the wiring 16 are also called signal lines. The signal SE is also called a control signal, and the signal OUT is also called an output signal.

[0026] The circuit 100 has a function of generating a signal INO by applying an offset to the signal IN. That is, the circuit 100 generates a signal INO that is a signal IN whose potential is lowered by the offset voltage. The circuit 100 also has a function of outputting a signal INO to the circuit 110. do.

[0027] The low-level potential of the signal INO is lower than the potential VL1 of the wiring 13. In addition, the high level potential of the signal INO is preferably a potential that exceeds VL1 and is lower than VH. Desirable.

[0028] The circuit 110 sets the signal OUT to a high level in response to the signal INO (the output signal of the circuit 100). For example, the circuit 110 has a function of selecting whether the inverter is at a high level or a low level. When functioning as a timer circuit, the circuit 110 outputs the signal INO when the signal INO is high. When the signal INO is at low level, the signal OUT is at high level. The circuit 110 also controls the potential of the wiring 15 in response to the signal INO. The potential detecting section 14 has a function of selecting whether to output the potential of the wiring 13 to the wiring 16 or to output the potential of the wiring 13 to the wiring 16 . For example, when the signal INO is at a high level, the circuit 110 supplies the potential of the wiring 13 to the wiring 16. and when the signal INO is at a low level, outputs the potential of the wiring 15 to the wiring 16. The circuit 110 also has the function of setting the high level of the signal OUT by a bootstrap operation. The potential of the bell is equalized to the potential VH of the wiring 15.

[0029] Next, specific examples of the circuit 100 and the circuit 110 will be described with reference to FIG.

[0030] The circuit 100 includes a capacitor 101 and a transistor 102. The first electrode of the transistor 102 is connected to the wiring 11. The first terminal of the transistor 102 is connected to a wiring 14, and the second terminal of the transistor 102 is connected to a capacitor. The other electrode of the transistor 101 is connected to a wiring 12 , and the gate of the transistor 102 is connected to a wiring 12 .

[0031] The circuit 110 includes a transistor 111, a transistor 112, a transistor 113, and a transistor 114. The first terminal of the transistor 111 is connected to the wiring 15. The second terminal of the transistor 111 is connected to the wiring 16. The first terminal of the transistor 112 is connected to the wiring 16. The first terminal of the transistor 112 is connected to the wiring 13, the second terminal of the transistor 113 is connected to the wiring 16, and the The gate of transistor 112 is connected to the gate of transistor 114. The first terminal of the transistor 3 is connected to the wiring 15, and the second terminal of the transistor 113 is connected to the The gate of the transistor 111 is connected to the wiring 15. A first terminal of the transistor 114 is connected to the wiring 13, and a second terminal of the transistor 114 is connected to the wiring 13. The gate of the transistor 114 is connected to the gate of the capacitor 101. The gate of the transistor 111 is connected to the other electrode of another transistor (e.g. For example, the connection point of the transistors 113 and 114 is defined as a node N1.

[0032] The capacitor 101 holds the potential difference between the wiring 11 and the second terminal of the transistor 102. Therefore, when the second terminal of the transistor 102 is in a floating state, In response to a signal input to the wiring 11, the potential of the second terminal of the transistor 102 also changes. That is, the potential of the signal INO also changes in response to the signal IN.

[0033] The transistor 102 supplies a potential VL2 of the wiring 14 to the other electrode of the capacitor 101. The transistor 102 supplies a potential VL2 to the other electrode of the capacitor 101. The timing of this is controlled by a signal SE on a line 12.

[0034] Note that the transistor 102 applies a potential lower than the potential VL1 to the other electrode of the capacitor 101. Specifically, the transistor 102 is connected to the first terminal of the transistor 114. A potential lower than the potential of the capacitor 101 may be supplied to the other electrode of the capacitor 101.

[0035] The transistor 111 has a function of supplying the potential VH of the wiring 15 to the wiring 16. The transistor 111 has a function of holding a potential difference between the gate and the second terminal. Therefore, when the node N1 is in a floating state, if the potential of the wiring 16 rises, the node N The potential of 1 also increases.

[0036] When a signal is input to the wiring 15, the transistor 111 receives the signal from the wiring 15. to the wiring 16.

[0037] The transistor 112 has a function of supplying a potential VL1 of the wiring 13 to the wiring 16. The timing at which the transistor 112 supplies the potential VL1 to the wiring 16 is determined by the output of the circuit 100. The potential of the capacitor 101 is controlled by a signal INO (potential of the other electrode of the capacitor 101).

[0038] The transistor 113 supplies the potential VH of the wiring 15 to the gate of the transistor 111. The transistor 113 also supplies a potential VH to the gate of the transistor 111. After the supply, the supply of the potential VH to the gate of the transistor 111 is stopped. In addition, the transistor 113 operates after the transistor 111 is turned on. The potential VH is supplied to the gate of the transistor 111 until the power supply 113 is turned off.

[0039] The potential supplied from the transistor 113 to the gate of the transistor 111 is Any potential may be used as long as it turns on the starter 111.

[0040] The transistor 114 supplies the potential VL1 of the wiring 13 to the gate of the transistor 111. The transistor 114 supplies a potential VL1 to the gate of the transistor 111. The timing of this is controlled by the signal INO output from the circuit 100.

[0041] Note that the transistors included in the semiconductor device of this embodiment (for example, the transistor 102, Transistor 111, transistor 112, transistor 113, and transistor 114 ) have the same conductivity type. The following description will be given assuming that the transistor is an N-channel type.

[0042] Next, an example of a method for driving the semiconductor device of FIG. 1A will be described with reference to FIG. 1B. FIG. 1B is a timing chart for explaining a method of driving the semiconductor device of FIG. 1A. This is an example of a chart.

[0043] A method for driving the semiconductor device in FIG. 1A will be described separately for a period T0 and a period T1.

[0044] The period T0 is a period for holding the offset voltage in the capacitance element 101. The signal IN is set to a low level, and the potential of one electrode of the capacitor 101 is set to VL1. Then, the signal SE is set to a high level to turn on the transistor 102. The potential VL2 is supplied to the other electrode of the capacitor 101, and the potential of the other electrode of the capacitor 101 is Therefore, the capacitor 101 receives a low-level potential VL1 of the signal IN and a low-level potential VL2 of the signal IN. The difference between the potential VL1 and the potential VL2 of the wiring 14 supplied by the transistor 102 (VL1-VL2) This difference (VL1-VL2) corresponds to the offset voltage.

[0045] Note that in the period T0, the transistor 102 applies a potential lower than VL1 to the capacitor 101 The other electrode may be supplied with the other of the two.

[0046] In the period T1, the signal IN is offset to generate the signal INO. This is the period for driving the circuit 110. First, the signal SE is set to low level, and the transistor By turning off the capacitor 102, the other electrode of the capacitor 101 is brought into a floating state. Since the potential difference VL1-VL2 is maintained in the period T0, the signal IN A signal INO is generated, which is a signal obtained by subtracting a value corresponding to the potential difference VL1-VL2. When the signal IN goes low, the signal INO also goes low. When the signal IN goes high, the potential of the terminal VL1 goes below VL1. The high level potential of the signal INO also becomes a potential lower than VH.

[0047] Regarding the driving method of the semiconductor device of FIG. 1A in the period T1, when the signal IN is at a high level, The cases where the signal is high and where the signal is low will be described separately.

[0048] During the period T1, when the signal IN becomes high level, the signal INO also becomes high level. Therefore, the transistor 112 and the transistor 114 are turned on. VL1 is supplied to the wiring 16 by the transistor 112. In addition, the potential VL 1 is supplied to node N1 by transistor 114. The potential VH of the wiring 15 is also supplied by the transistor 113. The W (channel width) / L (channel length) ratio is set to be sufficiently larger than the W / L ratio of the transistor 113. If the voltage is set high, the potential of the node N1 will be such that the transistor 111 is turned off. Therefore, the transistor 111 is turned off. Therefore, the signal OUT becomes low level. The potential becomes VL1.

[0049] On the other hand, during the period T1, when the signal IN becomes low level, the signal INO also becomes low level. Therefore, the transistor 112 and the transistor 114 are turned off. The potential VH of the wiring 15 is supplied by the transistor 113, and therefore the potential of the node N1 is As a result, the transistor 111 is turned on, and the potential VH of the wiring 15 rises. The potential of the wiring 16 rises because the potential is supplied to the wiring 16 by the capacitor 111. The potential of the node N1 rises to a potential obtained by subtracting the threshold voltage of the transistor 113 from the potential VH. When this occurs, the transistor 113 is turned off, and the node N1 is in a floating state. Even in the free state, the potential of the wiring 16 rises. When the transistor 113 is turned off, the node N1 and the wiring 1 are connected between the first terminal and the second terminal. Therefore, as the potential of the wiring 16 rises, the potential difference between the wiring 16 and the node N1 is maintained. The potential further increases and becomes higher than the potential VH, which is the so-called bootstrap operation. Therefore, the signal OUT becomes high level and its potential becomes VH.

[0050] When a signal is input to the wiring 15, the signal on the wiring 15 is output to the wiring 16. For example, when a clock signal is input to the wiring 15, during a period when the signal IN is at a low level, In the figure, a clock signal is output from wire 15 to wire 16.

[0051] As described above, when the signal OUT is set to a high level, the gate of the transistor 114 Since the potential of the transistor 114 is less than VL1, the Vgs of the transistor 114 can be set to a negative value. Therefore, even if the transistor 114 is a depletion type, the transistor 1 Alternatively, if the Vgs of the transistor 114 is 0 [V], Even if the drain current of the transistor is large, the drain current of the transistor 114 Therefore, by making the gate of the transistor 111 in a floating state, This makes it possible to prevent the circuit 110 from malfunctioning.

[0052] Similarly to the transistor 114, the Vgs of the transistor 112 can also be set to a negative value. Therefore, even if the transistor 112 is a depletion type, Alternatively, if the Vgs of the transistor 112 is 0 [V Even if the drain current of the transistor 112 is large, Therefore, the current flowing from the wiring 16 to the wiring 13 can be prevented or reduced. can be suppressed, thereby reducing power consumption.

[0053] When the signal OUT is set to a low level, the transistor 112 and the transistor Since the potential of the gate of the transistor 114 is lower than VH, the transistors 112 and 114 Therefore, the Vgs of the transistor 112 and the transistor 114 can be reduced. This makes it possible to suppress deterioration of the star 114.

[0054] The method for driving the semiconductor device in FIG. 1A has been described above.

[0055] Next, regarding semiconductor devices different from those shown in FIG. 1(A), FIGS. 2(A), 2(B), and 3(A) are shown. ), and will be described with reference to Figs. 3(B), 4(A), 4(B), 5(A), and 5(B). In the following, only the differences from FIG. 1(A) will be explained.

[0056] As shown in FIG. 2A, the wiring 14 is omitted from the semiconductor device of FIG. 1A, and the transistor The first terminal of the transistor 102 may be connected to the wiring 13. The potential VL2 may be supplied to the wiring 13, and the potential VL1 may be supplied to the wiring 13 in the period T1. In this case, the potential VL2 is supplied to the other electrode of the capacitor 101 during the period T0. Therefore, the semiconductor device can perform the same operation as that of the semiconductor device in FIG. The same effects as those of the semiconductor device shown in FIG. Therefore, the number of wirings can be reduced compared to the semiconductor device in FIG.

[0057] In the semiconductor device of FIG. 2A, the potential of the wiring 13 is set to the potential VL 1, and the potential of the wiring 11 may be set to a potential higher than the potential VL1 and lower than the potential VH. Even in this case, when the signal IN is at a low level during the period T1, the capacitance element 101 The potential of the other electrode can be set lower than the potential VL1. Therefore, the same effect as that of the semiconductor device in FIG. In addition, since the power supply potential can be kept constant, the potential can be supplied to the wiring 13. This simplifies the configuration of the power supply circuit and the like.

[0058] As shown in FIG. 2B, the wiring 14 is omitted from the semiconductor device of FIG. 1A, and the transistor The first terminal of the transistor 102 may be connected to the wiring 15. The potential VL2 may be supplied to the wiring 15, and the potential VH may be supplied to the wiring 15 in the period T1. In this case, the potential VL2 is supplied to the other electrode of the capacitor 101 during the period T0. Therefore, the semiconductor device can operate in the same manner as the semiconductor device in FIG. The same effects as those of the semiconductor device of 1(A) can be achieved. Therefore, the number of wirings can be reduced compared to the semiconductor device in FIG.

[0059] As shown in FIG. 3A, the wiring 14 is omitted from the semiconductor device of FIG. 1A, and the transistor The first terminal of the transistor 102 is connected to the wiring 12, and the second terminal of the transistor 102 is connected to the wiring 12. The gate may be connected to the other electrode of the capacitor 101. Alternatively, the signal SE may be set to a low level and the signal SE may be set to a high level during the period T1. However, the other electrode of the capacitor 101 can be set to a potential lower than VL1 during the period T0. Therefore, the semiconductor device can operate in the same manner as the semiconductor device shown in FIG. The same effects as those of the semiconductor device can be achieved. In addition, the wiring 14 can be omitted. Therefore, the number of wirings can be reduced compared to the semiconductor device in FIG.

[0060] As shown in FIG. 3B, in the semiconductor device of FIG. 1A, the wiring 12 and the wiring 14 are The first terminal of the transistor 102 is connected to the wiring 13, and the third terminal of the transistor 102 is connected to the wiring 14. The terminal and gate of the capacitor 101 may be connected to the other electrode of the capacitor 101. The potential VL2 is supplied to the wiring 13 during the period T1, and the potential VL1 is supplied to the wiring 13 during the period T2. In this case, the other electrode of the capacitor 101 may be set to the potential VL1 Therefore, the semiconductor device can operate in a manner similar to that of the semiconductor device shown in FIG. Therefore, the same effect as that of the semiconductor device shown in FIG. In addition, the wiring 14 can be omitted, so the number of wirings is reduced compared to the semiconductor device of FIG. can be reduced.

[0061] As shown in FIG. 4A, in the semiconductor device of FIG. 1A, the wiring 12 and the wiring 14 are The first terminal of the transistor 102 is connected to the wiring 15, and the third terminal of the transistor 102 is connected to the wiring 16. The terminal and gate of the capacitor 101 may be connected to the other electrode of the capacitor 101. A potential VL2 is supplied to the wiring 15 during a period T1, and a potential VH is supplied to the wiring 15 during a period T2. In this case, the other electrode of the capacitor 101 may be set to a potential lower than VL1 during the period T0. Since the voltage can be fully charged, the semiconductor device can operate in a manner similar to that of the semiconductor device in FIG. Therefore, the same effect as that of the semiconductor device of FIG. Since the wiring 14 can be omitted, the number of wirings can be reduced compared to the semiconductor device of FIG. It can be reduced.

[0062] As shown in FIG. 4B, in the semiconductor device of FIG. 1A, The gate may be connected to the wiring 11. In the semiconductor device of FIG. The timing at which the potential VL1 of the wiring 13 is supplied to the wiring 16 is controlled by a signal IN. The IN signal has a shorter fall time and rise time than the INO signal, so the transistor Compared with the case where the gate of the transistor 112 is connected to the other electrode of the capacitance element 101, Therefore, the timing at which the wire 13 turns on or off can be accelerated. The timing at which the potential VL1 is supplied to the wiring 16 also becomes earlier. In addition, the timing at which the transistor 112 is turned off can be shortened. This shortens the time during which a through current occurs between the wiring 15 and the wiring 13. Therefore, power consumption can be reduced.

[0063] As with the semiconductor device of FIG. 4(B), the semiconductor devices of FIGS. 2(A), 2(B), 3(A), and 3 In the semiconductor device of FIG. 4B and FIG. 4A, the gate of the transistor 112 is connected to the wiring 1. 1. In this case, the same effect as that of the semiconductor device of FIG. can be done.

[0064] As shown in FIG. 5A, in the semiconductor device of FIG. 1A, the first terminal is connected to the wiring 13. The second terminal is connected to the gate of the transistor 111, and the gate is connected to the wiring 12. The transistor 115 may be connected to the wiring 13. L1 to the gate of the transistor 111. The timing at which the potential VL1 is supplied to the gate of the transistor 111 is determined by the signal SE on the wiring 12. In the semiconductor device of FIG. 5A, the potential VL1 of the wiring 13 is controlled in the period T0. can be supplied to the gate of the transistor 111, thereby initializing the semiconductor device. Therefore, malfunction of the semiconductor device can be prevented.

[0065] In the semiconductor device of FIG. 5A, the first terminal of the transistor 115 is connected to the wiring 14. In this case, the first terminal of the transistor 115 may be connected to the wiring 13. The same operation can be performed as when

[0066] Note that the timing to acquire the offset voltage may differ from the timing to perform initialization. In this case, the gate of the transistor 115 may be connected to a wiring to which an initialization signal is input. stomach.

[0067] 2(A), 2(B), 3(A), 3(B), 4(A) and 4(B) In this semiconductor device, the first terminal is connected to the wiring 13 or the wiring 14, and the second terminal is Transistor 111 is connected to the gate of transistor 111, and the gate of transistor 111 is connected to wiring 12. In this case, the same effect as that of the semiconductor device shown in FIG. can be done.

[0068] As shown in FIG. 5B, in the semiconductor device of FIG. 1A, The terminal and gate of the second transistor may be connected to a wiring 17. A potential VH may be supplied to the wiring 17. Alternatively, a potential exceeding the potential VL1 and less than the potential VH may be supplied, or a signal may be input. An example of a signal input to the wiring 17 is an inverted signal of the signal IN. 11 may be connected to the wiring 17 via an inverter circuit. When 114 is turned on, the transistor 113 is turned off, so that the wiring 15 and the wiring 13 Therefore, it is possible to reduce power consumption. In addition, the W / L ratio of the transistor 114 can be set to be smaller than that of the transistor 113. The size of the transistor can be reduced because it no longer needs to be large enough .

[0069] In addition, Figures 2(A), 2(B), 3(A), 3(B), 4(A), 4(B) and 5A, the second terminal and the gate of the transistor 113 are also arranged. It may be connected to the line 17. In this case, the same effect as that of the semiconductor device of FIG. It is possible.

[0070] As shown in FIG. 22(A), the wiring 14 is omitted from the semiconductor device of FIG. 1(A), and the The first terminal of the transistor 102 is connected to the wiring 13, and one electrode is connected to the wiring 12. A capacitor 103 having the other electrode connected to the other electrode of the capacitor 101 may be provided. The capacitor 103 has a function of maintaining a potential difference between the wiring 12 and the other electrode of the capacitor 101. In the semiconductor device of FIG. 22A, the transistor 102 has a function of The semiconductor device shown in FIG. In the device, during a period T0, a low-level signal IN is applied to one electrode of the capacitor element 101. The other electrode of the capacitor 101 is connected to the potential VL1 of the wiring 13. Then, when the signal SE goes from high to low, the transistor The capacitor 102 is turned off, and the potential of the other electrode of the capacitor 101 is the capacitance of the capacitor 103. Therefore, in the period T0, the potential of the other capacitive element 101 decreases from the potential VL1 due to capacitance coupling. Since the potential of the electrode can be set to a potential lower than VL1, the semiconductor device can operate in the same manner as that of FIG. Therefore, the same effect as that of the semiconductor device of FIG. In addition, since the wiring 14 can be omitted, the semiconductor device shown in FIG. In addition, since the potential VL2 is not required, the number of power supply potentials can be reduced. can be reduced.

[0071] As shown in FIG. 22B, in the semiconductor device of FIG. 22A, the transistor 102 The first terminal of the low-level transistor 11 may be connected to the wiring 11. The signal IN of the capacitor is supplied to the other electrode of the capacitor element 101 by the transistor 102. Therefore, the semiconductor device can operate in the same manner as the semiconductor device in FIG. The same effects as those of the semiconductor device 22(A) can be achieved.

[0072] In the semiconductor device of FIGS. 22(A) and 22(B), the capacitor element 103 is omitted. In this case, instead of the capacitor 103, the gate and the second It is recommended to use the parasitic capacitance between terminal 2.

[0073] In the semiconductor device of FIGS. 22A and 22B, one of the capacitors 103 The electrode may be connected to a new wiring different from the wiring 12. The signal input to this wiring is During the period T0, the signal SE changes from high to low. This is preferably a signal that goes to a high level, so that transistor 102 is turned off. After that, the potential of the other electrode of the capacitor 101 can be lowered. The timing at which the signal SE goes high is preferably during the period when the signal SE is high. stomach.

[0074] In addition, Fig. 2(A), Fig. 2(B), Fig. 3(A), Fig. 3(B), Fig. 4(A), Fig. 4(B), In the semiconductor device of FIGS. 5A and 5B, the wiring 14 is omitted and the transistor 1 The first terminal of the element O2 is connected to the wiring 11 or 13, and one electrode is connected to the wiring 12. A capacitor 103 having the other electrode connected to the other electrode of the capacitor 101 may be provided. .

[0075] Although not shown, Figs. 2(A), 2(B), 3(A), 3(B), 4(A), 4(B), 5(A), 5(B), 22(A) and 22(B) Therefore, a capacitor may be connected between the gate and the second terminal of the transistor 111. This makes it possible to increase the capacitance between the wiring 16 and the node N1. Compared to the case where no capacitance element is provided between the gate and the second terminal of the transistor 111, Therefore, the node N1 can be made higher during the period when the signal IN is at a low level. This means that the Vgs of the transistor 111 can be increased. The drain current of 11 can be increased, and the rise time of the signal OUT can be shortened. This can be done.

[0076] Although not shown, Figs. 2(A), 2(B), 3(A), 3(B), 4(A), 4(B), 5(A), 5(B), 22(A) and 22(B) Therefore, a MOS capacitor may be used as the capacitive element 101. In this case, The gate of the transistor is connected to the wiring 11, and the source or drain of the transistor is connected to the wiring 12. It is preferable to connect the second terminal of the transistor 102 to the potential of the wiring 11. Since the potential of the second terminal of the transistor 102 is higher than that of the second terminal of the transistor 102, the capacitance value per unit area is increased. It can be made easier.

[0077] The semiconductor device having a different structure from that shown in FIG. 1A has been described above.

[0078] The larger the W / L ratio of the transistor 111, the shorter the rise time of the signal OUT. Therefore, the W / L ratio of the transistor 111 can be reduced. It is preferable that the W / L ratio of the transistor 111 is the largest. is the W / L ratio of transistor 102, the W / L ratio of transistor 112, and the 3 and preferably greater than the W / L ratio of transistor 114.

[0079] The transistor 112 supplies a potential to a load connected to the wiring 16. The transistor 114 supplies a potential to the gate of the transistor 111. The larger the W / L ratio of 112, the shorter the fall time of the signal OUT can be. Thus, the W / L ratio of transistor 112 is greater than the W / L ratio of transistor 114. It is preferable.

[0080] Note that the transistor 102 supplies charge to the other electrode of the capacitor 101 during the period T0. Therefore, it is not necessary to increase the W / L ratio of the transistor 102. The W / L ratio of transistor 102 is the same as the W / L ratio of transistor 112 or transistor 114. It is preferable that it is smaller than

[0081] Note that the capacitance value of the capacitor 101 is the gate capacitance of the transistor 112 and the The larger the sum of the gate capacitances of 14, the greater the amplitude voltage of the signal INO becomes. Therefore, the capacitance of the capacitor 101 is closer to the gate of the transistor 112. It is preferable that the capacitance is larger than the sum of the capacitance of the capacitor and the gate capacitance of the transistor 114. One electrode of the capacitor 101 is made of the same material as the gate electrode of the transistor. If the other electrode of the capacitor is made of the same material as the source or drain electrode of the transistor, The area where one electrode of the capacitor 101 overlaps with the other electrode is equal to the gate of the transistor 112. the area where the gate and source of the transistor 112 overlap, the area where the gate and drain of the transistor 112 overlap, The area where the gate and source of the transistor 114 overlap, and the area where the gate and source of the transistor 114 overlap It is preferable that the area is larger than the sum of the overlapping areas of the rain and the rain.

[0082] Note that in the period T0, the potential VL1 is not supplied to the wiring 13, and the wiring 13 is in a floating state. Alternatively, in the period T0, the potential VH may not be supplied to the wiring 15, and the wiring 15 may be It may be in a floating state, which can prevent malfunction during the period T0.

[0083] Note that in the period T1, the potential VL2 is not supplied to the wiring 14, and the wiring 14 is in a floating state. You may do so.

[0084] During the period when the signal IN is at a high level, a signal at a low level is sent to the wiring 15. In this way, when transistor 114 is turned on, transistor 11 Since the transistor 3 is turned off, it is possible to prevent current from flowing between the wiring 15 and the wiring 13. Therefore, power consumption can be reduced. Since the W / L ratio of the transistor 114 does not need to be sufficiently large, The size of the transistor can be reduced.

[0085] This embodiment mode can be implemented in appropriate combination with other embodiment modes or the like.

[0086] (Embodiment 2) In this embodiment, a semiconductor device according to one embodiment of the present invention is used in a flash memory device. The case where the present invention is applied to a flip-flop circuit will be described. The differences from mode 1 will be explained below.

[0087] The semiconductor device of this embodiment mode will be described with reference to FIG. A circuit diagram of a semiconductor device in this embodiment mode is shown. The first terminal of the transistor 111 is connected to the wiring 23, and the gate of the transistor 113 is connected to the wiring 21. 1A, and one electrode of the capacitor 101 is connected to the wiring 22. This is different from the semiconductor device.

[0088] A signal IN1 is input to the wiring 21. The signal IN1 is an input signal of the semiconductor device. It is a signal that functions as a start pulse. For example, signal IN1 is a digital signal, and signal The high level potential of the signal IN1 is VH, and the low level potential of the signal IN1 is VL1. The wiring 21 has a function of transmitting a signal IN1.

[0089] A signal IN2 is input to the wiring 22. The signal IN2 is an input signal of the semiconductor device. For example, signal IN2 is a digital signal. The high level potential of the signal IN2 is VH, and the low level potential of the signal IN2 is VL1. The wiring 22 has a function of transmitting a signal IN2.

[0090] A signal CK is input to the wiring 23. The signal CK is an input signal to the semiconductor device. For example, , the signal CK is a digital signal, the high level potential of the signal CK is VH, The low level potential of the signal CK is VL1. The wiring 23 has a function of transmitting the signal CK.

[0091] The wiring 21, wiring 22, and wiring 23 are also called signal lines. Also called a signal line.

[0092] Next, an example of a method for driving the semiconductor device of FIG. 6A will be described with reference to FIG. FIG. 7 is an example of a timing chart for explaining a method for driving the semiconductor device of FIG. 6(A). is.

[0093] In the period T0, the signal IN2 is set to a low level, and the potential of one electrode of the capacitor 101 is set to The signal SE is set to high level to turn on the transistor 102. The potential VL2 of the wiring 14 is supplied to the other electrode of the capacitor 101. The potential of the other electrode of the capacitor 101 is VL2. The potential VL1 of the bell and the potential VL2 of the wiring 14 supplied by the transistor 102 The difference (VL1-VL2) is maintained. This difference (VL1-VL2) corresponds to the offset voltage. do.

[0094] During the period T1, the signal SE is set to a low level to turn off the transistor 102. The other electrode of the capacitor 101 is in a floating state. Since the potential difference VL1-VL2 is maintained, the signal IN2 is Therefore, when the signal IN2 goes low, the signal IN2O is generated. When this occurs, the signal IN2O also goes low, and the low-level potential of the signal IN2O is lower than VL1. When the signal IN2 goes high, the signal IN2O also goes high. The high level potential of the signal IN2O becomes a potential lower than VH.

[0095] Regarding the method of driving the semiconductor device of FIG. 6A in the period T1, The period Tc and the period Td will be described separately.

[0096] During the period Ta, the signal IN2 becomes low level, and the signal IN2O also becomes low level. The transistor 112 and the transistor 114 are turned off. Therefore, the potential VH of the wiring 15 is Since the potential of the node N1 is supplied to the node N1, the potential of the node N1 rises. Then, the transistor 111 is turned on, and the signal CK on the wiring 23 is supplied to the wiring 16. During the period Ta, the signal CK is at a low level, so the signal OUT is at a low level. Furthermore, when the potential of the node N1 is changed from VH to the threshold voltage of the transistor 113, the potential of the node N1 becomes VL1. When the potential at node N1 rises to the voltage lowered by the voltage, transistor 113 is turned off. When the transistor 113 is turned off, the node N1 and the wiring 1 6 is maintained between the gate and the second terminal of the transistor 111.

[0097] During the period Tb, the signal IN2 remains at a low level, so the signal IN2O also remains at a low level. and the transistors 112 and 114 remain off. Since the signal IN1 is at a low level, the transistor 113 remains off. The node N1 remains in a floating state. The potential of the node N1 is the same as the potential in the period Ta. Since the signal CK on line 23 is maintained, transistor 111 remains on, and the signal CK on line 23 is connected to line 1. During the period Tb, the signal CK is at a high level, so that the signal is supplied to the wiring 16. At this time, the potential of the transistor 111 increases. The potential difference between the node N1 and the wiring 16 during the interval Ta is maintained. As the potential at node N6 rises, the potential at node N1 rises further and becomes higher than VH. The signal OUT goes high and its potential goes to VH.

[0098] During the period Tc, the signal IN2 becomes high level and the signal IN2O becomes high level. Therefore, the potential V L1 is provided to line 16 by transistor 112 and is further provided to line 16 by transistor 114. The signal IN1 remains at a low level, so the transistor Therefore, the potential of the node N1 becomes VL1, and the transistor 113 remains off. 111 is turned off. Therefore, the signal OUT becomes low level and its potential becomes VL1. .

[0099] During the period Td, the signal IN2 becomes low level and the signal IN2O becomes low level. When the signal IN1 is low, the transistor 112 and the transistor 114 are turned off. Since the voltage at node N1 remains at 0 V, transistor 113 remains off. The potential VL1 at Tc is maintained, and the transistor 111 is turned off. In order to maintain the potential VL1 during the period Tc, the signal OUT remains at the low level.

[0100] As described above, when the signal IN2 is set to a low level, the gate of the transistor 114 Since the potential of the transistor 114 is less than VL1, the Vgs of the transistor 114 can be set to a negative value. Therefore, even if the transistor 114 is a depletion type, the transistor 1 Alternatively, if the Vgs of the transistor 114 is 0 [V], Even if the drain current of the transistor is large, the drain current of the transistor 114 Therefore, by making the gate of the transistor 111 in a floating state, This makes it possible to prevent the circuit 110 from malfunctioning.

[0101] When the signal IN2 is set to a high level, the transistor 112 and the transistor Since the potential of the gate of the transistor 114 is lower than VH, the transistors 112 and 114 Therefore, the Vgs of the transistor 112 and the transistor 114 can be reduced. This makes it possible to suppress deterioration of the star 114.

[0102] The method for driving the semiconductor device of FIG. 6A has been described above.

[0103] Next, regarding semiconductor devices different from those shown in FIG. 6(A), FIGS. 6(B), 8(A), and 8(B) are shown. ), and will be described with reference to Figs. 9(A), 9(B) and 10(A). The differences from FIG. 6(A) will be explained below.

[0104] As shown in FIG. 6B, in the semiconductor device of FIG. 6A, The terminal 1 may be connected to the wiring 21. In the semiconductor device of FIG. During the period Ta, the transistor 113 supplies the signal IN1 of the wiring 21 to the node N1. Since the signal IN1 is at a high level, the potential of the node N1 rises. When the potential becomes VH minus the threshold voltage of transistor 113, transistor 1 During periods Tb, Tc, and Td, the transistor 113 is turned off. Therefore, the semiconductor device can operate in the same manner as in FIG. Therefore, the same effect as that of the semiconductor device of FIG. Therefore, the number of wirings can be reduced compared to the semiconductor device of FIG. 6A. Cut.

[0105] As shown in FIG. 8A, in the semiconductor device of FIG. 6B, the circuit 100 is Instead, they may be connected to the wiring 21. In the semiconductor device of FIG. An offset is applied to the signal IN1 of 21, and the signal IN1O obtained by applying an offset to the signal IN1 is The potential is supplied to the gate of the transistor 113. One electrode of the capacitor 101 is connected to the wiring 21. The other electrode of the capacitor 101 is connected to the gate of the transistor 113. A first terminal of the transistor 102 is connected to the wiring 14, and a second terminal of the transistor 102 is connected to the capacitor The other electrode of the capacitor 101 is connected to the gate of the transistor 102, and the other electrode of the capacitor 101 is connected to the wiring 12. The capacitor 101 reduces the potential difference between the wiring 21 and the gate of the transistor 113. The transistor 102 has a function of holding the potential VL1 of the wiring 14. In the semiconductor device of FIG. 8A, Vgs can be set to a negative value. Therefore, there is no need to worry about the amount of charge supplied to node N1. In addition, the W / L ratio of the transistor 113 can be increased. This reduces the time it takes for the potential of the node N1 to reach a predetermined potential, and The number can be higher.

[0106] As shown in FIG. 8B, in the semiconductor device of FIG. 6B, the circuit 100 is connected to the wiring 22. In FIG. 8B, the circuit 1 is provided on the wiring 22. 100, a capacitor 101 and a transistor 102 included in the circuit 100 are respectively 0A, a capacitor 101A, and a transistor 102A. The circuit 100, the capacitor 101 and the transistor 102 included in the circuit 100 are 100B, a capacitor 101B, and a transistor 102B. The circuit 100A is shown in FIG. 8A, and the circuit 100B is the same as the circuit 100 shown in FIG. Therefore, the description thereof will be omitted. 8A. The semiconductor device of FIG. 8A can provide the same effects as those of the semiconductor device of FIG.

[0107] As shown in FIG. 9A, in the semiconductor device of FIG. 6A, the gate of the transistor 112 The port may be connected to the wiring 24. The signal IN3 is input to the wiring 24. The wiring 24 is a signal The signal IN3 is a digital signal, and the high level of the signal IN3 The potential of the high level of the signal IN3 is VH, and the low level of the signal IN3 is VL1. The clock signal may be an inverted signal of the signal CK or a clock signal whose phase is shifted from the signal CK. In the semiconductor device in FIG. 9A, during the period Td, Since the potential VL1 of the wiring 13 is repeatedly turned on and off, the potential VL1 of the wiring 13 is periodically supplied to the wiring 16. This makes it easier to maintain the potential of the wiring 16 at VL1.

[0108] In the semiconductor devices of FIGS. 6(B), 8(A), and 8(B), the transistor The gate of 112 may be connected to the wiring 24. In this case, the semiconductor device shown in FIG. The same effect can be achieved.

[0109] In the semiconductor devices of FIGS. 6(A), 6(B), 8(A) and 8(B), The first terminal is connected to the wiring 13, the second terminal is connected to the wiring 16, and the gate is connected to the wiring 24. In this case, the semiconductor device shown in FIG. The following effects can be achieved.

[0110] As shown in FIG. 9B, in the semiconductor device of FIG. 6A, the first terminal is connected to the wiring 23. The first terminal is connected to the wiring 25, and the gate is connected to the gate of the transistor 111. A transistor 116 may be provided connected to the line 23. The transistor 116 receives a signal C The transistor 116 supplies the signal K from the wiring 23 to the wiring 25. The timing of supplying CK is controlled by the potential of the node N1. The capacitor 116 has a function of maintaining a potential difference between the wiring 25 and the node N1. A signal OUT is output from 25. The wiring 25 has the function of transmitting the signal OUT. In FIG. 9B, the signal OUT output from the wiring 16 is indicated as a signal OUTA, and the signal OUT from the wiring 2 is indicated as a signal OUTB. The signal OUT output from the output terminal 5 is indicated as the signal OUTB. The signal inverts between high and low levels at the same timing. In the device, one of the signals OUTA and OUTB is used as a signal for transferring the shift register. The other of the signals OUTA and OUTB can be used as a signal for driving a load or the like. Therefore, by using the semiconductor device of FIG. 9B in a flip-flop circuit, It can operate normally even when driving a large load.

[0111] In addition, in the semiconductor devices of FIGS. 6(B), 8(A), 8(B), and 9(A), The first terminal is connected to the wiring 23, the second terminal is connected to the wiring 25, and the gate is connected to the transistor A transistor 116 connected to the gate of the transistor 111 may be provided. The semiconductor device of 9(B) can achieve the same effects as those of the semiconductor device of 9(B).

[0112] As shown in FIG. 10A, in the semiconductor device of FIG. 6A, The circuit 120 may include a node N1, a wiring 12, and a capacitor 1 The circuit 120 is connected to one electrode of the node N1 and the signal SE of the wiring 12. and outputs the signal IN2 to one electrode of the capacitor element 101. For example, when the signal SE is at a high level, the circuit 120 calculates the potential of the node N1. Furthermore, the circuit 120 keeps the signal IN2 at a low level regardless of whether the signal SE is at a low level. In some cases, when the potential of the node N1 is high (period Ta, period Tb, etc.), the signal IN2 is set low. When the potential of the node N1 is low (such as during periods Tc and Td), the signal IN2 is set to high level. That is, the circuit 120 functions as a NOR circuit.

[0113] Note that the circuit 120 may be connected to the wiring 16 instead of the node N1.

[0114] The semiconductor devices of FIGS. 6(B), 8(A), 8(B), 9(A) and 9(B) In this case, a circuit 120 for generating the signal IN2 may be provided.

[0115] Although not shown, Figs. 6(A), 6(B), 8(A), 8(B), 9(A), In the semiconductor devices of Figs. 9(B) and 10(A), the transistors are the same as in the semiconductor device of Fig. 2(A). The second terminal of the transistor 102 may be connected to the wiring 13. In this case, the same as in FIG. The same effects as those of the semiconductor device are achieved.

[0116] Although not shown, Figs. 6(A), 6(B), 8(A), 8(B), 9(A), In the semiconductor device of FIG. 9(B) and FIG. 10(A), similarly to the semiconductor device of FIG. 2(B), The second terminal of the transistor 102 may be connected to the wiring 15. In this case, the same as in FIG. This provides the same effects as the semiconductor device described above.

[0117] Although not shown, Figs. 6(A), 6(B), 8(A), 8(B), 9(A), In the semiconductor devices of Figs. 9(B) and 10(A), similarly to the semiconductor device of Fig. 3(A), The first terminal of the transistor 102 is connected to the wiring 12, and the gate of the transistor 102 is connected to the transistor 104. The second terminal of the transistor 102 may be connected to the second terminal of the transistor 102. In this case, the semiconductor device of FIG. has the same effect.

[0118] Although not shown, Figs. 6(A), 6(B), 8(A), 8(B), 9(A), In the semiconductor device of FIG. 9(B) and FIG. 10(A), similarly to the semiconductor device of FIG. 3(B), The first terminal of the transistor 102 is connected to the wiring 13, and the gate of the transistor 102 is connected to the transistor 104. The second terminal of the transistor 102 may be connected to the second terminal of the transistor 102. In this case, the semiconductor device shown in FIG. has the same effect.

[0119] Although not shown, Figs. 6(A), 6(B), 8(A), 8(B), 9(A), In the semiconductor devices of Figs. 9(B) and 10(A), similarly to the semiconductor device of Fig. 4(A), The first terminal of the transistor 102 is connected to the wiring 15, and the gate of the transistor 102 is connected to the transistor 104. The second terminal of the transistor 102 may be connected to the second terminal of the transistor 102. In this case, the semiconductor device of FIG. has the same effect.

[0120] Although not shown, Figs. 6(A), 6(B), 8(A), 8(B), 9(A), In the semiconductor device of FIG. 9(B) and FIG. 10(A), similarly to the semiconductor device of FIG. 4(B), The gate of the transistor 112 may be connected to one electrode of the capacitor 101. The semiconductor device of FIG. 4B also has the same effect as that of the semiconductor device of FIG.

[0121] Although not shown, Figs. 6(A), 6(B), 8(A), 8(B), 9(A), In the semiconductor device of FIG. 9(B) and FIG. 10(A), similarly to the semiconductor device of FIG. 5(A), The first terminal is connected to the wiring 13, the second terminal is connected to the gate of the transistor 111, A transistor 115 whose gate is connected to the wiring 12 may be provided. The same effects as those of the semiconductor device (A) are achieved.

[0122] Although not shown, Figs. 6(A), 6(B), 8(A), 8(B), 9(A), 9(B) and 10(A), the semiconductor device of FIG. 22(A) and FIG. 22(B) As in the semiconductor device, the wiring 14 is omitted, and the first terminal of the transistor 102 is connected to the wiring 22 or the wiring 30. One electrode is connected to the wiring 12 and the other electrode is connected to the other electrode of the capacitor element 101. A capacitor 103 may be provided connected to one electrode of the capacitor 103. The same effects as those of the semiconductor device in FIG. 22(B) are achieved.

[0123] The semiconductor device of this embodiment mode, which has a different structure from that shown in FIG. 6A, has been described above.

[0124] Next, a specific example of the circuit 120 will be described.

[0125] FIG. 10B is a circuit diagram of the circuit 120. The circuit 120 includes a transistor 121, a transistor 122, a transistor 123, a transistor 124, a transistor 125, a transistor 126, a transistor 127, a transistor 128, a transistor 129, a transistor 130, a transistor 131, a transistor 132, a transistor 133, a transistor 134, a transistor 1 The first terminal of the transistor 121 is connected to a first terminal of the transistor 122 and a second terminal of the transistor 123. The second terminal of the transistor 121 is connected to the wiring 15, and the second terminal of the transistor 121 is connected to one electrode of the capacitor 101. The gate of the transistor 121 is connected to the wiring 15. The first terminal of the transistor 122 is connected to the wiring 13, and the second terminal of the transistor 122 is connected to the The gate of the transistor 122 is connected to the node N1. A first terminal of the transistor 123 is connected to the wiring 13, and a second terminal of the transistor 123 is connected to the capacitor The gate of the transistor 123 is connected to one electrode of the capacitor 101, and the gate of the transistor 123 is connected to the wiring 12. can be.

[0126] The transistor 121 has a function of supplying a potential VH of the wiring 15 to one electrode of the capacitor 101. The transistor 122 applies the potential VL1 of the wiring 13 to one electrode of the capacitor 101. The transistor 123 supplies a potential VL1 of the wiring 13 to the capacitor 101. The transistor 122 has a function of supplying a potential VL of the wiring 13 to one electrode of the The timing at which the potential of the node N1 is supplied to one electrode of the capacitor 101 is controlled by the potential of the node N1. The transistor 123 supplies the potential VL1 of the wiring 13 to one electrode of the capacitor 101. The timing of supplying the signal is controlled by the signal SE on the line 12.

[0127] During the period T0, the signal SE goes high, so that the transistor 123 is turned on. Therefore, regardless of whether the transistor 122 is on or off, the potential VL1 of the wiring 13 The signal IN2 is supplied to one electrode of the capacitor 101 by the transistor 123. becomes low level.

[0128] During the period T1, the signal SE is at a low level, so that the transistor 123 is turned off. Therefore, when the potential of the node N1 becomes high and the transistor 122 is turned on, The potential VL1 of the wiring 13 is supplied to one electrode of the capacitor 101 by the transistor 122. On the other hand, the potential of the node N1 becomes low, and the When the transistor 122 is turned off, the potential VL1 of the wiring 13 is applied to one side of the capacitor 101. Since no current is supplied to the electrode, the signal IN2 goes high.

[0129] As shown in FIG. 10C, in the circuit 120 of FIG. 10B, the transistor 124, transistor 125, and transistor 126 may be provided. A first terminal of the transistor 124 is connected to the wiring 15, and a second terminal of the transistor 124 is connected to the capacitor element 10. The gate of transistor 124 is connected to one electrode of transistor 121. a terminal connected to the second terminal of the transistor 122 and the second terminal of the transistor 123; A first terminal of the transistor 125 is connected to the wiring 13, and a second terminal of the transistor 125 is connected to the wiring 13. The terminal of the transistor 125 is connected to one electrode of the capacitor 101, and the gate of the transistor 125 is connected to the node The first terminal of the transistor 126 is connected to the wiring 13, and the second terminal of the transistor 126 is connected to the wiring 13. The second terminal of the transistor 126 is connected to one electrode of the capacitor 101. The gate is connected to the wiring 12. In the semiconductor device of FIG. 10(C), bootstrap operation By using this, the high level potential of the signal IN2 can be set to VH, and the low level potential of the signal IN2 can be set to VH. The potential of the upper level can be set to VL1.

[0130] In the circuit 120 in FIG. 10C, the wiring 23 may be used instead of the wiring 15. That is, the first terminal of the transistor 121, the gate of the transistor 121, and the The first terminal of the transistor 124 may be connected to the wiring 23. In this way, during the period Td, Therefore, the signal IN2 can be a signal that alternates between high and low levels. This allows the time that the transistors 112 and 114 are turned on to be shortened. Therefore, deterioration of the transistors 112 and 114 can be suppressed.

[0131] A specific example of the circuit 120 has been described above.

[0132] If the signal IN2 is set to a high level during all or part of the period Td, Therefore, the potential of the wiring 13 is The signal is supplied to the wiring 16 by the transistor 112 and then to the node 114 by the transistor 114. Therefore, even during the period Td, the potentials of the wiring 16 and the node N1 are It becomes easier to maintain VL1.

[0133] This embodiment mode can be implemented in appropriate combination with other embodiment modes or the like.

[0134] (Embodiment 3) In this embodiment, the semiconductor device described in the second embodiment is used as a flip-flop circuit. In this embodiment, the shift register circuit used as the The differences from modes 1 and 2 are explained below.

[0135] The shift register circuit of this embodiment will be described with reference to FIG. 11. 11 shows a circuit diagram of a shift register circuit according to the present embodiment. has N (N is a natural number) flip-flop circuits 200. However, in FIG. The first to third stage flip-flop circuits 200 (flip-flop circuit 200_1, flip-flop circuit 200_2, flip-flop circuit 200_3) 2, only flip-flop circuits 200_2 and 200_3 are shown.

[0136] In the shift register circuit of FIG. 11, the flip-flop circuit 200 is A) is used in the flip-flop circuit 200. The semiconductor device is not limited to A), and the semiconductor device in the second embodiment may be used as appropriate. It is Noh.

[0137] The connection relationship of the shift register circuit in FIG. 11 will be described. The flip-flop circuit 200 at any one stage is connected to the wiring 31 at the i-th stage (referred to as wiring 31_i). (i-1)th wiring 31 (referred to as wiring 31_i-1), (i+1)th wiring 31 (referred to as wiring 31_i+1), wiring 32, wiring 33, wiring 34, one of wiring 35 and wiring 36, and the wiring 37. Specifically, in the flip-flop circuit 200 in the i-th stage, , the wiring 16 is connected to the wiring 31 in the i-th stage, and the wiring 21 is connected to the wiring 31 in the (i-1)-th stage. The wiring 22 is connected to the wiring 31 of the (i+1)th stage. The wiring 15 is connected to the wiring 32. , the wiring 13 is connected to the wiring 33, the wiring 14 is connected to the wiring 34, and the wiring 23 is connected to the wiring 35. The first flip-flop 11 is connected to one end of the wiring 36, and the wiring 12 is connected to the wiring 37. In the flip-flop circuit 200, the point where the wiring 21 is connected to the wiring 38 is the flip-flop circuit of the i-th stage. This is different from the flip-flop circuit 200.

[0138] A signal OUT is output from the wiring 31, and the wiring 31 has the function of transmitting the signal OUT. .

[0139] The potential VH is supplied to the wiring 32, and the wiring 32 has a function of transmitting the potential VH.

[0140] The potential VL1 is supplied to the wiring 33, and the wiring 33 has a function of transmitting the potential VL1.

[0141] The potential VL2 is supplied to the wiring 34, and the wiring 34 has a function of transmitting the potential VL2.

[0142] A signal CK1 is input to the wiring 35, and the wiring 35 has the function of transmitting the signal CK1. In addition, the signal CK2 is input to the wiring 36, and the wiring 36 has the function of transmitting the signal CK2. 1 and signal CK2 are signals similar to signal CK. However, signals CK1 and CK2 are signals that are inverted from each other or out of phase with each other.

[0143] A signal SE is input to the wiring 37, and the wiring 37 has a function of transmitting the signal SE.

[0144] A signal SP is input to the wiring 38, and the wiring 38 has a function of transmitting the signal SP. SP is the start pulse of the shift register circuit. It is a digital signal whose high level potential is VH and whose low level potential is VL1.

[0145] Next, an example of a method for driving the shift register circuit of FIG. 11 will be described with reference to FIG. FIG. 12 is a timing chart for explaining a method of driving the shift register circuit of FIG. 12 shows an example of a chart. In FIG. 12, the signal O of the first-stage flip-flop circuit 200 is UT, the signal OUT of the second stage flip-flop circuit 200, the signal OUT of the Nth stage flip-flop circuit The signals OUT on the path 200 are designated as signal OUT1, signal OUT2, and signal OUTN, respectively.

[0146] During the period T0, the signal SE is at a high level. Each of the flip-flop circuits 200 performs the operation in the period T0 described in the second embodiment. conduct.

[0147] During the period T1, the signal SE is at a low level. Each of the flip-flop circuits 200 performs the operation in the period T1 described in the second embodiment. Specifically, when the signal OUT of the (i-1)th flip-flop circuit 200 is at a high level, Then, the flip-flop circuit 200 at the i-th stage performs the operation in the period Ta described in the second embodiment. Therefore, the signal OUT of the flip-flop circuit 200 in the i-th stage is low level. After that, when the signals CK1 and CK2 are inverted, the i-th flip-flop The circuit 200 performs the operation during the period Tb described in the second embodiment. The signal OUT of the flip-flop circuit 200 becomes high level. The signal CK2 is inverted, and the signal OUT of the flip-flop circuit 200 in the (i+1)th stage goes high. At this time, the flip-flop circuit 200 at the i-th stage operates during the period Tc Therefore, the signal OUT of the flip-flop circuit 200 in the i-th stage is low. After that, the signal OUT of the flip-flop circuit 200 at the (i-1)th stage again becomes high level. The flip-flop circuit 200 in the i-th stage continues to operate in the same manner as in the second embodiment until the level reaches the zero level. Therefore, the signal OUT of the flip-flop circuit 200 in the i-th stage maintains a low level.

[0148] The shift register circuit of FIG. 11 uses the semiconductor of FIG. 6(A) as the flip-flop circuit 200. Since the semiconductor device is used, the same effects as those of the semiconductor device in FIG. 6(A) can be achieved.

[0149] The method for driving the shift register circuit of FIG. 11 has been described above.

[0150] In the shift register circuit of FIG. 11, the wiring 37 is omitted, and each flip-flop In the circuit 200, the wire 12 may be connected to the wire 38. This reduces the number of wires. In addition, an offset voltage can be periodically held in the capacitor element 101. do.

[0151] When the semiconductor device shown in FIG. 9A is used as the flip-flop circuit 200, When connecting 23 to wiring 35, it is preferable to connect wiring 24 to wiring 36. In this way, an increase in the number of wirings can be suppressed.

[0152] When the semiconductor device of FIG. 9B is used as a flip-flop circuit, the wiring 25 It is preferable to connect the wiring 31 and the wiring 16 to a load. The flip-flop circuit 200 of another stage is driven by the signal OUTB of the wiring 25 that does not receive the Therefore, the shift register circuit can be driven stably.

[0153] This embodiment mode can be implemented in appropriate combination with other embodiment modes or the like.

[0154] (Fourth embodiment) In this embodiment, a display device using the shift register circuit of the third embodiment as a driving circuit is This section explains the location.

[0155] In addition, a part or the whole of the driver circuit is formed on the same substrate as the pixel section, and the system is A panel can be formed.

[0156] Display elements used in display devices include liquid crystal elements (also called liquid crystal display elements), light-emitting elements (light-emitting The light-emitting element is a light-emitting element that emits light by applying a current or a voltage. It includes elements whose intensity can be controlled, specifically inorganic EL (Electro L Also, electronic ink and other electrically-activated A display medium whose contrast changes depending on the light source can also be applied.

[0157] In FIG. 13A, a pixel portion 4002 is provided on a first substrate 4001. A sealant 4005 is provided on the substrate 4002, and the substrate 4002 is sealed with a second substrate 4006. In FIG. 13(A), the first substrate 4001 is surrounded by a sealing material 4005. In a region different from the above, a scanning line driver circuit 4004 and a signal line driver circuit are provided on a separately prepared substrate. A signal line driver circuit 4003 and a scanning line driver circuit 4004 are also mounted. Various signals and potentials given to the driving circuit 4004 or the pixel portion 4002 are transmitted through the FPC 4018. a(Flexible printed circuit), supplied from FPC4018b It has been done.

[0158] In FIG. 13B and FIG. 13C, the pixel portion 4 is provided on the first substrate 4001. A sealant 4005 is provided so as to surround the gate electrode 4002 and the scanning line driver circuit 4004. In addition, a second substrate 4006 is provided on the pixel portion 4002 and the scanning line driver circuit 4004. Therefore, the pixel portion 4002 and the scanning line driver circuit 4004 are connected to the first substrate 400. The display element is sealed with a sealing material 4005 and a second substrate 4006. In FIG. 13B and FIG. 13C, the sealant 4005 on the first substrate 4001 In an area different from the area surrounded by the 13(B) and 13(C), a separately formed signal is A scanning line driver circuit 4003 and a scanning line driver circuit 4004 or a pixel portion 4002 are connected to the scanning line driver circuit 4003 and the pixel portion 4002. The seed signal and potential are supplied from the FPC4018.

[0159] In addition, in FIG. 13(B) and FIG. 13(C), a signal line driver circuit 4003 is separately formed. 10, an example in which the scanning element 4001 is mounted on the first substrate 4001 is shown, but the present invention is not limited to this configuration. A signal line driver circuit may be formed separately and mounted, or a part of the signal line driver circuit or the scanning line driver circuit may be mounted. Only a part of the path may be formed separately and mounted.

[0160] The method of connecting the separately formed drive circuit is not particularly limited, and may be a COG (C Hip On Glass method, wire bonding method, or TAB (Tape On Glass) method The Automated Bonding method can be used. 4003 and a scanning line driver circuit 4004 are mounted by the COG method. FIG. 13B shows an example in which a signal line driver circuit 4003 is mounted by the COG method. 13(C) is an example in which the signal line driver circuit 4003 is mounted by the TAB method.

[0161] The display device includes a panel in which a display element is sealed, and a controller for the panel. This includes modules in which ICs, etc., including lasers, are mounted.

[0162] In this specification, the term "display device" refers to an image display device, a display device, or Refers to light sources (including lighting devices). Also refers to connectors such as FPC or TAB tape. or a module with TCP attached, a printed wiring board at the end of TAB tape or TCP A module with a display element or a display element with an IC (integrated circuit) directly mounted on it using the COG method. All installed modules are also included in the display device.

[0163] In addition, the pixel portion provided over the first substrate includes a plurality of transistors.

[0164] When liquid crystal elements are used as display elements, thermotropic liquid crystals, low molecular weight liquid crystals, polymer Liquid crystal, polymer dispersed liquid crystal, ferroelectric liquid crystal, antiferroelectric liquid crystal, etc. are used. Depending on the conditions, the phase can be cholesteric, smectic, cubic, chiral nematic, etc. It shows the crystalline phase, isotropic phase, etc.

[0165] Alternatively, a liquid crystal that exhibits a blue phase without using an alignment film may be used. When the temperature of the cholesteric liquid crystal is increased, the cholesteric phase transitions to the isotropic phase. The blue phase appears only in a narrow temperature range, so it is necessary to improve the temperature range. To improve the liquid crystal layer, it is recommended to use a liquid crystal composition containing 5% by weight or more of a chiral agent. A liquid crystal composition containing a liquid crystal exhibiting a blue phase and a chiral agent has a response speed of 1 msec or less. It is short and optically isotropic, so alignment treatment is not required and the viewing angle dependency is small. Since there is no need to provide a film, rubbing treatment is not required. This prevents electrostatic breakdown caused by the liquid crystal display device during the manufacturing process. Therefore, it is possible to improve the productivity of the liquid crystal display device.

[0166] The specific resistance of the liquid crystal material is 1×10 9Ω·cm or more, preferably 1×10 1 1 Ω·cm or more, and more preferably 1×10 12 Ω·cm or more. The specific resistance values ​​in the specification are those measured at 20°C.

[0167] The size of the storage capacitor provided in the liquid crystal display device is determined by the The capacitance is set to be able to hold charge for a predetermined period, taking into consideration factors such as the current flowing through the capacitor. The magnitude may be set in consideration of the off-state current of the transistor and the like.

[0168] There are two types of LCD displays: TN (Twisted Nematic) mode, IPS (In- Plane-Switching mode, FFS (Fringe Field Switching) mode tching) mode, ASM(Axially Symmetric aligned) Micro-cell) mode, OCB(Optical Compensated) Birefringence mode, FLC (Ferroelectric Liquid Crystal id Crystal) mode, AFLC (AntiFerroelectric Li Use modes such as Quid Crystal.

[0169] Furthermore, normally black type liquid crystal display devices, such as those employing vertical alignment (VA) mode, The vertical alignment mode may be a transmission type liquid crystal display device. For example, MVA (Multi-Domain Vertical Alignment) ) mode, PVA (Patterned Vertical Alignment) mode Mode, ASV mode, etc. can be used.

[0170] It can also be applied to VA type liquid crystal display devices. VA type liquid crystal display devices are: It is a type of method for controlling the alignment of liquid crystal molecules in a liquid crystal display panel. VA type liquid crystal display devices are When no voltage is applied, the liquid crystal molecules are oriented perpendicular to the panel surface. In addition, a pixel is divided into several regions (subpixels), each of which is oriented in a different direction. This is called multi-domain or multi-domain design, which is designed to knock down molecules. The following method can be used.

[0171] In addition, in display devices, black matrices (light-shielding layers), polarizing members, phase difference members, reflectors, Optical members (optical substrates) such as anti-reflection members are provided as appropriate. Circular polarization by the substrate may be used. Also, a backlight, a sidelight, etc. may be used as a light source. It may be used.

[0172] In addition, the display method in the pixel section uses the progressive method, interlace method, etc. In addition, the color elements controlled by pixels when displaying colors are RGB (R is red, G is green, and B is blue). For example, RGBW (W is white) ), or RGB plus one or more colors such as yellow, cyan, magenta, etc. The size of the display area may be different for each dot of the color element. The invention is not limited to color display devices, but is also applicable to monochrome display devices. You can also do this.

[0173] In addition, a light-emitting device using electroluminescence is used as a display element included in the display device. The light-emitting element using electroluminescence can be applied to a light-emitting material. They are classified according to whether the material is an organic compound or an inorganic compound. The latter is called an inorganic EL element.

[0174] In an organic EL element, when a voltage is applied to the light-emitting element, electrons and The holes are injected into the layers containing the light-emitting organic compounds, causing a current to flow. The recombination of carriers (electrons and holes) causes light-emitting organic compounds to transition to an excited state. The excited state is formed, and light is emitted when it returns to the ground state. The light emitting element is called a current excitation type light emitting element.

[0175] Inorganic EL elements are classified into dispersion-type inorganic EL elements and thin-film-type inorganic EL elements depending on the element structure. Dispersion-type inorganic EL elements have a light-emitting layer in which particles of light-emitting material are dispersed in a binder. The emission mechanism is a donor- The thin-film inorganic EL element is an acceptor recombination type luminescence element. The luminescent layer is sandwiched between dielectric layers. The structure is sandwiched between electrodes, and the light emission mechanism is the inner shell electron transition of the metal ion. This is the localized light emission that is utilized.

[0176] It is also possible to provide electronic paper that drives electronic ink as a display device. Electronic paper is also called an electrophoretic display (electrophoretic display), It has the same readability as paper, consumes less power than other display devices, and can be made thin and light. This has the advantage that:

[0177] The electrophoretic display device may have various forms, but the first particles have a positive charge. and a second particle having a negative charge are mixed with a solvent or solute. By applying an electric field to the microcapsules, By moving the particles in the capsule in opposite directions, only the color of the particles that have gathered on one side is displayed. The first particles or the second particles contain a dye, and in the absence of an electric field, The first particle and the second particle are different in color (including colorless). (Mm).

[0178] In this way, electrophoretic displays are designed so that materials with high dielectric constants move to areas with high electric fields. This is a display that utilizes the so-called dielectrophoretic effect.

[0179] The microcapsules dispersed in a solvent are called electronic ink. This electronic ink can be printed on surfaces such as glass, plastic, fabric, and paper. Furthermore, color display is possible by using color filters or particles containing pigments.

[0180] The first particles and the second particles in the microcapsules may be made of a conductive material or an insulating material. materials, semiconductor materials, magnetic materials, liquid crystal materials, ferroelectric materials, electroluminescent materials, A material selected from electrochromic materials, magnetophoretic materials, or a composite of these materials You can use the fee.

[0181] In addition, a display device using a twist ball display method can also be applied as electronic paper. The twist ball display method uses spherical particles painted in black and white as the display element. The electrode layer is disposed between the first electrode layer and the second electrode layer. A display method in which a potential difference is generated between the electrode layers to control the orientation of the spherical particles. is.

[0182] By applying the shift register circuit of the third embodiment to the display device described in this embodiment, Therefore, we have proposed a display device that can be stably driven even if the transistor is a depression type. It can be provided.

[0183] This embodiment mode can be implemented in appropriate combination with other embodiment modes or the like.

[0184] (Embodiment 5) In this embodiment, the semiconductor device of the first embodiment, the semiconductor device of the second embodiment, A transistor that can be used in the shift register circuit of the third embodiment and the display device of the fourth embodiment This section explains the data.

[0185] <About oxide semiconductors> The oxide semiconductor will be described in detail below.

[0186] The oxide semiconductor to be used is at least indium (In) or It is preferable that the material contains zinc (Zn). It is particularly preferable that the material contains In and Zn. A stabilizer for reducing variations in the electrical characteristics of transistors using oxide semiconductors It is preferable that the stabilizer further contains gallium (Ga). It is preferable to have tin (Sn) as a stabilizer. It is preferable to use aluminum (Al) as a stabilizer. It is preferable to have

[0187] Other stabilizers include lanthanides such as lanthanum (La) and cerium. (Ce), praseodymium (Pr), neodymium (Nd), samarium (Sm), europium Eu, Gadolinium (Gd), Terbium (Tb), Dysprosium (Dy), aluminium (Ho), erbium (Er), thulium (Tm), ytterbium (Yb), It may contain one or more of lutetium (Lu).

[0188] For example, oxide semiconductors include indium oxide, tin oxide, zinc oxide, and oxides of binary metals. oxides such as In-Zn oxides, Sn-Zn oxides, Al-Zn oxides, and Zn-Mg oxides, Sn-Mg oxides, In-Mg oxides, In-Ga oxides, ternary metals In-Ga-Zn oxide (also written as IGZO), In-Al-Zn oxides, In-Sn-Zn oxides, Sn-Ga-Zn oxides, Al-Ga-Zn oxides Oxides, Sn-Al-Zn oxides, In-Hf-Zn oxides, In-La-Zn oxides oxides, In-Ce-Zn oxides, In-Pr-Zn oxides, In-Nd-Zn oxides In-Sm-Zn oxides, In-Eu-Zn oxides, In-Gd-Zn oxides , In-Tb-Zn oxide, In-Dy-Zn oxide, In-Ho-Zn oxide, In-Er-Zn oxide, In-Tm-Zn oxide, In-Yb-Zn oxide, I n-Lu-Zn ​​oxide, In-Sn-Ga-Zn oxide, which is an oxide of a quaternary metal, In-Hf-Ga-Zn oxide, In-Al-Ga-Zn oxide, In-Sn-Al -Zn-based oxides, In-Sn-Hf-Zn-based oxides, In-Hf-Al-Zn-based oxides It can be used.

[0189] In-Ga-Zn oxide semiconductor materials have sufficiently high resistance in the absence of an electric field and can suppress the off-current sufficiently. It is possible to make the size of the semiconductor very small, and it has the advantage of having high field-effect mobility. Transistors using In-Sn-Zn oxide semiconductor materials are The field-effect mobility can be more than three times that of transistors using nitride semiconductor materials. These semiconductor materials have the advantage that the threshold voltage can be easily made positive. A suitable material for use in a transistor constituting a semiconductor device according to one embodiment of the present invention can be used. It is one.

[0190] Here, for example, In-Ga-Zn oxide refers to an oxide containing In, Ga, and Zn as its main components. The ratio of In, Ga, and Zn is not important. Metal elements other than Ga and Zn may be included.

[0191] In addition, as an oxide semiconductor, InMO3(ZnO) m (m>0 and m is not an integer ) may be used, where M is selected from Ga, Fe, Mn and Co. In addition, the oxide semiconductor is In3SnO 5(ZnO) n A material expressed as (n>0 and n is an integer) may be used.

[0192] For example, In:Ga:Zn=1:1:1 (=1 / 3:1 / 3:1 / 3) or In: In-Ga-Zn system with an atomic ratio of Ga:Zn=2:2:1 (=2 / 5:2 / 5:1 / 5) The oxide or an oxide having a similar composition can be used. 1:1:1(=1 / 3:1 / 3:1 / 3), In:Sn:Zn=2:1:3(=1 / 3: 1 / 6:1 / 2) or In:Sn:Zn=2:1:5 (=1 / 4:1 / 8:5 / 8) It is preferable to use an In-Sn-Zn oxide having an atomic ratio of 100% or an oxide having a composition close to that.

[0193] However, it is not limited to these, and the required semiconductor characteristics (mobility, threshold, variation, etc.) In order to obtain the required semiconductor properties, a material with an appropriate composition can be used. Carrier density, impurity concentration, defect density, atomic ratio of metal elements to oxygen, interatomic bond length, density It is preferable to set the degree etc. appropriately.

[0194] For example, high mobility can be obtained relatively easily with In-Sn-Zn oxides. However, even in In-Ga-Zn oxides, the mobility can be improved by reducing the defect density in the bulk. It can be raised.

[0195] For example, the atomic ratio of In, Ga, and Zn is In:Ga:Zn=a:b:c(a+b +c=1), the atomic ratio of the oxide is In:Ga:Zn=A:B:C (A+B+ C=1) is close to the oxide composition when a, b, and c are (a―A) 2 +(b-B) 2 +(c-C) 2 ≦r 2 The above expression means that r satisfies the above condition, and r can be set to, for example, 0.05. The same applies to other oxides. .

[0196] In addition, the oxide semiconductor layer does not contain impurities such as moisture or hydrogen that act as electron donors (donors). It is preferable that the amount of impurities is reduced and the resulting material is highly purified. The body layer is analyzed using secondary ion mass spectrometry (SIMS). The hydrogen concentration measured by spectrometer was 5×10 19 / cm 3 Below, I prefer Or 5 x 10 18 / cm 3 Less than or equal to 5 × 10 17 / cm 3 Below are some more preferred Or 1 x 10 16 / cm 3 The oxides that can be measured by Hall effect measurement are as follows: The carrier density of the semiconductor layer is 1×10 14 / cm 3 Less than 1 x 10 12 / cm 3 less than 1×10 11 / cm 3 is less than.

[0197] Here, the analysis of the hydrogen concentration in the oxide semiconductor layer will be described. The concentration is measured by secondary ion mass spectrometry. In principle, SIMS analysis is performed on the sample surface. It is known that it is difficult to obtain accurate data on the interface between layers of different materials. Therefore, when analyzing the distribution of hydrogen concentration in the thickness direction of the layer using SIMS, Within the range where the target layer exists, the value does not fluctuate dramatically and a nearly constant value is obtained. The average value in the area is used as the hydrogen concentration. In this case, the hydrogen concentration in the adjacent layer is affected, and a region where a nearly constant value is obtained is found. In this case, the maximum value of the hydrogen concentration in the region where the layer exists or The minimum value is adopted as the hydrogen concentration in the layer. If there is no mountain-shaped peak with a maximum value or a valley-shaped peak with a minimum value, the inflection point The value is taken as the hydrogen concentration.

[0198] In the case where an oxide semiconductor layer is formed by a sputtering method, the hydrogen concentration in the target is It is important to reduce not only the temperature but also the amount of water and hydrogen present in the chamber as much as possible. Specifically, the gas introduced into the chamber is used to bake the chamber before the formation. Reduce the concentration of water and hydrogen in the chamber, and prevent backflow in the exhaust system that exhausts gas from the chamber. It is effective to take measures such as preventing

[0199] The oxide semiconductor may be single-crystal or non-single-crystal. In the latter case, it may be amorphous or polycrystalline. It may also be a structure containing a crystalline portion in an amorphous state, or a non-amorphous structure. It can also be a s.

[0200] Amorphous oxide semiconductors can be easily flattened. This can reduce interface scattering when a transistor is fabricated, and can be fabricated relatively easily and relatively easily. High mobility can be obtained.

[0201] In addition, in a crystalline oxide semiconductor, defects in the bulk can be further reduced, and By improving the flatness of the surface, it is possible to obtain a mobility higher than that of an amorphous oxide semiconductor. In order to improve the flatness of the surface, it is preferable to form an oxide semiconductor on a flat surface. Specifically, the average surface roughness (Ra) is 1 nm or less, preferably 0.3 nm or less, and more preferably Preferably, it is formed on the surface to a thickness of 0.1 nm or less.

[0202] Note that Ra is the centerline average roughness defined in JIS B0601 applied to the surface. It is a three-dimensional extension of the method, which calculates the average absolute value of the deviation from the reference surface to the specified surface. This can be expressed as the "value obtained by dividing the total number of times the

[0203]

number

[0204] In the above, S0 is the measurement surface (coordinates (x1, y1) (x1, y2) (x2, y 1) The area of ​​the rectangular region bounded by four points (x2, y2), Z0 indicates the average height of the measurement surface. Ra is measured by an atomic force microscope (AFM). It can be evaluated using a microscope.

[0205] The oxide semiconductor film may be single-crystalline, polycrystalline (also referred to as polycrystalline), amorphous, or the like. Take the state.

[0206] Preferably, the oxide semiconductor film is CAAC-OS (C Axis Aligned C The film is a crystalline oxide semiconductor.

[0207] The CAAC-OS film is neither completely single crystalline nor completely amorphous. The film is an oxide semiconductor film having a crystalline-amorphous mixed phase structure in which a crystalline portion and an amorphous portion are present in the amorphous phase. The crystal part is small enough to fit inside a cube with one side less than 100 nm. In addition, transmission electron microscopes (TEM) In the observation image by microscope, the amorphous part in the CAAC-OS film The boundary between the grain and the crystalline part is not clear. Therefore, the grain boundary (also called the grain boundary) cannot be confirmed in the CAAC-OS film. Therefore, the decrease in electron mobility caused by the above phenomenon is suppressed.

[0208] The crystal part included in the CAAC-OS film has a c-axis that is normal to the surface on which the CAAC-OS film is formed. The three planes are aligned parallel to the normal vector of the wall or surface and perpendicular to the ab plane. It has a square or hexagonal atomic arrangement, and the metal atoms are layered or arranged in a direction perpendicular to the c-axis. In the crystal structure, metal atoms and oxygen atoms are arranged in layers. The orientation of the b-axis may be different. The range of 85° to 95° is also included. The range of 5° or more and 5° or less is also included.

[0209] In the CAAC-OS film, the distribution of the crystal parts may not be uniform. In the process of forming the AC-OS film, when crystals are grown from the surface side of the oxide semiconductor film, The proportion of crystalline parts near the surface may be higher than that near the formation surface. By adding impurities to the AAC-OS film, the crystalline part becomes non-crystalline in the impurity-doped region. It may also crystallize.

[0210] The c-axis of the crystalline part in the CAAC-OS film is the normal vector of the surface on which the CAAC-OS film is formed. The shape of the CAAC-OS film (the shape of the film) is Depending on the cross-sectional shape of the surface or the cross-sectional shape of the surface, they may face in different directions. The c-axis direction of the crystalline part is the normal vector of the surface on which the CAAC-OS film is formed. The direction of the crystal is parallel to the normal vector of the crystal or the surface. Alternatively, it is formed by carrying out a crystallization treatment such as a heat treatment after the film formation.

[0211] The electrical characteristics of a transistor using a CAAC-OS film change when irradiated with visible or ultraviolet light. Therefore, the transistor has high reliability.

[0212] Note that part of oxygen contained in the oxide semiconductor film may be substituted with nitrogen.

[0213] When the CAAC-OS film is formed by sputtering, the oxygen in the atmosphere is For example, sputtering in a mixed gas atmosphere of argon and oxygen is preferred. When the ring method is used, the oxygen gas ratio is preferably 30% or more, and more preferably 40% or more. It is more preferable to do so. The crystallization of CAAC is promoted by supplementing oxygen from the atmosphere. Because it is.

[0214] When a CAAC-OS film is formed by sputtering, It is preferable to heat the substrate on which the S film is to be formed to 150°C or higher, and it is not recommended to heat it to 170°C or higher. It is more preferable to heat the substrate. As the substrate temperature increases, the crystallization of CAAC is promoted. Because.

[0215] In addition, after the CAAC-OS film was heat-treated in a nitrogen atmosphere or in a vacuum, In this case, it is preferable to perform the heat treatment in an oxygen atmosphere or in a mixed atmosphere of oxygen and other gases. It is preferable that oxygen deficiency caused by the previous heat treatment is compensated for by supplying oxygen from the atmosphere in the subsequent heat treatment. This is because it can be restored.

[0216] In addition, the surface on which the CAAC-OS film is formed (the surface on which the film is to be formed) is preferably flat. The CAAC-OS film has a c-axis that is approximately perpendicular to the surface on which the film is formed. The unevenness in the CAAC-OS film induces the generation of grain boundaries. Therefore, before the CAAC-OS film is formed, the surface to be formed is subjected to chemical mechanical polishing. Chemical Mechanical Polishing (CMP) and other flattening methods It is preferable to perform a smoothing treatment. In addition, the average roughness of the surface to be coated is 0.5 nm or less. It is preferable that the thickness is 0.3 nm or less, and more preferable that the thickness is 0.3 nm or less.

[0217] Next, an example of a crystal structure contained in CAAC will be described in detail with reference to FIGS. 14 to 16. 14 to 16, the upward direction is the c-axis direction, and The plane perpendicular to the direction is the ab plane. When simply referring to the upper half and the lower half, the ab plane is used as the boundary. In Figure 14, the circled O represents a tetrahedral O. The double circled O indicates a three-coordinate O.

[0218] Figure 14(A) shows one hexacoordinated In atom and six tetracoordinated oxygen atoms (hereafter referred to as The structure shown has four-coordinated oxygen atoms. Here, one metal atom has four adjacent oxygen atoms. The structure showing only atoms is called a small group. The structure in Figure 14(A) has an octahedral structure, For simplicity, the structure is shown as a plane. There are three tetracoordinated O atoms in each group. The small group shown in Figure 14(A) has a zero charge.

[0219] Figure 14(B) shows one pentacoordinate Ga atom and three tricoordinate oxygen atoms (hereafter referred to as The structure shows a tricoordinate O and two adjacent tetracoordinate O. The upper and lower halves of Figure 14(B) each contain one 4-coordinate atom. In addition, since In also has a 5-coordinate structure, it can take the structure shown in Figure 14(B). The small group shown in 4(B) has a charge of 0.

[0220] FIG. 14(C) shows a structure having one tetracoordinate Zn and four tetracoordinate O atoms adjacent to the Zn. The structure of Fig. 14(C) shows one tetracoordinate O in the upper half and three tetracoordinate O in the lower half. Or, in Figure 14(C), there are three tetracoordinate O atoms in the upper half and one in the lower half. There may be four-coordinated O atoms. The small group shown in Figure 14(C) has a zero charge.

[0221] FIG. 14(D) shows a structure having one hexacoordinate Sn atom and six tetracoordinate O atoms adjacent to the Sn atom. The structure of Figure 14(D) shows three tetracoordinate O atoms in the upper half and three tetracoordinate O atoms in the lower half. The small group shown in Figure 14(D) has a charge of +1.

[0222] Figure 14(E) shows a small group containing two Zn atoms. The upper half of Figure 14(E) shows one Zn atom. The small group shown in Figure 14(E) has four tetrahedral O atoms, and the lower half has one tetrahedral O atom. The charge of the atom is -1.

[0223] Here, a collection of multiple small groups is called a medium group, and a collection of multiple medium groups is called a is called a large group (also called a unit cell).

[0224] Here, we will explain the rules for combining these small groups. The three O atoms in the upper half of the hexacoordinated In have three neighboring In atoms downward, and the lower half Each of the three O atoms has three adjacent In atoms in the upward direction. Each O in the upper half of the The O atom in the upper half of the 4-coordinate Zn shown in FIG. 14(C) has 1 O atom in the downward direction. The three Os in the lower half each have three neighboring Zns in the upper direction. As shown above, the number of tetrahedral O atoms above the metal atom and the number of adjacent metal atoms below the O atoms are is equal, and similarly, the number of tetrahedral O atoms below the metal atom and the number of neighboring metal atoms above the O atoms are The number of atoms is equal. Since O is tetracoordinated, the number of neighboring metal atoms below is equal to the number of neighboring metal atoms above. The sum of the number of neighboring metal atoms is 4. Therefore, the number of tetrahedral O atoms above the metal atom and When the sum of the number of tetracoordinated O atoms below another metal atom is 4, two kinds of metal atoms with The reason is as follows. For example, the six-coordinate gold When a group atom (In or Sn) is bonded through a tetrahedral O atom in the lower half, the tetrahedral O atom is 3 Therefore, it is possible to use a five-coordinate metal atom (Ga or In) or a four-coordinate metal atom (Zn) It will combine with either

[0225] Metal atoms with these coordination numbers are bonded via tetracoordinated oxygen atoms in the c-axis direction. In addition, multiple small groups are bonded together so that the total charge of the layer structure is zero. The medium group is composed of these.

[0226] Figure 15(A) shows a model diagram of the middle group that constitutes the In-Sn-Zn-O system layer structure. FIG. 15(B) shows a large group consisting of three medium groups. (C) shows the atomic arrangement when the layer structure of FIG. 15(B) is observed from the c-axis direction.

[0227] In FIG. 15(A), for simplicity, the tricoordinate O atoms are omitted, and only the number of tetracoordinate O atoms is shown. For example, the upper and lower halves of Sn each contain three tetrahedral O atoms. Similarly, in FIG. 15(A), the upper and lower halves of In are Each of the has one tetracoordinated O atom, which is shown as a circled 1. Similarly, in Figure 1 In 5(A), the bottom half has one tetrahedral O atom, and the top half has three tetrahedral O atoms. A Zn atom has one tetrahedral O atom in the top half and three tetrahedral O atoms in the bottom half. n.

[0228] In FIG. 15(A), the middle group, which constitutes the In-Sn-Zn-O system layer structure, is Sn has three tetrahedral O atoms in the upper half and one in the lower half, and It bonds to In atoms in the upper and lower halves, and the In atoms have three tetracoordinate O atoms in the upper half. It bonds to Zn, and three tetracoordinate O atoms are connected to the upper half of the Zn via one tetracoordinate O atom in the lower half. In is bonded to a Zn atom with one tetracoordinate O atom in the upper half. It bonds to a small group of two atoms via a tetracoordinate O atom in the lower half of this small group. The structure is such that three tetracoordinate O atoms are bonded to the Sn atoms in the upper and lower halves. Multiple groups combine to form a larger group.

[0229] Here, for tricoordinated O and tetracoordinated O, the charge per bond is -0. 667, -0.5. For example, In (6-coordinate or 5-coordinate), Zn ( The charges of Sn (four-coordinated), Sn (five-coordinated or six-coordinated) are +3, +2, and +4, respectively. Therefore, the small group containing Sn has a charge of +1. Therefore, when a layer structure containing Sn is formed, To achieve this, a charge of -1 is required to cancel out the charge of +1. As shown in 14(E), there is a small group containing two Zn atoms. For example, If there is one small group containing two Zn atoms for every small group containing one Zn atom, the charges will be cancelled out. Therefore, the total charge of the layer structure can be set to zero.

[0230] Specifically, the large group shown in Figure 15(B) is repeated to form an In-Sn-Z InO-based crystals (In2SnZn3O8) can be obtained. The n-Zn-O layer structure is In2SnZn2O7(ZnO) m (m is 0 or a natural number. ) can be expressed by the composition formula:

[0231] In addition to these, there are also oxides of quaternary metals such as In-Sn-Ga-Zn oxides, In-Ga-Zn oxide (also written as IGZO), which is a ternary metal oxide, -Al-Zn oxide, Sn-Ga-Zn oxide, Al-Ga-Zn oxide, Sn- Al-Zn oxide, In-Hf-Zn oxide, In-La-Zn oxide, In- Ce-Zn oxide, In-Pr-Zn oxide, In-Nd-Zn oxide, In-S m-Zn oxide, In-Eu-Zn oxide, In-Gd-Zn oxide, In-Tb -Zn-based oxide, In-Dy-Zn-based oxide, In-Ho-Zn-based oxide, In-Er- Zn-based oxide, In-Tm-Zn-based oxide, In-Yb-Zn-based oxide, In-Lu-Z n-based oxides, binary metal oxides such as In-Zn-based oxides, Sn-Zn-based oxides, and A l-Zn oxides, Zn-Mg oxides, Sn-Mg oxides, In-Mg oxides, The same applies when an In-Ga oxide is used.

[0232] For example, in Figure 16(A), a middle group model consisting of an In-Ga-Zn-O system layer structure is shown. A diagram is shown.

[0233] In FIG. 16(A), the middle group, which constitutes the In-Ga-Zn-O system layer structure, is In the upper half and lower half, there are three tetrahedral O atoms, and in the lower half, there is one tetrahedral O atom. It bonds to the Zn in the molecule, and through the three tetracoordinate O atoms in the lower half of the Zn, the tetracoordinate O atoms Each bond to a Ga atom in the upper half and the lower half, and one tetracoordinate O atom in the lower half of the Ga atom Three tetracoordinate O atoms are bonded to the In atoms in the upper and lower halves via the Several of these medium groups combine to form large groups.

[0234] Figure 16(B) shows a large group consisting of three medium groups. shows the atomic arrangement when the layer structure of FIG. 16(B) is observed from the c-axis direction.

[0235] Here, the charges of In (6- or 5-coordinate), Zn (4-coordinate), and Ga (5-coordinate) are +3, +2, and +3, respectively, so they are in a small group that includes either In, Zn, or Ga. The charge is 0. Therefore, if these small groups are combined, The total charge is always zero.

[0236] The middle group, which constitutes the In-Ga-Zn-O system layer structure, is shown in FIG. The combination of different middle groups, In, Ga, and Zn, is not limited to the same middle group. Large groups are also possible.

[0237] <Transistor with a channel formed in an oxide semiconductor layer> 17(A) to 17(D) are used for a transistor in which a channel is formed in an oxide semiconductor layer. 17(A) to 17(D) are cross-sectional views showing examples of the structure of a transistor. This is a formula diagram.

[0238] The transistor shown in FIG. 17(A) includes a conductive layer 601(a), an insulating layer 602(a), and The oxide semiconductor layer 603(a), the conductive layer 605a(a), the conductive layer 605b(a), and the insulating layer It includes an edge layer 606(a) and a conductive layer 608(a).

[0239] The conductive layer 601(a) is provided on the element formation layer 600(a).

[0240] An insulating layer 602(a) is disposed on the conductive layer 601(a).

[0241] The oxide semiconductor layer 603(a) is overlapped on the conductive layer 601(a) via the insulating layer 602(a). To fold.

[0242] The conductive layer 605a(a) and the conductive layer 605b(a) are formed on the oxide semiconductor layer 603. It is provided on the oxide semiconductor layer 603(a) and is electrically connected to the oxide semiconductor layer 603(a).

[0243] The insulating layer 606(a) is formed between the oxide semiconductor layer 603(a), the conductive layer 605a(a), and the conductive The conductive layer 605a(b) is disposed on the conductive layer 605a(b).

[0244] The conductive layer 608(a) overlaps the oxide semiconductor layer 603(a) via the insulating layer 606(a). To fold.

[0245] Note that it is not always necessary to provide either the conductive layer 601(a) or the conductive layer 608(a). In addition, if the conductive layer 608(a) is not provided, the insulating layer 606(a) may not be provided. stomach.

[0246] The transistor shown in FIG. 17(B) includes a conductive layer 601(b), an insulating layer 602(b), and The oxide semiconductor layer 603(b), the conductive layer 605a(b), the conductive layer 605b(b), and the insulating layer It includes an edge layer 606(b) and a conductive layer 608(b).

[0247] The conductive layer 601(b) is provided on the element formation layer 600(b).

[0248] An insulating layer 602(b) is provided on the conductive layer 601(b).

[0249] Each of the conductive layer 605a(b) and the conductive layer 605b(b) is a It is installed on some parts.

[0250] The oxide semiconductor layer 603(b) is formed on the conductive layer 605a(b) and the conductive layer 605b(b). and is electrically connected to the conductive layer 605a(b) and the conductive layer 605b(b). The oxide semiconductor layer 603(b) is connected to the conductive layer 601(b) via the insulating layer 602(b). ) is superimposed on

[0251] The insulating layer 606(b) is formed between the oxide semiconductor layer 603(b), the conductive layer 605a(b), and the conductive layer 605b. The conductive layer 605b(b) is disposed on the conductive layer 605b(b).

[0252] The conductive layer 608(b) overlaps the oxide semiconductor layer 603(b) via the insulating layer 606(b). To fold.

[0253] Note that it is not always necessary to provide either the conductive layer 601(b) or the conductive layer 608(b). If the conductive layer 608(b) is not provided, the insulating layer 606(b) may not be provided.

[0254] The transistor shown in FIG. 17(C) includes a conductive layer 601(c), an insulating layer 602(c), and The oxide semiconductor layer 603(c), the conductive layer 605a(c), and the conductive layer 605b(c) are Contains.

[0255] The oxide semiconductor layer 603(c) includes a region 604a(c) and a region 604b(c). The regions 604a(c) and 604b(c) are spaced apart from each other and each contain a dopant. The area between the area 604a(c) and the area 604b(c) is a region where fluorine is added. The oxide semiconductor layer 603(c) is a channel formation region. ) are provided on the region 604a(c) and the region 604b(c). It's not necessary.

[0256] The conductive layer 605a(c) and the conductive layer 605b(c) are formed on the oxide semiconductor layer 603(c). and is electrically connected to the oxide semiconductor layer 603(c). The side surfaces of the conductive layer 5a(c) and the conductive layer 605b(c) are tapered.

[0257] Furthermore, although the conductive layer 605a(c) overlaps a portion of the region 604a(c), this is not necessarily the case. The conductive layer 605a(c) may overlap a part of the region 604a(c). This reduces the resistance between the conductive layer 605a(c) and the region 604a(c). In addition, the entire region of the oxide semiconductor layer 603(c) overlapping with the conductive layer 605a(c) can be This may be area 604a(c).

[0258] Furthermore, the conductive layer 605b(c) overlaps a portion of the region 604b(c), but this is not necessarily the case. The conductive layer 605b(c) may overlap a part of the region 604b(c). This reduces the resistance between the conductive layer 605b(c) and the region 604b(c). In addition, the entire region of the oxide semiconductor layer 603(c) overlapping with the conductive layer 605b(c) can be may be area 604b(c).

[0259] The insulating layer 602(c) is made up of an oxide semiconductor layer 603(c), a conductive layer 605a(c), and a conductive The conductive layer 605b(c) is disposed on the conductive layer 605b(c).

[0260] The conductive layer 601(c) overlaps the oxide semiconductor layer 603(c) via the insulating layer 602(c). The oxide semiconductor layer 60(c) overlaps with the conductive layer 601(c) with the insulating layer 602(c) interposed therebetween. The region 3(c) becomes the channel formation region.

[0261] The transistor shown in FIG. 17(D) has a conductive layer 601(d) and an insulating layer 602(d ), an oxide semiconductor layer 603(d), a conductive layer 605a(d), and a conductive layer 605b(d) and includes.

[0262] The conductive layer 605a(d) and the conductive layer 605b(d) are formed on the element formation layer 600(d). The side surfaces of the conductive layer 605a(d) and the conductive layer 605b(d) are tapered. is.

[0263] The oxide semiconductor layer 603(d) includes a region 604a(d) and a region 604b(d). The region 604a(d) and the region 604b(d) are spaced apart from each other and each This is the area where the punt was added. Also, between area 604a(d) and area 604b(d) The oxide semiconductor layer 603(d) is formed by, for example, a conductive layer 605. a(d), the conductive layer 605b(d), and the element formation layer 600(d), The layer 605a(d) and the conductive layer 605b(d) are electrically connected to each other. The region 604a(d) and the region 604b(d) may not be provided.

[0264] Region 604a(d) is electrically connected to conductive layer 605a(d).

[0265] Region 604b(d) is electrically connected to conductive layer 605b(d).

[0266] The insulating layer 602(d) is provided on the oxide semiconductor layer 603(d).

[0267] The conductive layer 601(d) overlaps the oxide semiconductor layer 603(d) via the insulating layer 602(d). The oxide semiconductor layer 60(d) overlaps with the conductive layer 601(d) with the insulating layer 602(d) interposed therebetween. The region 3(d) is the channel formation region.

[0268] Furthermore, each of the components shown in FIGS. 17(A) to 17(D) will be described.

[0269] The element formation layers 600(a) to 600(d) may be, for example, insulating layers or A substrate having an insulating surface can be used. The insulating film can also be used as the element formation layer 600(a) to the element formation layer 600(d).

[0270] Each of the conductive layers 601(a) to 601(d) serves as a gate of a transistor. The layer functioning as the gate of a transistor is called a gate electrode or is also called the gate wiring.

[0271] The conductive layers 601(a) to 601(d) may be made of, for example, molybdenum, magnesium, or the like. Titanium, chromium, tantalum, tungsten, aluminum, copper, neodymium, or A layer of a metal material such as scandium or an alloy material containing this as the main component can be used. In addition, a layer of a material applicable to the formation of the conductive layers 601(a) to 601(d) can be formed. The conductive layers 601(a) to 601(d) can also be formed by stacking layers.

[0272] Each of the insulating layers 602(a) to 602(d) is a gate insulating layer of a transistor. It functions as a layer.

[0273] The insulating layers 602(a) to 602(d) may be, for example, a silicon oxide layer, a silicon nitride layer, or the like. Silicon layer, silicon oxynitride layer, silicon nitride oxide layer, aluminum oxide layer, aluminum nitride an aluminum oxide nitride layer, an aluminum oxide nitride layer, a hafnium oxide layer, or A lanthanum oxide layer can be used. ) are laminated to form insulating layers 602(a) to 602(d). You can also do this.

[0274] The insulating layers 602(a) to 602(d) may be made of, for example, An insulating layer made of a material containing a Group 13 element and oxygen may also be used. For example, an oxide When the semiconductor layers 603(a) to 603(d) contain a Group 13 element, The thirteenth insulating layer is in contact with the nitride semiconductor layer 603(a) to the oxide semiconductor layer 603(d). By using an insulating layer containing an element of the SiO 2 group, the state of the interface between the insulating layer and the oxide semiconductor layer can be improved. It can be done well.

[0275] Examples of materials containing a Group 13 element and an oxygen element include gallium oxide and aluminum oxide. Examples include aluminum gallium oxide, aluminum gallium oxide, and aluminum gallium oxide. Aluminum gallium chloride is a compound with a higher aluminum content (atomic %) than the gallium content (atomic %). Gallium aluminum oxide is a substance with a high gallium content ( A material whose atomic percent is equal to or greater than the aluminum content (atomic percent). For example, AlO x (x=3+α, α is a value greater than 0 and less than 1), Ga2O x (x=3+α, α is 0 (a value greater than or equal to 1 and less than 1) or Ga x Al 2-x O 3+α (x is greater than 0 and less than 2 A material expressed by a small value, α is greater than 0 and less than 1) can also be used.

[0276] In addition, by stacking layers of materials applicable to the insulating layers 602(a) to 602(d), Insulating layers 602(a) to 602(d) can also be configured. a2O x The insulating layer 602(a) to the insulating layer 602(b) are stacked by laminating layers containing gallium oxide. 602(d) may be configured. x Insulating material containing gallium oxide, denoted by layer and AlO x The insulating layer 602 is formed by laminating insulating layers containing aluminum oxide represented by Insulating layers 602(a) to 602(d) may be formed.

[0277] In addition, when the channel length of the transistor is 30 nm, the oxide semiconductor layer 603(a) The thickness of the oxide semiconductor layer 603(d) may be, for example, about 5 nm. The oxide semiconductor layers 603(a) to 603(d) are oxide semiconductor layers of CAAC. If present, the short channel effect in the transistor can be suppressed.

[0278] Region 604a(c), region 604b(c), region 604a(d), and region 604b( d) is doped with a dopant that gives it N-type or P-type conductivity, and is used as the source of the transistor. The dopant may be, for example, a 1-atom element in the periodic table. Group 3 elements (e.g., boron), Group 15 elements in the periodic table (e.g., nitrogen, phosphorus, and arsenic), and rare gas elements (e.g., helium, argon, and xenon One or more of the following can be used. The region that functions as the drain of a transistor is also called the source region. The region having the drain electrode 604 is also called a drain region. Dopants are added to regions 604a(d) and 604b(d) to form contacts with the conductive layer. Since the connection resistance can be reduced, the transistor can be miniaturized.

[0279] The conductive layers 605a(a) to 605a(d) and the conductive layers 605b(a) to 605b(d) are Each of the layers 605b(d) functions as a source or drain of a transistor. Note that the layer functioning as the source of the transistor is called a source electrode or a source wiring. The layer having the function of the drain of the transistor may be called a drain electrode or a drain wiring. Also called a line.

[0280] The conductive layers 605a(a) to 605a(d) and the conductive layers 605b(a) to 605b(d) are The layer 605b(d) may be made of, for example, aluminum, magnesium, chromium, copper, or tantalum. , titanium, molybdenum, tungsten, or other metal materials, or A layer of alloy material with a main component of copper, magnesium, and aluminum can be used. The conductive layers 605a(a) to 605a(d) are formed of a layer of an alloy material containing aluminum. and the conductive layers 605b(a) to 605b(d). Conductive layers 605a(a) to 605a(d) and conductive layers 605b(a) to 605b(d) are The conductive layers 605a(a) to 605b(d) are stacked by using layers of materials applicable to the conductive layers 605a(a) to 605b(d). 5a(d), and conductive layers 605b(a) to 605b(d). For example, a layer of an alloy material containing copper, magnesium, and aluminum and a layer containing copper may be stacked. The conductive layers 605a(a) to 605a(d) and the conductive layer 605b(a) The conductive layer 605b(d) can be formed.

[0281] In addition, the conductive layers 605a(a) to 605a(d) and the conductive layer 605b(a) The conductive layer 605b(d) may be a layer containing a conductive metal oxide. Examples of conductive metal oxides include indium oxide, tin oxide, zinc oxide, and indium Tin oxide or indium zinc oxide can be used. The conductive layers 605a(a) to 605a(d) and the conductive layers 605b(a) to 605b(d) Applicable conductive metal oxides may include silicon oxide.

[0282] The insulating layer 606(a) and the insulating layer 606(b) may be formed by the insulating layers 602(a) to 602(b). 602(d) can be a layer of applicable material. The insulating layer 606(a) and the insulating layer 606(b) are formed by stacking the materials applicable to the insulating layer 606(a) and the insulating layer 606(b). For example, a silicon oxide layer, an aluminum oxide layer, etc. may be used. The insulating layer 606(a) and the insulating layer 606(b) may be formed of, for example, aluminum oxide. By using the silicon layer, the oxide semiconductor layer 603(a) and the oxide semiconductor layer 603(b) In addition, the effect of suppressing the intrusion of impurities (water) into the oxide semiconductor layer 603 can be further improved. This can enhance the effect of suppressing oxygen desorption from the oxide semiconductor layer 603(a) and the oxide semiconductor layer 603(b).

[0283] Each of the conductive layers 608(a) and 608(b) serves as a gate of a transistor. Note that the transistor has the functions of the conductive layer 601(a) and the conductive layer 608(a). In the case of a structure including both, or both conductive layer 601(b) and conductive layer 608(b), One of conductive layer 601(a) and conductive layer 608(a), or conductive layer 601(b) and conductive layer 6 One of the gate electrodes is called a back gate, a back gate electrode, or a back gate wiring. By providing a plurality of conductive layers each having a function as a gate via a channel forming layer, This makes it easier to control the threshold voltage of the transistor.

[0284] The conductive layer 608(a) and the conductive layer 608(b) may be, for example, the conductive layers 601(a) to 601(b). A layer of a material applicable to the conductive layer 601(d) can be used. The conductive layers 608(a) and 608(b) are formed by stacking layers of material applicable to the conductive layers 608(a) and 608(b). Conductive layer 608(b) may be configured.

[0285] In addition, the insulating layers 602(a) to 602(d) may be made of laminated materials. The insulating layer may also function as a protective layer for the panel.

[0286] In addition, a base layer is formed on the element formation layers 600(a) to 600(d). A transistor may be formed on the underlying layer. In this case, the underlying layer may be, for example, an insulating layer. Any layer of applicable material can be used for the border layer 602(a) through the insulating layer 602(d). In addition, a base layer can be formed by stacking materials applicable to the insulating layers 602(a) to 602(d). For example, the base layer may be formed by laminating an aluminum oxide layer and a silicon oxide layer. By forming the oxide semiconductor layer 603(a) to the oxide semiconductor layer 603(b), oxygen contained in the base layer is transferred to the oxide semiconductor layer 603(a) to the oxide semiconductor layer 603(b). Desorption through the semiconductor layer 603(d) can be suppressed.

[0287] In addition, in the insulating layers in contact with the oxide semiconductor layers 603(a) to 603(d), By making the oxygen in the oxide semiconductor layer 603(a) to the oxide semiconductor layer 603(b), Therefore, the oxide semiconductor layer 603(a) to the oxide semiconductor layer 603(d) are easily supplied with the oxygen. 603(d) or the insulating layer and the oxide semiconductor layer 603(a) to the oxide semiconductor layer 60 3(d) can reduce oxygen defects at the interface of the oxide semiconductor layer 603( The carrier density of the oxide semiconductor layers 603(a) to 603(d) can be further reduced. However, the oxide semiconductor layer 603(a) to the oxide semiconductor layer 603(b) may be formed by a manufacturing process. Even when the oxygen contained in the oxide semiconductor layer 603(d) is in excess, the oxide semiconductor layer 603(a) The insulating layer in contact with the oxide semiconductor layer 603(d) prevents the oxide semiconductor layer 603(a) from This can prevent oxygen from being released from the oxide semiconductor layer 603(d).

[0288] <Characteristics of transistors in which the channel is formed in an oxide semiconductor layer> A transistor with a channel formation region made of an oxide semiconductor containing In, Sn, and Zn as its main components The oxide semiconductor layer is formed by heating the substrate. By performing heat treatment after forming the film, good properties can be obtained. An element that is contained in an amount of 5 atomic % or more by composition ratio.

[0289] By intentionally heating the substrate after forming an oxide semiconductor layer mainly composed of In, Sn, and Zn, This makes it possible to improve the field effect mobility of the transistor. This makes it possible to shift the threshold voltage of the transistor in a positive direction and make it normally off.

[0290] For example, Figs. 18(A) to (C) show a semiconductor device with a channel length L of 3 μm, a channel width W of 10 μm, and a gate insulating layer with a thickness of 100 nm. These are the characteristics of a transistor using V d was set to 10V.

[0291] Figure 18(A) shows a film made of In, Sn, and Zn as the main components by sputtering without intentionally heating the substrate. The figure shows the characteristics of a transistor when an oxide semiconductor layer is formed as a component. Movement is 18.8cm 2 On the other hand, by intentionally heating the substrate, In, Forming an oxide semiconductor layer containing Sn and Zn as its main components improves field-effect mobility. Fig. 18(B) shows the structure of the substrate heated to 200°C, which is mainly composed of In, Sn, and Zn. The transistor characteristics are shown when an oxide semiconductor layer is formed, and the field-effect mobility is 32. 2cm 2 / Vsec is obtained.

[0292] The field-effect mobility was measured by forming an oxide semiconductor layer mainly composed of In, Sn, and Zn and then thermally The effect can be further enhanced by further treatment. After sputtering the oxide semiconductor layer mainly composed of n at 200°C, it was heated at 650°C. The transistor characteristics after the treatment are shown below. At this time, the field effect mobility is 34.5 cm 2 / Vsec is obtained.

[0293] In addition, substrate heating and heat treatment can remove hydrogen and hydroxyl groups, which are harmful impurities for oxide semiconductors. It has the effect of preventing the inclusion of metal in the film or removing metal from the film. High purity can be achieved by removing hydrogen, which acts as a donor impurity in semiconductors. This allows the transistor to be normally off, and the oxide semiconductor is highly purified. By this, the off-current can be reduced to 1 aA / μm or less. The unit of the value indicates the current value per 1 μm of channel width.

[0294] Figure 19 shows the relationship between the off-state current of a transistor and the reciprocal of the substrate temperature (absolute temperature) at the time of measurement. For simplicity, the value obtained here is the reciprocal of the substrate temperature during measurement multiplied by 1000 (1000 / T) is the horizontal axis.

[0295] As shown in Figure 19, when the substrate temperature is 125°C, the -1 9 A / μm) or less, and at 85°C it is 10zA / μm (1×10 -20A / μm) or less Since the logarithm of the current value is proportional to the inverse of the temperature, at room temperature (27°C) it is 0. 1zA / μm(1×10 -22 Therefore, the off-state current is expected to be less than 1000 mA / μm. 1aA / μm (1×10 -18 A / μm) or less at 85°C 0zA / μm(1×10 -19 A / μm) or less at room temperature. -21 A / μm or less.

[0296] The transistor of this embodiment may be used in the semiconductor device described in the first and second embodiments. By using the semiconductor device in the present embodiment, the semiconductor device can be operated stably. By using a transistor of this type as the transistor 102, Therefore, the amount of charge lost from the capacitor 101 can be reduced. Therefore, the number of times that the offset voltage is held in the capacitor 101 can be reduced. .

[0297] This embodiment mode can be implemented in appropriate combination with other embodiment modes or the like.

[0298] (Embodiment 6) In this embodiment, the semiconductor device and the shift register circuit described in the above embodiment are An example of an electronic device equipped with a display device or the like will be described.

[0299] FIG. 20A shows a portable gaming machine, which includes a housing 9630, a display unit 9631, and a speaker 963 3, operation keys 9635, connection terminals 9636, recording medium reading unit 9672, etc. The portable gaming machine shown in 0(A) reads the program or data recorded on the recording medium. and a function to share information with other portable gaming machines via wireless communication. , etc. The functions of the portable gaming machine shown in FIG. 20(A) are not limited to these. , and has various functions.

[0300] FIG. 20B shows a digital camera, which includes a housing 9630, a display portion 9631, and a speaker 96 33, operation keys 9635, connection terminal 9636, shutter button 9676, image receiving unit 967 7, etc. The digital camera shown in FIG. 20(B) has a function of taking still images and a function of taking videos. It has the function of taking pictures, correcting the pictures automatically or manually, and receiving various information from the antenna. function to acquire images, save the captured images or information acquired from the antenna, The image captured by the camera or the information acquired from the antenna can be displayed on the display unit. The functions of the digital camera shown in 20(B) are not limited to these, and it has various functions. .

[0301] FIG. 20C shows a television receiver, which includes a housing 9630, a display portion 9631, and a speaker 963 3, operation keys 9635, connection terminals 9636, etc. The device has the function of processing television radio waves and converting them into image signals, and the function of processing image signals to make them suitable for display. It has the function of converting the image signal into a digital signal, and the function of converting the frame frequency of the image signal. The functions of the television receiver shown in FIG. 20(C) are not limited to these, and may have various functions. .

[0302] Figure 20(D) shows a monitor for use in a personal computer (PC monitor). 20(D) is a model having a housing 9630, a display portion 9631, and the like. The monitor shows an example in which a window-type display unit 9653 is located in the display unit 9631. For the sake of explanation, the window-type display unit 9653 is shown in the display unit 9631, but other symbols may be used. The display may be a ball, for example, an icon, an image, etc. In many cases, the image signal is rewritten only when it is input. This is suitable for applying the driving method of the device. The functions are not limited to these, and various functions are available.

[0303] FIG. 21A shows a computer, which includes a housing 9630, a display portion 9631, and a speaker 963 3. Operation keys 9635, connection terminals 9636, pointing devices 9681, external connections The computer shown in FIG. 21(A) has various information (still images, Functions for displaying videos, text images, etc. on the display, various software (programs) a function to control processing by wireless or wired communication, a communication function using a communication function Functions for connecting to various computer networks and transmitting various data using communication functions The computer shown in FIG. 21(A) has the following functions: is not limited to this and has various functions.

[0304] Next, FIG. 21(B) shows a mobile phone, which includes a housing 9630, a display portion 9631, a speaker 96 33, operation keys 9635, microphone 9638, etc. Mobile phones have the ability to display various information (still images, videos, text images, etc.), a calendar, , the function to display the date or time on the display unit, and the function to operate or edit the information displayed on the display unit It has functions such as controlling the processing by various software (programs), etc. The functions of the mobile phone shown in FIG. 21(B) are not limited to these, and the mobile phone may have various functions. do.

[0305] Next, FIG. 21C shows an electronic paper (also called an E-book), which includes a housing 9630, The electronic paper shown in FIG. Functions that display various information (still images, videos, text images, etc.), calendars, dates, or Functions for displaying the time, etc. on the display, functions for operating or editing the information displayed on the display, and various It has a function to control the processing by software (program), etc. The functions of the electronic paper shown in (C) are not limited to these, and it has various other functions. The structure of the electronic paper is shown in FIG. 21(D). The electronic paper shown in FIG. 21(D) 21(C) is equipped with a solar cell 9651 and a battery 9652. When a reflective display device is used as the display portion 9631, It is expected to be used in bright conditions, and is powered by solar cells 9651 and batteries 965 2 can be efficiently charged, which is preferable. The use of lithium ion batteries has the advantage of enabling miniaturization.

[0306] The electronic device described in this embodiment may include the semiconductor device of the first embodiment and the semiconductor device of the second embodiment. The semiconductor device, the shift register circuit of the third embodiment, or the display device of the fourth embodiment is applied. By doing so, it is possible to provide an electronic device that can be driven even if the transistor is a depletion type. It is possible.

[0307] This embodiment mode can be implemented by being appropriately combined with the configurations described in other embodiment modes. It is Noh. [Explanation of symbols]

[0308] 11 Wiring 12 Wiring 13 Wiring 14 Wiring 15 Wiring 16 Wiring 17 Wiring 21 Wiring 22 Wiring 23 Wiring 24 Wiring 25 Wiring 31 Wiring 31_i Wiring 31_i-1 Wiring 32 Wiring 33 Wiring 34 Wiring 35 Wiring 36 Wiring 37 Wiring 38 Wiring 100 circuits 101 Capacitor element 102 transistor 103 Capacitor element 110 circuits 111 Transistor 112 transistors 113 Transistor 114 transistors 115 transistors 116 transistors 120 circuits 121 Transistor 122 transistors 123 Transistor 124 transistors 125 transistors 126 transistors 200 Flip-Flop Circuit 200_1 Flip-flop circuit 200_2 Flip-flop circuit 200_3 Flip-flop circuit 600 Device formation layer 601 Conductive layer 602 Insulation layer 603 Oxide semiconductor layer 606 Insulation Layer 608 Conductive layer 100A circuit 100B circuit 101A Capacitive Element 101B Capacitor element 102A transistor 102B transistor 4001 board 4002 Pixel section 4003 Signal line driver circuit 4004 Scanning line driver circuit 4005 Sealing material 4006 board 4018 FPC 4018a FPC 4018b FPC 604a area 604b area 605a Conductive layer 605b conductive layer 9630 chassis 9631 Display section 9632 Operation Key 9633 Speaker 9635 Operation Key 9636 Connection terminal 9638 Microphone 9651 Solar Cell 9652 battery 9653 Window type display 9672 Recording medium reading unit 9676 Shutter button 9677 Image receiving unit 9680 External connection port 9681 Pointing Device IN signal INO signal IN1 signal IN1O signal IN2 signal IN2O signal IN3 signal SE signal OUT signal OUTA signal OUTB signal OUT1 signal OUT2 signal OUTN signal VH potential VDD potential VL1 potential VL2 potential N1 node T0 period T1 period Ta period Tb period Tc period Td period CK signal CK1 signal CK2 signal SP signal M1 transistor M2 transistor M3 transistor M4 transistor C1 Capacitor element

Claims

1. A semiconductor device comprising first to tenth transistors, one of the source and the drain of the first transistor is always electrically connected to a first wiring; the other of the source and the drain of the first transistor is always electrically connected to a second wiring; one of the source and the drain of the second transistor is always electrically connected to a power supply line; the other of the source and the drain of the second transistor is always electrically connected to the first wiring; one of the source and the drain of the third transistor is always electrically connected to the gate of the first transistor; the other of the source and the drain of the third transistor is always electrically connected to a third wiring; one of the source and the drain of the fourth transistor is always electrically connected to the power supply line; the other of the source and the drain of the fourth transistor is always electrically connected to the gate of the first transistor; a gate of the fourth transistor is always electrically connected to a gate of the second transistor; one of the source and the drain of the fifth transistor is always electrically connected to the gate of the second transistor; a gate of the fifth transistor is always electrically connected to a gate of the second transistor; one of the source and the drain of the sixth transistor is always electrically connected to the gate of the second transistor; one of the source and the drain of the seventh transistor is always electrically connected to the gate of the sixth transistor; one of the source and the drain of the eighth transistor is always electrically connected to the power supply line; the other of the source and the drain of the eighth transistor is always electrically connected to the gate of the sixth transistor; the gate of the eighth transistor is always electrically connected to the fourth wiring; one of the source and the drain of the ninth transistor is always electrically connected to the power supply line; the other of the source and the drain of the ninth transistor is always electrically connected to the gate of the sixth transistor; one of the source and the drain of the tenth transistor is always electrically connected to the power supply line; the gate of the tenth transistor is always electrically connected to the fourth wiring; when the power supply line and the gate of the third transistor are in a conductive state via at least a channel formation region of the tenth transistor, a potential of the power supply line is supplied to the gate of the third transistor; a MOS capacitor is formed between the gate of the sixth transistor and one of the source and the drain of the sixth transistor; Semiconductor device.

2. A semiconductor device comprising first to tenth transistors, one of the source and the drain of the first transistor is always electrically connected to a first wiring; the other of the source and the drain of the first transistor is always electrically connected to a second wiring; one of the source and the drain of the second transistor is always electrically connected to a power supply line; the other of the source and the drain of the second transistor is always electrically connected to the first wiring; one of the source and the drain of the third transistor is always electrically connected to the gate of the first transistor; the other of the source and the drain of the third transistor is always electrically connected to a third wiring; one of the source and the drain of the fourth transistor is always electrically connected to the power supply line; the other of the source and the drain of the fourth transistor is always electrically connected to the gate of the first transistor; a gate of the fourth transistor is always electrically connected to a gate of the second transistor; one of the source and the drain of the fifth transistor is always electrically connected to the gate of the second transistor; a gate of the fifth transistor is always electrically connected to a gate of the second transistor; one of the source and the drain of the sixth transistor is always electrically connected to the gate of the second transistor; one of the source and the drain of the seventh transistor is always electrically connected to the gate of the sixth transistor; one of the source and the drain of the eighth transistor is always electrically connected to the power supply line; the other of the source and the drain of the eighth transistor is always electrically connected to the gate of the sixth transistor; the gate of the eighth transistor is always electrically connected to the fourth wiring; one of the source and the drain of the ninth transistor is always electrically connected to the power supply line; the other of the source and the drain of the ninth transistor is always electrically connected to the gate of the sixth transistor; one of the source and the drain of the tenth transistor is always electrically connected to the power supply line; the gate of the tenth transistor is always electrically connected to the fourth wiring; when the power supply line and the gate of the third transistor are in a conductive state via at least a channel formation region of the tenth transistor, a potential of the power supply line is supplied to the gate of the third transistor; a MOS capacitor is formed between the gate of the sixth transistor and one of the source and the drain of the sixth transistor; the first wiring has a function of outputting a signal, the second wiring has a function of supplying a clock signal; Semiconductor device.

3. A semiconductor device comprising first to tenth transistors, one of the source and the drain of the first transistor is always electrically connected to a first wiring; the other of the source and the drain of the first transistor is always electrically connected to a second wiring; one of the source and the drain of the second transistor is always electrically connected to a power supply line; the other of the source and the drain of the second transistor is always electrically connected to the first wiring; one of the source and the drain of the third transistor is always electrically connected to the gate of the first transistor; the other of the source and the drain of the third transistor is always electrically connected to a third wiring; one of the source and the drain of the fourth transistor is always electrically connected to the power supply line; the other of the source and the drain of the fourth transistor is always electrically connected to the gate of the first transistor; a gate of the fourth transistor is always electrically connected to a gate of the second transistor; one of the source and the drain of the fifth transistor is always electrically connected to the gate of the second transistor; a gate of the fifth transistor is always electrically connected to a gate of the second transistor; one of the source and the drain of the sixth transistor is always electrically connected to the gate of the second transistor; one of the source and the drain of the seventh transistor is always electrically connected to the gate of the sixth transistor; one of the source and the drain of the eighth transistor is always electrically connected to the power supply line; the other of the source and the drain of the eighth transistor is always electrically connected to the gate of the sixth transistor; the gate of the eighth transistor is always electrically connected to the fourth wiring; one of the source and the drain of the ninth transistor is always electrically connected to the power supply line; the other of the source and the drain of the ninth transistor is always electrically connected to the gate of the sixth transistor; one of the source and the drain of the tenth transistor is always electrically connected to the power supply line; the gate of the tenth transistor is always electrically connected to the fourth wiring; when the power supply line and the gate of the third transistor are in a conductive state via at least a channel formation region of the tenth transistor, a potential of the power supply line is supplied to the gate of the third transistor; a MOS capacitor is formed between the gate of the sixth transistor and one of the source and the drain of the sixth transistor; Semiconductor device.

4. A semiconductor device comprising first to tenth transistors, one of the source and the drain of the first transistor is always electrically connected to a first wiring; the other of the source and the drain of the first transistor is always electrically connected to a second wiring; one of the source and the drain of the second transistor is always electrically connected to a power supply line; the other of the source and the drain of the second transistor is always electrically connected to the first wiring; one of the source and the drain of the third transistor is always electrically connected to the gate of the first transistor; the other of the source and the drain of the third transistor is always electrically connected to a third wiring; one of the source and the drain of the fourth transistor is always electrically connected to the power supply line; the other of the source and the drain of the fourth transistor is always electrically connected to the gate of the first transistor; a gate of the fourth transistor is always electrically connected to a gate of the second transistor; one of the source and the drain of the fifth transistor is always electrically connected to the gate of the second transistor; a gate of the fifth transistor is always electrically connected to a gate of the second transistor; one of the source and the drain of the sixth transistor is always electrically connected to the gate of the second transistor; one of the source and the drain of the seventh transistor is always electrically connected to the gate of the sixth transistor; one of the source and the drain of the eighth transistor is always electrically connected to the power supply line; the other of the source and the drain of the eighth transistor is always electrically connected to the gate of the sixth transistor; the gate of the eighth transistor is always electrically connected to the fourth wiring; one of the source and the drain of the ninth transistor is always electrically connected to the power supply line; the other of the source and the drain of the ninth transistor is always electrically connected to the gate of the sixth transistor; one of the source and the drain of the tenth transistor is always electrically connected to the power supply line; the gate of the tenth transistor is always electrically connected to the fourth wiring; when the power supply line and the gate of the third transistor are in a conductive state via at least a channel formation region of the tenth transistor, a potential of the power supply line is supplied to the gate of the third transistor; a MOS capacitor is formed between the gate of the sixth transistor and one of the source and the drain of the sixth transistor; the first wiring has a function of outputting a signal, the second wiring has a function of supplying a clock signal; Semiconductor device.

5. In any one of claims 1 to 4, the first to tenth transistors have the same conductivity type; Semiconductor device.

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