Diamond semiconductor device, electromechanical equipment, and, method for manufacturing diamond semiconductor device

Abstract

To provide a diamond semiconductor device which can contribute to materializing multilayer wiring structure while avoiding the complexity of a process, and to provide electromechanical equipment and a method for manufacturing a diamond semiconductor device.SOLUTION: A diamond semiconductor device comprises: a diamond semiconductor layer; a plurality of wirings arranged in a multilayer configuration on the diamond semiconductor layer; and at least one interlayer insulating layer arranged between the plurality of wirings. Electromechanical equipment includes the diamond semiconductor device. A method for manufacturing the diamond semiconductor device includes the steps of forming lower layer wiring, an interlayer insulating layer, and upper layer wiring in this order on the diamond semiconductor layer.SELECTED DRAWING: Figure 15

Description

[Technical Field]

[0001] The present invention relates to a diamond semiconductor device, an electric machine or device, and a method for manufacturing a diamond semiconductor device. [Background technology]

[0002] With the recent development of diamond CVD (Chemical Vapor Deposition) technology, diamond has become increasingly purified, and the development of diamond semiconductor devices in which elements using diamond semiconductors are formed on diamond substrates is progressing. Diamond semiconductor devices are expected to be next-generation semiconductor devices because, compared to semiconductor devices using materials such as silicon, SiC, and GaN, diamond semiconductor devices have superior element performance such as electrical properties and high-frequency properties due to the material strength of diamond, and also have excellent operation in harsh environments such as high temperatures and high radiation. For example, a field-effect transistor such as that disclosed in Patent Document 1 has been proposed as a diamond semiconductor device that can operate in harsh environments. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] Patent Publication No. 2022-104826 [Patent Document 2] Patent Publication No. 2018-078254 [Patent Document 3] Patent No. 4529212 Summary of the Invention [Problem to be solved by the invention]

[0004] The following analysis is provided by the present inventors.

[0005] However, diamond semiconductor devices are difficult to fabricate due to the difficulty of substrate processing and the immaturity of process technology, and so remain limited to very simple structures (see, for example, Patent Document 2). Development of devices with complex structures, such as multi-gate transistors, ICs (Integrated Circuits), and LSIs (Large Scale Integration), which require multi-layer wiring structures, has not progressed.

[0006] In order to realize a multilayer wiring structure in a diamond semiconductor device, it is conceivable to use a multilayer wiring structure in which multiple conductive layers are stacked in a diamond substrate by metal ion implantation, as in Patent Document 3. However, when attempting to form an element structure on a diamond substrate with metal ions implanted deep within the substrate, the process becomes complicated due to the difficulty of alignment.

[0007] The main object of the present invention is to provide a diamond semiconductor device, an electrical machine and an apparatus, and a method for manufacturing a diamond semiconductor device, which can contribute to realizing a multilayer wiring structure while avoiding the complexity of the process. [Means for solving the problem]

[0008] A diamond semiconductor device according to a first aspect comprises a diamond semiconductor layer, a plurality of wirings arranged in a multilayered manner on the diamond semiconductor layer, and at least one interlayer insulating layer arranged between the plurality of wirings.

[0009] An electrical device according to a second aspect includes the diamond semiconductor device according to the first aspect.

[0010] A method for manufacturing a diamond semiconductor device according to a third aspect includes the steps of forming a lower layer wiring, an interlayer insulating layer, and an upper layer wiring in this order on a diamond semiconductor layer. [Effects of the Invention]

[0011] The first to third aspects can contribute to realizing a multi-layer wiring structure while avoiding the complexity of the process. [Brief explanation of the drawings]

[0012] [Figure 1] 1 is a plan view schematically showing a first example of the configuration of a diamond semiconductor device according to the present disclosure. [Figure 2] 2A and 2B are schematic diagrams showing an example of the configuration of a diamond semiconductor device according to the present disclosure, in which (A) is a cross-sectional view taken along line X-X' in FIG. 1, (B) is a cross-sectional view taken along line Y-Y' in FIG. 1, and (C) is an enlarged cross-sectional view of R1 in FIG. 2B. [Figure 3] 2A and 2B are cross-sectional views taken along line X-X' and line Y-Y' in FIG. 1, respectively, which schematically show an example of the first step of the method for manufacturing a diamond semiconductor device according to the present disclosure. [Figure 4] 2A and 2B are cross-sectional views taken along line X-X' and line Y-Y' in FIG. 1, respectively, which schematically show an example of the second step of the method for manufacturing a diamond semiconductor device according to the present disclosure. [Figure 5] 2A and 2B are cross-sectional views taken along line X-X' and line Y-Y' in FIG. 1, respectively, which schematically show an example of the third step of the method for manufacturing a diamond semiconductor device according to the present disclosure. [Figure 6] 2A and 2B are cross-sectional views taken along line X-X' and line Y-Y' in FIG. 1, respectively, which schematically show an example of the fourth step of the method for manufacturing a diamond semiconductor device according to the present disclosure. [Figure 7] 2A and 2B are cross-sectional views taken along line X-X' and line Y-Y' in FIG. 1, respectively, which schematically show an example of the fifth step of the method for manufacturing a diamond semiconductor device according to the present disclosure. [Figure 8] 1A and 1B are cross-sectional views taken along line X-X' and line Y-Y', respectively, of a diamond semiconductor device according to the present disclosure, each showing a schematic diagram of an example of the sixth step of the method for manufacturing the diamond semiconductor device. [Figure 9] 1A and 1B are cross-sectional views taken along line X-X' and line Y-Y', respectively, of an example of the seventh step of the method for manufacturing a diamond semiconductor device according to the present disclosure. [Figure 10]1A and 1B are cross-sectional views taken along line X-X' and line Y-Y', respectively, of an example of the eighth step of the method for manufacturing a diamond semiconductor device according to the present disclosure. [Figure 11] 2A and 2B are cross-sectional views taken along line X-X' and line Y-Y' in FIG. 1, respectively, which schematically show an example of the 9th step of the method for manufacturing a diamond semiconductor device according to the present disclosure. [Figure 12] 10 is a graph showing a schematic diagram of the relationship between the drain voltage and the drain current when a predetermined voltage is applied to the first gate electrode pad G-1 of the diamond semiconductor device according to the example. [Figure 13] 10 is a graph showing a schematic diagram of the relationship between the drain voltage and the drain current when a predetermined voltage is applied to the second gate electrode pad G-2 of the diamond semiconductor device according to the example. [Figure 14] 10 is a graph showing a schematic diagram of the relationship between the drain voltage and the drain current when a predetermined voltage is applied to the third gate electrode pad G-3 of the diamond semiconductor device according to the example. [Figure 15] FIG. 2 is a plan view schematically showing a second example of the configuration of the diamond semiconductor device according to the present disclosure. [Figure 16] FIG. 10 is a plan view schematically showing a third example of the configuration of the diamond semiconductor device according to the present disclosure. DETAILED DESCRIPTION OF THE INVENTION

[0013] The following description of the embodiments will be made with reference to the drawings. Note that, when reference numerals are used in this application, they are intended solely to aid understanding and are not intended to limit the present invention to the illustrated embodiments. Furthermore, the following embodiments are merely examples and do not limit the present invention.

[0014] [Form 1] The diamond semiconductor device according to embodiment 1 will be described with reference to the drawings. Fig. 1 is a plan view schematically showing a first example of the configuration of the diamond semiconductor device according to the present disclosure. Fig. 2 is a schematic diagram showing an example of the configuration of the diamond semiconductor device according to the present disclosure, with (A) a cross-sectional view taken along line X-X' in Fig. 1, (B) a cross-sectional view taken along line Y-Y' in Fig. 1, and (C) an enlarged cross-sectional view taken along line R1 in Fig. 2(B).

[0015] The diamond semiconductor device 1 is a device including a diamond substrate 10, an element structure 2 using a diamond semiconductor, and a multilayer wiring structure 3 (see FIG. 1). The element structure 2 can be formed with a multi-gate FET (Field Effect Transistor) as shown in FIG. 2(A), but is not limited thereto. Elements such as a photodetector, a charge-coupled device, a charge-coupled device, a FET, a capacitor, an IC, and an LSI may also be formed. The multilayer wiring structure 3 can be formed with an upper-layer wiring 60a disposed on a third lower-layer wiring 40f via an interlayer insulating layer 50, and a three-dimensional crossing between the third lower-layer wiring 40f and the upper-layer wiring 60a, as shown in FIG. 2(C). However, the multilayer wiring structure 3 is not limited thereto. It is sufficient that a structure in which wiring, insulating layers, and wiring are stacked in this order, or a structure in which wiring and insulating layers are alternately stacked may also be formed. 1 and 2, the diamond semiconductor device 1 includes a diamond substrate 10, a diamond semiconductor layer 11, a source electrode 20a, a drain electrode 20b, an insulating layer 30, gate electrodes 40a to 40c, lower layer wirings 40d to 40f, pads 40g to 40i, an interlayer insulating layer 50, an upper layer wiring 60a, pads 60b, 60c, 60d, 60e, 60f, and a passivation insulating layer 70. The diamond semiconductor device 1 may have a configuration without the passivation insulating layer 70.

[0016] The diamond substrate 10 is a substrate made of diamond (see FIGS. 1 and 2). For example, a high-temperature, high-pressure synthetic diamond single crystal substrate can be used as the diamond substrate 10. The diamond substrate 10 may also be a diamond polycrystalline substrate. The diamond substrate 10 preferably has a surface roughness Ra of less than 100 nm, more preferably 10 nm or less. If the surface roughness Ra of the diamond substrate 10 exceeds 100 nm, it is preferable to polish the diamond substrate 10 so that the surface roughness is 100 nm or less. This has the advantages of reducing the surface roughness Ra of the diamond semiconductor layer 11 synthesized on the diamond substrate 10 and improving the contact between the diamond semiconductor layer 11 and metal layers (gate electrodes 40a-40c, lower-layer wiring 40d-40f, upper-layer wiring 60a) and insulating layers (insulating layer 30, interlayer insulating layer 50, passivation insulating layer 70). The surface of the diamond substrate 10 may be flat or may have steps or recesses for device formation.

[0017] The diamond semiconductor layer 11 is a layer (semiconductor layer) that includes diamond and a portion that functions as a semiconductor (see FIGS. 1 and 2). The thickness of the diamond semiconductor layer 11 can be, for example, several μm or several tens of μm, but is not limited thereto. The diamond semiconductor layer 11 can be formed, for example, by chemical vapor deposition of diamond crystals (epitaxial diamond crystals) on the diamond substrate 10 using hydrogen and methane gas without added impurities, using a microwave plasma CVD apparatus. The diamond semiconductor layer 11 has a hydrogen termination portion 12 on the upper surface (e.g., the (001) plane, the (111) plane, etc.) of a region that will become the channel of the element structure 2. The hydrogen termination portion 12 has a hole channel formed therein and exhibits P-type conductivity. The hydrogen termination portion 12 can be formed, for example, by irradiating the diamond semiconductor layer 11 with hydrogen plasma using a resist mask. The diamond semiconductor layer 11 has contact portions 13a and 13b formed on both sides of the channel of the element structure 2 (on both sides of the hydrogen termination portion 12). The contact portions 13a and 13b are portions where a P-type impurity (for example, boron) is implanted into the diamond semiconductor layer 11. When the P-type impurity is boron, the boron concentration in the contact portions 13a and 13b is, for example, 5×10 19 / cm 3 ~1×10 22 / cm 3 The thickness of the contact portions 13a and 13b can be, for example, about 20 to 300 nm.

[0018] The diamond semiconductor layer 11 is not limited to having the hydrogen termination portion 12, but may have a portion containing (doped or implanted) an impurity (for example, boron, phosphorus, etc.) in the diamond. Instead of having the diamond semiconductor layer 11 on the diamond substrate 10, a free-standing diamond film may be obtained by chemical vapor deposition of a diamond crystal on a seed substrate using hydrogen and methane gas as raw materials using a microwave plasma CVD apparatus, and then removing the seed substrate. The diamond semiconductor layer 11 may also be configured without the contact portions 13a and 13b. When the diamond semiconductor layer 11 does not have the contact portions 13a and 13b, it can be configured with the hydrogen termination portion 12 directly below the source electrode 20a and the drain electrode 20b.

[0019] The source electrode 20a and the drain electrode 20b are electrodes made of a predetermined metal (see FIGS. 1 and 2). The source electrode 20a and the drain electrode 20b can be made of, for example, Au. The source electrode 20a and the drain electrode 20b are formed on the contact portions 13a and 13b. When the diamond semiconductor layer 11 does not have the contact portions 13a and 13b, the source electrode 20a and the drain electrode 20b can be arranged so that the hydrogen termination portion 12 of the diamond semiconductor layer 11 extends directly below the source electrode 20a and the drain electrode 20b and is in direct contact (ohmic contact) with the extended hydrogen termination portion 12. The source electrode 20a and the drain electrode 20b can be formed, for example, by using a lift-off method.

[0020] The insulating layer 30 is a layer made of an insulator and formed on the diamond semiconductor layer 11 including the source electrode 20a, the drain electrode 20b, and the hydrogen termination portion 12 (see FIG. 2). The insulating layer 30 is used as a gate insulating film in the element structure 2. The insulating layer 30 is also used as a protective film for the hydrogen termination portion 12, which becomes the channel between the source electrode 20a and the drain electrode 20b in the element structure 2. This makes it possible to prevent the hydrogen termination portion 12 from being affected by contamination during the manufacturing process. Openings 31 and 32 that lead to the source electrode 20a and the drain electrode 20b are formed in the insulating layer 30. Pads 60b and 60c are formed (embedded) in the openings 31 and 32 on the source electrode 20a and the drain electrode 20b. The insulating layer 30 can be made of, for example, Al2O3. Alternatively, an insulating film having a single layer structure or a laminate structure of any combination of SiO2, HfO2, AlN, BN, Si3N4, SiON, Ta2O5, TiO2, WO3, CaF2, LaF3, MgF2, YF3, LiF, or LiF3 can be used. The insulating layer 30 can be formed, for example, by atomic layer deposition (ALD) or CVD. The thickness of the insulating layer 30 can be, for example, 5 nm to 100 nm. Furthermore, when forming the insulating layer 30, it is preferable to work in a clean environment and select equipment that can achieve a sufficiently high vacuum to prevent contamination. Unlike, for example, Si, the diamond semiconductor layer 11 does not have a high-quality native oxide film, so a process for forming the insulating layer 30 as a gate insulating film is added. Particularly when using multilayer wiring, careful consideration is required for the process for forming the insulating layer 30 on the diamond semiconductor layer 11.

[0021] The gate electrodes 40a to 40c are gate electrodes of the elements in the element structure 2 (see FIGS. 1 and 2). The gate electrodes 40a to 40c are formed on the insulating layer 30 in the region of the hydrogen termination 12. The gate electrodes 40a to 40c are arranged adjacent to each other with a predetermined interval between them. The gate electrodes 40a to 40c are formed so as to cross the hydrogen termination 12. The gate electrodes 40a to 40c are repeatedly formed in the order of gate electrode 40a, gate electrode 40b, and gate electrode 40c between the source electrode 20a and the drain electrode 20b. Each first gate electrode 40a is electrically connected to the first lower-layer wiring 40d via the upper-layer wiring 60a. Each second gate electrode 40b is directly connected to the second lower-layer wiring 40e. Each third gate electrode 40c is directly connected to the third lower-layer wiring 40f.

[0022] The lower-layer wirings 40d-40f are wirings for electrically connecting the corresponding pads 40g-40i and the corresponding gate electrodes 40a-40c (see FIGS. 1 and 2). The lower-layer wirings 40d-40f are formed on the insulating layer 30 in an area other than the element structure portion 2. The lower-layer wirings 40d-40f are directly connected to the corresponding pads 40g, 40h, and 40i. The first lower-layer wiring 40d is electrically connected to the first gate electrode 40a via the upper-layer wiring 60a. The second lower-layer wiring 40e is directly connected to the second gate electrode 40b. The third lower-layer wiring 40f is directly connected to the third gate electrode 40c. The third lower-layer wiring 40f crosses the upper-layer wiring 60a via the interlayer insulating layer 50.

[0023] The pads 40g, 40h, and 40i are bases for electrically connecting to the outside (see FIGS. 1 and 2). The pads 40g, 40h, and 40i are formed on the insulating layer 30 in an area other than the element structure portion 2. The pads 40g, 40h, and 40i are directly connected to the corresponding lower-layer wirings 40d to 40f. The first pad 40g is electrically connected to the first gate electrode 40a via the first lower-layer wiring 40d and the upper-layer wiring 60a. The second pad 40h is electrically connected to the second gate electrode 40b via the second lower-layer wiring 40e. The third pad 40i is electrically connected to the third gate electrode 40c via the third lower-layer wiring 40f.

[0024] The gate electrodes 40a-40c, lower wirings 40d-40f, and pads 40g, 40h, and 40i can be formed on the same layer on the insulating layer 30 and in the same process. The gate electrodes 40a-40c, lower wirings 40d-40f, and pads 40g, 40h, and 40i can be formed, for example, by a lift-off method. The gate electrodes 40a-40c, lower wirings 40d-40f, and pads 40g, 40h, and 40i can be formed using a metal film having a laminate structure of a predetermined combination of Au, Al, Ti, Mo, Cr, Ru, Cu, Pb, Zn, or Pt. The gate electrodes 40a-40c, lower wirings 40d-40f, and pads 40g, 40h, and 40i have a structure in which a lower metal layer 41, a main metal layer 42, and an upper metal layer 43 are laminated in this order on the insulating layer 30. The lower metal layer 41 is a metal layer disposed below the main metal layer 42. The lower metal layer 41 is made of a metal material that ensures a higher adhesion strength between the insulating layer 30 and the lower metal layer 41 than between the insulating layer 30 and the main metal layer 42. The main metal layer 42 is a metal layer disposed between the lower metal layer 41 and the upper metal layer 43. The main metal layer 42 can be made of a metal material that has a lower ionization tendency than the metal materials of the lower metal layer 41 and the upper metal layer 43. The upper metal layer 43 is a metal layer disposed above the main metal layer 42. The upper metal layer 43 is made of a metal material that ensures a higher adhesion strength between the interlayer insulating layer 50 and the upper metal layer 43 than between the interlayer insulating layer 50 and the main metal layer 42. The metal material of the upper metal layer 43 may be the same as or different from the metal material of the lower metal layer 41. The laminated metal layer of the lower metal layer 41, the main metal layer 42, and the upper metal layer 43 may be, for example, a Ti / Au / Ti metal layer, or may be, for example, a Cr / Au / Ti metal layer or a Cr / Au / Cr metal layer, but is not limited to these. The thickness of the laminated metal layer of the lower metal layer 41, the main metal layer 42, and the upper metal layer 43 may be, for example, approximately 10 nm to 500 nm. The thickness of the main metal layer 42 is preferably greater than the thickness of each of the lower metal layer 41 and the upper metal layer 43.The laminated metal layer, consisting of the lower metal layer 41, the main metal layer 42, and the upper metal layer 43, can be formed by physical deposition methods such as sputtering and vapor deposition, or chemical deposition methods such as CVD and MOCVD (Metal Organic Chemical Vapor Deposition). Furthermore, when forming the laminated metal layer, consisting of the lower metal layer 41, the main metal layer 42, and the upper metal layer 43, it is preferable to work in a clean environment and select equipment with a sufficiently high vacuum to prevent contamination. Here, adhesion strength is a value that can be physically evaluated based on the magnitude of peel energy. Since it is difficult to measure the adhesion between films laminated on a small diamond substrate, the stability of electrical properties may be evaluated instead of evaluating adhesion strength. Methods for evaluating the stability of electrical properties include, for example, measuring the variation in electrical properties after multiple measurements, the variation in electrical properties after repeated needle contact, and the variation in electrical properties after a certain period of time.

[0025] The interlayer insulating layer 50 is an insulating layer disposed between the insulating layer 30 and the passivation insulating layer 70 (see FIG. 2). The interlayer insulating layer 50 is formed on the insulating layer 30 including the gate electrodes 40a to 40c, the lower wirings 40d to 40f, and the pads 40g, 40h, and 40i. The interlayer insulating layer 50 has openings 51 and 52 that communicate with the first gate electrode 40a and the first lower-layer wiring 40d through openings 31 and 32 in the insulating layer 30. An upper-layer wiring 60a is formed in the openings 51 and 52. The interlayer insulating layer 50 has openings 53 and 54 that communicate with the source electrode 20a and the drain electrode 20b. A pad 60b and a plug 81 are formed (embedded) in the opening 53. A pad 60c and a plug 82 are formed (embedded) in the opening 54. Although not shown in FIG. 2, the interlayer insulating layer 50 has openings (not shown) that communicate with the pads 40g, 40h, and 40i, and pads 60d to 60f and plugs 80c to 80e are formed (embedded) in the openings. The interlayer insulating layer 50 can be made of, for example, SiO2. Alternatively, an insulating film having a single layer structure or a laminate structure of any combination of Al2O3, HfO2, AlN, BN, Si3N4, SiON, Ta2O5, TiO2, WO3, CaF2, LaF3, MgF2, YF3, LiF, or LiF3 can be used. The material of the interlayer insulating layer 50 can be different from or the same as the material of the insulating layer 30. The thickness of the interlayer insulating layer 50 is preferably 100 nm or more to ensure contact between the gate electrodes 40a-40c and the lower wirings 40d-40f and the insulating layer 30, and is preferably 300 nm or more to ensure flatness or flattening processability of the upper surface of the interlayer insulating layer 50. A thickness of 100 nm for the interlayer insulating layer 50 can ensure a breakdown voltage of 10 V at a breakdown field of 10 MV / cm. The interlayer insulating layer 50 can be formed by, for example, a plasma CVD method which is a high vacuum process and has a high deposition rate.

[0026] The upper-layer wiring 60a is a wiring that bypasses the third lower-layer wiring 40f upward and electrically connects the first lower-layer wiring 40d and the first gate electrode 40a (see FIGS. 1 and 2). The upper-layer wiring 60a is formed at a predetermined position on the interlayer insulating layer 50, and is also formed on the first lower-layer wiring 40d and the first gate electrode 40a through openings 51 and 52 in the interlayer insulating layer 50. Although the upper-layer wiring 60a is formed in a region other than the element structure 2 in FIG. 1, it may also be formed on the element structure 2 (including the gate electrodes 40a to 40c).

[0027] Pads 60b, 60c, 60d, 60e, and 60f are pads formed on the source electrode 20a, the drain electrode 20b, and the pads 40g, 40h, and 40i (see FIGS. 1 and 2). Pad 60b is formed (embedded) in opening 31 of insulating layer 30 and opening 51 of interlayer insulating layer 50. Pad 60c is formed (embedded) in opening 32 of insulating layer 30 and opening 52 of interlayer insulating layer 50. Although not shown in FIG. 2, pads 60d, 60e, and 60f are formed (embedded) in openings (not shown) of interlayer insulating layer 50.

[0028] The upper-layer wiring 60a and pads 60b, 60c, 60d, 60e, and 60f can be formed in the same process. The manufacturing method and materials for the upper-layer wiring 60a and pads 60b, 60c, 60d, 60e, and 60f can be similar to those for the gate electrodes 40a-40c, the lower-layer wirings 40d-40f, and the pads 40g, 40h, and 40i. The upper-layer wiring 60a and pads 60b, 60c, 60d, 60e, and 60f have a structure in which a lower metal layer 61, a main metal layer 62, and an upper metal layer 63 are stacked in this order. The configurations and manufacturing methods for the lower metal layer 61, the main metal layer 62, and the upper metal layer 63 can be similar to those for the lower metal layer 41, the main metal layer 42, and the upper metal layer 43, in terms of material, thickness, and manufacturing method.

[0029] The passivation insulating layer 70 is an insulating layer that covers the interlayer insulating layer 50 including the upper-layer wiring 60a to protect it from the outside (see FIG. 2). The passivation insulating layer 70 has openings 71 and 72 that communicate with the pads 60b and 60c through openings 53 and 54 in the interlayer insulating layer 50. Plugs 81 and 82 are formed (embedded) in the openings 71 and 72. Although not shown in FIG. 2, the passivation insulating layer 70 has openings (not shown) that communicate with the pads 60d, 60e, and 60f through openings (not shown) in the interlayer insulating layer 50, and the pads 60d to 60f are formed (embedded) in the openings. The passivation insulating layer 70 can be made of, for example, SiO2. Alternatively, an insulating film having a single layer structure or a laminate structure of any combination of Al2O3, CaF2, HfO2, AlN, BN, Si3N4, SiON, MgF2, YF3, polyimide, epoxy resin, or acrylic resin can be used. The material of the passivation insulating layer 70 can be the same as the material of the interlayer insulating layer 50, but it can also be a different material. The dielectric constant of the passivation insulating layer 70 is preferably 15 or less to sufficiently suppress adverse effects on frequency characteristics. The thickness of the passivation insulating layer 70 is preferably 500 nm or more. The passivation insulating layer 70 can be manufactured using the same method as the interlayer insulating layer 50. The passivation insulating layer 70 may be omitted.

[0030] The plugs 81 to 85 are formed on the pads 60b to 60f through openings 71 and 72 (there may be openings not shown) in the passivation insulating layer 70 (see FIGS. 1 and 2). For example, W, Al, Cu, etc. can be used as the plugs 81 to 85. The plugs 81 to 85 can be formed using, for example, a sputtering method, a metal CVD method, a CMP (Chemical Mechanical Polishing) method, a blanket method, a selective growth method, etc. Note that the plugs 81 to 85 may not be provided.

[0031] Next, the manufacturing method of the diamond semiconductor device according to embodiment 1 will be described with reference to the drawings. Figures 3 to 11 are (A) a cross-sectional view taken along line X-X' in Figure 1, and (B) a cross-sectional view taken along line Y-Y' in Figure 1, which schematically show an example of steps 1 to 9 of the manufacturing method of the diamond semiconductor device according to the present disclosure. Please refer to Figure 1 for the planar configuration of the diamond semiconductor device.

[0032] First, a diamond semiconductor layer 11 is formed on a diamond substrate 10 (see FIG. 3). The diamond semiconductor layer 11 can be formed by chemical vapor deposition of diamond crystals on the diamond substrate 10 using, for example, a microwave plasma CVD apparatus and hydrogen and methane gases without added impurities as raw materials.

[0033] Next, contact portions 13a and 13b for the source and drain regions of the element structure 2 are formed in the diamond semiconductor layer 11 (see FIG. 4). The contact portions 13a and 13b can be formed by implanting a high concentration of P-type impurity (e.g., boron) into the diamond semiconductor layer 11 (non-doped layer) so as to form ohmic contact with the diamond semiconductor layer 11. When the P-type impurity is boron, the boron concentration of the contact portions 13a and 13b is, for example, 5×10 19 / cm 3 ~1×10 22 / cm 3 The thickness of the contact portions 13a and 13b can be, for example, about 20 to 300 nm. The contact portions 13a and 13b can be formed by, for example, microwave plasma CVD with addition of P-type impurities.

[0034] Next, a hydrogen termination 12 for the channel of the element structure 2 is formed on the diamond semiconductor layer 11 (see FIG. 5). The hydrogen termination 12 can be formed, for example, by hydrogen-terminating the entire surface by microwave plasma CVD or the like, and then oxygen-terminating the area other than the channel area with oxygen plasma.

[0035] Next, an insulating layer 30 is formed on the diamond semiconductor layer 11 including the contact portions 13a, 13b and the hydrogen-terminated portion 12, and then openings 31, 32 that lead to the contact portions 13a, 13b are formed in the insulating layer 30 (see FIG. 6). The insulating layer 30 can be formed by, for example, the ALD method, or it may be formed by the CVD method. The openings 31, 32 can be formed by, for example, lithography and etching.

[0036] Next, the source electrode 20a and the drain electrode 20b are formed on the contact portions 13a and 13b (see FIG. 7). The source electrode 20a and the drain electrode 20b can be formed by using, for example, a lift-off method.

[0037] Next, the gate electrodes 40a to 40c, the lower layer wirings 40d to 40f, and the pads 40g, 40h, and 40i are formed on the insulating layer 30 (see FIG. 8). The gate electrodes 40a to 40c, the lower layer wirings 40d to 40f, and the pads 40g, 40h, and 40i can be formed by using, for example, a lift-off method.

[0038] Next, an interlayer insulating layer 50 is formed on the insulating layer 30 including the gate electrodes 40a-40c, the lower wiring 40d-40f, the source electrode 20a, the drain electrode 20b, and the pads 40g, 40h, and 40i. Thereafter, openings (51-54; openings for the pads 40g, 40h, and 40i are not shown) are formed in the interlayer insulating layer 50, leading to the first gate electrode 40a, the first lower wiring 40d, the source electrode 20a, the drain electrode 20b, and the pads 40g, 40h, and 40i (see FIG. 9). The interlayer insulating layer 50 can be formed using, for example, a plasma CVD method. The openings can be formed by, for example, lithography and etching.

[0039] Next, an upper-layer wiring 60a and pads 60b, 60c, 60d, 60e, and 60f are formed on the interlayer insulating layer 50 including the first gate electrode 40a, the first lower-layer wiring 40d, the source electrode 20a, the drain electrode 20b, and the pads 40g, 40h, and 40i (see FIG. 10). The upper-layer wiring 60a and pads 60b, 60c, 60d, 60e, and 60f can be formed by, for example, a lift-off method.

[0040] Next, a passivation insulating layer 70 is formed on the interlayer insulating layer 50 including the upper wiring 60a and the pads 60b, 60c, 60d, 60e, and 60f, and then openings (71, 72; openings for the pads 60d, 60e, and 60f are not shown) leading to the pads 60b, 60c, 60d, 60e, and 60f are formed in the passivation insulating layer 70 (see FIG. 11). The passivation insulating layer 70 can be formed using, for example, a plasma CVD method. The openings can be formed by, for example, lithography and etching.

[0041] Finally, plugs 81 to 85 are formed in openings (71, 72 and openings for pads 60d, 60e, and 60f are not shown) leading to pads 60b, 60c, 60d, 60e, and 60f (see FIG. 1). The plugs 81 to 85 can be formed by, for example, sputtering, metal CVD, CMP (Chemical Mechanical Polishing), blanket deposition, selective growth, or the like.

[0042] Next, the electrical characteristics of the sample of the diamond semiconductor device according to the first embodiment will be described. Fig. 12 is a graph showing the relationship between the drain voltage and the drain current when a predetermined voltage is applied to the first gate electrode pad G-1 of the diamond semiconductor device according to the example. Fig. 13 is a graph showing the relationship between the drain voltage and the drain current when a predetermined voltage is applied to the second gate electrode pad G-2 of the diamond semiconductor device according to the example. Fig. 14 is a graph showing the relationship between the drain voltage and the drain current when a predetermined voltage is applied to the third gate electrode pad G-3 of the diamond semiconductor device according to the example.

[0043] A sample of the diamond semiconductor device according to the first embodiment (see FIGS. 1 and 2) was obtained as follows. A diamond semiconductor layer 11 (100 nm thick) was formed on a diamond substrate 10 (12.5 mm diameter × 0.25 mm thickness) by microwave plasma CVD. The process parameters, including gas flow, temperature, and microwave output, during the formation of the diamond semiconductor layer 11 were set to 400 sccm, 950°C, and 3.9 kW, respectively. The CH4 / H2 gas ratio (gas flow rate ratio) was 4%. Next, contact portions 13a and 13b for the source and drain regions of the element structure 2 were formed on the diamond semiconductor layer 11 by microwave plasma CVD with boron added. The thickness of the contact portions 13a and 13b was approximately 100 nm. The boron concentration of the contact portions 13a and 13b was 10 19 / cm 3Next, the diamond substrate 10 was hydrogen-terminated, and then partially irradiated with oxygen plasma to form a hydrogen termination 12 for the channel of the element structure 2 on the diamond semiconductor layer 11. Next, an insulating layer 30 (40 nm thick) made of Al2O3 was formed on the diamond semiconductor layer 11, including the contact portions 13a, 13b and the hydrogen termination 12, using the ALD method. Then, openings 31, 32 leading to the contact portions 13a, 13b were formed in the insulating layer 30. In the ALD method, HO was used as the oxidizing agent, and the synthesis temperature was set to 300°C. Next, using the lift-off method, a source electrode 20a and a drain electrode 20b were formed on the contact portions 13a, 13b, each made of a metal layer (thickness: Ti / Au / Ti = 30 / 100 / 30 nm) stacked in this order from the bottom. In the lift-off method, the source electrode 20a and the drain electrode 20b were formed by RF sputtering while heating at 100° C. Next, using the lift-off method, gate electrodes 40a-40c, lower wirings 40d-40f, and pads 40g, 40h, and 40i were formed on the insulating layer 30, each made of a metal layer (thickness: Ti / Au / Ti=30 / 100 / 30 nm) stacked in this order from the bottom up, including Ti, Au, and Ti. Next, using a plasma CVD method, an interlayer insulating layer 50 (400 nm thick) made of SiO2 was formed on the insulating layer 30 including the gate electrodes 40a to 40c, the lower wiring 40d to 40f, the source electrode 20a, the drain electrode 20b, and the pads 40g, 40h, and 40i. After that, openings (51 to 54; openings for the pads 40g, 40h, and 40i are not shown) were formed in the interlayer insulating layer 50, leading to the first gate electrode 40a, the first lower wiring 40d, the source electrode 20a, the drain electrode 20b, and the pads 40g, 40h, and 40i. Next, using a lift-off method, an upper layer wiring 60a and pads 60b, 60c, 60d, 60e, and 60f consisting of metal layers (thickness: Ti / Au / Ti=30 / 100 / 30 nm) stacked in this order from the bottom up were formed on the interlayer insulating layer 50 including the first gate electrode 40a, the first lower layer wiring 40d, the source electrode 20a, the drain electrode 20b, and the pads 40g, 40h, and 40i.Next, using plasma CVD, a passivation insulating layer 70 (500 nm thick) was formed on the interlayer insulating layer 50 including the upper wiring 60a and the pads 60b, 60c, 60d, 60e, and 60f, and then openings (71, 72, openings for pads 60d, 60e, and 60f are not shown) were formed in the passivation insulating layer 70 to connect to the pads 60b, 60c, 60d, 60e, and 60f, thereby obtaining a sample.

[0044] The sample had three types of gate electrodes 40a-40c arranged 20 times between the source and drain electrodes. The gate length of all gate electrodes 40a-40c was 5 μm and the gate width was 100 μm. The thickness and length were measured using a laser microscope (Keyence, VK-X3000) and a stylus step profiler (KLA-Tencor, Alpha-Step IQ) as supplementary measurements. Electrical characteristics were measured using a prober (Hybridge, Ultra-High Vacuum Microprober, HUMP-100) and a semiconductor parameter analyzer (Agilent, B1505A).

[0045] Figure 12 shows the relationship between drain voltage and drain current when a predetermined voltage was applied only to the first gate electrode pad (corresponding to G-1 in Figure 1) of the sample's gate electrode pads. Figure 13 shows the relationship between drain voltage and drain current when a predetermined voltage was applied only to the second gate electrode pad (corresponding to G-2 in Figure 1) of the sample's gate electrode pads. Figure 14 shows the relationship between drain voltage and drain current when a predetermined voltage was applied only to the third gate electrode pad (corresponding to G-3 in Figure 1) of the sample's gate electrode pads. As can be seen from Figures 12 to 14, the performance of each device is very similar. For example, in many devices, the drain current value when a gate voltage of -2V and a drain voltage of 9V was within the range of -6 to -9 μA, which means that the channel resistance and threshold voltage had little variation (±20%). Furthermore, even when a multilayer interconnect structure using metal layers stacked in the order Ti, Au, and Ti from bottom to top was introduced for the gate electrodes 40a-40c, lower-layer interconnects 40d-40f, and upper-layer interconnect 60a, it was confirmed for the first time in a diamond device that transistor operation and good control were possible for each of the three gate electrodes. This would have been difficult to achieve in diamond devices without improving electrode adhesion. This fact also demonstrates the significant significance of form 1 for the widespread adoption of diamond devices, which are difficult to process. While performance appears to vary in Figures 12-14, this is due to factors inherent in the substrate and does not pose a problem to the multilayer interconnect structure. Furthermore, we confirmed that the electrical characteristics showed minimal change even after multiple measurements over a month, demonstrating durability. It should be noted that there are significant concerns about characteristic changes in devices fabricated on diamond, with electrical characteristics often changing significantly over a period of hours or days (e.g., resistance values ​​halving, doubling, or tripling). In this respect, too, the diamond semiconductor device sample according to form 1 exhibits stable performance.

[0046] According to the first embodiment, the third lower layer wiring 40f and the upper layer wiring 60a are arranged in a multi-layer configuration on the diamond semiconductor layer 11, and the interlayer insulating layer 50 is arranged between the third lower layer wiring 40f and the upper layer wiring 60a, which contributes to realizing a multi-layer wiring structure without complicating the process. This eliminates the need to form wiring in the diamond substrate 10, and allows realizing a simple multi-layer wiring structure.

[0047] Furthermore, according to form 1, the third lower layer wiring 40f has a layered structure of a main metal layer 42 and an upper metal layer 43, and the upper metal layer 43 is made of a metal material such that the adhesion strength between the interlayer insulating layer 50 and the upper metal layer 43 is higher than the adhesion strength between the interlayer insulating layer 50 and the main metal layer 42. This can contribute to improving the interlayer adhesion between the metal layer (third lower layer wiring 40f) and the insulating layer (interlayer insulating layer 50) adjacent to the upper side in the stacking direction in a diamond semiconductor device 1 having a multilayer wiring structure portion 3, thereby improving yield.

[0048] One of the factors that reduces the yield of diamond semiconductor devices is the poor adhesion between the insulating layer, diamond semiconductor layer, or semiconductor substrate and the metal layer. The substrate size used in the manufacture of diamond semiconductor devices is smaller than that used in the manufacture of semiconductor devices using materials such as silicon, due to the difficulty of manufacturing large substrates. Therefore, the automated manufacturing equipment used in the manufacture of silicon semiconductor devices cannot be used in the manufacture of diamond semiconductor devices. That is, automated manufacturing equipment is designed for substrates of a certain size (e.g., 4 inches or 6 inches) for the sake of substrate holding and process monitoring, and therefore cannot be used for diamond substrates smaller than that. In addition, diamond semiconductor films are often grown using vapor phase growth, and precise control of the growth thickness is difficult. As a result, the thickness of diamond substrates varies, preventing the use of automated manufacturing equipment that processes a large number of substrates of the same thickness under the same conditions. Therefore, diamond semiconductor devices are manufactured manually. When diamond semiconductor devices are manufactured manually, there is a high possibility that contaminants such as particles, ions, and impurities that affect yields will be introduced between layers during the formation of insulating and metal layers, resulting in poor interlayer adhesion and reduced yields. Poor interlayer adhesion can lead to issues beyond simple yields, such as poor electrical characteristics (such as the generation of excess resistance) and poor performance stability (electrical characteristics fluctuating depending on the electrode contact), limiting device performance. In particular, due to the lack of progress in the development of diamond semiconductor devices with multilayer wiring structures, there has been no technology to ensure interlayer adhesion between a metal layer and an adjacent insulating layer above it in the stacking direction in diamond semiconductor devices with multilayer wiring structures. In this regard, according to embodiment 1, the interlayer adhesion between the metal layer (third lower layer wiring 40f) and the adjacent insulating layer above it in the stacking direction is improved, thereby improving yields without using automated manufacturing equipment.

[0049] Furthermore, according to form 1, the interlayer adhesion between the third lower layer wiring 40 and the interlayer insulating layer 50 is increased, thereby improving yield, thereby increasing the reliability of the diamond semiconductor device 1 having the multilayer wiring structure 3 and enabling good electrical characteristics to be obtained.

[0050] Furthermore, according to the first aspect, a film formation technique with a high degree of vacuum, such as microwave plasma CVD or ALD, is used, so that contamination can be prevented and yield can be increased.

[0051] Furthermore, according to the first embodiment, the diamond semiconductor layer 11 including the hydrogen termination portion 12 that serves as the channel is covered with the insulating layer 30, so that contamination can be prevented and the yield can be increased.

[0052] Furthermore, according to the first embodiment, the interlayer adhesion between the third lower layer wiring 40 and the interlayer insulating layer 50 is improved, thereby improving the yield, and thus the present invention can be applied to CCDs (Charge Coupled Devices), CMOSs ​​(Complementary Metal Oxide Semiconductors), etc.

[0053] Here, in hydrogen-terminated diamond semiconductor devices, the conductivity of the channel is greatly influenced by surface adsorbates, etc., so generally, compared with semiconductor materials such as ordinary Si, the performance of the element part varies greatly, which has been a major problem for the widespread use of diamond semiconductor devices.In this respect, according to embodiment 1, multiple gate electrodes can be constructed on the same channel in a narrow area, so it becomes possible to manufacture hydrogen-terminated diamond semiconductor devices with multiple gate electrodes.The multiple gate electrodes of the hydrogen-terminated diamond semiconductor device are contained in a rectangular area (channel, in the embodiment, an area of ​​about 1 mm × 0.5 mm) on the surface of the diamond semiconductor layer, with one side being within 1 mm, so even in such diamond semiconductor devices, the variation of each element part using the same channel can be sufficiently suppressed.

[0054] [Form 2] The diamond semiconductor device according to embodiment 2 will be described with reference to the drawings. Fig. 15 is a plan view schematically showing a second example of the configuration of the diamond semiconductor device according to the present disclosure.

[0055] The second embodiment is a modification of the first embodiment, and has a MESFET type element structure in which the insulating layer 30 of FIG. 2 is eliminated (see FIG. 15). The lower metal layer 41 is made of a metal material that makes the adhesion strength between the diamond semiconductor layer 11 and the lower metal layer 41 higher than the adhesion strength between the diamond semiconductor layer 11 and the main metal layer 42. The other configurations and manufacturing methods are the same as those of the first embodiment.

[0056] According to the second embodiment, similarly to the first embodiment, the third lower layer wiring 40f and the upper layer wiring 60a are arranged in a multi-layered manner on the diamond semiconductor layer 11, and an interlayer insulating layer 50 is arranged between the third lower layer wiring 40f and the upper layer wiring 60a, thereby contributing to realizing a multi-layer wiring structure while avoiding the complexity of the process.

[0057] [Form 3] The diamond semiconductor device according to embodiment 3 will be described with reference to the drawings. Fig. 16 is a plan view schematically showing a third example of the configuration of the diamond semiconductor device according to the present disclosure.

[0058] The diamond semiconductor device 1 comprises a diamond semiconductor layer 11, a plurality of wirings 40, 60 arranged in a multi-layered manner on the diamond semiconductor layer 11, and at least one interlayer insulating layer 50 arranged between the plurality of wirings 40, 60.

[0059] According to the third embodiment, the wirings 40 and 60 are arranged in multiple layers on the diamond semiconductor layer 11, and an interlayer insulating layer 50 is arranged between the wirings 40 and 60, which contributes to realizing a multilayer wiring structure while avoiding the process from becoming complicated.

[0060] Some or all of the above aspects may be described as, but are not limited to, the following supplementary notes.

[0061] [Appendix 1] a diamond semiconductor layer; a plurality of wirings arranged in a multilayered manner on the diamond semiconductor layer; At least one interlayer insulating layer disposed between the plurality of wirings; A diamond semiconductor device comprising: [Appendix 2] The diamond semiconductor layer has a hydrogen termination portion in a region that becomes a channel. 2. The diamond semiconductor device according to claim 1. [Appendix 3] The plurality of wirings are arranged on a region other than the hydrogen termination portion. 3. The diamond semiconductor device according to claim 2. [Appendix 4] the plurality of wirings are disposed on the hydrogen termination portion; 3. The diamond semiconductor device according to claim 2. [Appendix 5] a plurality of gate electrodes arranged adjacent to each other on the hydrogen termination portion; 3. The diamond semiconductor device according to claim 2. [Appendix 6] the plurality of wirings include lower layer wirings arranged in a lower layer and upper layer wirings arranged in a layer above the lower layer wirings, The lower layer wiring has a laminated structure of a main metal layer and an upper metal layer, a metal material is used for the upper metal layer such that the adhesion strength between the interlayer insulating layer and the upper metal layer is higher than the adhesion strength between the interlayer insulating layer and the main metal layer; 6. A diamond semiconductor device according to any one of appendices 1 to 5. [Appendix 7] the plurality of wirings include lower layer wirings arranged in a lower layer and upper layer wirings arranged in a layer above the lower layer wirings, a first gate electrode of the plurality of gate electrodes is connected to the upper layer wiring; a second gate electrode different from the first gate electrode among the plurality of gate electrodes is connected to the lower layer wiring; 6. The diamond semiconductor device according to claim 5. [Appendix 8] an insulating layer disposed between the diamond semiconductor layer and the lower wiring; the lower layer wiring includes a lower metal layer interposed between the main metal layer and the insulating layer; a metal material is used for the lower metal layer such that the adhesive strength between the insulating layer and the lower metal layer is higher than the adhesive strength between the insulating layer and the main metal layer; 7. The diamond semiconductor device according to claim 6. [Appendix 9] the upper metal layer is made of Ti; the main metal layer is made of Au, The lower metal layer is made of Ti. 9. The diamond semiconductor device according to claim 8. [Appendix 10] The insulating layer is made of Al2O3. 10. The diamond semiconductor device according to claim 8 or 9. [Appendix 11] the lower layer wiring comprises a lower metal layer disposed between the main metal layer and the diamond semiconductor layer, a metal material is used for the lower metal layer such that the adhesion strength between the diamond semiconductor layer and the lower metal layer is higher than the adhesion strength between the diamond semiconductor layer and the main metal layer; 7. The diamond semiconductor device according to claim 6. [Appendix 12] the upper metal layer is made of Ti; the main metal layer is made of Au, The lower metal layer is made of Ti. 12. The diamond semiconductor device according to claim 11. [Appendix 13] a passivation insulating layer on the upper layer wiring; The upper layer wiring has a laminated structure of another main metal layer and another upper metal layer, a metal material for the other upper metal layer that provides a higher adhesion strength between the passivation insulating layer and the other upper metal layer than a higher adhesion strength between the passivation insulating layer and the other main metal layer; 13. A diamond semiconductor device according to any one of appendixes 6 to 12. [Appendix 14] the upper layer wiring includes another lower metal layer interposed between the other main metal layer and the interlayer insulating layer, a metal material for the other lower metal layer that provides a higher adhesion strength between the interlayer insulating layer and the other lower metal layer than a higher adhesion strength between the interlayer insulating layer and the other main metal layer; 14. A diamond semiconductor device according to any one of appendixes 6 to 13. [Appendix 15] The passivation insulating layer is made of SiO2. 14. The diamond semiconductor device according to claim 13. [Appendix 16] The interlayer insulating layer is made of SiO2. 16. A diamond semiconductor device according to any one of appendixes 1 to 15. [Appendix 17] A diamond semiconductor device in which a plurality of gate electrodes are arranged adjacent to each other on a channel arranged in a rectangular region of the surface of a diamond semiconductor layer, each side of which is 1 mm or less. [Appendix 18] A diamond semiconductor device in which a plurality of wirings are arranged in a multilayered manner on a channel formed in a rectangular region of the surface of a diamond semiconductor layer, each side of which is 1 mm or less. [Appendix 19] An electrical appliance comprising the diamond semiconductor device according to any one of appendixes 1 to 18. [Appendix 20] A method for manufacturing a diamond semiconductor device, comprising the steps of forming a lower layer wiring, an interlayer insulating layer, and an upper layer wiring in this order on a diamond semiconductor layer.

[0062] The disclosures of the above-cited patent documents are incorporated herein by reference and may be used as the basis or part of the present invention, as necessary. Modifications and adjustments of the embodiments are possible within the scope of the entire disclosure of the present invention (including the claims and drawings), and further based on the basic technical concept thereof. Furthermore, various combinations and selections (or non-selections, as necessary) of the various disclosed elements (including each element of each claim, each element of each embodiment or embodiment, each element of each drawing, etc.) are possible within the scope of the entire disclosure of the present invention. In other words, the present invention naturally includes various modifications and alterations that would be possible by a person skilled in the art in accordance with the entire disclosure and technical concept, including the claims and drawings. Furthermore, with regard to the numerical values ​​and numerical ranges described in this application, any intermediate values, lower values, and smaller ranges are deemed to be included, even if not explicitly stated. Furthermore, the disclosures of the above-cited documents, when used in part or in whole in combination with the disclosures herein as part of the disclosure of the present invention, in accordance with the spirit of the present invention, are also deemed to be included in (belong to) the disclosures of this application. [Explanation of symbols]

[0063] 1 Diamond semiconductor device 2. Element structure 3 Multilayer wiring structure 10 Diamond substrate 11 Diamond semiconductor layer 12 Hydrogen termination 13a, 13b Contact part 20a Source electrode 20b Drain electrode 30 insulating layer 31, 32 Opening 40 Lower layer wiring 40a First gate electrode 40b second gate electrode 40c Third gate electrode 40d 1st lower layer wiring 40e Second lower layer wiring 40f 3rd lower layer wiring 40g, 40h, 40i pads 41 Lower metal layer 42 Main metal layer 43 Upper metal layer 50 Interlayer insulation layer 51, 52 Opening 60, 60a upper layer wiring 60b, 60c, 60d, 60e, 60f pads 61 Lower metal layer 62 Main metal layer 63 Upper metal layer 70 Passivation insulating layer 71, 72 Openings 81~85 plug G-1 First gate electrode pad G-2 Second gate electrode pad G-3 Third gate electrode pad S Source Electrode Pad D Drain electrode pad

Claims

1. a diamond semiconductor layer; a plurality of wirings arranged in a multilayered manner on the diamond semiconductor layer; At least one interlayer insulating layer disposed between the plurality of wirings; A diamond semiconductor device comprising:

2. The diamond semiconductor layer has a hydrogen termination portion in a region that becomes a channel. The diamond semiconductor device according to claim 1.

3. The plurality of wirings are arranged on a region other than the hydrogen termination portion. The diamond semiconductor device according to claim 2.

4. the plurality of wirings are disposed on the hydrogen termination portion; The diamond semiconductor device according to claim 2.

5. a plurality of gate electrodes arranged adjacent to each other on the hydrogen termination portion; The diamond semiconductor device according to claim 2.

6. the plurality of wirings include lower layer wirings arranged in a lower layer and upper layer wirings arranged in a layer above the lower layer wirings, The lower layer wiring has a laminated structure of a main metal layer and an upper metal layer, a metal material is used for the upper metal layer such that the adhesion strength between the interlayer insulating layer and the upper metal layer is higher than the adhesion strength between the interlayer insulating layer and the main metal layer; The diamond semiconductor device according to claim 1.

7. the plurality of wirings include lower layer wirings arranged in a lower layer and upper layer wirings arranged in a layer above the lower layer wirings, a first gate electrode of the plurality of gate electrodes is connected to the upper layer wiring; a second gate electrode different from the first gate electrode among the plurality of gate electrodes is connected to the lower layer wiring; The diamond semiconductor device according to claim 5.

8. an insulating layer disposed between the diamond semiconductor layer and the lower wiring; the lower layer wiring includes a lower metal layer interposed between the main metal layer and the insulating layer; a metal material is used for the lower metal layer such that the adhesive strength between the insulating layer and the lower metal layer is higher than the adhesive strength between the insulating layer and the main metal layer; The diamond semiconductor device according to claim 6.

9. the upper metal layer is made of Ti; the main metal layer is made of Au, the lower metal layer is made of Ti; The diamond semiconductor device according to claim 8.

10. The insulating layer is made of Al ２ O ３ Consists of: The diamond semiconductor device according to claim 8.

11. the lower layer wiring comprises a lower metal layer disposed between the main metal layer and the diamond semiconductor layer, a metal material is used for the lower metal layer such that the adhesion strength between the diamond semiconductor layer and the lower metal layer is higher than the adhesion strength between the diamond semiconductor layer and the main metal layer; The diamond semiconductor device according to claim 6.

12. the upper metal layer is made of Ti; the main metal layer is made of Au, the lower metal layer is made of Ti; The diamond semiconductor device according to claim 11.

13. a passivation insulating layer on the upper layer wiring; The upper layer wiring has a laminated structure of another main metal layer and another upper metal layer, a metal material for the other upper metal layer that provides a higher adhesion strength between the passivation insulating layer and the other upper metal layer than a higher adhesion strength between the passivation insulating layer and the other main metal layer; The diamond semiconductor device according to claim 6.

14. the upper layer wiring includes another lower metal layer interposed between the other main metal layer and the interlayer insulating layer, a metal material for the other lower metal layer that provides a higher adhesion strength between the interlayer insulating layer and the other lower metal layer than a higher adhesion strength between the interlayer insulating layer and the other main metal layer; The diamond semiconductor device according to claim 6.

15. The passivation insulating layer is made of SiO ２ Consists of: The diamond semiconductor device according to claim 13.

16. The interlayer insulating layer is made of SiO ２ Consists of: The diamond semiconductor device according to claim 1.

17. An electrical device comprising the diamond semiconductor device according to any one of claims 1 to 16.

18. A method for manufacturing a diamond semiconductor device, comprising the steps of forming a lower layer wiring, an interlayer insulating layer, and an upper layer wiring in this order on a diamond semiconductor layer.

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