Semiconductor device conveyance method and carrier tape

Abstract

To suppress deterioration in the reliability of a semiconductor device.SOLUTION: A semiconductor device conveyance method comprises the steps of: arranging a semiconductor device inside a pocket part; pasting a cover tape on a carrier tape 30 so as to cover the semiconductor device arranged inside the pocket part; and conveying the carrier tape 30 stored with the semiconductor device. In this case, the pocket part comprises: plural corner parts CP each formed with a step part STP1; and plural side parts SP each located between the plural corner parts CP and formed with a first protruding part PLB1 and a second protruding part PLB2. Further, the width of a tip part of each second protruding part PLB2 is smaller than the width of a tip part of each first protruding part PLB1. Moreover, the protrusion amount of each second protruding part PLB2 from each side part SP is larger than the protrusion amount of each first protruding part PLB1 from each side part SP.SELECTED DRAWING: Figure 8

Description

[Technical Field]

[0001] The present invention relates to a method for transporting a semiconductor device and a carrier tape. [Background technology]

[0002] Japanese Patent Laid-Open Publication No. 2018-002211 (Patent Document 1) describes storing a semiconductor device in a storage portion (pocket portion) of an embossed carrier tape. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] Japanese Patent Application Publication No. 2018-002211 Summary of the Invention [Problem to be solved by the invention]

[0004] There are two methods for transporting semiconductor devices: one using a tray made of resin, and the other using a carrier tape. In the method using a tray, manufactured semiconductor devices are stored in multiple storage compartments (pockets) arranged in a matrix on the surface of the tray. To prevent the semiconductor devices from falling out of the storage compartments during transport of the tray, another tray is placed on the tray containing the semiconductor devices, and the tray is transported in this state. In contrast, in the method using a carrier tape, after the manufactured semiconductor devices are stored in the storage compartments of the carrier tape, the semiconductor devices are covered with cover tape to prevent the semiconductor devices from falling out of the storage compartments during transport of the carrier tape. The carrier tape with the cover tape attached to its surface is then wound onto a reel and transported in this state. Note that if the number of semiconductor devices to be transported needs to be increased, the length of the carrier tape wound onto the reel can be increased.

[0005] The present inventors have been studying the use of carrier tape to transport semiconductor devices having wiring substrates, such as ball grid arrays (BGAs) and land grid arrays (LGAs). Their investigations have revealed that, in the case of a transport method using carrier tape, foreign matter may be generated due to vibrations and shocks that occur during transport of the carrier tape housing the semiconductor device. The foreign matter is part of the material that constitutes the carrier tape. The generation of foreign matter may result in a decrease in the reliability of the semiconductor device or may cause problems when the semiconductor device is removed from the carrier tape and mounted on a mounting substrate. Therefore, a shape (structure) of the housing that can minimize the generation of foreign matter is desirable.

[0006] Other objects and novel features will become apparent from the description of this specification and the accompanying drawings. [Means for solving the problem]

[0007] A method for transporting a semiconductor device according to one embodiment includes the steps of placing the semiconductor device in a pocket, attaching a cover tape to the carrier tape so as to cover the semiconductor device placed in the pocket, and transporting the carrier tape containing the semiconductor device. The pocket has a plurality of corners with stepped portions and a plurality of side portions located between the corners and having first and second protrusions. The width of the tip of the second protrusion is smaller than the width of the tip of the first protrusion. Furthermore, the second protrusion protrudes from the side by a greater amount than the first protrusion.

[0008] A carrier tape according to one embodiment has a pocket portion including a plurality of corners each having a step portion formed therein and a plurality of sides each having a first protrusion and a second protrusion, the width of the tip of each of the second protrusions being smaller than the width of the tip of each of the first protrusions. The second protrusions protrude from the sides by a greater amount than the first protrusions.

[0009] A method for transporting semiconductor devices according to one embodiment includes the steps of placing a semiconductor device in a pocket, attaching a cover tape to a carrier tape so as to cover the semiconductor device placed in the pocket, and transporting the carrier tape containing the semiconductor device. Here, the pocket has a plurality of corners with cutouts formed therein and a plurality of sides located between the corners. Furthermore, the planar shapes of the two sides constituting the cutouts form arcs that curve from the first and second sides adjacent to the cutouts toward the apex of the cutout. Furthermore, the cutouts are arranged so that the distance between the two sides constituting the cutouts gradually decreases toward the apex of the cutouts. [Effects of the Invention]

[0010] According to the above embodiment, it is possible to suppress a decrease in reliability of the semiconductor device. [Brief explanation of the drawings]

[0011] [Figure 1] 1 is a top view of a semiconductor device according to an embodiment; [Figure 2] FIG. 2 is a bottom view of the semiconductor device shown in FIG. [Figure 3] FIG. 2 is a cross-sectional view taken along the line AA shown in FIG. [Figure 4] FIG. 2 is an enlarged plan view of a portion of the carrier tape according to the embodiment. [Figure 5] FIG. 5 is a cross-sectional view taken along the line B1-B1 shown in FIG. [Figure 6] FIG. 5 is a cross-sectional view taken along the line B2-B2 shown in FIG. [Figure 7] FIG. 5 is a cross-sectional view taken along the line B3-B3 shown in FIG. [Figure 8] 5 is an enlarged plan view of a portion of the carrier tape after the process shown in FIG. 4. [Figure 9] FIG. 9 is a cross-sectional view taken along the line C1-C1 shown in FIG. [Figure 10] FIG. 9 is a cross-sectional view taken along the line C2-C2 shown in FIG. 8. [Figure 11] FIG. 9 is a cross-sectional view taken along the line C3-C3 shown in FIG. 8. [Figure 12] 9 is an enlarged plan view of a portion of the carrier tape after the process shown in FIG. 8. FIG. [Figure 13] FIG. 13 is a cross-sectional view taken along the line D1-D1 shown in FIG. [Figure 14] FIG. 13 is a cross-sectional view taken along the line D2-D2 shown in FIG. [Figure 15] FIG. 13 is a cross-sectional view taken along the line D3-D3 shown in FIG. [Figure 16] 13 is a diagram showing a state in which the carrier tape is wound around a reel after the process shown in FIG. 12. FIG. [Figure 17] 17 is a diagram showing the reel shown in FIG. 16 housed in a moisture-proof bag. FIG. [Figure 18] FIG. 10 is a cross-sectional view of a modified carrier tape. [Figure 19] FIG. 10 is an enlarged plan view of a portion of a carrier tape according to another embodiment. [Figure 20] FIG. 20 is a cross-sectional view taken along the line E1-E1 shown in FIG. [Figure 21] FIG. 20 is a cross-sectional view taken along the line E2-E2 shown in FIG. [Figure 22] 20 is an enlarged plan view of a portion of the carrier tape after the process shown in FIG. 19. [Figure 23] FIG. 23 is a cross-sectional view taken along the line F1-F1 shown in FIG. 22. [Figure 24] FIG. 23 is a cross-sectional view taken along line F2-F2 shown in FIG. 22. [Figure 25] 23 is an enlarged plan view of a portion of the carrier tape after the process shown in FIG. 22. FIG. [Figure 26] FIG. 26 is a cross-sectional view taken along line G1-G1 shown in FIG. 25. [Figure 27] FIG. 26 is a cross-sectional view taken along line G2-G2 shown in FIG. 25. [Figure 28] 10 is a cross-sectional view showing a state in which a semiconductor device is accommodated in an accommodating portion of a carrier tape of a studied example. FIG. [Figure 29] FIG. 29 is a cross-sectional view showing a state during conveyance of the carrier tape shown in FIG. 28. DETAILED DESCRIPTION OF THE INVENTION

[0012] (Explanation of the description format, basic terms and usage in this application) In this application, the description of the embodiments will be divided into multiple sections, etc., for convenience, as necessary. However, unless otherwise expressly stated, these are not mutually independent and separate, and regardless of the order of description, they are each part of a single example, one being a partial detail of the other, or a partial or complete modification, etc. Furthermore, as a general rule, repeated explanations of similar parts will be omitted. Furthermore, each component in the embodiments is not essential unless otherwise expressly stated, there is a theoretical limit to the number, or it is clearly not essential from the context.

[0013] Similarly, in the description of embodiments, when a material, composition, etc. is described as "X consisting of A," this does not exclude elements other than A, unless otherwise expressly stated or clearly indicated by the context. For example, when referring to a component, it means "X containing A as its primary component." For example, a "silicon component" does not necessarily refer to pure silicon, but also includes SiGe (silicon-germanium) alloys and other multi-component alloys containing silicon as the primary component, as well as components containing other additives. Furthermore, gold plating, Cu layer, nickel plating, etc., are intended to include not only pure components but also components containing gold, Cu, nickel, etc. as their primary components, unless otherwise expressly stated.

[0014] Furthermore, even when a specific number or quantity is mentioned, unless otherwise specified, unless it is theoretically limited to that number, or unless it is clearly not the case from the context, the number may be greater than that specific number or less than that specific number.

[0015] Furthermore, in each drawing of the embodiment, the same or similar parts are indicated by the same or similar symbols or reference numbers, and descriptions thereof will not be repeated in principle.

[0016] In the accompanying drawings, hatching may be omitted even in cross sections if it would be too complicated or if the distinction from voids is clear. In relation to this, background contour lines may be omitted even in the case of holes that are closed in plan view if it is clear from the description, etc. Furthermore, hatching or dot patterns may be added even in cases where the drawing is not a cross section to clearly indicate that the hole is not a void or to clearly indicate the boundary of the area.

[0017] The technology described in the following embodiments is applicable to a carrier tape that houses a semiconductor device having a wiring substrate (a so-called substrate-type semiconductor device). Note that in this embodiment, a BGA-type semiconductor device in which a plurality of solder balls are formed on a plurality of bump lands provided on the underside of a wiring substrate is taken as an example of the substrate type.

[0018] (Embodiment 1) <Semiconductor device> Fig. 1 is a top view of the semiconductor device PKG of the present embodiment 1. Fig. 2 is a bottom view of the semiconductor device PKG shown in Fig. 1. Fig. 3 is a cross-sectional view taken along the line AA shown in Fig. 1.

[0019] 1, the semiconductor device PKG of the first embodiment includes a rectangular wiring board 10 having four sides 10s1, 10s2, 10s3, and 10s4 and four corners 10c1, 10c2, 10c3, and 10c4, and a heat sink LID arranged to cover the upper surface of the wiring board 10. Specifically, as shown in Fig. 1, the wiring board 10 includes a side 10s1 extending in a first direction (the "X1" direction in Fig. 1), a side 10s2 opposing the side 10s1 and extending in the first direction, a side 10s3 located between the two sides 10s1 and 10s2 and extending in a second direction (the "Y1" direction in Fig. 1) perpendicular to the first direction, and a side 10s4 opposing the side 10s3 and extending in the second direction. 1, wiring board 10 has angle 10c1 where side 10s1 and side 10s3 intersect, angle 10c2 where side 10s2 and side 10s4 intersect, angle 10c3 where side 10s4 and side 10s1 intersect, and angle 10c4 where side 10s3 and side 10s2 intersect. Although not shown, wiring board 10 corresponds to one of multiple package areas provided on a single substrate. That is, wiring board 10 is obtained by cutting this single substrate using a dicing blade (a rotating cutting blade) or a punch (a die). Furthermore, heat sink lid is made of, for example, a metal member.

[0020] 2, a plurality of external connection terminals 10e are provided on the lower surface of the semiconductor device PKG of the present embodiment 1. As shown in FIG. 2, the plurality of external connection terminals 10e are provided in a plurality of rows along each of the sides 10s1, 10s2, 10s3, and 10s4 of the wiring substrate 10. In the present embodiment 1, the external connection terminals 10e are solder balls. Specifically, a plurality of bump lands (not shown) are provided on the lower surface of the wiring substrate 10, and each solder ball is formed on each bump land.

[0021] 3, the wiring board 10 has a top surface 10t and a bottom surface 10b opposite the top surface 10t. Although not shown, a plurality of bonding fingers are provided on the top surface 10t of the wiring board 10. The plurality of bonding fingers (terminals) are electrically connected to a plurality of bump lands (terminals) via a plurality of wires (not shown) provided on the wiring board 10. More specifically, a solder resist film (not shown) is formed on the top surface 10t of the wiring board 10, and each bonding finger is exposed in an opening provided in the solder resist film. Similarly, a solder resist film is formed on the bottom surface 10b of the wiring board 10, and each bump land is exposed in an opening provided in the solder resist film. The wiring board 10 of the first embodiment is, for example, a glass epoxy substrate made of glass fiber impregnated with resin.

[0022] 3, a semiconductor chip 20 is mounted on the upper surface 10t of the wiring substrate 10. In the first embodiment, the semiconductor chip 20 is mounted on the wiring substrate 10 via a plurality of bump electrodes BMP so that the main surface 20t of the semiconductor chip 20 faces the upper surface 10t of the wiring substrate 10, as shown in FIG. 3. That is, the semiconductor device PKG of the first embodiment is a so-called face-down (flip-chip) mounted type semiconductor device in which the semiconductor chip 20 is electrically connected to the wiring substrate 10 via a plurality of bump electrodes BMP. Although not shown, a plurality of electrode pads electrically connected to semiconductor elements (e.g., field-effect transistors) formed on the semiconductor chip 20 are provided on the main surface 20t of the semiconductor chip 20, and in the first embodiment, each bump electrode BMP is formed on each electrode pad in advance.

[0023] Furthermore, in the first embodiment, as shown in FIG. 3, a heat sink LID is disposed on the wiring substrate 10 so as to cover the semiconductor chip 20. Also, as shown in FIG. 3, a portion (central portion) of the heat sink LID is fixed to the back surface 20b of the semiconductor chip 20 via a conductive adhesive AM1. Also, as shown in FIG. 3, another portion (peripheral portion) of the heat sink LID is fixed to the wiring substrate 10 via an insulating adhesive AM2. Note that a conductive adhesive may be used as the adhesive AM2. The other portion (peripheral portion) of the heat sink LID is located around the portion (central portion) of the heat sink LID as shown in FIG. 1. Furthermore, as shown in FIG. 3, the heat sink LID is bent so that the other portion (peripheral portion) of the heat sink LID is located closer to the wiring substrate 10 than the portion (central portion) of the heat sink LID. This allows the thickness of the adhesive AM2 to be approximately the same as the thickness of the adhesive AM1. If the adhesive AM2 is made of the same material as the adhesive AM1, only one type of adhesive needs to be prepared.

[0024] <Carrier tape> Next, the carrier tape 30 of the present embodiment 1 will be described. Fig. 4 is an enlarged plan view of a portion of the carrier tape of the present embodiment 1. Fig. 5 is a cross-sectional view taken along the line B1-B1 shown in Fig. 4. Fig. 6 is a cross-sectional view taken along the line B2-B2 shown in Fig. 4. Fig. 7 is a cross-sectional view taken along the line B3-B3 shown in Fig. 4.

[0025] As shown in FIG. 4, the carrier tape 30 of the first embodiment includes two peripheral edge portions 30p1 and 30p2 extending in a first direction (the "X2" direction in FIG. 4), and a central portion 30c located between the two peripheral edge portions 30p1 and 30p2 in a second direction (the "Y2" direction in FIG. 4) perpendicular to the first direction and extending in the first direction. Also, as shown in FIG. 4, each of the peripheral edge portions 30p1 and 30p2 of the carrier tape 30 is provided with a plurality of through holes (sprocket holes) 30h. As shown in FIG. 4, the plurality of through holes 30h are arranged in the first direction. Furthermore, a plurality of storage portions (pocket portions) PKT1 are provided in the central portion 30c of the carrier tape 30. Furthermore, a through hole 30v is provided in the center of each storage portion PKT1. Note that each container PKT1 is formed by embossing the carrier tape 30 using, for example, a mold or air pressure, and therefore the carrier tape 30 of the first embodiment is also called an embossed carrier tape (or blister tape). In addition, in this embodiment, the shapes of the multiple containers PKT1 are the same. Therefore, when providing a detailed description of the containers PKT1 in this embodiment, one container PKT1 will be taken up and described.

[0026] Moreover, the carrier tape 30 of the first embodiment is made of, for example, a resin material with carbon kneaded into it. Specifically, the carrier tape 30 has a structure in which a layer made of conductive polystyrene or conductive polycarbonate is formed on the front and back surfaces of a base material (core layer) made of polystyrene resin, ABS resin, or polyethylene terephthalate resin. That is, the carrier tape 30 of the first embodiment has a certain degree of conductivity. This makes it possible to prevent the carrier tape 30 from becoming electrically charged. As a result, it is possible to prevent a decrease in the reliability of the semiconductor device PKG during transportation of the carrier tape 30 with the semiconductor device PKG accommodated in the accommodation portion PKT1.

[0027] Next, the planar shape of the accommodation portion PKT1 will be described with reference to FIG. 4. The accommodation portion PKT1 of the first embodiment includes four corners CP on which step portions STP1 are formed, and four side portions SP located between two of the four corners CP adjacent to each other in the first direction X2 or the second direction Y2 and on which first protrusion portions PLB1 and second protrusion portions PLB2 are formed. The planar shape of each step portion STP1 is L-shaped. Furthermore, the tip of the first protrusion portion PLB1 protruding from each side portion SP toward the inside of the accommodation portion PKT1 and the tip of the second protrusion portion PLB2 protruding from each side portion toward the inside of the accommodation portion PKT1 have different shapes. Specifically, the width of the tip of the second protrusion portion PLB2 (i.e., the length along the adjacent side portion SP) is smaller than the width of the tip of the first protrusion portion PLB1 (i.e., the length along the adjacent side portion SP). That is, in a plan view, the tip of the second protrusion portion PLB2 is sharper than the tip of the first protrusion portion PLB1. Furthermore, the tip of the second protrusion portion PLB2 is located closer to the inside of the accommodation portion PKT1 than the tip of the first protrusion portion PLB1. That is, the amount of protrusion of the second protrusion portion PLB2 from the side portion SP is greater than the amount of protrusion of the first protrusion portion PLB1 from the side portion SP. Note that the "protrusion amount" of each protrusion here refers to, for example, in the case of a protrusion that protrudes from a side portion SP extending in the first direction X2 toward the inside of the accommodation portion PKT1, the length in the second direction Y2 from the side portion SP to the tip of the protrusion. Furthermore, in the first embodiment, an example will be described in which five first protrusion portions PLB1 and two second protrusion portions PLB2 are provided on each side portion SP, but the number of first protrusion portions PLB1 is not limited to this. In addition, on each side SP, the five first protrusions PLB1 are provided between two second protrusions PLB2. In other words, the two second protrusions PLB2 are located at both ends of each side SP so as to sandwich the first protrusion PLB1 therebetween.

[0028] Next, the cross-sectional shape of the storage portion PKT1 will be described with reference to Figures 5 to 7. First, as shown in Figure 5, the step portion STP1 is provided at each corner CP of the storage portion PKT1 so that the top surface STP1t of this step portion STP1 is located above the bottom surface PKT1b of the storage portion PKT1 and so that the top surface STP1t of this step portion STP1 is located below the top surfaces 30p1t, 30p2t of the peripheral portions 30p1, 30p2. In the first embodiment, as shown in Figure 5, another step portion STP2 is provided between the storage portion PKT1 and each peripheral portion 30p1, 30p2. 5, the other step portion STP2 is provided between the two peripheral portions 30p1 and 30p2 so that the top surface STP2t of the other step portion STP2 is located higher than the top surface STP1t of the step portion STP1 and lower than the top surfaces 30p1t and 30p2t of the peripheral portions 30p1 and 30p2. As shown in FIG. 5, the top surface STP1t of the step portion STP1, the bottom surface PKT1b of the accommodation portion PKT1, the top surfaces 30p1t and 30p2t of the peripheral portions 30p1 and 30p2, and the top surface STP2t of the other step portion STP2 are substantially parallel to one another.

[0029] As described above, the cross-sectional view shown in FIG. 6 corresponds to a cross-sectional view taken along line B2-B2 in FIG. 4. Therefore, although the step portion STP1 described above is not shown in FIG. 6, the first protrusion portion PLB1 and the through-hole 30v can be seen. Furthermore, the tip surface of the first protrusion portion PLB1 (the surface facing the side surface of the wiring board 10) protrudes further inward (toward the through-hole 30v) of the accommodation portion PKT1 than the inner wall surface of the accommodation portion PKT1 (the surface facing the side surface of the wiring board 10) (see FIGS. 5 and 6 together). That is, as shown in FIGS. 5 and 6, the distance DT2 between the tip surfaces of the two first protrusion portions PLB1 facing each other in the second direction Y2 is smaller than the distance DT1 between the inner wall surfaces of the two accommodation portions PKT1 facing each other in the second direction Y2.

[0030] Furthermore, as described above, the cross-sectional view shown in FIG. 7 corresponds to a cross-sectional view taken along line B3-B3 in FIG. 4. Therefore, although the step portion STP1 described above is not shown in FIG. 7, the second protrusion portion PLB2 can be seen. Furthermore, similar to the first protrusion portion PLB1, the tip portion of the second protrusion portion PLB2 (the portion facing the side surface of the wiring board 10) protrudes further inward from the inner wall surface of the accommodation portion PKT1 (see FIGS. 5 and 7 together). That is, as shown in FIGS. 5 and 7, the distance DT3 between the tip portions of the two second protrusion portions PLB2 facing each other in the second direction Y2 is smaller than the distance DT1 between the inner wall surfaces of the two accommodation portions PKT1 facing each other in the second direction Y2. Furthermore, the tip portion of the second protrusion portion PLB2 protrudes further inward from the accommodation portion PKT1 than the tip surface of the first protrusion portion PLB1 (see FIGS. 6 and 7 together). That is, as shown in Figures 6 and 7, the distance DT3 between the tip ends of two second protrusions PLB2 facing each other in the second direction Y2 is smaller than the distance DT2 between the tip ends of two first protrusions PLB1 facing each other in the second direction Y2.

[0031] <Method for transporting semiconductor devices> Next, a method for transporting a semiconductor device according to the first embodiment will be described. First, the semiconductor device PKG described with reference to Figures 1 to 3 and the carrier tape 30 described with reference to Figures 4 to 7 are prepared. The semiconductor device PKG prepared here is, for example, a product (shipped product) that has undergone a series of assembly processes (post-processing) and has been determined to be a non-defective product in a testing process.

[0032] Next, as shown in FIGS. 8 to 11, the semiconductor device PKG is placed (stored) in the storage portion (pocket portion) PKT1 of the carrier tape 30. Specifically, the semiconductor device PKG is placed in the storage portion PKT1 so that the lower surface 10b of the wiring substrate 10 faces the bottom surface PKT1b of the storage portion PKT1. At this time, air is sucked out of the storage portion PKT1 through the through-holes 30v formed in the bottom surface PKT1b of the storage portion PKT1. This allows the semiconductor device PKG to be easily placed in the storage portion PKT1. Also, as shown in FIG. 8, the semiconductor device PKG is placed in the storage portion PKT1 so that the corners 10c1, 10c2, 10c3, and 10c4 of the wiring substrate 10 are positioned at the corners CP of the storage portion PKT1. Note that, as shown in FIG. 8, the wiring substrate 10 is not in contact with the carrier tape 30 at the corners CP of the storage portion PKT1.

[0033] In the semiconductor device PKG disposed in the accommodation portion PKT1, at the position along the line C1-C1 shown in FIG. 8, the lower surface 10b of the peripheral portion of the wiring substrate 10 is in contact with the upper surface STP1t of the step portion STP1 of the carrier tape 30 (see FIG. 9). Note that the "periphery" of the wiring substrate 10 here refers to the region located outside the external connection terminals 10e located in the outermost row of the multiple external connection terminals 10e shown in FIG. 2. Also, as shown in FIG. 9, the lower surface 10b of the wiring substrate 10 and the upper surface STP1t of the step portion STP1 are substantially parallel to each other. Also, at the position along the line C2-C2 shown in FIG. 8, the wiring substrate 10 is spaced apart from the first protrusion portion PLB1 (see FIG. 10). Similarly, the multiple external connection terminals 10e are also spaced apart from the bottom surface PKT1b of the accommodation portion PKT1 (see FIG. 10). That is, at the position along line C2-C2 shown in FIG. 8, the semiconductor device PKG is not in contact with the carrier tape 30. On the other hand, at the position along line C3-C3 shown in FIG. 8, the wiring board 10 is in contact with the second protrusion PLB2 (see FIGS. 8 and 11). That is, the distance between the second protrusion PLB2 and the wiring board 10 is smaller than the distance between the first protrusion PLB1 and the wiring board 10. Here, as shown in FIGS. 10 and 11, the semiconductor device PKG is placed in the accommodation portion PKT1 so that the surface (top surface) of the heat sink LID is positioned higher than the top surface STP2t of another step portion STP2. Furthermore, in the first embodiment, two second protrusion portions PLB2 are provided on each side portion SP of the accommodation portion PKT1, but all (here, a total of eight) second protrusion portions PLB2 do not need to be in contact with the wiring board 10 when the semiconductor device PKG is placed in the accommodation portion PKT1.

[0034] Next, as shown in FIGS. 12 to 15, the cover tape TP is attached to the carrier tape 30 so as to cover the semiconductor device PKG arranged (housed) in the housing portion PKT1. Specifically, as shown in FIG. 12, the cover tape TP is attached to the carrier tape 30 along the central portion 30c extending in the first direction X2 between the two peripheral portions 30p1 and 30p2. At this time, at the position along the line D1-D1 shown in FIG. 12, the cover tape TP is spaced apart from the semiconductor device PKG (see FIG. 13). On the other hand, at the position along the line D2-D2 shown in FIG. 12 and the position along the line D3-D3 shown in FIG. 12, the cover tape TP is in contact with the surface (top surface) of the heat sink LID (see FIGS. 14 and 15). The cover tape TP used in the first embodiment is made of a stretchable material such as polyethylene resin or polyethylene terephthalate resin.

[0035] Here, a carrier tape 100 of a study example studied by the present inventors will be described. FIG. 28 is a cross-sectional view showing a state in which a semiconductor device PKG is accommodated in the accommodation portion PKT100 of the carrier tape 100 of this study example. As shown in FIG. 28, the inner wall surface of the accommodation portion PKT100 of the carrier tape 100 of this study example is inclined in two steps with respect to the bottom surface PKT100b of the accommodation portion PKT100, and at least the step portion STP1, first convex portion PLB1, and second convex portion PLB2 as in the first embodiment are not provided in the accommodation portion PKT100. Therefore, when the semiconductor device PKG is placed in the accommodation portion PKT100, as shown in FIG. 28, the edges EGE of the lower surface 10b of the wiring substrate 10 (i.e., each of the sides 10s1, 10s2, 10s3, and 10s4) come into contact with this inner wall surface (tapered surface). According to the inventors' investigations, the housing portion PKT100, unlike the first embodiment, does not support the lower surface 10b of the wiring substrate 10 with the upper surface STP1t of the step portion STP1. Therefore, it was found that the semiconductor device PKG is easily tilted within the housing portion PKT100 due to vibrations and impacts that occur during transport of the carrier tape 100 (see FIG. 29). As a result, it was found that the inner wall surface of the housing portion PKT100 is scraped off by the edge EGE of the wiring substrate 10. Furthermore, a portion of the scraped off carrier tape 100 may become foreign matter and scatter within the housing portion, potentially adhering to the external connection terminals 10e of the semiconductor device PKG so as to straddle the external connection terminals 10e. Furthermore, if the carrier tape is conductive, adhering a portion of the carrier tape to the semiconductor device PKG so as to straddle the external connection terminals 10e results in a defective product. As a countermeasure, the inventors also considered using a non-conductive carrier tape. However, even if an insulating carrier tape is used, if a part of the carrier tape becomes a foreign object and scatters inside the housing, it may adhere to the external connection terminals 10e of the semiconductor device PKG. If a foreign object adheres to the external connection terminals 10e, even if the foreign object is insulating, it may cause a mounting failure when the semiconductor device PKG is mounted on, for example, a mounting board.

[0036] 9, in the case of the carrier tape 30 of the first embodiment, the lower surface 10b of the wiring substrate 10 is supported not by the edge EGE of the wiring substrate 10 but by the step portions STP1 provided at each corner CP of the accommodation portion PKT1. Therefore, it is possible to prevent the semiconductor device PKG from moving within the accommodation portion PKT1 due to vibrations or impacts that occur during transportation of the carrier tape 30 or the weight of the semiconductor device PKG itself.

[0037] 9 and 10, the wiring substrate 10 is supported by step portions STP1 provided at each corner CP of the housing portion PKT1 so that the external connection terminals 10e do not come into contact with the bottom surface PKT1b of the housing portion PKT1. Here, the planar shape of the step portions STP1 is an L-shape along two adjacent sides of the four sides of the rectangular wiring substrate, as shown in FIG. 4. Therefore, when the semiconductor device PKG is placed in the housing portion PKT1, the lower surface 10b of the peripheral portion of the wiring substrate 10 comes into contact with the step portion STP1, but the external connection terminals 10e do not come into contact with the step portion STP1. As a result, deformation of the external connection terminals 10e due to the weight of the semiconductor device PKG can be suppressed.

[0038] Furthermore, in the case of the carrier tape 30 of the first embodiment, while the carrier tape 30 is being transported, the lower surface 10b of the wiring substrate 10 is supported by the step portion STP1, while the side surface of the wiring substrate 10 is supported by the second protrusion portion PLB2 of the carrier tape. Specifically, while the carrier tape 30 is being transported, the tip portion of the first protrusion portion PLB1, which has a width greater than that of the tip portion of the second protrusion portion PLB2, does not come into contact with the wiring substrate 10. That is, in the case of the carrier tape 30 of the first embodiment, the total area of ​​the carrier tape that comes into contact with the semiconductor device PKG is smaller than when the carrier tape 100 of the studied example is used. Therefore, it is possible to reduce the amount of foreign matter (parts of the carrier tape scraped off) generated by vibrations and impacts that occur during transport of the carrier tape 30 or the weight of the semiconductor device PKG.

[0039] Furthermore, in the case of the carrier tape 30 of the present embodiment 1, two second protrusions PLB2 are provided on each side SP of the accommodation portion PKT1, and on both ends of each side SP. Therefore, it is possible to prevent the semiconductor device PKG from rotating in the accommodation portion PKT1 due to vibrations or impacts that occur during transport of the carrier tape 30, and to prevent the side surface of the wiring board 10 from coming into contact with the inner wall surface of the accommodation portion PKT1.

[0040] Furthermore, in the case of the carrier tape 30 of the first embodiment, as described above, at the stage of attaching the cover tape TP to the carrier tape 30, the semiconductor device PKG is disposed in the accommodation portion PKT1 so that the surface (top surface) of the heat sink LID is positioned above the top surface STP2t of the other step portion STP2. Therefore, as shown in FIGS. 14 and 15 , when the cover tape TP is attached to the carrier tape 30, the cover tape TP is deformed by the amount by which the semiconductor device PKG protrudes outward from the accommodation portion PKT1. That is, a force is applied that presses the semiconductor device PKG toward the bottom surface PKT1b of the accommodation portion PKT1. This more reliably prevents the semiconductor device PKG from moving within the accommodation portion PKT1 even if vibrations or impacts occur during transport of the carrier tape 30. As a result, the amount of foreign matter generated can be further reduced.

[0041] Next, as shown in FIG. 16, the carrier tape 30 with the cover tape TP attached thereto is wound onto a reel REL. Note that the length of the carrier tape 30 that can be wound varies depending on the size of the reel REL used. Then, the reel REL with the carrier tape 30 wound around it is packaged in a moisture-proof bag BAG as shown in FIG. 17. Note that a label LAB indicating the product name, model number, etc., is attached to the surface of the moisture-proof bag BAG made of, for example, aluminum, and then the moisture-proof bag BAG with the reel REL packed therein is transported (or shipped). Then, at the transport destination, guide pins (not shown) are inserted into through holes 30h provided in each peripheral portion 30p1, 30p2 of the carrier tape 30 to feed the carrier tape 30 from the reel REL, and the semiconductor device PKG is then removed from each housing portion PKT1.

[0042] (Variation 1) Next, a modification of the first embodiment will be described with reference to FIG. 18. First, FIG. 18 corresponds to the position of line C3-C3 shown in FIG. 8 in the carrier tape 30 of the first embodiment, and differs from FIG. 11 in the shape of the second protrusion PLB2. Specifically, as shown in FIG. 18, the second protrusion PLB2m of the first modification has a first portion PLB2ma connected to the bottom surface PKT1b of the accommodating portion PKT1 and a second portion PLB2mb connected to the first portion PLB2ma, between the bottom surface PKT1b of the accommodating portion PKT1 and another step portion STP2. Also, as shown in FIG. 18, the inclination from the bottom surface PKT1b of the accommodating portion PKT1 to the inner wall surface of the second portion PLB2mb is greater than the inclination from the bottom surface PKT1b of the accommodating portion PKT1 to the inner wall surface of the first portion PLB2ma. 18, the point where the first portion PLB2ma and the second portion PLB2mb intersect with each other (i.e., the bending point of the second protrusion portion PLB2m) is located between the upper surface 10t and the lower surface 10b of the wiring board 10 of the semiconductor device PKG accommodated in the accommodation portion PKT1. That is, the second protrusion portion PLB2 in the first embodiment has a cross-sectional shape that contacts the side surface of the wiring board 10 over a wide area in the thickness direction of the wiring board 10. In contrast, the second protrusion portion PLB2m in the first modification is inclined in two steps as shown in FIG. 18, and therefore the area (length) where the second protrusion portion PLB2m contacts the side surface of the wiring board 10 in the thickness direction of the wiring board 10 can be reduced. As a result, the amount of foreign matter generated can be further reduced.

[0043] (Embodiment 2) Next, the present embodiment 2 will be described. The difference between the present embodiment 2 and the above-mentioned embodiment 1 is in the shape (structure) of the storage section of the carrier tape, and the other parts are the same as those described in the above-mentioned embodiment 1. Therefore, in the present embodiment 2, the differences from the above-mentioned embodiment 1 will mainly be described.

[0044] <Carrier tape> Fig. 19 is an enlarged plan view of a portion of the carrier tape of the second embodiment. Fig. 20 is a cross-sectional view taken along the line E1-E1 shown in Fig. 19. Fig. 21 is a cross-sectional view taken along the line E2-E2 shown in Fig. 19. The position of the line E1-E1 shown in Fig. 19 corresponds to the position of the line B1-B1 shown in Fig. 4. The position of the line E2-E2 shown in Fig. 19 corresponds to the position of the line B2-B2 shown in Fig. 4.

[0045] As shown in FIG. 19, the container PKT2 of the second embodiment includes four corners CP each having a cutout CTP formed therein, and four sides SP located between two adjacent corners CP in the first direction X2 or the second direction Y2. The planar shapes of the two sides CTPS constituting each cutout CTP form arcs that curve from the adjacent side SP toward the tip (vertex) TIP of the cutout CTP. That is, the container PKT2 does not have a bending point between a certain side SP (more specifically, the boundary between the side SP and the corner CP) and the tip TIP of the cutout CTP provided in the corner CP adjacent to that side SP. Furthermore, the side SP does not have the protrusions PLB1 and PLB2 described in the first embodiment. That is, the planar shape of each side SP is a straight line extending in the first direction X2 or the second direction Y2.

[0046] Next, the cross-sectional shape of the receiving portion PKT2 will be described with reference to FIGS. 20 and 21. First, as shown in FIG. 20, the carrier tape 40 of the second embodiment does not have the step portions STP1 and STP2 as in the first embodiment, and therefore the cross-sectional shape along the E1-E1 line shown in FIG. 19 is substantially the same as the cross-sectional shape along the E2-E2 line also shown in FIG. 19. However, as described above, each corner CP of the receiving portion PKT2 of the second embodiment has a cutout portion CTP. Therefore, as shown in FIGS. 20 and 21, the distance DT22 between the two side portions SP facing each other in the second direction Y2 is smaller than the distance DT11 between the inner wall surfaces of the two cutout portions CTP facing each other in the second direction Y2. Furthermore, this distance DT11 increases toward the tip (apex) TIP of the cutout portion CTP.

[0047] <Method for transporting semiconductor devices> Next, a description will be given of a method for transporting a semiconductor device according to the present embodiment 2. First, the semiconductor device PKG described with reference to Figures 1 to 3 and the carrier tape 40 described with reference to Figures 19 to 21 are prepared.

[0048] 22 to 24, the semiconductor device PKG is placed (stored) in the storage section (pocket section) PKT2 of the carrier tape 40. Specifically, the semiconductor device PKG is placed in the storage section PKT2 so that the lower surface 10b of the wiring substrate 10 faces the bottom surface PKT2b of the storage section PKT2. Also, as shown in FIG. 22, the semiconductor device PKG is placed in the storage section PKT2 so that the corners 10c1, 10c2, 10c3, and 10c4 of the wiring substrate 10 are located in the respective corners CP of the storage section PKT2. At this time, since the corners 10c1, 10c2, 10c3, and 10c4 of the wiring substrate 10 are located within the respective cutout portions CTP, as shown in FIG. 22, the wiring substrate 10 is not in contact with the carrier tape 40 at the respective corners CP of the storage section PKT2, as in the first embodiment.

[0049] 22 (i.e., the peripheral portion of the wiring board 10), the semiconductor device PKG including the wiring board 10, the heat sink LID, etc. is not in contact with the carrier tape 40 (see FIG. 23). On the other hand, at the position along the line F2-F2 shown in FIG. 22, the wiring board 10 is in contact with the inner wall surface of the housing portion PKT2 of the carrier tape 40 (see FIG. 24). Specifically, as shown in FIG. 22, the wiring board 10 is in contact with the carrier tape 40 (i.e., the inner wall surface of the housing portion PKT2) over the entire area of ​​each side portion SP of the housing portion PKT2. This is because, in the second embodiment, the protrusions PLB1 and PLB2 as in the first embodiment are not provided on the side portions SP adjacent to the sides 10s1, 10s2, 10s3, and 10s4 of the wiring board 10. Therefore, in a plan view, the width (length) of the portion of the carrier tape that contacts the wiring board 10 is larger than the width (length) of the tip of each of the protruding portions PLB1, PLB2 that contact the wiring board 10. As a result, compared to the carrier tape 30 of the above-mentioned first embodiment, the area where the carrier tape 40 and the semiconductor device PKG come into contact with each other is larger, while the impact per unit area generated by the contact between the carrier tape 40 and the semiconductor device PKG is smaller. This makes it possible to reduce the amount of foreign matter (part of the carrier tape scraped off) generated by the vibration or impact generated during transportation of the carrier tape 40 or the weight of the semiconductor device PKG itself.

[0050] As described above, each corner portion CP of the accommodation portion PKT2 of the second embodiment does not have a step portion STP1 as in the first embodiment (see FIG. 19). This is because, as shown in FIG. 19, each cutout portion CTP is provided so that the distance between the two sides CTPS constituting the cutout portion CTP gradually decreases toward the tip TIP of the cutout portion CTP. That is, this is because processing each corner portion CP of the second embodiment is more difficult than in the first embodiment. Therefore, as shown in FIG. 24, the external connection terminal 10e of the semiconductor device PKG arranged in the accommodation portion PKT2 is in contact with the bottom surface PKT2b of the accommodation portion PKT2.

[0051] 25 to 27, the cover tape TP is attached to the carrier tape 40 so as to cover the semiconductor device PKG arranged (housed) in the housing portion PKT2. Specifically, as shown in FIG. 25, the cover tape TP is attached to the carrier tape 40 along the central portion 40c extending in the first direction X2 between the two peripheral portions 40p1, 40p2. At this time, the cover tape TP is spaced apart from the semiconductor device PKG at the position along the line G1-G1 shown in FIG. 25 (see FIG. 26). The cover tape TP is also spaced apart from the semiconductor device PKG at the position along the line G2-G2 shown in FIG. 25 (see FIG. 27). This is because the housing portion PKT2 of the second embodiment does not have the step portion STP2 described in the first embodiment.

[0052] The invention made by the inventor has been specifically described above based on an embodiment, but it goes without saying that the present invention is not limited to the above embodiment and can be modified in various ways without departing from the gist of the invention.

[0053] For example, in the above-described embodiments, a so-called face-down (flip-chip) mounting type semiconductor device in which the semiconductor chip 20 is electrically connected to the wiring substrate 10 via a plurality of bump electrodes BMP has been described as an example of the semiconductor device PKG. However, a so-called face-up mounting type semiconductor device using a plurality of bonding wires may also be used. That is, the semiconductor device PKG may not have a heat sink LID. On the other hand, in the case of the semiconductor device PKG of each of the above-described embodiments, since it also has a heat sink LID, the weight of the semiconductor device 10 is greater than the weight of a face-up mounting type semiconductor device. Therefore, the above-described foreign matter is also noticeable when the semiconductor device PKG of the present embodiment is transported.

[0054] 3, the heat sink LID is bent so that another part (periphery) of the heat sink LID is closer to the wiring board 10 than one part (center) of the heat sink LID. However, a heat sink that is not bent may also be used. However, when a heat sink that is not bent is used, the thickness of the adhesive material AM2 needs to be increased.

[0055] Furthermore, for example, in the above-described embodiments, the carrier tape has been described as having a certain degree of conductivity, but an insulating carrier tape may also be used. However, even if an insulating carrier tape is used, if a portion of the carrier tape becomes a foreign object and scatters inside the housing, it may adhere to the external connection terminals 10e of the semiconductor device PKG. If a foreign object adheres to the external connection terminals 10e, even if the foreign object is insulating, it may cause a mounting failure when the semiconductor device PKG is mounted on, for example, a mounting board. On the other hand, the structure of the housing portions PKT1 and PKT2 in the above-described embodiments can prevent a portion of the carrier tape from becoming a foreign object and scattering, so the housing portions PKT1 and PKT2 in the above-described embodiments are also effective for carrier tapes that do not have conductivity.

[0056] Furthermore, for example, in the above-described first embodiment, an example in which a separate step portion STP2 is provided between the accommodation portion PKT1 and each peripheral portion 30p1, 30p2 has been described. However, this separate step portion STP2 does not have to be provided. However, in order to prevent the semiconductor device PKG from moving as much as possible during transport of the carrier tape 30, it is preferable to provide this separate step portion STP2 as in the above-described first embodiment. Similarly, in the above-described second embodiment, an example in which a separate step portion STP2 is not provided between the accommodation portion PKT2 and each peripheral portion 40p1, 40p2 has been described. However, from the viewpoint of preventing the semiconductor device PKG from moving as much as possible during transport of the carrier tape 40, it is preferable to provide the separate step portion STP2 in the carrier tape 40 of the above-described second embodiment, as in the above-described first embodiment. This allows the semiconductor device PKG placed in the accommodation portion PKT2 of the carrier tape 40 to be pressed against the bottom surface PKT2b of the accommodation portion PKT2, thereby more reliably preventing the semiconductor device PKG from moving within the accommodation portion PKT2 during transport of the carrier tape 40. However, from the viewpoint of minimizing deformation of the external connection terminals 10e, it is preferable not to provide a separate step portion STP2 in the carrier tape 40 of the second embodiment, which does not have the step portion STP1 as in the first embodiment.

[0057] Furthermore, for example, in the above embodiment 2, an example was described in which the step portion STP1 described in embodiment 1 is not provided at each corner CP of the storage portion PKT2, but this description does not exclude the provision of a step portion STP1 at each corner CP of the storage portion PKT2. [Explanation of symbols]

[0058] AM1,AM2 Adhesive BAG Moisture-proof bag BMP bump electrode CP corner CTP cutout CTPS side EGE Edge LAB Label LID heat sink PKG semiconductor device PKT1, PKT2, PKT100 storage area (pocket) PKT1b, PKT2b, PKT100b bottom PLB1, PLB2, PLB2m convex part REL Reel SP side part STP1, STP2 step section STP1t,STP2t top surface TP Cover Tape 10. Wiring board 10c1,10c2,10c3,10c4 corner 10e External connection terminal 10s1, 10s2, 10s3, 10s4 sides 10t top surface 10b Bottom side 20 Semiconductor chips 20t main surface 20b back side 30 Carrier Tape 30c central part 30h through hole 30p1, 30p2 peripheral area 30p1t,30p2t top surface 30v through hole 40 Carrier Tape 40c central part 40h through hole 40p1, 30p2 peripheral area 40p1t,40p2t top surface 40v through hole 100 Carrier Tape

Claims

1. A method for transporting a semiconductor device, comprising the following steps: (a) preparing the semiconductor device, the semiconductor device including: a wiring substrate having an upper surface and a lower surface opposite to the upper surface; a semiconductor chip mounted on the upper surface of the wiring substrate; and a plurality of external connection terminals provided on the lower surface of the wiring substrate; (b) preparing a carrier tape including a first peripheral edge portion and a second peripheral edge portion extending in a first direction, and a plurality of pocket portions positioned between the first peripheral edge portion and the second peripheral edge portion in a second direction perpendicular to the first direction and arranged side by side in the first direction; (c) after steps (a) and (b), placing the semiconductor device in the first pocket portion so that the lower surface of the wiring substrate faces a bottom surface of the first pocket portion among the plurality of pocket portions; (d) after (c), attaching a cover tape to the carrier tape so as to cover the semiconductor device disposed in the first pocket portion; (e) after (d), a step of transporting the carrier tape on which the semiconductor device is housed; where: The planar shape of the wiring board is rectangular, The first pocket portion, in a plan view, four corners where the first step portions are formed; four side portions that are located between two of the four corner portions that are adjacent to each other in the first direction or the second direction and that have first convex portions and second convex portions formed thereon; It is equipped with the first step portion has an upper surface formed so as to be located higher than the bottom surface of the first pocket portion and lower than upper surfaces of the first peripheral edge portion and the second peripheral edge portion in a cross-sectional view; In a plan view, a tip end portion of the first convex portion protruding from a first side portion of the four side portions toward the inside of the first pocket portion and a tip end portion of the second convex portion protruding from the first side portion toward the inside of the first pocket portion have different shapes from each other, In a plan view, a width of the tip end of the second protrusion is smaller than a width of the tip end of the first protrusion, In a plan view, a protrusion amount of the second convex portion from the first side portion is larger than a protrusion amount of the first convex portion from the first side portion, the semiconductor device disposed in the first pocket portion by (c) is spaced apart from the first protrusion, and the lower surface of the wiring substrate is in contact with the upper surface of the first step portion; A method for transporting semiconductor devices.

2. 2. The semiconductor device transport method according to claim 1, the semiconductor chip has a main surface, a plurality of electrode pads formed on the main surface, and a back surface opposite to the main surface; the semiconductor chip is mounted on the wiring substrate via a plurality of bump electrodes such that the main surface of the semiconductor chip faces the upper surface of the wiring substrate; a heat sink made of a metal member is fixed to the back surface of the semiconductor chip; A method for transporting semiconductor devices.

3. 2. The semiconductor device transport method according to claim 1, the wiring board is a glass epoxy board, The carrier tape is made of a resin material kneaded with carbon. A method for transporting semiconductor devices.

4. 2. The semiconductor device transport method according to claim 1, Each of the first peripheral portion and the second peripheral portion has a plurality of through holes arranged in the first direction. A method for transporting semiconductor devices.

5. 2. The semiconductor device transport method according to claim 1, the carrier tape prepared in (b) further includes a second step portion provided between the first pocket portion in which the first step portion is formed and the first peripheral edge portion and the second peripheral edge portion in the second direction; the second step portion has an upper surface that is located higher than the upper surface of the first step portion and lower than the upper surfaces of the first peripheral edge portion and the second peripheral edge portion in a cross-sectional view; In the step (d), the cover tape is attached to the upper surface of the second step portion. A method for transporting semiconductor devices.

6. 2. The semiconductor device transport method according to claim 1, a planar shape of the first step portion is an L-shape along two adjacent sides of four sides of the wiring substrate; A method for transporting semiconductor devices.

7. 2. The semiconductor device transport method according to claim 1, The second protrusions are located at both ends of the first side portion so as to sandwich the first protrusion in a plan view. A method for transporting semiconductor devices.

8. 2. The semiconductor device transport method according to claim 1, In a cross-sectional view, the second protrusion has a first portion connected to the bottom surface of the first pocket portion and a second portion connected to the first portion, an inclination of the second portion with respect to the bottom surface of the first pocket portion being smaller than an inclination of the first portion with respect to the bottom surface of the first pocket portion; after (c), a bending point of the second convex portion where the first portion and the second portion intersect with each other is located between the upper surface of the wiring substrate and the lower surface of the wiring substrate of the semiconductor device arranged in the first pocket portion; A method for transporting semiconductor devices.

9. 2. The semiconductor device transport method according to claim 1, In the step (e), the carrier tape containing the semiconductor device is transported in a state of being wound around a reel. A method for transporting semiconductor devices.

10. a first peripheral edge portion extending in a first direction; a second peripheral portion extending in the first direction; a plurality of pockets positioned between the first peripheral edge portion and the second peripheral edge portion in a second direction perpendicular to the first direction and arranged side by side in the first direction; Equipped with Each of the plurality of pocket portions, in a plan view, four corners where the first step portions are formed; four side portions that are located between two of the four corner portions that are adjacent to each other in the first direction or the second direction and that have first convex portions and second convex portions formed thereon; It is equipped with the first step portion has an upper surface formed so as to be located higher than the bottom surfaces of the plurality of pocket portions and lower than the upper surfaces of the first peripheral edge portion and the second peripheral edge portion in a cross-sectional view; In each of the plurality of pocket portions, a tip end portion of the first convex portion protruding inward from a first side portion of the four side portions and a tip end portion of the second convex portion protruding inward from the first side portion have different shapes from each other, In a plan view, a width of the tip end of the second protrusion is smaller than a width of the tip end of the first protrusion, In a plan view, a protrusion amount of the second convex portion from the first side portion is larger than a protrusion amount of the first convex portion from the first side portion. Carrier tape.

11. The carrier tape according to claim 10 is made of a resin material kneaded with carbon. Carrier tape.

12. The carrier tape according to claim 10, Each of the first peripheral portion and the second peripheral portion has a plurality of through holes arranged in the first direction. Carrier tape.

13. The carrier tape according to claim 10 further includes second step portions provided between each of the plurality of pocket portions in which the first step portions are formed and the first peripheral edge portion and the second peripheral edge portion in the second direction, the second step portion has an upper surface that is located higher than the upper surface of the first step portion and lower than the upper surfaces of the first peripheral edge portion and the second peripheral edge portion in a cross-sectional view; Carrier tape.

14. The carrier tape according to claim 10, The first step portion has an L-shape in plan view. Carrier tape.

15. The carrier tape according to claim 10, The second protrusions are located at both ends of the first side portion so as to sandwich the first protrusion in a plan view. Carrier tape.

16. The carrier tape according to claim 10, In a cross-sectional view, the second protrusion has a first portion connected to the bottom surface of each of the plurality of pocket portions and a second portion connected to the first portion, an inclination of the second portion with respect to the bottom surface of each of the plurality of pockets being smaller than an inclination of the first portion with respect to the bottom surface of each of the plurality of pockets; Carrier tape.

17. A method for transporting a semiconductor device, comprising the following steps: (a) preparing the semiconductor device, the semiconductor device including: a wiring substrate having an upper surface and a lower surface opposite to the upper surface; a semiconductor chip mounted on the upper surface of the wiring substrate; and a plurality of external connection terminals provided on the lower surface of the wiring substrate; (b) preparing a carrier tape including a first peripheral edge portion and a second peripheral edge portion extending in a first direction, and a plurality of pocket portions positioned between the first peripheral edge portion and the second peripheral edge portion in a second direction perpendicular to the first direction and arranged side by side in the first direction; (c) after steps (a) and (b), placing the semiconductor device in the first pocket portion so that the lower surface of the wiring substrate faces a bottom surface of the first pocket portion among the plurality of pocket portions; (d) after (c), attaching a cover tape to the carrier tape so as to cover the semiconductor device disposed in the first pocket portion; (e) after (d), a step of transporting the carrier tape on which the semiconductor device is housed; where: The planar shape of the wiring board is a square shape having corners, The first pocket portion, in a plan view, four corners in which notches are formed; four side portions located between two of the four corner portions that are adjacent to each other in the first direction or the second direction; It is equipped with the planar shapes of the two sides constituting the cutout portion describe arcs that curve from each of a first side portion and a second side portion, among the four sides, that are adjacent to the cutout portion toward a vertex of the cutout portion; the cutout portion is provided such that the distance between the two sides constituting the cutout portion gradually decreases toward the apex of the cutout portion, the semiconductor device placed in the first pocket portion by (c) is in contact with the four side portions, and the corner of the wiring substrate is located within the notch portion; A method for transporting semiconductor devices.

18. 18. The method for transporting a semiconductor device according to claim 17, the semiconductor chip has a main surface, a plurality of electrode pads formed on the main surface, and a back surface opposite to the main surface; the semiconductor chip is mounted on the wiring substrate via a plurality of bump electrodes such that the main surface of the semiconductor chip faces the upper surface of the wiring substrate; a heat sink made of a metal member is fixed to the back surface of the semiconductor chip; A method for transporting semiconductor devices.

19. 18. The method for transporting a semiconductor device according to claim 17, the wiring board is a glass epoxy board, The carrier tape is made of a resin material kneaded with carbon. A method for transporting semiconductor devices.

20. 18. The method for transporting a semiconductor device according to claim 17, the planar shapes of the two sides constituting the cutout portion describe an arc so as not to have any bending points between the first side portion and the second side portion and the vertex of the cutout portion; A method for transporting semiconductor devices.

Images