Optoelectronic integrated circuit

Abstract

To separate a process of forming a layer having electrical wiring and a process of forming a layer having optical wiring.SOLUTION: An optoelectronic integrated circuit 10 includes: a photonic integrated circuit 200 (PIC200); an interposer 300 having an electrical redistribution layer 310 (ERDL310) electrically connected to the PIC200; and a polymer waveguide layer 500 having an optical redistribution layer 510 (ORDL510) optically coupled to the PIC200. The interposer 300 and the polymer waveguide layer 500 are separate bodies.SELECTED DRAWING: Figure 3

Description

[Technical Field]

[0001] The present invention relates to optoelectronic integrated circuits. [Background technology]

[0002] In recent years, in order to reduce transmission loss and achieve high-density packaging, optoelectronic integrated circuits have been developed as an alternative to semiconductor packages. Optoelectronic integrated circuits include photonic integrated circuits (PICs).

[0003] Patent Document 1 describes an optoelectronic integrated circuit. The optoelectronic integrated circuit includes a circuit board, a semiconductor chip embedded in the circuit board, conductive paths electrically connected to the semiconductor chip, and a waveguide optically coupled to the semiconductor chip. The conductive paths and the waveguide extend within an insulating layer that covers the circuit board and the semiconductor chip.

[0004] Patent Document 2 describes an optical semiconductor module. The optical semiconductor module includes an electrical wiring layer, an optical wiring layer formed on the electrical wiring layer, an electrical element formed on the optical wiring layer, and an optical element formed on the optical wiring layer. [Prior art documents] [Patent documents]

[0005] [Patent Document 1] International Publication No. 2018 / 198490 [Patent Document 2] International Publication No. 2022 / 030001 Summary of the Invention [Problem to be solved by the invention]

[0006] In an optoelectronic integrated circuit, the same layer may have both electrical wiring and optical wiring, as described in Patent Document 1, or a layer having electrical wiring and a layer having optical wiring may be stacked on top of each other, as described in Patent Document 2. However, when the same layer has both electrical wiring and optical wiring, or when a layer having electrical wiring and a layer having optical wiring are stacked on top of each other, it may be difficult to separate the process for forming the layer having electrical wiring from the process for forming the layer having optical wiring.

[0007] One object of the present invention is to separate the process of forming a layer having electrical wiring from the process of forming a layer having optical wiring. Other objects of the present invention will become apparent from the description of this specification. [Means for solving the problem]

[0008] One aspect of the present invention is an optoelectronic integrated circuit comprising a photonic element, a first layer having electrical wiring electrically connected to the photonic element, and a second layer having optical wiring optically coupled to the photonic element, wherein the first layer and the second layer are separate entities. [Effects of the Invention]

[0009] According to the above aspect of the present invention, the process of forming the layer having electrical wiring and the process of forming the layer having optical wiring can be separated. [Brief explanation of the drawings]

[0010] [Figure 1] 1 is a plan view of an optoelectronic integrated circuit according to an embodiment; [Figure 2] 2 is an enlarged plan view of an area α surrounded by a dashed line in FIG. 1. FIG. [Figure 3] 3 is a cross-sectional view taken along the line AA in FIG. 2. [Figure 4] FIG. 10 is a cross-sectional view of an opto-electronic integrated circuit according to a first modification. [Figure 5] FIG. 10 is an enlarged plan view of an opto-electronic integrated circuit according to a second modification. [Figure 6]6 is a cross-sectional view of FIG. 5 taken along line B-B. DETAILED DESCRIPTION OF THE INVENTION

[0011] Hereinafter, embodiments and modifications of the present invention will be described with reference to the drawings. In all the drawings, similar components are designated by similar reference numerals, and descriptions thereof will be omitted as appropriate.

[0012] Fig. 1 is a plan view of an opto-electronic integrated circuit 10 according to an embodiment. Fig. 2 is an enlarged plan view of an area α surrounded by a dashed line in Fig. 1. Fig. 3 is a cross-sectional view taken along line AA in Fig. 2.

[0013] For the purpose of explanation, FIGS. 1 to 3 show an X axis, a Y axis, and a Z axis, which respectively indicate the X direction, the Y direction, and the Z direction. The Z direction is a direction parallel to the height of the optoelectronic integrated circuit 10. The X direction is one of the directions perpendicular to the Z direction. The Y direction is a direction perpendicular to both the Z direction and the X direction. In FIGS. 1 and 2, a white circle with a black dot indicating the Z direction indicates that the tip of the arrow indicating the Z direction is pointing towards the paper. In FIG. 3, a white circle with an X indicating the Y direction indicates that the tip of the arrow indicating the Y direction is pointing towards the paper.

[0014] Hereinafter, unless otherwise specified, the +X side refers to the tip side of the arrow indicating the X direction, the -X side refers to the side opposite the tip of the arrow indicating the X direction, the +Y side refers to the tip side of the arrow indicating the Y direction, the -Y side refers to the side opposite the tip of the arrow indicating the Y direction, the +Z side refers to the tip side of the arrow indicating the Z direction, and the -Z side refers to the side opposite the tip of the arrow indicating the Z direction. Hereinafter, unless otherwise specified, the +Z side refers to the upper side in the vertical direction, and the -Z side refers to the lower side in the vertical direction. However, the relationships between the X direction, Y direction, Z direction, and vertical direction are not limited to those described in the embodiment.

[0015] An optoelectronic integrated circuit 10 according to an embodiment will be described with reference to FIG.

[0016] 1, an optoelectronic integrated circuit 10 according to the embodiment includes a substrate 100, an interposer 300, and a plurality of optical connectors 600. For the sake of explanation, a plurality of EICs 400 shown in FIG. 3 have been removed from FIG. 1.

[0017] As shown in FIG. 1, when viewed from the Z direction, the substrate 100 has a substantially rectangular shape having a pair of sides parallel to the X direction and another pair of sides parallel to the Y direction. The shape of the substrate 100 is not limited to the example shown in FIG. 1. As shown in FIG. 1, when viewed from the Z direction, the interposer 300 is located at the center of the substrate 100 in the X and Y directions. As shown in FIG. 1, the interposer 300 has a substantially rectangular shape having a pair of sides parallel to the X direction and another pair of sides parallel to the Y direction. The shape and position of the interposer 300 are not limited to the example shown in FIG. 1. In the example shown in FIG. 1, two optical connectors 600 are arranged on the +X side edge of the substrate 100, and two other optical connectors 600 are arranged on the −X side edge of the substrate 100. The number and arrangement of the optical connectors 600 are not limited to the example shown in FIG. 1.

[0018] 2 and 3, a description will be given of a region α from an optical connector 600 arranged on the +Y side of the +X side edge of the optoelectronic integrated circuit 10 according to the embodiment to the interposer 300. The matters described for the region α with reference to Fig. 2 and 3 can also be applied to other regions from the optical connector 600 to the interposer 300 of the optoelectronic integrated circuit 10 according to the embodiment.

[0019] 2 and 3, in a region α, the optoelectronic integrated circuit 10 according to the embodiment includes a photonic integrated circuit 200 (PIC 200), a plurality of electrical integrated circuits 400 (EICs 400), and a polymer waveguide layer 500. For the sake of explanation, the plurality of EICs 400 shown in FIG. 3 have been removed in FIG. 2.

[0020] The substrate 100 is a packaging substrate such as a glass epoxy substrate, a ceramic substrate, a glass substrate, or a molded substrate. As shown in FIGS. 2 and 3, the substrate 100 is disposed perpendicular to the Z direction. As shown in FIG. 3, a plurality of substrate electrodes 102 are located on the +Z side surface of the substrate 100. In the example shown in FIG. 3, a functional layer 150 covers substantially the entire +Z side surface of the substrate 100, including the PIC 200. The functional layer 150 includes, for example, at least one of a sealing layer and a planarizing layer. The functional layer 150 may not be provided.

[0021] The PIC 200 is a photonic element such as a silicon photonics chip. As shown in FIG. 3 , the PIC 200 is at least partially embedded in a recess 104 formed on the +Z side surface of the substrate 100. This makes it easier to align the +Z side surface of the PIC 200 and the +Z side surface of the substrate 100 in the Z direction, compared to when the PIC 200 is not embedded in the recess 104 and is located on the +Z side of the +Z side surface of the substrate 100. This facilitates electrical input / output (I / O) between an electrical I / O region 200a (described later) and a plurality of EICs 400, and optical input / output (I / O) between an optical I / O region 200b (described later) and an optical connector 600, on the +Z side surface of the PIC 200. The PIC 200 may be located on the +Z side of the +Z side surface of the substrate 100 without being embedded in the recess 104.

[0022] 3, the PIC 200 includes a PIC die 210 and a PIC waveguide layer 220. The PIC 200 may further include optical elements such as a laser diode (LD), a photodiode (PD), an optical modulator, an optical amplifier, and an optical attenuator, which are not shown in FIG. 3, as well as electrical elements such as electrical wiring and a resistance heater made of TiN or the like.

[0023] 2, when viewed from the Z direction, the PIC die 210 has a substantially rectangular shape with a pair of sides parallel to the X direction and another pair of sides parallel to the Y direction. The shape of the PIC die 210 is not limited to the examples shown in FIGS. 2 and 3.

[0024] As shown in FIG. 3 , the PIC waveguide layer 220 is located on the +Z side of the +Z surface of the PIC die 210. The PIC waveguide layer 220 is, for example, a silicon waveguide layer. As shown in FIG. 3 , the PIC waveguide layer 220 includes a PIC core 222, a PIC lower cladding 224, and a PIC upper cladding 226. The PIC core 222 is, for example, silicon, silicon nitride, or silicon oxynitride. The PIC lower cladding 224 and the PIC upper cladding 226 are, for example, silicon oxide. As shown in FIG. 3 , the PIC core 222 extends in the X direction. The PIC lower cladding 224 is disposed perpendicular to the Z direction. The PIC upper cladding 226 is located on the +Z side of the +Z surface of the PIC lower cladding 224. The PIC upper cladding 226 covers the PIC core 222 with the PIC core 222 positioned on the +Z side relative to the +Z side surface of the PIC lower cladding 224 .

[0025] As shown in FIG. 3 , the +Z side surface of the PIC 200 has an electrical I / O region 200a and an optical I / O region 200b. The electrical I / O region 200a has multiple PIC electrodes 202. The multiple PIC electrodes 202 are located on the +Z side of the +Z side surface of the PIC waveguide layer 220. Each PIC electrode 202 serves as an electrical I / O port of the PIC 200. The optical I / O region 200b defines an opening 228 in the PIC waveguide layer 220. A bottom mirror 230 is located inside the opening 228. Light emitted from one end of the +X side of the PIC core 222 can be reflected toward the +Z side by the bottom mirror 230. Therefore, the opening 228 serves as an optical I / O port of the PIC 200. The bottom mirror 230 according to the embodiment is a polymer mirror. For example, the bottom mirror 230 includes a photosensitive resin such as polyimide and a reflective layer such as a metal layer covering the photosensitive resin. The bottom mirror 230 is not limited to a polymer mirror, and may be, for example, a silicon mirror or a metal mirror.

[0026] In this embodiment, the electrical I / O area 200a and the optical I / O area 200b are offset from each other in the X direction. The electrical I / O area 200a has electrical I / O ports such as the PIC electrode 202, but does not have optical I / O ports such as the opening 228. Therefore, the I / O performed by the electrical I / O area 200a is electrical I / O only, and does not include optical I / O. However, the electrical I / O area 200a may have an optical I / O port for testing. The optical I / O port for testing is a port used to test the performance of the PIC 200 alone, and is not optically coupled to the outside of the PIC 200 when the PIC 200 is incorporated into the optoelectronic integrated circuit 10 according to the embodiment. The optical I / O area 200b has optical I / O ports such as the opening 228, but does not have electrical I / O ports such as the PIC electrode 202. Therefore, the I / O performed by the optical I / O area 200b does not include electrical I / O, but is only optical I / O. However, the optical I / O area 200b may have an electrical I / O port for testing. The electrical I / O port for testing is a port used to test the performance of the PIC 200 alone, and is a port that is not electrically connected to anything outside the PIC 200 when the PIC 200 is incorporated into the optoelectronic integrated circuit 10 according to the embodiment.

[0027] The interposer 300 according to the embodiment is an organic interposer. As shown in FIGS. 2 and 3, the interposer 300 is arranged perpendicular to the Z direction. As shown in FIG. 3, the interposer 300 includes an electrical redistribution layer 310 (ERDL 310) and multiple insulating layers 320. The ERDL 310 is made of a metal such as copper. The ERDL 310 is at least partially embedded in the multiple insulating layers 320. In the example shown in FIG. 3, the ERDL 310 includes multiple metal layers 312 perpendicular to the Z direction and multiple metal vias 314 parallel to the Z direction. In one example, the metal layer 312 is a copper layer with a thickness in the Z direction of 10 μm to 20 μm, both inclusive, from the viewpoint of high density and high-speed transmission. Each insulating layer 320 is, for example, a resin layer. Each insulating layer 320 is arranged perpendicular to the Z direction. The multiple insulating layers 320 are stacked in the Z direction.

[0028] In the embodiment, the dimensions of the ERDL 310 can be made relatively large, suitable for high-speed transmission, compared to when the interposer 300 is a silicon interposer. Furthermore, in the embodiment, the interposer 300 can be formed without a core. Furthermore, in the embodiment, the interposer 300 can be made less expensive, compared to when the interposer 300 is a silicon interposer. However, the interposer 300 does not have to be an organic interposer, and may be an inorganic interposer such as a silicon interposer.

[0029] 2 and 3, the interposer 300 is flip-chip mounted on the +Z side surface of the substrate 100 and the +Z side surface of the PIC 200, with a plurality of first bumps 710 located between the +Z side surface of the substrate 100 and the -Z side surface of the interposer 300, and a plurality of second bumps 720 located between the +Z side surface of the PIC 200 and the -Z side surface of the interposer 300. The interposer 300 is mechanically supported by the plurality of first bumps 710 located between the +Z side surface of the substrate 100 and the -Z side surface of the interposer 300. As shown in FIG. 3, the plurality of substrate electrodes 102 and the plurality of first bumps 710 are electrically connected to each other via a plurality of first connection conductors 712 that penetrate the functional layer 150 in the Z direction. When viewed from the Z direction, the multiple first bumps 710 may be regularly arranged in a direction perpendicular to the Z direction, or may be irregularly arranged in a direction perpendicular to the Z direction. As shown in Fig. 3, the multiple PIC electrodes 202 and the multiple second bumps 720 are electrically connected to each other via multiple second connection conductors 722 that penetrate the functional layer 150 in the Z direction. When viewed from the Z direction, the multiple second bumps 720 may be regularly arranged in a direction perpendicular to the Z direction, or may be irregularly arranged in a direction perpendicular to the Z direction.

[0030] Each of the first bumps 710 and each of the second bumps 720 according to the embodiment is a copper bump. Each of the first bumps 710 and each of the second bumps 720 may be a different material from a copper bump, for example, a solder ball. The diameter of each of the first bumps 710 is determined based on the distance between the +Z side surface of the substrate 100 and the -Z side surface of the interposer 300, and is, for example, 10 μm to 1,000 μm. The diameter of each of the second bumps 720 is determined based on the distance between the +Z side surface of the PIC 200 and the -Z side surface of the interposer 300, and is, for example, 10 μm to 1,000 μm. The diameter of each of the second bumps 720 may be smaller than the diameter of each of the first bumps 710.

[0031] Each EIC 400 functions as, for example, at least one of a signal processing circuit, a power supply circuit, a control circuit, and a drive circuit. The signal processing circuit includes, for example, a processor, a memory, a SerDes (serializer / deserializer), and a compensation circuit (e.g., a digital signal processor (DSP), an analog equalizer). The power supply circuit includes, for example, at least one of a low dropout (LDO), a DC / DC converter, a capacitor, and an LC filter. The control circuit includes, for example, at least one of a microcontroller, an AD / DA converter, a programmable LDO, and a temperature sensor. The drive circuit includes, for example, at least one of a driver integrated circuit (IC) for a PIC200, a transimpedance amplifier (TIA), and a high-frequency transmission line. As shown in FIG. 3, each EIC 400 is arranged vertically in the Z direction. Each EIC 400 is flip-chip mounted on the +Z side surface of the interposer 300, with multiple third bumps 730 located between the +Z side surface of the interposer 300 and the -Z side surface of each EIC 400. Multiple EIC electrodes 402 are located on the -Z side surface of each EIC 400. Each EIC electrode 402 and each third bump 730 are electrically connected to each other.

[0032] The EIC 400 functioning as a power supply circuit, the EIC 400 functioning as a control circuit, and the EIC 400 functioning as a drive circuit may be mounted on the +Z side of the substrate 100 instead of the +Z side of the interposer 300. For example, the EIC 400 functioning as a power supply circuit may be mounted on the substrate 100, and the EIC 400 functioning as a control circuit and the EIC 400 functioning as a drive circuit may be mounted on the interposer 300. Alternatively, the EIC 400 functioning as a power supply circuit and the EIC 400 functioning as a control circuit may be mounted on the substrate 100, and the EIC 400 functioning as a drive circuit may be mounted on the interposer 300. Alternatively, all of the EIC 400 functioning as a power supply circuit, the EIC 400 functioning as a control circuit, and the EIC 400 functioning as a drive circuit may be mounted on the interposer 300. Alternatively, the EIC 400 functioning as a control circuit may be mounted on the substrate 100, and the EIC 400 functioning as a power supply circuit and the EIC 400 functioning as a drive circuit may be mounted on the interposer 300. When the EIC 400 that functions as a power supply circuit, a control circuit, or a drive circuit is mounted on the substrate 100, the substrate 100 and the EIC 400 are electrically connected to each other via conductors such as bumps.

[0033] When an EIC 400 functioning as a power supply circuit is mounted on the substrate 100 and an EIC 400 functioning as a driver circuit is mounted on the interposer 300, the thickness of the wiring electrically connected to the EIC 400 on the substrate 100 can be made to a thickness suitable for the power supply circuit, and the thickness of the wiring, such as the ERDL 310, electrically connected to the EIC 400 on the interposer 300 can be made to a thickness suitable for the driver circuit. That is, the thickness of the wiring on the interposer 300 is desirably relatively thin from the viewpoint of high density and high-speed transmission. In contrast, the thickness of the wiring electrically connected to the power supply circuit, through which a large current flows, is desirably relatively thick from the viewpoint of increasing current capacity and reducing power supply noise by reducing impedance. When an EIC 400 functioning as a power supply circuit is mounted on the substrate 100 and an EIC 400 functioning as a driver circuit is mounted on the interposer 300, the wiring electrically connected to the power supply circuit and the wiring electrically connected to the driver circuit can be provided separately on the substrate 100 and the interposer 300, respectively, and the wiring on the substrate 100 can be made relatively thick and the wiring on the interposer 300 can be made relatively thin. Therefore, it is possible to achieve both high density and high speed transmission in the interposer 300 and an increase in current capacity and a reduction in power supply noise in the power supply circuit.

[0034] The plurality of substrate electrodes 102 and some of the EIC electrodes 402 are electrically connected to one another via the plurality of first bumps 710, some of the ERDLs 310, and some of the third bumps 730. Therefore, the some of the ERDLs 310 serve as electrical wiring electrically connected to the substrate 100 and at least some of the EICs 400. Electrical signals, such as signals for a power supply circuit and signals for a control circuit, and power can be transmitted between the plurality of substrate electrodes 102 and some of the EIC electrodes 402 via the some of the ERDLs 310.

[0035] The plurality of PIC electrodes 202 and some of the other EIC electrodes 402 are electrically connected to one another via the plurality of second bumps 720, some of the other ERDLs 310, and some of the other third bumps 730. Therefore, the other ERDLs 310 form electrical wiring electrically connected to the PIC 200 and at least some of the EICs 400. Electrical signals such as high-speed signals can be transmitted between the plurality of PIC electrodes 202 and some of the other EIC electrodes 402 via the other ERDLs 310.

[0036] As shown in FIG. 3 , the interposer 300 is a layer at least partially located between the assembly including the substrate 100 and the PIC 200 and the plurality of EICs 400. Therefore, the interposer 300 can function as a buffer layer to buffer the coefficient of thermal expansion (CTE) mismatch between the assembly including the substrate 100 and the PIC 200 and the plurality of EICs 400. Furthermore, during operation of the optoelectronic integrated circuit 10, each EIC 400 may become the hottest in the optoelectronic integrated circuit 10. In an embodiment, by providing an insulating layer with relatively low thermal conductivity, such as a resin layer, as at least a portion of the insulating layer 320, the interposer 300 can suppress thermal crosstalk from the plurality of EICs 400 to the substrate 100 and the PIC 200. Therefore, in an embodiment, the substrate 100 and the EICs 400 can be electrically connected to each other using bumps including the first bump 710, the second bump 720, and the third bump 730, and the PIC 200 and the EICs 400 can be electrically connected to each other.

[0037] 2 and 3, the polymer waveguide layer 500 is disposed perpendicular to the Z direction. As shown in Fig. 2, when viewed from the Z direction, the polymer waveguide layer 500 has a substantially rectangular shape having a pair of sides parallel to the X direction and another pair of sides parallel to the Y direction. The shape of the polymer waveguide layer 500 is not limited to the example shown in Figs. 2 and 3.

[0038] As shown in FIGS. 2 and 3, the polymer waveguide layer 500 includes a plurality of optical redistribution layers 510 (ORDLs 510), a polymer lower cladding 520, and a polymer upper cladding 530.

[0039] Each ORDL 510, the polymer lower cladding 520, and the polymer upper cladding 530 are made of, for example, a polymer. As shown in FIGS. 2 and 3 , when viewed from the Z direction, the multiple ORDLs 510 are aligned in the Y direction with each ORDL 510 extending in the X direction. The layout of the multiple ORDLs 510 is not limited to the example shown in FIG. 2 . The polymer lower cladding 520 is a layer perpendicular to the Z direction. As shown in FIG. 3 , an anti-reflection film 550 (AR coating 550) is at least partially located between the +Z side surface of the functional layer 150 and the −Z side surface of the polymer lower cladding 520. The polymer upper cladding 530 is located on the +Z side of the +Z side surface of the polymer lower cladding 520. Polymer upper cladding 530 covers the ORDLs 510 with the ORDLs 510 positioned on the +Z side relative to the +Z side surface of polymer lower cladding 520 .

[0040] As shown in FIG. 3 , a top mirror 540 is located on the +Z side of the bottom mirror 230. The top mirror 540 according to the embodiment is, for example, a metal mirror. The −X side end of the ORDL 510 is located on the +X side of the top mirror 540. Therefore, light emitted from the +X side end of the PIC core 222 can be reflected by the bottom mirror 230 toward the top mirror 540, and can be reflected by the top mirror 540 toward the −X side end of the ORDL 510. The optical structure that propagates light emitted from the +X side end of the PIC core 222 toward the −X side end of the ORDL 510 is not limited to the bottom mirror 230 and the top mirror 540, but may be, for example, a grating coupler or adiabatic coupling. The optoelectronic integrated circuit 10 may include a silicon waveguide layer, a silicon oxide film waveguide, or a silicon nitride film waveguide instead of the polymer waveguide layer 500.

[0041] The optical connector 600 is provided at the end of the polymer waveguide layer 500 on the +X side. The optical connector 600 mechanically guides an external optical fiber (not shown) to optically couple the other end of the +X side of each ORDL 510 to an external optical fiber (not shown). Therefore, with the optical connector 600 mechanically guiding the external optical fiber, each ORDL 510 forms an optical wiring optically coupled to the PIC 200 and the external optical fiber.

[0042] In an embodiment, as shown in FIG. 3 , the Z-direction thickness of the polymer waveguide layer 500 is less than the Z-direction thickness of the PIC 200. Taking into consideration the impedance matching and transmission loss of the PIC 200 and each EIC 400, the Z-direction thickness of the interposer 300 is, for example, 50 μm or more and 500 μm or less. Taking into consideration the dissipation of heat generated from the PIC 200, the Z-direction thickness of the polymer waveguide layer 500 is, for example, 30 μm or more and 100 μm or less. The Z-direction thickness of the polymer waveguide layer 500 may be equal to or greater than the Z-direction thickness of the PIC 200.

[0043] In this embodiment, the interposer 300 and the polymer waveguide layer 500 are separate bodies. As shown in FIGS. 2 and 3 , the electrical I / O region 200a and the optical I / O region 200b of the PIC 200 are offset from each other in the X direction, and the +X side end of the interposer 300 and the electrical I / O region 200a of the PIC 200 overlap each other in the Z direction, while the −X side end of the polymer waveguide layer 500 and the optical I / O region 200b of the PIC 200 overlap each other in the Z direction. Therefore, when viewed from the Z direction, the interposer 300 and the polymer waveguide layer 500 are offset from each other. Heat generated from the PIC 200 may be difficult to dissipate from the portion where the interposer 300 and the polymer waveguide layer 500 overlap each other in the Z direction. However, in the embodiment, the overlapping portion between the interposer 300 and the polymer waveguide layer 500 in the Z direction can be eliminated, and the heat generated from the PIC 200 can be easily dissipated toward the +Z side.

[0044] 2, when viewed in the Z direction, the +X side edge of the interposer 300 and the −X side edge of the polymer waveguide layer 500 are spaced apart in the X direction by a distance. This distance may be, for example, 750 μm or more from the viewpoint of heat dissipation of the PIC 200. This distance may be, for example, 1,250 μm or less from the viewpoint of high-density mounting of the optoelectronic integrated circuit 10. The region between the +X side edge of the interposer 300 and the −X side edge of the polymer waveguide layer 500 may be hollow or may be filled with a material such as resin.

[0045] In the embodiment, the ERDL 310 is embedded in a layer including a plurality of insulating layers 320, and the ORDL 510 is embedded in a layer including a polymer lower cladding 520 and a polymer upper cladding 530. This allows for higher density packaging of the optoelectronic integrated circuit 10 than when a discrete electrical connecting member such as a wire harness is used instead of the interposer 300. Similarly, it allows for higher density packaging of the optoelectronic integrated circuit 10 than when a discrete optical coupling member such as an optical fiber cable is used instead of the polymer waveguide layer 500.

[0046] Next, an example of a method for manufacturing the optoelectronic integrated circuit 10 according to the embodiment will be described with reference to FIGS.

[0047] First, the substrate 100 and the PIC 200 are prepared. The PIC 200 has a PIC die 210 and a PIC waveguide layer 220. A bottom mirror 230 is disposed inside an opening 228 of the PIC waveguide layer 220. The PIC 200 is embedded in a recess 104 on the +Z side surface of the substrate 100. Substantially the entire +Z side surface of the substrate 100, including the PIC 200, is covered with a functional layer 150.

[0048] Next, a polymer waveguide layer 500 is formed on the +Z side of the +Z surface of the substrate 100. In forming the polymer waveguide layer 500, an AR coating 550 is first formed on the +Z surface of the functional layer 150 where the polymer waveguide layer 500 is to be formed. The AR coating 550 may be formed on the entire +Z surface of the functional layer 150. Next, a polymer lower cladding 520 is formed on the +Z side of the +Z surface of the AR coating 550. Next, multiple ORDLs 510 are formed on the +Z side of the +Z surface of the polymer lower cladding 520. The multiple ORDLs 510 are formed by a method such as direct laser writing or lithography using a mask. In this method, light such as ultraviolet (UV) light is irradiated onto the +Z surface of the substrate 100 from the +Z side. The AR coating 550 is at least partially located on the -Z side of the polymer lower cladding 520. Therefore, in the embodiment, reflection of light used to form the multiple ORDLs 510 on the +Z side surface of the substrate 100 can be suppressed. This can improve the uniformity of each ORDL 510 and suppress defects in each ORDL 510. After each ORDL 510 is formed, the ORDLs 510 and the AR coating 550 at least partially overlap in the Z direction. Next, a +Z side polymer upper cladding 530 is formed on the +Z side surface of the polymer lower cladding 520. Next, a top mirror 540 is formed on the -X side of one end of each ORDL 510 on the -X side.

[0049] Next, an optical connector 600 is provided at the end of the polymer waveguide layer 500 on the +X side.

[0050] Next, the interposer 300 is prepared. Next, the interposer 300 is flip-chip mounted on the +Z side surface of the substrate 100 and the +Z side surface of the PIC 200, with the plurality of first bumps 710 positioned between the +Z side surface of the substrate 100 and the -Z side surface of the interposer 300, and the plurality of second bumps 720 positioned between the +Z side surface of the PIC 200 and the -Z side surface of the interposer 300. With the interposer 300 flip-chip mounted on the +Z side surface of the substrate 100 and the +Z side surface of the PIC 200, the plurality of substrate electrodes 102 and the plurality of first bumps 710 are electrically connected to each other via the plurality of first connecting conductors 712, and the plurality of PIC electrodes 202 and the plurality of second bumps 720 are electrically connected to each other via the plurality of second connecting conductors 722.

[0051] In the embodiment, the interposer 300 and the polymer waveguide layer 500 are separate bodies. Therefore, the process for forming the layer including the ERDL 310 can be separated from the process for forming the layer including the ORDL 510. Specifically, the interposer 300 already includes the ERDL 310 and the multiple insulating layers 320 before the interposer 300 is flip-chip mounted on the +Z side of the substrate 100. This prevents metal and organic contamination of the polymer waveguide layer 500 during the process for forming the ERDL 310. Therefore, compared to when metal and organic contamination occurs, the location on the polymer waveguide layer 500 where the optical connector 600 is to be provided can be kept clean. Furthermore, in the embodiment, compared to when the ERDL 310 and the ORDL 510 are included in the same layer, considerations regarding the matching of the materials of the layer including the ERDL 310 and the layer including the ORDL 510, and the matching of the process for forming the ERDL 310 and the process for forming the ORDL 510, can be reduced. Furthermore, in the embodiment, compared to when a layer having ERDL310 and a layer having ORDL510 are stacked on top of each other in the Z direction, consideration of issues such as stress, adhesion, and reliability that accompany increasing the number of layers can be reduced. Therefore, in the embodiment, compared to when the same layer has ERDL310 and ORDL510, or when a layer having ERDL310 and a layer having ORDL510 are stacked on top of each other in the Z direction, the manufacturing process for the optoelectronic integrated circuit 10 can be made easier and simpler, and the productivity and yield of the optoelectronic integrated circuit 10 can be improved.

[0052] Next, a plurality of EICs 400 are prepared. Next, the plurality of EICs 400 are flip-chip mounted on the +Z side surface of the interposer 300, with a plurality of third bumps 730 positioned between the +Z side surface of the interposer 300 and the −Z side surface of each EIC 400. With the plurality of EICs 400 flip-chip mounted on the +Z side surface of the interposer 300, the plurality of EIC electrodes 402 and the plurality of third bumps 730 are electrically connected to each other.

[0053] In this manner, the optoelectronic integrated circuit 10 according to the embodiment is manufactured.

[0054] 4 is a cross-sectional view of an opto-electronic integrated circuit 10A according to Modification 1. The opto-electronic integrated circuit 10A according to Modification 1 is similar to the opto-electronic integrated circuit 10 according to the embodiment, except for the following points.

[0055] As shown in Fig. 4, the polymer lower cladding 520A and the polymer upper cladding 530A of the polymer waveguide layer 500A according to the first modification are located on the +Z side with respect to substantially the entire +Z side surface of the substrate 100. Therefore, as shown in Fig. 4, in the first modification, the interposer 300 and the polymer waveguide layer 500A at least partially overlap in the Z direction. As shown in Fig. 4, the ORDL 510A of the polymer waveguide layer 500A according to the first modification is located on the +X side with respect to the portion of the polymer lower cladding 520A and the polymer upper cladding 530A that overlaps with the interposer 300 in the Z direction. As in the embodiment, an AR coating may be provided on the portion of the +Z side surface of the functional layer 150 that overlaps with the ORDL 510A in the Z direction. As shown in Fig. 4, the substrate electrodes 102 and the first bumps 710 are electrically connected to each other via first connecting conductors 712A that penetrate the functional layer 150, the polymer lower cladding 520A, and the polymer upper cladding 530A in the Z direction. As shown in Fig. 4, the PIC electrodes 202 and the second bumps 720 are electrically connected to each other via second connecting conductors 722A that penetrate the functional layer 150, the polymer lower cladding 520A, and the polymer upper cladding 530A in the Z direction.

[0056] In the first modification, the interposer 300 and the polymer waveguide layer 500A are also separate bodies. Therefore, similar to the embodiment, the process for forming the layer having the ERDL 310 and the process for forming the layer having the ORDL 510A can be separated.

[0057] 4, the -Z side surface of the interposer 300 and the +Z side surface of the polymer waveguide layer 500A are spaced apart in the Z direction. This distance may be, for example, 75 μm or more from the perspective of heat dissipation of the PIC 200. This distance may be, for example, 125 μm or less from the perspective of high-density packaging of the optoelectronic integrated circuit 10. The region between the -Z side surface of the interposer 300 and the +Z side surface of the polymer waveguide layer 500A may be hollow or filled with a material such as resin.

[0058] Fig. 5 is an enlarged plan view of an optoelectronic integrated circuit 10B according to Modification 2. Fig. 6 is a cross-sectional view taken along line BB in Fig. 5. The optoelectronic integrated circuit 10B according to Modification 2 is similar to the optoelectronic integrated circuit 10 according to the embodiment, except for the following points. For the sake of explanation, Fig. 6 also shows a polymer waveguide layer 500 located on the +Y side with respect to line BB in Fig. 5.

[0059] 5 and 6, the +X side ends of the multiple insulating layers 320B of the interposer 300B according to the second modification protrude toward the +X side further than the +X side ends of the multiple insulating layers 320 of the interposer 300 according to the embodiment. As shown in Fig. 6, in the second modification, the +X side ends of the multiple interposers 300B are located on the +Z side of approximately half of the polymer waveguide layer 500 on the -X side. Therefore, in the second modification, the interposer 300B and the polymer waveguide layer 500 at least partially overlap in the Z direction.

[0060] As shown in FIG. 6, the +X side end of the substrate 100B according to the second modification has a substrate shunt 110B. The substrate shunt 110B is made of a material having a relatively high thermal conductivity, such as a metal. In the example shown in FIG. 6, the substrate shunt 110B includes a plurality of substrate shunt metal layers 112B perpendicular to the Z direction and a plurality of substrate shunt metal vias 114B parallel to the Z direction. As shown in FIG. 6, the +X side end of the interposer 300B according to the second modification has an interposer shunt 310B. The interposer shunt 310B is made of a material having a relatively high thermal conductivity, such as a metal. In the example shown in FIG. 6, the interposer shunt 310B includes a plurality of interposer shunt metal layers 312B perpendicular to the Z direction and a plurality of interposer shunt metal vias 314B parallel to the Z direction. As shown in FIGS. 5 and 6, additional first bumps 710B are located around the polymer waveguide layer 500 between the +Z-side surface of the +X-side end of the substrate 100B and the -Z-side surface of the +X-side end of the interposer 300B. Around the polymer waveguide layer 500, the +X-side end of the interposer 300B is mechanically supported by the additional first bumps 710B, with the additional first bumps 710B located between the +Z-side surface of the +X-side end of the substrate 100B and the -Z-side surface of the +X-side end of the interposer 300B. As shown in FIG. 6, a heat dissipation plate 400B is mounted on the +Z-side surface of the +X-side end of the interposer 300B according to the second modification. The heat dissipation plate 400B is, for example, a metal plate such as an aluminum plate.

[0061] In the example shown in Figure 6, the -Z side surface of the PIC 200 and one end of the substrate shunt 110B are thermally coupled to each other. One end of the interposer shunt 310B and the heat dissipation plate 400B are thermally coupled to each other. The other end of the substrate shunt 110B and the other end of the interposer shunt 310B are thermally coupled to each other via the additional first bumps 710B. Therefore, in the example shown in Figure 6, the substrate shunt 110B, the additional first bumps 710B, the interposer shunt 310B, and the heat dissipation plate 400B can form a heat dissipation path for dissipating heat generated from the PIC 200.

[0062] The structure of the heat dissipation path for dissipating heat generated from the PIC 200 is not limited to the example shown in FIG. 6 . For example, the PIC 200 and the heat dissipation plate 400B may be thermally coupled to each other via the substrate shunt 110B when the heat dissipation plate 400B is mounted on the +Z side surface of the substrate 100B. That is, the interposer 300B may not have a heat dissipation path, but the substrate 100B may have a heat dissipation path. Alternatively, the PIC 200 and the heat dissipation plate 400B may be thermally coupled to each other via the second bump 720 and the ERDL 310 when the heat dissipation plate 400B is mounted on the +Z side surface of the interposer 300B. That is, the substrate 100B may not have a heat dissipation path, but the interposer 300B may have a heat dissipation path. Alternatively, at least a portion of the heat dissipation path may be provided in the polymer waveguide layer 500.

[0063] The additional first bump 710B according to the second modification is a copper bump. The additional first bump 710B may be a different material from a copper bump, for example, a solder ball. The diameter of the additional first bump 710B may be greater than the thickness of the polymer waveguide layer 500 in the Z direction. The diameter of the additional first bump 710B is, for example, 50 μm or more and 500 μm or less. When the diameter of the additional first bump 710B is greater than the thickness of the polymer waveguide layer 500 in the Z direction, the −Z side surface of the +X side end of the interposer 300B and the +Z side surface of approximately half of the −X side of the polymer waveguide layer 500 can be spaced apart from each other by a distance in the Z direction. This distance may be, for example, 75 μm or more from the viewpoint of heat dissipation of the PIC 200. This distance may be, for example, 125 μm or less from the viewpoint of high-density packaging of the optoelectronic integrated circuit 10. The area between the -Z side surface of the +X side end of interposer 300B and the +Z side surface of approximately half of the -X side of polymer waveguide layer 500 may be hollow or may be filled with a material such as resin.

[0064] In the second modification, the interposer 300B and the polymer waveguide layer 500 are also separate bodies. Therefore, similar to the embodiment, the process for forming the layer having the ERDL 310 and the process for forming the layer having the ORDL 510 can be separated.

[0065] Although the embodiments and modifications of the present invention have been described above with reference to the drawings, these are merely examples of the present invention, and various other configurations can also be adopted.

[0066] For example, in the embodiment and modified examples, the interposer is a layer having an ERDL, but the layer having an ERDL may be a layer different from the interposer as long as the process for forming the layer having an ERDL and the process for forming the layer having an ORDL can be separated.

[0067] According to the present specification, the following aspects are provided. 1. A photonic device; a first layer having electrical wiring electrically connected to the photonic element; a second layer having optical wiring optically coupled to the photonic element; Equipped with The optoelectronic integrated circuit, wherein the first layer and the second layer are separate entities. 2. The optoelectronic integrated circuit described in 1., wherein the portion of the photonic element that overlaps with the first layer and the portion of the photonic element that overlaps with the second layer are positioned offset from each other. 3. The optoelectronic integrated circuit of claim 1, wherein the first layer and the second layer at least partially overlap each other. 4. The optoelectronic integrated circuit according to any one of 1. to 3., wherein the first layer has an interposer. 5. The optoelectronic integrated circuit according to claim 4, wherein the interposer is an organic interposer. 6. The optoelectronic integrated circuit according to any one of 1. to 5., further comprising an anti-reflection film at least partially overlapping the optical wiring. 7. The optoelectronic integrated circuit according to any one of 1. to 6., wherein the thickness of the first layer is 50 μm or more and 500 μm or less. 8. The optoelectronic integrated circuit according to any one of 1. to 7., wherein the thickness of the second layer is less than the thickness of the first layer. 9. The optoelectronic integrated circuit according to any one of 1. to 8., wherein the photonic element and the first layer do not at least partially overlap each other. 10. An optoelectronic integrated circuit according to any one of 1. to 9., wherein at least one of the first layer and the second layer has a heat dissipation path thermally coupled to the photonic element. [Explanation of symbols]

[0068] 10,10A,10B Optoelectronic integrated circuit, 100,100B Substrate, 102 Substrate electrode, 104 Recess, 110B Substrate shunt, 112B Substrate shunt metal layer, 114B Substrate shunt metal via, 150 Functional layer, 200 PIC, 202 PIC electrode, 210 PIC die, 220 PIC waveguide layer, 222 PIC core, 224 PIC lower cladding, 226 PIC upper cladding, 228 Aperture, 230 Bottom mirror, 300,300B Interposer, 310 ERDL, 310B Interposer shunt, 312 Metal layer, 312B Interposer shunt metal layer, 314 Metal via, 314B Interposer shunt metal via 320,320B Insulating layer, 400 EIC, 400B Heat dissipation plate, 402 EIC electrode, 500, 500A Polymer waveguide layer, 510, 510A ORDL, 520, 520A Polymer lower cladding, 530, 530A Polymer upper cladding, 540 Top mirror, 550 AR coating, 600 Optical connector, 710 First bump, 710B Additional first bump, 712, 712A First connecting conductor, 720 Second bump, 722, 722A Second connecting conductor, 730 Third bump

Claims

1. a photonic element; a first layer having electrical wiring electrically connected to the photonic element; a second layer having optical wiring optically coupled to the photonic element; Equipped with The optoelectronic integrated circuit, wherein the first layer and the second layer are separate entities.

2. The optoelectronic integrated circuit of claim 1 , wherein a portion of said photonic element overlapping said first layer and a portion of said photonic element overlapping said second layer are offset from each other.

3. The optoelectronic integrated circuit of claim 1 , wherein the first layer and the second layer at least partially overlap one another.

4. The optoelectronic integrated circuit of any one of claims 1 to 3, wherein the first layer comprises an interposer.

5. The optoelectronic integrated circuit of claim 4 , wherein the interposer is an organic interposer.

6. 4. The optoelectronic integrated circuit according to claim 1, further comprising an anti-reflection film at least partially overlapping said optical wiring.

7. 4. The optoelectronic integrated circuit according to claim 1, wherein the first layer has a thickness of 50 μm or more and 500 μm or less.

8. The optoelectronic integrated circuit according to any one of claims 1 to 3, wherein the thickness of the second layer is less than the thickness of the first layer.

9. The optoelectronic integrated circuit of any one of claims 1 to 3, wherein the photonic element and the first layer are at least partially non-overlapping with each other.

10. The optoelectronic integrated circuit of any one of claims 1 to 3, wherein at least one of the first layer and the second layer has a heat dissipation path thermally coupled to the photonic element.

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