Semiconductor circuit structure

Abstract

To suppress generation of a large electric capacity, large influence on AC performance of a circuit, consumption of more power, and increase in noise.SOLUTION: A semiconducting circuit structure 20 includes: a set of transistors 20A formed based on a semiconducting substrate; a first STI region 214-1 adjacent to the set of transistors 20A and extending along a first direction X; a large STI region 224-1 away from the set of transistors 20A; a first underground interconnect line 205 in the first STI region 214-1 and located below a semiconducting surface; and a first underground interconnect pad 209 electrically coupled to the first underground interconnect line 205. Each transistor 20A includes a gate structure, a first conductive region, and a second conductive region. The first underground interconnect line 205 extends along the first direction X. A width of the first underground interconnect pad 209 is greater than that of the first underground wiring line 205.SELECTED DRAWING: Figure 2D

Description

Detailed Description of the Invention

[0001] [Technical Field] FIELD OF THE DISCLOSURE This disclosure relates to semiconductor structures, and more particularly to semiconductor circuit structures. Description of Related Art

[0002] State-of-the-art integrated circuits feature numerous transistors connected by conductive interconnects, such as metal or polysilicon wires, to facilitate signal transmission between the gate, source, and drain regions (GSDs) of these transistors. These conductive interconnects connect the transistors' gate, source, and drain regions through numerous contact holes or connection plugs, posing significant challenges and difficulties to chip design goals such as reducing area, power consumption, noise, and integrated circuit performance. To cite an example of an area penalty, the dimensions of the source or drain diffusion region must be designed to be larger than the dimensions of the contact hole used to connect the conductive interconnect to the source or drain region. This is to avoid unavoidable photolithography misalignment resulting from limitations in lithography equipment. This results in the contact hole being formed outside the bottom edge of the source or drain region. This inevitably increases the transistor's diffusion area and, therefore, the die area. This results in a large capacitance, which significantly impacts the circuit's AC performance, consumes more power, and increases noise.

[0003] Therefore, how to introduce better self-aligned contact structures and techniques to connect transistors to the first interconnect (metal) layer in a smaller surface area for transmitting and receiving signals is a key challenge for effectively shrinking integrated circuits and improving their performance.

[0004] Furthermore, as monolithic integration capabilities on silicon chips evolve from gigascale integration (GSI)—integrating billions of transistors on a die—to terascale integration (TSI)—operating such a large number of transistors results in a sharp increase in power consumption. The increased power consumption, in turn, increases transistor junction temperatures and, ultimately, the temperature of the entire chip due to current-limited heat dissipation. Silicon dioxide has very low thermal conductivity, while silicon itself has a relatively low thermal conductivity. This material and device structure creates a negative circular effect: higher die temperatures slow down transistor speeds, forcing designs to increase circuit power to boost transistor performance. However, this mechanism significantly increases die temperatures, exacerbating the heat dissipation problem. This lack of heat dissipation, which causes rising chip operating temperatures, is a critical issue the entire chip industry must address to avoid a major obstacle to integrating more devices on a die. However, progress in reducing GSI chip temperatures has not yet improved. In fact, as technology nodes continue to shrink, transistor dimensions are forced to become smaller (e.g., minimum feature size shrinks from 7 nm to 5 nm and then to 3 nm), the oxide layer coverage relative to the total transistor size becomes higher, and the heat dissipation capability of the entire device junction becomes more concentrated. Many heat dissipation methods have been developed, such as covering the entire chip with high-heat removal pads outside the chip or circulating liquid cooling outside the packaged chip, but both are very expensive and less efficient in effectively reducing the transistor junction temperature. 〔overview〕

[0005] An embodiment of the present disclosure provides a semiconductor circuit structure. The semiconductor circuit structure includes a semiconductor substrate having an initial semiconductor surface, a set of transistors formed based on the semiconductor substrate, a first shallow trench isolation (STI) region adjacent to the set of transistors and extending along a first direction, a large shallow trench isolation (STI) region spaced apart from the set of transistors, a first underground interconnect line located within the first STI region and below the initial semiconductor surface, and a first underground interconnect pad electrically coupled to the first underground interconnect line. Each transistor includes a gate structure, a first conductive region, and a second conductive region. The first underground interconnect line extends along the first direction. The first underground interconnect pad is located within the large STI region and below the initial semiconductor surface. The width of the first underground interconnect pad is greater than the width of the first underground interconnect line.

[0006] According to one aspect of the present disclosure, the first underground interconnect pad is directly connected to the first underground interconnect line.

[0007] According to one aspect of the present disclosure, the semiconductor circuit structure further includes a through-semiconductor via (TSV) extending from a lower surface of the first underground interconnect pad to a back surface of the semiconductor substrate, the TSV being electrically connected to the first underground interconnect pad and configured to transmit power or data signals from the back surface of the semiconductor substrate to the first underground interconnect pad, the back surface facing the initial semiconductor surface.

[0008] According to one aspect of the present disclosure, the first conductive region of a first transistor of the set of transistors is electrically connected to the first underground interconnect line via a connection plug located within an active area accommodating the first transistor, and the power signal or the data signal is transmitted to the first transistor via the first underground interconnect pad, the first underground interconnect line, and the corresponding connection plug.

[0009] According to one aspect of the present disclosure, the connection plug contacts a sidewall of the first underground interconnection line.

[0010] According to one aspect of the present disclosure, both the first underground interconnect pad and the first underground interconnect line include W and TiN.

[0011] According to one embodiment of the present disclosure, the TSV includes a Cu pillar.

[0012] According to one aspect of the present disclosure, the semiconductor circuit structure further includes a conductive pad adjacent to a back surface of the semiconductor substrate and connected to the TSV.

[0013] According to one aspect of the present disclosure, the semiconductor circuit structure further includes a second shallow trench isolation (STI) region separate from the set of transistors, and a second underground interconnect line within the second STI region and located below the initial semiconductor surface, the second underground interconnect line extending along a second direction different from the first direction, the second underground interconnect line being connected to the first underground interconnect line.

[0014] According to one aspect of the present disclosure, the semiconductor circuit structure further includes a second shallow trench isolation (STI) region separate from the set of transistors, and a second underground interconnect line within the second STI region and located below the initial semiconductor surface, the second underground interconnect line extending along a second direction different from the first direction, the second underground interconnect line being connected to the first underground interconnect pad.

[0015] According to one aspect of the present disclosure, the semiconductor circuit structure further includes a plurality of metal layers positioned above the initial semiconductor surface and spaced apart vertically from one another, and a plurality of connection vias above the initial semiconductor surface and electrically connected to the plurality of metal layers, wherein the first conductive region of a first transistor of the set of transistors is electrically connected to the first underground interconnect pad through the plurality of metal layers and the plurality of connection vias.

[0016] According to one aspect of the present disclosure, the semiconductor circuit structure further includes a plurality of metal layers positioned above the initial semiconductor surface and spaced apart vertically from each other, a plurality of connection vias positioned above the initial semiconductor surface and electrically connected to the plurality of metal layers, and a second underground interconnect pad positioned below the initial semiconductor surface, wherein the width of the second underground interconnect pad is greater than the width of the first underground interconnect line, and the first underground interconnect pad is electrically connected to the second underground interconnect pad through the plurality of metal layers and the plurality of connection vias.

[0017] Another embodiment of the present disclosure provides a semiconductor circuit structure including: a semiconductor substrate having an initial semiconductor surface; a set of transistors formed on the semiconductor substrate; a first shallow trench isolation (STI) region adjacent to the set of transistors and extending along a first direction; a second shallow trench isolation (STI) region remote from the set of transistors; a large shallow trench isolation (STI) region remote from the set of transistors; a first underground interconnect line within the first STI region and below the initial semiconductor surface; a second underground interconnect line within the second STI region and below the initial semiconductor surface; and a first underground interconnect pad within the large STI region and below the initial semiconductor surface. The first underground interconnect line extends along the first direction; and the second underground interconnect line extends along a second direction different from the first direction. The second underground interconnect line is connected to the first underground interconnect line or the first underground interconnect pad.

[0018] According to one aspect of the present disclosure, a width of the first underground interconnect pad is greater than a width of the first underground interconnect line.

[0019] According to one aspect of the present disclosure, the first underground interconnect pad is connected to the first underground interconnect line.

[0020] According to one aspect of the present disclosure, the semiconductor circuit structure further includes a third shallow trench isolation (STI) region separate from the set of transistors, and a third underground interconnect line within the third STI region and located below the initial semiconductor surface, the third underground interconnect line extending along the first direction, and the second underground interconnect line being between the first underground interconnect line and the third underground interconnect line and connected to the first underground interconnect line and the third underground interconnect line.

[0021] Another embodiment of the present disclosure provides a semiconductor circuit structure. The semiconductor circuit structure includes a semiconductor substrate having an initial semiconductor surface, a set of transistors formed based on the semiconductor substrate, a first shallow trench isolation (STI) region adjacent to the set of transistors and extending along a first direction, a large shallow trench isolation (STI) region remote from the set of transistors, a first underground interconnect line within the first STI region and located below the initial semiconductor surface, a first underground interconnect pad electrically coupled to the first underground interconnect line, and a through-semiconductor via (TSV) within the large STI region and connected to the first underground interconnect pad. Each transistor includes a gate structure, a first conductive region, and a second conductive region. The first underground interconnect line extends along the first direction. The first underground interconnect pad is located within the large STI region and below the initial semiconductor surface.

[0022] According to one aspect of the present disclosure, the large STI region extends from an edge of the first STI region, and the first underground interconnect pad is directly connected to the first underground interconnect line.

[0023] According to one aspect of the present disclosure, the TSV extends from a lower surface of the first underground interconnect pad to a back surface of the semiconductor substrate and is configured to transmit power or data signals from the back surface of the semiconductor substrate to the first underground interconnect pad, the back surface facing the initial semiconductor surface.

[0024] According to one aspect of the present disclosure, the first conductive region of a first transistor of the set of transistors is electrically connected to the first underground interconnect line via a connection plug located within an active area accommodating the first transistor, and the power signal or the data signal is transmitted to the first transistor via the first underground interconnect pad, the first underground interconnect line, and the corresponding connection plug.

[0025] According to one aspect of the present disclosure, the connection plug contacts a sidewall of the first underground interconnection line.

[0026] According to one aspect of the present disclosure, the semiconductor circuit structure further includes a conductive pad adjacent to a back surface of the semiconductor substrate and connected to the TSV.

[0027] These and other embodiments of the present disclosure will be better understood with regard to the following detailed description of non-limiting embodiments, the following description being made with reference to the accompanying drawings. BRIEF DESCRIPTION OF THE DRAWINGS

[0028] FIG. 1 shows a schematic top view of a conventional semiconductor circuit structure having STI regions and active areas.

[0029] FIG. 2A shows a schematic top view of a semiconductor circuit structure according to some embodiments of the present disclosure.

[0030] FIG. 2B is a schematic cross-sectional view of the semiconductor circuit structure taken along line BB' shown in FIG. 2A.

[0031] FIG. 2C is a schematic cross-sectional view of the semiconductor circuit structure taken along line CC' shown in FIG. 2A.

[0032] FIG. 2D shows a schematic top view of a semiconductor circuit structure according to some embodiments of the present disclosure.

[0033] FIG. 2E shows a schematic top view of a semiconductor circuit structure according to some embodiments of the present disclosure.

[0034] FIG. 3 shows a schematic top view of a semiconductor circuit structure according to some embodiments of the present disclosure.

[0035] FIG. 4 shows a schematic cross-sectional view of a semiconductor circuit structure according to some embodiments of the present disclosure.

[0036] FIG. 5 shows a schematic cross-sectional view of a semiconductor circuit structure according to some embodiments of the present disclosure.

[0037] FIG. 6 shows a schematic cross-sectional view of a semiconductor circuit structure according to some embodiments of the present disclosure.

[0038] FIG. 7 shows a schematic cross-sectional view of a semiconductor circuit structure according to some embodiments of the present disclosure.

[0039] FIG. 8 shows a schematic cross-sectional view of a semiconductor circuit structure according to some embodiments of the present disclosure.

[0040] FIG. 9 shows a schematic cross-sectional view of a semiconductor circuit structure according to some embodiments of the present disclosure.

[0041] FIG. 10 shows a schematic cross-sectional view of a semiconductor circuit structure according to some embodiments of the present disclosure.

[0042] FIG. 11A shows the temperature distribution of a FinFET established by TCAD Sentaurus.

[0043] FIG. 11B shows the temperature difference versus the thickness of the STI region.

[0044] FIG. 12 shows a schematic cross-sectional view of a semiconductor circuit structure according to some embodiments of the present disclosure.

[0045] 13A-21 illustrate a method for fabricating an underground interconnect structure in an STI region according to some embodiments of the present disclosure.

[0046] 22A-29C illustrate a method for fabricating an underground interconnect structure in an STI region according to some embodiments of the present disclosure.

[0047] 30A-30B illustrate a method of manufacturing a UGI mesh according to some embodiments of the present disclosure. Detailed Description

[0048] Various embodiments will now be described in more detail with reference to the accompanying drawings, which are provided for purposes of illustration and description, and not for purposes of limitation. For clarity, components may not be drawn to scale. Additionally, some components and / or reference numerals may be omitted from some of the drawings. It is contemplated that elements and features of one embodiment may be beneficially incorporated in other embodiments without further description. In the following method for manufacturing a semiconductor device, one or more additional operations may be present between those described, and the order of operations may differ. The figures use the same / similar reference numerals to indicate the same / similar elements.

[0049] As used herein and in the appended claims, ordinal numbers such as "first," "second," etc., used to describe elements do not imply or represent a particular location in a structure, order of arrangement, or order of manufacture. Ordinal numbers are used only to clearly distinguish between multiple elements having the same name. As used herein and in the appended claims, spatial relationship terms such as "on," "above," "over," "upper," "top," "below," "beneath," "under," "lower," and "bottom" may be used to describe relative spatial or positional relationships between one element and another, as illustrated in the drawings, and these spatial or positional relationships may be direct or indirect unless otherwise specified. Spatial relationship terms are intended to encompass different orientations of the structure in addition to the orientation depicted in the drawings. The structure may be flipped or rotated at various angles, and the spatial relationship descriptions used herein may be interpreted accordingly.

[0050] Additionally, the terms "electrically connected" and "electrically coupled," as used herein and in the claims, may refer to ohmic contact between elements, or current passing through elements, or an operative relationship between elements. An operative relationship may mean, for example, that one element is used to drive another element, but current does not flow directly between the two elements.

[0051] The present disclosure focuses on semiconductor circuit structures that include underground interconnect (UGI) structures within a semiconductor substrate for signal transmission and / or heat dissipation. Signal transmission includes power signal transmission and data signal transmission. The UGI structures can be fabricated in a monolithic integrated circuit fabrication process. The underground interconnect structures can include underground interconnect lines (UGI lines), underground interconnect pads (UGI pads), etc. The underground interconnect structures within the semiconductor substrate can form a mid-side signal transmission network ("mid-side signal network") and / or a heat dissipation network to improve the performance of the integrated circuit.

[0052] In a semiconductor circuit structure on a conventional semiconductor substrate, there are many active regions or active areas (AA) where transistors or circuit elements are arranged, and there are many shallow trench isolation (STI) regions surrounding these active regions, as shown in Figure 1. However, the STI regions of the semiconductor substrate can occupy 40% or more of the total area of ​​the semiconductor substrate, and these STI regions do not provide any special function other than for isolation purposes.

[0053] Meanwhile, FIG. 2A shows a schematic top view of a semiconductor circuit structure 10 according to some embodiments of the present disclosure. FIG. 2B shows a schematic cross-sectional view of the semiconductor circuit structure 10 taken along line BB' in FIG. 2A. FIG. 2C shows a schematic cross-sectional view of the semiconductor circuit structure 10 taken along line CC' in FIG. 2A. As shown in FIGS. 2A-2C, the semiconductor circuit structure 10 of the present invention includes a semiconductor substrate 100 having an initial semiconductor surface 100S. The semiconductor substrate 100 includes one or more active regions or active areas (AA) 10A and one or more shallow trench isolation (STI) regions 114. The STI regions 114 surround the active regions 10A, and the active regions 10A may be isolated from one another by the STI regions 114. The active regions 10A can be used to house one or more transistors. Prior to forming the transistors, a pad oxide layer 104 and a pad nitride layer 106 are formed to define or protect the active regions 10A.

[0054] According to the present invention, the STI region 114 includes one or more underground interconnect (UGI) structures to replace a portion of the initial insulating material (e.g., oxide) within the STI region 114. These underground interconnect (UGI) structures may provide a predetermined function different from the insulating purpose of the initial STI region 114. Such UGI structures are like "mid-side connectors" within the substrate, and the aforementioned composite STI region including the initial insulating material and UGI structures can be considered heterogeneous STI (HSTI).

[0055] In one embodiment, the UGI structure includes a UGI element 105 (e.g., a conductive material or other suitable material) and a barrier layer 107. The barrier layer 107 covers the bottom surface and / or sidewalls of the UGI element 105. The barrier layer 107 shown in FIGS. 2A-2C can be omitted in some embodiments, i.e., the UGI structure may not include the barrier layer 107. The UGI structure is located below the initial semiconductor surface 100S of the semiconductor substrate 100. Furthermore, the UGI structure is formed within an STI region 114. For example, as shown in FIG. 2B, the UGI element 105 is sandwiched by the material of the STI region 114. In this embodiment, the UGI structure extends along the X-direction, and the STI region 114 also extends along the X-direction. In such a case, the UGI structure or the UGI element may be a UGI line.

[0056] In one embodiment, the UGI structures or elements within and extending along the STI regions 114 can be connected to the source or drain terminals of the transistors in a self-aligned or self-assembled manner by connection plugs in the active region 10A, which are connected to the sidewalls of the UGI structures.

[0057] The UGI structure in the STI region 114 can be used for signal delivery (including power and data signals) and / or heat dissipation. For signal delivery, the UGI element 105 may include (or be made of) a metal such as tungsten, and the barrier layer 107 may include (or be made of) titanium nitride (TiN). Rather than being limited to a particular type of metal material, there are still several suitable metal layers that can be suitably used in the UGI element 105. For heat dissipation, the UGI element 105 can include, in the STI region 114, a material with a higher thermal conductivity than the initial insulating material (such as an oxide), such as AlN, BN, SiC, and metal.

[0058] FIG. 2D shows a schematic top view of a semiconductor circuit structure 20 according to one embodiment of the present disclosure. The semiconductor circuit structure 20 may be formed in a semiconductor chip or substrate. FIG. 2D illustrates more active regions or active areas 20A, STI regions 20B, and pad open layers 20C that may accommodate contact pads of the semiconductor circuit structure 20. Several large STI regions 224-1 through 224-4 of the STI region 20B may be disposed in corner regions adjacent to the peripheral / edge regions of the semiconductor chip or in a spare region in the center of the chip. Large UGI structures (e.g., UGI pads) 209 are located within the large STI regions 224-1 through 224-4 and are disposed below the initial semiconductor surface of the semiconductor substrate. Additionally, other thin or long UGI structures (e.g., UGI lines) 205 are disposed below the initial semiconductor surface of the semiconductor substrate and are formed within those thin or long STI regions 214-1 through 214-4 of the STI region 20B. The UGI structure 205 and STI regions 214-1 through 214-4 may extend along the X direction (or along the length of the active region). Furthermore, the UGI structure 205 may extend across two or more active regions 20A. For example, the UGI structure 205 located in the upper right portion of FIG. 2D extends from a predetermined point in the STI region 214-1 adjacent to the active region 20A-1 to the large STI region 224-1.

[0059] 3 , a first set of active regions extending along the x-direction is located on one side of STI region 214-1, and a second set of active regions also extending along the x-direction is located on the other side of STI region 214-1. Thus, STI region 214-1 is located between the first and second sets of active regions and extends along the x-direction. Furthermore, VHDC structure 205 within STI region 214-1 is located between the first and second sets of active regions and also extends along the x-direction. In one embodiment, the smallest and / or largest width (e.g., along the y-direction) of VHDC structure 205 between the first and second sets of active regions is smaller than the width (e.g., along the y-direction) of VHDC structure 209 connected to VHDC structure 205.

[0060] Each of STI regions 214-1 through 214-4 may be adjacent to a set of transistors in active area 20A, and large STI region 224-1 may be remote from the set of transistors. UGI structure 205 is electrically coupled to UGI structure 209 or directly connected to UGI structure 209. Each of UGI structures 205 and 209 may include a UGI element and a barrier layer, as shown in FIGS. 2A-2C . In some embodiments, UGI structures 205 and 209 may not include a barrier layer.

[0061] The width of the large STI region 224-1 along the Y direction is greater than the width of the STI region 214-1 along the Y direction. The width of the UGI structure 209 along the Y direction is greater than the width of the UGI structure 205 along the Y direction. For example, the width of the UGI structure 209 along the Y direction may range from about 2 μm (micrometers) to about 8 μm. The width of the UGI structure 205 along the Y direction may range from about 10 nm (nanometers) to about 100 nm. The area of ​​the UGI structure 209 is about 4 μm (micrometers). 2 to approximately 50 μm (micrometers) 2 For signal transmission, UGI structures 205 and 209 may include (or be made of) a metal such as tungsten. The materials of UGI structures 205 and 209 may be the same or different.

[0062] 2E, the large STI regions 224 may form extra alignment marks for the backside signal / power distribution network and backside TSVs (Through Silicon Vias), i.e., signals / power are supplied to the active areas from the backside of the active areas. Of course, the large STI regions 224 may also form extra alignment marks for the topside signal / power distribution network and topside TSVs, i.e., signals / power are supplied to the active areas from the topside of the active areas.

[0063] In other embodiments, the UGI structures may extend along a direction other than the X-direction, as shown in FIG. 3 . FIG. 3 illustrates a schematic top view of a semiconductor circuit structure 30 according to some embodiments of the present disclosure. Compared with the semiconductor circuit structure 20 illustrated in FIG. 2D , the semiconductor circuit structure 30 illustrated in FIG. 3 further includes STI regions 314-1, 314-2, and 314-3 and UGI structures 305-1, 305-2, and 305-3 extending along the Y-direction. The UGI structures 305-1, 305-2, and 305-3 are disposed below the initial semiconductor surface of the semiconductor substrate and are formed within the STI regions 314-1, 314-2, and 314-3, respectively. The UGI structures 305-1, 305-2, and 305-3 may be UGI lines. UGI structures 305-1, 305-2, and 305-3 and STI regions 314-1, 314-2, and 314-3 can extend along the Y direction (or along the width direction of the active area). Furthermore, UGI structures 305-1, 305-2, and 305-3 can extend across two or more active areas 20A. For example, UGI structure 305-1, located in the upper left portion of FIG. 3, extends from a predetermined point in STI region 314-1 adjacent to active area 20A-2 to horizontal STI region 214. Each of STI regions 314-1, 314-2, and 314-3 can adjoin a set of transistors in active area 20A.

[0064] 3, UGI structures extending along directions other than the X direction can be connected to (or electrically coupled with) UGI structures extending along the X direction and / or UGI pads in the large STI region. For example, UGI structure 305-1 is connected to (or electrically coupled with) UGI structure 205, UGI structure 305-2 is connected to (or electrically coupled with) two UGI structures 205 and is connected between these two UGI structures 205, and UGI structure 305-3 is connected to (or electrically coupled with) UGI pad 209 in the large STI region 224. UGI structures 305-1, 305-2, and 305-3 may have similar dimensions and materials as UGI structure 205. Each of UGI structures 305-1, 305-2, and 305-3 may include a UGI element (or may further comprise a barrier layer), as shown in FIG. 1.

[0065] The arrangement of UGI structures / lines extending along the X direction, UGI structures / lines extending along the Y direction (or a direction other than the X direction), and UGI pads within the large STI region provides a UGI mesh (or mid-side signal network) within the chip or semiconductor substrate and below the initial semiconductor surface of the semiconductor substrate. UGI structures extending along the X direction (i.e., horizontal UGI lines) can be used to connect UGI structures (i.e., UGI pads) within the large STI region or the sources / drains of transistors within the active region, and UGI structures extending along the Y direction (i.e., vertical UGI lines) can be used to connect UGI pads or horizontal UGI lines.

[0066] [1. UGI-based Mid-Side Signal Power Network]

[0067] 4 to 6 relate to mid-side signal / power networks based on UGI structures. For the layout of UGI structures on the XY plane, please refer to the descriptions related to FIGS. 2 and 3. The positions, sizes, and numbers of UGI structures are not limited to those shown in FIGS. 2 and 3.

[0068] In some embodiments, large STI regions such as those shown in FIGS. 2 and 3 may be employed to align with one or more TSVs, as shown in FIG. 4. FIG. 4 illustrates a schematic cross-sectional view of a semiconductor circuit structure 40 according to some embodiments of the present disclosure. The semiconductor circuit structure 40 includes a semiconductor substrate 400 having an initial semiconductor surface 400S, an active region 40A in the semiconductor substrate 400, transistors TS formed in the active region 40A based on the semiconductor substrate 400, an STI region 414, a large STI region 424, a first UGI structure in the STI region 414, and a second UGI structure in the large STI region 424. Each transistor TS includes a first conductive region (e.g., a source) T1, a second conductive region (e.g., a drain) T2, and a gate structure T3. A first UGI structure (e.g., a UGI line) in the STI region 414 and a second UGI structure (e.g., a UGI pad) in the large STI region 424 are disposed below the initial semiconductor surface 400S of the semiconductor substrate 400, with the first UGI structures extending along the X direction. Each of the first UGI structures may include a UGI element 405 and a barrier layer 407 on the bottom surface and / or sidewall of the UGI element 405. Each of the second UGI structures may include a UGI element 409 and a barrier layer 407 on the bottom surface and / or sidewall of the UGI element 409. The semiconductor circuit structure 40 further includes a connection plug 431 that contacts the sidewall of the UGI element 405 of the first UGI structure and is electrically coupled to the transistor TS and the first UGI structure. A power signal or a data signal may be transmitted to the transistor TS through the second UGI structure, the first UGI structure, and the corresponding connection plug 431. The connection plug 431 is disposed in the active area that accommodates the transistor TS.

[0069] The semiconductor circuit structure 40 further includes a TSV 433 directly below the second UGI structure (i.e., a UGI pad) in the large STI region 424 and connected to the second UGI structure, and a barrier film or insulating film 435 on the sidewall of the TSV 433. The TSV 433 extends from the bottom surface of the second UGI structure to the back surface 400B of the semiconductor substrate 400. The back surface 400B faces the initial semiconductor surface 400S. The TSV 433 may be understood as a backside TSV. The TSV 433 may be electrically connected to the second UGI structure. Power or data signals may be transmitted from the back surface 400B of the semiconductor substrate 400 to the second UGI structure. The TSV 433 may be connected to a backside conductive pad 437 located on or near the back surface 400B of the semiconductor substrate 400 (or on the backside of the chip). The backside conductive pad 437 may be an input for power or data signals. Therefore, the present disclosure provides a convenient and efficient method for realizing a backside signal transmission network. The TSVs 433 may include a conductive material such as copper. The TSVs 433 may be or include Cu pillars. The barrier film 435 may include a dielectric material such as an oxide.

[0070] The semiconductor circuit structure 40 further includes an upper interconnect structure 440 on the semiconductor substrate 400 and a bonding layer 450 on the upper interconnect structure 440. The upper interconnect structure 440 includes a contact structure 441, metal layers M1-M3, connection vias V1 and V2, and a dielectric layer 442. The contact structure 441, the metal layers M1-M3, and the connection vias V1 and V2 are present in the dielectric layer 442, which may include multiple dielectric underlayers. The contact structure 441 is present between the transistor TS and the metal layer M1. The metal layers M1-M3 are sequentially disposed on the initial semiconductor surface 400S of the semiconductor substrate 400 along the Z direction. The metal layers M1-M3 are vertically spaced apart from each other. The connection vias V1 and V2 are disposed on the initial semiconductor surface 400S of the semiconductor substrate 400. The connection via V1 is present between the metal layers M1 and M2. The connection via V2 is present between the metal layers M2 and M3. The metal layers M1-M3 and the connection vias V1 and V2 are electrically connected to each other. The transistor TS is electrically coupled to the metal layer M1 through the contact structure 441. Power or data signals can be transmitted among the backside conductive pad 437, the TSV 433, the second UGI structure, the first UGI structure, the transistor TS, the contact structure 441, the metal layers M1-M3, and the connection vias V1 and V2.

[0071] Conventional semiconductor circuit structures without the proposed UGI structure may encounter TSV misalignment issues, and furthermore, the TSVs must extend to a greater depth to connect to transistors through the metal layer of the upper interconnect structure 440. On the other hand, as shown in FIG. 4 , by using the UGI structure (including UGI lines and / or UGI pads), the present disclosure provides greater misalignment tolerance for the TSVs due to the larger STI region that accommodates the UGI pads, and the backside TSVs have a shorter path to connect to transistors through the UGI structure without going through the metal layer of the upper interconnect structure 440. Therefore, the IR drop between the TSVs and the transistors can be significantly improved.

[0072] FIG. 5 shows a schematic cross-sectional view of a semiconductor circuit structure 50 according to another embodiment of the present invention. The semiconductor circuit structure 50 shown in FIG. 5 differs from the semiconductor circuit structure 40 shown in FIG. 4 in that the semiconductor circuit structure 50 does not include backside TSVs. Without backside signal transmission via backside TSVs, in a typical foundry process, power / data signals can be transmitted from the top surface of the chip to the second or first UGI structure via metal layers M1-M3 and / or connection vias V1 and V2. Furthermore, if necessary, the second or first UGI structure can also be connected to a transistor (or other UGI structure) via metal layers M1-M3 and connection vias V1 and V2. The first or second conductive region of the transistor TS can be electrically connected to the second UGI structure via metal layers M1-M3 and connection vias V1 and V2.

[0073] FIG. 6 shows a schematic cross-sectional view of a semiconductor circuit structure 60 according to some embodiments of the present disclosure. As shown in FIG. 6, one second UGI structure (i.e., a UGI pad not shown in FIG. 6) in one large STI region 424 is connected to a backside TSV 433 for backside signal transmission, and another second UGI structure (i.e., a UGI pad not shown in FIG. 6) in another large STI region 424 is connected to one connection via 661 (top-side down via) overlying the chip / semiconductor substrate 400 for topside signal transmission. Several first UGI structures (i.e., UGI lines not shown in FIG. 6) can extend within the STI region 414 along the X direction. Furthermore, the semiconductor circuit structure 60 may include one or more first UGI structures 662 (i.e., UGI lines shown by dashed lines in FIG. 6) extending along the Y direction. The UGI lines 662 may connect to the UGI lines of the STI region 414 and / or the UGI pads of the large STI region 424. Therefore, UGI pads and UGI lines extending along different directions can be connected to each other to form a UGI mesh, and the source terminal of a transistor TS can be connected to several UGI lines.

[0074] [2. Heat Dissipation Network Based on UGI]

[0075] 7-10 relate to a heat dissipation network within the midside of a chip or semiconductor substrate based on a UGI structure according to the present disclosure. For the arrangement of the UGI structure on the XY plane, see the descriptions associated with FIGS. 2 and 3. The arrangement, dimensions, and number of UGI structures are not limited to those shown in FIGS. 2 and 3. For heat dissipation applications, the UGI structure can include (or consist of) a highly thermally conductive material, such as tungsten (thermal conductivity approximately 170 W / m·K), boron nitride (BN, thermal conductivity approximately 600 W / m·K), or aluminum nitride (AlN, thermal conductivity approximately 321 W / m·K). It is also possible to use other materials with higher thermal conductivity than the initial material (such as silicon dioxide) of the STI region, such as SiC, SiGe, or undoped Si. In some embodiments, the UGI structure can include (or be made of) a composite material including two or more highly thermally conductive materials. The UGI structure can replace some of the silicon dioxide in the initial STI region, thereby improving heat dissipation capabilities since the material of the UGI structure has a higher thermal conductivity than silicon dioxide and / or silicon.

[0076] Similar to the UGI structure used for signal / power transmission, the UGI structure used for heat dissipation is separated from the active area where the transistors are placed by several STI regions to a UGI pad (e.g., the area of ​​the UGI pad is about 4 μm 2 to about 50 μm 2 ) are placed, similar to those shown in Figures 2 and 3. The UGI structures can be thermally coupled to each other. For example, the UGI structure (i.e., UGI pad) of the large STI region can be thermally coupled to the UGI structure (i.e., UGI line) of the STI region. Furthermore, the large STI region can be adapted to align with one or more TSVs, as shown in Figure 4. The TSVs can be used for heat dissipation, and the TSVs can be understood as thermal vias. Furthermore, compared to signal / power transmission, all or most (e.g., 60% or more, or 70% to 90%) of the STI region in the semiconductor chip can be filled with the proposed UGI structure for heat dissipation purposes.

[0077] 7 is a schematic cross-sectional view of a semiconductor circuit structure 70 according to some embodiments of the present disclosure. The main difference between the semiconductor circuit structure 40 shown in FIG. 4 and the semiconductor circuit structure 70 shown in FIG. 7 is that the semiconductor circuit structure 70 includes a TSV 733 directly below and connected to a second UGI structure in the large STI region 424 (i.e., a UGI pad), a heat dissipation film 734 on the sidewall of the TSV 733, a barrier film 735 on the sidewall of the heat dissipation film 734, a heat dissipation plate 737 located on or near the back surface 400B of the semiconductor substrate 400 (or on the back surface of the chip), and an upper heat dissipation plate 739 located on the upper interconnect structure 440. The TSV 733 is used for heat dissipation and can be understood as a (backside) thermal via. The heat dissipation plate 737 can be a heat sink, and its material can be the same as that of the heat dissipation film 734 or the TSV 733. The TSVs 733 extend from the bottom surface of the second UGI structure to the back surface 400B of the semiconductor substrate 400. The TSVs 733 are connected between the second UGI structure and the heat dissipation plate 737, forming a heat dissipation path that includes the second UGI structure proximate the transistor, the TSVs 733, and the heat dissipation plate 737. In some embodiments, the barrier film 735 and / or the heat dissipation film 734 can be omitted.

[0078] For heat dissipation, the UGI structure in this embodiment may include (or be made of) a material with a thermal conductivity higher than that of SiO2 and / or Si. For example, the UGI structure may include tungsten, copper, BN, AlN, SiC, SiGe, or undoped Si, or a combination thereof. In some embodiments, the UGI structure includes an insulating material with a thermal conductivity higher than that of SiO2 and / or Si. The TSVs 733 may include copper, and the heat dissipation film 734 may be BN or AlN.

[0079] Furthermore, TSV733 is directly connected to a second UGI structure (such as a UGI pad of STI isolation 424), which in turn is connected to a first UGI structure (such as a UGI line of STI isolation 414). The first UGI structure is connected to a transistor (such as a source / drain region of the transistor) through a corresponding connecting plug 431. In this manner, heat generated from the transistor can be dissipated to TSV733 via connecting plug 431, the first UGI structure, and the second UGI structure. Therefore, a UGI heat dissipation network with high heat dissipation efficiency is provided. In another embodiment, the UGI structure may be isolated from the transistor, but the heat dissipation objective can be achieved via the UGI line, UGI pad, and TSV733.

[0080] Conventional semiconductor circuit structures may include only upper thermal vias in the upper interconnect structure 440 and may not include UGI structures, particularly UGI pads. Therefore, aligning the upper thermal vias is a significant issue. Furthermore, the upper thermal vias in conventional semiconductor circuit structures are located within the dielectric layer 442 of the upper interconnect structure 440 and are only insulated by the dielectric layer 442, which means that the upper thermal vias are far from the transistors. Therefore, it is difficult to efficiently dissipate the heat generated by the transistors. However, the semiconductor circuit structure according to the present disclosure provides a larger alignment window for the thermal vias with the aid of the UGI pads. Furthermore, the UGI structure shortens the thermal coupling path between the thermal vias and the source / drain terminals of the transistors. Therefore, the configuration according to the present disclosure can efficiently dissipate the heat generated by the transistors.

[0081] 8 shows a schematic cross-sectional view of a semiconductor circuit structure 80 according to some embodiments of the present disclosure. The semiconductor circuit structure 80 includes an upper thermal via 833 in the dielectric layer 442 of the upper interconnect structure 440. The upper thermal via 833 extends upward from the top surface of the second UGI structure to the upper heat dissipation plate 739 and penetrates the dielectric layer 442 of the upper interconnect structure 440.

[0082] Thus, the upper thermal via 833 is connected to the second UGI structure (such as a UGI pad of the STI insulation 424) and the upper heat dissipation plate 739, which is then connected to the first UGI structure (such as a UGI line of the STI insulation 414), and the first UGI structure is connected to the transistor (such as a source / drain region of the transistor) via the corresponding connection plug 431. Thus, the upper heat dissipation plate 739, the upper thermal via 833, and the first and second UGI structures can form a heat dissipation path for heat generated from the transistor. In this way, the heat generated from the transistor can be dissipated to the upper thermal via 833 via the connection plug 431, the first UGI structure, and the second UGI structure. A UGI heat dissipation network with high heat dissipation efficiency is provided.

[0083] In another embodiment, the UGI structure (such as the UGI line of STI isolation 414) can be isolated from the transistor, but the heat dissipation purpose can still be achieved. In other embodiments, the upper thermal via 833 can extend from the top surface of the upper interconnect structure 440 to the first UGI structure. The upper thermal via 833 can include (or be made of) a material with a higher thermal conductivity than Si or SiO2, such as copper.

[0084] 9 shows a schematic cross-sectional view of a semiconductor circuit structure 90 according to some embodiments of the present disclosure. The semiconductor circuit structure 90 shown in FIG. 9 differs from the semiconductor circuit structure 80 shown in FIG. 8 in that the semiconductor circuit structure 90 includes an upper heat dissipation film 934 on the sidewall of the upper thermal via 833. The upper heat dissipation film 934 may include (or be made of) a material having a higher thermal conductivity than Si or SiO2, such as BN or AlN. By configuring the upper heat dissipation film 934 on the upper thermal via 833, heat dissipation efficiency can be improved.

[0085] In some embodiments, as shown in FIG. 10 , the TSVs 733 shown in FIG. 7 and the upper thermal vias 833 shown in FIG. 8 (or the upper heat dissipation film 934 and upper thermal vias 833 in FIG. 9 ) can be combined together. In the semiconductor circuit structure 91 shown in FIG. 10 , some upper thermal vias 833 extend from the top surface of the upper interconnect structure 440 to the second UGI structure and are connected to an upper heat dissipation plate 739. The TSVs 733 (additional thermal vias) extend from the back surface 400B of the semiconductor substrate 400 to the second UGI structure (or other UGI structure) and are connected to a heat dissipation plate 737 located on or near the back surface 400B of the semiconductor substrate 400. Such a sandwich structure (with an intermediate UGI structure within the chip, an upper heat dissipation plate connected to the intermediate UGI structure, and a heat dissipation plate on the back surface of the semiconductor substrate and connected to the intermediate UGI structure) can significantly improve the heat dissipation capability of the IC chip. In some embodiments, the barrier film 735 and / or the heat dissipation film 734 can be omitted.

[0086] FIG. 11A illustrates a semiconductor circuit structure including a FinFET transistor and an STI region adjacent to (or surrounding) the FinFET transistor, where a portion of the STI region (shown as a diagonal line) is replaced with a tungsten UGI structure. FIG. 11A also illustrates the temperature distribution of the FinFET, established by the TCAD simulation software Sentaurus. The temperature difference (ΔT) between the transistor's peak temperature (hot spot region) and the ambient temperature (40°C) is calculated when a portion of the STI region is replaced with tungsten, as shown in FIG. 11B. The term "full" in FIG. 11B indicates that none of the STI region is replaced with tungsten. The terms "1 nm" to "15 nm" represent the remaining thickness of the STI region that is not replaced with tungsten. It is clear that the smaller the remaining thickness of the STI region, the smaller the temperature difference between the transistor's peak temperature and the ambient temperature (improving heat dissipation performance). Therefore, the present disclosure can effectively reduce the transistor's peak temperature.

[0087] [3. UGI-based signal network and heat dissipation network within the same chip]

[0088] Signal transmission and heat dissipation based on the UGI structure according to the present disclosure can be combined together in the same IC chip, as shown in FIG. 12. In the semiconductor circuit structure 92 shown in FIG. 12, several upper thermal vias 833 extend from the top surface of the upper interconnect structure 440 to the second UGI structure (e.g., UGI pad) in the large STI region 424 and are connected to the upper heat dissipation plate 739. An upper heat dissipation film 934 is on the sidewall of the upper thermal vias 833. A TSV 433 is located directly below the second UGI structure (i.e., UGI pad) in the large STI region 424 and is connected to the second UGI structure. The TSV 433 extends from the bottom of the second UGI structure (i.e., UGI pad) to the back surface 400B of the semiconductor substrate 400 and is connected to one or more back surface conductive pads 437 on the back surface 400B of the semiconductor substrate 400 (or the back surface of the chip) for power or data signal transmission. A lower heat dissipation plate 737 located on the back surface 400B of the semiconductor substrate 400 may surround or be coupled to the back surface conductive pad 437.

[0089] The heat dissipation film 4331 may be on a sidewall of the TSV 433, and the barrier film 4332 may be on a sidewall of the heat dissipation film 4331. The TSV 433 may include (or be made of) a conductive material such as copper. The heat dissipation film 4331 may include (or be made of) a material with a higher thermal conductivity than Si or SiO2, such as BN or AlN, to aid in heat dissipation. The barrier film 4332 may include a dielectric such as an oxide. In some embodiments, on the same chip / semiconductor substrate, some UGI pads are used for signal transmission and other UGI pads are used for heat dissipation.

[0090] 13A-21 illustrate exemplary methods for fabricating a UGI structure according to some embodiments of the present disclosure.

[0091] FIG. 13A shows a schematic top view of a structure at a stage of a manufacturing method, FIG. 13B shows a schematic cross-sectional view of the structure at the stage shown along line BB' shown in FIG. 13A, and FIG. 13C shows a schematic cross-sectional view of the structure at the stage shown along line CC' shown in FIG. 13A. Referring to FIGS. 13A-13C, a pad oxide layer 1204 and a pad nitride layer 1206 are deposited to define an active area. Portions of the semiconductor substrate 1202 outside the active area are removed. The semiconductor substrate 1202 may include or be made of a semiconductor material such as silicon. Next, an oxide layer is deposited and etched back to form portions of shallow trench isolation (STI) regions 1214.

[0092] FIG. 14A shows a schematic top view of a structure at a stage of the fabrication method, FIG. 14B shows a schematic cross-sectional view of the structure at the stage shown along line BB′ in FIG. 14A, and FIG. 14C shows a schematic cross-sectional view of the structure at the stage shown along line CC′ in FIG. 14A. Referring to FIGS. 14A-14C, a thermal oxide layer 1205 is grown along the exposed sidewalls of the active region. The thermal oxide layer 1205 may have a length along the Z direction of about 89-200 nm. The thermal oxide layer 1205 may have a thickness along the Y direction of about 2.5 nm. Depending on the pitch of the active regions, the distance between the thermal oxide layers 1205 on different active regions along the Y direction may be about 13 nm. The top surface of the thermal oxide layer 1205 may be lower in the Z direction than the top surface of the pad oxide layer 1204 and the bottom surface of the pad nitride layer 1206. A portion of the STI region 1214 may be exposed, or the lower portion of the STI region 1214 may also be covered by the thermal oxide layer 1205 .

[0093] FIG. 15A shows a schematic top view of the structure at a stage in the fabrication method, FIG. 15B shows a schematic cross-sectional view of the structure at the stage shown along line BB' shown in FIG. 15A, and FIG. 15C shows a schematic cross-sectional view of the structure at the stage shown along line CC' shown in FIG. 15A. Referring to FIGS. 15A-15C, SOD material 1207 is deposited to fill the spaces between the active areas. A planarization process, such as a chemical mechanical planarization (CMP) process, can be performed to remove portions of SOD material 1207 above pad nitride layer 1206 and make the top surfaces of SOD material 1207 and pad nitride layer 1206 coplanar.

[0094] Figure 16A shows a schematic top view of the structure at a stage in the fabrication method, Figure 16B shows a schematic cross-sectional view of the structure at the stage shown along line BB' shown in Figure 16A, and Figure 16C shows a schematic cross-sectional view of the structure at the stage shown along line CC' shown in Figure 16A. Referring to Figures 16A-16C, a photoresist layer 1306 is formed and patterned to cover a portion of the active area and expose a portion of the SOD material 1207. For example, more than half of the active area can be covered with photoresist layer 1306.

[0095] FIG. 17A shows a schematic top view of the structure at a stage of the fabrication process. FIG. 17B shows a schematic cross-sectional view of the structure at the stage shown along line BB′ in FIG. 17A. FIG. 17C shows a schematic cross-sectional view of the structure at the stage shown along line CC′ in FIG. 17A. Referring to FIGS. 17A-17C, the portion of SOD material 1207 not covered by photoresist layer 1306 and the thermal oxide layer 1205 covered by this portion of SOD material 1207 are removed to form a narrow slot between the retained SOD material 1207 and the active region. The narrow slot may have a width along the Y direction of 2 to 5 nm, e.g., 3 nm. After removing the portion of SOD material 1207 not covered by photoresist layer 1306 and the underlying thermal oxide layer 1205, one sidewall of the active region is exposed in the narrow slot.

[0096] FIG. 18A shows a schematic top view of the structure at a stage of the fabrication method, FIG. 18B shows a schematic cross-sectional view of the structure at a stage indicated by line BB′ shown in FIG. 18A, and FIG. 18C shows a schematic cross-sectional view of the structure at a stage indicated by line CC′ shown in FIG. 18A. Referring to FIGS. 18A-18C, photoresist layer 1306 is removed, and a material (e.g., SiOCN) 1209 different from thermal oxide layer 1205 is deposited in the narrow slot. A planarization process, such as a CMP process, can be performed to remove portions of SiOCN material 1209 on pad nitride layer 1206 and SOD material 1207 and to make the top surfaces of SiOCN material 1209, SOD material 1207, and pad nitride layer 1206 coplanar. Thus, an asymmetric spacer including different materials (e.g., thermal oxide layer 1205 and SiOCN material 1209) is formed in STI region 1214. Viewed another way, such asymmetric spacers each cover two sidewalls of the active area.

[0097] FIG. 19A shows a schematic top view of a structure at a stage of a manufacturing method, FIG. 19B shows a schematic cross-sectional view of the structure at the stage shown along line BB′ in FIG. 19A, and FIG. 19C shows a schematic cross-sectional view of the structure at the stage shown along line CC′ in FIG. 19A. Referring to FIGS. 19A-19C, the SOD material 1207 removes the space formed between the thermal oxide layer 1205 and the SiOCN material 1209. A TiN layer 1303 and a tungsten layer 1305 are sequentially deposited in the space, and then an etch-back process is performed to remove a portion of the TiN layer 1303 and a portion of the tungsten layer 1305. After the etch-back process, the retained tungsten layer 1305 can be defined as an underground interconnect (UGI) structure, and the retained TiN layer 1303 can be defined as a barrier layer. The TiN layer 1303 exists between the tungsten layer 1305 and the thermal oxide layer 1205. The TiN layer 1303 is between the tungsten layer 1305 and the SiOCN material 1209. The TiN layer 1303 is between the tungsten layer 1305 and the STI region 1214. The distance between the top surface of the thermal oxide layer 1205 and the top surface of the tungsten layer 1305 along the Z direction can be 39 to 150 nm. The distance between the top surface of the tungsten layer 1305 and the top surface of the STI region 1214 along the Z direction can be 50 to 150 nm. The thickness of the STI region 1214 along the Z direction can be 20 to 50 nm.

[0098] FIG. 20A shows a schematic top view of a structure at one stage of a fabrication process, FIG. 20B shows a schematic cross-sectional view of the structure at the stage indicated by line BB' in FIG. 20A, and FIG. 20C shows a schematic cross-sectional view of the structure at the stage indicated by line CC' in FIG. 20A. Referring to FIGS. 20A-20C, a SiN layer 1307 and an HDP (high-density plasma) oxide layer 1309 are sequentially formed on a tungsten layer 1305 and a TiN layer 1303. Thus, an STI region between active regions is completed. As a result, an underground interconnect structure within the STI region is provided, and a three-dimensional schematic diagram of the structure is shown in FIG. 21. Fabrication processes for forming transistors within the active regions can be performed after the stages shown in FIGS. 20A-20C.

[0099] In one example, the UGI structure or UGI element extending within and along the STI region can be connected to the source or drain terminal of a transistor by a connection plug in the active region. For example, after removing a portion of the active region to form a trench, the asymmetric spacer of SiOCN material 1209 and the thermal oxide layer 1205 are exposed in the trench. Next, thermal oxide is formed to cover the exposed Si portion in the trench so that only one sidewall of the trench is covered by the SiOCN material 1209. Then, the SiOCN material 1209 is removed to expose the sidewall of the UGI structure. Then, a connection plug (e.g., tungsten or heavily doped Si) is filled in the trench to connect to the exposed sidewall of the UGI structure.

[0100] If there is no need to connect the UGI structure to the source or drain terminal of a transistor, the steps of forming the asymmetric spacer of SiOCN material 1209 and thermal oxide layer 1205 can be omitted, and it is sufficient to only form thermal oxide layer 1205, as shown in Figures 14A-14C. Then, the UGI structure can be deposited on top of STI region 1214, and other dielectrics (such as SiN layer 1307 and HDP oxide layer 1309) can be formed on top of the UGI structure.

[0101] 22A-29C illustrate a method for fabricating an underground interconnect structure in an STI region according to some embodiments of the present disclosure.

[0102] FIG. 22A shows a schematic top view of a structure at a stage of a manufacturing method, FIG. 22B shows a schematic cross-sectional view of the structure at the stage shown along line BB′ shown in FIG. 22A, and FIG. 22C shows a schematic cross-sectional view of the structure at the stage shown along line CC′ shown in FIG. 22A. Referring to FIGS. 22A-22C, a pad oxide layer 2204 and a pad nitride layer 2206 are deposited to define active areas. Portions of the semiconductor substrate 2202 outside the active areas are removed. The semiconductor substrate 2202 may include or be made of a semiconductor material such as silicon. Next, an oxide layer is deposited and etched back to form shallow trench isolation (STI) regions 2214. The width of the pad nitride layer 2206 along the Y direction may be 12 nm. The distance between two adjacent active areas along the Y direction may be 18 nm. The distance between the bottom surface of the pad oxide layer 2204 and the top surface of the STI region 2214 along the Z direction may be in the range of 150 nm to 200 nm.

[0103] FIG. 23A shows a schematic top view of a structure at a stage of a manufacturing method, FIG. 23B shows a schematic cross-sectional view of the structure at the stage shown along line BB' shown in FIG. 23A, and FIG. 23C shows a schematic cross-sectional view of the structure at the stage shown along line CC' shown in FIG. 23A. Referring to FIGS. 23A-23C, SiOCN material 2209 is deposited along the sidewalls of semiconductor substrate 2202, the sidewalls of pad oxide layer 2204, the sidewalls of pad nitride layer 2206, and the top surface of pad nitride layer 2206. The thickness of SiOCN material 2209 along the Y direction may be 4 nm. The distance D23 between the sidewalls of SiOCN material 2209 along the Y direction may be 10 nm. A portion of STI region 2214 is exposed.

[0104] Figure 24A shows a schematic top view of the structure at a stage in the manufacturing method, Figure 24B shows a schematic cross-sectional view of the structure at the stage shown along line BB' shown in Figure 24A, and Figure 24C shows a schematic cross-sectional view of the structure at the stage shown along line CC' shown in Figure 24A. Referring to Figures 24A-24C, SOD material 2207 is deposited to fill the spaces between the active areas. A planarization process, such as a CMP process, can be performed to remove the portion of SOD material 2207 above pad nitride layer 2206 and make the top surfaces of SOD material 2207 and pad nitride layer 2206 coplanar.

[0105] Figure 25A shows a schematic top view of the structure at a stage in the fabrication method, Figure 25B shows a schematic cross-sectional view of the structure at the stage shown along line BB' shown in Figure 25A, and Figure 25C shows a schematic cross-sectional view of the structure at the stage shown along line CC' shown in Figure 25A. Referring to Figures 25A-25C, a photoresist layer 2306 is formed and patterned to cover a portion of the active area and to expose a portion of SOD material 2207 and a portion of SiOCN material 2209. For example, more than half of the active area can be covered with photoresist layer 2306.

[0106] FIG. 26A shows a schematic top view of the structure at a stage in the manufacturing method, FIG. 26B shows a schematic cross-sectional view of the structure at the stage shown along line BB' shown in FIG. 26A, and FIG. 26C shows a schematic cross-sectional view of the structure at the stage shown along line CC' shown in FIG. 26A. Referring to FIGS. 26A-26C, portions of SiOCN material 2209 not covered by photoresist layer 2306 and SOD material 2207 are removed, and photoresist layer 2306 is removed. Slots 2210 are formed between the retained SiOCN material 2209 and the active areas. After the removal, one sidewall of each active area is exposed in slot 2210.

[0107] FIG. 27A shows a schematic top view of the structure at a stage of the fabrication method, FIG. 27B shows a schematic cross-sectional view of the structure at a stage indicated by line BB′ shown in FIG. 27A, and FIG. 27C shows a schematic cross-sectional view of the structure at a stage indicated by line CC′ shown in FIG. 27A. Referring to FIGS. 27A-27C, a thermal oxide layer 2205 is grown along the exposed sidewalls of the active regions and within the slots 2210. The upper surface of the thermal oxide layer 2205 can be lower in the Z direction than the upper surface of the pad oxide layer 2204 and the lower surface of the pad nitride layer 2206. Thus, asymmetric spacers comprising different materials (e.g., thermal oxide layer 2205 and SiOCN material 2209) are formed within the STI regions 2214. From another perspective, such asymmetric spacers cover two sidewalls of each active region.

[0108] FIG. 28A shows a schematic top view of the structure at a stage of the manufacturing method, FIG. 28B shows a schematic cross-sectional view of the structure at the stage shown along line BB' shown in FIG. 28A, and FIG. 28C shows a schematic cross-sectional view of the structure at the stage shown along line CC' shown in FIG. 28A. Referring to FIGS. 28A-28C, a TiN layer 2303 and a tungsten layer 2305 are sequentially deposited in slot 2210, and then an etch-back process is performed to remove a portion of TiN layer 2303 and a portion of tungsten layer 2305. After the etch-back process, the retained tungsten layer 2305 can be defined as an underground interconnect (UGI) structure, and the retained TiN layer 2303 can be defined as a barrier layer.

[0109] FIG. 29A shows a schematic top view of a structure at a stage of a fabrication method, FIG. 29B shows a schematic cross-sectional view of the structure at the stage shown along line BB' in FIG. 29A, and FIG. 29C shows a schematic cross-sectional view of the structure at the stage shown along line CC' in FIG. 29A. Referring to FIGS. 29A-29C, a SiN layer 2307 and an HDP (high-density plasma) oxide layer 2309 are sequentially formed on the tungsten layer 2305 and the TiN layer 2303. Thus, a structure including an underground interconnect structure within the STI region is provided. Fabrication steps for forming transistors in the active region can be performed after the stages shown in FIGS. 29A-29C.

[0110] 30A-30B illustrate an exemplary method for fabricating a UGI mesh according to some embodiments of the present disclosure. FIGS. 30A-30B show schematic top views of the structure at different stages of the fabrication method. A pad oxide layer and a pad nitride layer 3206 are sequentially deposited on a semiconductor substrate. Next, a temporary active area is first defined by a photolithography process, and STI and large STI areas (shown by dotted lines in FIG. 30A) are defined outside the temporary active area. Then, material for the UGI structure is formed in the STI and large STI areas, as described above. The true active area 30A is then defined by another photolithography process, and the removed temporary active area can be used for the remaining STI area, as shown in FIG. 30B.

[0111] The present disclosure provides underground interconnect structures (e.g., UGI lines and UGI pads) below the initial semiconductor surface and within the STI region. The UGI structures are isolated from the semiconductor substrate, and depending on requirements, several UGI structures can be connected to transistors. This underground interconnect structure can form a UGI mesh (which can also be understood as a mid-side signal / power transmission network or heat dissipation network) within the chip or semiconductor substrate, providing greater misalignment tolerance through large STI regions with ample space for signal routing, shortening the path connecting the backside TSVs to the UGI mesh to improve IR drop for signal transmission and improving heat dissipation.

[0112] It should be noted that the above-described structures and methods are provided for illustrative purposes. The present disclosure is not limited to the above-disclosed structures and procedures. Other embodiments having different configurations of known elements are applicable, and the illustrated structures may be adjusted and modified based on the needs of actual applications. Of course, it should be noted that the illustrated configurations are depicted for illustrative purposes only, and not for purposes of limitation. Therefore, it is known to those skilled in the art that the associated elements and layers in the semiconductor structure, the shape or positional relationship of the elements, and the details of the procedures may be adjusted or modified depending on the actual requirements and / or manufacturing stages of the actual application.

[0113] While this disclosure has been described by way of example and in terms of exemplary embodiments, it is to be understood that the disclosure is not limited thereto. On the contrary, the disclosure is intended to cover various modifications and similar arrangements and procedures. The scope of the appended claims, therefore, should be accorded the broadest interpretation so as to encompass all such modifications and similar arrangements and procedures. [Brief explanation of the drawings]

[0114] [Figure 1] 1 shows a schematic top view of a conventional semiconductor circuit structure having an STI region and an active region. [Figure 2A] 1 shows a schematic top view of a semiconductor circuit structure according to some embodiments of the present disclosure. [Figure 2B] 2B is a schematic cross-sectional view of the semiconductor circuit structure shown along line BB' shown in FIG. 2A. [Figure 2C] 2B is a schematic cross-sectional view of the semiconductor circuit structure shown along line CC' shown in FIG. 2A. [Figure 2D] 1 shows a schematic top view of a semiconductor circuit structure according to some embodiments of the present disclosure. [Figure 2E] 1 shows a schematic top view of a semiconductor circuit structure according to some embodiments of the present disclosure. [Figure 3]1 shows a schematic top view of a semiconductor circuit structure according to some embodiments of the present disclosure. [Figure 4] 1A and 1B show schematic cross-sectional views of semiconductor circuit structures according to some embodiments of the present disclosure. [Figure 5] 1A and 1B show schematic cross-sectional views of semiconductor circuit structures according to some embodiments of the present disclosure. [Figure 6] 1A and 1B show schematic cross-sectional views of semiconductor circuit structures according to some embodiments of the present disclosure. [Figure 7] 1A and 1B show schematic cross-sectional views of semiconductor circuit structures according to some embodiments of the present disclosure. [Figure 8] 1A and 1B show schematic cross-sectional views of semiconductor circuit structures according to some embodiments of the present disclosure. [Figure 9] 1A and 1B show schematic cross-sectional views of semiconductor circuit structures according to some embodiments of the present disclosure. [Figure 10] 1A and 1B show schematic cross-sectional views of semiconductor circuit structures according to some embodiments of the present disclosure. [Figure 11A] The temperature distribution of the FinFET established by Sentaurus TCAD is shown. [Figure 11B] The temperature difference is shown as a function of the thickness of the STI region. [Figure 12] 1A and 1B show schematic cross-sectional views of semiconductor circuit structures according to some embodiments of the present disclosure. [Figure 13A] 1 illustrates a method for fabricating an underground interconnect structure in an STI region according to some embodiments of the present disclosure. [Figure 13B] 1 illustrates a method for fabricating an underground interconnect structure in an STI region according to some embodiments of the present disclosure. [Figure 13C] 1 illustrates a method for fabricating an underground interconnect structure in an STI region according to some embodiments of the present disclosure. [Figure 14A] 1 illustrates a method for fabricating an underground interconnect structure in an STI region according to some embodiments of the present disclosure. [Figure 14B] 1 illustrates a method for fabricating an underground interconnect structure in an STI region according to some embodiments of the present disclosure. [Figure 14C]1 illustrates a method for fabricating an underground interconnect structure in an STI region according to some embodiments of the present disclosure. [Figure 15A] 1 illustrates a method for fabricating an underground interconnect structure in an STI region according to some embodiments of the present disclosure. [Figure 15B] 1 illustrates a method for fabricating an underground interconnect structure in an STI region according to some embodiments of the present disclosure. [Figure 15C] 1 illustrates a method for fabricating an underground interconnect structure in an STI region according to some embodiments of the present disclosure. [Figure 16A] 1 illustrates a method for fabricating an underground interconnect structure in an STI region according to some embodiments of the present disclosure. [Figure 16B] 1 illustrates a method for fabricating an underground interconnect structure in an STI region according to some embodiments of the present disclosure. [Figure 16C] 1 illustrates a method for fabricating an underground interconnect structure in an STI region according to some embodiments of the present disclosure. [Figure 17A] 1 illustrates a method for fabricating an underground interconnect structure in an STI region according to some embodiments of the present disclosure. [Figure 17B] 1 illustrates a method for fabricating an underground interconnect structure in an STI region according to some embodiments of the present disclosure. [Figure 17C] 1 illustrates a method for fabricating an underground interconnect structure in an STI region according to some embodiments of the present disclosure. [Figure 18A] 1 illustrates a method for fabricating an underground interconnect structure in an STI region according to some embodiments of the present disclosure. [Figure 18B] 1 illustrates a method for fabricating an underground interconnect structure in an STI region according to some embodiments of the present disclosure. [Figure 18C] 1 illustrates a method for fabricating an underground interconnect structure in an STI region according to some embodiments of the present disclosure. [Figure 19A] 1 illustrates a method for fabricating an underground interconnect structure in an STI region according to some embodiments of the present disclosure. [Figure 19B] 1 illustrates a method for fabricating an underground interconnect structure in an STI region according to some embodiments of the present disclosure. [Figure 19C] 1 illustrates a method for fabricating an underground interconnect structure in an STI region according to some embodiments of the present disclosure. [Figure 20A] 1 illustrates a method for fabricating an underground interconnect structure in an STI region according to some embodiments of the present disclosure. [Figure 20B] 1 illustrates a method for fabricating an underground interconnect structure in an STI region according to some embodiments of the present disclosure. [Figure 20C] 1 illustrates a method for fabricating an underground interconnect structure in an STI region according to some embodiments of the present disclosure. [Figure 21] 1 illustrates a method for fabricating an underground interconnect structure in an STI region according to some embodiments of the present disclosure. [Figure 22A] 1 illustrates a method for fabricating an underground interconnect structure in an STI region according to some embodiments of the present disclosure. [Figure 22B] 1 illustrates a method for fabricating an underground interconnect structure in an STI region according to some embodiments of the present disclosure. [Figure 22C] 1 illustrates a method for fabricating an underground interconnect structure in an STI region according to some embodiments of the present disclosure. [Figure 23A] 1 illustrates a method for fabricating an underground interconnect structure in an STI region according to some embodiments of the present disclosure. [Figure 23B] 1 illustrates a method for fabricating an underground interconnect structure in an STI region according to some embodiments of the present disclosure. [Figure 23C] 1 illustrates a method for fabricating an underground interconnect structure in an STI region according to some embodiments of the present disclosure. [Figure 24A] 1 illustrates a method for fabricating an underground interconnect structure in an STI region according to some embodiments of the present disclosure. [Figure 24B] 1 illustrates a method for fabricating an underground interconnect structure in an STI region according to some embodiments of the present disclosure. [Figure 24C] 1 illustrates a method for fabricating an underground interconnect structure in an STI region according to some embodiments of the present disclosure. [Figure 25A] 1 illustrates a method for fabricating an underground interconnect structure in an STI region according to some embodiments of the present disclosure. [Figure 25B] 1 illustrates a method for fabricating an underground interconnect structure in an STI region according to some embodiments of the present disclosure. [Figure 25C] 1 illustrates a method for fabricating an underground interconnect structure in an STI region according to some embodiments of the present disclosure. [Figure 26A] 1 illustrates a method for fabricating an underground interconnect structure in an STI region according to some embodiments of the present disclosure. [Figure 26B] 1 illustrates a method for fabricating an underground interconnect structure in an STI region according to some embodiments of the present disclosure. [Figure 26C] 1 illustrates a method for fabricating an underground interconnect structure in an STI region according to some embodiments of the present disclosure. [Figure 27A] 1 illustrates a method for fabricating an underground interconnect structure in an STI region according to some embodiments of the present disclosure. [Figure 27B] 1 illustrates a method for fabricating an underground interconnect structure in an STI region according to some embodiments of the present disclosure. [Figure 27C] 1 illustrates a method for fabricating an underground interconnect structure in an STI region according to some embodiments of the present disclosure. [Figure 28A] 1 illustrates a method for fabricating an underground interconnect structure in an STI region according to some embodiments of the present disclosure. [Figure 28B] 1 illustrates a method for fabricating an underground interconnect structure in an STI region according to some embodiments of the present disclosure. [Figure 28C] 1 illustrates a method for fabricating an underground interconnect structure in an STI region according to some embodiments of the present disclosure. [Figure 29A] 1 illustrates a method for fabricating an underground interconnect structure in an STI region according to some embodiments of the present disclosure. [Figure 29B] 1 illustrates a method for fabricating an underground interconnect structure in an STI region according to some embodiments of the present disclosure. [Figure 29C] 1 illustrates a method for fabricating an underground interconnect structure in an STI region according to some embodiments of the present disclosure. [Figure 30A] 1 illustrates a method for manufacturing a UGI mesh according to some embodiments of the disclosure. [Figure 30B] 1 illustrates a method for manufacturing a UGI mesh according to some embodiments of the disclosure.

Claims

1. a semiconductor substrate having an initial semiconductor surface; a set of transistors formed on the semiconductor substrate, each transistor comprising a gate structure, a first conductive region, and a second conductive region; a first shallow trench isolation (STI) region adjacent to the set of transistors and extending along a first direction; a large shallow trench isolation (STI) region spaced apart from the set of transistors; a first underground interconnect line within the first STI region and below the initial semiconductor surface; a first underground interconnect pad electrically coupled to the first underground interconnect line; the first underground interconnection line extends along the first direction; a first underground interconnect pad located within the large shallow trench isolation (STI) region and below the initial semiconductor surface, the first underground interconnect pad having a width greater than a width of the first underground interconnect line;

2. 2. The semiconductor circuit structure of claim 1, wherein said first underground interconnect pad is directly connected to said first underground interconnect line.

3. a through-semiconductor via (TSV) extending from a lower surface of the first underground interconnect pad to a back surface of the semiconductor substrate; 3. The semiconductor circuit structure of claim 2, wherein the TSV is electrically connected to the first underground interconnect pad and configured to carry power or data signals from the back surface of the semiconductor substrate to the first underground interconnect pad, the back surface facing the initial semiconductor surface.

4. 4. The semiconductor circuit structure of claim 3, wherein the first conductive region of a first transistor of the set of transistors is electrically connected to the first underground interconnect line through a connection plug located in an active area accommodating the first transistor, and the power signal or the data signal is transmitted to the first transistor through the first underground interconnect pad, the first underground interconnect line, and the corresponding connection plug.

5. 5. The semiconductor circuit structure of claim 4, wherein the connecting plug contacts a sidewall of the first underground interconnect line.

6. 4. The semiconductor circuit structure of claim 3, wherein both the first underground interconnect pad and the first underground interconnect line comprise W and TiN.

7. The semiconductor circuit structure of claim 3 , wherein the TSV comprises a Cu pillar.

8. The semiconductor circuit structure of claim 7 , further comprising a conductive pad adjacent a backside of the semiconductor substrate and connected to the TSV.

9. a second shallow trench isolation (STI) region spaced apart from the set of transistors; and a second underground interconnect line within the second STI region and located below the initial semiconductor surface, the second underground interconnect line extending along a second direction different from the first direction; 2. The semiconductor circuit structure of claim 1, wherein said second underground interconnect line is connected to said first underground interconnect line.

10. a second shallow trench isolation (STI) region spaced apart from the set of transistors; and a second underground interconnect line within the second STI region and located below the initial semiconductor surface, the second underground interconnect line extending along a second direction different from the first direction; 2. The semiconductor circuit structure of claim 1, wherein said second underground interconnect line is connected to said first underground interconnect pad.

11. a plurality of metal layers positioned vertically spaced apart from one another over the initial semiconductor surface; a plurality of connection vias overlying the initial semiconductor surface and electrically connected to the plurality of metal layers; 2. The semiconductor circuit structure of claim 1, wherein the first conductive region of a first transistor of the set of transistors is electrically connected to the first underground interconnect pad through the plurality of metal layers and the plurality of connecting vias.

12. a plurality of metal layers positioned vertically spaced apart from one another over the initial semiconductor surface; a plurality of connection vias overlying the initial semiconductor surface and electrically connected to the plurality of metal layers; a second underground interconnect pad located below the initial semiconductor surface; a width of the second underground interconnect pad is greater than a width of the first underground interconnect line; 2. The semiconductor circuit structure of claim 1, wherein said first underground interconnect pad is electrically connected to said second underground interconnect pad through said plurality of metal layers and said plurality of connecting vias.

13. a semiconductor substrate having an initial semiconductor surface; a set of transistors formed on the semiconductor substrate; a first shallow trench isolation (STI) region adjacent to the set of transistors and extending along a first direction; a second shallow trench isolation (STI) region spaced apart from the set of transistors; and a large shallow trench isolation (STI) region spaced apart from the set of transistors; a first underground interconnect line within the first STI region and below the initial semiconductor surface; a second underground interconnect line within the second STI region and below the initial semiconductor surface; a first underground interconnect pad located within the large STI region and below the initial semiconductor surface; the first underground interconnection line extends along the first direction; the second underground interconnection line extends along a second direction different from the first direction; The second underground interconnect line is connected to the first underground interconnect line or the first underground interconnect pad.

14. 14. The semiconductor circuit structure of claim 13, wherein a width of the first underground interconnect pad is greater than a width of the first underground interconnect line.

15. 14. The semiconductor circuit structure of claim 13, wherein the first underground interconnect pad is connected to the first underground interconnect line.

16. a third shallow trench isolation (STI) region spaced apart from the set of transistors; and a third underground interconnect line within the third STI region and below the initial semiconductor surface; the third underground interconnection line extends along the first direction; 14. The semiconductor circuit structure of claim 13, wherein the second underground interconnect line is between the first underground interconnect line and a third underground interconnect line and is connected to the first underground interconnect line and the third underground interconnect line.

17. a semiconductor substrate having an initial semiconductor surface; a set of transistors formed on the semiconductor substrate, each transistor comprising a gate structure, a first conductive region, and a second conductive region; a first shallow trench isolation (STI) region adjacent to the set of transistors and extending along a first direction; a large shallow trench isolation (STI) region spaced apart from the set of transistors; a first underground interconnect line within the first STI region and below the initial semiconductor surface; a first underground interconnect pad electrically coupled to the first underground interconnect line; a through semiconductor via (TSV) in the large STI region and connected to the first underground interconnect pad; the first underground interconnection line extends along the first direction; The semiconductor circuit structure, wherein the first underground interconnect pad is located within the large shallow trench isolation (STI) region and below the initial semiconductor surface.

18. 20. The semiconductor circuit structure of claim 17, wherein the large STI region extends from an edge of the first STI region, and the first underground interconnect pad is directly connected to the first underground interconnect line.

19. 20. The semiconductor circuit structure of claim 18, wherein the TSV extends from a lower surface of the first underground interconnect pad to a back surface of the semiconductor substrate and is configured to transmit power or data signals from the back surface of the semiconductor substrate to the first underground interconnect pad, the back surface facing the initial semiconductor surface.

20. the first conductive region of a first transistor of the set of transistors is electrically connected to the first underground interconnect line through a connection plug located within an active area containing the first transistor; 20. The semiconductor circuit structure of claim 19, wherein the power signal or the data signal is transmitted to the first transistor via the first underground interconnect pad, the first underground interconnect line, and the corresponding connecting plug.

21. 21. The semiconductor circuit structure of claim 20, wherein the connection plug contacts a sidewall of the first underground interconnect line.

22. 20. The semiconductor circuit structure of claim 17, further comprising a conductive pad adjacent a backside of the semiconductor substrate and connected to the TSV.

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