Semiconductor device structure and method of forming the semiconductor device structure

Abstract

To provide a semiconductor device structure that further can effectively miniaturize an integrated circuit and improve performance.SOLUTION: A semiconductor device structure comprises: a semiconductor substrate having an original semiconductor surface and an active region; a shallow trench isolation (STI) region 284 surrounding the active region; a transistor formed based on the active region and comprising a dummy gate structure 280, a first conductive region 3291, a second conductive region 3292, and a channel region between the first and second conductive regions; an underground interconnection (UGI) structure 282 extending beyond the transistor; and a connecting plug 3072 electrically connecting the UGI structure 282 to the first conductive region 3291 of the transistor. The first conductive region 3291 includes an epitaxial semiconductor material. The UGI structure 282 is disposed below the original semiconductor surface and within the STI region 284.SELECTED DRAWING: Figure 22

Description

Detailed Description of the Invention

[0001] [background] <Technical field> The present disclosure relates to semiconductor structures, and more particularly to semiconductor device structures and methods of forming the same.

[0002] <Description of Related Art> In state-of-the-art integrated circuits, many transistors are connected by multiple conductive interconnects (e.g., metal or polysilicon wires), which facilitate signal transmission between the transistor's gate, source, and drain regions (GSDs). All of these conductive interconnects are connected to the GSDs through numerous contact holes and connecting plugs. This poses significant challenges and difficulties to the chip design goals of reducing area, power consumption, noise, and performance, especially as the dimensions of integrated circuits on a die must be significantly reduced to meet the shrinking device dimensions required to satisfy Moore's Law. An example of the area penalty is as follows: The size of the source or drain diffusion region must be designed to be larger than the size of the contact hole used to connect the conductive interconnect to the source or drain region. This design aims to avoid unavoidable photolithographic misalignments resulting from lithography equipment limitations. Photolithographic misalignment causes contact holes to be formed outside the underlying edges of the source or drain regions. This inevitably increases the diffusion area of ​​the transistor and increases the die area. The increased die area results in a large capacitance. This capacitance incurs a large penalty on the AC performance of the circuit, resulting in increased power consumption and noise. How to introduce better self-aligned contact structures and techniques to connect transistors to the first interconnect (metal) layer with the minimum surface area required for signal transmission and reception is a key challenge for further effectively miniaturizing integrated circuits and improving their performance.

[0003] Furthermore, the monolithic integration capabilities of silicon chips have grown from gigascale integration (GSI) (over billions of transistors integrated on a die) to terascale integration (TSI) (trillions of transistors integrated on a die), significantly increasing chip performance. This has led to a rapid increase in the power consumption required to operate such a large number of transistors. Unfortunately, current limited heat dissipation capabilities (e.g., silicon dioxide has very low thermal conductivity, while silicon has relatively low thermal conductivity) increase the junction temperature of the transistors, ultimately increasing the overall chip temperature. This material and device structural problem creates a negative circular effect: increasing die temperature reduces transistor speed. This forces designs to increase the power delivered to the circuit to accelerate transistor performance. However, this mechanism significantly increases die temperature, ultimately exacerbating the heat dissipation problem. In fact, this lack of heat dissipation, which results in increased chip operating temperatures, is considered the most serious problem the entire chip industry must solve to avoid hindering the integration of more devices onto a die. However, progress in reducing GSI chip temperatures has not improved as much as expected. As technology nodes shrink, transistor dimensions inevitably become smaller (e.g., minimum feature sizes shrink from 7 nm to 5 nm, then to 3 nm, and so on), the ratio of oxide film to the total transistor size increases, and the heat dissipation capability of the entire device junction becomes more integrated. Many heat dissipation methods have been developed, such as covering the entire chip with a thermal pad located higher on the outside of the chip or using a liquid cooling system outside the packaged chip. However, both methods are very expensive and inefficient, and cannot effectively reduce the transistor junction temperature.

[0004] [overview] An embodiment of the present disclosure provides a semiconductor device structure. The semiconductor device structure includes a semiconductor substrate having an original semiconductor surface and an active region, a shallow trench isolation (STI) region surrounding the active region, and a transistor formed based on the active region. The transistor includes a gate structure, a first conductive region, a second conductive region, and a channel region located between the first conductive region and the second conductive region. The semiconductor device structure also includes an interconnect structure extending beyond the transistor and a connection plug electrically connecting the interconnect structure to the first conductive region of the transistor. The first conductive region includes epitaxial semiconductor material. The interconnect structure is located below the original semiconductor surface and within the STI region. The connection plug is located within the active region, and the epitaxial semiconductor material of the first conductive region is located above an upper surface of the connection plug. Alternatively, the contact plug is located inside the STI region, and the epitaxial semiconductor material of the first conductive region is connected to the first sidewall of the contact plug.

[0005] According to one aspect of the present disclosure, an interconnect structure is insulated from a semiconductor substrate by an insulating region, the insulating region including a first spacer located on a first side of the interconnect structure and a second spacer located on a second side of the interconnect structure, the first spacer being made of a different material than the second spacer.

[0006] According to one aspect of the present disclosure, the second sidewall of the connection plug is aligned with and in contact with the sidewall of the interconnect.

[0007] According to one aspect of the present disclosure, a semiconductor device structure includes a trench within an active region, and a contact plug located within the trench, the contact plug including titanium nitride (TiN) and tungsten (W).

[0008] According to one aspect of the present disclosure, a semiconductor device structure includes a thin slot within an STI region. A contact plug is located within the thin slot. The contact plug includes a highly doped semiconductor material or TiN. An epitaxial semiconductor material of a first conductive region further exists above a top surface of the contact plug. A second sidewall of the contact plug is located opposite the first sidewall of the contact plug.

[0009] According to one aspect of the present disclosure, the transistor is a fin field-effect transistor (FinFET), a GAA transistor, or a CFET. The STI region has a top surface that is lower than the original semiconductor surface.

[0010] According to one aspect of the present disclosure, the first conductive region includes a selectively epitaxially grown material.

[0011] According to one aspect of the present disclosure, the connection plug is located within the active area, and the first conductive region only extends from a vertical sidewall of the active area that is located directly below the spacer structure covering the gate structure.

[0012] According to one aspect of the present disclosure, the connection plug is located within the STI region, and the first conductive region extends from a vertical sidewall of the active region located directly beneath the spacer structure covering the gate structure and from a horizontal surface of the active region located near a top surface of the STI region.

[0013] According to one aspect of the present disclosure, a semiconductor device structure includes a metal cap (M0) covering a first conductive region.

[0014] An embodiment of the present disclosure provides a semiconductor device structure. The semiconductor device structure includes a semiconductor substrate having an original semiconductor surface and an active region, a shallow trench isolation (STI) region surrounding the active region, and a transistor formed based on the active region. The transistor includes a gate structure, a first conductive region, a second conductive region, and a channel region located between the first conductive region and the second conductive region. The semiconductor device structure includes an interconnect structure extending beyond the transistor. The interconnect structure is located below the original semiconductor surface and within the STI region. The semiconductor device structure includes a connection plug electrically connecting the interconnect structure to the first conductive region of the transistor. The semiconductor device structure includes a metal cap (M0). The metal cap covers the first conductive region and the epitaxial semiconductor material of the connection plug.

[0015] According to one aspect of the present disclosure, an interconnect structure is insulated from a semiconductor substrate by an insulating region, the insulating region including a first spacer located on a first side of the interconnect structure and a second spacer located on a second side of the interconnect structure, the first spacer being made of a different material than the second spacer.

[0016] According to one aspect of the present disclosure, a sidewall of the connection plug is aligned with and in contact with a sidewall of the interconnect structure.

[0017] According to one aspect of the present disclosure, a semiconductor device structure includes a trench within an active region, a contact plug disposed within the trench, and the contact plug includes tungsten.

[0018] According to one aspect of the present disclosure, the transistor is a FinFET, the channel region includes a fin structure, and the STI region has a top surface that is lower than the original semiconductor surface.

[0019] According to one aspect of the present disclosure, the first conductive region includes an epitaxial semiconductor material.

[0020] According to one aspect of the present disclosure, the connection plug is located within the active area, and the first conductive region extends from a vertical sidewall of the fin structure located directly below the spacer structure covering the gate structure and from a horizontal surface of the active area located near a top surface of the STI region.

[0021] According to one aspect of the present disclosure, the transistor is a gate-all-around (GAA) transistor, the channel region includes a plurality of nanosheets, and the STI region has a top surface located below the top surfaces of the plurality of nanosheets.

[0022] According to one aspect of the present disclosure, the first conductive region includes an epitaxial semiconductor material.

[0023] According to one aspect of the present disclosure, the connection plug is located within the active area, and the first conductive region extends from vertical sidewalls of the plurality of nanosheets located directly below the spacer structure covering the gate structure and from a horizontal surface of the active area located near a top surface of the STI region.

[0024] An embodiment of the present disclosure provides a method for forming a semiconductor device structure. The method includes providing a semiconductor substrate having an original surface, forming an active area based on the semiconductor substrate, forming an STI region surrounding the active area, forming a plurality of asymmetric spacers within the STI region, and forming an interconnect structure between the plurality of asymmetric spacers. The interconnect structure is located within the STI region and below the original surface of the semiconductor substrate. The method also includes forming a contact plug in contact with the interconnect layer. The contact plug is located within the active area or within the STI region. The method also includes forming a first conductive region of a transistor based on the active area. The first conductive region is in contact with the contact plug.

[0025] According to one aspect of the present disclosure, the asymmetric spacer includes a first spacer and a second spacer, the first spacer being made of a different material than the second spacer.

[0026] According to one aspect of the present disclosure, the first spacer is made of silicon oxycarbonitride (SiOCN) or nitride, and the second spacer is made of silicon dioxide (SiO2).

[0027] According to one aspect of the present disclosure, the step of forming the connection plug includes: forming a trench within the active area by etching a portion of the active area to expose a first spacer; removing the exposed first spacer based on the trench to expose a sidewall of the interconnect structure; and forming a conductive material within the trench to contact the conductive material with the sidewall of the interconnect structure.

[0028] According to one aspect of the present disclosure, the conductive material includes TiN and tungsten.

[0029] According to one aspect of the present disclosure, the conductive material includes tungsten.

[0030] According to one aspect of the present disclosure, the step of forming the connection plug includes: etching a portion of the active region to expose a top surface of a first spacer, thereby exposing a horizontal surface of the active region located near the top surface of the STI region; removing the first spacer based on the exposed top surface of the first spacer to form a thin slot and expose a sidewall of the interconnect layer; and forming a conductive material inside the thin slot, such that the conductive material contacts the sidewall of the first interconnect layer.

[0031] According to one aspect of the present disclosure, the conductive material includes a highly doped semiconductor material or TiN.

[0032] According to one aspect of the present disclosure, forming an asymmetric spacer includes forming a first spacer covering a sidewall of an active region and a temporary spacer covering a sidewall of another active region adjacent to the first active region. The first spacer and the temporary spacer are located within an STI region. The first spacer and the temporary spacer comprise the same material. Then, forming an asymmetric spacer includes forming a sacrificial layer within the STI region to cover the first spacer and the temporary spacer, removing the sacrificial layer and the temporary spacer to expose the sidewall of the other active region, and forming a second spacer covering the exposed sidewall of the other active region.

[0033] According to one aspect of the present disclosure, the step of forming the second spacer includes oxidizing exposed sidewalls of the other active area.

[0034] According to one aspect of the present disclosure, the step of removing the sacrificial layer and the temporary spacers includes forming a patterned photoresist layer to expose portions of the sacrificial layer and the temporary spacers, and removing the exposed sacrificial layer and the temporary spacers.

[0035] According to one aspect of the present disclosure, the above-mentioned method includes forming a metal cap covering the first conductive region and the connection plug.

[0036] The above-described and other embodiments of the present disclosure will be better understood with regard to the following detailed description of one or more non-limiting embodiments, the following description being made with reference to the accompanying drawings.

[0037] [Brief description of the drawing] 1A-9 illustrate a method for forming an underground interconnect structure within an STI region according to a first process embodiment of the present disclosure.

[0038] 10A-17C illustrate a method for forming an underground interconnect structure within an STI region according to a second process embodiment of the present disclosure.

[0039] 18-22C illustrate a method for electrically connecting an underground interconnect structure to a transistor according to a first connection embodiment of the present disclosure.

[0040] 23-26 illustrate a method for electrically connecting an underground interconnect structure to a transistor according to a second connection embodiment of the present disclosure.

[0041] 27-28 illustrate a method for electrically connecting an underground interconnect structure to a transistor according to a third connection embodiment of the present disclosure.

[0042] 29-37A illustrate a method for electrically connecting an underground interconnect structure to a transistor according to a fourth connection embodiment of the present disclosure.

[0043] 38-48A illustrate a method for electrically connecting an underground interconnect structure to a transistor according to a fifth connection embodiment of the present disclosure.

[0044] 49-57A illustrate a method of electrically connecting an underground interconnect structure to a transistor according to a sixth connection embodiment of the present disclosure.

[0045] [Detailed explanation] Various embodiments will now be described in more detail with reference to the accompanying drawings. These drawings are provided for purposes of illustration and description, and not for purposes of limitation. For clarity, components may not be drawn to scale. Additionally, some components and / or reference numerals may be omitted from some of the drawings. It is contemplated that elements and features in one embodiment may be beneficially incorporated into other embodiments without further description. In the following methods for forming semiconductor device structures, one or more additional operations may be present between the operations described. The order of the operations may be varied. The same or similar reference numerals are used in the drawings to indicate the same or similar elements.

[0046] As used herein and in the appended claims, ordinal numbers such as "first," "second," and the like, used to describe elements, do not imply or represent a particular location, order of placement, or order of manufacture in a structure. Ordinal numbers are used solely to clearly distinguish between multiple elements having the same name. As used herein and in the appended claims, spatial terms such as "on," "above," "over," "upper," "top," "below," "beneath," "under," and "lower" may be used to describe relative spatial or positional relationships between one element or elements and one or more other elements illustrated in the drawings. These spatial or positional relationships may be direct or indirect, unless otherwise specified. Spatial terms are intended to encompass different orientations of a structure in addition to the orientation depicted in the drawings. The structures may be flipped or rotated by various angles and the spatially relative descriptions used herein may be interpreted accordingly.

[0047] Additionally, as used herein and in the claims, the terms "electrically connected" and "electrically coupled" may refer to an electrical current passing through or an operational relationship between elements. An operational relationship may mean, for example, that one element is used to drive another element, although current may not flow directly between the two elements.

[0048] This disclosure focuses on underground interconnection (UGI) structures within semiconductor substrates for signal transmission or heat dissipation applications. Signal transmission includes power signal transmission and data signal transmission. The UGI structures can be fabricated using a monolithic process for fabricating transistors. For example, the transistors can be fin field-effect transistors (FinFETs), gate-all-around (GAA) transistors, complementary FETs (CFETs), or planar transistors. The underground interconnection structures can be underground interconnection lines (UGI lines) or underground interconnection pads (UGI pads).

[0049] [Formation of UGI structure below the original semiconductor surface]

[0050] <Embodiment 1 of the First Process>

[0051] 1A-9 illustrate an exemplary method for fabricating a UGI structure according to a first embodiment of the present disclosure.

[0052] FIG. 1A shows a schematic top view of a structure at a certain stage of a manufacturing method. FIG. 1B shows a schematic cross-sectional view of the structure at that stage, taken along line BB′ in FIG. 1A. FIG. 1C shows a schematic cross-sectional view of the structure at that stage, taken along line CC′ in FIG. 1A. Referring to FIGS. 1A-1C, a pad-oxide layer 1204 and a pad-nitride layer 1206 are formed by a deposition process to define an active area. Portions of a semiconductor substrate 1202 located outside the active area are removed. The semiconductor substrate 1202 may include or be made of a semiconductor material such as silicon. An oxide layer is then formed by a deposition process, and an etch-back process is performed on the oxide layer to form shallow trench isolation (STI) regions 1214. The STI regions 1214 may surround the active area.

[0053] FIG. 2A shows a schematic top view of a structure at a certain stage of a fabrication process. FIG. 2B shows a schematic cross-sectional view of the structure at that stage, taken along line BB′ in FIG. 2A. FIG. 2C shows a schematic cross-sectional view of the structure at that stage, taken along line CC′ in FIG. 2A. Referring to FIGS. 2A-2C, a thermal oxide layer 1205 is grown along exposed sidewalls of the active region. The thermal oxide layer 1205 may be formed by oxidizing the exposed sidewalls of the active region. The thermal oxide layer 1205 may have a length of approximately 89 nm to 200 nm along the Z direction. The thermal oxide layer 1205 may have a thickness of approximately 2.5 nm along the Y direction. Depending on the pitch of the active regions, the distance between the thermal oxide layers 1205 in different active regions along the Y direction may be approximately 13 nm. The top surface of the thermal oxide layer 1205 may be lower in the Z direction than the top surface of the pad oxide layer 1204 and the bottom surface of the pad nitride layer 1206. Part of the STI region 1214 may be exposed. Alternatively, the bottom of the STI region 1214 may be covered by the thermal oxide layer 1205. At this stage, the part of the thermal oxide layer 1205 located to the left of the active area can be considered a temporary spacer. And the other part of the thermal oxide layer 1205 located to the right (opposite side) of the active area can be considered a second spacer.

[0054] FIG. 3A shows a schematic top view of the structure at a certain stage of the fabrication process. FIG. 3B shows a schematic cross-sectional view of the structure at that stage, taken along line BB′ in FIG. 3A. FIG. 3C shows a schematic cross-sectional view of the structure at that stage, taken along line CC′ in FIG. 3A. Referring to FIGS. 3A-3C, SOD material 1207 fills the spaces between the active areas through a deposition process. A planarization process, such as a chemical-mechanical planarization (CMP) process, can be performed to remove portions of SOD material 1207 above pad nitride layer 1206, making the top surfaces of SOD material 1207 and pad nitride layer 1206 coplanar. SOD material 1207 can be considered a sacrificial layer. SOD material 1207 may cover the second spacers and temporary spacers described in FIGS. 2A-2C.

[0055] FIG. 4A shows a schematic top view of the structure at a certain stage of the fabrication process. FIG. 4B shows a schematic cross-sectional view of the structure at that stage, taken along line BB' in FIG. 4A. FIG. 4C shows a schematic cross-sectional view of the structure at that stage, taken along line CC' in FIG. 4A. Referring to FIGS. 4A-4C, a photoresist layer 1306 is formed. The photoresist layer 1306 is patterned to cover a portion of the active area and to expose a portion of the SOD material 1207. More than half of the active area may be covered by the photoresist layer 1306.

[0056] FIG. 5A shows a schematic top view of the structure at a certain stage of the fabrication process. FIG. 5B shows a schematic cross-sectional view of the structure at that stage, taken along line BB′ in FIG. 5A. FIG. 5C shows a schematic cross-sectional view of the structure at that stage, taken along line CC′ in FIG. 5A. Referring to FIGS. 5A-5C, a narrow slot is formed by removing a portion of the SOD material 1207 not covered by the photoresist layer 1306 and the thermal oxide layer 1205 (i.e., temporary spacer) covered by the portion of the SOD material 1207. The narrow slot is formed between the remaining SOD material 1207 and the active area. The narrow slot may have a width of 2 nm to 6 nm (e.g., 3 nm) along the Y direction. After removing the portion of the SOD material 1207 not covered by the photoresist layer 1306 and the underlying thermal oxide layer 1205, one sidewall of the active area is exposed within the narrow slot.

[0057] FIG. 6A shows a schematic top view of the structure at a certain stage of the fabrication process. FIG. 6B shows a schematic cross-sectional view of the structure at that stage, taken along line BB′ in FIG. 6A. FIG. 6C shows a schematic cross-sectional view of the structure at that stage, taken along line CC′ in FIG. 6A. Referring to FIGS. 6A-6C, photoresist layer 1306 is removed, and a material (e.g., SiOCN) 1209 different from thermal oxide layer 1205 is formed inside the narrow slot by a deposition process. A planarization process, such as a CMP process, can be performed to remove portions of SiOCN material 1209 above pad nitride layer 1206 and SOD material 1207, making the top surfaces of SiOCN material 1209, SOD material 1207, and pad nitride layer 1206 coplanar. Therefore, an asymmetric spacer including different materials (e.g., a thermal oxide layer 1205 and an SiOCN material 1209) is formed inside the STI region 1214. From another perspective, the asymmetric spacer covers two sidewalls of the active region, respectively. The SiOCN material 1209 can be considered a first spacer. The asymmetric spacer can include a first spacer and a second spacer.

[0058] FIG. 7A shows a schematic top view of a structure at a certain stage of a manufacturing method. FIG. 7B shows a schematic cross-sectional view of the structure at that stage, taken along line BB′ in FIG. 7A. FIG. 7C shows a schematic cross-sectional view of the structure at that stage, taken along line CC′ in FIG. 7A. Referring to FIGS. 7A-7C, the SOD material 1207 is removed to form a space between the thermal oxide layer 1205 and the SiOCN material 1209. Conductive layers (such as a TiN layer 1303 and a tungsten layer 1305) are then sequentially formed in the space by a deposition process. An etch-back process is then performed to remove a portion of the TiN layer 1303 and a portion of the tungsten layer 1305. After the etch-back process, the remaining tungsten layer 1305 can be defined as an underground interconnect (UGI) structure. The remaining TiN layer 1303 can be defined as a barrier layer. The TiN layer 1303 is present between the tungsten layer 1305 and the thermal oxide layer 1205. The TiN layer 1303 is also present between the tungsten layer 1305 and the SiOCN material 1209. The TiN layer 1303 is also present between the tungsten layer 1305 and the STI region 1214. The distance between the top surface of the thermal oxide layer 1205 and the top surface of the tungsten layer 1305 along the Z direction can be 39 nm to 150 nm. The distance between the top surface of the tungsten layer 1305 and the top surface of the STI region 1214 along the Z direction can be 50 nm to 150 nm. The thickness of the STI region 1214 along the Z direction can be 20 nm to 50 nm.

[0059] FIG. 8A shows a schematic top view of the structure at a certain stage of the fabrication method. FIG. 8B shows a schematic cross-sectional view of the structure at that stage, taken along line BB′ in FIG. 8A. FIG. 8C shows a schematic cross-sectional view of the structure at that stage, taken along line CC′ in FIG. 8A. Referring to FIGS. 8A-8C, a SiN layer 1307 and a high-density plasma (HDP) oxide layer 1309 are sequentially formed above a tungsten layer 1305 and a TiN layer 1303. This results in STI regions located between multiple active areas. In this way, an underground wiring structure within the STI regions is provided. FIG. 9 shows a three-dimensional schematic view of the structure. Fabrication steps for forming transistors within the active areas may be performed after the stages shown in FIGS. 8A-8C.

[0060] <Embodiment 2 of the process>

[0061] 10A to 17C illustrate a method for fabricating an underground interconnect structure inside an STI region according to a second embodiment of the present disclosure.

[0062] FIG. 10A shows a schematic top view of a structure at a certain stage of a manufacturing method, and FIG. 10B shows a schematic cross-sectional view of the structure at that stage, taken along line BB′ in FIG. 10A . FIG. 10C shows a schematic cross-sectional view of the structure at that stage, taken along line CC′ in FIG. 10A . Referring to FIGS. 10A-10C , a pad-oxide layer 2204 and a pad-nitride layer 2206 are formed by a deposition process to define an active area. Portions of a semiconductor substrate 2202 located outside the active area are removed. The semiconductor substrate 2202 may include or be made of a semiconductor material such as silicon. Next, an oxide layer is formed by a deposition process, and an etch-back process is performed on the oxide layer to form shallow trench isolation (STI) regions 2214. The STI regions 2214 may surround the active area. The width of the pad nitride layer 2206 along the Y direction may be 12 nm. The distance between two adjacent active areas along the Y direction may be 18 nm. The distance between the bottom surface of the pad oxide layer 2204 and the top surface of the STI region 2214 along the Z direction may be 150 nm to 200 nm.

[0063] FIG. 11A shows a schematic top view of a structure at a certain stage of a manufacturing method. FIG. 11B shows a schematic cross-sectional view of the structure at that stage, taken along line BB′ in FIG. 11A. FIG. 11C shows a schematic cross-sectional view of the structure at that stage, taken along line CC′ in FIG. 11A. Referring to FIGS. 11A-11C, SiOCN material 2209 is formed along the sidewalls of semiconductor substrate 2202, pad oxide layer 2204, pad nitride layer 2206, and a top surface of pad nitride layer 2206 by a deposition process. The thickness of SiOCN material 2209 along the Y direction may be 4 nm. The distance D23 between the sidewalls of SiOCN material 2209 along the Y direction may be 10 nm. Next, a portion of STI region 2214 is exposed. At this stage, a portion of SiOCN material 2209 located to the right of the active region can be considered a temporary spacer. Another part of the SiOCN material 2209 located on the left side (opposite the right side) of this active region can be considered to be a first spacer.

[0064] FIG. 12A shows a schematic top view of a structure at a certain stage of a manufacturing method. FIG. 12B shows a schematic cross-sectional view of the structure at that stage, taken along line BB′ in FIG. 12A. FIG. 12C shows a schematic cross-sectional view of the structure at that stage, taken along line CC′ in FIG. 12A. Referring to FIGS. 12A-12C, SOD material 2207 fills spaces between active areas through a deposition process. A planarization process, such as a CMP process, can be performed to remove portions of SOD material 2207 above pad nitride layer 2206, making the top surfaces of SOD material 2207 and pad nitride layer 2206 coplanar. SOD material 2207 can be considered a sacrificial layer. SOD material 2207 may cover the first spacers and temporary spacers described in FIGS. 11A-11C.

[0065] FIG. 13A shows a schematic top view of the structure at a certain stage of the fabrication process. FIG. 13B shows a schematic cross-sectional view of the structure at that stage, taken along line BB′ in FIG. 13A. FIG. 13C shows a schematic cross-sectional view of the structure at that stage, taken along line CC′ in FIG. 13A. Referring to FIGS. 13A-13C, a photoresist layer 2306 is formed. The photoresist layer 2306 is patterned to cover a portion of the active area and to expose a portion of the SOD material 2207 and a portion of the SiOCN material 2209 (i.e., the temporary spacer). For example, more than half of the active area may be covered by the photoresist layer 2306.

[0066] FIG. 14A shows a schematic top view of the structure at a certain stage of the fabrication process, and FIG. 14B shows a schematic cross-sectional view of the structure at that stage, taken along line BB′ in FIG. 14A. FIG. 14C shows a schematic cross-sectional view of the structure at that stage, taken along line CC′ in FIG. 14A. Referring to FIGS. 14A-14C, the portions of SiOCN material 2209 not covered by photoresist layer 2306 (i.e., temporary spacers) and SOD material 2207 have been removed, and photoresist layer 2306 has been removed. Slots 2210 have been formed between the remaining SiOCN material 2209 and the active areas. After the removal, one sidewall of each active area is exposed within slot 2210.

[0067] FIG. 15A shows a schematic top view of a structure at a certain stage of a fabrication method. FIG. 15B shows a schematic cross-sectional view of the structure at that stage, taken along line BB′ in FIG. 15A. FIG. 15C shows a schematic cross-sectional view of the structure at that stage, taken along line CC′ in FIG. 15A. Referring to FIGS. 15A-15C, a thermal oxide layer 2205 is grown along the exposed sidewalls of the active area and within the slots 2210. The thermal oxide layer 2205 may be formed by oxidizing the exposed sidewalls of the active area. In the Z direction, the upper surface of the thermal oxide layer 2205 may be lower than the upper surface of the pad oxide layer 2204 and the lower surface of the pad nitride layer 2206. In this way, an asymmetric spacer including different materials (e.g., the thermal oxide layer 2205 and the SiOCN material 2209) is formed within the STI region 2214. From another perspective, the asymmetric spacer covers two sidewalls of each active area (or covers two sidewalls of each STI area). The thermal oxide layer 2205 can be considered to be a second spacer. The asymmetric spacer can include a first spacer and a second spacer.

[0068] FIG. 16A shows a schematic top view of a structure at a certain stage of a manufacturing method. FIG. 16B shows a schematic cross-sectional view of the structure at that stage, taken along line BB′ in FIG. 16A , and FIG. 16C shows a schematic cross-sectional view of the structure at that stage, taken along line CC′ in FIG. 16A . Referring to FIGS. 16A-16C , a deposition process sequentially forms a TiN layer 2303 and a tungsten layer 2305 inside the slot 2210, and then an etch-back process is performed to remove a portion of the TiN layer 2303 and a portion of the tungsten layer 2305. After the etch-back process, a photolithography process is performed to divide the TiN layer 2303 and the tungsten layer 2305 into a plurality of remaining TiN layers 2303 and remaining tungsten layers 2305. The remaining tungsten layers 2305 may be defined as underground interconnect (UGI) structures. The remaining TiN layer 2303 can then be defined as a barrier layer.

[0069] FIG. 17A shows a schematic top view of a structure at a certain stage of a fabrication method. FIG. 17B shows a schematic cross-sectional view of the structure at that stage, as shown along line BB′ in FIG. 17A. FIG. 17C shows a schematic cross-sectional view of the structure at that stage, as shown along line CC′ in FIG. 17A. Referring to FIGS. 17A-17C, a SiN layer 2307 and a HDP (high density plasma) oxide layer 2309 are sequentially formed above the tungsten layer 2305 and the TiN layer 2303. Thus, a structure including an underground interconnect structure within the STI region is provided. Fabrication steps for forming transistors within the active region may be performed after the stages shown in FIGS. 17A-17C.

[0070] The method illustrated in FIGS. 1A-17C provides an underground interconnect structure (e.g., tungsten layer 1305 shown in FIG. 8C and tungsten layer 2305 shown in FIG. 17C) located below the original semiconductor surface and within the STI region. The UGI structure may extend along the STI region. The UGI structure is insulated from the semiconductor substrate. If desired, some UGI structures may be electrically connected to transistors. In one embodiment, the UGI structure may be electrically connected to the source or drain terminal of a transistor by a self-aligned or self-construction method through a connection plug located within the active area housing the transistor. Forming multiple asymmetric spacers (e.g., thermal oxide layer 1205 and SiOCN material 1209 shown in FIG. 8C and thermal oxide layer 2205 and SiOCN material 2209 shown in FIG. 17C ) along the sidewalls of the active area and forming a UGI structure between the multiple asymmetric spacers and below the original semiconductor surface are important in this disclosure. The UGI structure located inside the semiconductor substrate can form a UGI mesh that extends to other preliminary STI regions or large STI regions away from the active area of ​​the semiconductor substrate. The UGI mesh may be understood as a middle-side signal delivery network ("Mid-side Signal Network") and / or a heat dissipation network. The use of a UGI mesh inside a chip or semiconductor substrate can provide greater misalignment tolerance due to the large STI regions that have more space for signal routing. The use of a UGI mesh can shorten the path connecting the backside TSV to the UGI mesh and improve IR drop in signal transmission. And the use of UGI mesh can enhance heat dissipation and improve the above-mentioned drawbacks in ICs mainly formed by transistors.

[0071] [UGI structure and electrical connection with fin field-effect transistors]

[0072] In the following description, a FinFET is used as an example to describe a method for electrically connecting a UGI structure to a source or drain terminal of a transistor. The source or drain terminal of a FinFET may be formed by a selective epitaxy growth process. The techniques described herein are also applicable to the electrical connection between a UGI structure and the source / drain terminals of a GAA transistor, a CFET, or a planar transistor (the source / drain terminals of a planar transistor may be formed by an ion implantation process).

[0073] <First Connection Embodiment>

[0074] 18-22C illustrate a method of electrically connecting an underground interconnect structure to a transistor according to this embodiment of the present disclosure. In some embodiments, the fabrication steps illustrated with reference to FIGS. 18-22C may be performed after the fabrication steps illustrated with reference to FIGS. 1A-9 or after the fabrication steps illustrated with reference to FIGS. 10A-17C.

[0075] FIG. 18 shows a three-dimensional schematic diagram of a structure at a certain stage of a manufacturing method. FIG. 18A shows a schematic cross-sectional view of the structure taken along line AA in FIG. 18. FIG. 18B shows a schematic cross-sectional view of the structure taken along line BB in FIG. 18. FIG. 18C shows a schematic cross-sectional view of the structure taken along line CC in FIG. 18. Referring to FIGS. 18-18C, after forming a structure including a UGI structure 282 protected by an asymmetric spacer 283 within an STI region 284, a dummy gate structure 280 (or, in some cases, a real gate structure) and a spacer structure 281 covering the dummy gate structure 280 are formed according to a standard foundry process. A portion of the active region (or fin structure) located outside the spacer structure 281 and above an upper surface 284U of the STI region 284 is then exposed. The dummy gate structure 280 may include a cap nitride layer 2804, a cap oxide layer 2801, a semiconductor layer 2802, and a high-k dielectric layer 2803, stacked along the Z direction. The semiconductor layer 2802 may be located between the cap oxide layer 2801 and the high-k dielectric layer 2803. The cap oxide layer 2801 may include an oxide. The semiconductor layer 2802 may include a semiconductor material such as polycrystalline silicon. The high-k dielectric layer 2803 may include a dielectric material having a high dielectric constant. The spacer structure 281 may be a composite of a first spacer material 2811 and a second spacer material 2812 different from the first spacer material 2811. In some embodiments, the first spacer material 2811 may be an oxide, and the second spacer material 2812 may be a nitride. The spacer structure 281 may cover opposing sidewalls of the dummy gate structure 280. UGI structure 282 may be any conductive material (e.g., tungsten layer 1305 shown in FIG. 8C or tungsten layer 2305 shown in FIG. 17C). STI region 284 may be STI region 1214 shown in FIG. 8C or STI region 2214 shown in FIG. 17C.The asymmetric spacer 283 includes a first spacer 2831 covering a first side of the UGI structure 282 and a second spacer 2832 covering a second side of the UGI structure 282. The first side of the UGI structure 282 is opposite the second side of the UGI structure 282. The material of the first spacer 2831 is different from the material of the second spacer 2832. The first spacer 2831 and the second spacer 2832 may be alternately arranged along the Y direction. The first spacer 2831 may be the SiOCN material 1209 shown in FIG. 8C or the SiOCN material 2209 shown in FIG. 17C. The second spacer 2832 may be the thermal oxide layer 1205 shown in FIG. 8C or the thermal oxide layer 2205 shown in FIG. 17C.

[0076] Next, the exposed portion of the active area and other fin structures made of silicon located below the exposed portion of the active area (below the upper surface 284U of the STI region 284) are removed by an etching process. As a result, a trench 285 is formed, exposing the asymmetric spacer 283 described above. The vertical sidewall of the active area, which has a (110) crystal orientation and is located directly below the spacer structure 281 covering the dummy gate structure 280, is also exposed. The trench 285 is located inside the active area.

[0077] 19A-19C are schematic cross-sectional views of a structure at different stages of the fabrication process, obtained by cutting the structure at different angles. The cross-sectional views of FIG. 18A and FIG. 19A are taken at approximately the same angle and in approximately the same location. The cross-sectional views of FIG. 18B and FIG. 19B are taken at approximately the same angle and in approximately the same location. The cross-sectional views of FIG. 18C and FIG. 19C are taken at approximately the same angle and in approximately the same location. Referring to FIGS. 19A-19C, a thermal oxide layer 296 is formed at the bottom of the trench 285 by a thermal oxidation process. The vertical sidewalls of the active region, which have a (110) crystal orientation, are also oxidized. Next, a first spacer 2831, one of the multiple asymmetric spacers 283 exposed by the trench 285, is removed by an etching process, exposing the sidewalls of the UGI structure 282. Second spacers 2832 are left in place (as shown in FIG. 19B). In some embodiments, if nitride spacers (e.g., TiN layer 1303 shown in FIG. 8C or TiN layer 2303 shown in FIG. 17C) are used, the nitride spacers are removed along with first spacers 2831. Thermal oxide layer 296 can include silicon dioxide (SiO2).

[0078] 20A-20C are schematic cross-sectional views of a structure at a certain stage of a manufacturing process, obtained by cutting the structure at different angles. The cross-sectional views of FIG. 18A and FIG. 20A are taken at approximately the same angle and in approximately the same position. The cross-sectional views of FIG. 18B and FIG. 20B are taken at approximately the same angle and in approximately the same position. The cross-sectional views of FIG. 18C and FIG. 20C are taken at approximately the same angle and in approximately the same position. Referring to FIGS. 20A-20C, a TiN film 3071 and a conductive film 3072 are formed inside the trench 285 by an atomic layer deposition process. The TiN film 3071 may be formed on the top surface and sidewalls of the thermal oxide layer 296. The conductive film 3072 may be formed on the top surface and sidewalls of the TiN film 3071. The TiN film 3071 may be present between the conductive film 3072 and the thermal oxide layer 296. The TiN film 3071 and the conductive film 3072 may form a connection plug 307 for electrically connecting the exposed sidewall of the UGI structure 282. As shown in FIG. 20B, the connection plug 307 may be in contact with the exposed sidewall of the UGI structure 282. The conductive film 3072 may include or be made of a conductive material such as tungsten (W). The connection plug 307 is formed within the active area. A portion of the thermal oxide layer 296 is covered by the connection plug 307. Meanwhile, as shown in FIG. 20C, another portion of the thermal oxide layer 296 is exposed.

[0079] 21A-21C are schematic cross-sectional views of a structure at various stages in the fabrication process, obtained by cutting the structure at different angles. The cross-sectional views of FIG. 18A and FIG. 21A are taken at approximately the same angle and in approximately the same location. The cross-sectional views of FIG. 18B and FIG. 21B are taken at approximately the same angle and in approximately the same location. The cross-sectional views of FIG. 18C and FIG. 21C are taken at approximately the same angle and in approximately the same location. Referring to FIGS. 21A-21C, the exposed portions of thermal oxide layer 296 are removed by an etching process, exposing portions of the vertical sidewalls of the active area having a (110) crystal orientation.

[0080] FIG. 22 shows a three-dimensional schematic diagram of a structure at a certain stage of a fabrication method. FIG. 22A shows a schematic cross-sectional view of the structure taken along line AA in FIG. 22. FIG. 22B shows a schematic cross-sectional view of the structure taken along line BB in FIG. 22. FIG. 22C shows a schematic cross-sectional view of the structure taken along line CC in FIG. 22. Referring to FIGS. 22-22C, based on exposed portions of the vertical sidewalls of the active region having a (110) crystal orientation, a selective epitaxy growth (SEG) process forms a first lightly doped region 3281, a second lightly doped region 3282, a first conductive region (or first heavily doped region) 3291, and a second conductive region (or second heavily doped region) 3292. The exposed portions of the vertical sidewalls of the active region may be located directly below the spacer structure 281. A first lightly doped region 3281 and a second lightly doped region 3282 may be formed on the exposed portions of the vertical sidewalls of the active region and below the spacer structure 281. The first lightly doped region 3281 may be in contact with the first conductive region 3291. The second lightly doped region 3282 may be in contact with the second conductive region 3292. The first conductive region 3291 is connected to (or brought into contact with) the connection plug 307. The connection plug 307 is then connected to the UGI structure 282. Thus, the UGI structure 282 is electrically connected to the first conductive region 3291 via the connection plug 307. The second conductive region 3292 is connected to (or brought into contact with) the connection plug 307. The connection plug 307 is then connected to the UGI structure 282. Therefore, the UGI structure 282 is electrically connected to the second conductive region 3292 via the connection plug 307. The first lightly doped region 3281 and the second lightly doped region 3282 may include a doped semiconductor material (e.g., N-type silicon). The first conductive region 3291 and the second conductive region 3292 may also include a doped semiconductor material (e.g., N-type silicon).The first conductive region 3291 and the second conductive region 3292 may be highly doped. The first conductive region 3291 may function as one of the source and drain of the FinFET. The second conductive region 3292 may function as the other of the source and drain of the FinFET. In one embodiment, after forming the structure shown in FIG. 22 , a conventional gate-last process may be performed to replace the dummy gate structure 280 with the gate structure of the FinFET to complete the formation of the FinFET. The FINFET may include a channel region defined between the drain and the source.

[0081] <Second Connection Embodiment>

[0082] 23-26 illustrate a method of electrically connecting an underground interconnect structure to a transistor according to this embodiment of the present disclosure. In some embodiments, the fabrication steps illustrated with reference to FIGS. 23-26 may be performed after the fabrication steps illustrated with reference to FIGS. 1A-9 or after the fabrication steps illustrated with reference to FIGS. 10A-17C.

[0083] FIG. 23 shows a three-dimensional schematic diagram of a structure at a certain stage of the manufacturing method of the present invention. FIG. 23A shows a schematic cross-sectional view of the structure taken along line AA in FIG. 23. FIG. 23B shows a schematic cross-sectional view of the structure taken along line BB in FIG. 23. FIG. 23C shows a schematic cross-sectional view of the structure taken along line CC in FIG. 23. Referring to FIGS. 23-23C, after forming a structure including a UGI structure 332 protected by an asymmetric spacer 333 within an STI region 334, a dummy gate structure 330 and a spacer structure 331 covering the sidewall of the dummy gate structure 330 are formed using a standard foundry process. Then, a portion of the active region (or fin structure) located outside the spacer structure 331 and above an upper surface 334U of the STI region 334 is exposed. The dummy gate structure 330 may include a cap nitride layer 3304, a cap oxide layer 3301, a semiconductor layer 3302, and a high-k dielectric layer 3303, stacked along the Z direction. The cap oxide layer 3301 may include an oxide. The semiconductor layer 3302 may include a semiconductor material such as polycrystalline silicon. The high-k dielectric layer 3303 may include a dielectric material having a high dielectric constant. The spacer structure 331 may be a composite of a first spacer material 3311 and a second spacer material 3312 different from the first spacer material 3311, similar to the spacer structure 281 described in FIG. 18 . Therefore, details of the spacer structure 331 will be omitted. The UGI structure 332 may be a tungsten layer 1305 with a TiN layer, as shown in FIG. 8C or FIG. 17C . The STI region 334 may be the STI region 1214 shown in Fig. 8C or the STI region 2214 shown in Fig. 17C. The asymmetric spacer 333 includes a first spacer 3331 located on a first side of the UGI structure 332 and a second spacer 3332 located on a second side of the UGI structure 332, similar to the asymmetric spacer 283 shown in Fig. 18. Therefore, details of the asymmetric spacer 333 will be omitted.

[0084] Next, the exposed active area above the upper surface 334U of the STI region 334 is removed by an etching process. As a result, the horizontal surface of the active area having a (100) crystal orientation located near the upper surface 334U of the STI region 334 is exposed. Also, the vertical sidewall of the active area having a (110) crystal orientation located directly below the spacer structure 331 covering the dummy gate structure 330 is exposed. The upper surface of the first spacer 3331 is also exposed. The horizontal surface of the active area having a (100) crystal orientation may be located lower than the upper surface 334U of the STI region 334 and higher than the upper surface of the UGI structure 332 in the Z direction.

[0085] 24A-24C are schematic cross-sectional views of a structure at a certain stage of the fabrication process, taken at different angles. The cross-sectional views of FIG. 23A and FIG. 24A are taken at approximately the same angle and at approximately the same location. The cross-sectional views of FIG. 23B and FIG. 24B are taken at approximately the same angle and at approximately the same location. The cross-sectional views of FIG. 23C and FIG. 24C are taken at approximately the same angle and at approximately the same location. Referring to FIGS. 24A-24C, based on the exposed top surface of the first spacer 3331, the first spacer 3331 covering the dummy gate structure 330 outside the spacer structure 331 is removed by an etching process. As a result, a shallow slot 345 is formed inside the STI region 334, and the sidewall of the UGI structure 332 is exposed. The second spacer 3332 remains (see FIG. 24B). In one embodiment, if nitride spacers (e.g., TiN layer 1303 shown in FIG. 8C or TiN layer 2303 shown in FIG. 17C) are used, the nitride spacers are removed along with first spacer 3331, exposing a portion of the fin structure within thin slot 345.

[0086] FIG. 25 shows a three-dimensional schematic view of a structure at a stage of a fabrication method. FIG. 25A shows a schematic cross-sectional view of the structure along line AA shown in FIG. 25. FIG. 25B shows a schematic cross-sectional view of the structure along line BB shown in FIG. 25. FIG. 25C shows a schematic cross-sectional view of the structure along line CC shown in FIG. 25. Referring to FIGS. 25-25C, a contact plug 3595 is formed within the shallow slot 345 by an atomic layer deposition process. The contact plug 3595 may contact the exposed sidewall of the UGI structure 332. The contact plug 3595 may be formed within the STI region 334 along the sidewall of the active area. The contact plug 3595 may comprise a conductive material, such as titanium nitride, formed by atomic layer deposition (ALD).

[0087] Next, a first lightly doped semiconductor region 3581, a second lightly doped semiconductor region 3582, a first heavily doped semiconductor region 3591, and a second heavily doped semiconductor region 3592 are formed by a selective epitaxy growth (SEG) process based on the exposed horizontal surfaces of the active region having a (100) crystal orientation and the exposed vertical sidewalls of the active region having a (110) crystal orientation. The first lightly doped semiconductor region 3581 and the second lightly doped semiconductor region 3582 may be formed on the exposed horizontal surfaces of the active region having a (100) crystal orientation and on the exposed vertical sidewalls of the active region having a (110) crystal orientation. The first lightly doped semiconductor region 3581 and the second lightly doped semiconductor region 3582 may be in contact with the horizontal surfaces and the vertical sidewalls. The first heavily doped semiconductor region 3591 may be in contact with the first lightly doped semiconductor region 3581. The second heavily doped semiconductor region 3592 may be in contact with the second lightly doped semiconductor region 3582. The UGI structure 332 is electrically connected to the first heavily doped semiconductor region 3591. In another example, the UGI structure 332 is electrically connected to the second heavily doped semiconductor region 3592. The first lightly doped semiconductor region 3581 and the second lightly doped semiconductor region 3582 may comprise a doped semiconductor material (e.g., N-type silicon). The first heavily doped semiconductor region 3591 and the second heavily doped semiconductor region 3592 may comprise a heavily doped semiconductor material. In some embodiments, after forming the structure shown in FIG. 25 , a conventional gate-last process may be performed to replace the dummy gate structure 330 with a gate structure comprising a FinFET to complete the formation of the FinFET. In one embodiment, cap nitride layer 3304, cap oxide layer 3301, semiconductor layer 3302, and high-k dielectric layer 3303 are removed and replaced with gate dielectric material 3601 and gate conductive material 3602 to form a gate structure for a FinFET, as shown in Figure 26. The FINFET may include a channel region defined between a drain and a source.

[0088] <Third Connection Embodiment>

[0089] 27-28 illustrate a method of electrically connecting an underground interconnect structure to a transistor according to this embodiment of the present disclosure. In some embodiments, the fabrication steps illustrated with reference to Figures 27-28 may be performed after the fabrication steps illustrated with reference to Figures 24A-24C.

[0090] Figure 27 shows a three-dimensional schematic view of a structure at a stage in the manufacturing process, with Figure 27A showing a schematic cross-sectional view of the structure taken along line AA shown in Figure 27, Figure 27B showing a schematic cross-sectional view of the structure taken along line BB shown in Figure 27, and Figure 27C showing a schematic cross-sectional view of the structure taken along line CC shown in Figure 27.

[0091] Next, based on the exposed horizontal surfaces of the active region having a (100) crystal orientation and the exposed vertical sidewalls of the active region having a (110) crystal orientation, a selective epitaxial growth (SEG) process is used to form first lightly doped semiconductor region 3581, second lightly doped semiconductor region 3582, first heavily doped semiconductor region 3591, and second heavily doped semiconductor region 3592. During the formation of first heavily doped semiconductor region 3591, a connecting plug 3795 grown by SEG using a heavily doped semiconductor material may also be formed inside thin slot 345.

[0092] The first heavily doped semiconductor region 3591 and the connection plug 3795 are electrically connected to each other. Thus, the UGI structure 332 is electrically connected to the first heavily doped semiconductor region 3591 via the connection plug 3795. After the formation of the structure shown in FIG. 27, the formation of the FinFET can be completed by performing a conventional gate-last process, shown in FIG. 28, to replace the dummy gate structure 330 with the gate structure of the FinFET. Details of the FinFET are described in FIG. 26.

[0093] <Fourth Connection Embodiment>

[0094] 29-37A illustrate a method of electrically connecting an underground interconnect structure to a transistor according to this embodiment of the present disclosure. In some embodiments, the fabrication steps illustrated with reference to FIGS. 29-37A may be performed after the fabrication steps illustrated with reference to FIGS. 1A-9 or after the fabrication steps illustrated with reference to FIGS. 10A-17C.

[0095] FIG. 29 shows a three-dimensional schematic diagram of a structure at a certain stage of the fabrication process. After forming a structure including a UGI structure 392 protected by an asymmetric spacer 393 within an STI region 394, a dummy gate structure 390 and a spacer structure 391 covering the sidewall of the dummy gate structure 390 are formed based on a standard foundry process. A portion of the active region (or fin structure) is then exposed outside the spacer structure 391. The structure of the dummy gate structure 390 may be similar to the structure of the dummy gate structure 280 or the structure of the dummy gate structure 330. The spacer structure 391 may be similar to the spacer structure 281 or the spacer structure 331. The UGI structure 392 may be the tungsten layer 1305 with a TiN layer, as shown in FIG. 8C or FIG. 17C. The STI region 394 may be the STI region 1214 shown in FIG. 8C or the STI region 2214 shown in FIG. 17C. The asymmetric spacer 393 includes a first spacer 3931 located on a first side of the UGI structure 392 and a second spacer 3932 located on a second side of the UGI structure 392. The first spacer 3931 may be the SiOCN material 1209 shown in FIG. 8C or the SiOCN material 2209 shown in FIG. 17C. The second spacer 3932 may be the thermal oxide layer 1205 shown in FIG. 8C or the thermal oxide layer 2205 shown in FIG. 17C. The thickness of the spacer structure 391 in the X direction may be greater than the thickness of the spacer structure 281 and the thickness of the spacer structure 331. The width of the spacer structure 391 in the Y direction may be determined by the position of the UGI structure 392. Next, as shown in FIG. 29 , the active area not covered by the dummy gate structure 390 and the spacer structure 391 is partially removed.

[0096] FIG. 30 shows a three-dimensional schematic diagram of the structure at a stage of fabrication. A lithographic patterning photomask 405 is formed over a first portion of the exposed active area. A second portion of the exposed active area (the second portion not covered by the lithographic patterning photomask 405, located below the upper surface 394U of the STI region 394, and made of silicon) is removed by an etching process to form a trench 406 within the active area. In this embodiment, the first and second exposed portions of the active area may be located on opposite sides of the dummy gate structure 390 in the X direction. The asymmetric spacer 393 is exposed by the trench 406. The vertical sidewalls of the active area, which have a (110) crystal orientation, are located below the spacer structure 391. The horizontal surfaces of the active area, which have a (100) crystal orientation, are exposed by the trench 406.

[0097] 31 shows a three-dimensional schematic diagram illustrating the structure at a stage in the fabrication process: A thermal oxidation process forms a thermal oxide layer 416 at the bottom of the trench 406 (i.e., on the horizontal surfaces of the active area having a (100) crystal orientation) and on the vertical sidewalls of the active area having a (110) crystal orientation located directly below the spacer structure 391.

[0098] FIG. 32 shows a three-dimensional schematic diagram of the structure at a certain stage of the fabrication process. A first spacer 3931, one of the asymmetric spacers 393 exposed by the trench 406, is removed by an etching process to expose the sidewall of the UGI structure 392. The second spacer 3932 remains. After the sidewall of the UGI structure 392 is exposed, a contact plug 427 is formed inside the trench 406 to connect the exposed sidewall of the UGI structure 392. In one embodiment, the contact plug 427 can include a TiN film and a conductive film. The conductive film can include or be made of tungsten (W). In this example, the contact plug 427, which is self-aligned to the UGI structure 392, is formed inside the active region.

[0099] 33 shows a three-dimensional schematic view of the structure at a stage in the fabrication process. Portions of the thermal oxide layer 416 covering the vertical sidewalls of the active area having a (110) crystal orientation are removed by an etching process, exposing portions of the vertical sidewalls of the active area that lie above the upper surfaces 394U of the STI regions 394.

[0100] FIG. 34 shows a three-dimensional schematic view of the structure at a stage in the fabrication process. The lithography patterning photomask 405 has been removed. By reducing the thickness of the spacer structure 391 in the X-direction, a spacer structure 441 may be formed based on electrical performance requirements and the UGI process window. Outside the spacer structure 441, an excess portion 448 of the fin structure is exposed. In another embodiment, the spacer structure 441 is not formed by thinning the spacer structure 391. In another embodiment, the spacer structure 391 is removed, and then the spacer structure 441 is formed using a low-k dielectric material.

[0101] 35 shows a three-dimensional schematic diagram of the structure at a certain stage of the manufacturing method. The excess portion 448 of the fin structure (which may be made of silicon) may be removed by an anisotropic etching process. The horizontal surface of the active region having a (100) crystal orientation located near the upper surface 394U of the STI region 394 and the vertical sidewall of the active region having a (110) crystal orientation located directly below the spacer structure 441 are exposed. The exposed vertical sidewall of the active region may be slightly recessed relative to the surface of the spacer structure 441.

[0102] 36 shows a three-dimensional schematic diagram of the structure at a certain stage of the fabrication method. Based on the exposed horizontal surfaces of the active region having a (100) crystal orientation and the exposed vertical sidewalls of the active region having a (110) crystal orientation located directly below the spacer structure 441, a first lightly doped region 4681, a second lightly doped region 4682, a first conductive region (or a first highly doped semiconductor region) 4691, and a second conductive region (or a second highly doped semiconductor region) 4692 are formed by a selective epitaxial growth (SEG) process, completing the formation of the source and drain of the FinFET. Thus, the UGI structure 392 is electrically connected to the first conductive region 4691 via the connection plug 427.

[0103] FIG. 37 shows a three-dimensional schematic diagram of the structure at a certain stage of the fabrication process. FIG. 37A shows a schematic cross-sectional view of the structure, taken along line AA in FIG. 37. The dummy gate structure 390 is replaced with a real gate structure 470 of the FinFET. For example, the real gate structure 470 of the FinFET may be a high-k metal gate (HKMG) structure. To further connect the first conductive region 4691 to the connection plug 427, a metal cap (M0) 475 covering the first conductive region 4691 may be formed by a conventional metal zero (M0) layer process, thereby reducing contact resistance. In this manner, a conventional FinFET having the connection plug 427 to the UGI structure 392 is completed. The FINFET may include a channel region defined between the drain and source. The metal cap 475 may include a titanium nitride (TiN) layer and a tungsten (W) layer overlying the titanium nitride layer.

[0104] <Fifth Connection Embodiment>

[0105] 38-48A illustrate methods of electrically connecting an underground interconnect structure to a transistor according to embodiments of the present disclosure. In some embodiments, the fabrication steps illustrated with reference to FIGS. 38-48A may be performed after the fabrication steps illustrated with reference to FIGS. 1A-9 or after the fabrication steps illustrated with reference to FIGS. 10A-17C.

[0106] FIG. 38 shows a three-dimensional schematic diagram of a structure at a certain stage of a fabrication method. After forming a structure including a UGI structure 482 protected by an asymmetric spacer 483 within an STI region 484, a dummy gate structure 480 and a spacer structure 481 covering the sidewall of the dummy gate structure 480 are formed based on a standard foundry process. Then, a portion of the active region (or fin structure) is partially removed outside the spacer structure 481. The structure of the dummy gate structure 480 may be similar to the structure of the dummy gate structure 280 or the structure of the dummy gate structure 330. The structure of the spacer structure 481 may be similar to the structure of the spacer structure 281 or the structure of the spacer structure 331. The UGI structure 482 may be the tungsten layer 1305 shown in FIG. 8C or the tungsten layer 2305 shown in FIG. 17C. 8C or 2214 shown in FIG. 17C. The asymmetric spacer 483 includes a first spacer 4831 located on a first side of the UGI structure 482 and a second spacer 4832 located on a second side of the UGI structure 482. A bottom surface 480B of the dummy gate structure 480 in the STI region 484 is located at a lower position than an upper surface 484U of the STI region 484.

[0107] 39 shows a three-dimensional schematic diagram of the structure at a stage of the fabrication process. A lithographic patterning photomask 495 is formed to cover a first portion of the exposed active area. A second portion of the exposed active area (not covered by the lithographic patterning photomask 495, located below the upper surface 484U of the STI region 484, and made of silicon) is further etched down by an etching process. As a result, a trench 496 is formed within the active area. The asymmetric spacer 483 is exposed by the trench 496. The vertical sidewalls of the active area, which have a (110) crystal orientation, and the horizontal surfaces of the active area, which have a (100) crystal orientation, are exposed by the trench 496.

[0108] 40 shows a three-dimensional schematic view of the structure at a stage in the fabrication process. A thermal oxidation process forms a thermal oxide layer 506 on the bottom of the trench 496 (i.e., on the horizontal surfaces of the active area having a (100) crystal orientation) and on the vertical sidewalls of the active area having a (110) crystal orientation located directly below the spacer structure 481.

[0109] FIG. 41 shows a three-dimensional schematic diagram of the structure at a certain stage of the fabrication method. A first spacer 4831, one of the asymmetric spacers 483 exposed by the trench 496, is removed by an etching process to expose the sidewall of the UGI structure 482. The second spacer 4832 remains. After the sidewall of the UGI structure 482 is exposed, a contact plug 517 is formed inside the trench 496 to connect the exposed sidewall of the UGI structure 482. In one embodiment, the contact plug 517 can include a TiN film and a conductive film. The conductive film can include or be made of tungsten (W).

[0110] 42 is a three-dimensional schematic diagram of the structure at a stage in the fabrication process. Portions of the thermal oxide layer 506 covering the vertical sidewalls of the active area having a (110) crystal orientation are removed by an etching process, exposing portions of the vertical sidewalls of the active area that are located above the top surface 484U of the STI region 484.

[0111] FIG. 43 is a three-dimensional schematic diagram of a structure at a stage in a fabrication process. The lithography patterning photomask 495 is removed. To form the structure shown in FIG. 43, the spacer structures 481 located opposite the dummy gate structure 480 may be removed. In the structure shown in FIG. 43, the excess portion 538 of the fin structure located outside the dummy gate structure 480 is exposed. A recess 539 is formed within the STI region 484. The sidewalls of the dummy gate structure 480 and the excess portion 538 may be exposed by the recess 539. The recess 539 may be located opposite the dummy gate structure 480. In another embodiment, the thickness of the removed spacer structures 481 in the X-direction may be reduced to form thinner spacer structures to redefine the length of the channel region based on electrical performance requirements and the UGI process window.

[0112] 44 shows a three-dimensional schematic view of the structure at a stage in the fabrication method. A deposition process and an etch-back process may form a dielectric element 549 within the recess 539. The top surface of the dielectric element 549 may be aligned with the top surface 484U of the STI region 484. The top surface of the dielectric element 549 may be coplanar with the top surface 484U of the STI region 484.

[0113] 45 shows a three-dimensional schematic view of the structure at a stage in the fabrication process. Spacer structures 551 are formed on opposing sidewalls of dummy gate structure 480 and on dielectric element 549 to redefine the length of the channel region based on electrical performance requirements and UGI process window. Spacer structures 551 may cover opposing sidewalls of dummy gate structure 480. Spacer structures 551 may include or be fabricated from a low-k dielectric material.

[0114] 46 shows a three-dimensional schematic view of the structure at a certain stage of the fabrication method. Portions of the fin structure (which may be made of silicon and are not covered by the spacer structures 551) may be removed by an anisotropic etching process, exposing horizontal surfaces of the active area having a (100) crystal orientation located near the top surfaces 484U of the STI regions 484 and vertical sidewalls of the active area having a (110) crystal orientation located directly below the spacer structures 551.

[0115] FIG. 47 shows a three-dimensional schematic diagram of the structure at a certain stage of the fabrication method. A selective epitaxy growth (SEG) process forms a first lightly doped region 5781, a second lightly doped region 5782, a first conductive region (or a first highly doped semiconductor region) 5791, and a second conductive region (or a second highly doped semiconductor region) 5792 based on the exposed horizontal surfaces of the active region having a (100) crystal orientation and the exposed vertical sidewalls of the active region having a (110) crystal orientation located directly below the spacer structure 551. This completes the formation of the source and drain of the FinFET, as described above. The first conductive region 5791 is connected to (or in contact with) the connection plug 517. The connection plug 517 is then connected to the UGI structure 482. Thus, the UGI structure 482 is electrically connected to the first conductive region 5791 via the connection plug 517.

[0116] FIG. 48 shows a three-dimensional schematic diagram of the structure at a certain stage of the fabrication process. FIG. 48A shows a schematic cross-sectional view of the structure, taken along line AA in FIG. 48. The dummy gate structure 480 has been replaced with a FinFET real gate structure 580. For example, the FinFET real gate structure 580 may be a high-k metal gate (HKMG). A bottom 580B of the gate structure 580 in the STI region 484 is located lower than the bottoms of the first conductive region 5791 and the second conductive region 5792. To further connect the first conductive region 5791 and the connection plug 517, a metal cap (M0) 585 covering the first conductive region 5791 may be formed by a conventional metal zero (M0) layer process, thereby reducing contact resistance. In this way, a conventional FinFET having a connection plug 517 for the UGI structure 482 is completed.

[0117] <Sixth connection form>

[0118] In the following description, a GAA transistor is used as an example to describe how to electrically connect the UGI structure to the source or drain terminal of the transistor. The source or drain terminal of the GAA transistor may be formed by a selective epitaxy growth process.

[0119] 49-57A illustrate a method for electrically connecting an underground interconnect structure to a transistor according to embodiments of the present disclosure. In some embodiments, the fabrication steps illustrated with reference to FIGS. 49-57A may be performed after the fabrication steps illustrated with reference to FIGS. 1A-9 or after the fabrication steps illustrated with reference to FIGS. 10A-17C. The method in this embodiment differs from the methods in the previous embodiments in that it includes exposing vertical sidewalls of semiconductor nanosheets located underneath spacer structures of a GAA transistor (as shown in FIGS. 49-55) rather than exposing vertical sidewalls of fin structures located underneath spacer structures of a FinFET transistor (e.g., FIGS. 27-33).

[0120] FIG. 49 shows a three-dimensional schematic diagram of a structure at a certain stage of the fabrication process. After forming a structure including a UGI structure 592 protected by an asymmetric spacer 593 within an STI region 594, a dummy gate structure 590 on a nanosheet stack 595 and a spacer structure 591 covering the sidewall of the dummy gate structure 590 are formed based on a standard foundry process. A portion of the active region located outside the spacer structure 591 is then partially removed. The nanosheet stack 595 includes semiconductor nanosheets 5951 and sacrificial nanosheets 5952 alternately stacked along the Z direction. The material of the semiconductor nanosheet 5951 may be different from the material of the sacrificial nanosheet 5952. The semiconductor nanosheet 5951 may include or be made of a semiconductor material such as silicon. The sacrificial nanosheet 5952 may include or be made of silicon germanium (SiGe). Nanosheet stack 595 may be formed by an epitaxial growth process. In the structure shown in FIG. 49 , the vertical sidewalls of semiconductor nanosheet 5951 located below spacer structure 591 are exposed. The exposed vertical sidewalls of semiconductor nanosheet 5951 may have a (110) crystal orientation. Dummy gate structure 590 may have a structure similar to that of dummy gate structure 280 or dummy gate structure 330. Spacer structure 591 may not cover the top surface of dummy gate structure 590. Spacer structure 591 may have a structure similar to that of spacer structure 281 or spacer structure 331. UGI structure 592 may be tungsten layer 1305 with a TiN layer as shown in FIG. 8C or tungsten layer 2305 with a TiN layer as shown in FIG. 17C. STI region 594 may be STI region 1214 shown in FIG. 8C or may be STI region 2214 shown in FIG. 17C.As described above, the asymmetric spacer 593 includes a first spacer 5931 located on a first side of the UGI structure 592 and a second spacer 5932 located on a second side of the UGI structure 592. The nanosheet stack 595, the dummy gate structure 590, and the spacer structure 591 may be located above an upper surface 594U of the STI region 594.

[0121] FIG. 50 is a three-dimensional schematic diagram illustrating a structure at a stage of fabrication. A lithographic patterning photomask 605 is formed to cover a first portion of the exposed active area. A second portion of the exposed active area (not covered by the lithographic patterning photomask 605, located below the upper surface 594U of the STI region 594, and made of silicon) is further etched down by an etching process, thereby forming a trench 606 within the active area. The asymmetric spacer 593 is exposed by the trench 606. The vertical sidewalls of the active area, which are located below the spacer structure 591 and have a (110) crystal orientation, are exposed. Finally, the horizontal surfaces of the active area, which have a (100) crystal orientation, are exposed by the trench 606.

[0122] 51 shows a three-dimensional schematic view of the structure at a stage in the fabrication process. A thermal oxidation process forms thermal oxide layer 616 at the bottom of trench 606 (i.e., on the horizontal surfaces of the active area), on the sidewalls of trench 606 (i.e., on the vertical sidewalls of the active area directly underneath spacer structure 591), and on the exposed vertical sidewalls of semiconductor nanosheet 5951 directly underneath spacer structure 591.

[0123] 52 shows a three-dimensional schematic view of the structure at a stage in the fabrication process. One of the asymmetric spacers 593 exposed by trench 606, a first spacer 5931, is removed by an etching process to expose the sidewall of UGI structure 592. Second spacer 5932 remains. After the sidewall of UGI structure 592 is exposed, a contact plug 627 is formed inside trench 606 to connect the exposed sidewall of UGI structure 592.

[0124] 53 shows a three-dimensional schematic view of the structure at a stage in the fabrication process. A portion of the thermal oxide layer 616 covering the vertical sidewall of the semiconductor nanosheet 5951 located directly below the spacer structure 591 is removed by an etching process. As a result, the vertical sidewall of the semiconductor nanosheet 5951 located directly below the spacer structure 591 and having a (110) crystal orientation is exposed.

[0125] FIG. 54 shows a three-dimensional schematic diagram of the structure at a certain stage of the fabrication method. The lithography patterning photomask 605 is removed. By reducing the X-direction thickness of the spacer structure 591, a spacer structure 641 may be formed based on the electrical performance requirements and the UGI process window. Thus, an excess portion 648 of the semiconductor nanosheet 5951 is exposed outside the spacer structure 641. At this stage, the sacrificial nanosheet 5952 located between the semiconductor nanosheets 5951 may be removed. In another embodiment, the spacer structure 641 is not formed by thinning the spacer structure 591. In another embodiment, the spacer structure 641 is formed by removing the spacer structure 591 and then using a low-k dielectric material.

[0126] 55 is a three-dimensional schematic diagram of the structure at a certain stage of the fabrication method. An anisotropic etching process may remove excess portion 648 of semiconductor nanosheet 5951. Thus, the horizontal surface of the active region having a (100) crystal orientation, located near upper surface 594U of STI region 594, and the vertical sidewall of semiconductor nanosheet 5951 having a (110) crystal orientation, located directly below spacer structure 641, are exposed. The exposed vertical sidewall of semiconductor nanosheet 5951 may be slightly recessed relative to the surface of spacer structure 641.

[0127] Figure 56 is a three-dimensional schematic diagram of the structure at a certain stage of the fabrication method. Based on the exposed horizontal surfaces of the active region having a (100) crystal orientation and the exposed vertical sidewalls of the semiconductor nanosheet 5951 having a (110) crystal orientation, a first lightly doped region 6681, a second lightly doped region 6682, a first conductive region (or a first highly doped semiconductor region) 6691, and a second conductive region (or a second highly doped semiconductor region) 6692 are formed by the selective epitaxy (SEG) process described above. In this way, the formation of the source and drain of the GAA transistor is completed. The first lightly doped region 6681 and the second lightly doped region 6682 may be formed on the exposed vertical sidewalls of the semiconductor nanosheet 5951. The first lightly doped region 6681 and the second lightly doped region 6682 may be in contact with the exposed vertical sidewalls of the semiconductor nanosheet 5951. The first conductive region 6691 may be formed on a sidewall of the first lightly doped region 6681. The second conductive region 6692 may be formed on a sidewall of the second lightly doped region 6682. The first conductive region is connected to (or in contact with) the connection plug 627. The connection plug 627 is connected to the UGI structure 592. Thus, the UGI structure 592 is electrically connected to the first conductive region 6691. The first conductive region 6691 may function as one of the source and drain of a GAA transistor. The second conductive region 6692 may function as the other of the source and drain of the GAA transistor.

[0128] FIG. 57 shows a three-dimensional schematic diagram of the structure at a certain stage of the fabrication process. FIG. 57A shows a schematic cross-sectional view of the structure, taken along line AA in FIG. 57. The dummy gate structure 590 is replaced with a GAA transistor gate structure 670. For example, the GAA transistor gate structure 670 may be a high-k metal gate (HKMG) structure. To further connect the first conductive region 6691 to the connection plug 627, a metal cap (M0) 675 covering the first conductive region 6691 may be formed by a conventional metal zero (M0) layer process, thereby reducing contact resistance. In this way, a conventional GAA transistor having a connection plug 627 for the UGI structure 592 is completed.

[0129] An intermediate-side signal transmission network in an integrated circuit can be realized by an underground interconnect structure and connection plugs (located inside an active area or along a sidewall of an active area) connecting the underground interconnect structure to transistors (such as planar transistors, FinFETs, GAA transistors, or complementary FETs (CFETs)) of the integrated circuit. The underground interconnect structure and connection of the underground interconnect structure according to the present disclosure can free up layout space for conventional metal layers located above the original semiconductor surface, simplify the layout for conventional metal layers located above the original semiconductor surface, and reduce IR drop for signal transmission. Furthermore, backside signal transmission can be effectively realized for a semiconductor circuit chip based on the underground interconnect structure and connection of the underground interconnect structure to transistors of the integrated circuit according to the present disclosure.

[0130] Furthermore, when the underground interconnect structure located inside the STI region includes a heat dissipation material having a thermal conductivity higher than that of Si or SiO2, the underground interconnect structure and the connection of the underground interconnect structure according to the present disclosure can be applied to a heat dissipation network. In particular, the underground interconnect structure located inside the semiconductor substrate extends away from the active region toward other spare areas (pre-areas) or large STI regions. Thermal vias may be disposed above the other spare areas or large STI regions. Alternatively, through-silicon vias may be disposed below the other spare areas or large STI regions.

[0131] It should be noted that the above-described structures and methods are provided for illustrative purposes. The present disclosure should not be limited to the structures and procedures (approaches) disclosed above. Other embodiments having different configurations of known elements are applicable, and the illustrated structures can be adjusted and modified based on the practical needs of actual applications. Of course, it should be noted that the configurations in the figures are drawn for illustrative purposes only, and not for limiting purposes. Therefore, it is known to those skilled in the art that the relevant elements and layers in a semiconductor structure, the shape or positional relationship of elements, and the details of procedures can be adjusted or modified according to the practical requirements and / or manufacturing steps of an actual application.

[0132] While the present disclosure has been described in terms of one or more exemplary embodiment(s) for illustrative purposes, it is to be understood that the present disclosure is not limited to these examples. To the contrary, the present disclosure is intended to cover various modifications and similar arrangements and procedures. The scope of the appended claims, therefore, should be accorded the broadest interpretation so as to encompass all such modifications and similar arrangements and procedures. [Brief explanation of the drawings]

[0133] [Figure 1A]1 illustrates a method for forming an underground interconnect structure inside an STI region according to a first process embodiment of the present disclosure. [Figure 1B] 1 illustrates a method for forming an underground interconnect structure inside an STI region according to a first process embodiment of the present disclosure. [Figure 1C] 1 illustrates a method for forming an underground interconnect structure inside an STI region according to a first process embodiment of the present disclosure. [Figure 2A] 1 illustrates a method for forming an underground interconnect structure inside an STI region according to a first process embodiment of the present disclosure. [Figure 2B] 1 illustrates a method for forming an underground interconnect structure inside an STI region according to a first process embodiment of the present disclosure. [Figure 2C] 1 illustrates a method for forming an underground interconnect structure inside an STI region according to a first process embodiment of the present disclosure. [Figure 3A] 1 illustrates a method for forming an underground interconnect structure inside an STI region according to a first process embodiment of the present disclosure. [Figure 3B] 1 illustrates a method for forming an underground interconnect structure inside an STI region according to a first process embodiment of the present disclosure. [Figure 3C] 1 illustrates a method for forming an underground interconnect structure inside an STI region according to a first process embodiment of the present disclosure. [Figure 4A] 1 illustrates a method for forming an underground interconnect structure inside an STI region according to a first process embodiment of the present disclosure. [Figure 4B] 1 illustrates a method for forming an underground interconnect structure inside an STI region according to a first process embodiment of the present disclosure. [Figure 4C] 1 illustrates a method for forming an underground interconnect structure inside an STI region according to a first process embodiment of the present disclosure. [Figure 5A] 1 illustrates a method for forming an underground interconnect structure inside an STI region according to a first process embodiment of the present disclosure. [Figure 5B] 1 illustrates a method for forming an underground interconnect structure inside an STI region according to a first process embodiment of the present disclosure. [Figure 5C] 1 illustrates a method for forming an underground interconnect structure inside an STI region according to a first process embodiment of the present disclosure. [Figure 6A] 1 illustrates a method for forming an underground interconnect structure inside an STI region according to a first process embodiment of the present disclosure. [Figure 6B] 1 illustrates a method for forming an underground interconnect structure inside an STI region according to a first process embodiment of the present disclosure. [Figure 6C] 1 illustrates a method for forming an underground interconnect structure inside an STI region according to a first process embodiment of the present disclosure. [Figure 7A] 1 illustrates a method for forming an underground interconnect structure inside an STI region according to a first process embodiment of the present disclosure. [Figure 7B] 1 illustrates a method for forming an underground interconnect structure inside an STI region according to a first process embodiment of the present disclosure. [Figure 7C] 1 illustrates a method for forming an underground interconnect structure inside an STI region according to a first process embodiment of the present disclosure. [Figure 8A] 1 illustrates a method for forming an underground interconnect structure inside an STI region according to a first process embodiment of the present disclosure. [Figure 8B] 1 illustrates a method for forming an underground interconnect structure inside an STI region according to a first process embodiment of the present disclosure. [Figure 8C]1 illustrates a method for forming an underground interconnect structure inside an STI region according to a first process embodiment of the present disclosure. [Figure 9] 1 illustrates a method for forming an underground interconnect structure inside an STI region according to a first process embodiment of the present disclosure. [Figure 10A] 10 illustrates a method for forming an underground interconnect structure inside an STI region according to a second process embodiment of the present disclosure. [Figure 10B] 10 illustrates a method for forming an underground interconnect structure inside an STI region according to a second process embodiment of the present disclosure. [Figure 10C] 10 illustrates a method for forming an underground interconnect structure inside an STI region according to a second process embodiment of the present disclosure. [Figure 11A] 10 illustrates a method for forming an underground interconnect structure inside an STI region according to a second process embodiment of the present disclosure. [Figure 11B] 10 illustrates a method for forming an underground interconnect structure inside an STI region according to a second process embodiment of the present disclosure. [Figure 11C] 10 illustrates a method for forming an underground interconnect structure inside an STI region according to a second process embodiment of the present disclosure. [Figure 12A] 10 illustrates a method for forming an underground interconnect structure inside an STI region according to a second process embodiment of the present disclosure. [Figure 12B] 10 illustrates a method for forming an underground interconnect structure inside an STI region according to a second process embodiment of the present disclosure. [Figure 12C] 10 illustrates a method for forming an underground interconnect structure inside an STI region according to a second process embodiment of the present disclosure. [Figure 13A] 10 illustrates a method for forming an underground interconnect structure inside an STI region according to a second process embodiment of the present disclosure. [Figure 13B] 10 illustrates a method for forming an underground interconnect structure inside an STI region according to a second process embodiment of the present disclosure. [Figure 13C] 10 illustrates a method for forming an underground interconnect structure inside an STI region according to a second process embodiment of the present disclosure. [Figure 14A] 10 illustrates a method for forming an underground interconnect structure inside an STI region according to a second process embodiment of the present disclosure. [Figure 14B] 10 illustrates a method for forming an underground interconnect structure inside an STI region according to a second process embodiment of the present disclosure. [Figure 14C] 10 illustrates a method for forming an underground interconnect structure inside an STI region according to a second process embodiment of the present disclosure. [Figure 15A] 10 illustrates a method for forming an underground interconnect structure inside an STI region according to a second process embodiment of the present disclosure. [Figure 15B] 10 illustrates a method for forming an underground interconnect structure inside an STI region according to a second process embodiment of the present disclosure. [Figure 15C] 10 illustrates a method for forming an underground interconnect structure inside an STI region according to a second process embodiment of the present disclosure. [Figure 16A] 10 illustrates a method for forming an underground interconnect structure inside an STI region according to a second process embodiment of the present disclosure. [Figure 16B] 10 illustrates a method for forming an underground interconnect structure inside an STI region according to a second process embodiment of the present disclosure. [Figure 16C] 10 illustrates a method for forming an underground interconnect structure inside an STI region according to a second process embodiment of the present disclosure. [Figure 17A]10 illustrates a method for forming an underground interconnect structure inside an STI region according to a second process embodiment of the present disclosure. [Figure 17B] 10 illustrates a method for forming an underground interconnect structure inside an STI region according to a second process embodiment of the present disclosure. [Figure 17C] 10 illustrates a method for forming an underground interconnect structure inside an STI region according to a second process embodiment of the present disclosure. [Figure 18] 1 illustrates a method for electrically connecting an underground interconnect structure to a transistor according to a first connection embodiment of the present disclosure. [Figure 18A] 1 illustrates a method for electrically connecting an underground interconnect structure to a transistor according to a first connection embodiment of the present disclosure. [Figure 18B] 1 illustrates a method for electrically connecting an underground interconnect structure to a transistor according to a first connection embodiment of the present disclosure. [Figure 18C] 1 illustrates a method for electrically connecting an underground interconnect structure to a transistor according to a first connection embodiment of the present disclosure. [Figure 19A] 1 illustrates a method for electrically connecting an underground interconnect structure to a transistor according to a first connection embodiment of the present disclosure. [Figure 19B] 1 illustrates a method for electrically connecting an underground interconnect structure to a transistor according to a first connection embodiment of the present disclosure. [Figure 19C] 1 illustrates a method for electrically connecting an underground interconnect structure to a transistor according to a first connection embodiment of the present disclosure. [Figure 20A] 1 illustrates a method for electrically connecting an underground interconnect structure to a transistor according to a first connection embodiment of the present disclosure. [Figure 20B] 1 illustrates a method for electrically connecting an underground interconnect structure to a transistor according to a first connection embodiment of the present disclosure. [Figure 20C] 1 illustrates a method for electrically connecting an underground interconnect structure to a transistor according to a first connection embodiment of the present disclosure. [Figure 21A] 1 illustrates a method for electrically connecting an underground interconnect structure to a transistor according to a first connection embodiment of the present disclosure. [Figure 21B] 1 illustrates a method for electrically connecting an underground interconnect structure to a transistor according to a first connection embodiment of the present disclosure. [Figure 21C] 1 illustrates a method for electrically connecting an underground interconnect structure to a transistor according to a first connection embodiment of the present disclosure. [Figure 22] 1 illustrates a method for electrically connecting an underground interconnect structure to a transistor according to a first connection embodiment of the present disclosure. [Figure 22A] 1 illustrates a method for electrically connecting an underground interconnect structure to a transistor according to a first connection embodiment of the present disclosure. [Figure 22B] 1 illustrates a method for electrically connecting an underground interconnect structure to a transistor according to a first connection embodiment of the present disclosure. [Figure 22C] 1 illustrates a method for electrically connecting an underground interconnect structure to a transistor according to a first connection embodiment of the present disclosure. [Figure 23] 1 illustrates a method for electrically connecting an underground interconnect structure to a transistor according to a second connection embodiment of the present disclosure. [Figure 23A] 1 illustrates a method for electrically connecting an underground interconnect structure to a transistor according to a second connection embodiment of the present disclosure. [Figure 23B] 1 illustrates a method for electrically connecting an underground interconnect structure to a transistor according to a second connection embodiment of the present disclosure. [Figure 23C]1 illustrates a method for electrically connecting an underground interconnect structure to a transistor according to a second connection embodiment of the present disclosure. [Figure 24A] 1 illustrates a method for electrically connecting an underground interconnect structure to a transistor according to a second connection embodiment of the present disclosure. [Figure 24B] 1 illustrates a method for electrically connecting an underground interconnect structure to a transistor according to a second connection embodiment of the present disclosure. [Figure 24C] 1 illustrates a method for electrically connecting an underground interconnect structure to a transistor according to a second connection embodiment of the present disclosure. [Figure 25] 1 illustrates a method for electrically connecting an underground interconnect structure to a transistor according to a second connection embodiment of the present disclosure. [Figure 25A] 1 illustrates a method for electrically connecting an underground interconnect structure to a transistor according to a second connection embodiment of the present disclosure. [Figure 25B] 1 illustrates a method for electrically connecting an underground interconnect structure to a transistor according to a second connection embodiment of the present disclosure. [Figure 25C] 1 illustrates a method for electrically connecting an underground interconnect structure to a transistor according to a second connection embodiment of the present disclosure. [Figure 26] 1 illustrates a method for electrically connecting an underground interconnect structure to a transistor according to a second connection embodiment of the present disclosure. [Figure 27] 10 illustrates a method of electrically connecting an underground interconnect structure to a transistor according to a third connection embodiment of the present disclosure. [Figure 27A] 10 illustrates a method of electrically connecting an underground interconnect structure to a transistor according to a third connection embodiment of the present disclosure. [Figure 27B] 10 illustrates a method of electrically connecting an underground interconnect structure to a transistor according to a third connection embodiment of the present disclosure. [Figure 27C] 10 illustrates a method of electrically connecting an underground interconnect structure to a transistor according to a third connection embodiment of the present disclosure. [Figure 28] 10 illustrates a method of electrically connecting an underground interconnect structure to a transistor according to a third connection embodiment of the present disclosure. [Figure 29] 10 illustrates a method of electrically connecting an underground interconnect structure to a transistor according to a fourth connection embodiment of the present disclosure. [Figure 30] 10 illustrates a method of electrically connecting an underground interconnect structure to a transistor according to a fourth connection embodiment of the present disclosure. [Figure 31] 10 illustrates a method of electrically connecting an underground interconnect structure to a transistor according to a fourth connection embodiment of the present disclosure. [Figure 32] 10 illustrates a method of electrically connecting an underground interconnect structure to a transistor according to a fourth connection embodiment of the present disclosure. [Figure 33] 10 illustrates a method of electrically connecting an underground interconnect structure to a transistor according to a fourth connection embodiment of the present disclosure. [Figure 34] 10 illustrates a method of electrically connecting an underground interconnect structure to a transistor according to a fourth connection embodiment of the present disclosure. [Figure 35] 10 illustrates a method of electrically connecting an underground interconnect structure to a transistor according to a fourth connection embodiment of the present disclosure. [Figure 36] 10 illustrates a method of electrically connecting an underground interconnect structure to a transistor according to a fourth connection embodiment of the present disclosure. [Figure 37] 10 illustrates a method of electrically connecting an underground interconnect structure to a transistor according to a fourth connection embodiment of the present disclosure. [Figure 37A]10 illustrates a method of electrically connecting an underground interconnect structure to a transistor according to a fourth connection embodiment of the present disclosure. [Figure 38] 10 illustrates a method of electrically connecting an underground interconnect structure to a transistor according to a fifth connection embodiment of the present disclosure. [Figure 39] 10 illustrates a method of electrically connecting an underground interconnect structure to a transistor according to a fifth connection embodiment of the present disclosure. [Figure 40] 10 illustrates a method of electrically connecting an underground interconnect structure to a transistor according to a fifth connection embodiment of the present disclosure. [Figure 41] 10 illustrates a method of electrically connecting an underground interconnect structure to a transistor according to a fifth connection embodiment of the present disclosure. [Figure 42] 10 illustrates a method of electrically connecting an underground interconnect structure to a transistor according to a fifth connection embodiment of the present disclosure. [Figure 43] 10 illustrates a method of electrically connecting an underground interconnect structure to a transistor according to a fifth connection embodiment of the present disclosure. [Figure 44] 10 illustrates a method of electrically connecting an underground interconnect structure to a transistor according to a fifth connection embodiment of the present disclosure. [Figure 45] 10 illustrates a method of electrically connecting an underground interconnect structure to a transistor according to a fifth connection embodiment of the present disclosure. [Figure 46] 10 illustrates a method of electrically connecting an underground interconnect structure to a transistor according to a fifth connection embodiment of the present disclosure. [Figure 47] 10 illustrates a method of electrically connecting an underground interconnect structure to a transistor according to a fifth connection embodiment of the present disclosure. [Figure 48] 10 illustrates a method of electrically connecting an underground interconnect structure to a transistor according to a fifth connection embodiment of the present disclosure. [Figure 48A] 10 illustrates a method of electrically connecting an underground interconnect structure to a transistor according to a fifth connection embodiment of the present disclosure. [Figure 49] 10 illustrates a method of electrically connecting an underground interconnect structure to a transistor according to a sixth connection embodiment of the present disclosure. [Figure 50] 10 illustrates a method of electrically connecting an underground interconnect structure to a transistor according to a sixth connection embodiment of the present disclosure. [Figure 51] 10 illustrates a method of electrically connecting an underground interconnect structure to a transistor according to a sixth connection embodiment of the present disclosure. [Figure 52] 10 illustrates a method of electrically connecting an underground interconnect structure to a transistor according to a sixth connection embodiment of the present disclosure. [Figure 53] 10 illustrates a method of electrically connecting an underground interconnect structure to a transistor according to a sixth connection embodiment of the present disclosure. [Figure 54] 10 illustrates a method of electrically connecting an underground interconnect structure to a transistor according to a sixth connection embodiment of the present disclosure. [Figure 55] 10 illustrates a method of electrically connecting an underground interconnect structure to a transistor according to a sixth connection embodiment of the present disclosure. [Figure 56] 10 illustrates a method of electrically connecting an underground interconnect structure to a transistor according to a sixth connection embodiment of the present disclosure. [Figure 57] 10 illustrates a method of electrically connecting an underground interconnect structure to a transistor according to a sixth connection embodiment of the present disclosure. [Figure 57A] 10 illustrates a method of electrically connecting an underground interconnect structure to a transistor according to a sixth connection embodiment of the present disclosure.

Claims

1. 1. A semiconductor device structure comprising: a semiconductor substrate having an original semiconductor surface and an active region; a shallow trench isolation (STI) region surrounding the active area; a transistor formed based on the active region; an interconnect structure extending beyond the transistor; a connection plug; The transistor is A gate structure; a first conductive region; a second conductive region; a channel region located between the first conductive region and the second conductive region, the first conductive region includes an epitaxial semiconductor material; the interconnect structure is disposed below the original semiconductor surface and within the STI region; the connecting plug electrically connects the interconnect structure to the first conductive region of the transistor; the connecting plug is located inside the active region, and the epitaxial semiconductor material of the first conductive region is located above an upper surface of the connecting plug; or the connecting plug is located within the STI region, and the epitaxial semiconductor material of the first conductive region is connected to a first sidewall of the connecting plug; Semiconductor device structure.

2. the interconnect structure is insulated from the semiconductor substrate by an insulating region; the insulating region comprises a first spacer located on a first side of the interconnect structure and a second spacer located on a second side of the interconnect structure; the material of the first spacer is different from the material of the second spacer; The semiconductor device structure of claim 1 .

3. a second sidewall of the connection plug being aligned with and in contact with a sidewall of the interconnect structure; The semiconductor device structure of claim 1 .

4. the semiconductor device structure further comprises a trench within the active area; the connection plug is disposed inside the trench; The contact plug includes titanium nitride (TiN) and tungsten (W). The semiconductor device structure of claim 3 .

5. the semiconductor device structure further comprises a shallow slot within the STI region; The connection plug is disposed inside the thin slot, the contact plug comprises a highly doped semiconductor material or TiN; the epitaxial semiconductor material of the first conductive region is located above the top surface of the connection plug; the second side wall of the connection plug is located on the opposite side to the first side wall of the connection plug; The semiconductor device structure of claim 3 .

6. the transistor is a fin field effect transistor (FinFET), a GAA transistor, or a CFET; the STI region has an upper surface that is lower than the original semiconductor surface; The semiconductor device structure of claim 1 .

7. the first conductive region comprises selectively epitaxially grown material; The semiconductor device structure of claim 6.

8. the connection plug is located inside the active area; the first conductive region only extends from a vertical sidewall of the active region directly beneath a spacer structure covering the gate structure. The semiconductor device structure of claim 7.

9. the connection plug is located inside the STI region, the first conductive region extends from a vertical sidewall of the active region directly beneath a spacer structure covering the gate structure and from a horizontal surface of the active region adjacent the top surface of the STI region; The semiconductor device structure of claim 7.

10. Further comprising a metal cap (M0) covering the first conductive region. The semiconductor device structure of claim 1 .

11. 1. A semiconductor device structure comprising: a semiconductor substrate having an original semiconductor surface and an active region; a shallow trench isolation (STI) region surrounding the active area; a transistor formed based on the active region; an interconnect structure extending beyond the transistor; A connection plug and a metal cap (M0), The transistor is A gate structure; a first conductive region; a second conductive region; a channel region located between the first conductive region and the second conductive region, the interconnect structure is disposed below the original semiconductor surface and within the STI region; the connecting plug electrically connects the interconnect structure to the first conductive region of the transistor; the metal cap covers the epitaxial semiconductor material of the first conductive region and the connection plug; Semiconductor device structure.

12. the interconnect structure is insulated from the semiconductor substrate by an insulating region; the insulating region comprises a first spacer located on a first side of the interconnect structure and a second spacer located on a second side of the interconnect structure; the material of the first spacer is different from the material of the second spacer; The semiconductor device structure of claim 11.

13. a sidewall of the connection plug is aligned with and in contact with a sidewall of the interconnect structure; The semiconductor device structure of claim 11.

14. the semiconductor device structure further comprises a trench within the active area; the connection plug is disposed inside the trench; The connection plug contains tungsten. The semiconductor device structure of claim 13.

15. the transistor is a FinFET; the channel region comprises a fin structure; the STI region has an upper surface that is lower than the original semiconductor surface; The semiconductor device structure of claim 11.

16. the first conductive region includes an epitaxial semiconductor material; 16. The semiconductor device structure of claim 15.

17. the connection plug is located inside the active area; the first conductive region extends from a vertical sidewall of the fin structure directly beneath a spacer structure covering the gate structure and from a horizontal surface of the active region adjacent the top surface of the STI region; 17. The semiconductor device structure of claim 16.

18. the transistor is a gate-all-around (GAA) transistor; the channel region comprises a plurality of nanosheets; The STI region has an upper surface located at a position lower than the top of the plurality of nanosheet structures. The semiconductor device structure of claim 11.

19. the first conductive region includes an epitaxial semiconductor material; 20. The semiconductor device structure of claim 18.

20. the connection plug is located inside the active area; the first conductive region extends from both vertical sidewalls of the nanosheets located directly below a spacer structure covering the gate structure, and extends from a horizontal surface of the active region located near the top surface of the STI region; 20. The semiconductor device structure of claim 19.

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