Memory system

Abstract

To provide a memory system that manages an amount of valid data with high accuracy.SOLUTION: In an information processing system 1, a memory system comprises: a non-volatile memory; and a memory controller that allocates a logical address range to a namespace in a first unit and releases the logical address range. The first unit includes one or more second units, and each of the second units includes a plurality of third units. The memory controller, in response to a first command from a host instructing invalidation of data stored in a first logical address range designating one or more third units, manages, for each of the second units, a first count that is the number of third units in which valid data is stored among the plurality of third units.SELECTED DRAWING: Figure 1

Description

[Technical Field]

[0001] The embodiments relate to a memory system. [Background technology]

[0002] A memory system including a NAND flash memory as a nonvolatile memory and a memory controller that controls the nonvolatile memory is known. The memory controller manages whether data stored in the nonvolatile memory is valid or invalid. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] US Patent Application Publication No. 2021 / 0089209 [Patent Document 2] U.S. Patent Application Publication No. 2021 / 0294506 [Patent Document 3] US Patent Application Publication No. 2019 / 0361611 Summary of the Invention [Problem to be solved by the invention]

[0004] Manage the amount of valid data with high precision. [Means for solving the problem]

[0005] In one embodiment, the memory system includes a nonvolatile memory and a memory controller that allocates and releases a logical address range to a namespace in a first unit. The first unit includes one or more second units, and the second unit includes a plurality of third units. In response to a first command from a host instructing invalidation of data stored in a first logical address range that specifies one or more of the third units, the memory controller invalidates the data for each of the third units, and manages, for each of the second units, a first count that is the number of the third units among the plurality of third units in which valid data is stored. [Brief explanation of the drawings]

[0006] [Figure 1] FIG. 1 is a block diagram showing an example of the configuration of an information processing system according to an embodiment. [Figure 2] FIG. 2 is a diagram showing an example of the configuration of a logical address used when a host designates a memory space in a memory system according to an embodiment. [Figure 3] FIG. 2 is a diagram showing an example of the configuration of a logical address space of the memory system according to the embodiment. [Figure 4] FIG. 2 is a block diagram showing an example of the functional configuration of a memory controller according to the embodiment. [Figure 5] FIG. 2 is a diagram showing an example of the data structure of a namespace table according to the embodiment. [Figure 6] 1 is a diagram showing an example of the relationship between the logical address space of the memory system according to the embodiment and the data structures of valid cluster count information, trim bit information, and a lookup table. FIG. [Figure 7] 10 is a flowchart showing an example of a series of processes from receiving a trim command to responding to a host in a memory system according to an embodiment. [Figure 8] 10 is a flowchart showing an example of a first calculation process of a valid cluster count in the memory system according to the embodiment. [Figure 9] 10 is a flowchart showing a first example of loop processing in a first calculation process of a valid cluster count in the memory system according to the embodiment. [Figure 10] 10 is a flowchart showing a second example of loop processing in the first calculation process of the valid cluster count in the memory system according to the embodiment. [Figure 11] 10 is a flowchart showing an example of a second calculation process of a valid cluster count in the memory system according to the embodiment. [Figure 12] 10 is a flowchart showing an example of loop processing in a second calculation process of a valid cluster count in the memory system according to the embodiment. [Figure 13] 10 is a flowchart showing an example of a trimming process in the memory system according to the embodiment. [Figure 14] 10 is a flowchart showing an example of a reset process of a trim bit in the memory system according to the embodiment. [Figure 15] 10 is a flowchart showing an example of a series of processes from receiving a write command to responding to a host in a memory system according to an embodiment. [Figure 16] 10 is a flowchart showing an example of a write process in the memory system according to the embodiment. [Figure 17] 10 is a flowchart showing an example of a series of processes from receiving a NUSE information acquisition command to responding to the host in the memory system according to the embodiment. [Figure 18] 10A and 10B are diagrams showing specific examples of valid cluster count information, trim bit information, and a lookup table in a first case of the memory system according to the embodiment. [Figure 19] 10A and 10B are diagrams showing specific examples of valid cluster count information, trim bit information, and a lookup table in a second case of the memory system according to the embodiment. [Figure 20] 10A and 10B are diagrams showing specific examples of valid cluster count information, trim bit information, and a lookup table in a third case of the memory system according to the embodiment. [Figure 21] 10A and 10B are diagrams showing specific examples of valid cluster count information, trim bit information, and a lookup table in a fourth case of the memory system according to the embodiment. [Figure 22]10A and 10B are diagrams showing a first specific example of valid cluster count information, trim bit information, and a lookup table in a fifth case of the memory system according to the embodiment. [Figure 23] 10A and 10B are diagrams showing a second specific example of valid cluster count information, trim bit information, and a lookup table in the fifth case of the memory system according to the embodiment. DETAILED DESCRIPTION OF THE INVENTION

[0007] Hereinafter, embodiments will be described with reference to the drawings. In the following description, components having the same function and configuration will be given the same reference numerals. Furthermore, when multiple components having the same reference numerals are to be distinguished from one another, a subscript will be added to the common reference numeral. In addition, when no particular distinction is required between multiple components, only the common reference numerals will be added to the multiple components, and no subscript will be added.

[0008] 1. Configuration 1.1 Information Processing System The configuration of an information processing system according to an embodiment will be described.

[0009] 1 is a block diagram showing an example of the configuration of an information processing system according to an embodiment. As shown in FIG. 1, the information processing system 1 includes a host 2 and a memory system 3.

[0010] The host 2 is a data processing device that performs processes such as writing, reading, and erasing data using the memory system 3. The host 2 is, for example, a personal computer or a server in a data center. The host 2 uses a logical address to specify a memory address in the memory system 3.

[0011] The memory system 3 is a storage device configured to be connected to the host 2. The memory system 3 is, for example, an SD TMThe memory system 3 includes a memory card such as a card, a universal flash storage (UFS), and a solid state drive (SSD). The memory system 3 has an internal logical address space as a memory space. The internal logical address space of the memory system 3 is, for example, a logical cluster address (LCA).

[0012] 2 is a diagram showing an example of the configuration of a logical address used by a host according to an embodiment. As shown in FIG. 2, the host 2 specifies a memory address of the memory system 3 using a namespace identifier (NS ID) and an address within the namespace (NS). The memory system 3 subdivides the address within the NS into a namespace allocation unit (NSAU) granularity upper address and an offset within the NSAU.

[0013] The NS ID is a bit string that identifies the namespace NS. The namespace NS is a partial space provided to the host 2 by logically dividing the space of internal logical addresses (hereinafter also simply referred to as logical addresses) of the memory system 3. The ranges of addresses within the NS assigned to each namespace NS may be equal to or different from each other.

[0014] The NSAU granularity upper address is a bit string that specifies the range of logical addresses in units of namespace allocation units NSAU. A namespace allocation unit NSAU is a subspace smaller than the namespace NS. The namespace allocation unit NSAU is used, for example, as a unit when allocating and releasing the logical address space of the memory system 3 to the namespace NS. The memory capacity allocated to each namespace allocation unit NSAU is equal to each other.

[0015] The offset within the NSAU is a bit string that specifies a predetermined logical address within the range specified by the NSAU granularity upper address.

[0016] FIG. 3 is a diagram showing an example of the configuration of a logical address space of the memory system according to the embodiment.

[0017] 3, the logical address space of the memory system 3 is divided into a plurality of namespace allocation units NSAU (NSAU0, NSAU1, ...). Each namespace allocation unit NSAU is divided into a plurality of valid cluster count units VCCU (VCCU0, VCCU1, ...). Each valid cluster count unit VCCU is divided into a plurality of segments SEG (SEG0, SEG1, ...). Each segment SEG is divided into a plurality of clusters CST (CST0, CST1, ...).

[0018] The cluster CST is an execution unit of the trim process in the memory system 3. The trim process is also called an unmap process. The trim process will be described in detail later.

[0019] A segment SEG is a unit for postponing trim processing in the memory system 3. Postponing trim processing means that the memory system 3 suspends execution of the trim processing despite receiving a trim command from the host 2. The memory capacity of a segment SEG is larger than the memory capacity of a cluster CST.

[0020] The valid cluster count unit VCCU is a unit for managing the number of clusters CST that store valid data. The memory capacity of the valid cluster count unit VCCU is equal to or larger than the memory capacity of the segment SEG and equal to or smaller than the memory capacity of the namespace allocation unit NSAU.

[0021] 1.2 Memory System Next, the internal configuration of the memory system according to the embodiment will be described with reference to Fig. 1 again. The memory system 3 includes a memory controller 10, a nonvolatile memory 20, and a volatile memory 30.

[0022] The memory controller 10 is configured as an integrated circuit such as a system-on-a-chip (SoC). The memory controller 10 may be configured with multiple semiconductor chips. The memory controller 10 controls the nonvolatile memory 20 based on a request from the host 2.

[0023] Specifically, for example, the memory controller 10 executes a write process to write data to the nonvolatile memory 20 based on a write command from the host 2. Furthermore, the memory controller 10 executes a trim process to invalidate data written to the nonvolatile memory 20 based on a trim command from the host 2. The memory controller 10 then notifies the host 2 in a timely manner of the amount of data stored in the memory system 3 that is valid from the perspective of the host 2. Hereinafter, of the data stored in the memory system 3, data that is valid from the perspective of the host 2 is referred to as valid data. Of the data stored in the memory system 3, data that is invalid from the perspective of the host 2 is referred to as invalid data.

[0024] The nonvolatile memory 20 is, for example, a NAND flash memory. The nonvolatile memory 20 includes a plurality of blocks BLK (BLK0 to BLK3). Each block BLK includes a plurality of memory cells. Each memory cell is a physical area that stores data in a nonvolatile manner. A block BLK is, for example, a unit of data erasure.

[0025] The volatile memory 30 is, for example, a dynamic random access memory (DRAM). The volatile memory 30 stores, for example, a namespace table (NST) 31, valid cluster count (VCC) information 32, trim bit (TB) information 33, and a look up table (LUT) 34. Details of the information stored in the volatile memory 30 will be described later.

[0026] 1.3 Memory Controller Next, the internal configuration of the memory controller 10 will be described.

[0027] 1.3.1 Hardware Configuration First, the hardware configuration of the memory controller 10 will be described with reference to Figure 1. The memory controller 10 includes a control circuit 11, a host interface circuit (host I / F) 12, a volatile memory interface circuit (VMI / F) 13, and a nonvolatile memory interface circuit (NVMI / F) 14. The functions of the control circuit 11, host interface circuit 12, volatile memory interface circuit 13, and nonvolatile memory interface circuit 14 described below can be realized by dedicated hardware, a processor that executes a program, or a combination of these.

[0028] The control circuit 11 is a circuit that controls the entire memory controller 10. The control circuit 11 includes, for example, a processor such as a CPU (central processing unit), a ROM (read only memory), and a RAM (random access memory).

[0029] The host interface circuit 12 controls communication between the memory controller 10 and the host 2. The host interface circuit 12 is connected to the host 2 via a host bus. The host bus may be, for example, an NVMe TM (non-volatile memory express) compliant.

[0030] The volatile memory interface circuit 13 controls communication between the memory controller 10 and the volatile memory 30. The bus connecting the volatile memory 30 and the memory controller 10 complies with, for example, the DRAM interface standard.

[0031] The nonvolatile memory interface circuit 14 manages communication between the memory controller 10 and the nonvolatile memory 20. The nonvolatile memory interface circuit 14 is connected to the nonvolatile memory 20 via a memory bus. The memory bus conforms to, for example, an SDR (single data rate) interface, a toggle DDR (double data rate) interface, or an ONFI (open NAND flash interface).

[0032] 1.3.2 Functional Configuration Next, the functional configuration of the memory controller 10 will be described.

[0033] 4 is a block diagram showing an example of the functional configuration of a memory controller according to an embodiment. As shown in FIG. 4, the memory controller 10 functions as an NST manager 15, a VCC manager 16, a TB manager 17, a LUT manager 18, and a command responder 19.

[0034] The NST management unit 15 associates the logical address specified by the host 2 with the logical address space of the memory system 3. Specifically, the NST management unit 15 allocates and releases the logical address space of the memory system 3 at the granularity of the namespace allocation unit NSAU for the namespace NS specified by the NS ID. The NST management unit 15 generates an NST 31 to manage the allocation status of the logical address space of the memory system 3 at the granularity of the namespace allocation unit NSAU. The NST management unit 15 stores the generated NST 31 in the volatile memory 30.

[0035] 5 is a diagram showing an example of the data structure of the NST according to the embodiment. As shown in FIG. 5, the NST 31 is made up of a plurality of storage areas each including a pair of an NS ID and an NSAU ID.

[0036] The NSAU ID is an identifier for identifying a namespace allocation unit NSAU. The range of logical addresses specified by one NSAU ID is equal to the range of logical addresses specified by one NSAU granularity upper address.

[0037] 5, the namespace allocation units NSAU0 and NSAU2 are assigned to the namespace NS0 in the logical address space of the memory system 3. Also, the namespace allocation unit NSAU1 is assigned to the namespace NS1 in the logical address space of the memory system 3.

[0038] The VCC management unit 16 (see FIG. 4) manages the valid cluster count VCC at the granularity of the valid cluster count unit VCCU. The valid cluster count VCC is the number of clusters CST (valid clusters CST) that store valid data. The VCC management unit 16 generates VCC information 32 to manage the valid cluster count VCC. The VCC management unit 16 stores the generated VCC information 32 in the volatile memory 30.

[0039] FIG. 6 is a diagram showing an example of the relationship between the logical address space of the memory system according to the embodiment and the data structures of the VCC information, the TB information, and the LUT.

[0040] 6, the VCC information 32 is made up of a plurality of storage areas each corresponding to a valid cluster count unit VCCU. Each storage area stores a valid cluster count VCC.

[0041] In the example of Figure 6, "1" is stored as the valid cluster count VCC corresponding to the valid cluster count unit VCCU0 in the namespace allocation unit NSAU0. That is, it can be understood that the valid cluster count unit VCCU0 in the namespace allocation unit NSAU0 has one cluster CST storing valid data. Also, "2" is stored as the valid cluster count VCC corresponding to the valid cluster count unit VCCU1 in the namespace allocation unit NSAU0. That is, it can be understood that the valid cluster count unit VCCU1 in the namespace allocation unit NSAU0 has two clusters CST storing valid data.

[0042] The TB management unit 17 (see FIG. 4) manages the trim bits at the granularity of the segment SEG. The trim bit is a bit that indicates whether the memory system 3 is postponing the trim processing for the corresponding segment SEG. For example, if the trim bit is "1", this indicates that the memory system 3 is postponing the trim processing for the corresponding segment SEG. If the trim bit is "0", this indicates that the memory system 3 is not postponing the trim processing for the corresponding segment SEG. The TB management unit 17 generates TB information 33 to manage the trim bits. The TB management unit 17 stores the generated TB information 33 in the volatile memory 30.

[0043] 6, the TB information 33 is made up of a plurality of storage areas each corresponding to a segment SEG. A trim bit is stored in each storage area.

[0044] 6, "0" and "1" are stored as trim bits corresponding to segments SEG0 and SEG1 in valid cluster count unit VCCU0 in namespace allocation unit NSAU0, respectively. Also, "0" and "0" are stored as trim bits corresponding to segments SEG0 and SEG1 in valid cluster count unit VCCU1 in namespace allocation unit NSAU0, respectively. In other words, it can be seen that the memory system 3 postpones the trim processing for segment SEG1 in valid cluster count unit VCCU0 in namespace allocation unit NSAU0.

[0045] The LUT management unit 18 (see FIG. 4) associates the logical address space with the physical address space in the memory system 3. Specifically, the LUT management unit 18 associates the address (physical address) of the physical area where data is stored with the logical address of the data. The LUT management unit 18 generates an LUT 34 to manage pairs of logical addresses and physical addresses associated with the same data. The LUT management unit 18 stores the generated LUT 34 in the volatile memory 30.

[0046] 6, the LUT 34 is configured with a plurality of storage areas (LUT entries), each of which corresponds to a cluster CST. A physical address PA is stored in each LUT entry.

[0047] The LUT 34 is used to manage the mapping between each logical address and each physical address PA. The memory controller 10 uses the LUT 34 to manage the mapping between each logical address and each physical address PA in a specific management size unit. Here, the specific management size unit is a cluster CST. A physical address PA corresponding to a certain logical address indicates a physical storage location in the nonvolatile memory 20 to which data at this logical address is written. The memory controller 10 uses the LUT 34 to manage multiple storage areas obtained by logically dividing the storage area of ​​the nonvolatile memory 20. The size of each of these multiple storage areas is a cluster CST. These multiple storage areas correspond to multiple logical addresses, respectively. In other words, each of these multiple storage areas is identified by a single logical address. The LUT 34 may be loaded from the nonvolatile memory 20 to the volatile memory 30 when the memory system 3 is started up.

[0048] The memory controller 10 writes updated data corresponding to a logical address to a different physical storage location, rather than to the physical storage location where the previous data corresponding to this logical address is stored. The memory controller 10 then invalidates the previous data by updating the LUT entry to associate this logical address with this different physical storage location. Data referenced by the LUT 34 (i.e., data associated with a logical address) is valid data. Data not associated with any logical address is invalid data. Valid data is data that may be read by the host 2 later. Invalid data is data that may no longer be read by the host 2.

[0049] In the example of Figure 6, data specified by the logical address of cluster CST0 in segment SEG0 in valid cluster count unit VCCU0 in namespace allocation unit NSAU0 is stored in a physical area specified by physical address PA0. Data specified by the logical address of cluster CST0 in segment SEG1 in valid cluster count unit VCCU0 in namespace allocation unit NSAU0 is stored in a physical area specified by physical address PA1. Data specified by the logical address of cluster CST0 in segment SEG0 in valid cluster count unit VCCU1 in namespace allocation unit NSAU0 is stored in a physical area specified by physical address PA2. Data specified by the logical address of cluster CST0 in segment SEG1 in valid cluster count unit VCCU1 in namespace allocation unit NSAU0 is stored in a physical area specified by physical address PA3.

[0050] Note that valid data is not necessarily stored in the physical address PA stored in the LUT 34. For example, in the example of FIG. 6, the trim bit corresponding to the segment SEG1 in the valid cluster count unit VCCU0 in the namespace allocation unit NSAU0 is "1." Therefore, the data stored in the physical area specified by the physical address PA1 is data for which trim processing is scheduled to be performed, and is data that has already been instructed to be invalidated by the host 2 (i.e., invalid data). Therefore, the cluster CST0 in the segment SEG1 corresponding to the LUT count that stores the physical address PA1 is not counted in the valid cluster count VCC.

[0051] On the other hand, the trim bit corresponding to the segment SEG0 in the valid cluster count unit VCCU0 in the namespace allocation unit NSAU0 is "0." Therefore, the data stored in the physical area specified by the physical address PA0 is valid data that is not scheduled to undergo trim processing. Therefore, the cluster CST0 in the segment SEG0 corresponding to the LUT count stored in the physical area specified by the physical address PA0 is counted in the valid cluster count VCC.

[0052] The command response unit 19 (see FIG. 4) returns a command completion response to the host 2 in response to various commands from the host 2. The response to the host 2 conforms to the OCP (Open Compute Project). The response includes a value obtained by aggregating the sum of the available cluster count VCC for each namespace NS. This sum of the available cluster count VCC is also called NUSE (namespace utilization). For example, NUSE is included in the response to a command from the host 2 to obtain NUSE information.

[0053] 2. Operation Next, the operation of the information processing system according to the embodiment will be described.

[0054] 2.1 A series of processes from receiving a trim command to responding to the host First, a series of processes from receiving a trim command to responding to the host in the memory system according to the embodiment will be described.

[0055] 2.1.1 Overall processing FIG. 7 is a flowchart showing an example of a series of processes from receiving a trim command to responding to the host in the memory system according to the embodiment.

[0056] When a trim command is received from the host 2 (start), the control circuit 11 converts the trim range specified by the host 2 into an internal trim range on the logical address space of the memory system 3 (S1).

[0057] The control circuit 11 identifies all valid cluster count units VCCU included in the internal trim range (S2). Here, if at least a portion of the valid cluster count unit VCCU is included in the internal trim range, the control circuit 11 considers the valid cluster count unit VCCU to be included in the internal trim range.

[0058] After the process of S2, the control circuit 11 executes a loop process L1 (S3). The loop process L1 includes the processes of S11 to S17 shown below.

[0059] In loop processing L1, the control circuit 11 selects one of the valid cluster count units VCCU identified in the processing of S2 (S11). In loop processing L1, the valid cluster count unit VCCU selected in the processing of S11 is called a selected unit VCCU.

[0060] The control circuit 11 refers to the TB information 33 and determines whether the currently designated internal trim range and the range in which the trim bit is "1" (see S14) cover all of the selected units VCCU (S12).

[0061] If the internal trim range and the range where the trim bit is “1” cover all of the selected units VCCU (S12; yes), the control circuit 11 edits the VCC information 32 and sets the valid cluster count VCC corresponding to the selected unit VCCU to “0” (S13).

[0062] After the process of S13, the control circuit 11 sets all of the trim bits corresponding to all of the segments SEG in the selection unit VCCU to "1" (S14).

[0063] If the internal trim range and the range in which the trim bit is "1" do not cover the entire selection unit VCCU (S12; no), the control circuit 11 determines whether the number of segments SEG in the selection unit VCCU whose corresponding trim bit is "0" and which are within the internal trim range is less than or equal to the number of segments SEG whose corresponding trim bit is "0" and which are outside the internal trim range (S15).

[0064] If the number of segments SEGs in the selection unit VCCU whose corresponding trim bits are "0" and that are within the internal trim range is equal to or less than the number of segments SEGs whose corresponding trim bits are "0" and that are outside the internal trim range (S15; yes), the control circuit 11 executes a first calculation process to calculate a new value of VCC (S16). That is, the first calculation process focuses on segments SEGs whose corresponding trim bits are "0" and that are within the internal trim range. The first calculation process calculates the effective cluster count VCC taking the trim command into consideration by subtracting it from the current value. Details of the first calculation process will be described later. Also, here, if the corresponding trim bit is "0" but only some of the segments SEGs in the selection unit VCCU are within the internal trim range, the segment SEG is not included in the "number of segments SEGs whose corresponding trim bits are "0" and that are outside the internal trim range." Similarly, the segment SEG is not included in the "number of segments SEGs whose corresponding trim bits are "0" and that are within the internal trim range."

[0065] In the selection unit VCCU, if the number of segments SEG whose corresponding trim bit is "0" and that are within the internal trim range is greater than the number of segments SEG whose corresponding trim bit is "0" and that are outside the internal trim range (S15; no), the control circuit 11 executes a second calculation process to calculate a new value of VCC (S17). That is, the second calculation process focuses on segments SEG whose corresponding trim bit is "0" and that are outside the internal trim range. The second calculation process calculates the valid cluster count VCC taking the trim command into consideration by an additive method starting from 0. Details of the second calculation process will be described later.

[0066] After the process of S14, S16, or S17, the control circuit 11 determines whether or not all valid cluster count units VCCU identified in the process of S2 have been selected. If there are any unselected valid cluster count units VCCU, the control circuit 11 repeats the processes of S11 to S17 described above. After all valid cluster count units VCCU identified in the process of S2 have been selected, the control circuit 11 ends the loop process L1.

[0067] After the loop process L1, the control circuit 11 returns a response corresponding to the trim command to the host 2 (S4).

[0068] When the process of S4 is completed, the series of processes from receiving the trim command to responding to the host 2 is completed (end).

[0069] 2.1.2 First calculation process 8 is a flowchart showing an example of a first calculation process in the memory system according to the embodiment. The processes of S21 and S22 shown in FIG. 8 correspond to the first calculation process of S16 in FIG.

[0070] When the first calculation process is started (START), the control circuit 11 identifies all segments SEG included in the internal trim range from the selection unit VCCU (S21). Here, if at least a portion of a segment SEG is included in the internal trim range, the control circuit 11 considers the segment SEG to be included in the internal trim range.

[0071] After the process of S21, the control circuit 11 executes a loop process L2 (S22). The loop process L2 includes the processes of S31 to S38 shown below.

[0072] In loop processing L2, the control circuit 11 selects one of the segments SEG identified in the processing of S21 (S31). In loop processing L2, the segment SEG selected in the processing of S31 is called the selected segment SEG.

[0073] The control circuit 11 refers to the TB information 33 and determines whether the trim bit corresponding to the selected segment SEG is "1" (S32).

[0074] If the trim bit corresponding to the selected segment SEG is "0" (S32; no), the control circuit 11 determines whether the internal trim range includes the entire selected segment SEG (S33).

[0075] If the internal trim range includes the entire selected segment SEG (S33; yes), the control circuit 11 identifies all clusters CST within the selected segment SEG (S34).

[0076] After the process of S34, the control circuit 11 executes loop process L3 (S35). Fig. 9 is a flowchart showing a first example of loop process in the first calculation process in the memory system according to the embodiment. The processes of S41 to S43 shown in Fig. 9 correspond to loop process L3 of S35 in Fig. 8.

[0077] 9, in loop processing L3, the control circuit 11 selects one of the clusters CST identified in the processing of S34 (S41). In loop processing L3, the cluster CST selected in the processing of S41 is called the selected cluster CST.

[0078] The control circuit 11 refers to the LUT 34 and determines whether or not a valid physical address PA is stored in the LUT entry corresponding to the selected cluster CST (S42).

[0079] If a valid physical address PA is stored in the LUT entry corresponding to the selected cluster CST (S42; yes), the control circuit 11 edits the VCC information 32 and decrements the valid cluster count VCC corresponding to the selected unit VCCU (S43).

[0080] If a valid physical address PA is not stored in the LUT entry corresponding to the selected cluster CST (S42; no), or after the process of S43, the control circuit 11 determines whether or not all of the clusters CST identified in the process of S34 have been selected. If there are any unselected clusters CST, the control circuit 11 repeats the processes of S41 to S43 described above. After all of the clusters CST identified in the process of S34 have been selected, the control circuit 11 ends the loop process L3 (end).

[0081] The first calculation process will be described again with reference to FIG.

[0082] After the loop process L3 of S35, the control circuit 11 edits the TB information 33 and sets the trim bit corresponding to the selected segment SEG to "1" (S36).

[0083] If the internal trim range does not include the entire selected segment SEG (S33; no), the control circuit 11 identifies all clusters CST included in the internal trim range from the selected segment SEG (S37).

[0084] After the process of S37, the control circuit 11 executes loop process L4 (S38). Fig. 10 is a flowchart showing a second example of loop process in the first calculation process in the memory system according to the embodiment. The processes of S51 to S54 shown in Fig. 10 correspond to loop process L4 of S38 in Fig. 8.

[0085] 10, in loop processing L4, the control circuit 11 selects one of the clusters CST identified in the processing of S37 (S51). In loop processing L4, the cluster CST selected in the processing of S51 is called the selected cluster CST.

[0086] The control circuit 11 refers to the LUT 34 and determines whether or not a valid physical address PA is stored in the LUT entry corresponding to the selected cluster CST (S52).

[0087] If a valid physical address PA is stored in the LUT entry corresponding to the selected cluster CST (S52; yes), the control circuit 11 edits the LUT 34 and invalidates the LUT entry corresponding to the selected cluster CST (S53).

[0088] After the process of S53, the control circuit 11 edits the VCC information 32 and decrements the valid cluster count VCC corresponding to the selected unit VCCU (S54).

[0089] If a valid physical address PA is not stored in the LUT entry corresponding to the selected cluster CST (S52; no), or after the process of S54, the control circuit 11 determines whether or not all of the clusters CST identified in the process of S37 have been selected. If there are any unselected clusters CST, the control circuit 11 repeats the processes of S51 to S54 described above. After all of the clusters CST identified in the process of S37 have been selected, the control circuit 11 ends the loop process L4 (end).

[0090] The first calculation process will be described again with reference to FIG.

[0091] If the trim bit corresponding to the selected segment SEG is "1" (S32; yes), after loop process L3 of S36 or after loop process L4 of S38, the control circuit 11 determines whether all of the segments SEG identified in the process of S21 have been selected. If there are any unselected segments SEG, the control circuit 11 repeats the processes of S21 to S28 described above. After all of the segments SEG identified in the process of S21 have been selected, the control circuit 11 ends loop process L2.

[0092] When the loop process L2 ends, the first calculation process ends (ends).

[0093] 2.1.3 Second calculation process 11 is a flowchart showing an example of the second calculation process in the memory system according to the embodiment. The processes of S61 to S63 shown in FIG. 11 correspond to the second calculation process of S17 in FIG.

[0094] When the second calculation process is started (START), the control circuit 11 edits the VCC information 32 and sets the valid cluster count VCC corresponding to the selected unit VCCU to "0" (S61).

[0095] After the process of S61, the control circuit 11 identifies all segments SEG included in the internal trim range from the selection unit VCCU (S62).

[0096] After the process of S62, the control circuit 11 executes loop process L5 (S63). Loop process L5 includes the processes of S71 to S76 shown below.

[0097] In loop processing L5, control circuit 11 selects one of the segments SEG identified in the processing of S62 (S71). In loop processing L5, the segment SEG selected in the processing of S62 is called the selected segment SEG.

[0098] The control circuit 11 refers to the TB information 33 and determines whether the trim bit corresponding to the selected segment SEG is "1" (S72).

[0099] If the trim bit corresponding to the selected segment SEG is "0" (S72; no), the control circuit 11 determines whether the internal trim range includes the entire selected segment SEG (S73).

[0100] If the internal trim range includes the entire selected segment SEG (S73; yes), the control circuit 11 edits the TB information 33 and sets the trim bit corresponding to the selected segment SEG to "1" (S74).

[0101] If the internal trim range does not include the entire selected segment SEG (S73; no), the control circuit 11 identifies all clusters CST included in the internal trim range from the selected segment SEG (S75).

[0102] After the process of S75, the control circuit 11 executes loop processing L6 (S76). Fig. 12 is a flowchart showing an example of loop processing in the second calculation process in the memory system according to the embodiment. The processes of S81 to S85 shown in Fig. 12 correspond to loop processing L6 of S76 in Fig. 11.

[0103] 12, in loop processing L6, the control circuit 11 selects one of the clusters CST identified in the processing of S75 (S81). In loop processing L6, the cluster CST selected in the processing of S81 is called the selected cluster CST.

[0104] The control circuit 11 refers to the LUT 34 and determines whether or not a valid physical address PA is stored in the LUT entry corresponding to the selected cluster CST (S82).

[0105] If a valid physical address PA is stored in the LUT entry corresponding to the selected cluster CST (S82; yes), the control circuit 11 determines whether the selected cluster CST is within the internal trim range (S83).

[0106] If the selected cluster CST is within the internal trim range (S83; yes), the control circuit 11 edits the LUT 34 and invalidates the LUT entry corresponding to the selected cluster CST (S84).

[0107] If the selected cluster CST is not within the internal trim range (S83; no), the control circuit 11 edits the VCC information 32 and increments the valid cluster count VCC corresponding to the selected unit VCCU (S85).

[0108] If a valid physical address PA is not stored in the LUT entry corresponding to the selected cluster CST (S82; no), after the process of S84 or after the process of S85, the control circuit 11 determines whether all of the clusters CST identified in the process of S75 have been selected. If there are any unselected clusters CST, the control circuit 11 repeats the processes of S81 to S85 described above. After all of the clusters CST identified in the process of S75 have been selected, the control circuit 11 ends the loop process L6 (end).

[0109] The second calculation process will be described again with reference to FIG.

[0110] If the trim bit corresponding to the selected segment SEG is "1" (S72; yes), after the process of S74 or after the loop process L6 of S76, the control circuit 11 determines whether or not all of the segments SEG identified in the process of S62 have been selected. If there are any unselected segments SEG, the control circuit 11 repeats the processes of S71 to S76 described above. After all of the segments SEG identified in the process of S62 have been selected, the control circuit 11 ends the loop process L5.

[0111] When the loop process L5 ends, the second calculation process ends (ends).

[0112] 2.2 Trim processing Next, the trimming process in the memory system according to the embodiment will be described.

[0113] The memory system 3 can start the trim process at any timing, regardless of when the trim command is received. The memory system 3 executes the trim process in the background, during a period when the memory system 3 is not executing a process that has a response time constraint on the host 2 (for example, a period when data is being written to the nonvolatile memory 20). The memory system 3 executes the trim process, for example, before a write process, in order to reuse the physical area storing invalid data.

[0114] FIG. 13 is a flowchart showing an example of a trimming process in the memory system according to the embodiment.

[0115] When the trimming process starts (START), the control circuit 11 refers to the TB information 33 and determines whether or not there is a segment SEG whose trim bit is "1" (S91).

[0116] If there is a segment SEG whose trim bit is "1" (S91; yes), the control circuit 11 selects one segment SEG whose trim bit is "1" (S92). In the trim process, the segment selected in the process of S92 is called the selected segment SEG.

[0117] Although the segment SEG to be selected is arbitrary, the control circuit 11 may determine the segment SEG to be selected based on a predetermined criterion. For example, the control circuit 11 may preferentially select a segment SEG for which a long time has elapsed since the trim bit became "1." Alternatively, for example, the control circuit 11 may preferentially select a segment SEG within the range of the write process.

[0118] After the process of S92, the control circuit 11 executes a reset process (to be described in detail later) of the trim bit corresponding to the segment SEG selected in the process of S92 (S93).

[0119] After the reset process in S93, the trimming process ends (END).

[0120] 14 is a flowchart showing an example of a reset process of the trim bit in the memory system according to the embodiment. The processes of S101 to S103 shown in FIG. 14 correspond to the reset process of S93 in FIG.

[0121] When the trim bit reset process starts (START), the control circuit 11 identifies all clusters CST included in the selected segment SEG (S101).

[0122] After the process of S101, the control circuit 11 executes loop process L7 (S102). Loop process L7 includes the processes of S111 to S113 shown below.

[0123] In loop processing L7, the control circuit 11 selects one of the clusters CST identified in the processing of S101 (S111). In loop processing L7, the cluster CST selected in the processing of S111 is called the selected cluster CST.

[0124] The control circuit 11 refers to the LUT 34 and determines whether or not a valid physical address PA is stored in the LUT entry corresponding to the selected cluster CST (S112).

[0125] If a valid physical address PA is stored in the LUT entry corresponding to the selected cluster CST (S112; yes), the control circuit 11 edits the LUT 34 and invalidates the LUT entry corresponding to the selected cluster CST (S113).

[0126] If a valid physical address PA is not stored in the LUT entry corresponding to the selected cluster CST (S112; no), or after the process of S113, the control circuit 11 determines whether or not all of the clusters CST identified in the process of S101 have been selected. If there are any unselected clusters CST, the control circuit 11 repeats the processes of S111 to S113 described above. After all of the clusters CST identified in the process of S101 have been selected, the control circuit 11 ends the loop process L7.

[0127] After the loop process L7 in S102, the control circuit 11 sets the trim bit corresponding to the selected segment to "0" (S103).

[0128] When the process of S103 is completed, the trim bit reset process is completed (END).

[0129] 2.3 A series of processes from receiving a write command to responding to the host Next, a series of processes from receiving a write command to responding to the host in the memory system according to the embodiment will be described.

[0130] 2.3.1 Overall processing FIG. 15 is a flowchart showing an example of a series of processes from receiving a write command to responding to the host in the memory system according to the embodiment.

[0131] When a write command is received from the host 2 (start), the control circuit 11 converts the write range specified by the host 2 into an internal write range on the logical address space of the memory system 3 (S121).

[0132] The control circuit 11 determines whether or not there is a segment SEG with a trim bit of "1" within the internal write range (S122).

[0133] If there is a segment SEG with a trim bit of "1" within the internal write range (S122; yes), the control circuit 11 identifies all segments SEG with a trim bit of "1" within the internal write range (S123).

[0134] After the process of S123, the control circuit 11 executes loop process L8 (S124). Loop process L8 includes the processes of S131 and S132 shown below.

[0135] In loop processing L8, the control circuit 11 selects one of the segments SEG identified in the processing of S123 (S131). In loop processing L8, the segment SEG selected in the processing of S131 is called the selected segment SEG.

[0136] After the process of S131, the control circuit 11 executes a reset process of the trim bit (S132). The reset process of S132 is the same as the processes of S101 to S103 described with reference to FIG.

[0137] After the reset process of S132, the control circuit 11 determines whether all of the segments SEG identified in the process of S123 have been selected. If there are any unselected segments SEG, the control circuit 11 repeats the processes of S131 and S132 described above. After all of the segments SEG identified in the process of S123 have been selected, the control circuit 11 ends the loop process L8.

[0138] If there is no segment SEG with a trim bit of "1" within the internal write range (S122; no), or after the loop process L8 of S124, the control circuit 11 identifies all clusters CST within the internal write range (S125).

[0139] After the process of S125, the control circuit 11 executes loop process L9 (S126). Loop process L9 includes the processes of S141 and S142 shown below.

[0140] In loop processing L9, the control circuit 11 selects one of the clusters CST identified in the processing of S125 (S141). In loop processing L9, the cluster CST selected in the processing of S141 is called the selected cluster CST.

[0141] After the process of S141, the control circuit 11 executes a write process (S142). Fig. 16 is a flowchart showing an example of a write process in the memory system according to the embodiment. The processes of S151 to S154 shown in Fig. 16 correspond to the write process of S142 in Fig. 15.

[0142] As shown in FIG. 16, in the write process, the control circuit 11 refers to the LUT 34 and determines whether or not a valid physical address PA is stored in the LUT entry corresponding to the selected cluster CST (S151).

[0143] If a valid physical address PA is not stored in the LUT entry corresponding to the selected cluster CST (S151; no), the control circuit 11 edits the VCC information 32 and increments the valid cluster count VCC corresponding to the valid cluster count unit VCCU to which the selected cluster CST belongs (S152).

[0144] If a valid physical address PA is stored in the LUT entry corresponding to the selected cluster CST (S151; yes), or after the process of S152, the control circuit 11 writes the valid data to the nonvolatile memory 20 (S153).

[0145] Furthermore, the control circuit 11 edits the LUT 34 and stores the physical address of the valid data in the LUT entry corresponding to the selected cluster CST (S154).

[0146] When the process of S154 ends, the write process ends (end).

[0147] Referring again to FIG. 15, a series of processes from receiving a write command to responding to the host will be described.

[0148] After the write process of S142, the control circuit 11 determines whether all of the clusters CST identified in the process of S125 have been selected. If there are any unselected clusters CST, the control circuit 11 repeats the processes of S141 and S142. After all of the clusters CST identified in the process of S125 have been selected, the control circuit 11 ends the loop process L9.

[0149] After the loop process L9 of S126, the control circuit 11 returns a response to the write command to the host 2 (S127).

[0150] When the process of S127 ends, the series of processes from receiving the write command to responding to the host ends (end).

[0151] 2.4 A series of processes from receiving a NUSE information acquisition command to responding to the host Next, a series of processes from receiving a NUSE information acquisition command to responding to the host in the memory system according to the embodiment will be described.

[0152] 2.4.1 Overall processing FIG. 17 is a flowchart showing an example of a series of processes from receiving a NUSE information acquisition command to responding to the host in the memory system according to the embodiment.

[0153] When the control circuit 11 receives an NUSE information acquisition command from the host 2 (start), it calculates the sum of the valid cluster count VCC values ​​for each specified namespace NS (S160). The calculated sum of the valid cluster count VCC is the NUSE.

[0154] The control circuit 11 returns a response including the calculated value of NUSE to the host 2 (S161).

[0155] When the process of S161 ends, the series of processes from receiving the NUSE information acquisition command to responding to the host ends (end).

[0156] Although the method described here is one in which the control circuit 11 calculates NUSE by adding up the valid cluster count VCC for each namespace NS after receiving the NUSE information acquisition command, NUSE may also be calculated by another method. For example, a NUSE counter whose initial value is 0 may be provided for each namespace NS when the namespace NS is created. In this case, the control circuit 11 may calculate NUSE by incrementing or decrementing the NUSE counter each time the value of the valid cluster count VCC assigned to the namespace NS increases or decreases.

[0157] 3. Specific Examples Next, a specific example of a change in the valid cluster count VCC in the memory system according to the embodiment will be described.

[0158] In the following specific example, the states of the VCC information 32, TB information 33, and LUT 34 shown in Figure 6 are assumed to be initial states. For convenience of explanation, it is assumed that the namespace allocation unit NSAU0 is divided into two valid cluster count units VCCU0 and VCCU1. It is assumed that each of the valid cluster count units VCCU0 and VCCU1 is divided into two segments SEG0 and SEG1. It is assumed that each of the segments SEG0 and SEG1 is divided into two clusters CST0 and CST1.

[0159] 3.1 First Case First, the first case will be described. The first case is an example when the memory system 3 receives a trim command from the host 2, and corresponds to a case where it is determined that the range of the trim processing covers the selected unit VCCU (S12; yes). In the first case, the internal trim range is assumed to be the valid cluster count unit VCCU0.

[0160] FIG. 18 is a diagram showing specific examples of VCC information, TB information, and an LUT in the first case of the memory system according to the embodiment.

[0161] 18, the control circuit 11 changes the valid cluster count VCC corresponding to the valid cluster count unit VCCU0 from "1" to "0" (S13). The process of S13 is executed without checking the valid cluster count VCC at the granularity of the cluster CST. Therefore, the control circuit 11 can execute the process of S13 faster than when checking the valid cluster count VCC at the granularity of the cluster CST.

[0162] After the process of S13, the control circuit 11 changes the trim bit corresponding to the segment SEG0 of the valid cluster count unit VCCU0 to "1" (S14).

[0163] Thereafter, the control circuit 11 returns a response to the trim command to the host 2 (S4).

[0164] The trimming process is executed after the response process of S4, that is, the memory system 3 postpones the trimming process to be executed in the background.

[0165] 3.2 Second Case Next, the second case will be described. The second case is an example when the memory system 3 receives a trim command from the host 2, and corresponds to the case where it is determined that the range of the trim process does not cover the selection unit VCCU (S12; no) and includes the entire selection segment SEG (S33; yes). The second case also corresponds to the first calculation process (S16). In the second case, the internal trim range is assumed to be segment SEG0 of the valid cluster count unit VCCU1. That is, in the second case, the selection unit VCCU is the valid cluster count unit VCCU1, and the selection segment SEG is segment SEG0 of the valid cluster count unit VCCU1.

[0166] FIG. 19 is a diagram showing specific examples of VCC information, TB information, and an LUT in the second case of the memory system according to the embodiment.

[0167] 19, in loop processing L3, the control circuit 11 decrements the valid cluster count VCC corresponding to the valid cluster count unit VCCU1 according to the number of LUT entries in which valid physical addresses PA are stored (S35). That is, the control circuit 11 checks whether there is a valid cluster in the selected segment SEG0 at the granularity of the cluster CST. In the second case, since the valid cluster CST in the selected segment SEG0 is the cluster CST0, the control circuit 11 changes the valid cluster count VCC from "2" to "1." This allows the control circuit 11 to accurately grasp the valid cluster count VCC at the granularity of the cluster CST.

[0168] After the process of S35, the control circuit 11 changes the trim bit corresponding to the segment SEG0 of the valid cluster count unit VCCU1 from "0" to "1" (S36).

[0169] Thereafter, the control circuit 11 returns a response to the trim command to the host 2 (S4).

[0170] The trimming process is executed after the response process of S4, that is, the memory system 3 postpones the trimming process to be executed in the background.

[0171] 3.3 Third Case Next, the third case will be described. The third case is an example when the memory system 3 receives a trim command from the host 2, and corresponds to the case where it is determined that the range of the trim process does not cover the selected unit VCCU (S12; no) and does not include the entire selected segment SEG (S33; no). The third case also corresponds to the first calculation process (S16). In the third case, the internal trim range is assumed to be cluster CST0 of segment SEG1 of valid cluster count unit VCCU1. That is, in the third case, the selected unit VCCU is valid cluster count unit VCCU1. The selected segment SEG is segment SEG1 of valid cluster count unit VCCU1. The selected cluster CST is cluster CST0 of segment SEG1 of valid cluster count unit VCCU1.

[0172] FIG. 20 is a diagram showing specific examples of VCC information, TB information, and an LUT in the third case of the memory system according to the embodiment.

[0173] 20, the control circuit 11 invalidates the selected cluster CST0 in the loop processing L4 (S53). That is, the control circuit 11 invalidates the physical address PA stored in the LUT entry corresponding to the selected cluster CST0 in the LUT 34.

[0174] After the process of S53, the control circuit 11 decrements the valid cluster count VCC corresponding to the valid cluster count unit VCCU1 according to the number of invalidated LUTs (S54). That is, the control circuit 11 checks the valid cluster count VCC corresponding to the valid cluster count unit VCCU1 at the granularity of the cluster CST. In the third case, since the valid cluster CST0 in the selected segment SEG0 is invalidated, the control circuit 11 changes the valid cluster count VCC from "2" to "1." This allows the control circuit 11 to accurately grasp the valid cluster count VCC at the granularity of the cluster CST.

[0175] Thereafter, the control circuit 11 returns a response to the trim command to the host 2 (S4).

[0176] In this way, when the internal trim range is narrower than the segment SEG, the trim processing is not postponed but is executed before the response processing of S4. Therefore, in the third case, the trim bit is not changed.

[0177] 3.4 Case 4 Next, the fourth case will be described. The fourth case is an example of a trim bit reset process executed in the background. In the fourth case, the target range of the trim bit reset process is assumed to be the segment SEG1 of the valid cluster count unit VCCU0. That is, in the fourth case, the selected segment SEG is the segment SEG1 of the valid cluster count unit VCCU0. The selected cluster CST is the cluster CST0 of the segment SEG1 of the valid cluster count unit VCCU0.

[0178] FIG. 21 is a diagram showing specific examples of VCC information, TB information, and an LUT in the fourth case of the memory system according to the embodiment.

[0179] As shown in FIG. 21, in loop processing L7, the control circuit 11 invalidates the LUT entry corresponding to the selected cluster CST0 (S102).

[0180] After the loop process L7, the control circuit 11 changes the trim bit corresponding to the selected segment SEG1 from "1" to "0" (S103).

[0181] In this way, when the trim process is performed in the background after the response process of S4, the valid cluster count VCC is not changed.

[0182] 3.5 Fifth Case Next, the fifth case will be described. The fifth case is an example of a write process. In the fifth case, the target range of the write process is assumed to be the cluster CST1 of the segment SEG1 of the valid cluster count unit VCCU0. That is, in the fifth case, the selected segment SEG is the segment SEG1 of the valid cluster count unit VCCU0.

[0183] 22 is a diagram showing a first specific example of VCC information, TB information, and LUT in a fifth case of the memory system according to the embodiment. FIG. 23 is a diagram showing a second specific example of VCC information, TB information, and LUT in the fifth case of the memory system according to the embodiment. The first specific example of the fifth case shows changes in VCC information 32, TB information 33, and LUT 34 based on a trim bit reset process executed in the foreground prior to a write process. The second specific example of the fifth case shows changes in VCC information 32, TB information 33, and LUT 34 based on a write process.

[0184] As shown in FIG. 22, the control circuit 11 executes a reset process of the trim bit for the selected segment SEG1 (S132).

[0185] Accordingly, in loop processing L7, the control circuit 11 invalidates the LUT entry corresponding to the cluster CST0 in the selected segment SEG1 (S102).

[0186] After the loop process L7, the control circuit 11 changes the trim bit corresponding to the selected segment SEG1 from "1" to "0" (S103).

[0187] In this way, the effective cluster count VCC is not changed when the trim bit reset process is performed.

[0188] After the trim bit reset process is completed, the control circuit 11 executes the write process (S142) as shown in FIG.

[0189] Before the write process is performed, no valid data is stored in the cluster CST1, which is the internal write range (S151; no). Therefore, the control circuit 11 changes the valid cluster count VCC corresponding to the valid cluster count unit VCCU0 to which the cluster CST belongs from “1” to “2” (S152).

[0190] Thereafter, the control circuit 11 writes the valid data to the nonvolatile memory 20 (S153). Furthermore, the control circuit 11 stores the physical address of the valid data in the LUT entry corresponding to the cluster CST1 (S154).

[0191] Thereafter, the control circuit 11 returns a response to the write command to the host 2 (S127).

[0192] 4. Effects of the embodiment According to an embodiment, the memory controller 10 executes trim processing at the granularity of clusters CST in response to a trim command from the host 2. The memory controller 10 updates the valid cluster count VCC for each valid cluster count unit VCCU. The memory controller 10 calculates the sum (NUSE) of the valid cluster counts VCC in the namespace NS. If the target range (internal trim range) of the trim processing is equal to or greater than the segment SEG, the memory controller 10 can return a response including the calculated sum (NUSE) to the host 2 before executing the trim processing. This allows the calculated sum (NUSE) to be managed with high accuracy while shortening the response time to a NUSE information acquisition command from the host 2.

[0193] Additionally, in order to accurately grasp the amount of valid data when the trimming process is postponed, it is necessary to determine the presence or absence of valid data at the granularity of the cluster CST. However, if the above determination is made for all cluster CSTs, it may take a long time for the host 2 to respond to the NUSE information acquisition command.

[0194] According to an embodiment, when the internal trim range is less than the segment SEG, the memory controller 10 invalidates the LUT entry for each cluster CST included in the internal trim range. The memory controller 10 calculates the valid cluster count VCC based on the invalidation.

[0195] If the target range of the trimming process is equal to or larger than the segment SEG and smaller than the valid cluster count unit VCCU, the memory controller 10 determines whether valid data is stored in each cluster CST included in the internal trimming range without invalidating the LUT entries.The memory controller 10 calculates the valid cluster count VCC based on the result of the determination.

[0196] If the target range of the trimming process is equal to or greater than the valid cluster count unit VCCU, the memory controller 10 does not invalidate the LUT entries for the target range. The memory controller 10 sets the valid cluster count VCC corresponding to the valid cluster count unit VCCU in the target range to “0” without making a determination for each cluster CST.

[0197] Here, a method for calculating NUSE in a comparative example will be described. In the comparative example, NUSE is calculated by counting valid clusters on the LUT entry. Therefore, if there is a trimming process that has been postponed, an accurate NUSE cannot be calculated until that trimming process is completed. As a result, there are cases where the correct NUSE cannot be returned in response to a NUSE information acquisition command from host 2.

[0198] In this embodiment, even if the trimming process is postponed, it is possible to update the valid cluster count VCC and calculate the NUSE. This shortens the response time to the NUSE information acquisition command from the host 2, and makes it possible to calculate the valid cluster count VCC with less error than the calculation method of the comparative example.

[0199] Note that the closer the size of the valid cluster count unit VCCU is to the segment SEG, the faster the calculation speed of the valid cluster count VCC becomes, but the size of the VCC information 32 becomes larger. On the other hand, the closer the size of the valid cluster count unit VCCU is to the namespace allocation unit NSAU, the slower the calculation speed of the valid cluster count VCC becomes, but the size of the VCC information 32 becomes smaller. In an embodiment, the size of the valid cluster count unit VCCU can be set arbitrarily within a range of equal to or larger than the segment SEG and equal to or smaller than the namespace allocation unit NSAU. This makes it possible to balance the response time and the size of the volatile memory 30.

[0200] Although several embodiments of the present invention have been described, these embodiments are presented as examples and are not intended to limit the scope of the invention. These embodiments can be implemented in various other forms, and various omissions, substitutions, and modifications can be made without departing from the spirit of the invention. These embodiments and their modifications are included within the scope and spirit of the invention, as well as within the scope of the invention described in the claims and their equivalents. [Explanation of symbols]

[0201] 1. Information processing system 2. Host 3. Memory system 10...Memory controller 11...Control circuit 12...Host interface circuit 13...Volatile memory interface circuit 14...Non-volatile memory interface circuit 15…NST Management Department 16…VCC Management Department 17…TB Management Department 18…LUT management department 19...Command response section 20...Non-volatile memory 30...Volatile memory 31...NST 32…VCC information 33…TB information 34...LUT

Claims

1. a non-volatile memory; a memory controller that allocates and frees logical address ranges to a namespace in a first unit; Equipped with the first unit includes one or more second units, and the second unit includes a plurality of third units; the memory controller, in response to a first command from a host instructing invalidation of data stored in a first logical address range specifying one or more of the third units, invalidating the data for each of the third units; managing a first count, which is the number of the third units in which valid data is stored, among the plurality of third units, for each of the second units; Memory system.

2. in response to a second command from the host requesting a sum of the first counts of each of the one or more second units included in the first unit assigned to the namespace; The memory controller calculates the sum; transmitting the sum to the host in response to the second command; 10. The memory system of claim 1.

3. the second unit includes one or more fourth units, and the fourth units include a plurality of the third units; The memory controller if the first logical address range is equal to or greater than the fourth unit, returning the sum to the host as a response to the second command before invalidating the data; 3. The memory system of claim 2.

4. The memory controller Identifying at least one of the second units including the third unit specified by the first logical address range; In the specified second unit, when a range equal to or larger than the fourth unit and smaller than the second unit is designated as the first logical address range, determining whether valid data is stored for each of the third units; updating the first count based on the result of the determination; 4. The memory system of claim 3.

5. The memory controller determining whether valid data is stored in each of the third units for the second units included in the first logical address range; subtracting from the first count the number of the third units determined to store valid data; 5. The memory system of claim 4.

6. The memory controller determining whether valid data is stored for each of the third units for the second units not included in the first logical address range; updating the first count with the number of the third units determined to store valid data; 5. The memory system of claim 4.

7. When the first logical address range is equal to or greater than the second unit, the memory controller updates the first count corresponding to the second unit, all of which is included in the first logical address range, to 0 before invalidating the data.

10. The memory system of claim 1.

8. The memory controller in response to a second command from the host requesting a sum of the first counts of each of the one or more second units included in the first unit assigned to the namespace, calculating the sum before performing the invalidation of the data; transmitting the sum to the host in response to the second command; 8. The memory system of claim 7.

9. the second unit includes one or more fourth units, and the fourth units include a plurality of the third units; The memory controller Identifying at least one of the second units including the third unit specified by the first logical address range; and if the first logical address range is less than the fourth unit in the specified second unit, after invalidating the data, returning the sum to the host as a response to the second command.

3. The memory system of claim 2.

10. The memory controller managing information indicating whether or not the third units designated by the first logical address range include a third unit for which data invalidation has not been executed, for each of the plurality of fourth units; 4. The memory system of claim 3.

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