Semiconductor device and display device

Abstract

To provide a driving circuit in which flicker of a screen of a display device is reduced and shortening of a data writing time and reduction of consumption power are secured, and a display device.SOLUTION: In a pulse output circuit provided in a shift register, a power source line connected to a transistor is set to a low-potential driving voltage in an output part connected to a pulse output circuit in the next stage and a power source line connected to the transistor is set to a variable potential driving voltage in an output part connected to a scan signal line. The variable potential driving voltage can be a low-potential driving voltage in a normal mode and a high-potential driving voltage or a low-potential driving voltage in a simultaneous mode. In the simultaneous mode, display scan signals can be output collectively at the same timing to a plurality of scan signal lines.SELECTED DRAWING: Figure 1

Description

[Technical Field]

[0001] The present invention relates to a driver circuit (also called a pulse output circuit or a shift register). The present invention relates to a display device having a driving circuit formed on the same substrate as the element part. The present invention relates to an electronic device equipped with the above. [Background technology]

[0002] With the spread of large display devices such as LCD TVs, there is a demand for higher value-added products. In particular, the channel region is made of amorphous semiconductor. By using thin film transistors (TFTs), the scanning line driving circuit and other components are mounted on the same substrate as the pixel section. The technology that configures the drive circuit is being actively developed because it contributes greatly to reducing costs and improving reliability. Development is underway.

[0003] Furthermore, reducing the power consumption of display devices is also a major issue. In an image display device having a display function, the output of an ON signal to each scanning signal line is sequentially changed from Based on the control signal for shifting to the collective output, each of the plurality of scanning signals corresponding to the non-display area is output. The output of an ON signal to each scanning signal line is controlled so that the display scanning signal is output to all lines at once. An image display circuit is disclosed that is provided with an output control block that controls the force. [Prior art documents] [Patent documents]

[0004] [Patent Document 1] Japanese Patent Application Laid-Open No. 2001-343928 Summary of the Invention [Problem to be solved by the invention]

[0005] In a display device, a gate is formed for each pixel line of a display panel in which a plurality of pixels are arranged in a matrix. The gate lines (scanning lines) are provided, and the period of one horizontal period of the display scanning signal is ) are selected and driven in sequence to update the displayed image. A gate line driving circuit (scanning line) for sequentially selecting and driving gate lines (scanning lines) The driving circuit is a shifter that performs a shift operation that completes one cycle in one frame period of the display scanning signal. Conventionally, the shift register in this driving circuit has a certain The output signal is controlled by counting up every period. Of course, all scan lines (signal lines) must be output, which increases the data writing time. There was a problem.

[0006] One embodiment of the present invention is to reduce screen flicker in a display device and shorten the data writing time. One of the objectives of the present invention is to provide a driver circuit and a display device that ensure reduction in size and power consumption. do. [Means for solving the problem]

[0007] In one aspect of the present invention, a first electrode is electrically connected to a first input terminal, and a second electrode is a first transistor electrically connected to the output terminal of the transistor, and a gate electrode electrically connected to the first node; a transistor having a first electrode electrically connected to the first output terminal and a second electrode electrically connected to the first a second transistor electrically connected to the power supply line and having a gate electrode electrically connected to the second node; a first electrode electrically connected to a first input terminal and a second electrode electrically connected to a second output terminal; a third transistor electrically connected to the terminal and having a gate electrode electrically connected to the first node; a transistor, the first electrode of which is electrically connected to the second output terminal and the second electrode of which is electrically connected to the second power supply line; a fourth transistor electrically connected to the first node and having a gate electrode electrically connected to the second node; and a control section for controlling the level of a potential to be applied to the first node and the second node. The power supply line 2 is supplied with a high potential drive voltage or a low potential drive voltage by switching. The pulse output circuit is characterized by the above.

[0008] One embodiment of the present invention is a semiconductor device including first to eleventh transistors and a first input terminal. The power supply line includes a first power supply line through a sixth power supply line. The first transistor is electrically connected to the power supply line, and the first electrode of the first transistor is electrically connected to the first input terminal. and a second electrode electrically connected to a first electrode of a second transistor, The electrode is electrically connected to the gate electrode of the third transistor and the first electrode of the seventh transistor. the second transistor has a second electrode electrically connected to the first power supply line and a gate The gate electrode of the fourth transistor, the gate electrode of the sixth transistor, the gate electrode of the ninth transistor a second electrode of the tenth transistor, a second electrode of the eleventh transistor, a third transistor having a first electrode electrically connected to the first input terminal; a first electrode electrically connected to the second output terminal; a fourth electrode electrically connected to the second output terminal; The transistor has a first electrode electrically connected to the second output terminal and a second electrode electrically connected to the second power supply line. The fifth transistor has a first electrode electrically connected to the second electrode of the seventh transistor. the first electrode is electrically connected to a third power supply line, and the gate electrode is a sixth transistor electrically connected to the fourth input terminal and having a first electrode connected to the fifth transistor; a first electrode of the transistor electrically connected to the first power supply line; The seventh transistor has a gate electrode electrically connected to the fourth power supply line, and the eighth transistor has a gate electrode electrically connected to the fourth power supply line. The first electrode of the transistor is electrically connected to the fifth power supply line, and the second electrode of the transistor is electrically connected to the ninth power supply line. the gate electrode is electrically connected to the first electrode of the transistor, and the gate electrode is electrically connected to the second input terminal. The ninth transistor has a gate electrode electrically connected to the third input terminal, and the tenth transistor has a gate electrode electrically connected to the third input terminal. The transistor has a first electrode electrically connected to the sixth power supply line and a gate electrode electrically connected to the fifth input the eleventh transistor is electrically connected to the terminal, and the second electrode of the eleventh transistor is electrically connected to the first power supply line. the gate electrode is electrically connected to the fourth input terminal, and the second power supply line is It is a pulse output circuit in which a high potential drive voltage or a low potential drive voltage is switched and supplied. .

[0009] In one aspect of the present invention, a third power supply line, a fourth power supply line, a fifth power supply line, and a sixth power supply line are connected to each other. The potential of the line may be higher than the potential of the first power supply line and the second power supply line.

[0010] In one embodiment of the present invention, the first to eleventh transistors are N-channel The pulse output circuit may be a transistor of the same type.

[0011] One aspect of the present invention is a pulse output circuit (m-1), a pulse output circuit (m+1), a pulse output circuit (m-2), a pulse output circuit (m+1 ... ) pulse output circuit and (m+2) pulse output circuit (m≧2), The mth pulse output circuit has first to fourth signal lines for outputting clock signals. In the above, the first input terminal to the third input terminal are connected to three of the first signal line to the fourth signal line. The fourth input terminal is electrically connected to the (m-1)th pulse output terminal. The fifth input terminal is electrically connected to the first output terminal of the circuit, and the fifth input terminal is connected to the (m+2)th pulse output terminal of the circuit. and a first output terminal of the power circuit, the first output terminal being electrically connected to the (m+1)th pulse A shift register electrically connected to the fourth input terminal of the output circuit.

[0012] In one embodiment of the present invention, each of the first to fourth signal lines is sequentially delayed by a quarter period. Alternatively, the clock signal may be a shift register that outputs a clock signal. [Effects of the Invention]

[0013] According to one embodiment of the present invention, it is possible to reduce screen flicker in a display device and shorten the data writing time. It is possible to provide a driver circuit and a display device that ensure a reduction in the time and power consumption. [Brief explanation of the drawings]

[0014] [Figure 1] FIG. 2 is a diagram showing an example of a shift register and a pulse output circuit. [Figure 2] FIG. 2 is a diagram showing an example of a shift register and a pulse output circuit. [Figure 3] FIG. 2 is a diagram showing an example of a shift register and a pulse output circuit. [Figure 4] FIG. 4 is a diagram showing an example of the operation of a pulse output circuit. [Figure 5] 10A and 10B are diagrams showing a comparison of the operation of pulse output circuits; [Figure 6] FIG. 2 is a diagram showing an example of a shift register and a pulse output circuit. [Figure 7] FIG. 4 is a diagram showing an example of the operation of a pulse output circuit. [Figure 8] 10A and 10B are diagrams showing a comparison of the operation of pulse output circuits; [Figure 9]10A and 10B are diagrams showing a comparison of the operation of pulse output circuits; [Figure 10] 1A to 1C illustrate one embodiment of a display device. [Figure 11] 1A to 1C illustrate one embodiment of a display device. [Figure 12] 1A to 1C illustrate one embodiment of a display device. [Figure 13] 1A to 1C illustrate one embodiment of a display device. [Figure 14] 1A to 1C illustrate one embodiment of a display device. [Figure 15] 1A and 1B are diagrams illustrating electronic devices. [Figure 16] 1A and 1B are diagrams illustrating electronic devices. [Figure 17] 1A and 1B are diagrams illustrating electronic devices. [Figure 18] 1A to 1C illustrate one mode of a transistor that can be used in a display device. [Figure 19] 1A to 1C illustrate one mode of a manufacturing method of a transistor that can be used in a display device. DETAILED DESCRIPTION OF THE INVENTION

[0015] Hereinafter, an embodiment of the present invention will be described with reference to the drawings. It is to be understood that the invention may be practiced in various different ways without departing from the spirit and scope thereof. It will be readily understood by those skilled in the art that various changes can be made in form and detail. It should not be construed as being limited to the description of the present embodiment. In the present invention, reference numerals indicating the same objects are common among different drawings.

[0016] In the drawings referred to in the following description, transistors are shown in both solid and dashed lines in the same drawing. When the transistor is expressed by both lines and solid lines, the transistor is in a conducting state. When the dashed line indicates that the transistor is in the ON state, This indicates that the circuit is in a non-conducting state (off state).

[0017] (Embodiment 1) In this embodiment, an example of a pulse output circuit and a shift register including the pulse output circuit is This will be explained with reference to FIG.

[0018] The shift register shown in this embodiment has first pulse output circuits 10_1 to n-th pulse output circuits 10_2 to 10_3. and a first signal line 11 to a fourth signal line 12 that output clock signals. 14 (see FIG. 1A). The first signal line 11 transmits a first clock signal (CK1 ), the second signal line 12 outputs a second clock signal (CK2), and the third signal line 13 outputs a third clock signal (CK3), and a fourth signal line 14 outputs a fourth clock signal Output (CK4).

[0019] The clock signal (CK) is a signal that alternates between high and low levels at regular intervals. Here, the first clock signal (CK1) to the fourth clock signal (CK4) are, in order: In this embodiment, the first clock signal (CK1) to the fourth clock signal (CK2) are delayed by 1 / 4 period. The clock signal (CK4) is used to control the driving of the pulse output circuit.

[0020] Each of the first pulse output circuit 10_1 to the n-th pulse output circuit 10_n has a first input terminal terminal 21, a second input terminal 22, a third input terminal 23, a fourth input terminal 24, a first output terminal The first input terminal 25, the fifth input terminal 26, and the second output terminal 27 (see FIG. 1(B)).

[0021] The first input terminal 21, the second input terminal 22, and the third input terminal 23 are connected to the first signal line 11. 1, the first to fourth signal lines 14 are electrically connected to the first to fourth signal lines 14. For example, in FIG. The pulse output circuit 10_1 has a first input terminal 21 electrically connected to a first signal line 11. The second input terminal 22 is electrically connected to the second signal line 12, and the third input terminal 23 is The second pulse output circuit 10_2 is electrically connected to the third signal line 13. The first input terminal 21 is electrically connected to the second signal line 12, and the second input terminal 22 is electrically connected to the third signal line 13. The third input terminal 23 is electrically connected to the fourth signal line 14. It continues.

[0022] In addition, in the mth pulse output circuit (m≧2) of the shift register shown in this embodiment, The fourth input terminal 24 of the m-th pulse output circuit is connected to the first output terminal 25 of the (m-1)-th pulse output circuit. The fifth input terminal 26 of the m-th pulse output circuit is electrically connected to the m+ 2) is electrically connected to the first output terminal 25 of the pulse output circuit m), The first output terminal 25 of the (m+1)th pulse output circuit is electrically connected to the fourth input terminal 24 of the (m+1)th pulse output circuit. The second output terminal 27 of the m-th pulse output circuit outputs a signal to OUT(m). .

[0023] For example, in the third pulse output circuit 10_3, the fourth pulse of the third pulse output circuit 10_3 The input terminal 24 is electrically connected to the first output terminal 25 of the second pulse output circuit 10_2. The fifth input terminal 26 of the third pulse output circuit 10_3 is connected to the fifth pulse output circuit 10_ 5 and the first output terminal 25 of the third pulse output circuit 10_3. The input terminal 25 is connected to the fourth input terminal 24 of the fourth pulse output circuit 10_4 and the first pulse output It is electrically connected to the fifth input terminal 26 of the circuit 10_1.

[0024] In addition, in the first pulse output circuit 10_1, a first start pulse is input to the fourth input terminal 24. (SP1) is input. In addition, in the (n-1)th pulse output circuit 10_(n-1), A second start pulse (SP2) is input to the fifth input terminal 26. In the start output circuit 10_n, a third start pulse (SP3) is input to the fifth input terminal 26. The second start pulse (SP2) and the third start pulse (SP3) are The signal may be an externally input signal or may be a signal generated separately within the driving circuit. good.

[0025] Next, the specific configurations of the first pulse output circuit 10_1 to the n-th pulse output circuit 10_n will be described. This section explains the following.

[0026] FIG. 1(C) is a schematic diagram of a pulse output circuit according to the invention disclosed in this specification. Each of the pulse output circuits 10_1 to 10_n controls the node f1. A first transistor 101 and a second transistor 102 output a first clock signal (CK1) to an output line. and the third transistor 103, and the low potential drive voltage (VSS1) is generated by controlling the node f2. A second transistor 102 outputs to the output line and a variable potential drive voltage (VSS2) an output section 70 comprising a fourth transistor 104 outputting to the input line; and a control unit 60 for controlling the node f2. The fourth input terminal 24, the fifth input terminal 26, the first output terminal 25, and the second output terminal 27 are connected to the The first power supply line 31, the second power supply line 32, and the eighth power supply line 38 are connected to the first transistor 1. A signal is supplied to the first to fourth transistors 101 to 104.

[0027] The first transistor 101 has a first electrode electrically connected to the first input terminal 21 and a The second electrode is electrically connected to the first electrode of the second transistor 102, and the gate electrode is connected to the The second transistor 102 has a first electrode electrically connected to the first the first electrode is electrically connected to the output terminal 25, the second electrode is electrically connected to the first power supply line 31, The gate electrode of the third transistor 103 is electrically connected to the node f2. The first electrode is electrically connected to the first input terminal 21, and the second electrode is connected to the fourth transistor 10 4, and the gate electrode is electrically connected to node f1. The fourth transistor 104 has a first electrode electrically connected to the second output terminal 27, The second electrode is electrically connected to the second power supply line 32, and the gate electrode is electrically connected to the node f2. is connected.

[0028] As shown in FIG. 2, the voltage shift applied to the second transistor 102 at the node f2 is To reduce the stress, the gates of the second transistor 102 and the fourth transistor 104 are A transistor 100 may be provided between the gate electrodes. The gate electrode is electrically connected to the seventh power supply line 37 .

[0029] As shown in FIG. 6C, the control unit 60 controls the fifth transistor 105 to the eleventh transistor 106. It is composed of node f1 and node f2. For the sake of convenience, the control unit 60 is configured as shown in FIG. As an example, only the case where the control unit 60 has the same configuration as the control unit 60 is shown in the timing chart of FIG. The operation of the pulse output circuit will be explained with reference to the timing diagram shown in Figure 4. In the timing chart, there are a first period 51, a second period 52, a third period 53, and a fourth period The first period 51 is divided into a first period 52 and a second period 53. The first period 52 is divided into a first period 53 and a second period 54. The first period 52 is divided into a second period 54 and a third period 55. The first period 52 is divided into a first period 53 and a fourth period 54. The second period 53 is divided into a second period 54 and a fifth period 55. The first period 51 is divided into a first period The start time of the second period 52 is represented by b, the start time of the third period 53 is represented by c, and the start time of the fourth period 54 is represented by The time between the first period 51 and the second period 52 is d, and the start time of the fifth period 55 is e. The first period 53, the period t1 from 61 to 62 including the fourth period 54, is the normal mode, and the fifth period The period t2 from 62 to 63 in the interval 55 is the simultaneous mode. In the following description, the first transistor The first to fourth transistors 101 to 104 are N-channel transistors, and the gate voltage When the voltage between the electrode and source electrode (Vgs) exceeds the threshold voltage (Vth), the transistor becomes conductive. This shall be the case.

[0030] The output of the first pulse output circuit 10_1 shown in FIG. 1(A) will be described. The clock output circuit 10_1 has a first input terminal 21 that supplies a first clock signal (CK1). The second input terminal 22 is electrically connected to the first signal line 11, which is connected to the second clock signal (C K2), and the third input terminal 23 is electrically connected to the second signal line 12 that supplies the third clock. It is electrically connected to a third signal line 13 that supplies a lock signal (CK3).

[0031] The first power supply line 31 is supplied with a low potential drive voltage (VSS1), and the second power supply line 3 2 is supplied with a variable potential drive voltage (VSS2), and the eighth power supply line 38 is supplied with a high potential drive voltage (VDD) is supplied, where VSS1 is smaller than VDD and VSS2 is VDD or less. In addition, the first clock signal (CK1) to the fourth clock signal ( CK4) is a signal that alternates between H and L levels at regular intervals, but the H level potential All the L-level potentials are VDD, and all the L-level potentials are VSS1. For simplicity, VSS1=0 is used, but this is not limiting.

[0032] In the first period 51, the first start pulse (SP1) becomes H level (a in FIG. 4). ) Node f1 is charged and the potential rises, and node f2 is discharged to VSS1. Therefore, the first transistor 101 and the third transistor 103 are turned on, and the second transistor The second transistor 102 and the fourth transistor 104 are turned off. The potentials of the first output terminal 25 and the second output terminal 27 are determined by the first clock signal (CK 1) becomes the L level (see Figure 5(A)).

[0033] In the second period 52, the first clock signal (CK1) becomes H level (b in FIG. 4). The floating node f1 is connected to the gate electrode and source electrode of the third transistor 103. Bootstrapping occurs due to the effect of capacitive coupling caused by parasitic capacitance formed at the overlapping portion between the two. As a result, the potential of the node f1 further increases, and the first transistor 101 and The third transistor 103 is fully turned on. The potentials of the first output terminal 25 and the second output terminal 27 become H level (see FIG. 5B).

[0034] At this time, since the node f2 is maintained at the L level, the first output terminal 25 and the second When the potential of the output terminal 27 rises from the L level to the H level, the node f2 and the first output To suppress problems caused by capacitive coupling between the terminal 25 and the node f2 and the second output terminal 27. can be done.

[0035] In the third period 53, the first start pulse (SP1) changes from H level to L level. (c in FIG. 4) The first clock signal (CK1) maintains the H level following the second period 52. Since the potential of the node f1 does not change following the second period 52, the first transistor The first transistor 101 and the third transistor 103 remain on. The potentials of the first output terminal 25 and the second output terminal 27 in 53 become H level. See Figure 5(C).

[0036] In the fourth period 54, the first clock signal (CK1) changes from H level to L level ( In FIG. 4(d), when a reset signal (RESET) is input, the potential of the node f1 becomes The potential of the node f2 rises. The first and third transistors 101 and 103 are turned off, and the second and fourth transistors 102 and 103 are turned on. Therefore, the first output terminal 25 and the second output terminal 104 are turned on during the fourth period 54. The potential of the second output terminal 27 becomes L level (see FIG. 5(D)).

[0037] Next, in the fifth period 55, when switching from the normal mode to the simultaneous on mode, the second The potential of the power supply line 32 (VSS2) is changed from L level to H level (e in FIG. 4). The start pulse (SP1) and the reset signal (RESET) remain at the L level. At this time, a high-level potential is supplied to the second power supply line 32, and the floating node The gate electrode f2 is formed in the overlapping portion between the gate electrode and the source electrode of the fourth transistor 104. This results in bootstrap due to the capacitive coupling effect of the parasitic capacitance. The rise in the potential of the second transistor 102 allows the fourth transistor 104 to be completely turned on. The first power supply line 31 is at the L level. The potential of the terminal 25 becomes L level, and the potential of the second output terminal 27 becomes H level.

[0038] In the fifth period 55, when the second power supply line 32 is set to the H level, the second transistor In order to reduce the voltage stress on the capacitor 102, A transistor 100 may be provided in node f2.

[0039] In this way, the first power supply line 31 is connected to the second electrode of the second transistor 102, and the second power supply line 32 is electrically connected to the second electrode of the fourth transistor 104. During the period in which the potential of the fourth input terminal 24 and the potential of the fifth input terminal 26 are held at the L level, The potential of the second electrode of the second transistor 102 and the potential of the second electrode of the fourth transistor 104 are The potentials of the first and second electrodes can be controlled completely independently without being dependent on each other. In this case, in the output section 70 of the pulse output circuit provided in the shift register, A second transistor electrically connected to a first output terminal 25 connected to the pulse output circuit. The potential supplied to the first power supply line 31 from the first power supply line 32 is set to a low potential drive voltage (VSS1), a fourth transistor electrically connected to a second output terminal 27 connected to each scanning signal line; The potential supplied to 104 from the second power supply line 32 is set as a variable potential drive voltage (VSS2).

[0040] In normal mode, the variable potential drive voltage (VSS2) is set to the low potential drive voltage (VSS1). In simultaneous ON mode, the high potential drive voltage (VDD) is used, and in simultaneous OFF mode, By setting the low potential drive voltage (VSS1), the potential of the second output terminal 27 is set to the second potential It can be freely controlled by changing the potential of the source line 32. The ON signal (or OFF signal) is simultaneously sent to the second output terminal 27 connected to the signal).

[0041] According to the above configuration and method, in the drive circuit of the image display device, a specific color (e.g. When displaying (all black or all white), multiple scanning signal lines are simultaneously Since it is possible to output a display scanning signal (ON signal or OFF signal), data writing This allows the time to be shortened, and also ensures a period during which the scanning signal line driver is stopped after the batch display. This makes it possible to reduce the power consumption of the scanning signal line driver during this period. High-speed operation reduces the burden on the drive circuit, reducing screen flicker. This can be prevented.

[0042] FIG. 6 shows a specific circuit configuration of the pulse output circuit shown in FIG. 1(C). .

[0043] The shift register according to the invention disclosed in this specification includes a first pulse output circuit 10_1 to a second pulse output circuit 10_2. n pulse output circuits 10_n (n≧2) and first signal lines 11 to The first signal line 11 is a first clock signal line. The first signal line 11 outputs a second clock signal (CK1), and the second signal line 12 outputs a second clock signal (CK2). The third signal line 13 outputs a third clock signal (CK3), and the fourth signal line 14 outputs a fourth clock signal (CK4). Outputs the clock signal (CK4).

[0044] The clock signal (CK) is a signal that alternates between high and low levels at regular intervals. Here, the first clock signal (CK1) to the fourth clock signal (CK4) are, in order: In this embodiment, the first clock signal (CK1) to the fourth clock signal (CK2) are delayed by 1 / 4 period. The clock signal (CK4) is used to control the driving of the pulse output circuit.

[0045] Each of the first pulse output circuit 10_1 to the n-th pulse output circuit 10_n has a first input terminal terminal 21, a second input terminal 22, a third input terminal 23, a fourth input terminal 24, a first output terminal The first input terminal 25, the fifth input terminal 26, and the second output terminal 27 (see FIG. 6(B)).

[0046] The first input terminal 21, the second input terminal 22, and the third input terminal 23 are connected to the first signal line 11. 6, the first to fourth signal lines 14 are electrically connected to the first to fourth signal lines 14. The pulse output circuit 10_1 has a first input terminal 21 electrically connected to a first signal line 11. The second input terminal 22 is electrically connected to the second signal line 12, and the third input terminal 23 is The second pulse output circuit 10_2 is electrically connected to the third signal line 13. The first input terminal 21 is electrically connected to the second signal line 12, and the second input terminal 22 is electrically connected to the third signal line 13. The third input terminal 23 is electrically connected to the fourth signal line 14. It continues.

[0047] In addition, in the mth pulse output circuit (m≧2) of the shift register shown in this embodiment, The fourth input terminal 24 of the m-th pulse output circuit is connected to the first output terminal 25 of the (m-1)-th pulse output circuit. The fifth input terminal 26 of the m-th pulse output circuit is electrically connected to the m+ 2) is electrically connected to the first output terminal 25 of the pulse output circuit m), The first output terminal 25 of the (m+1)th pulse output circuit is electrically connected to the fourth input terminal 24 of the (m+1)th pulse output circuit. The second output terminal 27 of the m-th pulse output circuit outputs a signal to OUT(m). .

[0048] For example, in the third pulse output circuit 10_3, the fourth pulse of the third pulse output circuit 10_3 The input terminal 24 is electrically connected to the first output terminal 25 of the second pulse output circuit 10_2. The fifth input terminal 26 of the third pulse output circuit 10_3 is connected to the fifth pulse output circuit 10_ 5 and the first output terminal 25 of the third pulse output circuit 10_3. The input terminal 25 is connected to the fourth input terminal 24 of the fourth pulse output circuit 10_4 and the first pulse output It is electrically connected to the fifth input terminal 26 of the circuit 10_1.

[0049] In addition, in the first pulse output circuit 10_1, a first start pulse is input to the fourth input terminal 24. (SP1) is input. In addition, in the (n-1)th pulse output circuit 10_(n-1), A second start pulse (SP2) is input to the fifth input terminal 26. In the start output circuit 10_n, a third start pulse (SP3) is input to the fifth input terminal 26. The second start pulse (SP2) and the third start pulse (SP3) are The signal may be an externally input signal or may be a signal generated separately within the driving circuit. good.

[0050] Next, the specific configurations of the first pulse output circuit 10_1 to the n-th pulse output circuit 10_n will be described. This will be explained in more detail.

[0051] Each of the first pulse output circuit 10_1 to the n-th pulse output circuit 10_n is a first transformer. The transistors 101 to 111 are also included (see FIG. 6C). The first input terminal 21, the second input terminal 22, the third input terminal 23, and the fourth input terminal 24, the fifth input terminal 26, the first output terminal 25, the second output terminal 27, and the first The power supply line 31 to the sixth power supply line 36 are connected to the first transistor 101 to the eleventh transistor 11. A signal is supplied to 1.

[0052] The first transistor 101 has a first electrode electrically connected to the first input terminal 21 and a The second electrode is electrically connected to the first electrode of the second transistor 102, and the gate electrode is The gate electrode of the third transistor 103 and the first electrode of the seventh transistor 107 are electrically connected to each other. The second transistor 102 has a second electrode electrically connected to the first power supply line 31. The gate electrodes of the fourth transistor 104 and the sixth transistor 105 are electrically connected to each other. the gate electrode of the ninth transistor 106, the second electrode of the ninth transistor 109, the a second electrode of the eleventh transistor 110 and a first electrode of the eleventh transistor 111; The third transistor 103 has a first electrode electrically connected to the first input terminal 21. The first electrode is electrically connected to the second output terminal 27. The first electrode of the capacitor 104 is electrically connected to the second output terminal 27, and the second electrode of the capacitor 104 is electrically connected to the second output terminal 28. The fifth transistor 105 has a first electrode connected to the third The second electrode is electrically connected to the power supply line 33 of the seventh transistor 107. and the gate electrode is electrically connected to the fourth input terminal 24. The first electrode of the transistor 106 is electrically connected to the second electrode of the fifth transistor 105. The first electrode is electrically connected to the first power supply line 31. The gate electrode of the transistor 107 is electrically connected to the fourth power supply line 34. The resistor 108 has a first electrode electrically connected to the fifth power supply line 35 and a second electrode electrically connected to the ninth power supply line 36. The first electrode of the transistor 109 is electrically connected to the second input terminal 2. The ninth transistor 109 has a gate electrode electrically connected to the third input terminal The tenth transistor 110 has a first electrode electrically connected to the sixth The gate electrode is electrically connected to the fifth input terminal 26. The eleventh transistor 111 has a second electrode electrically connected to the first power supply line 31. The gate electrode is electrically connected to a fourth input terminal 24 .

[0053] In FIG. 6C, the gate electrode of the first transistor 101, the gate electrode of the third transistor 10 The connection point between the gate electrode of the third transistor and the first electrode of the seventh transistor 107 is defined as a node f1. In addition, the gate electrode of the second transistor 102 and the gate electrode of the fourth transistor 104 are a gate electrode of the sixth transistor 106; a second electrode of the ninth transistor 109; The second electrode of the tenth transistor 110 and the first electrode of the eleventh transistor 111 The connection point is assumed to be node f2.

[0054] As shown in FIG. 3, at node f2, the second transistor 102, the sixth transistor In order to reduce the voltage stress on the eleventh transistor 111, The gate electrodes of the second transistor 102 and the fourth transistor 104 are connected to the first transistor 103. In this case, the gate electrode of the transistor 100 is connected to the seventh power supply line 3 7 and electrically connected to each other.

[0055] The gate electrode of the eighth transistor 108 is connected to the second input terminal 22. A clock signal is provided to the gate electrode of the ninth transistor 109 by the third input terminal 23. The clock signal supplied to the gate electrode of the eighth transistor 108 is input to the third input terminal 23. , the gate electrode of the ninth transistor 109 is connected to the second input The wiring may be reversed so that the clock signal is provided by terminal 22. By doing so, the potentials of the second input terminal 22 and the third input terminal 23 are reduced. This reduces the potential drop of the node f2, thereby reducing the fluctuation of the potential of the node f2 and reducing noise. It is possible.

[0056] Next, the operation of the shift register shown in FIG. 1 will be described with reference to FIGS. Specifically, in the timing chart of FIG. 7, there are a first period 51, a second period 52, a third period 53, and a fourth period 54. The first period 53, the fourth period 54, and the fifth period 55 will be explained. The start time of the first period 52 is a, the start time of the second period 52 is b, the start time of the third period 53 is c, and the The start time of the fourth period 54 is d, and the start time of the fifth period 55 is e. The period t1 from 61 to 62 including the second period 52, the third period 53, and the fourth period 54 is The period t2 from 62 to 63 in the fifth period 55 is the normal mode. The period from 63 onwards will be explained assuming that the mode is back to normal mode. The first to fourth transistors 101 to 104 are N-channel transistors. When the voltage between the gate electrode and source electrode (Vgs) exceeds the threshold voltage (Vth), When this occurs, the device is in a conductive state.

[0057] Here, the output of the first pulse output circuit 10_1 will be described. The output circuit 10_1 has a first input terminal 21 that supplies a first clock signal (CK1). The second input terminal 22 is electrically connected to the signal line 11 of the first clock signal (CK2 ), and the third input terminal 23 is electrically connected to the second signal line 12 that supplies the third clock The clock signal (CK3) is electrically connected to a third signal line 13 that supplies the clock signal (CK3).

[0058] The first power supply line 31 is supplied with a low potential drive voltage (VSS1), and the second power supply line 32 is supplied with a low potential drive voltage (VSS2). The variable potential drive voltage (VSS2) (switchable between high potential drive voltage and low potential drive voltage) The third power supply line 33, the fourth power supply line 34, and the fifth power supply line 35 are connected to the power supply line 36. The sixth power supply line 36 is supplied with a high potential drive voltage (VDD). Assume that SS1 is smaller than VDD and VSS2 is equal to or smaller than VDD. The signal (CK1) to the fourth clock signal (CK4) alternate between H level and L level at regular intervals. Although it is a repeating signal, the H level potential is all VDD and the L level potential is all VSS1. In addition, for the sake of simplicity, VSS1=0 is assumed here, but this is not limiting. stomach.

[0059] In the first period 51, the first start pulse (SP1) becomes H level (a in FIG. 7). ) A fifth transistor electrically connected to the fourth input terminal 24 of the first pulse output circuit 10_1 The third clock signal ( Since CK3 is also at H level, the ninth transistor 109 is also turned on. A high potential drive voltage (VDD) is applied to the gate of the seventh transistor 107. The resistor also turns on (see FIG. 8(A)).

[0060] At this time, the fifth transistor 105 and the seventh transistor 107 are on. The potential of node f1 rises. Also, since the eleventh transistor 111 is on, The potential of f2 decreases.

[0061] The potential of the second electrode of the fifth transistor 105 is The electrode of the fifth transistor 10 serves as the source, and the potential VDD of the third power supply line 33 is supplied to the fifth transistor 10. VDD-Vth105 (Vth105 is the fifth threshold voltage) The potential of the node f1 is equal to the threshold voltage of the seventh transistor 105. The second electrode of the seventh transistor 107 serves as a source, and the potential of the second electrode of the seventh transistor 107 Since the value is obtained by subtracting the threshold voltage of the seventh transistor 107 from VDD-Vth 105, VDD-Vth105-Vth107 (Vth107 is the voltage of the seventh transistor 107) threshold voltage).

[0062] Here, in the first transistor 101 and the third transistor 103, The potential of the first transistor 101 is VDD-Vth105-Vth107. the potential between the gate electrode and the source electrode of the third transistor 102 and the potential between the gate electrode and the source electrode of the third transistor 103 When the potential between the electrodes is higher than the threshold voltage of each transistor, i.e., VDD- Vth105-Vth107>Vth101 (Vth101 is the first transistor 101 threshold voltage) and VDD-Vth105-Vth107>Vth103(Vth10 3 is the threshold voltage of the third transistor 103), The third transistor 103 is turned on. Therefore, the potential of the first output terminal 25 and the second The potential of the output terminal 27 becomes the L level of the first clock signal (CK1).

[0063] In the second period 52, the first input terminal 21 of the first pulse output circuit 10_1 is at the L level. The first transistor 101 and the third transistor 102 are switched from the high level to the high level (b in FIG. 7). Since the second transistor 103 is on, the first transistor 101 and the third transistor A current flows between the source and drain electrodes of the transistor 103, and the potential of the first output terminal 25 and the potential (OUT(1)) of the second output terminal 27, that is, the potential of the first transistor 101 The potential of the second electrode (in this case, the source electrode) and the second electrode of the third transistor 103 The potential of the first output terminal 25 and the potential of the second output terminal 26 (in this case, the source electrode) start to rise. As the potential of the output terminal 27 rises, the node f1, which is in a floating state, The overlapping portion between the gate electrode and source electrode of the third transistor 101 and the gate of the third transistor 103 The bootstrap is affected by the capacitive coupling due to the parasitic capacitance formed in the overlapping area between the electrode and the source electrode. The potential of the gate electrode of the first transistor 101 and the potential of the gate electrode of the third transistor 1 The potential of the gate electrode of node f1 rises. The potential of the gate electrode of the third transistor 101 and the potential of the gate electrode of the third transistor 103 are higher than VDD+Vth101 and VDD+Vth103, respectively, and the first output The potential of the terminal 25 and the potential of the second output terminal 27 are set to the H level of the first clock signal (CK1). (See Figure 8(B))

[0064] At this time, the fourth input terminal 24 of the first pulse output circuit 10_1 is connected to the first start Since the pulse (SP1) is at H level, the eleventh transistor 111 is turned on. Therefore, the potential of the first output terminal 25 and the potential of the second output terminal When the potential of the output terminal 27 rises from the L level to the H level, the node f2 and the first output terminal Therefore, the problem caused by the capacitive coupling between the node f2 and the second output terminal 27 can be suppressed. can.

[0065] Next, in the third period 53, the first start pulse (SP1) becomes L level (see FIG. c) The fifth transistor 105 and the eleventh transistor 111 are turned off. The first clock signal (CK1) is maintained at the H level following the second period 52, and the second Since the potential of the node f1 does not change after the period 52, the first transistor 101 An H-level signal is supplied to the first electrode of the third transistor 103 and the first electrode of the third transistor 104. As a result, the potential of the first output terminal 25 and the potential of the second output terminal 27 become H level (see FIG. 9(A)). In the third period 53, the transistors connected to the node f2 are turned on. When the node f2 is turned off, the node f2 is in a floating state, but the potential of the first output terminal 25 and Since the potential of the second output terminal 27 does not change, the potential of the node f2, the first output terminal 25, and the node Problems caused by capacitive coupling between f2 and the second output terminal 27 can be suppressed.

[0066] As shown in FIG. 6C, a high potential drive voltage (VDD) is applied to the gate from the fourth power supply line 34. By providing the seventh transistor 107 to which the voltage is applied, bootstrap operation Before and after, there are the following advantages:

[0067] A seventh transistor to whose gate a high potential drive voltage (VDD) is applied from the fourth power supply line 34. If the capacitor 107 is not present, when the potential of the node f1 rises due to the bootstrap operation, The potential of the source electrode, which is the second electrode of the transistor 105, rises to a high potential drive voltage. Then, the potential of the source electrode of the fifth transistor 105 becomes larger than the voltage (VDD). The potential is switched to the potential on the first electrode side, that is, the potential on the third power supply line 33 side. In the case of the gate electrode 105, during the period (third period 53) of FIG. 9(A), A large bias voltage is applied between the gate and drain electrodes. Voltage stress is applied, which can cause transistor degradation.

[0068] A seventh transistor 107 is provided to the gate electrode of which a high potential drive voltage (VDD) is applied. By setting the voltage at node f1 to 0, the voltage at node f1 rises due to the bootstrap operation. This can prevent the potential of the second electrode of the transistor 105 from increasing. That is, by providing the seventh transistor 107, the gate of the fifth transistor 105 The value of the negative bias voltage applied between the ground electrode and the source electrode can be reduced. Therefore, with the circuit configuration of this embodiment, the gate of the fifth transistor 105 The negative bias voltage applied between the electrode and the source electrode can also be reduced, reducing voltage stress. This can suppress deterioration of the fifth transistor 105 due to the temperature rise.

[0069] The seventh transistor 107 is provided in the same place as the fifth transistor 105. Between the second electrode and the gate electrode of the first transistor 101 and the fifth transistor 1 The first electrode and the second electrode are connected between the second electrode of the third transistor 105 and the gate electrode of the third transistor 103. It is sufficient that the electrodes are connected to each other. When configuring a shift register having a plurality of input circuits, it is necessary to use a signal circuit having more stages than the scanning line driving circuit. In the line driver circuit, the seventh transistor 107 may be omitted.

[0070] Next, in the fourth period 54, the first input terminal 21 of the first pulse output circuit 10_1 is set to L The potential of the first output terminal 25 and the potential of the second output terminal 27 become During the fourth period 54, the second input terminal 22 and the third input terminal 23 are at the H level. When a reset signal (RESET) is input, the fifth input terminal 26 also becomes the H level. The tenth transistor 110 is turned on because the tenth transistor 110 When this is turned on, the potential at node f2 is charged to VDD-Vth110. (The potential of the node f2 is changed from the potential VDD of the sixth power supply line 36 to the potential of the tenth transistor 1 Since it is the value obtained by subtracting the threshold voltage of 10, VDD-Vth110 (Vth110 is the 10th As a result, the second transistor 102 The fourth transistor 104 and the sixth transistor 106 are also turned on. When the first transistor 102 and the fourth transistor 104 are turned on, the first output terminal The potential of the second output terminal 25 and the potential of the second output terminal 27 drop and are discharged to the low potential drive voltage (VSS1). When the sixth transistor 106 is turned on, the node f1 is driven by the low potential drive voltage ( Therefore, the first transistor 101 and the third transistor 102 are discharged to VSS1. 03 is turned off, and the potential of the first output terminal 25 and the potential of the second output terminal 27 become L level. (See Figure 9(B)).

[0071] After that, in the fifth period 55, when switching from the normal mode to the all-on mode, The potential of the power supply line 32 of the second pulse is set to H level (e in FIG. 7). ), and the reset signal (RESET) remain at L level. The potential of the second electrode of the tenth transistor 110 is set to the source potential. The potential VDD of the sixth power supply line 36 is changed to the threshold voltage of the tenth transistor 110. Since the voltage is subtracted, VDD-Vth110 (Vth110 is the voltage of the 10th transistor) 10) is supplied to the second power supply line 32. As a result, the floating node f2 is connected to the gate electrode of the fourth transistor 104 and the Bootstrapping occurs due to the influence of capacitive coupling caused by the parasitic capacitance formed in the overlapping area between the source electrodes. Therefore, the potential of node f2 is VDD-Vth110+VDD. The potential of f2 rises, and the fourth transistor 104 can be turned on completely. The first power supply line 31 is at L level, and the reset signal is also held at L level. .

[0072] At this time, the first power supply line 31 is at L level, and the reset signal is also held at L level. Therefore, the potential of the first output terminal 25 in the fifth period 55 becomes L level, and the second The potential of the output terminal 27 becomes H level.

[0073] In addition, in the fifth period 55, when the second power supply line 32 is set to the H level (simultaneous ON mode ) to reduce the voltage stress on the second transistor 102, In this way, the transistor 100 may be provided in advance at the node f2.

[0074] In this way, the first power supply line 31 is connected to the second electrode of the second transistor 102, The second electrode of the eleventh transistor 111 is electrically connected to the second electrode of the eleventh transistor 106. The second power supply line 32 is electrically connected to the second electrode of the fourth transistor 104. By providing this, the potential of the fourth input terminal 24 and the potential of the fifth input terminal 26 are maintained at the L level. During this period, the potential of the second electrode of the second transistor 102 and the potential of the fourth transistor The potentials of the second electrodes in the capacitors 104 are controlled completely independently without depending on each other. In this case, the output section 70 in the pulse output circuit provided in the shift register , which is electrically connected to the first output terminal 25 connected to the pulse output circuit of the next stage. The potential supplied to the second transistor 102 from the first power supply line 31 is set to a low potential drive voltage (V SS1), and the fourth output terminals 27 electrically connected to the second output terminals 27 connected to the respective scanning signal lines. The potential supplied to the transistor 104 from the second power supply line 32 is set as a variable potential drive voltage (VS S2).

[0075] In normal mode, the variable potential drive voltage (VSS2) is set to the low potential drive voltage (VSS1). In simultaneous ON mode, the high potential drive voltage (VDD) is used, and in simultaneous OFF mode, By setting the low potential drive voltage (VSS1), the potential of the second output terminal 27 is set to the second potential It can be freely controlled by changing the potential of the source line 32. The ON signal (or OFF signal) is simultaneously sent to the second output terminal 27 connected to the signal).

[0076] According to the above configuration and method, in the drive circuit of the image display device, a specific color (e.g. When displaying (all black or all white), multiple scanning signal lines are simultaneously Since it is possible to output a display scanning signal (ON signal or OFF signal), data writing This allows the time to be shortened, and also ensures a period during which the scanning signal line driver is stopped after the batch display. This makes it possible to reduce the power consumption of the scanning signal line driver during this period. High-speed operation reduces the burden on the drive circuit, reducing screen flicker. This can be prevented.

[0077] Note that the shift register and the pulse output circuit shown in this embodiment mode may be the same as those shown in other embodiments in this specification. It can be implemented in combination with the configuration of the shift register and pulse output circuit shown in the embodiment. The present invention can also be applied to semiconductor devices. The term "semiconductor device" refers to a device that can function by utilizing semiconductor properties.

[0078] (Embodiment 2) In this embodiment mode, a shift register and a pulse output circuit different from those shown in the above embodiment modes are used. The configuration will be explained.

[0079] In the configuration shown in the above-described embodiment mode 1, all the circuits use N-channel transistors. In this example, a P-channel transistor is used. A similar configuration may be achieved by using only transistors. In the diagram shown in FIG. 6(C), the transistors are connected in the same manner, and the potential of the power supply line is This can be achieved by reversing the explanation given in the first embodiment. The invention of this embodiment is not limited to semiconductor devices. This can also be applied to placement.

[0080] In this embodiment, the contents described in each drawing may be the same as those described in another embodiment. However, they can be freely combined or replaced as appropriate.

[0081] (Embodiment 3) In this embodiment, a display device using a shift register according to the invention disclosed in this specification Examples of applicable transistors are shown below. The structure of the transistor applicable to the display device is not particularly limited, and may be, for example, a top gate Alternatively, a staggered type or planar type bottom gate structure may be used. The transistor may have a single gate structure in which one channel formation region is formed, or two It may be a double gate structure in which three gates are formed, or a triple gate structure in which three gates are formed. In addition, the semiconductor device has two gate electrode layers arranged above and below the channel region with a gate insulating layer interposed therebetween. 18A to 18D show cross-sectional structures of the transistors. An example of the transistor shown in FIGS. 18A to 18D is shown below. The advantage of using oxide semiconductors is that they are relatively simple and The advantage is that high mobility and low off-state current can be obtained in a low-temperature process. A conductor may also be used.

[0082] The transistor 410 shown in FIG. 18A is a thin film transistor having a bottom gate structure. This is also called an inverted staggered thin film transistor.

[0083] The transistor 410 includes a gate electrode layer 401, a gate electrode layer 402, a gate electrode layer 403, a gate electrode layer 404, a gate electrode layer 405, a gate electrode layer 406, a gate electrode layer 407, a gate electrode layer 408, a gate electrode layer 409 ...10, a gate electrode layer 411, a gate electrode layer 412, a gate electrode The insulating layer 402, the oxide semiconductor layer 403, the source electrode layer 405a, and the drain electrode layer 40 5b. In addition, an insulating film covering the transistor 410 and stacked on the oxide semiconductor layer 403 A protective insulating layer 409 is further formed on the insulating film 407. .

[0084] The transistor 420 shown in FIG. 18B is a channel protection type (also called a channel stop type). It is one of the bottom gate structures known as inverted staggered thin film transistors.

[0085] The transistor 420 includes a gate electrode layer 401, a gate The insulating layer 402, the oxide semiconductor layer 403, and the insulating layer 402 are formed on the oxide semiconductor layer 403. The insulating layer 427 serving as a channel protective layer, the source electrode layer 405a, and the drain electrode A protective insulating layer 409 is formed to cover the transistor 420. do.

[0086] The transistor 430 shown in FIG. 18C is a bottom-gate thin film transistor. On a substrate 400, which is a substrate having an edge surface, a gate electrode layer 401, a gate insulating layer 402, The semiconductor layer includes a source electrode layer 405a, a drain electrode layer 405b, and an oxide semiconductor layer 403. In addition, an insulating film 407 that covers the transistor 430 and is in contact with the oxide semiconductor layer 403 is provided. A protective insulating layer 409 is further formed on the insulating film 407.

[0087] In transistor 430, gate insulating layer 402 is formed between substrate 400 and gate electrode layer 400. 1, a source electrode layer 405a and a drain electrode layer 405b are provided on the gate insulating layer 402. The gate insulating layer 402 and the source electrode layer 405b are provided in contact with each other. 5a, an oxide semiconductor layer 403 is provided over a drain electrode layer 405b.

[0088] The transistor 440 shown in FIG. 18D is a thin film transistor with a top gate structure. The transistor 440 is formed on a substrate 400 having an insulating surface, an insulating layer 437, an oxide a compound semiconductor layer 403, a source electrode layer 405a, a drain electrode layer 405b, and a gate insulating layer 402, a gate electrode layer 401, a source electrode layer 405a, and a drain electrode layer 405b. The wiring layers 436a and 436b are provided adjacent to each other and are electrically connected to each other.

[0089] In this embodiment, as described above, the oxide semiconductor layer 403 is used as the semiconductor layer. The oxide semiconductor used for the oxide semiconductor layer 403 is at least In, Ga, Sn, and Zn. For example, the oxide of a quaternary metal, In-Sn -Ga-Zn-O oxide semiconductors and In-Ga-Zn-O, which is an oxide of a ternary metal Oxide semiconductors, In-Sn-Zn-O oxide semiconductors, In-Al-Zn-O oxide semiconductors Conductor, Sn-Ga-Zn-O oxide semiconductor, Al-Ga-Zn-O oxide semiconductor, S n-Al-Zn-O oxide semiconductors and In-Zn-O oxides, which are binary metal oxides Semiconductors, Sn-Zn-O oxide semiconductors, Al-Zn-O oxide semiconductors, Zn-Mg- O-based oxide semiconductors, Sn-Mg-O-based oxide semiconductors, In-Mg-O-based oxide semiconductors, In-Ga-O-based oxide semiconductors, In-O-based oxide semiconductors, which are oxides of single-component metals, S nO-based oxide semiconductors, Zn-O-based oxide semiconductors, etc. can be used. The oxide semiconductor may contain elements other than In, Ga, Sn, and Zn, such as SiO2.

[0090] For example, an In-Ga-Zn-O oxide semiconductor is a semiconductor containing indium (In), gallium (G a) It means an oxide semiconductor containing zinc (Zn), and the composition ratio is not important.

[0091] The oxide semiconductor layer 403 is formed of a material having the chemical formula InMO3(ZnO) m (m>0) A thin film can be used, where M is one selected from Ga, Al, Mn, and Co. For example, M may be Ga, Ga and Al, Ga and Mn, or or Ga and Co.

[0092] In addition, when an In-Zn-O-based material is used as the oxide semiconductor, the composition of the target to be used The atomic ratio of In:Zn is 50:1 to 1:2 (converted to molar ratio, In2O3 In:ZnO=25:1 to 1:4), preferably In:Zn=20:1 to 1:1 (molar ratio) In terms of conversion, In2O3:ZnO=1:2 to 10:1), more preferably In:Zn=1 0.5:1 to 15:1 (converted to a molar ratio of In2O3:ZnO = 3:4 to 15:2) For example, the target used to form an In-Zn-O based oxide semiconductor has an atomic ratio of When In:Zn:O=X:Y:Z, Z>1.5X+Y.

[0093] The transistors 410, 420, 430, and 440 including the oxide semiconductor layer 403 are in an off state. Therefore, the current value (off-state current value) in the OFF state can be reduced. The signal retention time can be extended, and the write interval can also be set longer when the power is on. Therefore, the frequency of refresh operations can be reduced, which is effective in reducing power consumption. To bear fruit.

[0094] The transistors 410, 420, 430, and 440 including the oxide semiconductor layer 403 are Since a relatively high field effect mobility can be obtained, high speed driving is possible. By using the transistor in a pixel portion, a high-quality image can be provided. The transistor can be separately formed in a driver circuit portion or a pixel portion over the same substrate. This allows the number of parts in the display device to be reduced.

[0095] There is no significant limitation on the substrate that can be used for the substrate 400 having an insulating surface. A glass substrate such as borosilicate glass or aluminoborosilicate glass is used.

[0096] In the bottom-gate transistors 410, 420, and 430, an insulating film serving as a base film The base film may be provided between the substrate and the gate electrode layer. It has a function of blocking the light and is made of silicon nitride film, silicon oxide film, silicon nitride oxide film, or oxynitride film. The insulating film may be formed by a laminate structure of one or more films selected from silicon dioxide films.

[0097] The material of the gate electrode layer 401 is molybdenum, titanium, chromium, tantalum, tungsten, Metallic materials such as aluminum, copper, neodymium, scandium, etc., or alloys containing these as their main components The gold material can be used to form a single layer or a multilayer structure.

[0098] The gate insulating layer 402 is formed by depositing silicon oxide using a plasma CVD method, a sputtering method, or the like. silicon layer, silicon nitride layer, silicon oxynitride layer, silicon nitride oxide layer, aluminum oxide layer , an aluminum nitride layer, an aluminum oxynitride layer, an aluminum nitride oxide layer, or an aluminum oxide layer. The aluminum layer can be formed as a single layer or a stacked layer. For example, the first gate insulating layer and the Then, a silicon nitride layer (SiN) with a thickness of 50 nm to 200 nm was formed by plasma CVD. y (y>0)) and a second gate insulating layer having a thickness of 5 nm was formed on the first gate insulating layer. A silicon oxide layer (SiO x (x>0)) to form a total film thickness of 20 The gate insulating layer is 0 nm thick.

[0099] The conductive film used for the source electrode layer 405a and the drain electrode layer 405b is, for example, Al , Cr, Cu, Ta, Ti, Mo, W, or the above elements are contained An alloy film of Al or an alloy film of a combination of the above elements can be used. A high melting point metal such as Ti, Mo, W, etc. is placed on either or both of the upper and lower sides of the metal layer such as Cu. It is also possible to use a laminated structure of layers. Heat resistance is achieved by using Al material containing elements that prevent heat buildup (Si, Nd, Sc, etc.). It is possible to improve

[0100] The wiring layer 436a connected to the source electrode layer 405a and the drain electrode layer 405b, The conductive film such as 6b is also made of the same material as the source electrode layer 405a and the drain electrode layer 405b. It can be used.

[0101] In addition, the source electrode layer 405a, the drain electrode layer 405b (wiring formed in the same layer as this) The conductive film (including the layer) may be formed of a conductive metal oxide. The oxides include indium oxide (In2O3), tin oxide (SnO2), zinc oxide (ZnO ), indium oxide tin oxide alloy (In2O3-SnO2, abbreviated as ITO), Indium zinc oxide alloy (In2O3-ZnO) or these metal oxide materials with silicon oxide It is possible to use a material containing kon.

[0102] The insulating films 407, 427, and 437 are typically silicon oxide films, silicon oxynitride films, or oxide films. An inorganic insulating film such as an aluminum nitride film or an aluminum oxynitride film can be used. do.

[0103] The protective insulating layer 409 is made of a silicon nitride film, an aluminum nitride film, a silicon nitride oxide film, a nitride An inorganic insulating film such as an aluminum oxide film can be used.

[0104] In addition, a planarizing insulating film is formed on the protective insulating layer 409 to reduce surface irregularities caused by the transistor. The planarization insulating film may be formed using a material such as polyimide, acrylic, or benzocyclobutene. In addition to the above organic materials, low dielectric constant materials (low In addition, multiple insulating films made of these materials can be stacked. A planarization insulating film may be formed by performing the above-mentioned process.

[0105] As described above, in this embodiment, a transistor including an oxide semiconductor layer having a low off-state current value is By using the capacitor, a display device with low power consumption can be provided.

[0106] (Fourth embodiment) In this embodiment, an example of a transistor including an oxide semiconductor layer and a manufacturing method thereof will be described with reference to FIGS. The same parts as those in the above embodiment or parts having similar functions and steps will be described in detail. This can be done in the same way as in the above embodiment, and the repeated explanation will be omitted. A detailed description of this will be omitted.

[0107] 19A to 19E show examples of cross-sectional structures of transistors. 18A.) The transistor 510 shown in FIG. 18A has a bottom This is an inverted staggered thin film transistor with a gate structure.

[0108] The oxide semiconductor used in the semiconductor layer of this embodiment is an oxide semiconductor that does not contain hydrogen as an n-type impurity. and purify the oxide semiconductor to minimize the amount of impurities other than the main component. This results in an i-type (intrinsic) oxide semiconductor or an oxide semiconductor that is as close to i-type (intrinsic) as possible. That is, instead of adding impurities to make it i-type, impurities such as hydrogen and water are By removing as much as possible, it is possible to obtain a highly purified i-type (intrinsic semiconductor) or something close to it. Therefore, the oxide semiconductor layer included in the transistor 510 is highly purified and and an oxide semiconductor layer that has been made electrically i-type (intrinsic).

[0109] In addition, there are very few carriers (close to zero) in highly purified oxide semiconductors. Rear density is 1 x 10 14 / cm 3 Less than 1 x 10 12 / cm 3 Less than or even better Preferably 1 x 10 11 / cm 3 is less than.

[0110] Since there are very few carriers in the oxide semiconductor, the off-state current of the transistor can be reduced. The smaller the off-state current, the better.

[0111] Specifically, the thin film transistor having the above-mentioned oxide semiconductor layer has a channel width of 1 μm. The off-state current density per unit area is 10 aA / μm (1×10 -17 A / μm) or less and further to 1 aA / μm (1×10 -18 A / μm) or less, even 10zA / μm(1×10 -20 It is possible to reduce the resistance to less than 1 / μm.

[0112] A transistor with an extremely small current value in an off state (off-state current value) is used in the pixel portion. This allows refreshing of still image areas with fewer image data writes. It is possible to do so.

[0113] In addition, the transistor 510 including the above-described oxide semiconductor layer has little temperature dependence of on-state current. The off-state current remains very small.

[0114] 19A to 19E, a process for manufacturing a transistor 510 on a substrate 505 will be described. Explain the process.

[0115] First, a conductive film is formed on a substrate 505 having an insulating surface, and then a first photolithography is performed. A gate electrode layer 511 is formed by a process. If the resist mask is formed by the inkjet method, a photomask can be used. Therefore, manufacturing costs can be reduced.

[0116] The substrate 505 having an insulating surface is the same as the substrate 400 shown in Embodiment 3. In this embodiment mode, a glass substrate is used as the substrate 505.

[0117] An insulating film serving as a base film may be provided between the substrate 505 and the gate electrode layer 511. , which has the function of preventing the diffusion of impurity elements from the substrate 505, and The insulating film is made of one or more films selected from a silicon film, a silicon nitride oxide film, and a silicon oxynitride film. The insulating film can be formed by a laminated structure.

[0118] The material of the gate electrode layer 511 is molybdenum, titanium, tantalum, tungsten, or aluminum. Metallic materials such as aluminum, copper, neodymium, scandium, etc., or alloy materials containing these as the main components The insulating film can be formed as a single layer or a laminate using a material.

[0119] Next, a gate insulating layer 507 is formed on the gate electrode layer 511. The gate insulating layer 507 is , a silicon oxide layer, a silicon nitride layer, etc., are formed by using a plasma CVD method, a sputtering method, etc. , silicon oxynitride layer, silicon nitride oxide layer, aluminum oxide layer, aluminum nitride layer a single layer of aluminum oxide nitride, aluminum oxide nitride, or hafnium oxide; can be formed by laminating.

[0120] The oxide semiconductor of this embodiment is an oxide semiconductor that has been made i-type or substantially i-type by removing impurities. Such highly purified oxide semiconductors have low resistance to interface states and interface charges. Since the interface between the oxide semiconductor layer and the gate insulating layer is extremely sensitive to the temperature, the interface between the oxide semiconductor layer and the gate insulating layer is important. Therefore, the gate insulating layer in contact with the highly purified oxide semiconductor is required to have high quality.

[0121] For example, high-density plasma CVD using microwaves (e.g., frequency 2.45 GHz) produces dense This is preferable because it allows the formation of a high-quality insulating layer with high dielectric strength. The close contact between the gate insulating layer and the high-quality gate insulating layer reduces the interface state and improves the interface characteristics. This is because it can be considered as such.

[0122] Of course, if a good insulating layer can be formed as a gate insulating layer, sputtering is also possible. Other film formation methods such as the plasma CVD method and the like can also be applied. Even if the insulating layer is one in which the film quality of the gate insulating layer and the interface characteristics with the oxide semiconductor are modified by In any case, it is important that the film quality as a gate insulating layer is good, and that the oxidation Any material may be used as long as it can reduce the interface state density with the compound semiconductor and form a good interface.

[0123] In addition, the gate insulating layer 507 and the oxide semiconductor film 530 contain hydrogen, a hydroxyl group, and moisture as much as possible. In order to prevent the oxide semiconductor film 530 from being broken, sputtering was performed as pretreatment before the formation of the oxide semiconductor film 530. The substrate 505 on which the gate electrode layer 511 is formed or the gate insulating layer 5 The substrate 505 on which the above-mentioned steps 107 are formed is preheated to remove hydrogen, moisture, etc. adsorbed on the substrate 505. It is preferable to desorb and exhaust the impurities. A pump is preferable. However, this preheating process can be omitted. Before the insulating layer 516 is formed, the source electrode layer 515a and the drain electrode layer 515b are heated. The same process may be carried out on the formed substrate 505 .

[0124] Next, a film having a thickness of 2 nm to 200 nm, preferably 5 nm or more, is formed on the gate insulating layer 507. An oxide semiconductor film 530 having a thickness of 30 nm or less is formed (see FIG. 19A).

[0125] Note that before the oxide semiconductor film 530 is formed by a sputtering method, argon gas is introduced. The reverse sputtering is performed by introducing the silicon dioxide into the gate insulating layer 507 to generate plasma. It is preferable to remove the powdery material (also called particles or dust) that is sputtered. In this experiment, no voltage was applied to the target side, and a voltage was applied to the substrate side using an RF power supply in an argon atmosphere. This is a method of modifying the surface by applying a plasma to the substrate. Instead, nitrogen, helium, oxygen, etc. may be used.

[0126] The oxide semiconductor used for the oxide semiconductor film 530 is selected from at least In, Ga, Sn, and Zn. For example, the quaternary metal oxide shown in the third embodiment contains one or more elements selected from the above. oxide semiconductors such as ternary metal oxides, binary metal oxides, and single metal oxides In addition, elements other than In, Ga, Sn, and Zn can be used in the oxide semiconductor. For example, SiO2 may be included.

[0127] For example, an In-Ga-Zn-O oxide semiconductor is a semiconductor containing indium (In), gallium (G a) It means an oxide semiconductor containing zinc (Zn), and the composition ratio is not important.

[0128] The oxide semiconductor layer has the chemical formula InMO3(ZnO) m A thin film expressed as (m>0) Here, M is one or more selected from Zn, Ga, Al, Mn and Co. For example, M may represent Ga, Ga and Al, Ga and Mn, or Examples of the elements include Ga and Co.

[0129] In this embodiment, the oxide semiconductor film 530 is formed using an In—Ga—Zn—O-based oxide target. The cross section at this stage corresponds to Figure 19(A). The oxide semiconductor film 530 is heated under a rare gas (typically, argon) atmosphere or an oxygen atmosphere. It can be formed by sputtering in an atmosphere of air or a mixture of rare gas and oxygen. do.

[0130] In addition, when an In-Zn-O-based material is used as the oxide semiconductor, the composition of the target to be used The atomic ratio of In:Zn is 50:1 to 1:2 (converted to molar ratio, In2O3 In:ZnO=25:1 to 1:4), preferably In:Zn=20:1 to 1:1 (molar ratio) In terms of conversion, In2O3:ZnO=1:2 to 10:1), more preferably In:Zn=1 0.5:1 to 15:1 (converted to a molar ratio of In2O3:ZnO = 3:4 to 15:2) For example, the target used to form an In-Zn-O based oxide semiconductor has an atomic ratio of When In:Zn:O=X:Y:Z, Z>1.5X+Y. Oxide target filling The filling rate is 90% or more and 100% or less, preferably 95% or more and 100% or less. By using an oxide target, the deposited oxide semiconductor film becomes a dense film.

[0131] The oxide semiconductor film 530 is formed using a sputtering gas containing hydrogen, water, a hydroxyl group, or hydrogen. It is preferable to use a high-purity gas from which impurities such as oxides have been removed.

[0132] The substrate is held in a film-forming chamber maintained in a reduced pressure state, and the substrate temperature is preferably set to 100°C or more and 600°C or less. The temperature is preferably 200°C or higher and 400°C or lower. The concentration of impurities contained in the sputtered oxide semiconductor film can be reduced. Damage caused by coating is reduced. The removed sputtering gas is introduced, and an oxide semiconductor is deposited on the substrate 505 using the target. To remove residual moisture in the deposition chamber, an adsorption type vacuum pump, e.g. For example, it is preferable to use a cryopump, an ion pump, or a titanium sublimation pump. The exhaust means is preferably a turbo pump with a cold trap added. The deposition chamber evacuated using a cryopump may contain, for example, hydrogen atoms, water (H2O), Compounds containing hydrogen atoms (and more preferably compounds containing carbon atoms) are exhausted. Therefore, the impurity concentration in the oxide semiconductor film formed in the deposition chamber can be reduced.

[0133] As an example of the film formation conditions, the distance between the substrate and the target is 100 mm, and the pressure is 0.6 Pa. The conditions were: DC power 0.5kW, oxygen (oxygen flow rate 100%) atmosphere. In addition, when a pulsed DC power supply is used, powdery substances (particles, etc.) generated during film formation are This is preferable because it can reduce the thickness (also called "slippage") and make the film thickness distribution uniform.

[0134] Next, the oxide semiconductor film 530 is subjected to a second photolithography process to form an island-shaped oxide semiconductor film. In addition, a resist mask for forming an island-shaped oxide semiconductor layer is applied to the substrate. If the resist mask is formed by the ink jet method, the photomask Since no disk is used, manufacturing costs can be reduced.

[0135] In addition, when a contact hole is formed in the gate insulating layer 507, the process is performed using an oxide semiconductor This can be done simultaneously with the processing of the film 530 .

[0136] The etching of the oxide semiconductor film 530 here can be performed by dry etching or wet etching. For example, wet etching of the oxide semiconductor film 530 may be used. The etching solution used for etching is a mixture of phosphoric acid, acetic acid, and nitric acid, or ammonia hydrogen peroxide. (31% by weight hydrogen peroxide solution: 28% by weight ammonia solution: water = 5:2:2) Alternatively, ITO07N (manufactured by Kanto Chemical Co., Ltd.) may be used.

[0137] Next, the oxide semiconductor layer is subjected to first heat treatment. The conductor layer can be dehydrated or dehydrogenated. The temperature of the first heat treatment is 400°C. The temperature is set to 750°C or higher, or 400°C or higher but lower than the distortion point of the substrate. The substrate was placed in an electric furnace, which is one of the facilities, and the oxide semiconductor layer was heated to 450°C in a nitrogen atmosphere. After the heat treatment for 1 hour, the oxide semiconductor layer was cooled to room temperature and then cooled to room temperature without being exposed to the air. The recontamination of elements is prevented, and an oxide semiconductor layer 531 is obtained (see FIG. 19B).

[0138] The heat treatment device is not limited to an electric furnace, and may be a heat treatment device using heat conduction or heat from a heat source such as a resistance heating element. A device that heats the object to be treated by radiation may be used. For example, a GRTA (Gas Reactor Tank Apparatus) apid Thermal Anneal) equipment, LRTA (Lamp Rapid T RTA (Rapid Thermal Anneal) equipment, etc. The LRTA device can be used with halogen lamps, metal halide lamps, etc. lamp, xenon arc lamp, carbon arc lamp, high-pressure sodium lamp, high-pressure mercury lamp It is a device that heats the object to be treated by radiating light (electromagnetic waves) emitted from a lamp or other lamp. The GRTA device is a device that uses high-temperature gas to perform heat treatment. Inert gases such as argon or nitrogen that do not react with the material to be treated by heat treatment An active gas is used.

[0139] For example, as the first heat treatment, a base is placed in an inert gas heated to a high temperature of 650°C to 700°C. The plate is moved and placed in the oven, heated for several minutes, and then the substrate is moved and placed in an inert gas atmosphere heated to a high temperature. You may also perform a GRTA.

[0140] In the first heat treatment, nitrogen or a rare gas such as helium, neon, or argon is used. It is preferable that the nitrogen introduced into the heat treatment device does not contain water, hydrogen, etc. Or the purity of rare gases such as helium, neon, and argon must be 6N (99.9999%) or higher. Preferably, the impurity concentration is 7N (99.99999%) or more (i.e., 1 ppm or less, It is preferable that the concentration is 0.1 ppm or less.

[0141] After the oxide semiconductor layer is heated by the first heat treatment, the oxide semiconductor layer is heated while the heating temperature is maintained or During the process of lowering the temperature from the heating temperature, high-purity oxygen gas, high-purity N2O gas, or Ultra-dry air (dew point of -40°C or less, preferably -60°C or less) may be introduced. It is preferable that the gas or N2O gas does not contain water, hydrogen, etc. The purity of the oxygen gas or NO gas introduced into the device is 6N or more, preferably 7N or more (i.e. The impurity concentration in the oxygen gas or N2O gas is 1 ppm or less, preferably 0.1 ppm or less. It is preferable to dehydrate or dehydrogenate the material by the action of oxygen gas or N2O gas. The oxide semiconductor that is reduced at the same time by the process of removing impurities through chemical treatment By supplying oxygen, which is the main component material, the oxide semiconductor layer is highly purified and electrically It becomes type i (true).

[0142] In addition, the first heat treatment of the oxide semiconductor layer is performed on the oxide semiconductor layer before it is processed into the island-shaped oxide semiconductor layer. The semiconductor film 530 can also be subjected to the first heat treatment. In that case, after the first heat treatment, The substrate is removed and subjected to a photolithography process.

[0143] In addition to the above, the first heat treatment may be performed after the oxide semiconductor layer is formed. After stacking the source electrode layer and the drain electrode layer on the insulating layer, or This may be done either after forming an insulating layer on the drain electrode layer or after forming an insulating layer on the drain electrode layer.

[0144] In addition, when a contact hole is formed in the gate insulating layer 507, the process is performed using an oxide semiconductor This may be done before or after the film 530 is subjected to the first heat treatment.

[0145] In addition, the oxide semiconductor layer is formed in two separate steps and heat-treated in two separate steps. Regardless of the material of the component, such as oxide, nitride, or metal, the film thickness is thick and the crystalline region (single crystal region) In other words, even if an oxide semiconductor layer having a crystal region with a c-axis aligned perpendicular to the film surface is formed, For example, a first oxide semiconductor film having a thickness of 3 nm to 15 nm is formed, and nitrogen, oxygen, In a rare gas or dry air atmosphere, the temperature is 450°C or higher and 850°C or lower, preferably 550°C or higher. The first heat treatment is performed at 750°C or less, and a crystalline region (including plate-like crystals) is formed in the region including the surface. Then, a second oxide semiconductor film having a thickness larger than that of the first oxide semiconductor film is formed. 2, and the oxide semiconductor film is formed at 450° C. or higher and 850° C. or lower, preferably 600° C. or higher and 70° C. or lower. Second heat treatment is performed at 0° C. or lower, and the first oxide semiconductor film is used as a seed for crystal growth. Crystal growth is performed to crystallize the entire second oxide semiconductor film, resulting in a thick crystalline region. Alternatively, an oxide semiconductor layer having a region may be formed.

[0146] Next, a source electrode layer and a drain electrode layer are formed on the gate insulating layer 507 and the oxide semiconductor layer 531. A conductive film is formed to become the source electrode layer (including wiring formed in the same layer). The conductive film used for the source electrode layer 4 shown in Embodiment 3 can be used as the conductive film for the drain electrode layer. The materials used for the drain electrode layer 405a and the drain electrode layer 405b can be used.

[0147] A resist mask is formed on the conductive film by a third photolithography process, and selective etching is performed. After forming the source electrode layer 515a and the drain electrode layer 515b by etching, The mask is removed (see FIG. 19(C)).

[0148] The third photolithography process involves exposure to ultraviolet light or KrF laser light when forming a resist mask. The source electrodes adjacent to each other on the oxide semiconductor layer 531 may be formed by using a laser beam or an ArF laser beam. The width of the gap between the bottom end of the drain electrode layer and the bottom end of the drain electrode layer determines the width of the gap between the bottom end of the drain electrode layer and the bottom end of the transistor to be formed later. The channel length L is determined. When performing exposure with a channel length L of less than 25 nm, Extreme ultraviolet rays have extremely short wavelengths ranging from a few nm to a few tens of nm. et) is used to perform exposure during resist mask formation in the third photolithography process. Extreme ultraviolet light exposure provides high resolution and a large depth of focus. The channel length L of the transistor can be set to 10 nm or more and 1000 nm or less. The operating speed of the circuit can be increased.

[0149] In addition, in order to reduce the number of photomasks and steps used in the photolithography process, The resist mask is formed by a multi-tone mask, which is an exposure mask that allows the incident light to have multiple intensities. The etching process may be performed using a resist mask formed using a multi-tone mask. The mask has a shape with multiple film thicknesses, and the shape can be further deformed by etching. Therefore, it can be used in multiple etching processes to process different patterns. Therefore, one multi-tone mask can handle at least two different patterns. Therefore, the number of exposure masks can be reduced. Since the corresponding photolithography process can also be eliminated, the process can be simplified.

[0150] Note that when the conductive film is etched, the oxide semiconductor layer 531 is etched and divided. However, it is desirable to optimize the etching conditions so that the conductive film alone does not It is difficult to achieve a condition in which the oxide semiconductor layer 531 is etched while the oxide semiconductor layer 532 is not etched at all. When the conductive film is etched, only a part of the oxide semiconductor layer 531 is etched, and the groove In some cases, the oxide semiconductor layer may have a recess (concave portion).

[0151] In this embodiment, a Ti film is used as the conductive film, and an In—Ga— Since a Zn-O-based oxide semiconductor was used, ammonia hydrogen peroxide (ammonia hydrogen peroxide) was used as an etchant. A mixture of water and hydrogen peroxide is used.

[0152] Next, plasma treatment is performed using gases such as N2O, N2, or Ar to remove the exposed The plasma treatment may be performed to remove adsorbed water or the like attached to the surface of the oxide semiconductor layer. In this case, the insulating layer 5, which serves as a protective insulating film in contact with a part of the oxide semiconductor layer, is formed without being exposed to the air. Form 16.

[0153] The insulating layer 516 has a thickness of at least 1 nm, and is formed by a method such as sputtering. The insulating layer 516 can be formed by appropriately using a method that does not mix impurities such as hydrogen. When hydrogen is contained in the oxide semiconductor layer, the hydrogen penetrates into the oxide semiconductor layer, or the oxide semiconductor layer is deformed by the hydrogen. Oxygen is extracted from the layer, and the back channel of the oxide semiconductor layer becomes low-resistance (N-type). Therefore, the insulating layer 516 should be as thin as possible. It is important that the deposition process does not use hydrogen, resulting in a hydrogen-free film.

[0154] In this embodiment, a silicon oxide film having a thickness of 200 nm is formed as the insulating layer 516 by sputtering. The substrate temperature during film formation should be between room temperature and 300°C. In this embodiment, the temperature is set to 100° C. The silicon oxide film is formed by sputtering using a rare gas (typically In an atmosphere of oxygen, or a mixture of rare gases and oxygen, In addition, a silicon oxide target or a silicon target can be used as the target. For example, a silicon target can be used in an oxygen-containing atmosphere. Silicon oxide can be formed in contact with the oxide semiconductor layer by sputtering. The insulating layer 516 formed by the insulating layer 516 is resistant to moisture, hydrogen ions, OH - It does not contain impurities such as It uses an inorganic insulating film that blocks external penetration, typically a silicon oxide film or an acid A silicon oxynitride film, an aluminum oxide film, an aluminum oxynitride film, or the like is used.

[0155] As in the case of forming the oxide semiconductor film 530, residual moisture in the deposition chamber for the insulating layer 516 is removed. To achieve this, it is preferable to use an adsorption type vacuum pump (such as a cryopump). The concentration of impurities contained in the insulating layer 516 formed in a deposition chamber evacuated using an opto-pump was reduced. In addition, the following exhaust means can be used to remove residual moisture in the deposition chamber for the insulating layer 516: A turbo pump with a cold trap may also be used.

[0156] The insulating layer 516 is formed using a sputtering gas such as hydrogen, water, a hydroxyl group, or a hydride. It is preferable to use a high-purity gas from which impurities have been removed.

[0157] Next, a second heat treatment (preferably 2 For example, the temperature is increased by heating in a nitrogen atmosphere. The second heat treatment is carried out at 250°C for 1 hour under atmospheric pressure. A part of the body layer (channel forming region) is heated while being in contact with the insulating layer 516 .

[0158] Through the above steps, the oxide semiconductor film is subjected to the first heat treatment to remove hydrogen and Impurities such as moisture, a hydroxyl group, or hydrides (also called hydrogen compounds) are intentionally removed from the oxide semiconductor layer. The oxide semiconductor is formed by eliminating impurities and reducing the impurity concentration. Therefore, the oxide semiconductor layer can be supplied with oxygen, which is one of the main components of the oxide semiconductor layer. It is purified and electrically made i-type (intrinsic).

[0159] Through the above steps, a transistor 510 is formed (see FIG. 19D).

[0160] Furthermore, when a silicon oxide layer containing many defects is used as the insulating layer 516, after the silicon oxide layer is formed, The heat treatment reduces hydrogen, moisture, a hydroxyl group, hydride, or the like contained in the oxide semiconductor layer. Impurities are diffused into the oxide insulating layer, and the impurities contained in the oxide semiconductor layer are further reduced. This has the effect of

[0161] A protective insulating layer 506 may be further formed on the insulating layer 516. For example, the protective insulating layer 506 may be formed by RF sputtering. The RF sputtering method is suitable for mass production, so it is used to form a silicon nitride film. This is a preferable film formation method. The protective insulating layer does not contain impurities such as moisture, and these impurities are easily absorbed from the outside. Inorganic insulating films such as silicon nitride and aluminum nitride are used to block the penetration of In this embodiment, the protective insulating layer 506 is formed using a silicon nitride film. (See Figure 19(E)).

[0162] In this embodiment, the substrate 505 on which the insulating layer 516 is formed is used as the protective insulating layer 506. It is heated to a temperature of 100℃ to 400℃ and then heated with a sputter containing high-purity nitrogen from which hydrogen and moisture have been removed. A silicon nitride film is formed by introducing a target gas and using a silicon semiconductor target. In this case, similarly to the insulating layer 516, the protective insulating layer 50 is removed while removing the remaining moisture in the processing chamber. It is preferable to deposit 6.

[0163] After the protective insulation layer is formed, it is further heated in air at 100°C to 200°C for 1 hour to 30 hours. This heat treatment may be carried out by maintaining a constant heating temperature. Alternatively, the temperature may be increased from room temperature to a heating temperature of 100°C or more and 200°C or less, and then reduced from the heating temperature to room temperature. The temperature drop at this temperature may be repeated several times.

[0164] In this manner, the transistor including the highly purified oxide semiconductor layer manufactured according to this embodiment By using a transistor, the current value in the off state (off current value) can be reduced. Therefore, the retention time of electrical signals such as image signals can be extended, and writing The interval can also be set longer, so the frequency of refresh operations can be reduced. Therefore, the effect of suppressing power consumption can be enhanced.

[0165] Furthermore, a transistor including a highly purified oxide semiconductor layer can have high field-effect mobility. Therefore, when the transistor is used in the pixel portion of a display device, This allows for high-quality images to be provided. Since the driver circuit section and pixel section can be separately manufactured on the board, it is possible to manufacture The number of points can be reduced.

[0166] This embodiment mode can be implemented by being appropriately combined with the configurations described in other embodiments. is.

[0167] (Embodiment 5) A display device is manufactured using the shift register shown as an example in any one of Embodiments 1 and 2. In addition, a part or the whole of the driver circuit including the shift register can be arranged in the same area as the pixel section. The display panel can be formed integrally on the same substrate to form a system-on-panel.

[0168] In FIG. 10A, a pixel portion 4002 provided on a first substrate 4001 is surrounded by a In FIG. 10A, the first substrate 400 is provided with a sealing material 4005. A separately prepared substrate is provided in an area different from the area surrounded by the sealing material 4005 on the substrate 1. A scanning line driver circuit 4004 formed on a plate using a single crystal semiconductor film or a polycrystalline semiconductor film, a signal line A driver circuit 4003 is mounted on the substrate. Various signals and potentials given to the scanning line driver circuit 4004 or the pixel portion 4002 are transmitted through the FPC ( Flexible printed circuit) Supplied from 4018a, 4018b It has been done.

[0169] In FIG. 10(B) and (C), a pixel portion 4002 is provided on a first substrate 4001, and A sealant 4005 is provided so as to surround the scanning line driver circuit 4004. A second substrate 4006 is provided on the element portion 4002 and the scanning line driver circuit 4004 . Therefore, the pixel portion 4002 and the scanning line driver circuit 4004 are formed by the first substrate 4001 and the sealing material. The display element is sealed by the second substrate 4005 and the second substrate 4006. In (C), the area surrounded by the seal material 4005 on the first substrate 4001 A single crystal semiconductor film or a polycrystalline semiconductor film is formed on a separately prepared substrate in a region different from the region. In FIG. 10(B) and (C), a signal line driver circuit 4003 is mounted. The signal line driver circuit 4003 and the scanning line driver circuit 4004 or the pixel portion 4002 are formed. The various signals and potentials are supplied from the FPC4018.

[0170] In addition, in FIGS. 10B and 10C, a signal line driver circuit 4003 is separately formed. 4001, but the present invention is not limited to this configuration. It may be formed separately and mounted, or only a part of the signal line driver circuit or a part of the scanning line driver circuit may be mounted. may be formed separately and mounted.

[0171] The method of connecting the separately formed drive circuit is not particularly limited, and may be ip On Glass) method, wire bonding method, or TAB (Tape A A method such as a fused bonding method can be used. This is an example in which a signal line driver circuit 4003 and a scanning line driver circuit 4004 are implemented by the COG method. 10B shows an example in which a signal line driver circuit 4003 is mounted by the COG method. 0(C) is an example in which the signal line driver circuit 4003 is mounted by the TAB method.

[0172] The display device also includes a panel in which a display element is sealed, and a controller for the panel. and modules in which ICs, etc., including the above are mounted.

[0173] In this specification, the term "display device" refers to an image display device, a display device, or an optical device. Also refers to connectors, such as FPC or TAB tape. Modules with TCP attached, TAB tape or TCP with a printed wiring board attached The IC (integrated circuit) is directly mounted on the module or display element using the COG method. All such modules are also included in the display device.

[0174] In addition, the pixel portion, the scanning line driver circuit, and the signal line driver circuit provided on the first substrate are The shift register shown in any one of the embodiments 1 and 2 can be applied. By applying a register, when displaying a specific color (for example, all black or all white), multiple A display scanning signal (ON signal or OFF signal) is sent to each of the multiple scanning signal lines at the same time. Since it is possible to output a signal, the time required to write data can be reduced. A period for stopping the scanning signal line driver can be secured after the display is completed, and the scanning signal line driver can be This reduces the power consumption of the drive circuitry. This reduces the load and prevents flickering on the screen.

[0175] The display element provided in the display device may be a liquid crystal element (also called a liquid crystal display element), a light-emitting element ( The light-emitting element emits light by applying a current or a voltage. This category includes elements whose brightness can be controlled, specifically inorganic EL (Electroluminescent) Luminescence, organic electroluminescence, etc. Also, electronic ink, etc. A display medium whose contrast changes depending on use can also be applied.

[0176] One embodiment of a display device will be described with reference to FIGS. 11 to 13. This corresponds to the cross-sectional view taken along line MN in FIG. 10(B).

[0177] As shown in FIGS. 11 to 13, the display device has a connection terminal electrode 4015 and a terminal electrode 4016. The connection terminal electrode 4015 and the terminal electrode 4016 are terminal electrodes of the FPC 4018. The electrode is electrically connected to the electrode via an anisotropic conductive film 4019 .

[0178] The connection terminal electrode 4015 is formed from the same conductive film as the first electrode layer 4030. 016 is a conductive film that is the same as the source and drain electrodes of the transistors 4010 and 4011. It is formed by.

[0179] A pixel portion 4002 and a scanning line driver circuit 4004 are provided on a first substrate 4001. 11 to 13, the transistors included in the pixel portion 4002 are 4004 and a transistor 4011 included in the scanning line driver circuit 4004. In FIG. 11, an insulating film 4020 is provided on the transistors 4010 and 4011. 12 and 13, an insulating layer 4021 is further provided. Note that the insulating film 4023 functions as a base film.

[0180] In this embodiment, the scanning line driver circuit 4004 is the same as that in any one of Embodiments 1 and 2. By applying the shift register shown in the figure, As a display device of this embodiment mode shown in FIGS. 11 to 13, the power consumption of the driver circuit portion is reduced. This can prevent screen flickering.

[0181] The transistor 4010 provided in the pixel portion 4002 is electrically connected to a display element. The display element is not particularly limited as long as it can display, and various display elements can be used. can be used.

[0182] FIG. 11 shows an example of a liquid crystal display device using a liquid crystal element as a display element. The liquid crystal element 4013 includes a first electrode layer 4030, a second electrode layer 4031, and a The liquid crystal layer 4008 is sandwiched between insulating layers that function as alignment layers. The second electrode layer 4031 is provided on the second substrate 4006. The first electrode layer 4030 and the second electrode layer 4031 are disposed on the liquid crystal layer 4008 side. The structure is such that the layers are stacked.

[0183] 4035 is a columnar spacer obtained by selectively etching the insulating film. The spacers are provided to control the film thickness (cell gap) of the liquid crystal layer 4008. The shape of the spacer is not limited to a columnar shape, and for example, a spherical spacer may be used. .

[0184] When liquid crystal elements are used as display elements, thermotropic liquid crystals, low molecular weight liquid crystals, polymer liquid crystals, etc. The liquid crystal material can be selected from a variety of materials, including ferroelectric liquid crystal, antiferroelectric liquid crystal, etc. This allows for the formation of cholesteric, smectic, cubic, chiral nematic phases. It shows isotropic phase equivalence.

[0185] Alternatively, a liquid crystal that exhibits a blue phase without using an alignment film may be used. The blue phase is one of the liquid crystal phases. When the temperature of cholesteric liquid crystal is increased, the phase immediately transitions from the cholesteric phase to the isotropic phase. The blue phase appears only in a narrow temperature range, so the temperature range needs to be improved. To achieve this, a liquid crystal composition containing several weight percent or more of a chiral agent is used in the liquid crystal layer. The liquid crystal composition containing the liquid crystal exhibiting the blue phase and the chiral agent has a short response time of 1 msec or less. Since the liquid crystal display is optically isotropic, no alignment treatment is required and the viewing angle dependency is small. Since there is no need to provide a rubbing treatment, the This can prevent electrostatic breakdown, which may occur during the manufacturing process, thereby reducing defects and damage to the liquid crystal display device. Therefore, it is possible to improve the productivity of the liquid crystal display device.

[0186] In addition, polymer dispersed liquid crystal (PDLC) d Crystal), polymer dispersed liquid crystal, polymer dispersed liquid crystal) or polymer network Network Liquid Crystal (PNLC) An example in which a polymer liquid crystal is used for the liquid crystal layer is shown in Figure 14. .

[0187] The display device of FIG. 14 is a reflective liquid crystal display device, and is made up of a first substrate 4001 and a second substrate 40 The liquid crystal element 4013 sandwiched between the first electrode layer 4930 and the second electrode layer 4931 has a reflective property. A second electrode layer 4931 having a light-transmitting property and a liquid crystal layer 4908 using a polymer dispersed liquid crystal are formed. The outer side of the second substrate 4006 on the viewing side (opposite to the liquid crystal layer 4908) is provided with a phase retarder. A retarder 4951 and a polarizer 4952 are provided. By laminating these layers, the film can function as a circular polarizer.

[0188] In a liquid crystal display device that includes a liquid crystal layer using polymer dispersed liquid crystal, light scattering by the liquid crystal is utilized. The liquid crystal layer 4908 is made of a polymer that forms a polymer network. The layer has liquid crystal particles dispersed therein.

[0189] In the liquid crystal layer 4908, a voltage is applied to the first electrode layer 4930 and the second electrode layer 4931. When the liquid crystal is not in the ON state (also called the OFF state), the liquid crystal particles dispersed in the polymer layer are randomly aligned. Because the refractive index of the polymer and the refractive index of the liquid crystal molecules are different, the incident light is scattered by the liquid crystal particles. Therefore, even if the polarizing plate 4952 is provided, the incident light polarized by the liquid crystal layer 4908 Because of the scattering, a certain percentage of the light passes through the polarizing plate 4952 and is emitted to the viewing side. The display that can be seen from the viewing side is a bright display. Therefore, even if the surface of the first electrode layer 4930 having reflectivity is a mirror surface, reflection does not occur. There is no loss of visibility.

[0190] On the other hand, when a voltage is applied to the first electrode layer 4930 and the second electrode layer 4931 (ON state), An electric field is formed in the liquid crystal layer 4908, and the liquid crystal molecules in the liquid crystal particles are aligned in the direction of the electric field. Since the refractive index of the molecules and the refractive index of the liquid crystal molecules on the short axis are almost the same, the incident light is scattered by the liquid crystal particles. The polarization state of the incident light is not disturbed and passes through the liquid crystal layer 4908. 2 and a retardation plate 4951, which is a quarter wave plate (λ / 4 plate), the incident light passes through the polarizer 4952 and the phase Since the light passes through the difference plate 4951 twice, a phase shift of 1 / 2 wavelength occurs. Therefore, the incident light is absorbed by the polarizing plate 4952 when it is emitted, and the surface that can be seen from the viewing side is The display will be dimmed.

[0191] The size of the storage capacitor provided in the liquid crystal display device is determined by the lead of the transistor arranged in the pixel portion. It is set so that the charge can be maintained for a predetermined period, taking into consideration the current and other factors. By using a transistor with a semiconductor film, the liquid crystal capacitance in each pixel It is sufficient to provide a storage volume having a size of 1 / 3 or less, preferably 1 / 5 or less, of the capacity of the do.

[0192] The shift register used in this embodiment is used for displaying a specific color (for example, all black display or all white display). A display scanning signal (ON signal or ON signal) is simultaneously applied to each of the plurality of scanning signal lines. Since it is possible to output a write signal, the data write time can be reduced. After the batch display, a period for stopping the scanning signal line driver can be secured, and the scanning signal The power consumption of the line driver can be reduced. This reduces the burden on the user, thereby preventing screen flicker.

[0193] There are two types of LCD displays: TN (Twisted Nematic) mode, IPS (In-P lane-Switching) mode, FFS(Fringe Field Switching) mode, ching) mode, ASM(Axially Symmetric aligned) Micro-cell mode, OCB (Optical Compensated B) refrigeration mode, FLC (Ferroelectric Liquid d Crystal) mode, AFLC (AntiFerroelectric Liq. uid Crystal) mode can be used.

[0194] Furthermore, normally black type liquid crystal display devices, for example, those employing vertical alignment (VA) mode The liquid crystal display device may be a transmission type liquid crystal display device. This is a method of controlling the arrangement of crystal molecules, and when no voltage is applied, In this method, the liquid crystal molecules are aligned vertically. There are several types of vertical alignment modes: However, for example, MVA (Multi-Domain Vertical Alignment) nt) mode, PVA (Patterned Vertical Alignment) mode, ASV mode, etc. can be used. Also, pixels can be divided into several It is a multi-layer structure that is divided into regions (sub-pixels) and designed to tilt the molecules in different directions in each region. A method known as domaining or multi-domain design can be used.

[0195] In addition, in display devices, black matrices (light-shielding layers), polarizing members, phase difference members, reflecting members, Optical members (optical substrates) such as a protection member are provided as appropriate. For example, a polarizing substrate and a retardation substrate are provided as appropriate. Alternatively, a backlight or a sidelight may be used as the light source. It's fine.

[0196] In addition, multiple light-emitting diodes (LEDs) are used as backlights, and a time-division display system is used. It is also possible to perform field sequential driving. By applying the color drive method, color display can be achieved without using a color filter. This can be done.

[0197] In addition, the display method in the pixel section uses the progressive method, interlace method, etc. In addition, the color elements controlled by pixels when displaying colors are RGB (R is It is not limited to the three colors (red, green, and blue). For example, RGBW (W stands for white). , or RGB plus one or more colors such as yellow, cyan, magenta, etc. The size of the display area may differ for each dot of the color element. The present invention is not limited to display devices with a monochromatic display, but can also be applied to display devices with a monochrome display. can.

[0198] Furthermore, a light-emitting element that utilizes electroluminescence is used as a display element included in the display device. The light-emitting element using electroluminescence can be applied to a light-emitting material They are distinguished by whether they are organic or inorganic compounds, and generally, the former are organic E The latter is called an inorganic EL element.

[0199] In an organic EL element, electrons and holes are released from a pair of electrodes by applying a voltage to the light-emitting element. are injected into the layers containing the light-emitting organic compounds, causing a current to flow. The recombination of the electrons and holes creates an excited state in the light-emitting organic compound. The excited state is then converted to the ground state, at which point light is emitted. Such a light-emitting element is called a current-excited light-emitting element.

[0200] Inorganic EL elements are divided into dispersion-type inorganic EL elements and thin-film-type inorganic EL elements depending on the element structure. Dispersion-type inorganic EL elements have a light-emitting layer in which particles of light-emitting material are dispersed in a binder. The emission mechanism is a donor-acceptor interaction that utilizes the donor and acceptor levels. Thin-film inorganic EL devices sandwich the light-emitting layer between dielectric layers. Furthermore, this structure is sandwiched between electrodes, and the light emission mechanism utilizes the inner-shell electron transition of metal ions. In this example, the light emitting element is an organic EL element. do.

[0201] The light emitting element only needs to have at least one of the pair of electrodes transparent in order to extract light. The transistor and the light emitting element are formed on the substrate, and light is extracted from the surface opposite to the substrate. There are two types of emission: top emission, which emits light from the surface on the substrate side, bottom emission, which emits light from the surface on the substrate side, and emission from the surface on the opposite side to the substrate. There are light emitting elements with a double-sided emission structure that emits light from the side, and light emitting elements with any emission structure are suitable. It can be used.

[0202] An example of a light-emitting device using a light-emitting element as a display element is shown in FIG. The transistor 4513 is electrically connected to the transistor 4010 provided in the pixel portion 4002. The light-emitting element 4513 includes a first electrode layer 4030, an electroluminescent layer 4511, a second The electrode layer 4031 has a stacked structure, but is not limited to the structure shown. The configuration of the light emitting element 4513 can be changed as appropriate depending on the direction of light to be extracted.

[0203] The partition wall 4510 is formed using an organic insulating material or an inorganic insulating material, particularly a photosensitive resin. An opening is formed on the first electrode layer 4030 using a material, and the sidewall of the opening has a continuous curved surface. It is preferable to form the inclined surface so as to have a certain slope.

[0204] The electroluminescent layer 4511 may be composed of a single layer or a plurality of layers stacked. It doesn't matter whether it's done or not.

[0205] The second electrode layer is formed to prevent oxygen, hydrogen, moisture, carbon dioxide, and the like from entering the light-emitting element 4513. A protective film may be formed on the insulating film 4031 and the partition wall 4510. The protective film may be made of silicon nitride. A silicon nitride film, a silicon oxide film, a DLC film, etc. can be formed on the first substrate 400. The space sealed by the first substrate 4001, the second substrate 4006, and the sealing material 4005 is filled with a filler 45. 14 is provided and sealed. In this way, it is highly airtight and degassed so as not to be exposed to the outside air. Protective films with low wear (laminating films, UV-curing resin films, etc.) and covering materials It is preferable to package (enclose) the

[0206] Filler 4514 can be an inert gas such as nitrogen or argon, or an ultraviolet curing resin or Thermosetting resin can be used, and PVC (polyvinyl chloride), acrylic, polyimide Mido, epoxy resin, silicone resin, PVB (Polyvinyl Butyral) or EVA (Elastomer) For example, nitrogen may be used as a filler. stomach.

[0207] If necessary, a polarizing plate or a circular polarizing plate (including an elliptical polarizing plate) may be provided on the light-emitting surface of the light-emitting element. Optical films such as retardation plates (λ / 4 plates, λ / 2 plates) and color filters may be provided as appropriate. In addition, an anti-reflection film may be provided on the polarizing plate or the circular polarizing plate. Anti-glare treatment can be applied to diffuse reflected light and reduce glare.

[0208] It is also possible to provide electronic paper that drives electronic ink as a display device. Electronic paper is also called an electrophoretic display (electrophoretic display), and is a paper It is possible to make it as easy to read as a digital camera, consume less power than other display devices, and have a thinner and lighter form factor. This has the advantage that

[0209] The electrophoretic display device may have various forms, but it has a structure in which first particles having a positive charge and The microcapsules containing the negatively charged second particles are mixed in a solvent or solute. By applying an electric field to the microcapsules, the particles in the microcapsules are dispersed. The particles are moved in opposite directions to each other, and only the color of the particles that have gathered on one side is displayed. The first particles or the second particles contain a dye and do not move in the absence of an electric field. In addition, the color of the first particles and the color of the second particles are different (including colorless).

[0210] In this way, the electrophoretic display device moves materials with high dielectric constants to areas with high electric fields, so-called This is a display that utilizes the dielectrophoretic effect.

[0211] A dispersion of multiple microcapsules in a solvent is called electronic ink. This electronic ink can be printed on surfaces such as glass, plastic, fabric, and paper. In addition, color displays are possible by using color filters or particles containing pigments. .

[0212] The first particles and the second particles in the microcapsules may be made of a conductive material, an insulating material, Semiconductor materials, magnetic materials, liquid crystal materials, ferroelectric materials, electroluminescent materials, A material selected from magnetochromic materials, magnetophoretic materials, or a composite material thereof Just use it.

[0213] In addition, a display device using a twist ball display method can also be applied as electronic paper. The twist ball display method uses spherical particles painted in black and white as the display element. The first electrode layer and the second electrode layer are disposed between the first electrode layer and the second electrode layer. A display is produced by generating a potential difference in the electrode layer and controlling the orientation of the spherical particles. It is the law.

[0214] FIG. 13 shows an active matrix electronic paper as one mode of a semiconductor device. The electronic paper shown in 13 is an example of a display device that uses the twisting ball display method.

[0215] A first electrode layer 4030 connected to the transistor 4010 and a second electrode layer 4031 provided on the second substrate 4006 Between the second electrode layer 4031 and the black area 4615a and the white area 4615b, A spherical particle 4613 is provided, which includes a cavity 4612 that is filled with liquid. The spherical particles 4613 are filled with a filler 4614 such as a resin. The second electrode layer 4031 corresponds to a common electrode (counter electrode). and electrically connected to each other.

[0216] 11 to 13, the first substrate 4001 and the second substrate 4006 are In addition to a glass substrate, a flexible substrate can also be used. For example, a transparent plastic substrate can be used. As for plastic, FRP (Fibre Plastic) can be used. Ass-Reinforced Plastics) plate, PVF (Polyvinyl Fluoride) A film, a polyester film or an acrylic resin film can be used. In addition, aluminum foil is sandwiched between PVF film or polyester film. A port can also be used.

[0217] The insulating film 4020 is made of silicon oxide, silicon oxynitride, hafnium oxide, or aluminum oxide. The insulating film 40 can be formed using a material containing an inorganic insulating material such as gallium oxide. The method for producing 20 is not particularly limited, and may be, for example, a plasma CVD method or a sputtering method. It can be produced using a film-forming method. In addition, it is difficult for hydrogen and water to be mixed in. In this case, the sputtering method is preferable.

[0218] The insulating film 4024 is formed by sputtering a silicon nitride film, a silicon nitride oxide film, an oxidized silicon film, or a silicon nitride film. aluminum film, aluminum nitride film, aluminum oxynitride film, or aluminum oxynitride film The protective film may be formed of a single layer or a stack of layers of a protective film, and functions as a protective film for the transistor.

[0219] The insulating layer 4021 can be formed using an inorganic insulating material or an organic insulating material. , acrylic resin, polyimide, benzocyclobutene resin, polyamide, epoxy resin, etc. When the above-mentioned organic insulating material having heat resistance is used, it is suitable as a planarizing insulating film. In addition to organic insulating materials, low-k materials, siloxane resins, PSG (polysiloxane group) BPSG (Boron Phosphide Glass), etc. can be used. The insulating layer may be formed by stacking a plurality of insulating films made of the material.

[0220] The method for forming the insulating layer 4021 is not particularly limited, and may be a sputtering method, a sintering method, or the like, depending on the material. Pin coating method, dipping method, spray coating, droplet ejection method (inkjet method, screen printing, offset printing, etc.), roll coating, curtain coating, knife coating Coatings, etc. can be used.

[0221] A display device transmits light from a light source or a display element to display an image. All thin films such as the substrate, insulating film, and conductive film provided in the part are resistant to light in the visible light wavelength range. It shall be translucent.

[0222] A first electrode layer and a second electrode layer (a pixel electrode layer, a common electrode layer, a pair of electrodes) that apply a voltage to the display element In the case of a light-emitting diode (also called a counter electrode layer), the direction of the light to be extracted, the location of the electrode layer, and The light transmission property or reflectivity can be selected depending on the pattern structure of the electrode layer.

[0223] The first electrode layer 4030 and the second electrode layer 4031 are made of an indium oxide containing tungsten oxide. oxide, indium zinc oxide with tungsten oxide, indium oxide with titanium oxide Indium tin oxide (hereinafter referred to as ITO) ), indium zinc oxide, indium tin oxide with silicon oxide added, etc. A conductive material that can be used can be used.

[0224] The first electrode layer 4030 and the second electrode layer 4031 are made of tungsten (W) and molybdenum. (Mo), zirconium (Zr), hafnium (Hf), vanadium (V), niobium (N b), Tantalum (Ta), Chromium (Cr), Cobalt (Co), Nickel (Ni), Titanium Metals such as titanium (Ti), platinum (Pt), aluminum (Al), copper (Cu), and silver (Ag), Alternatively, it may be formed using one or more of the alloys or nitrides thereof. .

[0225] In addition, since transistors are easily damaged by static electricity, a protection circuit for protecting the drive circuit is required. It is preferable that the protection circuit is configured using a non-linear element.

[0226] As described above, by applying the shift register shown in any one of the first and second embodiments, Therefore, when a specific color (for example, all black display or all white display) is displayed, the same signal is applied to each of the plurality of scanning signal lines. It is possible to output display scanning signals (ON signals or OFF signals) all at once at the same timing. Therefore, the data writing time can be shortened. Therefore, the power consumption of the scanning signal line driver during the period can be reduced. In addition, high-speed operation can reduce the load on the drive circuit section. This prevents screen flickering.

[0227] This embodiment mode can be implemented by being appropriately combined with the configurations described in other embodiments. is.

[0228] (Sixth embodiment) The liquid crystal display device disclosed in this specification can be applied to various electronic devices (including gaming machines). The electronic device can be, for example, a television device (television or television (also called digital receivers), computer monitors, digital cameras, digital video cameras digital photo frames, mobile phones (also called mobile phones or mobile phone devices), Examples include large game machines such as small game machines, mobile information terminals, sound reproduction devices, and pachinko machines. can be.

[0229] FIG. 15A shows an example of a television device. The television device 9600 includes: A display unit 9603 is incorporated in a housing 9601. The display unit 9603 displays images. In this case, the housing 9601 is supported by a stand 9605. The figure shows the configuration.

[0230] The television device 9600 can be operated using an operation switch on the housing 9601 or a separate remote control. This can be done by the remote control operation device 9610. The channel and volume can be controlled by the 9609, and the information displayed on the display 9603 is In addition, the remote control operation device 9610 can operate the video. A display portion 9607 for displaying information output from 9610 may be provided.

[0231] The television device 9600 is configured to include a receiver, a modem, and the like. It can receive more general TV broadcasts and can also receive them via wired or wireless modems. By connecting to a communication network, it can be one-way (sender to receiver) or two-way. It is also possible to communicate information (between a sender and a receiver, or between receivers).

[0232] FIG. 15B shows an example of a digital photo frame. The frame 9700 has a display unit 9703 built into a housing 9701. 3 is capable of displaying various images, for example, images taken with a digital camera. By displaying data, it can function like a regular photo frame.

[0233] The Digital Photo Frame 9700 has an operation panel, external connection terminals (USB terminal, US A terminal that can be connected to various cables such as B cable, etc., and a recording medium insertion section. These components may be incorporated on the same surface as the display unit, but they may be incorporated on the side or back. It is desirable to have it because it improves the design. For example, the Digital Photo Frame 9700 Insert a memory that stores image data taken with a digital camera into the recording medium insertion section of the Image data can be captured and displayed on the display unit 9703. do.

[0234] The digital photo frame 9700 may also be configured to be capable of transmitting and receiving information wirelessly. It is also possible to configure the device so that desired image data can be wirelessly acquired and displayed.

[0235] FIG. 16(A) shows a portable gaming machine, which is composed of two cabinets, a cabinet 9881 and a cabinet 9891. The housing 9881 is connected to a connector 9893 so as to be openable and closable. A display unit 9883 is incorporated in the housing 9891. The portable gaming machine shown in FIG. 16(A) also includes a speaker unit 9884, a recording medium insertion unit 988, 6, LED lamp 9890, input means (operation key 9885, connection terminal 9887, sensor 9 888 (force, displacement, position, velocity, acceleration, angular velocity, rotation speed, distance, light, liquid, magnetism, temperature, Chemical substances, sound, time, hardness, electric field, current, voltage, power, radiation, flow rate, humidity, gradient, vibration (including the function of measuring movement, smell or infrared rays), equipped with microphone 9889, etc. Of course, the configuration of the portable gaming machine is not limited to the above, and at least Any configuration may be used as long as it includes the disclosed liquid crystal display device, and other auxiliary equipment may be provided as appropriate. The portable gaming machine shown in FIG. 16(A) can be The function of reading out programs or data and displaying them on the display, and wireless communication with other portable gaming machines The portable gaming machine shown in FIG. 16(A) has the function of sharing information by performing the above. The functions are not limited to these, and various functions can be provided.

[0236] FIG. 16(B) shows an example of a slot machine, which is a large gaming machine. 900 has a display unit 9903 built into a housing 9901. 900 also includes other operating means such as a start lever and stop switch, a coin slot, Of course, the configuration of the slot machine 9900 is not limited to the above. However, the present invention is not limited to this, and any configuration may be used as long as it includes at least the liquid crystal display device disclosed in this specification. Other auxiliary equipment may be provided as appropriate.

[0237] 17A shows an example of a mobile phone. The mobile phone 1000 has a housing 1001. In addition to the display unit 1002 incorporated in the It is equipped with a speaker 1005, a microphone 1006, etc.

[0238] The mobile phone 1000 shown in FIG. 17A displays information by touching the display unit 1002 with a finger or the like. You can also make calls, write emails, and perform other operations. This can be done by touching the display portion 1002 with a finger or the like.

[0239] The screen of the display unit 1002 has three main modes. The first is a display mode that mainly displays images. The first mode is a display mode, and the second mode is an input mode that mainly inputs information such as characters. This is a display + input mode that combines two modes: display mode and input mode.

[0240] For example, when making a call or creating an email, the display unit 1002 is used to input characters. This is the main character input mode, and you can input characters displayed on the screen. It is preferable to display a keyboard or number buttons on most of the screen of the display unit 1002. Desirable.

[0241] In addition, the mobile phone 1000 may include a sensor for detecting tilt, such as a gyro or an acceleration sensor. By providing a detection device having the above configuration, the orientation of the mobile phone 1000 (portrait or landscape) can be determined and the display The screen display of the display unit 1002 can be automatically switched.

[0242] The screen mode can be switched by touching the display unit 1002 or by operating the housing 1001. This is done by operating the button 1003. Also, depending on the type of image displayed on the display unit 1002, For example, if the image signal to be displayed on the display unit is a video signal, If it is data, the display mode is switched to, and if it is text data, the input mode is switched to.

[0243] In the input mode, the optical sensor of the display unit 1002 detects a signal and displays it. If there is no input by touch operation of the part 1002 for a certain period of time, the screen mode is changed to the input mode. Alternatively, the display mode may be switched from the normal mode to the display mode.

[0244] The display unit 1002 can also function as an image sensor. By touching the palm or fingers to 02, palm prints, fingerprints, etc. are captured to authenticate the user. In addition, the display unit 1002 may be provided with a backlight that emits near-infrared light or a display device that emits near-infrared light. By using a light-emitting sensing light source, it is also possible to capture images of finger veins, palm veins, etc.

[0245] FIG. 17B is also an example of a mobile phone. The mobile phone in FIG. 17B has a housing 9411. A display device 9410 including a display portion 9412 and an operation button 9413 is mounted on a housing 9401. An operation button 9402, an external input terminal 9403, a microphone 9404, a speaker 9405, and The communication device 9400 includes a light emitting unit 9406 that emits light when an incoming call is received, and has a display function. The display device 9410 can be attached to and detached from the communication device 9400 having a telephone function in two directions as shown by the arrows. Therefore, the display device 9410 and the communication device 9400 can be attached to each other with their short axes facing each other. The display device 9410 and the communication device 9400 can be attached to each other with their long axes facing each other. When only the function is required, the display device 9410 is removed from the communication device 9400. The communication device 9400 and the display device 9410 can be used in wireless communication. Images or input information can be sent and received via wired or wireless communication, and each can be recharged with a battery. Having Terry. [Explanation of symbols]

[0246] 10 Pulse output circuit 11 Signal line 12 Signal line 13 Signal line 14 Signal line 21 Input terminal 22 Input terminal 23 Input terminal 24 input terminals 25 Output terminal 26 Input terminals 27 Output terminal 31 Power line 32 Power line 33 Power line 34 Power line 35 Power line 36 Power line 37 Power line 38 Power line 51 period 52 period 53 period 54 period 55 period 60 Control Unit 70 Output section 100 transistors 101 Transistor 102 transistor 103 Transistor 104 transistors 105 transistors 106 transistors 107 Transistor 108 transistors 109 Transistor 110 Transistor 111 Transistor 400 boards 401 Gate electrode layer 402 Gate insulating layer 403 Oxide semiconductor layer 407 Insulating Film 409 Protective Insulation Layer 410 Transistor 420 transistors 427 Insulating Layer 430 transistors 437 Insulating Layer 440 transistors 505 board 506 Protective insulation layer 507 Gate insulating layer 510 Transistor 511 Gate electrode layer 516 Insulating Layer 530 Oxide semiconductor film 531 Oxide semiconductor layer 1000 mobile phones 1001 Case 1002 Display section 1003 Operation button 1004 External connection port 1005 Speaker 1006 Mike 4001 board 4002 Pixel section 4003 Signal line driver circuit 4004 Scanning line driver circuit 4005 Sealing material 4006 board 4008 Liquid crystal layer 4010 transistor 4011 transistor 4013 Liquid crystal element 4015 Connection terminal electrode 4016 Terminal electrode 4018 FPC 4019 Anisotropic conductive film 4020 insulating film 4021 Insulation layer 4023 Insulating film 4024 insulating film 4030 Electrode layer 4031 Electrode layer 4032 Insulating film 405a Source electrode layer 405b Drain electrode layer 436a Wiring layer 436b wiring layer 4510 Bulkhead 4511 Electroluminescent layer 4513 Light-emitting element 4514 Filling material 4612 Cavity 4613 Spherical particles 4614 Filling material 4908 Liquid crystal layer 4930 Electrode layer 4931 Electrode layer 4951 Retardation plate 4952 Polarizing plate 515a Source electrode layer 515b Drain electrode layer 9400 Communication Equipment 9401 Housing 9402 Operation button 9403 External input terminal 9404 Microphone 9405 Speaker 9406 Light-emitting part 9410 Display device 9411 Housing 9412 Display section 9413 Operation button 9600 Television Equipment 9601 Housing 9603 Display section 9605 Stand 9607 Display section 9609 Operation Key 9610 Remote Controlled Machine 9700 Digital Photo Frame 9701 Housing 9703 Display section 9881 Case 9882 Display section 9883 Display section 9884 Speaker section 9885 Input means (operation keys 9886 Recording medium insertion section 9887 Connection terminal 9888 Sensor 9889 Microphone 9890 LED Lamp 9891 Case 9893 Connection section 9900 slot machine 9901 Housing 9903 Display Department 4018a FPC 4018b FPC 4615a Black Territory 4615b White Field

Claims

1. The first to sixth transistors are included, one of the source and the drain of the first transistor is always electrically connected to a clock signal line; the other of the source and the drain of the first transistor is always electrically connected to an output signal line; one of the source and the drain of the second transistor is always electrically connected to the output signal line; the other of the source and the drain of the second transistor is always electrically connected to a first power supply line; one of the source and the drain of the third transistor is always electrically connected to the gate of the second transistor; a first potential is input to the other of the source and the drain of the third transistor; the gate of the third transistor is always electrically connected to the first signal line; one of the source and the drain of the fourth transistor is always electrically connected to the second power supply line; a gate of the fourth transistor is always electrically connected to a gate of the second transistor; one of the source and the drain of the fifth transistor is always electrically connected to the gate of the second transistor; the gate of the fifth transistor is always electrically connected to the second signal line; one of the source and the drain of the sixth transistor is always electrically connected to the first wiring; a gate of the sixth transistor is always electrically connected to the second signal line; The first potential is input to the first wiring, when the second power supply line is in a conductive state with the gate of the first transistor via at least a channel formation region of the fourth transistor, a potential of the second power supply line is input to the gate of the first transistor via at least a channel formation region of the fourth transistor; when the other of the source or the drain of the fifth transistor is in a state of conduction with the gate of the second transistor at least via a channel formation region of the fifth transistor, a potential of the other of the source or the drain of the fifth transistor is input to the gate of the second transistor at least via the channel formation region of the fifth transistor; When the first wiring is in a conductive state with the gate of the first transistor through at least a channel formation region of the sixth transistor, the first potential is input to the gate of the first transistor through at least a channel formation region of the sixth transistor.

2. A scanning line driver circuit and a pixel portion are included. the scanning line driving circuit and the pixel portion are provided on the same substrate, the scanning line driving circuit has a pulse output circuit, the pulse output circuit has first to sixth transistors, one of the source and the drain of the first transistor is always electrically connected to a clock signal line; the other of the source and the drain of the first transistor is always electrically connected to the pixel portion via an output signal line; one of the source and the drain of the second transistor is always electrically connected to the pixel portion via the output signal line; the other of the source and the drain of the second transistor is always electrically connected to a first power supply line; one of the source and the drain of the third transistor is always electrically connected to the gate of the second transistor; a first potential is input to the other of the source and the drain of the third transistor; the gate of the third transistor is always electrically connected to the first signal line; one of the source and the drain of the fourth transistor is always electrically connected to the second power supply line; a gate of the fourth transistor is always electrically connected to a gate of the second transistor; one of the source and the drain of the fifth transistor is always electrically connected to the gate of the second transistor; the gate of the fifth transistor is always electrically connected to the second signal line; one of the source and the drain of the sixth transistor is always electrically connected to the first wiring; a gate of the sixth transistor is always electrically connected to the second signal line; The first potential is input to the first wiring, when the second power supply line is in a conductive state with the gate of the first transistor via at least a channel formation region of the fourth transistor, a potential of the second power supply line is input to the gate of the first transistor via at least a channel formation region of the fourth transistor; when the other of the source or the drain of the fifth transistor is in a state of conduction with the gate of the second transistor at least via a channel formation region of the fifth transistor, a potential of the other of the source or the drain of the fifth transistor is input to the gate of the second transistor at least via the channel formation region of the fifth transistor; A display device in which, when the first wiring is in a conductive state with the gate of the first transistor through at least a channel formation region of the sixth transistor, the first potential is input to the gate of the first transistor through at least a channel formation region of the sixth transistor.

3. In claim 2, The pixel portion is a display device having an organic EL element.

Images