Controller, magnetic tape device, and control method

Abstract

To provide a controller, a magnetic tape device, and a control method capable of reducing occurrences of failures of a motor of a magnetic tape device.SOLUTION: A controller comprises: detection means which detects an abnormal state of a processor which controls a magnetic tape device; signal output means which outputs a reset signal for resetting the processor to the processor when the abnormal state is detected; and current control means which stops supply of current to a motor of the magnetic tape device when the abnormal state is detected, and supplies the current to the motor when the processor is reset and rebooted.SELECTED DRAWING: Figure 11

Description

[Technical Field]

[0001] The present disclosure relates to a control device, a magnetic tape device, and a control method. [Background technology]

[0002] In magnetic tape drives, a processor uses firmware to control the motor that operates the mechanical mechanism that winds up the magnetic tape. If external noise (static electricity) applied to the magnetic tape drive is applied to the control card inside the magnetic tape drive through the housing, the processor may stop functioning, i.e., the firmware may go out of control. If the firmware goes out of control, the firmware will not be able to control the magnetic tape drive.

[0003] If a magnetic tape device falls into a state where it cannot be controlled by the firmware, the user must manually turn off the power to the device (re-resetting the processor) and then manually turn the power to the device on (removing the reset) in order to return the device to a state where it can be controlled by the firmware.

[0004] For example, Patent Document 1 describes a magnetic tape device that prevents the magnetic tape from breaking by setting the voltage output to the motor drive circuit to zero when a runaway of the microprocessor is detected. [Prior art documents] [Patent documents]

[0005] [Patent Document 1] Japanese Patent Application Publication No. 2-306453 Summary of the Invention [Problem to be solved by the invention]

[0006] In a magnetic tape device, if the firmware goes out of control while the accessor is operating and the device stops operating while current is still flowing through the motor (motor lock state), there is a risk of motor malfunction (for example, motor coil burnout).

[0007] The magnetic tape device described in Patent Document 1 sets the voltage output to the motor drive circuit to zero to prevent the magnetic tape from breaking. However, Patent Document 1 does not describe avoiding motor malfunctions or controlling the current output to the motor drive circuit.

[0008] An object of the present disclosure is to provide a control device, a magnetic tape device, and a control method that solve the above-mentioned problems. [Means for solving the problem]

[0009] A control device according to one aspect of the present disclosure includes a detection means for detecting an abnormal state of a processor that controls a magnetic tape device, a signal output means for outputting a reset signal to the processor to reset the processor when the abnormal state is detected, and a current control means for stopping the supply of current to the motor of the magnetic tape device when the abnormal state is detected, and for supplying the current to the motor when the processor is reset and restarted.

[0010] A magnetic tape device according to one aspect of the present disclosure includes a magnetic tape, a tape drive that records data on the magnetic tape and reads data from the magnetic tape, a motor that drives the tape drive, a processor that controls the motor, a detection means that detects an abnormal state of the processor, a signal output means that outputs a reset signal to the processor to reset the processor when the abnormal state is detected, and a current control means that stops the supply of current to the motor when the abnormal state is detected, and supplies the current to the motor when the processor is reset and restarted.

[0011] A control method according to one aspect of the present disclosure detects an abnormal state of a processor that controls a magnetic tape device, outputs a reset signal to the processor to reset the processor when the abnormal state is detected, stops supplying current to a motor of the magnetic tape device when the abnormal state is detected, and supplies the current to the motor when the processor is reset and restarted. [Effects of the Invention]

[0012] According to the above aspect, it is possible to reduce the occurrence of malfunctions in the motor of the magnetic tape device when the processor is in an abnormal state. [Brief explanation of the drawings]

[0013] [Figure 1] 1 is a hardware configuration diagram of a magnetic tape device according to the present disclosure. [Figure 2] FIG. 2 is a hardware configuration diagram of a control device according to the present disclosure. [Figure 3] FIG. 2 is a hardware configuration diagram of a resistance switching circuit according to the present disclosure. [Figure 4] 1 is a hardware configuration diagram of a CPLD (Complex Programmable Logic Device) according to the present disclosure. [Figure 5] FIG. 2 is a hardware configuration diagram of a motor current control circuit according to the present disclosure. [Figure 6] 10 is a flowchart of a monitoring process according to the present disclosure. [Figure 7] 3 is a timing chart of each signal according to the present disclosure. [Figure 8] 3 is a timing chart of each signal according to the present disclosure. [Figure 9] 10 is a flowchart of a hardware recovery process according to the present disclosure. [Figure 10] 10 is a flowchart of a firmware restoration process according to the present disclosure. [Figure 11] FIG. 2 is a hardware configuration diagram of a control device according to the present disclosure. DETAILED DESCRIPTION OF THE INVENTION

[0014] Each embodiment will be described below with reference to the drawings. In all drawings, the same or corresponding components are designated by the same reference numerals, and common descriptions will be omitted.

[0015] First Embodiment An embodiment of the present disclosure will be described below with reference to the drawings. Fig. 1 shows the hardware configuration of a magnetic tape device 100 according to this embodiment.

[0016] The magnetic tape device 100 comprises a control device 101, a tape drive 102, and a magnetic tape 103. The tape drive 102 has a mechanical mechanism and records data on the magnetic tape 103 and reads data from the magnetic tape 103. The control device 101 is mounted on a control card for the magnetic tape device and controls the operation of the tape drive 102.

[0017] 2 shows the hardware configuration of the control device 101. The control device 101 includes a watchdog timer 1, a reset IC 2, a resistor switching circuit 3, a resistor circuit 4, a reset circuit 5, an encoder pulse counter circuit 6, a response check circuit 7, a motor current control circuit 8, a motor driver circuit 9, a selection circuit 10, a motor 11, a CPU (Central Processing Unit) 12, an operation history storage circuit 13, and an encoder sensor 14.

[0018] The CPU 12 is a processor that reads and executes firmware programs from a memory (not shown in Fig. 2) to perform processing according to the firmware. A microprocessor may also perform processing according to the firmware.

[0019] The watchdog timer 1 receives a clock generated by the firmware from the CPU 12 and monitors whether there is a response. This allows the watchdog timer 1 to detect whether the CPU 12 is in a normal or abnormal state. The watchdog timer 1 sets an abnormality detection signal to the response check circuit 7 depending on whether there is a response. If there is a response, the CPU 12 is in a normal state, and the watchdog timer 1 sets the abnormality detection signal to the "High" side. If there is no response, the CPU 12 is in an abnormal state, and the watchdog timer 1 sets the abnormality detection signal to the "Low" side. The watchdog timer 1 functions as a detection means for detecting an abnormal state of the CPU 12.

[0020] The response check circuit 7 receives the abnormality detection signal from the watchdog timer 1 and outputs various signals. Specifically, the response check circuit 7 outputs a current control signal for controlling the motor current control circuit 8 to the motor current control circuit 8, and outputs a resistance control signal for controlling the resistance switching circuit 3 to the resistance switching circuit 3. The response check circuit 7 also outputs a reset generation signal to the reset circuit 5 for causing the reset circuit 5 to generate a reset signal, and outputs a level signal to the selection circuit 10 for controlling the selection circuit 10. When the abnormality detection signal output by the watchdog timer 1 goes low, the response check circuit 7 executes hardware recovery processing.

[0021] The reset circuit 5 generates a reset signal to be output to the CPU 12 in response to the reset generation signal output by the response check circuit 7. The reset circuit 5 is a one-shot pulse circuit, and the reset signal has a predetermined pulse width. The reset circuit 5 functions as a signal output means that outputs a reset signal to the CPU 12 to reset the CPU 12 when an abnormal state of the CPU 12 is detected.

[0022] The resistor switching circuit 3 switches the resistance of the resistor circuit 4 in response to the resistance control signal output from the response check circuit 7. As a result, the resistor switching circuit 3 sets the pulse width of the reset signal in response to the time constant of the element (resistor / capacitor) externally attached to the reset circuit 5.

[0023] 3 shows the hardware configuration of the resistance switching circuit 3. The resistance switching circuit 3 includes a selector circuit 31 and an analog switch 32. The selector circuit 31 controls the on / off of the analog switch 32 in response to a resistance control signal output by the response check circuit 7. The analog switch 32 is connected to the resistance circuit 4. An analog switch 32 is provided corresponding to each of the multiple resistors included in the resistance circuit 4. The resistance value of the resistance circuit 4 changes depending on whether the analog switch 32 is on or off.

[0024] Referring again to FIG. 2, reset IC2 functions as a second signal output means that outputs a second reset signal to CPU 12 to reset CPU 12 when CPU 12 is in a normal state. Selection circuit 10 switches between the reset signal from reset circuit 5 and the reset signal from reset IC2 according to the level signal output by response check circuit 7 to prevent conflict with the normal CPU reset performed by reset IC2. Selection circuit 10 functions as a switching means that inputs a reset signal to CPU 12 when it detects an abnormal state of CPU 12, and inputs the second reset signal to CPU 12 when CPU 12 is in a normal state.

[0025] The encoder pulse counter circuit 6 counts the encoder pulses output by the encoder sensor 14. The value counted by the encoder pulse counter circuit 6 represents the current position of the mechanical mechanism. The motor driver circuit 9 controls the on / off of the current supply to the motor 11 in accordance with the level signal output by the motor current control circuit 8. The motor 11 rotates in accordance with the motor drive current output by the motor driver circuit 9, and moves the mechanical mechanism of the tape drive 102.

[0026] 4 shows the hardware configuration of the CPLD 15 included in the control device 101. The CPLD 15 includes an encoder pulse counter circuit 6, a motor current control circuit 8, an operation history storage circuit 13, and an I / O port 16. The encoder pulse counter circuit 6, the motor current control circuit 8, the operation history storage circuit 13, and the I / O port 16 are connected to one another via an internal bus IB. The I / O port 16 is connected to the CPU 12 via an address bus AB and a data bus DB.

[0027] The motor current control circuit 8 controls the motor drive current that the motor driver circuit 9 outputs to the motor 11 in response to the current control signal output by the response check circuit 7 or the signal output by the CPU 12. The motor current control circuit 8 functions as a current control means that stops the supply of the motor drive current to the motor 11 when it detects an abnormal state of the CPU 12, and supplies the motor drive current to the motor 11 when the CPU 12 is reset and restarted.

[0028] The operation history storage circuit 13 is arranged in the CPLD 15 as an internal RAM (Random Access Memory). The operation history storage circuit 13 stores, as operation history, motor operation commands issued from the CPU 12 to the I / O port 16 while the magnetic tape device 100 is in operation, and a history of motor pulse settings. The operation history indicates the operating state of the motor 11. The operation history storage circuit 13 functions as storage means that outputs status information indicating the operating state of the motor 11 to the CPU 12 when the CPU 12 is reset and restarted.

[0029] 5 shows the hardware configuration of the motor current control circuit 8. The motor current control circuit 8 includes a NOR gate 81, a FET (Field Effect Transistor) 82, a NOR gate 83, a FET 84, and a multiplexer 85. The FET 82 and the FET 84 are N-channel FETs.

[0030] The NOR gate 81 has a terminal A, a terminal B, and an output terminal. The current control signal output by the response check circuit 7 is input to the terminal A of the NOR gate 81. The terminal B of the NOR gate 81 is pulled down. The output terminal of the NOR gate 81 is connected to the gate terminal of the FET 82. The drain terminal of the FET 82 is connected to the multiplexer 85. The drain terminal of the FET 82 is also connected to a power supply via a resistor. The source terminal of the FET 82 is connected to ground. The FET 82 outputs a signal corresponding to the on / off state of the FET 82 from its drain terminal to the multiplexer 85.

[0031] The NOR gate 83 has an A terminal, a B terminal, and an output terminal. A signal output by the firmware is input to the A terminal of the NOR gate 83. The B terminal of the NOR gate 83 is pulled down. The output terminal of the NOR gate 83 is connected to the gate terminal of the FET 84. The drain terminal of the FET 84 is connected to the multiplexer 85. The drain terminal of the FET 84 is also connected to a power supply via a resistor. The source terminal of the FET 84 is connected to ground. The FET 84 outputs a signal corresponding to the on / off state of the FET 84 from the drain terminal to the multiplexer 85.

[0032] The multiplexer 85 has an A terminal, a B terminal, an S terminal, and a Z terminal. A signal corresponding to the on / off state of FET 82 is input to the A terminal of the multiplexer 85. A signal corresponding to the on / off state of FET 84 is input to the B terminal of the multiplexer 85. A switching signal output by the CPU 12 is input to the S terminal of the multiplexer 85. The Z terminal of the multiplexer 85 is connected to the motor driver circuit 9. The multiplexer 85 outputs a signal corresponding to the voltage of the A terminal or the B terminal to the motor driver circuit 9 from the Z terminal.

[0033] The motor driver circuit 9 has an STB terminal, an OUT_A terminal, and an OUT_B terminal. The signal output by the multiplexer 85 is input to the STB terminal. The OUT_A terminal and the OUT_B terminal are connected to the motor 11. The motor driver circuit 9 outputs a motor drive current corresponding to the signal input to the STB terminal from the OUT_A terminal and the OUT_B terminal to the motor 11.

[0034] The motor current control circuit 8 controls the motor drive current to the motor 11 in accordance with control by hardware and control by firmware. When the CPU 12 is operating normally, the CPU 12 outputs a "High" level switching signal to the S terminal of the multiplexer 85 by the firmware. At this time, the motor current control circuit 8 controls the motor drive current to the motor 11 in accordance with control by the firmware. In accordance with the "High" level switching signal, the multiplexer 85 disables the input to the A terminal and enables the input to the B terminal.

[0035] When the signal output by the CPU 12 to the NOR gate 83 by firmware is at a "High" level, the NOR gate 83 outputs a "Low" level signal to the FET 84. At this time, the FET 84 is turned off, and a "High" level signal corresponding to the power supply voltage Vcc is input to the B terminal of the multiplexer 85. The multiplexer 85 outputs a signal corresponding to that voltage from the Z terminal to the STB terminal of the motor driver circuit 9. The motor driver circuit 9 outputs a motor drive current to the motor 11 from the OUT_A terminal and the OUT_B terminal. The motor driver of the motor 11 is turned on in response to the motor drive current. For example, when the power to the magnetic tape device 100 is turned on, or when the CPU 12 is reset and restarted in accordance with hardware control, the control device 101 performs the above operations.

[0036] When the signal output by the CPU 12 to the NOR gate 83 by firmware is at a "Low" level, the NOR gate 83 outputs a "High" level signal to the FET 84. At this time, the FET 84 is turned on, and a "Low" level signal is input to the B terminal of the multiplexer 85. The multiplexer 85 outputs a "Low" level signal from the Z terminal to the STB terminal of the motor driver circuit 9. The motor driver circuit 9 stops outputting the motor drive current to the motor 11. The motor driver for the motor 11 is turned off. For example, when the power to the magnetic tape device 100 is turned off, the control device 101 performs the above operation.

[0037] When communication between the CPU 12 and the watchdog timer 1 becomes abnormal, a "Low" level switching signal is input to the S terminal of the multiplexer 85. At this time, the motor current control circuit 8 controls the motor drive current to the motor 11 in accordance with hardware control. In accordance with the "Low" level switching signal, the multiplexer 85 disables the input to the B terminal and enables the input to the A terminal.

[0038] When communication between the CPU 12 and the watchdog timer 1 becomes abnormal, the response check circuit 7 outputs a "Low" level current control signal to the NOR gate 81. The NOR gate 81 outputs a "High" level signal to the FET 82. At this time, the FET 82 turns on, and a "Low" level signal is input to the A terminal of the multiplexer 85. The multiplexer 85 outputs a "Low" level signal from the Z terminal to the STB terminal of the motor driver circuit 9. The motor driver circuit 9 stops outputting the motor drive current to the motor 11 (cuts off the motor current). The motor driver for the motor 11 turns off.

[0039] After the motor driver is turned off, when the CPU 12 returns to a normal state, the CPU 12 uses firmware to turn on the motor driver of the motor 11. Therefore, the control device 101 does not turn on the motor driver of the motor 11 using hardware control.

[0040] The following describes in detail the operation of the control device 101. FIG.

[0041] At the start of the monitoring process, the watchdog timer 1 resets the counter value in the watchdog timer 1 to "0" (step S101). At this time, the watchdog timer 1 starts measuring the time that will be used as the basis for the determination in step S106, which will be described later.

[0042] After step S101, when the watchdog timer 1 detects a clock from the CPU 12 (step S102), it increments (counts up) the counter value by 1 (step S103). If the watchdog timer 1 does not detect a clock from the CPU 12, it does not count up, but instead executes step S106, which will be described later.

[0043] After step S103, the watchdog timer 1 checks the counter value and compares it with a preset threshold value (step S104). For example, the threshold value is 255. If the counter value reaches 255, communication between the CPU 12 and the watchdog timer 1 is normal. Therefore, the watchdog timer 1 sets the abnormality detection signal to the response check circuit 7 to the "High" side (step S105). Thereafter, the watchdog timer 1 resets the counter value to "0" (step S101) and resumes counting up the counter value.

[0044] If the counter value has not reached 255, the watchdog timer 1 checks the time being measured and determines whether a preset specified time has elapsed (step S106). If the specified time has not elapsed, the watchdog timer 1 executes step S102.

[0045] If the communication between the CPU 12 and the watchdog timer 1 is in an abnormal state, the clock from the CPU 12 is interrupted. As a result, the counter value does not reach 255 within the specified time, and the specified time passes. If the specified time has passed, the watchdog timer 1 sets the abnormality detection signal to the response check circuit 7 to the "Low" side. This starts the hardware recovery process (step S107). After the hardware recovery process starts, the watchdog timer 1 resets the counter value to "0" (step S101) and resumes counting up the counter value.

[0046] 7 and 8 show waveforms of signals related to the operation of the watchdog timer 1. Fig. 7 shows the operation of the watchdog timer 1 when the CPU 12 is in a normal state, and Fig. 8 shows the operation of the watchdog timer 1 when the CPU 12 is in an abnormal state.

[0047] When the CPU 12 is in a normal state, as shown in Fig. 7, the watchdog timer 1 counts up based on a clock generated by the CPU 12 using firmware. When the counter value reaches 255, the counter value is reset to 0, and the watchdog timer 1 starts counting up again. When the counter value is reset, the watchdog timer 1 sets the abnormality detection signal to the response check circuit 7 to a "High" level. In the example shown in Fig. 7, the initial state of the abnormality detection signal is a "High" level. Therefore, when the counter value is reset, the abnormality detection signal is maintained at a "High" level.

[0048] When the CPU 12 is in an abnormal state, the count-up operation of the watchdog timer 1 stops before the specified time has elapsed, as shown in Figure 8. When the specified time has elapsed, the watchdog timer 1 sets the abnormality detection signal to the response check circuit 7 to the "Low" level.

[0049] In the above example, the counter value threshold for determining that communication between the CPU 12 and the watchdog timer 1 is abnormal is 255. This threshold may be changeable. For example, the threshold in step S104 may be initially set to 255, and the threshold in step S104 after the CPU 12 is reset by hardware control may be set to a value smaller than 255. This enables the magnetic tape device 100 to more quickly detect an abnormality in the communication state between the CPU 12 and the watchdog timer 1, and to more quickly reset the CPU 12 and stop the supply of current to the motor 11.

[0050] 9 shows the hardware recovery process. At the start of the hardware recovery process, the response check circuit 7 outputs a current control signal for stopping the output of the motor drive current to the motor current control circuit 8. The motor current control circuit 8 outputs a signal corresponding to the current control signal to the motor driver circuit 9, thereby stopping the output of the motor drive current (step S201).

[0051] Step S201 will now be described in detail. At the start of the hardware recovery process, a "Low" level switching signal is input to the S terminal of the multiplexer 85 of the motor current control circuit 8. In accordance with the "Low" level switching signal, the multiplexer 85 disables the input to the B terminal and enables the input to the A terminal.

[0052] The response check circuit 7 outputs a "Low" level current control signal to the NOR gate 81. The NOR gate 81 outputs a "High" level signal to the FET 82. At this time, the FET 82 is turned on, and a "Low" level signal is input to the STB terminal of the motor driver circuit 9 via the multiplexer 85. The motor driver circuit 9 stops outputting the motor drive current to the motor 11, and turns off the motor driver for the motor 11.

[0053] After step S201, the response check circuit 7 disables the reset signal generated by the reset IC 2 and outputs a level signal to the selection circuit 10 to enable the reset signal generated by the reset circuit 5. The selection circuit 10 selects the reset signal generated by the reset circuit 5 (step S202).

[0054] After step S202, the response check circuit 7 outputs a resistance control signal to the resistance switching circuit 3 to initialize the resistance value of the resistance circuit 4. The resistance switching circuit 3 initializes the resistance value of the resistance circuit 4 (step S203).

[0055] After step S203, the response check circuit 7 outputs a reset generation signal to the reset circuit 5. The reset circuit 5 generates a reset signal and outputs it to the CPU 12 (step S204). The CPU 12, to which the reset signal has been input, is reset and restarts the firmware (step S205).

[0056] After the firmware is restarted, the response check circuit 7 checks the state of communication between the CPU 12 and the watchdog timer 1 based on the abnormality detection signal from the watchdog timer 1 (step S206).

[0057] The watchdog timer 1 executes the monitoring process shown in Fig. 6. The threshold value in step S104 of the monitoring process after the CPU 12 is reset may be a value smaller than 255.

[0058] When the abnormality detection signal output by the watchdog timer 1 is at a "High" level, the response check circuit 7 determines that communication between the CPU 12 and the watchdog timer 1 has returned to a normal state (step S207). The response check circuit 7 outputs a level signal to the selection circuit 10 to enable the reset signal generated by the reset IC 2 and disable the reset signal generated by the reset circuit 5. The selection circuit 10 selects the reset signal generated by the reset IC 2 (step S208). At this time, the hardware recovery process is completed, and the operation of the magnetic tape device 100 returns to normal.

[0059] On the other hand, if the abnormality detection signal remains at "Low" level even after the CPU 12 is reset in response to the reset signal generated by the reset circuit 5, the response check circuit 7 determines that the communication between the CPU 12 and the watchdog timer 1 remains abnormal (step S207). The response check circuit 7 outputs a resistance control signal to the resistor switching circuit 3 to change the resistance value of the resistor circuit 4. The resistor switching circuit 3 changes the resistance value by switching the resistance of the resistor circuit 4. This changes the pulse width of the reset signal generated by the reset circuit 5 (step S209).

[0060] For example, the resistance switching circuit 3 switches the resistance of the resistance circuit 4 so that the resistance value of the resistance circuit 4 increases, thereby increasing the pulse width of the reset signal generated by the reset circuit 5.

[0061] After the resistor switching circuit 3 changes the resistance value of the resistor circuit 4, the response check circuit 7 outputs a reset generation signal to the reset circuit 5. The reset circuit 5 generates a reset signal and outputs it to the CPU 12 (step S204). The CPU 12, which has received the reset signal generated by the reset circuit 5, is reset and restarts the firmware (step S205). The response check circuit 7 repeats the operation to change the pulse width of the reset signal until communication between the CPU 12 and the watchdog timer 1 is restored to a normal state.

[0062] After the CPU 12 is reset, the CPU 12 executes firmware restoration processing by firmware. Figure 10 shows the firmware restoration processing. The CPU 12 starts transmitting clocks to the watchdog timer 1 by firmware (step S301).

[0063] After step S301, the CPU 12 reads the operation history of the device from the operation history storage circuit 13 using firmware, and also reads the current counter value from the encoder pulse counter circuit 6 via the motor current control circuit 8. At this time, the operation history storage circuit 13 outputs the operation history to the CPU 12, and the encoder pulse counter circuit 6 outputs the current counter value to the CPU 12 via the motor current control circuit 8 (step S302).

[0064] After step S302, the CPU 12 turns on the motor driver of the motor 11 by firmware (step S303).

[0065] Step S303 will now be described in detail. At the start of the firmware restoration process, a "High" level switching signal is input to the S terminal of the multiplexer 85 of the motor current control circuit 8. In accordance with the "High" level switching signal, the multiplexer 85 disables the input to the A terminal and enables the input to the B terminal.

[0066] The CPU 12 uses firmware to output a "High" level current control signal to the NOR gate 83. The NOR gate 83 outputs a "Low" level signal to the FET 84. At this time, the FET 84 is turned off, and a "High" level signal corresponding to the power supply voltage Vcc is input to the STB terminal of the motor driver circuit 9 via the multiplexer 85. The motor driver circuit 9 outputs a motor drive current to the motor 11, turning on the motor driver of the motor 11.

[0067] After step S303, the CPU 12 continues the operation of the mechanical mechanism using the operation history read in step S302 and the current counter value through firmware. If the CPU 12 goes into an abnormal state during the operation of the mechanical mechanism and the mechanical mechanism does not move to the target position, the CPU 12 retries the operation of the mechanical mechanism through firmware (step S304). At this point, the firmware recovery process ends.

[0068] The operation of the operation history storage circuit 13 will now be described in detail. During operation of the magnetic tape device 100, the CPLD 15 stores the history of setting information (motor operation commands, motor pulse settings) output by the CPU 12 to the I / O port 16 as operation history in the operation history storage circuit 13 via the internal bus IB. When the CPU 12 is reset, the CPLD 15 holds the operation history stored in the operation history storage circuit 13.

[0069] After the firmware is restarted, the CPU 12 reads the operation history from the operation history storage circuit 13 via the I / O port 16, and also reads the current count value from the encoder pulse counter circuit 6 via the I / O port 16. Based on the operation history and the current count value, the firmware causes the CPU 12 to resume operation of the mechanical mechanism from the state immediately before the CPU 12 was reset.

[0070] In this embodiment, the control device 101 detects the state of the CPU 12 by using the watchdog timer 1, and generates a reset signal by using the reset circuit 5. Therefore, even if device control by firmware becomes impossible due to the influence of disturbance noise (static electricity), automatic recovery of device operation is possible.

[0071] Furthermore, when an abnormal state of the CPU 12 is detected, the motor current control circuit 8 controls the motor driver circuit 9 to stop the supply of current to the motor 11. Therefore, even if the CPU 12 stops operating while current is flowing through the motor 11 (motor lock state), the occurrence of malfunctions of the motor 11 (for example, burnout of the motor coil) can be reduced.

[0072] When an abnormal state of the CPU 12 is detected, the NOR gate 81 and FET 82 (first current control means) of the motor current control circuit 8 cause the motor driver circuit 9 to stop supplying the motor drive current to the motor 11. Furthermore, when the CPU 12 is reset and restarted, or when the CPU 12 is in a normal state, the NOR gate 83 and FET 84 (second current control means) of the motor current control circuit 8 cause the motor driver circuit 9 to supply the motor drive current to the motor 11. In this way, it is possible to control the motor drive current by hardware and by firmware.

[0073] When the firmware is restarted after resetting the CPU 12, the firmware does not retain the control state and position information of the mechanical mechanism. The operation history storage circuit 13 stores an operation history (state information) indicating the operation state of the motor 11, and outputs the operation history to the CPU 12 when the CPU 12 is reset in response to a reset signal from the reset circuit 5. Therefore, initialization operations including searching for the origin position and checking the mechanical operation range in the operation of the mechanical mechanism are not required, and device operation can be quickly restored.

[0074] There may be cases where the CPU 12 does not recover to a normal state after being reset and remains in an abnormal state. In such cases, the response check circuit 7 resets the CPU 12 again by causing the reset circuit 5 to generate a reset signal again. Even if the CPU 12 does not recover to a normal state after a single reset, the CPU 12 can be recovered to a normal state by repeating the reset.

[0075] When an abnormal state of CPU 12 is detected, reset circuit 5 outputs a reset signal having a first pulse width to CPU 12. When an abnormal state of CPU 12 is detected again after resetting CPU 12, reset circuit 5 outputs a reset signal having a second pulse width longer than the first pulse width to CPU 12. Even if CPU 12 does not return to a normal state by a single reset, CPU 12 can be more reliably restored to a normal state by increasing the pulse width of the reset signal and resetting CPU 12 again.

[0076] <Second embodiment> An embodiment of the present disclosure will be described below with reference to the drawings. Fig. 11 shows the hardware configuration of a control device 101a of this embodiment.

[0077] The control device 101a includes a detection means 111, a signal output means 112, and a current control means 113. The detection means 111 detects an abnormal state of the processor that controls the magnetic tape device. The signal output means 112 outputs a reset signal to the processor to reset the processor when an abnormal state is detected. The current control means 113 stops the supply of current to the motor of the magnetic tape device when an abnormal state is detected, and supplies current to the motor when the processor is reset and restarted.

[0078] The control device 101a of this embodiment can reduce the occurrence of malfunctions in the motor of the magnetic tape device when the processor is in an abnormal state.

[0079] Although the present disclosure has been described above with reference to the embodiments, the present disclosure is not limited to the above-described embodiments. Various modifications that can be understood by those skilled in the art can be made to the configuration and details of the present disclosure within the scope of the present disclosure. Furthermore, each embodiment can be combined with other embodiments as appropriate.

[0080] Some or all of the above-described embodiments can be described as, but are not limited to, the following supplementary notes.

[0081] (Appendix 1) a detection means for detecting an abnormal state of a processor that controls the magnetic tape device; signal output means for outputting a reset signal to the processor when the abnormal state is detected; a current control means for stopping the supply of current to the motor of the magnetic tape device when the abnormal state is detected, and for supplying the current to the motor when the processor is reset and restarted; Equipped with Control device.

[0082] (Appendix 2) The current control means a first current control means for stopping the supply of the current to the motor when the abnormal state is detected; a second current control means for supplying the current to the motor when the processor is reset and restarted or when the processor is in a normal state; Equipped with 10. The control device of claim 1.

[0083] (Appendix 3) a storage means for storing status information indicating an operating status of the motor and outputting the status information to the processor when the processor is reset and restarted; 10. The control device of claim 1 or 2.

[0084] (Appendix 4) If the abnormal state is detected again after the processor is reset and restarted, the signal output means outputs the reset signal to the processor again. 4. The control device of any one of claims 1 to 3.

[0085] (Appendix 5) the reset signal is a pulse signal, The signal output means outputting the reset signal having a first pulse width to the processor when the abnormal state is detected; outputting the reset signal having a second pulse width longer than the first pulse width to the processor when the abnormal state is detected again after the processor has been reset and restarted; 5. The control device according to claim 4.

[0086] (Appendix 6) second signal output means for outputting a second reset signal to the processor for resetting the processor when the processor is in a normal state; a switching means for inputting the reset signal to the processor when the abnormal state is detected, and for inputting the second reset signal to the processor when the processor is in a normal state; Equipped with 6. The control device of any one of claims 1 to 5.

[0087] (Appendix 7) The detection means Counting clocks output from the processor; If the value counted by the clock does not reach a threshold value within a specified time, the abnormal state is detected. 7. The control device of any one of claims 1 to 6.

[0088] (Appendix 8) The threshold is variable. 8. The control device according to claim 7.

[0089] (Appendix 9) Magnetic tape and a tape drive for recording data on the magnetic tape and reading data from the magnetic tape; a motor that drives the tape drive; a processor for controlling the motor; a detection means for detecting an abnormal state of the processor; signal output means for outputting a reset signal to the processor when the abnormal state is detected; a current control means for stopping the supply of current to the motor when the abnormal state is detected, and for supplying the current to the motor when the processor is reset and restarted; A magnetic tape device comprising:

[0090] (Appendix 10) The current control means a first current control means for stopping the supply of the current to the motor when the abnormal state is detected; a second current control means for supplying the current to the motor when the processor is reset and restarted or when the processor is in a normal state; Equipped with 10. A magnetic tape device as described in Appendix 9.

[0091] (Appendix 11) a storage means for storing status information indicating an operating status of the motor and outputting the status information to the processor when the processor is reset and restarted; 11. A magnetic tape device according to claim 9 or 10.

[0092] (Appendix 12) If the abnormal state is detected again after the processor is reset and restarted, the signal output means outputs the reset signal to the processor again. 12. A magnetic tape device according to any one of appendices 9 to 11.

[0093] (Appendix 13) the reset signal is a pulse signal, The signal output means outputting the reset signal having a first pulse width to the processor when the abnormal state is detected; outputting the reset signal having a second pulse width longer than the first pulse width to the processor when the abnormal state is detected again after the processor has been reset and restarted; 13. The magnetic tape device according to claim 12.

[0094] (Appendix 14) second signal output means for outputting a second reset signal to the processor for resetting the processor when the processor is in a normal state; a switching means for inputting the reset signal to the processor when the abnormal state is detected, and for inputting the second reset signal to the processor when the processor is in a normal state; Equipped with 14. A magnetic tape device according to any one of appendices 9 to 13.

[0095] (Appendix 15) The detection means Counting clocks output from the processor; If the value counted by the clock does not reach a threshold value within a specified time, the abnormal state is detected. 15. A magnetic tape device according to any one of appendices 9 to 14.

[0096] (Appendix 16) The threshold is variable. 16. The magnetic tape device of claim 15.

[0097] (Appendix 17) Detecting an abnormal state of a processor that controls a magnetic tape device, outputting a reset signal to the processor when the abnormal state is detected; When the abnormal state is detected, the supply of current to the motor of the magnetic tape device is stopped; supplying the current to the motor when the processor is reset and restarted; Control method.

[0098] (Appendix 18) When the abnormal state is detected, a first current control means stops supplying the current to the motor; When the processor is reset and restarted, or when the processor is in a normal state, the current is supplied to the motor by a second current control means. 18. The control method of claim 17.

[0099] (Appendix 19) State information indicating the operating state of the motor is stored in a storage means, and when the processor is reset and restarted, the state information is output from the storage means to the processor. 19. The control method according to claim 17 or 18.

[0100] (Appendix 20) If the abnormal state is detected again after the processor is reset and restarted, the reset signal is output to the processor again. 20. The control method of any one of appendices 17 to 19.

[0101] (Appendix 21) the reset signal is a pulse signal, outputting the reset signal having a first pulse width to the processor when the abnormal state is detected; outputting the reset signal having a second pulse width longer than the first pulse width to the processor when the abnormal state is detected again after the processor has been reset and restarted; 21. The control method of claim 20.

[0102] (Appendix 22) outputting a second reset signal to the processor for resetting the processor when the processor is in a normal state; inputting the reset signal to the processor when the abnormal state is detected, and inputting the second reset signal to the processor when the processor is in a normal state; 22. The control method of any one of appendices 18 to 21.

[0103] (Appendix 23) Counting clocks output from the processor; If the value counted by the clock does not reach a threshold value within a specified time, the abnormal state is detected. 23. The control method of any one of appendices 17 to 22.

[0104] (Appendix 24) The threshold is variable. 24. The control method of claim 23. [Explanation of symbols]

[0105] 1 Watchdog Timer 2 Reset IC 3 Resistor switching circuit 4 Resistance circuit 5 Reset Circuit 6 Encoder pulse counter circuit 7 Response check circuit 8 Motor current control circuit 9 Motor driver circuit 10 Selection circuit 11 Motor 12 CPU 13 Operation history memory circuit 14 Encoder Sensor 15 CPLD 16 I / O ports 31 Selector circuit 32 Analog Switch 81,83 NOR gate 82,84 FET 85 Multiplexer 100 Magnetic Tape Unit 101, 101a Control device 102 tape drive 103 Magnetic Tape

Claims

1. a detection means for detecting an abnormal state of a processor that controls the magnetic tape device; signal output means for outputting a reset signal to the processor when the abnormal state is detected; a current control means for stopping the supply of current to the motor of the magnetic tape device when the abnormal state is detected, and for supplying the current to the motor when the processor is reset and restarted; Equipped with Control device.

2. The current control means a first current control means for stopping the supply of the current to the motor when the abnormal state is detected; a second current control means for supplying the current to the motor when the processor is reset and restarted or when the processor is in a normal state; Equipped with The control device according to claim 1 .

3. a storage means for storing status information indicating an operating status of the motor and outputting the status information to the processor when the processor is reset and restarted; The control device according to claim 1 or 2.

4. If the abnormal state is detected again after the processor is reset and restarted, the signal output means outputs the reset signal to the processor again. The control device according to claim 1 or 2.

5. the reset signal is a pulse signal, The signal output means outputting the reset signal having a first pulse width to the processor when the abnormal state is detected; outputting the reset signal having a second pulse width longer than the first pulse width to the processor when the abnormal state is detected again after the processor has been reset and restarted; The control device according to claim 4.

6. second signal output means for outputting a second reset signal to the processor for resetting the processor when the processor is in a normal state; a switching means for inputting the reset signal to the processor when the abnormal state is detected, and for inputting the second reset signal to the processor when the processor is in a normal state; Equipped with The control device according to claim 1 or 2.

7. The detection means Counting clocks output from the processor; If the value counted by the clock does not reach a threshold value within a specified time, the abnormal state is detected. The control device according to claim 1 or 2.

8. The threshold is variable. The control device according to claim 7.

9. Magnetic tape and a tape drive for recording data on the magnetic tape and reading data from the magnetic tape; a motor that drives the tape drive; a processor for controlling the motor; a detection means for detecting an abnormal state of the processor; signal output means for outputting a reset signal to the processor when the abnormal state is detected; a current control means for stopping the supply of current to the motor when the abnormal state is detected, and for supplying the current to the motor when the processor is reset and restarted; A magnetic tape device comprising:

10. Detecting an abnormal state of a processor that controls a magnetic tape device, outputting a reset signal to the processor when the abnormal state is detected; When the abnormal state is detected, the supply of current to the motor of the magnetic tape device is stopped; supplying the current to the motor when the processor is reset and restarted; Control method.

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